if_edreg.h revision 520
1/* 2 * National Semiconductor DS8390 NIC register definitions 3 * 4 * $Id: if_edreg.h,v 2.0 93/09/29 00:37:15 davidg Exp Locker: davidg $ 5 * 6 * Modification history 7 * 8 * $Log: if_edreg.h,v $ 9 * Revision 2.0 93/09/29 00:37:15 davidg 10 * changed double buffering flag to multi buffering 11 * made changes/additions for 3c503 multi-buffering 12 * ...companion to Rev. 2.0 of 'ed' driver. 13 * 14 * Revision 1.6 93/09/28 17:20:03 davidg 15 * first cut at PIO (e.g. NE1000/2000) support 16 * 17 * Revision 1.5 93/08/25 20:38:34 davidg 18 * added define for card type WD8013WC (10BaseT) 19 * 20 * Revision 1.4 93/08/14 20:07:55 davidg 21 * fix board type definition for 8013EP 22 * 23 * Revision 1.3 93/07/20 15:25:25 davidg 24 * added config flags for forcing 8/16bit mode and disabling double 25 * xmit buffers. 26 * 27 * Revision 1.2 93/06/23 03:03:05 davidg 28 * added some additional definitions for the 83C584 bus interface 29 * chip (SMC/WD boards) 30 * 31 * Revision 1.1 93/06/23 03:01:07 davidg 32 * Initial revision 33 * 34 */ 35 36/* 37 * Page 0 register offsets 38 */ 39#define ED_P0_CR 0x00 /* Command Register */ 40 41#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 42#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 43 44#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 45#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 46 47#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 48 49#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 50#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 51 52#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 53#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 54 55#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 56#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 57 58#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 59 60#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 61#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 62 63#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 64#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 65 66#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 67 68#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 69 70#define ED_P0_RSR 0x0c /* Receive Status (read) */ 71#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 72 73#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 74#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 75 76#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 77#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 78 79#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 80#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 81 82/* 83 * Page 1 register offsets 84 */ 85#define ED_P1_CR 0x00 /* Command Register */ 86#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 87#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 88#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 89#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 90#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 91#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 92#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 93#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 94#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 95#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 96#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 97#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 98#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 99#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 100#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 101 102/* 103 * Page 2 register offsets 104 */ 105#define ED_P2_CR 0x00 /* Command Register */ 106#define ED_P2_PSTART 0x01 /* Page Start (read) */ 107#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 108#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 109#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 110#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 111#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 112#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 113#define ED_P2_ACU 0x06 /* Address Counter Upper */ 114#define ED_P2_ACL 0x07 /* Address Counter Lower */ 115#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 116#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 117#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 118#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 119 120/* 121 * Command Register (CR) definitions 122 */ 123 124/* 125 * STP: SToP. Software reset command. Takes the controller offline. No 126 * packets will be received or transmitted. Any reception or 127 * transmission in progress will continue to completion before 128 * entering reset state. To exit this state, the STP bit must 129 * reset and the STA bit must be set. The software reset has 130 * executed only when indicated by the RST bit in the ISR being 131 * set. 132 */ 133#define ED_CR_STP 0x01 134 135/* 136 * STA: STArt. This bit is used to activate the NIC after either power-up, 137 * or when the NIC has been put in reset mode by software command 138 * or error. 139 */ 140#define ED_CR_STA 0x02 141 142/* 143 * TXP: Transmit Packet. This bit must be set to indicate transmission of 144 * a packet. TXP is internally reset either after the transmission is 145 * completed or aborted. This bit should be set only after the Transmit 146 * Byte Count and Transmit Page Start register have been programmed. 147 */ 148#define ED_CR_TXP 0x04 149 150/* 151 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 152 * of the remote DMA channel. RD2 can be set to abort any remote DMA 153 * command in progress. The Remote Byte Count registers should be cleared 154 * when a remote DMA has been aborted. The Remote Start Addresses are not 155 * restored to the starting address if the remote DMA is aborted. 156 * 157 * RD2 RD1 RD0 function 158 * 0 0 0 not allowed 159 * 0 0 1 remote read 160 * 0 1 0 remote write 161 * 0 1 1 send packet 162 * 1 X X abort 163 */ 164#define ED_CR_RD0 0x08 165#define ED_CR_RD1 0x10 166#define ED_CR_RD2 0x20 167 168/* 169 * PS0, PS1: Page Select. The two bits select which register set or 'page' to 170 * access. 171 * 172 * PS1 PS0 page 173 * 0 0 0 174 * 0 1 1 175 * 1 0 2 176 * 1 1 reserved 177 */ 178#define ED_CR_PS0 0x40 179#define ED_CR_PS1 0x80 180/* bit encoded aliases */ 181#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 182#define ED_CR_PAGE_1 0x40 183#define ED_CR_PAGE_2 0x80 184 185/* 186 * Interrupt Status Register (ISR) definitions 187 */ 188 189/* 190 * PRX: Packet Received. Indicates packet received with no errors. 191 */ 192#define ED_ISR_PRX 0x01 193 194/* 195 * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 196 */ 197#define ED_ISR_PTX 0x02 198 199/* 200 * RXE: Receive Error. Indicates that a packet was received with one or more 201 * the following errors: CRC error, frame alignment error, FIFO overrun, 202 * missed packet. 203 */ 204#define ED_ISR_RXE 0x04 205 206/* 207 * TXE: Transmission Error. Indicates that an attempt to transmit a packet 208 * resulted in one or more of the following errors: excessive 209 * collisions, FIFO underrun. 210 */ 211#define ED_ISR_TXE 0x08 212 213/* 214 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 215 * would exceed (has exceeded?) the boundry pointer, resulting in data 216 * that was previously received and not yet read from the buffer to be 217 * overwritten. 218 */ 219#define ED_ISR_OVW 0x10 220 221/* 222 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 223 * Counters has been set. 224 */ 225#define ED_ISR_CNT 0x20 226 227/* 228 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 229 */ 230#define ED_ISR_RDC 0x40 231 232/* 233 * RST: Reset status. Set when the NIC enters the reset state and cleared when a 234 * Start Command is issued to the CR. This bit is also set when a receive 235 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 236 * packets have been removed from the ring. This is a read-only bit. 237 */ 238#define ED_ISR_RST 0x80 239 240/* 241 * Interrupt Mask Register (IMR) definitions 242 */ 243 244/* 245 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 246 * an interrupt. 247 */ 248#define ED_IMR_PRXE 0x01 249 250/* 251 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 252 * a packet transmission completes. 253 */ 254#define ED_IMR_PTXE 0x02 255 256/* 257 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 258 * packet is received with an error. 259 */ 260#define ED_IMR_RXEE 0x04 261 262/* 263 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 264 * a transmission results in an error. 265 */ 266#define ED_IMR_TXEE 0x08 267 268/* 269 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 270 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded. 271 */ 272#define ED_IMR_OVWE 0x10 273 274/* 275 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 276 * the MSB of one or more of the Network Statistics counters has been set. 277 */ 278#define ED_IMR_CNTE 0x20 279 280/* 281 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 282 * when a remote DMA transfer has completed. 283 */ 284#define ED_IMR_RDCE 0x40 285 286/* 287 * bit 7 is unused/reserved 288 */ 289 290/* 291 * Data Configuration Register (DCR) definitions 292 */ 293 294/* 295 * WTS: Word Transfer Select. WTS establishes byte or word transfers for 296 * both remote and local DMA transfers 297 */ 298#define ED_DCR_WTS 0x01 299 300/* 301 * BOS: Byte Order Select. BOS sets the byte order for the host. 302 * Should be 0 for 80x86, and 1 for 68000 series processors 303 */ 304#define ED_DCR_BOS 0x02 305 306/* 307 * LAS: Long Address Select. When LAS is 1, the contents of the remote 308 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 309 */ 310#define ED_DCR_LAS 0x04 311 312/* 313 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 314 * of the TCR must also be programmed for loopback operation. 315 * When 1, normal operation is selected. 316 */ 317#define ED_DCR_LS 0x08 318 319/* 320 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 321 * under program control. When 1, remote DMA is automatically initiated 322 * and the boundry pointer is automatically updated 323 */ 324#define ED_DCR_AR 0x10 325 326/* 327 * FT0, FT1: Fifo Threshold select. 328 * FT1 FT0 Word-width Byte-width 329 * 0 0 1 word 2 bytes 330 * 0 1 2 words 4 bytes 331 * 1 0 4 words 8 bytes 332 * 1 1 8 words 12 bytes 333 * 334 * During transmission, the FIFO threshold indicates the number of bytes 335 * or words that the FIFO has filled from the local DMA before BREQ is 336 * asserted. The transmission threshold is 16 bytes minus the receiver 337 * threshold. 338 */ 339#define ED_DCR_FT0 0x20 340#define ED_DCR_FT1 0x40 341 342/* 343 * bit 7 (0x80) is unused/reserved 344 */ 345 346/* 347 * Transmit Configuration Register (TCR) definitions 348 */ 349 350/* 351 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 352 * is not appended by the transmitter. 353 */ 354#define ED_TCR_CRC 0x01 355 356/* 357 * LB0, LB1: Loopback control. These two bits set the type of loopback that is 358 * to be performed. 359 * 360 * LB1 LB0 mode 361 * 0 0 0 - normal operation (DCR_LS = 0) 362 * 0 1 1 - internal loopback (DCR_LS = 0) 363 * 1 0 2 - external loopback (DCR_LS = 1) 364 * 1 1 3 - external loopback (DCR_LS = 0) 365 */ 366#define ED_TCR_LB0 0x02 367#define ED_TCR_LB1 0x04 368 369/* 370 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 371 * another station to disable the NIC's transmitter by transmitting to 372 * a multicast address hashing to bit 62. Reception of a multicast address 373 * hashing to bit 63 enables the transmitter. 374 */ 375#define ED_TCR_ATD 0x08 376 377/* 378 * OFST: Collision Offset enable. This bit when set modifies the backoff 379 * algorithm to allow prioritization of nodes. 380 */ 381#define ED_TCR_OFST 0x10 382 383/* 384 * bits 5, 6, and 7 are unused/reserved 385 */ 386 387/* 388 * Transmit Status Register (TSR) definitions 389 */ 390 391/* 392 * PTX: Packet Transmitted. Indicates successful transmission of packet. 393 */ 394#define ED_TSR_PTX 0x01 395 396/* 397 * bit 1 (0x02) is unused/reserved 398 */ 399 400/* 401 * COL: Transmit Collided. Indicates that the transmission collided at least 402 * once with another station on the network. 403 */ 404#define ED_TSR_COL 0x04 405 406/* 407 * ABT: Transmit aborted. Indicates that the transmission was aborted due to 408 * excessive collisions. 409 */ 410#define ED_TSR_ABT 0x08 411 412/* 413 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 414 * transmission of the packet. (Transmission is not aborted because 415 * of a loss of carrier) 416 */ 417#define ED_TSR_CRS 0x10 418 419/* 420 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 421 * transmission memory before the FIFO emptied. Transmission of the 422 * packet was aborted. 423 */ 424#define ED_TSR_FU 0x20 425 426/* 427 * CDH: CD Heartbeat. Indicates that the collision detection circuitry 428 * isn't working correctly during a collision heartbeat test. 429 */ 430#define ED_TSR_CDH 0x40 431 432/* 433 * OWC: Out of Window Collision: Indicates that a collision occurred after 434 * a slot time (51.2us). The transmission is rescheduled just as in 435 * normal collisions. 436 */ 437#define ED_TSR_OWC 0x80 438 439/* 440 * Receiver Configuration Register (RCR) definitions 441 */ 442 443/* 444 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 445 * packets with CRC and frame errors are not discarded. 446 */ 447#define ED_RCR_SEP 0x01 448 449/* 450 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 451 * If set to 1, packets with less than 64 byte are not discarded. 452 */ 453#define ED_RCR_AR 0x02 454 455/* 456 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 457 * accepted. 458 */ 459#define ED_RCR_AB 0x04 460 461/* 462 * AM: Accept Multicast. If set, packets sent to a multicast address are checked 463 * for a match in the hashing array. If clear, multicast packets are ignored. 464 */ 465#define ED_RCR_AM 0x08 466 467/* 468 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 469 * accepted. If clear, a physical destination address must match this 470 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 471 * must also be set. In addition, the multicast hashing array must be set 472 * to all 1's so that all multicast addresses are accepted. 473 */ 474#define ED_RCR_PRO 0x10 475 476/* 477 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 478 * but are not stored in the ring-buffer. If clear, packets are stored (normal 479 * operation). 480 */ 481#define ED_RCR_MON 0x20 482 483/* 484 * bits 6 and 7 are unused/reserved. 485 */ 486 487/* 488 * Receiver Status Register (RSR) definitions 489 */ 490 491/* 492 * PRX: Packet Received without error. 493 */ 494#define ED_RSR_PRX 0x01 495 496/* 497 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 498 * alignment errors. 499 */ 500#define ED_RSR_CRC 0x02 501 502/* 503 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 504 * a byte boundry and the CRC did not match at the last byte boundry. 505 */ 506#define ED_RSR_FAE 0x04 507 508/* 509 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 510 * causing it to overrun. Reception of the packet is aborted. 511 */ 512#define ED_RSR_FO 0x08 513 514/* 515 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 516 * the ring-buffer because of insufficient buffer space (exceeding the 517 * boundry pointer), or because the transfer to the ring-buffer was inhibited 518 * by RCR_MON - monitor mode. 519 */ 520#define ED_RSR_MPA 0x10 521 522/* 523 * PHY: Physical address. If 0, the packet received was sent to a physical address. 524 * If 1, the packet was accepted because of a multicast/broadcast address 525 * match. 526 */ 527#define ED_RSR_PHY 0x20 528 529/* 530 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor 531 * mode. Cleared when the receiver exits monitor mode. 532 */ 533#define ED_RSR_DIS 0x40 534 535/* 536 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 537 * are active, and the transceiver has set the CD line as a result of the 538 * jabber. 539 */ 540#define ED_RSR_DFR 0x80 541 542/* 543 * receive ring discriptor 544 * 545 * The National Semiconductor DS8390 Network interface controller uses 546 * the following receive ring headers. The way this works is that the 547 * memory on the interface card is chopped up into 256 bytes blocks. 548 * A contiguous portion of those blocks are marked for receive packets 549 * by setting start and end block #'s in the NIC. For each packet that 550 * is put into the receive ring, one of these headers (4 bytes each) is 551 * tacked onto the front. 552 */ 553struct ed_ring { 554 struct edr_status { /* received packet status */ 555 u_char rs_prx:1, /* packet received intack */ 556 rs_crc:1, /* crc error */ 557 rs_fae:1, /* frame alignment error */ 558 rs_fo:1, /* fifo overrun */ 559 rs_mpa:1, /* packet received intack */ 560 rs_phy:1, /* packet received intack */ 561 rs_dis:1, /* packet received intack */ 562 rs_dfr:1; /* packet received intack */ 563 } ed_rcv_status; /* received packet status */ 564 u_char next_packet; /* pointer to next packet */ 565 u_short count; /* bytes in packet (length + 4) */ 566}; 567 568/* 569 * Common constants 570 */ 571#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 572#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 573 574/* 575 * Vendor types 576 */ 577#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 578#define ED_VENDOR_3COM 0x01 /* 3Com */ 579#define ED_VENDOR_NOVELL 0x02 /* Novell */ 580 581/* 582 * Compile-time config flags 583 */ 584/* 585 * this sets the default for enabling/disablng the tranceiver 586 */ 587#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 588 589/* 590 * This forces the board to be used in 8/16bit mode even if it 591 * autoconfigs differently 592 */ 593#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 594#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 595 596/* 597 * This disables the use of double transmit buffers. 598 */ 599#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 600 601/* 602 * This forces all operations with the NIC memory to use Programmed 603 * I/O (i.e. not via shared memory) 604 */ 605#define ED_FLAGS_FORCE_PIO 0x0010 606 607/* 608 * Definitions for Western digital/SMC WD80x3 series ASIC 609 */ 610/* 611 * Memory Select Register (MSR) 612 */ 613#define ED_WD_MSR 0 614 615#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 616#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 617#define ED_WD_MSR_RST 0x80 /* Reset board */ 618 619/* 620 * Interface Configuration Register (ICR) 621 */ 622#define ED_WD_ICR 1 623 624#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 625#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 626#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 627#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 628#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 629#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 630#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 631#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 632 633/* 634 * IO Address Register (IAR) 635 */ 636#define ED_WD_IAR 2 637 638/* 639 * EEROM Address Register 640 */ 641#define ED_WD_EAR 3 642 643/* 644 * Interrupt Request Register (IRR) 645 */ 646#define ED_WD_IRR 4 647 648#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 649#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 650#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 651#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 652#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 653 654/* 655 * The three bit of the encoded IRQ are decoded as follows: 656 * 657 * IR2 IR1 IR0 IRQ 658 * 0 0 0 2/9 659 * 0 0 1 3 660 * 0 1 0 5 661 * 0 1 1 7 662 * 1 0 0 10 663 * 1 0 1 11 664 * 1 1 0 15 665 * 1 1 1 4 666 */ 667#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 668#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 669#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 670 671/* 672 * LA Address Register (LAAR) 673 */ 674#define ED_WD_LAAR 5 675 676#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 677#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 678#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 679#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 680 681/* i/o base offset to station address/card-ID PROM */ 682#define ED_WD_PROM 8 683 684/* i/o base offset to CARD ID */ 685#define ED_WD_CARD_ID ED_WD_PROM+6 686 687/* Board type codes in card ID */ 688#define ED_TYPE_WD8003S 0x02 689#define ED_TYPE_WD8003E 0x03 690#define ED_TYPE_WD8013EBT 0x05 691#define ED_TYPE_WD8013EP 0x27 692#define ED_TYPE_WD8013WC 0x28 693#define ED_TYPE_WD8013EBP 0x2c 694#define ED_TYPE_WD8013EPC 0x29 695 696/* Bit definitions in card ID */ 697#define ED_WD_REV_MASK 0x1f /* Revision mask */ 698#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 699#define ED_WD_LARGERAM 0x40 /* Large RAM */ 700#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 701 702/* 703 * Checksum total. All 8 bytes in station address PROM will add up to this 704 */ 705#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 706 707#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 708#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 709#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 710 711#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 712 713/* 714 * Definitions for 3Com 3c503 715 */ 716#define ED_3COM_NIC_OFFSET 0 717#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 718 719/* 720 * XXX - The I/O address range is fragmented in the 3c503; this is the 721 * number of regs at iobase. 722 */ 723#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 724 725/* tx memory starts in second bank on 8bit cards */ 726#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 727 728/* tx memory starts in first bank on 16bit cards */ 729#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 730 731/* ...and rx memory starts in second bank */ 732#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 733 734 735/* 736 * Page Start Register. Must match PSTART in NIC 737 */ 738#define ED_3COM_PSTR 0 739 740/* 741 * Page Stop Register. Must match PSTOP in NIC 742 */ 743#define ED_3COM_PSPR 1 744 745/* 746 * Drq Timer Register. Determines number of bytes to be transfered during 747 * a DMA burst. 748 */ 749#define ED_3COM_DQTR 2 750 751/* 752 * Base Configuration Register. Read-only register which contains the 753 * board-configured I/O base address of the adapter. Bit encoded. 754 */ 755#define ED_3COM_BCFR 3 756 757#define ED_3COM_BCFR_2E0 0x01 758#define ED_3COM_BCFR_2A0 0x02 759#define ED_3COM_BCFR_280 0x04 760#define ED_3COM_BCFR_250 0x08 761#define ED_3COM_BCFR_350 0x10 762#define ED_3COM_BCFR_330 0x20 763#define ED_3COM_BCFR_310 0x40 764#define ED_3COM_BCFR_300 0x80 765 766/* 767 * EPROM Configuration Register. Read-only register which contains the 768 * board-configured memory base address. Bit encoded. 769 */ 770#define ED_3COM_PCFR 4 771 772#define ED_3COM_PCFR_C8000 0x10 773#define ED_3COM_PCFR_CC000 0x20 774#define ED_3COM_PCFR_D8000 0x40 775#define ED_3COM_PCFR_DC000 0x80 776 777/* 778 * GA Configuration Register. Gate-Array Configuration Register. 779 */ 780#define ED_3COM_GACFR 5 781 782/* 783 * mbs2 mbs1 mbs0 start address 784 * 0 0 0 0x0000 785 * 0 0 1 0x2000 786 * 0 1 0 0x4000 787 * 0 1 1 0x6000 788 * 789 * Note that with adapters with only 8K, the setting for 0x2000 must 790 * always be used. 791 */ 792#define ED_3COM_GACFR_MBS0 0x01 793#define ED_3COM_GACFR_MBS1 0x02 794#define ED_3COM_GACFR_MBS2 0x04 795 796#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 797#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 798#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 799#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 800#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 801 802/* 803 * Control Register. Miscellaneous control functions. 804 */ 805#define ED_3COM_CR 6 806 807#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 808#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 809#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 810#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 811#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 812#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 813#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 814#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 815 816/* 817 * Status Register. Miscellaneous status information. 818 */ 819#define ED_3COM_STREG 7 820 821#define ED_3COM_STREG_REV 0x07 /* GA revision */ 822#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 823#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 824#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 825#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 826#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 827 828/* 829 * Interrupt/DMA Configuration Register 830 */ 831#define ED_3COM_IDCFR 8 832 833#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 834#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 835#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 836#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 837#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 838#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 839#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 840#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 841 842/* 843 * DMA Address Register MSB 844 */ 845#define ED_3COM_DAMSB 9 846 847/* 848 * DMA Address Register LSB 849 */ 850#define ED_3COM_DALSB 0x0a 851 852/* 853 * Vector Pointer Register 2 854 */ 855#define ED_3COM_VPTR2 0x0b 856 857/* 858 * Vector Pointer Register 1 859 */ 860#define ED_3COM_VPTR1 0x0c 861 862/* 863 * Vector Pointer Register 0 864 */ 865#define ED_3COM_VPTR0 0x0d 866 867/* 868 * Register File Access MSB 869 */ 870#define ED_3COM_RFMSB 0x0e 871 872/* 873 * Register File Access LSB 874 */ 875#define ED_3COM_RFLSB 0x0f 876 877/* 878 * Definitions for Novell NE1000/2000 boards 879 */ 880 881/* 882 * Board type codes 883 */ 884#define ED_TYPE_NE1000 0x01 885#define ED_TYPE_NE2000 0x02 886 887/* 888 * Register offsets/total 889 */ 890#define ED_NOVELL_NIC_OFFSET 0x00 891#define ED_NOVELL_ASIC_OFFSET 0x10 892#define ED_NOVELL_IO_PORTS 32 893 894/* 895 * Remote DMA data register; for reading or writing to the NIC mem 896 * via programmed I/O (offset from ASIC base) 897 */ 898#define ED_NOVELL_DATA 0x00 899 900/* 901 * Reset register; reading from this register causes a board reset 902 */ 903#define ED_NOVELL_RESET 0x0f 904