if_edreg.h revision 172
1/* 2 * National Semiconductor DS8390 NIC register definitions 3 * 4 * $Log: if_edreg.h,v $ 5 * Revision 1.3 93/07/20 15:25:25 davidg 6 * added config flags for forcing 8/16bit mode and disabling double 7 * xmit buffers. 8 * 9 * Revision 1.2 93/06/23 03:03:05 davidg 10 * added some additional definitions for the 83C584 bus interface 11 * chip (SMC/WD boards) 12 * 13 * Revision 1.1 93/06/23 03:01:07 davidg 14 * Initial revision 15 * 16 */ 17 18/* 19 * Page 0 register offsets 20 */ 21#define ED_P0_CR 0x00 /* Command Register */ 22 23#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 24#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 25 26#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 27#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 28 29#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 30 31#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 32#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 33 34#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 35#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 36 37#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 38#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 39 40#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 41 42#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 43#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 44 45#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 46#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 47 48#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 49 50#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 51 52#define ED_P0_RSR 0x0c /* Receive Status (read) */ 53#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 54 55#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 56#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 57 58#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 59#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 60 61#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 62#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 63 64/* 65 * Page 1 register offsets 66 */ 67#define ED_P1_CR 0x00 /* Command Register */ 68#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 69#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 70#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 71#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 72#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 73#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 74#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 75#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 76#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 77#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 78#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 79#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 80#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 81#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 82#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 83 84/* 85 * Page 2 register offsets 86 */ 87#define ED_P2_CR 0x00 /* Command Register */ 88#define ED_P2_PSTART 0x01 /* Page Start (read) */ 89#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 90#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 91#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 92#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 93#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 94#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 95#define ED_P2_ACU 0x06 /* Address Counter Upper */ 96#define ED_P2_ACL 0x07 /* Address Counter Lower */ 97#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 98#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 99#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 100#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 101 102/* 103 * Command Register (CR) definitions 104 */ 105 106/* 107 * STP: SToP. Software reset command. Takes the controller offline. No 108 * packets will be received or transmitted. Any reception or 109 * transmission in progress will continue to completion before 110 * entering reset state. To exit this state, the STP bit must 111 * reset and the STA bit must be set. The software reset has 112 * executed only when indicated by the RST bit in the ISR being 113 * set. 114 */ 115#define ED_CR_STP 0x01 116 117/* 118 * STA: STArt. This bit is used to activate the NIC after either power-up, 119 * or when the NIC has been put in reset mode by software command 120 * or error. 121 */ 122#define ED_CR_STA 0x02 123 124/* 125 * TXP: Transmit Packet. This bit must be set to indicate transmission of 126 * a packet. TXP is internally reset either after the transmission is 127 * completed or aborted. This bit should be set only after the Transmit 128 * Byte Count and Transmit Page Start register have been programmed. 129 */ 130#define ED_CR_TXP 0x04 131 132/* 133 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 134 * of the remote DMA channel. RD2 can be set to abort any remote DMA 135 * command in progress. The Remote Byte Count registers should be cleared 136 * when a remote DMA has been aborted. The Remote Start Addresses are not 137 * restored to the starting address if the remote DMA is aborted. 138 * 139 * RD2 RD1 RD0 function 140 * 0 0 0 not allowed 141 * 0 0 1 remote read 142 * 0 1 0 remote write 143 * 0 1 1 send packet 144 * 1 X X abort 145 */ 146#define ED_CR_RD0 0x08 147#define ED_CR_RD1 0x10 148#define ED_CR_RD2 0x20 149 150/* 151 * PS0, PS1: Page Select. The two bits select which register set or 'page' to 152 * access. 153 * 154 * PS1 PS0 page 155 * 0 0 0 156 * 0 1 1 157 * 1 0 2 158 * 1 1 reserved 159 */ 160#define ED_CR_PS0 0x40 161#define ED_CR_PS1 0x80 162/* bit encoded aliases */ 163#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 164#define ED_CR_PAGE_1 0x40 165#define ED_CR_PAGE_2 0x80 166 167/* 168 * Interrupt Status Register (ISR) definitions 169 */ 170 171/* 172 * PRX: Packet Received. Indicates packet received with no errors. 173 */ 174#define ED_ISR_PRX 0x01 175 176/* 177 * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 178 */ 179#define ED_ISR_PTX 0x02 180 181/* 182 * RXE: Receive Error. Indicates that a packet was received with one or more 183 * the following errors: CRC error, frame alignment error, FIFO overrun, 184 * missed packet. 185 */ 186#define ED_ISR_RXE 0x04 187 188/* 189 * TXE: Transmission Error. Indicates that an attempt to transmit a packet 190 * resulted in one or more of the following errors: excessive 191 * collisions, FIFO underrun. 192 */ 193#define ED_ISR_TXE 0x08 194 195/* 196 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 197 * would exceed (has exceeded?) the boundry pointer, resulting in data 198 * that was previously received and not yet read from the buffer to be 199 * overwritten. 200 */ 201#define ED_ISR_OVW 0x10 202 203/* 204 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 205 * Counters has been set. 206 */ 207#define ED_ISR_CNT 0x20 208 209/* 210 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 211 */ 212#define ED_ISR_RDC 0x40 213 214/* 215 * RST: Reset status. Set when the NIC enters the reset state and cleared when a 216 * Start Command is issued to the CR. This bit is also set when a receive 217 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 218 * packets have been removed from the ring. This is a read-only bit. 219 */ 220#define ED_ISR_RST 0x80 221 222/* 223 * Interrupt Mask Register (IMR) definitions 224 */ 225 226/* 227 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 228 * an interrupt. 229 */ 230#define ED_IMR_PRXE 0x01 231 232/* 233 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 234 * a packet transmission completes. 235 */ 236#define ED_IMR_PTXE 0x02 237 238/* 239 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 240 * packet is received with an error. 241 */ 242#define ED_IMR_RXEE 0x04 243 244/* 245 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 246 * a transmission results in an error. 247 */ 248#define ED_IMR_TXEE 0x08 249 250/* 251 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 252 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded. 253 */ 254#define ED_IMR_OVWE 0x10 255 256/* 257 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 258 * the MSB of one or more of the Network Statistics counters has been set. 259 */ 260#define ED_IMR_CNTE 0x20 261 262/* 263 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 264 * when a remote DMA transfer has completed. 265 */ 266#define ED_IMR_RDCE 0x40 267 268/* 269 * bit 7 is unused/reserved 270 */ 271 272/* 273 * Data Configuration Register (DCR) definitions 274 */ 275 276/* 277 * WTS: Word Transfer Select. WTS establishes byte or word transfers for 278 * both remote and local DMA transfers 279 */ 280#define ED_DCR_WTS 0x01 281 282/* 283 * BOS: Byte Order Select. BOS sets the byte order for the host. 284 * Should be 0 for 80x86, and 1 for 68000 series processors 285 */ 286#define ED_DCR_BOS 0x02 287 288/* 289 * LAS: Long Address Select. When LAS is 1, the contents of the remote 290 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 291 */ 292#define ED_DCR_LAS 0x04 293 294/* 295 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 296 * of the TCR must also be programmed for loopback operation. 297 * When 1, normal operation is selected. 298 */ 299#define ED_DCR_LS 0x08 300 301/* 302 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 303 * under program control. When 1, remote DMA is automatically initiated 304 * and the boundry pointer is automatically updated 305 */ 306#define ED_DCR_AR 0x10 307 308/* 309 * FT0, FT1: Fifo Threshold select. 310 * FT1 FT0 Word-width Byte-width 311 * 0 0 1 word 2 bytes 312 * 0 1 2 words 4 bytes 313 * 1 0 4 words 8 bytes 314 * 1 1 8 words 12 bytes 315 * 316 * During transmission, the FIFO threshold indicates the number of bytes 317 * or words that the FIFO has filled from the local DMA before BREQ is 318 * asserted. The transmission threshold is 16 bytes minus the receiver 319 * threshold. 320 */ 321#define ED_DCR_FT0 0x20 322#define ED_DCR_FT1 0x40 323 324/* 325 * bit 7 (0x80) is unused/reserved 326 */ 327 328/* 329 * Transmit Configuration Register (TCR) definitions 330 */ 331 332/* 333 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 334 * is not appended by the transmitter. 335 */ 336#define ED_TCR_CRC 0x01 337 338/* 339 * LB0, LB1: Loopback control. These two bits set the type of loopback that is 340 * to be performed. 341 * 342 * LB1 LB0 mode 343 * 0 0 0 - normal operation (DCR_LS = 0) 344 * 0 1 1 - internal loopback (DCR_LS = 0) 345 * 1 0 2 - external loopback (DCR_LS = 1) 346 * 1 1 3 - external loopback (DCR_LS = 0) 347 */ 348#define ED_TCR_LB0 0x02 349#define ED_TCR_LB1 0x04 350 351/* 352 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 353 * another station to disable the NIC's transmitter by transmitting to 354 * a multicast address hashing to bit 62. Reception of a multicast address 355 * hashing to bit 63 enables the transmitter. 356 */ 357#define ED_TCR_ATD 0x08 358 359/* 360 * OFST: Collision Offset enable. This bit when set modifies the backoff 361 * algorithm to allow prioritization of nodes. 362 */ 363#define ED_TCR_OFST 0x10 364 365/* 366 * bits 5, 6, and 7 are unused/reserved 367 */ 368 369/* 370 * Transmit Status Register (TSR) definitions 371 */ 372 373/* 374 * PTX: Packet Transmitted. Indicates successful transmission of packet. 375 */ 376#define ED_TSR_PTX 0x01 377 378/* 379 * bit 1 (0x02) is unused/reserved 380 */ 381 382/* 383 * COL: Transmit Collided. Indicates that the transmission collided at least 384 * once with another station on the network. 385 */ 386#define ED_TSR_COL 0x04 387 388/* 389 * ABT: Transmit aborted. Indicates that the transmission was aborted due to 390 * excessive collisions. 391 */ 392#define ED_TSR_ABT 0x08 393 394/* 395 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 396 * transmission of the packet. (Transmission is not aborted because 397 * of a loss of carrier) 398 */ 399#define ED_TSR_CRS 0x10 400 401/* 402 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 403 * transmission memory before the FIFO emptied. Transmission of the 404 * packet was aborted. 405 */ 406#define ED_TSR_FU 0x20 407 408/* 409 * CDH: CD Heartbeat. Indicates that the collision detection circuitry 410 * isn't working correctly during a collision heartbeat test. 411 */ 412#define ED_TSR_CDH 0x40 413 414/* 415 * OWC: Out of Window Collision: Indicates that a collision occurred after 416 * a slot time (51.2us). The transmission is rescheduled just as in 417 * normal collisions. 418 */ 419#define ED_TSR_OWC 0x80 420 421/* 422 * Receiver Configuration Register (RCR) definitions 423 */ 424 425/* 426 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 427 * packets with CRC and frame errors are not discarded. 428 */ 429#define ED_RCR_SEP 0x01 430 431/* 432 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 433 * If set to 1, packets with less than 64 byte are not discarded. 434 */ 435#define ED_RCR_AR 0x02 436 437/* 438 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 439 * accepted. 440 */ 441#define ED_RCR_AB 0x04 442 443/* 444 * AM: Accept Multicast. If set, packets sent to a multicast address are checked 445 * for a match in the hashing array. If clear, multicast packets are ignored. 446 */ 447#define ED_RCR_AM 0x08 448 449/* 450 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 451 * accepted. If clear, a physical destination address must match this 452 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 453 * must also be set. In addition, the multicast hashing array must be set 454 * to all 1's so that all multicast addresses are accepted. 455 */ 456#define ED_RCR_PRO 0x10 457 458/* 459 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 460 * but are not stored in the ring-buffer. If clear, packets are stored (normal 461 * operation). 462 */ 463#define ED_RCR_MON 0x20 464 465/* 466 * bits 6 and 7 are unused/reserved. 467 */ 468 469/* 470 * Receiver Status Register (RSR) definitions 471 */ 472 473/* 474 * PRX: Packet Received without error. 475 */ 476#define ED_RSR_PRX 0x01 477 478/* 479 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 480 * alignment errors. 481 */ 482#define ED_RSR_CRC 0x02 483 484/* 485 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 486 * a byte boundry and the CRC did not match at the last byte boundry. 487 */ 488#define ED_RSR_FAE 0x04 489 490/* 491 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 492 * causing it to overrun. Reception of the packet is aborted. 493 */ 494#define ED_RSR_FO 0x08 495 496/* 497 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 498 * the ring-buffer because of insufficient buffer space (exceeding the 499 * boundry pointer), or because the transfer to the ring-buffer was inhibited 500 * by RCR_MON - monitor mode. 501 */ 502#define ED_RSR_MPA 0x10 503 504/* 505 * PHY: Physical address. If 0, the packet received was sent to a physical address. 506 * If 1, the packet was accepted because of a multicast/broadcast address 507 * match. 508 */ 509#define ED_RSR_PHY 0x20 510 511/* 512 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor 513 * mode. Cleared when the receiver exits monitor mode. 514 */ 515#define ED_RSR_DIS 0x40 516 517/* 518 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 519 * are active, and the transceiver has set the CD line as a result of the 520 * jabber. 521 */ 522#define ED_RSR_DFR 0x80 523 524/* 525 * receive ring discriptor 526 * 527 * The National Semiconductor DS8390 Network interface controller uses 528 * the following receive ring headers. The way this works is that the 529 * memory on the interface card is chopped up into 256 bytes blocks. 530 * A contiguous portion of those blocks are marked for receive packets 531 * by setting start and end block #'s in the NIC. For each packet that 532 * is put into the receive ring, one of these headers (4 bytes each) is 533 * tacked onto the front. 534 */ 535struct ed_ring { 536 struct edr_status { /* received packet status */ 537 u_char rs_prx:1, /* packet received intack */ 538 rs_crc:1, /* crc error */ 539 rs_fae:1, /* frame alignment error */ 540 rs_fo:1, /* fifo overrun */ 541 rs_mpa:1, /* packet received intack */ 542 rs_phy:1, /* packet received intack */ 543 rs_dis:1, /* packet received intack */ 544 rs_dfr:1; /* packet received intack */ 545 } ed_rcv_status; /* received packet status */ 546 u_char next_packet; /* pointer to next packet */ 547 u_short count; /* bytes in packet (length + 4) */ 548}; 549 550/* 551 * Common constants 552 */ 553#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 554#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 555 556/* 557 * Vendor types 558 */ 559#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 560#define ED_VENDOR_3COM 0x01 /* 3Com */ 561 562/* 563 * Compile-time config flags 564 */ 565/* 566 * this sets the default for enabling/disablng the tranceiver 567 */ 568#define ED_FLAGS_DISABLE_TRANCEIVER 0x01 569 570/* 571 * This forces the board to be used in 8/16bit mode even if it 572 * autoconfigs differently 573 */ 574#define ED_FLAGS_FORCE_8BIT_MODE 0x02 575#define ED_FLAGS_FORCE_16BIT_MODE 0x04 576 577/* 578 * This disables the use of double transmit buffers. 579 */ 580#define ED_FLAGS_NO_DOUBLE_BUFFERING 0x08 581 582/* 583 * Definitions for Western digital/SMC WD80x3 series ASIC 584 */ 585/* 586 * Memory Select Register (MSR) 587 */ 588#define ED_WD_MSR 0 589 590#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 591#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 592#define ED_WD_MSR_RST 0x80 /* Reset board */ 593 594/* 595 * Interface Configuration Register (ICR) 596 */ 597#define ED_WD_ICR 1 598 599#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 600#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 601#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 602#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 603#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 604#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 605#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 606#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 607 608/* 609 * IO Address Register (IAR) 610 */ 611#define ED_WD_IAR 2 612 613/* 614 * EEROM Address Register 615 */ 616#define ED_WD_EAR 3 617 618/* 619 * Interrupt Request Register (IRR) 620 */ 621#define ED_WD_IRR 4 622 623#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 624#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 625#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 626#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 627#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 628 629/* 630 * The three bit of the encoded IRQ are decoded as follows: 631 * 632 * IR2 IR1 IR0 IRQ 633 * 0 0 0 2/9 634 * 0 0 1 3 635 * 0 1 0 5 636 * 0 1 1 7 637 * 1 0 0 10 638 * 1 0 1 11 639 * 1 1 0 15 640 * 1 1 1 4 641 */ 642#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 643#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 644#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 645 646/* 647 * LA Address Register (LAAR) 648 */ 649#define ED_WD_LAAR 5 650 651#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 652#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 653#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 654#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 655 656/* i/o base offset to station address/card-ID PROM */ 657#define ED_WD_PROM 8 658 659/* i/o base offset to CARD ID */ 660#define ED_WD_CARD_ID ED_WD_PROM+6 661 662#define ED_TYPE_WD8003S 0x02 663#define ED_TYPE_WD8003E 0x03 664#define ED_TYPE_WD8013EBT 0x05 665#define ED_TYPE_WD8013EB 0x27 666#define ED_TYPE_WD8013EBP 0x2c 667#define ED_TYPE_WD8013EPC 0x29 668 669/* Bit definitions in card ID */ 670#define ED_WD_REV_MASK 0x1f /* Revision mask */ 671#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 672#define ED_WD_LARGERAM 0x40 /* Large RAM */ 673#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 674 675/* 676 * Checksum total. All 8 bytes in station address PROM will add up to this 677 */ 678#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 679 680#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 681#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 682#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 683 684#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 685 686/* 687 * Definitions for 3Com 3c503 688 */ 689#define ED_3COM_NIC_OFFSET 0 690#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 691 692/* 693 * XXX - The I/O address range is fragmented in the 3c503; this is the 694 * number of regs at iobase. 695 */ 696#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 697 698#define ED_3COM_PAGE_OFFSET 0x20 /* memory starts in second bank */ 699 700/* 701 * Page Start Register. Must match PSTART in NIC 702 */ 703#define ED_3COM_PSTR 0 704 705/* 706 * Page Stop Register. Must match PSTOP in NIC 707 */ 708#define ED_3COM_PSPR 1 709 710/* 711 * Drq Timer Register. Determines number of bytes to be transfered during 712 * a DMA burst. 713 */ 714#define ED_3COM_DQTR 2 715 716/* 717 * Base Configuration Register. Read-only register which contains the 718 * board-configured I/O base address of the adapter. Bit encoded. 719 */ 720#define ED_3COM_BCFR 3 721 722#define ED_3COM_BCFR_2E0 0x01 723#define ED_3COM_BCFR_2A0 0x02 724#define ED_3COM_BCFR_280 0x04 725#define ED_3COM_BCFR_250 0x08 726#define ED_3COM_BCFR_350 0x10 727#define ED_3COM_BCFR_330 0x20 728#define ED_3COM_BCFR_310 0x40 729#define ED_3COM_BCFR_300 0x80 730 731/* 732 * EPROM Configuration Register. Read-only register which contains the 733 * board-configured memory base address. Bit encoded. 734 */ 735#define ED_3COM_PCFR 4 736 737#define ED_3COM_PCFR_C8000 0x10 738#define ED_3COM_PCFR_CC000 0x20 739#define ED_3COM_PCFR_D8000 0x40 740#define ED_3COM_PCFR_DC000 0x80 741 742/* 743 * GA Configuration Register. Gate-Array Configuration Register. 744 */ 745#define ED_3COM_GACFR 5 746 747/* 748 * mbs2 mbs1 mbs0 start address 749 * 0 0 0 0x0000 750 * 0 0 1 0x2000 751 * 0 1 0 0x4000 752 * 0 1 1 0x6000 753 * 754 * Note that with adapters with only 8K, the setting for 0x2000 must 755 * always be used. 756 */ 757#define ED_3COM_GACFR_MBS0 0x01 758#define ED_3COM_GACFR_MBS1 0x02 759#define ED_3COM_GACFR_MBS2 0x04 760 761#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 762#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 763#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 764#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 765#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 766 767/* 768 * Control Register. Miscellaneous control functions. 769 */ 770#define ED_3COM_CR 6 771 772#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 773#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 774#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 775#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 776#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 777#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 778#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 779#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 780 781/* 782 * Status Register. Miscellaneous status information. 783 */ 784#define ED_3COM_STREG 7 785 786#define ED_3COM_STREG_REV 0x07 /* GA revision */ 787#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 788#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 789#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 790#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 791#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 792 793/* 794 * Interrupt/DMA Configuration Register 795 */ 796#define ED_3COM_IDCFR 8 797 798#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 799#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 800#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 801#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 802#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 803#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 804#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 805#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 806 807/* 808 * DMA Address Register MSB 809 */ 810#define ED_3COM_DAMSB 9 811 812/* 813 * DMA Address Register LSB 814 */ 815#define ED_3COM_DALSB 0x0a 816 817/* 818 * Vector Pointer Register 2 819 */ 820#define ED_3COM_VPTR2 0x0b 821 822/* 823 * Vector Pointer Register 1 824 */ 825#define ED_3COM_VPTR1 0x0c 826 827/* 828 * Vector Pointer Register 0 829 */ 830#define ED_3COM_VPTR0 0x0d 831 832/* 833 * Register File Access MSB 834 */ 835#define ED_3COM_RFMSB 0x0e 836 837/* 838 * Register File Access LSB 839 */ 840#define ED_3COM_RFLSB 0x0f 841