e1000_phy.h revision 169248 
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32*******************************************************************************/
33
34/*
35 * $FreeBSD: head/sys/dev/em/e1000_phy.h 169248 2007-05-04 13:30:44Z rwatson $
36 */
37
38
39#ifndef _E1000_PHY_H_
40#define _E1000_PHY_H_
41
42typedef enum {
43	e1000_ms_hw_default = 0,
44	e1000_ms_force_master,
45	e1000_ms_force_slave,
46	e1000_ms_auto
47} e1000_ms_type;
48
49typedef enum {
50	e1000_smart_speed_default = 0,
51	e1000_smart_speed_on,
52	e1000_smart_speed_off
53} e1000_smart_speed;
54
55#include "e1000_api.h"
56
57s32  e1000_check_downshift_generic(struct e1000_hw *hw);
58s32  e1000_check_polarity_m88(struct e1000_hw *hw);
59s32  e1000_check_polarity_igp(struct e1000_hw *hw);
60s32  e1000_check_reset_block_generic(struct e1000_hw *hw);
61s32  e1000_copper_link_autoneg(struct e1000_hw *hw);
62s32  e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63s32  e1000_copper_link_setup_igp(struct e1000_hw *hw);
64s32  e1000_copper_link_setup_m88(struct e1000_hw *hw);
65s32  e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
66s32  e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
67s32  e1000_get_cable_length_m88(struct e1000_hw *hw);
68s32  e1000_get_cable_length_igp_2(struct e1000_hw *hw);
69s32  e1000_get_cfg_done_generic(struct e1000_hw *hw);
70s32  e1000_get_phy_id(struct e1000_hw *hw);
71s32  e1000_get_phy_info_igp(struct e1000_hw *hw);
72s32  e1000_get_phy_info_m88(struct e1000_hw *hw);
73s32  e1000_phy_sw_reset_generic(struct e1000_hw *hw);
74void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
75s32  e1000_phy_hw_reset_generic(struct e1000_hw *hw);
76s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
77s32  e1000_phy_setup_autoneg(struct e1000_hw *hw);
78s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
79s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
80s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
81s32  e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, boolean_t active);
82s32  e1000_setup_copper_link_generic(struct e1000_hw *hw);
83s32  e1000_wait_autoneg_generic(struct e1000_hw *hw);
84s32  e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
85s32  e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
86s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
87s32  e1000_phy_reset_dsp(struct e1000_hw *hw);
88s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
89                                u32 usec_interval, boolean_t *success);
90s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
91
92
93
94/* IGP01E1000 Specific Registers */
95#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
96#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
97#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
98#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
99#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
100#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
101#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
102#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
103
104#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
105#define IGP01E1000_PHY_POLARITY_MASK      0x0078
106
107#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
108#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
109
110#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
111
112#define IGP01E1000_GMII_FLEX_SPD          0x0010 /* Enable flexible speed
113                                                  * on link-up */
114#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
115
116#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
117#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
118#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
119
120#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
121
122#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
123#define IGP01E1000_PSSR_MDIX              0x0008
124#define IGP01E1000_PSSR_SPEED_MASK        0xC000
125#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
126
127#define IGP02E1000_PHY_CHANNEL_NUM        4
128#define IGP02E1000_PHY_AGC_A              0x11B1
129#define IGP02E1000_PHY_AGC_B              0x12B1
130#define IGP02E1000_PHY_AGC_C              0x14B1
131#define IGP02E1000_PHY_AGC_D              0x18B1
132
133#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
134#define IGP02E1000_AGC_LENGTH_MASK        0x7F
135#define IGP02E1000_AGC_RANGE              15
136
137#define IGP03E1000_PHY_MISC_CTRL          0x1B
138#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
139
140#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
141
142#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
143#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
144#define E1000_KMRNCTRLSTA_REN             0x00200000
145#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
146#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
147
148#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
149#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
150#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
151#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
152
153/* IFE PHY Extended Status Control */
154#define IFE_PESC_POLARITY_REVERSED    0x0100
155
156/* IFE PHY Special Control */
157#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
158#define IFE_PSC_FORCE_POLARITY             0x0020
159#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
160
161/* IFE PHY Special Control and LED Control */
162#define IFE_PSCL_PROBE_MODE            0x0020
163#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
164#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
165
166/* IFE PHY MDIX Control */
167#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
168#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
169#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
170
171#endif
172