e1000_phy.h revision 169240
15696Smgronlun/******************************************************************************* 25696Smgronlun 35696Smgronlun Copyright (c) 2001-2007, Intel Corporation 45696Smgronlun All rights reserved. 55696Smgronlun 65696Smgronlun Redistribution and use in source and binary forms, with or without 75696Smgronlun modification, are permitted provided that the following conditions are met: 85696Smgronlun 95696Smgronlun 1. Redistributions of source code must retain the above copyright notice, 105696Smgronlun this list of conditions and the following disclaimer. 115696Smgronlun 125696Smgronlun 2. Redistributions in binary form must reproduce the above copyright 135696Smgronlun notice, this list of conditions and the following disclaimer in the 145696Smgronlun documentation and/or other materials provided with the distribution. 155696Smgronlun 165696Smgronlun 3. Neither the name of the Intel Corporation nor the names of its 175696Smgronlun contributors may be used to endorse or promote products derived from 185696Smgronlun this software without specific prior written permission. 195696Smgronlun 205696Smgronlun THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 215696Smgronlun AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 225696Smgronlun IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 235696Smgronlun ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 245696Smgronlun LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 255696Smgronlun CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 265696Smgronlun SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 275696Smgronlun INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 285696Smgronlun CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 295696Smgronlun ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 305696Smgronlun POSSIBILITY OF SUCH DAMAGE. 315696Smgronlun 325696Smgronlun*******************************************************************************/ 335696Smgronlun$FreeBSD: head/sys/dev/em/e1000_phy.h 169240 2007-05-04 00:00:12Z jfv $ 345696Smgronlun 355696Smgronlun 365696Smgronlun#ifndef _E1000_PHY_H_ 375696Smgronlun#define _E1000_PHY_H_ 385696Smgronlun 395696Smgronluntypedef enum { 405696Smgronlun e1000_ms_hw_default = 0, 415696Smgronlun e1000_ms_force_master, 425696Smgronlun e1000_ms_force_slave, 435696Smgronlun e1000_ms_auto 445696Smgronlun} e1000_ms_type; 455696Smgronlun 465696Smgronluntypedef enum { 475696Smgronlun e1000_smart_speed_default = 0, 485696Smgronlun e1000_smart_speed_on, 495696Smgronlun e1000_smart_speed_off 505696Smgronlun} e1000_smart_speed; 515696Smgronlun 525696Smgronlun#include "e1000_api.h" 535696Smgronlun 545696Smgronluns32 e1000_check_downshift_generic(struct e1000_hw *hw); 555696Smgronluns32 e1000_check_polarity_m88(struct e1000_hw *hw); 565696Smgronluns32 e1000_check_polarity_igp(struct e1000_hw *hw); 575696Smgronluns32 e1000_check_reset_block_generic(struct e1000_hw *hw); 585696Smgronluns32 e1000_copper_link_autoneg(struct e1000_hw *hw); 595696Smgronluns32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 605696Smgronluns32 e1000_copper_link_setup_igp(struct e1000_hw *hw); 615696Smgronluns32 e1000_copper_link_setup_m88(struct e1000_hw *hw); 625696Smgronluns32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); 635696Smgronluns32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); 645696Smgronluns32 e1000_get_cable_length_m88(struct e1000_hw *hw); 655696Smgronluns32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); 665696Smgronluns32 e1000_get_cfg_done_generic(struct e1000_hw *hw); 675696Smgronluns32 e1000_get_phy_id(struct e1000_hw *hw); 685696Smgronluns32 e1000_get_phy_info_igp(struct e1000_hw *hw); 69s32 e1000_get_phy_info_m88(struct e1000_hw *hw); 70s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); 71void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 72s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); 73s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); 74s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 75s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); 76s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 77s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 78s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, boolean_t active); 79s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); 80s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); 81s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); 82s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 83s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 84s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 85s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 86 u32 usec_interval, boolean_t *success); 87s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); 88 89 90 91/* IGP01E1000 Specific Registers */ 92#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 93#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 94#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 95#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 96#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 97#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ 98#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 99#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 100 101#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 102#define IGP01E1000_PHY_POLARITY_MASK 0x0078 103 104#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 105#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 106 107#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 108 109#define IGP01E1000_GMII_FLEX_SPD 0x0010 /* Enable flexible speed 110 * on link-up */ 111#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ 112 113#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 114#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 115#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 116 117#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 118 119#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 120#define IGP01E1000_PSSR_MDIX 0x0008 121#define IGP01E1000_PSSR_SPEED_MASK 0xC000 122#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 123 124#define IGP02E1000_PHY_CHANNEL_NUM 4 125#define IGP02E1000_PHY_AGC_A 0x11B1 126#define IGP02E1000_PHY_AGC_B 0x12B1 127#define IGP02E1000_PHY_AGC_C 0x14B1 128#define IGP02E1000_PHY_AGC_D 0x18B1 129 130#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ 131#define IGP02E1000_AGC_LENGTH_MASK 0x7F 132#define IGP02E1000_AGC_RANGE 15 133 134#define IGP03E1000_PHY_MISC_CTRL 0x1B 135#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ 136 137#define E1000_CABLE_LENGTH_UNDEFINED 0xFF 138 139#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 140#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 141#define E1000_KMRNCTRLSTA_REN 0x00200000 142#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 143#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 144 145#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 146#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ 147#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ 148#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 149 150/* IFE PHY Extended Status Control */ 151#define IFE_PESC_POLARITY_REVERSED 0x0100 152 153/* IFE PHY Special Control */ 154#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 155#define IFE_PSC_FORCE_POLARITY 0x0020 156#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 157 158/* IFE PHY Special Control and LED Control */ 159#define IFE_PSCL_PROBE_MODE 0x0020 160#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 161#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 162 163/* IFE PHY MDIX Control */ 164#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 165#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 166#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ 167 168#endif 169