e1000_82575.c revision 176667
1187517Sgonzo/****************************************************************************** 2187517Sgonzo 3187517Sgonzo Copyright (c) 2001-2008, Intel Corporation 4187517Sgonzo All rights reserved. 5187517Sgonzo 6187517Sgonzo Redistribution and use in source and binary forms, with or without 7187517Sgonzo modification, are permitted provided that the following conditions are met: 8187517Sgonzo 9187517Sgonzo 1. Redistributions of source code must retain the above copyright notice, 10187517Sgonzo this list of conditions and the following disclaimer. 11187517Sgonzo 12187517Sgonzo 2. Redistributions in binary form must reproduce the above copyright 13187517Sgonzo notice, this list of conditions and the following disclaimer in the 14187517Sgonzo documentation and/or other materials provided with the distribution. 15187517Sgonzo 16187517Sgonzo 3. Neither the name of the Intel Corporation nor the names of its 17187517Sgonzo contributors may be used to endorse or promote products derived from 18187517Sgonzo this software without specific prior written permission. 19187517Sgonzo 20187517Sgonzo THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21187517Sgonzo AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22187517Sgonzo IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23187517Sgonzo ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24187517Sgonzo LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25187517Sgonzo CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26187517Sgonzo SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27187517Sgonzo INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28187517Sgonzo CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29187517Sgonzo ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30187517Sgonzo POSSIBILITY OF SUCH DAMAGE. 31187517Sgonzo 32187517Sgonzo******************************************************************************/ 33187517Sgonzo/*$FreeBSD: head/sys/dev/igb/e1000_82575.c 176667 2008-02-29 21:50:11Z jfv $*/ 34187517Sgonzo 35187517Sgonzo/* e1000_82575 36187517Sgonzo * e1000_82576 37187517Sgonzo */ 38187517Sgonzo 39232847Sgonzo#include "e1000_api.h" 40232847Sgonzo#include "e1000_82575.h" 41232847Sgonzo 42232847Sgonzostatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 43187517Sgonzostatic s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 44187517Sgonzostatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 45199497Sgonzostatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 46187517Sgonzostatic void e1000_release_phy_82575(struct e1000_hw *hw); 47187517Sgonzostatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 48187517Sgonzostatic void e1000_release_nvm_82575(struct e1000_hw *hw); 49221257Sadrianstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw); 50187517Sgonzostatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 51232847Sgonzostatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 52232847Sgonzo u16 *duplex); 53188883Sgonzostatic s32 e1000_init_hw_82575(struct e1000_hw *hw); 54188883Sgonzostatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 55188883Sgonzostatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 56188883Sgonzo u16 *data); 57188883Sgonzostatic s32 e1000_reset_hw_82575(struct e1000_hw *hw); 58188883Sgonzostatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 59188883Sgonzo bool active); 60263279Sadrianstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 61263279Sadrianstatic s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw); 62187517Sgonzostatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 63187517Sgonzo u32 offset, u16 data); 64212413Savgstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 65187517Sgonzostatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 66187517Sgonzostatic s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw); 67187517Sgonzostatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 68187517Sgonzo u16 *speed, u16 *duplex); 69187517Sgonzostatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 70187517Sgonzostatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 71187517Sgonzostatic bool e1000_sgmii_active_82575(struct e1000_hw *hw); 72187517Sgonzostatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 73187517Sgonzostatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 74232847Sgonzostatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 75187517Sgonzo 76187517Sgonzo 77187517Sgonzostruct e1000_dev_spec_82575 { 78187517Sgonzo bool sgmii_active; 79187517Sgonzo}; 80187517Sgonzo 81187517Sgonzo/** 82187517Sgonzo * e1000_init_phy_params_82575 - Init PHY func ptrs. 83192822Sgonzo * @hw: pointer to the HW structure 84192822Sgonzo * 85187517Sgonzo * This is a function pointer entry point called by the api module. 86192822Sgonzo **/ 87187517Sgonzostatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 88187517Sgonzo{ 89187517Sgonzo struct e1000_phy_info *phy = &hw->phy; 90187517Sgonzo s32 ret_val = E1000_SUCCESS; 91187517Sgonzo 92187517Sgonzo DEBUGFUNC("e1000_init_phy_params_82575"); 93187517Sgonzo 94192822Sgonzo if (hw->phy.media_type != e1000_media_type_copper) { 95192822Sgonzo phy->type = e1000_phy_none; 96187517Sgonzo goto out; 97187517Sgonzo } else { 98192822Sgonzo phy->ops.power_up = e1000_power_up_phy_copper; 99187517Sgonzo phy->ops.power_down = e1000_power_down_phy_copper_82575; 100187517Sgonzo } 101187517Sgonzo 102187517Sgonzo phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 103187517Sgonzo phy->reset_delay_us = 100; 104187517Sgonzo 105187517Sgonzo phy->ops.acquire = e1000_acquire_phy_82575; 106187517Sgonzo phy->ops.check_reset_block = e1000_check_reset_block_generic; 107187517Sgonzo phy->ops.commit = e1000_phy_sw_reset_generic; 108257338Snwhitehorn phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 109187517Sgonzo phy->ops.release = e1000_release_phy_82575; 110187517Sgonzo 111187517Sgonzo if (e1000_sgmii_active_82575(hw)) { 112187517Sgonzo phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 113187517Sgonzo phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 114187517Sgonzo phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 115187517Sgonzo } else { 116187517Sgonzo phy->ops.reset = e1000_phy_hw_reset_generic; 117187517Sgonzo phy->ops.read_reg = e1000_read_phy_reg_igp; 118191837Sgonzo phy->ops.write_reg = e1000_write_phy_reg_igp; 119191837Sgonzo } 120191837Sgonzo 121191837Sgonzo /* Set phy->phy_addr and phy->id. */ 122191837Sgonzo ret_val = e1000_get_phy_id_82575(hw); 123191837Sgonzo 124191837Sgonzo /* Verify phy id and set remaining function pointers */ 125191837Sgonzo switch (phy->id) { 126191837Sgonzo case M88E1111_I_PHY_ID: 127191837Sgonzo phy->type = e1000_phy_m88; 128187517Sgonzo phy->ops.check_polarity = e1000_check_polarity_m88; 129187517Sgonzo phy->ops.get_info = e1000_get_phy_info_m88; 130187517Sgonzo phy->ops.get_cable_length = e1000_get_cable_length_m88; 131187517Sgonzo phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 132187517Sgonzo break; 133187517Sgonzo case IGP03E1000_E_PHY_ID: 134187517Sgonzo phy->type = e1000_phy_igp_3; 135187517Sgonzo phy->ops.check_polarity = e1000_check_polarity_igp; 136187517Sgonzo phy->ops.get_info = e1000_get_phy_info_igp; 137187517Sgonzo phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 138187517Sgonzo phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 139187517Sgonzo phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 140187517Sgonzo phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 141187517Sgonzo break; 142187517Sgonzo default: 143232847Sgonzo ret_val = -E1000_ERR_PHY; 144187517Sgonzo goto out; 145187517Sgonzo } 146187517Sgonzo 147187517Sgonzoout: 148187517Sgonzo return ret_val; 149187517Sgonzo} 150187517Sgonzo 151187517Sgonzo/** 152187517Sgonzo * e1000_init_nvm_params_82575 - Init NVM func ptrs. 153232847Sgonzo * @hw: pointer to the HW structure 154232847Sgonzo * 155232847Sgonzo * This is a function pointer entry point called by the api module. 156232847Sgonzo **/ 157232847Sgonzostatic s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 158232847Sgonzo{ 159187517Sgonzo struct e1000_nvm_info *nvm = &hw->nvm; 160187517Sgonzo u32 eecd = E1000_READ_REG(hw, E1000_EECD); 161187517Sgonzo u16 size; 162187517Sgonzo 163187517Sgonzo DEBUGFUNC("e1000_init_nvm_params_82575"); 164187517Sgonzo 165187517Sgonzo nvm->opcode_bits = 8; 166187517Sgonzo nvm->delay_usec = 1; 167187517Sgonzo switch (nvm->override) { 168187517Sgonzo case e1000_nvm_override_spi_large: 169187517Sgonzo nvm->page_size = 32; 170187517Sgonzo nvm->address_bits = 16; 171187517Sgonzo break; 172187517Sgonzo case e1000_nvm_override_spi_small: 173187517Sgonzo nvm->page_size = 8; 174187517Sgonzo nvm->address_bits = 8; 175188883Sgonzo break; 176188883Sgonzo default: 177188883Sgonzo nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 178191837Sgonzo nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 179187517Sgonzo break; 180187517Sgonzo } 181191837Sgonzo 182191837Sgonzo nvm->type = e1000_nvm_eeprom_spi; 183188883Sgonzo 184188883Sgonzo size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 185187517Sgonzo E1000_EECD_SIZE_EX_SHIFT); 186187517Sgonzo 187187517Sgonzo /* 188187517Sgonzo * Added to a constant, "size" becomes the left-shift value 189187517Sgonzo * for setting word_size. 190187517Sgonzo */ 191187517Sgonzo size += NVM_WORD_SIZE_BASE_SHIFT; 192187517Sgonzo 193187517Sgonzo /* EEPROM access above 16k is unsupported */ 194187517Sgonzo if (size > 14) 195187517Sgonzo size = 14; 196187517Sgonzo nvm->word_size = 1 << size; 197187517Sgonzo 198187517Sgonzo /* Function Pointers */ 199187517Sgonzo nvm->ops.acquire = e1000_acquire_nvm_82575; 200187517Sgonzo nvm->ops.read = e1000_read_nvm_eerd; 201187517Sgonzo nvm->ops.release = e1000_release_nvm_82575; 202187517Sgonzo nvm->ops.update = e1000_update_nvm_checksum_generic; 203187517Sgonzo nvm->ops.valid_led_default = e1000_valid_led_default_generic; 204187517Sgonzo nvm->ops.validate = e1000_validate_nvm_checksum_generic; 205187517Sgonzo nvm->ops.write = e1000_write_nvm_spi; 206187517Sgonzo 207188883Sgonzo return E1000_SUCCESS; 208188883Sgonzo} 209188883Sgonzo 210188883Sgonzo/** 211187517Sgonzo * e1000_init_mac_params_82575 - Init MAC func ptrs. 212187517Sgonzo * @hw: pointer to the HW structure 213187517Sgonzo * 214187517Sgonzo * This is a function pointer entry point called by the api module. 215187517Sgonzo **/ 216187517Sgonzostatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 217191837Sgonzo{ 218191837Sgonzo struct e1000_mac_info *mac = &hw->mac; 219191837Sgonzo struct e1000_dev_spec_82575 *dev_spec; 220187517Sgonzo u32 ctrl_ext = 0; 221187517Sgonzo s32 ret_val = E1000_SUCCESS; 222187517Sgonzo 223187517Sgonzo DEBUGFUNC("e1000_init_mac_params_82575"); 224187517Sgonzo 225187517Sgonzo hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575); 226187517Sgonzo 227187517Sgonzo /* Device-specific structure allocation */ 228187517Sgonzo ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 229187517Sgonzo if (ret_val) 230187517Sgonzo goto out; 231187517Sgonzo 232187517Sgonzo dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec; 233187517Sgonzo 234187517Sgonzo /* Set media type */ 235187517Sgonzo /* 236187517Sgonzo * The 82575 uses bits 22:23 for link mode. The mode can be changed 237187517Sgonzo * based on the EEPROM. We cannot rely upon device ID. There 238187517Sgonzo * is no distinguishable difference between fiber and internal 239187517Sgonzo * SerDes mode on the 82575. There can be an external PHY attached 240187517Sgonzo * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 241187517Sgonzo */ 242187517Sgonzo hw->phy.media_type = e1000_media_type_copper; 243187517Sgonzo dev_spec->sgmii_active = FALSE; 244187517Sgonzo 245187517Sgonzo ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 246187517Sgonzo if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == 247187517Sgonzo E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { 248187517Sgonzo hw->phy.media_type = e1000_media_type_internal_serdes; 249187517Sgonzo ctrl_ext |= E1000_CTRL_I2C_ENA; 250187517Sgonzo } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { 251187517Sgonzo dev_spec->sgmii_active = TRUE; 252187517Sgonzo ctrl_ext |= E1000_CTRL_I2C_ENA; 253187517Sgonzo } else { 254187517Sgonzo ctrl_ext &= ~E1000_CTRL_I2C_ENA; 255187517Sgonzo } 256187517Sgonzo E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 257187517Sgonzo 258187517Sgonzo /* Set mta register count */ 259187517Sgonzo mac->mta_reg_count = 128; 260187517Sgonzo /* Set rar entry count */ 261187517Sgonzo mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 262187517Sgonzo /* Set if part includes ASF firmware */ 263187517Sgonzo mac->asf_firmware_present = TRUE; 264187517Sgonzo /* Set if manageability features are enabled. */ 265187517Sgonzo mac->arc_subsystem_valid = 266187517Sgonzo (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 267187517Sgonzo ? TRUE : FALSE; 268187517Sgonzo 269187517Sgonzo /* Function pointers */ 270187517Sgonzo 271187517Sgonzo /* bus type/speed/width */ 272187517Sgonzo mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 273187517Sgonzo /* reset */ 274187517Sgonzo mac->ops.reset_hw = e1000_reset_hw_82575; 275187517Sgonzo /* hw initialization */ 276187517Sgonzo mac->ops.init_hw = e1000_init_hw_82575; 277187517Sgonzo /* link setup */ 278187517Sgonzo mac->ops.setup_link = e1000_setup_link_generic; 279187517Sgonzo /* physical interface link setup */ 280187517Sgonzo mac->ops.setup_physical_interface = 281187517Sgonzo (hw->phy.media_type == e1000_media_type_copper) 282187517Sgonzo ? e1000_setup_copper_link_82575 283187517Sgonzo : e1000_setup_fiber_serdes_link_82575; 284187517Sgonzo /* check for link */ 285187517Sgonzo mac->ops.check_for_link = e1000_check_for_link_82575; 286187517Sgonzo /* receive address register setting */ 287187517Sgonzo mac->ops.rar_set = e1000_rar_set_generic; 288187517Sgonzo /* read mac address */ 289187517Sgonzo mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 290187517Sgonzo /* multicast address update */ 291187517Sgonzo mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 292187517Sgonzo /* writing VFTA */ 293187517Sgonzo mac->ops.write_vfta = e1000_write_vfta_generic; 294187517Sgonzo /* clearing VFTA */ 295187517Sgonzo mac->ops.clear_vfta = e1000_clear_vfta_generic; 296187517Sgonzo /* setting MTA */ 297187517Sgonzo mac->ops.mta_set = e1000_mta_set_generic; 298187517Sgonzo /* blink LED */ 299187517Sgonzo mac->ops.blink_led = e1000_blink_led_generic; 300192822Sgonzo /* setup LED */ 301187517Sgonzo mac->ops.setup_led = e1000_setup_led_generic; 302187517Sgonzo /* cleanup LED */ 303187517Sgonzo mac->ops.cleanup_led = e1000_cleanup_led_generic; 304199497Sgonzo /* turn on/off LED */ 305199497Sgonzo mac->ops.led_on = e1000_led_on_generic; 306199497Sgonzo mac->ops.led_off = e1000_led_off_generic; 307199497Sgonzo /* remove device */ 308199497Sgonzo mac->ops.remove_device = e1000_remove_device_generic; 309199497Sgonzo /* clear hardware counters */ 310199497Sgonzo mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 311187517Sgonzo /* link info */ 312187517Sgonzo mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 313187517Sgonzo 314187517Sgonzoout: 315199497Sgonzo return ret_val; 316187517Sgonzo} 317192822Sgonzo 318191837Sgonzo/** 319187517Sgonzo * e1000_init_function_pointers_82575 - Init func ptrs. 320187517Sgonzo * @hw: pointer to the HW structure 321187517Sgonzo * 322187517Sgonzo * The only function explicitly called by the api module to initialize 323187517Sgonzo * all function pointers and parameters. 324187517Sgonzo **/ 325187517Sgonzovoid e1000_init_function_pointers_82575(struct e1000_hw *hw) 326187517Sgonzo{ 327187517Sgonzo DEBUGFUNC("e1000_init_function_pointers_82575"); 328187517Sgonzo 329187517Sgonzo hw->mac.ops.init_params = e1000_init_mac_params_82575; 330187517Sgonzo hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 331187517Sgonzo hw->phy.ops.init_params = e1000_init_phy_params_82575; 332187517Sgonzo} 333187517Sgonzo 334187517Sgonzo/** 335187517Sgonzo * e1000_acquire_phy_82575 - Acquire rights to access PHY 336192822Sgonzo * @hw: pointer to the HW structure 337187517Sgonzo * 338187517Sgonzo * Acquire access rights to the correct PHY. This is a 339187517Sgonzo * function pointer entry point called by the api module. 340187517Sgonzo **/ 341187517Sgonzostatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 342187517Sgonzo{ 343187517Sgonzo u16 mask; 344187517Sgonzo 345187517Sgonzo DEBUGFUNC("e1000_acquire_phy_82575"); 346232847Sgonzo 347187517Sgonzo mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 348187517Sgonzo 349187517Sgonzo return e1000_acquire_swfw_sync_82575(hw, mask); 350187517Sgonzo} 351232847Sgonzo 352233104Sgonzo/** 353187517Sgonzo * e1000_release_phy_82575 - Release rights to access PHY 354187517Sgonzo * @hw: pointer to the HW structure 355187517Sgonzo * 356187517Sgonzo * A wrapper to release access rights to the correct PHY. This is a 357221257Sadrian * function pointer entry point called by the api module. 358221257Sadrian **/ 359221257Sadrianstatic void e1000_release_phy_82575(struct e1000_hw *hw) 360221257Sadrian{ 361221257Sadrian u16 mask; 362249119Sadrian 363249119Sadrian DEBUGFUNC("e1000_release_phy_82575"); 364256174Sadrian 365256174Sadrian mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 366256174Sadrian e1000_release_swfw_sync_82575(hw, mask); 367263228Sadrian} 368221257Sadrian 369263228Sadrian/** 370221257Sadrian * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 371221257Sadrian * @hw: pointer to the HW structure 372221257Sadrian * @offset: register offset to be read 373221257Sadrian * @data: pointer to the read data 374221257Sadrian * 375221257Sadrian * Reads the PHY register at offset using the serial gigabit media independent 376187517Sgonzo * interface and stores the retrieved information in data. 377187517Sgonzo **/ 378232847Sgonzostatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 379233104Sgonzo u16 *data) 380233104Sgonzo{ 381233104Sgonzo struct e1000_phy_info *phy = &hw->phy; 382233318Sgonzo u32 i, i2ccmd = 0; 383233318Sgonzo 384233318Sgonzo DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 385232847Sgonzo 386232847Sgonzo if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 387232847Sgonzo DEBUGOUT1("PHY Address %u is out of range\n", offset); 388232847Sgonzo return -E1000_ERR_PARAM; 389191837Sgonzo } 390263228Sadrian 391199497Sgonzo /* 392187517Sgonzo * Set up Op-code, Phy Address, and register address in the I2CCMD 393187517Sgonzo * register. The MAC will take care of interfacing with the 394187517Sgonzo * PHY to retrieve the desired data. 395232847Sgonzo */ 396199497Sgonzo i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 397187517Sgonzo (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 398187517Sgonzo (E1000_I2CCMD_OPCODE_READ)); 399187517Sgonzo 400187517Sgonzo E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 401187517Sgonzo 402187517Sgonzo /* Poll the ready bit to see if the I2C read completed */ 403187517Sgonzo for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 404187517Sgonzo usec_delay(50); 405187517Sgonzo i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 406187517Sgonzo if (i2ccmd & E1000_I2CCMD_READY) 407187517Sgonzo break; 408187517Sgonzo } 409187517Sgonzo if (!(i2ccmd & E1000_I2CCMD_READY)) { 410187517Sgonzo DEBUGOUT("I2CCMD Read did not complete\n"); 411187517Sgonzo return -E1000_ERR_PHY; 412187517Sgonzo } 413187517Sgonzo if (i2ccmd & E1000_I2CCMD_ERROR) { 414187517Sgonzo DEBUGOUT("I2CCMD Error bit set\n"); 415187517Sgonzo return -E1000_ERR_PHY; 416187517Sgonzo } 417187517Sgonzo 418187517Sgonzo /* Need to byte-swap the 16-bit value. */ 419187517Sgonzo *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 420187517Sgonzo 421187517Sgonzo return E1000_SUCCESS; 422187517Sgonzo} 423187517Sgonzo 424187517Sgonzo/** 425187517Sgonzo * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 426187517Sgonzo * @hw: pointer to the HW structure 427187517Sgonzo * @offset: register offset to write to 428187517Sgonzo * @data: data to write at register offset 429187517Sgonzo * 430187517Sgonzo * Writes the data to PHY register at the offset using the serial gigabit 431187517Sgonzo * media independent interface. 432187517Sgonzo **/ 433187517Sgonzostatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 434187517Sgonzo u16 data) 435187517Sgonzo{ 436187517Sgonzo struct e1000_phy_info *phy = &hw->phy; 437187517Sgonzo u32 i, i2ccmd = 0; 438187517Sgonzo u16 phy_data_swapped; 439187517Sgonzo 440187517Sgonzo DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 441187517Sgonzo 442187517Sgonzo if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 443187517Sgonzo DEBUGOUT1("PHY Address %d is out of range\n", offset); 444187517Sgonzo return -E1000_ERR_PARAM; 445187517Sgonzo } 446212413Savg 447187517Sgonzo /* Swap the data bytes for the I2C interface */ 448187517Sgonzo phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 449187517Sgonzo 450187517Sgonzo /* 451187517Sgonzo * Set up Op-code, Phy Address, and register address in the I2CCMD 452187517Sgonzo * register. The MAC will take care of interfacing with the 453187517Sgonzo * PHY to retrieve the desired data. 454187517Sgonzo */ 455187517Sgonzo i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 456187517Sgonzo (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 457187517Sgonzo E1000_I2CCMD_OPCODE_WRITE | 458187517Sgonzo phy_data_swapped); 459187517Sgonzo 460187517Sgonzo E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 461187517Sgonzo 462187517Sgonzo /* Poll the ready bit to see if the I2C read completed */ 463187517Sgonzo for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 464187517Sgonzo usec_delay(50); 465187517Sgonzo i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 466187517Sgonzo if (i2ccmd & E1000_I2CCMD_READY) 467187517Sgonzo break; 468187517Sgonzo } 469187517Sgonzo if (!(i2ccmd & E1000_I2CCMD_READY)) { 470187517Sgonzo DEBUGOUT("I2CCMD Write did not complete\n"); 471187517Sgonzo return -E1000_ERR_PHY; 472187517Sgonzo } 473187517Sgonzo if (i2ccmd & E1000_I2CCMD_ERROR) { 474187517Sgonzo DEBUGOUT("I2CCMD Error bit set\n"); 475187517Sgonzo return -E1000_ERR_PHY; 476187517Sgonzo } 477187517Sgonzo 478187517Sgonzo return E1000_SUCCESS; 479187517Sgonzo} 480187517Sgonzo 481187517Sgonzo/** 482263279Sadrian * e1000_get_phy_id_82575 - Retrieve PHY addr and id 483263279Sadrian * @hw: pointer to the HW structure 484263279Sadrian * 485263279Sadrian * Retrieves the PHY address and ID for both PHY's which do and do not use 486263279Sadrian * sgmi interface. 487263279Sadrian **/ 488263279Sadrianstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 489263279Sadrian{ 490263279Sadrian struct e1000_phy_info *phy = &hw->phy; 491263279Sadrian s32 ret_val = E1000_SUCCESS; 492263279Sadrian u16 phy_id; 493263279Sadrian 494263279Sadrian DEBUGFUNC("e1000_get_phy_id_82575"); 495263279Sadrian 496263279Sadrian /* 497263279Sadrian * For SGMII PHYs, we try the list of possible addresses until 498263279Sadrian * we find one that works. For non-SGMII PHYs 499263279Sadrian * (e.g. integrated copper PHYs), an address of 1 should 500263279Sadrian * work. The result of this function should mean phy->phy_addr 501263279Sadrian * and phy->id are set correctly. 502263279Sadrian */ 503263279Sadrian if (!(e1000_sgmii_active_82575(hw))) { 504263279Sadrian phy->addr = 1; 505263279Sadrian ret_val = e1000_get_phy_id(hw); 506263279Sadrian goto out; 507263279Sadrian } 508263279Sadrian 509263279Sadrian /* 510263279Sadrian * The address field in the I2CCMD register is 3 bits and 0 is invalid. 511263279Sadrian * Therefore, we need to test 1-7 512263279Sadrian */ 513187517Sgonzo for (phy->addr = 1; phy->addr < 8; phy->addr++) { 514187517Sgonzo ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 515187517Sgonzo if (ret_val == E1000_SUCCESS) { 516187517Sgonzo DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 517187517Sgonzo phy_id, 518187517Sgonzo phy->addr); 519187517Sgonzo /* 520187517Sgonzo * At the time of this writing, The M88 part is 521187517Sgonzo * the only supported SGMII PHY product. 522187517Sgonzo */ 523187517Sgonzo if (phy_id == M88_VENDOR) 524187517Sgonzo break; 525187517Sgonzo } else { 526187517Sgonzo DEBUGOUT1("PHY address %u was unreadable\n", 527263279Sadrian phy->addr); 528187517Sgonzo } 529227843Smarius } 530187517Sgonzo 531187517Sgonzo /* A valid PHY type couldn't be found. */ 532187517Sgonzo if (phy->addr == 8) { 533187517Sgonzo phy->addr = 0; 534187517Sgonzo ret_val = -E1000_ERR_PHY; 535187517Sgonzo goto out; 536187517Sgonzo } 537187517Sgonzo 538187517Sgonzo ret_val = e1000_get_phy_id(hw); 539187517Sgonzo 540out: 541 return ret_val; 542} 543 544/** 545 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 546 * @hw: pointer to the HW structure 547 * 548 * Resets the PHY using the serial gigabit media independent interface. 549 **/ 550static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 551{ 552 s32 ret_val = E1000_SUCCESS; 553 554 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 555 556 /* 557 * This isn't a true "hard" reset, but is the only reset 558 * available to us at this time. 559 */ 560 561 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 562 563 if (!(hw->phy.ops.write_reg)) 564 goto out; 565 566 /* 567 * SFP documentation requires the following to configure the SPF module 568 * to work on SGMII. No further documentation is given. 569 */ 570 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 571 if (ret_val) 572 goto out; 573 574 ret_val = hw->phy.ops.commit(hw); 575 576out: 577 return ret_val; 578} 579 580/** 581 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 582 * @hw: pointer to the HW structure 583 * @active: TRUE to enable LPLU, FALSE to disable 584 * 585 * Sets the LPLU D0 state according to the active flag. When 586 * activating LPLU this function also disables smart speed 587 * and vice versa. LPLU will not be activated unless the 588 * device autonegotiation advertisement meets standards of 589 * either 10 or 10/100 or 10/100/1000 at all duplexes. 590 * This is a function pointer entry point only called by 591 * PHY setup routines. 592 **/ 593static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 594{ 595 struct e1000_phy_info *phy = &hw->phy; 596 s32 ret_val = E1000_SUCCESS; 597 u16 data; 598 599 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 600 601 if (!(hw->phy.ops.read_reg)) 602 goto out; 603 604 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 605 if (ret_val) 606 goto out; 607 608 if (active) { 609 data |= IGP02E1000_PM_D0_LPLU; 610 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 611 data); 612 if (ret_val) 613 goto out; 614 615 /* When LPLU is enabled, we should disable SmartSpeed */ 616 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 617 &data); 618 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 619 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 620 data); 621 if (ret_val) 622 goto out; 623 } else { 624 data &= ~IGP02E1000_PM_D0_LPLU; 625 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 626 data); 627 /* 628 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 629 * during Dx states where the power conservation is most 630 * important. During driver activity we should enable 631 * SmartSpeed, so performance is maintained. 632 */ 633 if (phy->smart_speed == e1000_smart_speed_on) { 634 ret_val = phy->ops.read_reg(hw, 635 IGP01E1000_PHY_PORT_CONFIG, 636 &data); 637 if (ret_val) 638 goto out; 639 640 data |= IGP01E1000_PSCFR_SMART_SPEED; 641 ret_val = phy->ops.write_reg(hw, 642 IGP01E1000_PHY_PORT_CONFIG, 643 data); 644 if (ret_val) 645 goto out; 646 } else if (phy->smart_speed == e1000_smart_speed_off) { 647 ret_val = phy->ops.read_reg(hw, 648 IGP01E1000_PHY_PORT_CONFIG, 649 &data); 650 if (ret_val) 651 goto out; 652 653 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 654 ret_val = phy->ops.write_reg(hw, 655 IGP01E1000_PHY_PORT_CONFIG, 656 data); 657 if (ret_val) 658 goto out; 659 } 660 } 661 662out: 663 return ret_val; 664} 665 666/** 667 * e1000_acquire_nvm_82575 - Request for access to EEPROM 668 * @hw: pointer to the HW structure 669 * 670 * Acquire the necessary semaphores for exclusive access to the EEPROM. 671 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 672 * Return successful if access grant bit set, else clear the request for 673 * EEPROM access and return -E1000_ERR_NVM (-1). 674 **/ 675static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 676{ 677 s32 ret_val; 678 679 DEBUGFUNC("e1000_acquire_nvm_82575"); 680 681 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 682 if (ret_val) 683 goto out; 684 685 ret_val = e1000_acquire_nvm_generic(hw); 686 687 if (ret_val) 688 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 689 690out: 691 return ret_val; 692} 693 694/** 695 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 696 * @hw: pointer to the HW structure 697 * 698 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 699 * then release the semaphores acquired. 700 **/ 701static void e1000_release_nvm_82575(struct e1000_hw *hw) 702{ 703 DEBUGFUNC("e1000_release_nvm_82575"); 704 705 e1000_release_nvm_generic(hw); 706 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 707} 708 709/** 710 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 711 * @hw: pointer to the HW structure 712 * @mask: specifies which semaphore to acquire 713 * 714 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 715 * will also specify which port we're acquiring the lock for. 716 **/ 717static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 718{ 719 u32 swfw_sync; 720 u32 swmask = mask; 721 u32 fwmask = mask << 16; 722 s32 ret_val = E1000_SUCCESS; 723 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 724 725 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 726 727 while (i < timeout) { 728 if (e1000_get_hw_semaphore_generic(hw)) { 729 ret_val = -E1000_ERR_SWFW_SYNC; 730 goto out; 731 } 732 733 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 734 if (!(swfw_sync & (fwmask | swmask))) 735 break; 736 737 /* 738 * Firmware currently using resource (fwmask) 739 * or other software thread using resource (swmask) 740 */ 741 e1000_put_hw_semaphore_generic(hw); 742 msec_delay_irq(5); 743 i++; 744 } 745 746 if (i == timeout) { 747 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 748 ret_val = -E1000_ERR_SWFW_SYNC; 749 goto out; 750 } 751 752 swfw_sync |= swmask; 753 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 754 755 e1000_put_hw_semaphore_generic(hw); 756 757out: 758 return ret_val; 759} 760 761/** 762 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 763 * @hw: pointer to the HW structure 764 * @mask: specifies which semaphore to acquire 765 * 766 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 767 * will also specify which port we're releasing the lock for. 768 **/ 769static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 770{ 771 u32 swfw_sync; 772 773 DEBUGFUNC("e1000_release_swfw_sync_82575"); 774 775 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 776 /* Empty */ 777 778 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 779 swfw_sync &= ~mask; 780 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 781 782 e1000_put_hw_semaphore_generic(hw); 783} 784 785/** 786 * e1000_get_cfg_done_82575 - Read config done bit 787 * @hw: pointer to the HW structure 788 * 789 * Read the management control register for the config done bit for 790 * completion status. NOTE: silicon which is EEPROM-less will fail trying 791 * to read the config done bit, so an error is *ONLY* logged and returns 792 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 793 * would not be able to be reset or change link. 794 **/ 795static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 796{ 797 s32 timeout = PHY_CFG_TIMEOUT; 798 s32 ret_val = E1000_SUCCESS; 799 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 800 801 DEBUGFUNC("e1000_get_cfg_done_82575"); 802 803 if (hw->bus.func == 1) 804 mask = E1000_NVM_CFG_DONE_PORT_1; 805 806 while (timeout) { 807 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 808 break; 809 msec_delay(1); 810 timeout--; 811 } 812 if (!timeout) { 813 DEBUGOUT("MNG configuration cycle has not completed.\n"); 814 } 815 816 /* If EEPROM is not marked present, init the PHY manually */ 817 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 818 (hw->phy.type == e1000_phy_igp_3)) { 819 e1000_phy_init_script_igp3(hw); 820 } 821 822 return ret_val; 823} 824 825/** 826 * e1000_get_link_up_info_82575 - Get link speed/duplex info 827 * @hw: pointer to the HW structure 828 * @speed: stores the current speed 829 * @duplex: stores the current duplex 830 * 831 * This is a wrapper function, if using the serial gigabit media independent 832 * interface, use PCS to retrieve the link speed and duplex information. 833 * Otherwise, use the generic function to get the link speed and duplex info. 834 **/ 835static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 836 u16 *duplex) 837{ 838 s32 ret_val; 839 840 DEBUGFUNC("e1000_get_link_up_info_82575"); 841 842 if (hw->phy.media_type != e1000_media_type_copper || 843 e1000_sgmii_active_82575(hw)) { 844 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 845 duplex); 846 } else { 847 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 848 duplex); 849 } 850 851 return ret_val; 852} 853 854/** 855 * e1000_check_for_link_82575 - Check for link 856 * @hw: pointer to the HW structure 857 * 858 * If sgmii is enabled, then use the pcs register to determine link, otherwise 859 * use the generic interface for determining link. 860 **/ 861static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 862{ 863 s32 ret_val; 864 u16 speed, duplex; 865 866 DEBUGFUNC("e1000_check_for_link_82575"); 867 868 /* SGMII link check is done through the PCS register. */ 869 if ((hw->phy.media_type != e1000_media_type_copper) || 870 (e1000_sgmii_active_82575(hw))) 871 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 872 &duplex); 873 else 874 ret_val = e1000_check_for_copper_link_generic(hw); 875 876 return ret_val; 877} 878 879/** 880 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 881 * @hw: pointer to the HW structure 882 * @speed: stores the current speed 883 * @duplex: stores the current duplex 884 * 885 * Using the physical coding sub-layer (PCS), retrieve the current speed and 886 * duplex, then store the values in the pointers provided. 887 **/ 888static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 889 u16 *speed, u16 *duplex) 890{ 891 struct e1000_mac_info *mac = &hw->mac; 892 u32 pcs; 893 894 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 895 896 /* Set up defaults for the return values of this function */ 897 mac->serdes_has_link = FALSE; 898 *speed = 0; 899 *duplex = 0; 900 901 /* 902 * Read the PCS Status register for link state. For non-copper mode, 903 * the status register is not accurate. The PCS status register is 904 * used instead. 905 */ 906 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 907 908 /* 909 * The link up bit determines when link is up on autoneg. The sync ok 910 * gets set once both sides sync up and agree upon link. Stable link 911 * can be determined by checking for both link up and link sync ok 912 */ 913 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 914 mac->serdes_has_link = TRUE; 915 916 /* Detect and store PCS speed */ 917 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 918 *speed = SPEED_1000; 919 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 920 *speed = SPEED_100; 921 } else { 922 *speed = SPEED_10; 923 } 924 925 /* Detect and store PCS duplex */ 926 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 927 *duplex = FULL_DUPLEX; 928 } else { 929 *duplex = HALF_DUPLEX; 930 } 931 } 932 933 return E1000_SUCCESS; 934} 935 936/** 937 * e1000_reset_hw_82575 - Reset hardware 938 * @hw: pointer to the HW structure 939 * 940 * This resets the hardware into a known state. This is a 941 * function pointer entry point called by the api module. 942 **/ 943static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 944{ 945 u32 ctrl, icr; 946 s32 ret_val; 947 948 DEBUGFUNC("e1000_reset_hw_82575"); 949 950 /* 951 * Prevent the PCI-E bus from sticking if there is no TLP connection 952 * on the last TLP read/write transaction when MAC is reset. 953 */ 954 ret_val = e1000_disable_pcie_master_generic(hw); 955 if (ret_val) { 956 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 957 } 958 959 DEBUGOUT("Masking off all interrupts\n"); 960 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 961 962 E1000_WRITE_REG(hw, E1000_RCTL, 0); 963 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 964 E1000_WRITE_FLUSH(hw); 965 966 msec_delay(10); 967 968 ctrl = E1000_READ_REG(hw, E1000_CTRL); 969 970 DEBUGOUT("Issuing a global reset to MAC\n"); 971 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 972 973 ret_val = e1000_get_auto_rd_done_generic(hw); 974 if (ret_val) { 975 /* 976 * When auto config read does not complete, do not 977 * return with an error. This can happen in situations 978 * where there is no eeprom and prevents getting link. 979 */ 980 DEBUGOUT("Auto Read Done did not complete\n"); 981 } 982 983 /* If EEPROM is not present, run manual init scripts */ 984 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 985 e1000_reset_init_script_82575(hw); 986 987 /* Clear any pending interrupt events. */ 988 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 989 icr = E1000_READ_REG(hw, E1000_ICR); 990 991 e1000_check_alt_mac_addr_generic(hw); 992 993 return ret_val; 994} 995 996/** 997 * e1000_init_hw_82575 - Initialize hardware 998 * @hw: pointer to the HW structure 999 * 1000 * This inits the hardware readying it for operation. 1001 **/ 1002static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1003{ 1004 struct e1000_mac_info *mac = &hw->mac; 1005 s32 ret_val; 1006 u16 i, rar_count = mac->rar_entry_count; 1007 1008 DEBUGFUNC("e1000_init_hw_82575"); 1009 1010 /* Initialize identification LED */ 1011 ret_val = e1000_id_led_init_generic(hw); 1012 if (ret_val) { 1013 DEBUGOUT("Error initializing identification LED\n"); 1014 /* This is not fatal and we should not stop init due to this */ 1015 } 1016 1017 /* Disabling VLAN filtering */ 1018 DEBUGOUT("Initializing the IEEE VLAN\n"); 1019 mac->ops.clear_vfta(hw); 1020 1021 /* Setup the receive address */ 1022 e1000_init_rx_addrs_generic(hw, rar_count); 1023 /* Zero out the Multicast HASH table */ 1024 DEBUGOUT("Zeroing the MTA\n"); 1025 for (i = 0; i < mac->mta_reg_count; i++) 1026 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1027 1028 /* Setup link and flow control */ 1029 ret_val = mac->ops.setup_link(hw); 1030 1031 /* 1032 * Clear all of the statistics registers (clear on read). It is 1033 * important that we do this after we have tried to establish link 1034 * because the symbol error count will increment wildly if there 1035 * is no link. 1036 */ 1037 e1000_clear_hw_cntrs_82575(hw); 1038 1039 return ret_val; 1040} 1041 1042/** 1043 * e1000_setup_copper_link_82575 - Configure copper link settings 1044 * @hw: pointer to the HW structure 1045 * 1046 * Configures the link for auto-neg or forced speed and duplex. Then we check 1047 * for link, once link is established calls to configure collision distance 1048 * and flow control are called. 1049 **/ 1050static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1051{ 1052 u32 ctrl, led_ctrl; 1053 s32 ret_val; 1054 bool link; 1055 1056 DEBUGFUNC("e1000_setup_copper_link_82575"); 1057 1058 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1059 ctrl |= E1000_CTRL_SLU; 1060 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1061 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1062 1063 switch (hw->phy.type) { 1064 case e1000_phy_m88: 1065 ret_val = e1000_copper_link_setup_m88(hw); 1066 break; 1067 case e1000_phy_igp_3: 1068 ret_val = e1000_copper_link_setup_igp(hw); 1069 /* Setup activity LED */ 1070 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1071 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1072 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1073 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1074 break; 1075 default: 1076 ret_val = -E1000_ERR_PHY; 1077 break; 1078 } 1079 1080 if (ret_val) 1081 goto out; 1082 1083 if (hw->mac.autoneg) { 1084 /* 1085 * Setup autoneg and flow control advertisement 1086 * and perform autonegotiation. 1087 */ 1088 ret_val = e1000_copper_link_autoneg(hw); 1089 if (ret_val) 1090 goto out; 1091 } else { 1092 /* 1093 * PHY will be set to 10H, 10F, 100H or 100F 1094 * depending on user settings. 1095 */ 1096 DEBUGOUT("Forcing Speed and Duplex\n"); 1097 ret_val = hw->phy.ops.force_speed_duplex(hw); 1098 if (ret_val) { 1099 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1100 goto out; 1101 } 1102 } 1103 1104 ret_val = e1000_configure_pcs_link_82575(hw); 1105 if (ret_val) 1106 goto out; 1107 1108 /* 1109 * Check link status. Wait up to 100 microseconds for link to become 1110 * valid. 1111 */ 1112 ret_val = e1000_phy_has_link_generic(hw, 1113 COPPER_LINK_UP_LIMIT, 1114 10, 1115 &link); 1116 if (ret_val) 1117 goto out; 1118 1119 if (link) { 1120 DEBUGOUT("Valid link established!!!\n"); 1121 /* Config the MAC and PHY after link is up */ 1122 e1000_config_collision_dist_generic(hw); 1123 ret_val = e1000_config_fc_after_link_up_generic(hw); 1124 } else { 1125 DEBUGOUT("Unable to establish link!!!\n"); 1126 } 1127 1128out: 1129 return ret_val; 1130} 1131 1132/** 1133 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes 1134 * @hw: pointer to the HW structure 1135 * 1136 * Configures speed and duplex for fiber and serdes links. 1137 **/ 1138static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw) 1139{ 1140 u32 reg; 1141 1142 DEBUGFUNC("e1000_setup_fiber_serdes_link_82575"); 1143 1144 /* 1145 * On the 82575, SerDes loopback mode persists until it is 1146 * explicitly turned off or a power cycle is performed. A read to 1147 * the register does not indicate its status. Therefore, we ensure 1148 * loopback mode is disabled during initialization. 1149 */ 1150 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1151 1152 /* Force link up, set 1gb, set both sw defined pins */ 1153 reg = E1000_READ_REG(hw, E1000_CTRL); 1154 reg |= E1000_CTRL_SLU | 1155 E1000_CTRL_SPD_1000 | 1156 E1000_CTRL_FRCSPD | 1157 E1000_CTRL_SWDPIN0 | 1158 E1000_CTRL_SWDPIN1; 1159 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1160 1161 /* Set switch control to serdes energy detect */ 1162 reg = E1000_READ_REG(hw, E1000_CONNSW); 1163 reg |= E1000_CONNSW_ENRGSRC; 1164 E1000_WRITE_REG(hw, E1000_CONNSW, reg); 1165 1166 /* 1167 * New SerDes mode allows for forcing speed or autonegotiating speed 1168 * at 1gb. Autoneg should be default set by most drivers. This is the 1169 * mode that will be compatible with older link partners and switches. 1170 * However, both are supported by the hardware and some drivers/tools. 1171 */ 1172 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1173 1174 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1175 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1176 1177 if (hw->mac.autoneg) { 1178 /* Set PCS register for autoneg */ 1179 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1180 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1181 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1182 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1183 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 1184 } else { 1185 /* Set PCS register for forced speed */ 1186 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1187 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1188 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1189 E1000_PCS_LCTL_FSD | /* Force Speed */ 1190 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1191 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); 1192 } 1193 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1194 1195 return E1000_SUCCESS; 1196} 1197 1198/** 1199 * e1000_configure_pcs_link_82575 - Configure PCS link 1200 * @hw: pointer to the HW structure 1201 * 1202 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1203 * only used on copper connections where the serialized gigabit media 1204 * independent interface (sgmii) is being used. Configures the link 1205 * for auto-negotiation or forces speed/duplex. 1206 **/ 1207static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw) 1208{ 1209 struct e1000_mac_info *mac = &hw->mac; 1210 u32 reg = 0; 1211 1212 DEBUGFUNC("e1000_configure_pcs_link_82575"); 1213 1214 if (hw->phy.media_type != e1000_media_type_copper || 1215 !(e1000_sgmii_active_82575(hw))) 1216 goto out; 1217 1218 /* For SGMII, we need to issue a PCS autoneg restart */ 1219 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1220 1221 /* AN time out should be disabled for SGMII mode */ 1222 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1223 1224 if (mac->autoneg) { 1225 /* Make sure forced speed and force link are not set */ 1226 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1227 1228 /* 1229 * The PHY should be setup prior to calling this function. 1230 * All we need to do is restart autoneg and enable autoneg. 1231 */ 1232 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; 1233 } else { 1234 /* Set PCS register for forced speed */ 1235 1236 /* Turn off bits for full duplex, speed, and autoneg */ 1237 reg &= ~(E1000_PCS_LCTL_FSV_1000 | 1238 E1000_PCS_LCTL_FSV_100 | 1239 E1000_PCS_LCTL_FDV_FULL | 1240 E1000_PCS_LCTL_AN_ENABLE); 1241 1242 /* Check for duplex first */ 1243 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) 1244 reg |= E1000_PCS_LCTL_FDV_FULL; 1245 1246 /* Now set speed */ 1247 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) 1248 reg |= E1000_PCS_LCTL_FSV_100; 1249 1250 /* Force speed and force link */ 1251 reg |= E1000_PCS_LCTL_FSD | 1252 E1000_PCS_LCTL_FORCE_LINK | 1253 E1000_PCS_LCTL_FLV_LINK_UP; 1254 1255 DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n", 1256 reg); 1257 } 1258 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1259 1260out: 1261 return E1000_SUCCESS; 1262} 1263 1264/** 1265 * e1000_sgmii_active_82575 - Return sgmii state 1266 * @hw: pointer to the HW structure 1267 * 1268 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1269 * which can be enabled for use in the embedded applications. Simply 1270 * return the current state of the sgmii interface. 1271 **/ 1272static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1273{ 1274 struct e1000_dev_spec_82575 *dev_spec; 1275 bool ret_val; 1276 1277 DEBUGFUNC("e1000_sgmii_active_82575"); 1278 1279 if (hw->mac.type != e1000_82575) { 1280 ret_val = FALSE; 1281 goto out; 1282 } 1283 1284 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec; 1285 1286 ret_val = dev_spec->sgmii_active; 1287 1288out: 1289 return ret_val; 1290} 1291 1292/** 1293 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1294 * @hw: pointer to the HW structure 1295 * 1296 * Inits recommended HW defaults after a reset when there is no EEPROM 1297 * detected. This is only for the 82575. 1298 **/ 1299static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1300{ 1301 DEBUGFUNC("e1000_reset_init_script_82575"); 1302 1303 if (hw->mac.type == e1000_82575) { 1304 DEBUGOUT("Running reset init script for 82575\n"); 1305 /* SerDes configuration via SERDESCTRL */ 1306 e1000_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1307 e1000_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1308 e1000_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); 1309 e1000_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); 1310 1311 /* CCM configuration via CCMCTL register */ 1312 e1000_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); 1313 e1000_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); 1314 1315 /* PCIe lanes configuration */ 1316 e1000_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); 1317 e1000_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); 1318 e1000_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); 1319 e1000_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); 1320 1321 /* PCIe PLL Configuration */ 1322 e1000_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); 1323 e1000_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); 1324 e1000_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); 1325 } 1326 1327 return E1000_SUCCESS; 1328} 1329 1330/** 1331 * e1000_read_mac_addr_82575 - Read device MAC address 1332 * @hw: pointer to the HW structure 1333 **/ 1334static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1335{ 1336 s32 ret_val = E1000_SUCCESS; 1337 1338 DEBUGFUNC("e1000_read_mac_addr_82575"); 1339 if (e1000_check_alt_mac_addr_generic(hw)) 1340 ret_val = e1000_read_mac_addr_generic(hw); 1341 1342 return ret_val; 1343} 1344 1345/** 1346 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1347 * @hw: pointer to the HW structure 1348 * 1349 * In the case of a PHY power down to save power, or to turn off link during a 1350 * driver unload, or wake on lan is not enabled, remove the link. 1351 **/ 1352static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1353{ 1354 struct e1000_phy_info *phy = &hw->phy; 1355 struct e1000_mac_info *mac = &hw->mac; 1356 1357 if (!(phy->ops.check_reset_block)) 1358 return; 1359 1360 /* If the management interface is not enabled, then power down */ 1361 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1362 e1000_power_down_phy_copper(hw); 1363 1364 return; 1365} 1366 1367/** 1368 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1369 * @hw: pointer to the HW structure 1370 * 1371 * Clears the hardware counters by reading the counter registers. 1372 **/ 1373static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1374{ 1375 volatile u32 temp; 1376 1377 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1378 1379 e1000_clear_hw_cntrs_base_generic(hw); 1380 1381 temp = E1000_READ_REG(hw, E1000_PRC64); 1382 temp = E1000_READ_REG(hw, E1000_PRC127); 1383 temp = E1000_READ_REG(hw, E1000_PRC255); 1384 temp = E1000_READ_REG(hw, E1000_PRC511); 1385 temp = E1000_READ_REG(hw, E1000_PRC1023); 1386 temp = E1000_READ_REG(hw, E1000_PRC1522); 1387 temp = E1000_READ_REG(hw, E1000_PTC64); 1388 temp = E1000_READ_REG(hw, E1000_PTC127); 1389 temp = E1000_READ_REG(hw, E1000_PTC255); 1390 temp = E1000_READ_REG(hw, E1000_PTC511); 1391 temp = E1000_READ_REG(hw, E1000_PTC1023); 1392 temp = E1000_READ_REG(hw, E1000_PTC1522); 1393 1394 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1395 temp = E1000_READ_REG(hw, E1000_RXERRC); 1396 temp = E1000_READ_REG(hw, E1000_TNCRS); 1397 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1398 temp = E1000_READ_REG(hw, E1000_TSCTC); 1399 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1400 1401 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1402 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1403 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1404 1405 temp = E1000_READ_REG(hw, E1000_IAC); 1406 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1407 1408 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1409 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1410 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1411 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1412 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1413 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1414 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1415 1416 temp = E1000_READ_REG(hw, E1000_CBTMPC); 1417 temp = E1000_READ_REG(hw, E1000_HTDPMC); 1418 temp = E1000_READ_REG(hw, E1000_CBRMPC); 1419 temp = E1000_READ_REG(hw, E1000_RPTHC); 1420 temp = E1000_READ_REG(hw, E1000_HGPTC); 1421 temp = E1000_READ_REG(hw, E1000_HTCBDPC); 1422 temp = E1000_READ_REG(hw, E1000_HGORCL); 1423 temp = E1000_READ_REG(hw, E1000_HGORCH); 1424 temp = E1000_READ_REG(hw, E1000_HGOTCL); 1425 temp = E1000_READ_REG(hw, E1000_HGOTCH); 1426 temp = E1000_READ_REG(hw, E1000_LENERRS); 1427 1428 /* This register should not be read in copper configurations */ 1429 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1430 temp = E1000_READ_REG(hw, E1000_SCVPC); 1431} 1432