1133819Stjr/****************************************************************************** 2133819Stjr 3133819Stjr Copyright (c) 2001-2015, Intel Corporation 4133819Stjr All rights reserved. 5133819Stjr 6255676Srdivacky Redistribution and use in source and binary forms, with or without 7133819Stjr modification, are permitted provided that the following conditions are met: 8133819Stjr 9133819Stjr 1. Redistributions of source code must retain the above copyright notice, 10133819Stjr this list of conditions and the following disclaimer. 11133819Stjr 12133819Stjr 2. Redistributions in binary form must reproduce the above copyright 13133819Stjr notice, this list of conditions and the following disclaimer in the 14177999Skib documentation and/or other materials provided with the distribution. 15227776Slstewart 16164199Sru 3. Neither the name of the Intel Corporation nor the names of its 17133819Stjr contributors may be used to endorse or promote products derived from 18255673Srdivacky this software without specific prior written permission. 19133819Stjr 20161330Sjhb THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21161330Sjhb AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22133819Stjr IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23133819Stjr ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24133819Stjr LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25133819Stjr CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26133819Stjr SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27133819Stjr INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28133819Stjr CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29133819Stjr ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30133819Stjr POSSIBILITY OF SUCH DAMAGE. 31133819Stjr 32133819Stjr******************************************************************************/ 33133819Stjr/*$FreeBSD: releng/11.0/sys/dev/e1000/e1000_82575.c 300050 2016-05-17 12:52:31Z eadler $*/ 34133819Stjr 35133819Stjr/* 36133819Stjr * 82575EB Gigabit Network Connection 37143198Ssobomax * 82575EB Gigabit Backplane Connection 38133819Stjr * 82575GB Gigabit Network Connection 39133819Stjr * 82576 Gigabit Network Connection 40133819Stjr * 82576 Quad Port Gigabit Mezzanine Adapter 41133819Stjr * 82580 Gigabit Network Connection 42133819Stjr * I350 Gigabit Network Connection 43133819Stjr */ 44133819Stjr 45133819Stjr#include "e1000_api.h" 46133819Stjr#include "e1000_i210.h" 47133819Stjr 48133819Stjrstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 49133819Stjrstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 50133819Stjrstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 51133819Stjrstatic void e1000_release_phy_82575(struct e1000_hw *hw); 52133819Stjrstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 53133819Stjrstatic void e1000_release_nvm_82575(struct e1000_hw *hw); 54133819Stjrstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw); 55133819Stjrstatic s32 e1000_check_for_link_media_swap(struct e1000_hw *hw); 56133819Stjrstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 57133819Stjrstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 58133819Stjr u16 *duplex); 59133819Stjrstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 60133819Stjrstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 61133819Stjr u16 *data); 62133819Stjrstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw); 63133819Stjrstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw); 64236027Sedstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 65236027Sed u32 offset, u16 *data); 66133819Stjrstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 67133819Stjr u32 offset, u16 data); 68133819Stjrstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 69133819Stjr bool active); 70133819Stjrstatic s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 71133819Stjr bool active); 72133819Stjrstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 73133819Stjr bool active); 74133819Stjrstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 75133819Stjrstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 76133819Stjrstatic s32 e1000_get_media_type_82575(struct e1000_hw *hw); 77133819Stjrstatic s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw); 78133819Stjrstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 79133819Stjrstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 80133819Stjr u32 offset, u16 data); 81133819Stjrstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 82133819Stjrstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 83133819Stjrstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 84133819Stjr u16 *speed, u16 *duplex); 85133819Stjrstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 86133819Stjrstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 87156919Snetchildstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw); 88156919Snetchildstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 89156919Snetchildstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 90156919Snetchildstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw); 91133819Stjrstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 92133819Stjrstatic void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 93133819Stjrstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 94133819Stjrstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 95133819Stjrstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 96133819Stjrstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 97133819Stjrstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 98133819Stjrstatic s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 99133819Stjr u16 offset); 100133819Stjrstatic s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 101133819Stjr u16 offset); 102133819Stjrstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 103133819Stjrstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 104133819Stjrstatic void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 105133819Stjrstatic void e1000_clear_vfta_i350(struct e1000_hw *hw); 106133819Stjr 107133819Stjrstatic void e1000_i2c_start(struct e1000_hw *hw); 108133819Stjrstatic void e1000_i2c_stop(struct e1000_hw *hw); 109133819Stjrstatic s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data); 110133819Stjrstatic s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data); 111133819Stjrstatic s32 e1000_get_i2c_ack(struct e1000_hw *hw); 112133819Stjrstatic s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data); 113133819Stjrstatic s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data); 114133819Stjrstatic void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 115133819Stjrstatic void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 116133819Stjrstatic s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 117133819Stjrstatic bool e1000_get_i2c_data(u32 *i2cctl); 118133819Stjr 119133819Stjrstatic const u16 e1000_82580_rxpbs_table[] = { 120133819Stjr 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 121133819Stjr#define E1000_82580_RXPBS_TABLE_SIZE \ 122133819Stjr (sizeof(e1000_82580_rxpbs_table) / \ 123133819Stjr sizeof(e1000_82580_rxpbs_table[0])) 124133819Stjr 125133819Stjr 126133819Stjr/** 127133819Stjr * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 128133819Stjr * @hw: pointer to the HW structure 129133819Stjr * 130133819Stjr * Called to determine if the I2C pins are being used for I2C or as an 131133819Stjr * external MDIO interface since the two options are mutually exclusive. 132133819Stjr **/ 133133819Stjrstatic bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 134133819Stjr{ 135133819Stjr u32 reg = 0; 136227692Sed bool ext_mdio = FALSE; 137133819Stjr 138133819Stjr DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 139133819Stjr 140133819Stjr switch (hw->mac.type) { 141133819Stjr case e1000_82575: 142133819Stjr case e1000_82576: 143133819Stjr reg = E1000_READ_REG(hw, E1000_MDIC); 144133819Stjr ext_mdio = !!(reg & E1000_MDIC_DEST); 145133819Stjr break; 146133819Stjr case e1000_82580: 147133819Stjr case e1000_i350: 148133819Stjr case e1000_i354: 149133819Stjr case e1000_i210: 150133819Stjr case e1000_i211: 151133819Stjr reg = E1000_READ_REG(hw, E1000_MDICNFG); 152133819Stjr ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 153133819Stjr break; 154133819Stjr default: 155133819Stjr break; 156133819Stjr } 157234354Sjkim return ext_mdio; 158133819Stjr} 159133819Stjr 160133819Stjr/** 161133819Stjr * e1000_init_phy_params_82575 - Init PHY func ptrs. 162133819Stjr * @hw: pointer to the HW structure 163133819Stjr **/ 164133819Stjrstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 165133819Stjr{ 166133819Stjr struct e1000_phy_info *phy = &hw->phy; 167133819Stjr s32 ret_val = E1000_SUCCESS; 168133819Stjr u32 ctrl_ext; 169133819Stjr 170133819Stjr DEBUGFUNC("e1000_init_phy_params_82575"); 171133819Stjr 172133819Stjr phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; 173133819Stjr phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; 174133819Stjr 175133819Stjr if (hw->phy.media_type != e1000_media_type_copper) { 176133819Stjr phy->type = e1000_phy_none; 177133819Stjr goto out; 178133819Stjr } 179133819Stjr 180133819Stjr phy->ops.power_up = e1000_power_up_phy_copper; 181133819Stjr phy->ops.power_down = e1000_power_down_phy_copper_82575; 182133819Stjr 183133819Stjr phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 184133819Stjr phy->reset_delay_us = 100; 185133819Stjr 186133819Stjr phy->ops.acquire = e1000_acquire_phy_82575; 187133819Stjr phy->ops.check_reset_block = e1000_check_reset_block_generic; 188133819Stjr phy->ops.commit = e1000_phy_sw_reset_generic; 189133819Stjr phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 190133819Stjr phy->ops.release = e1000_release_phy_82575; 191133819Stjr 192133819Stjr ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 193133819Stjr 194133819Stjr if (e1000_sgmii_active_82575(hw)) { 195133819Stjr phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 196133819Stjr ctrl_ext |= E1000_CTRL_I2C_ENA; 197133819Stjr } else { 198133819Stjr phy->ops.reset = e1000_phy_hw_reset_generic; 199133819Stjr ctrl_ext &= ~E1000_CTRL_I2C_ENA; 200133819Stjr } 201133819Stjr 202161309Snetchild E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 203161309Snetchild e1000_reset_mdicnfg_82580(hw); 204161309Snetchild 205133819Stjr if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 206133819Stjr phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 207133819Stjr phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 208133819Stjr } else { 209133819Stjr switch (hw->mac.type) { 210133819Stjr case e1000_82580: 211133819Stjr case e1000_i350: 212133819Stjr case e1000_i354: 213133819Stjr phy->ops.read_reg = e1000_read_phy_reg_82580; 214133819Stjr phy->ops.write_reg = e1000_write_phy_reg_82580; 215133819Stjr break; 216133819Stjr case e1000_i210: 217133819Stjr case e1000_i211: 218133819Stjr phy->ops.read_reg = e1000_read_phy_reg_gs40g; 219133819Stjr phy->ops.write_reg = e1000_write_phy_reg_gs40g; 220133819Stjr break; 221133819Stjr default: 222133819Stjr phy->ops.read_reg = e1000_read_phy_reg_igp; 223133819Stjr phy->ops.write_reg = e1000_write_phy_reg_igp; 224133819Stjr } 225133819Stjr } 226133819Stjr 227133819Stjr /* Set phy->phy_addr and phy->id. */ 228133819Stjr ret_val = e1000_get_phy_id_82575(hw); 229133819Stjr 230133819Stjr /* Verify phy id and set remaining function pointers */ 231133819Stjr switch (phy->id) { 232156843Snetchild case M88E1543_E_PHY_ID: 233156843Snetchild case M88E1512_E_PHY_ID: 234156843Snetchild case I347AT4_E_PHY_ID: 235156843Snetchild case M88E1112_E_PHY_ID: 236133819Stjr case M88E1340M_E_PHY_ID: 237133819Stjr case M88E1111_I_PHY_ID: 238133819Stjr phy->type = e1000_phy_m88; 239133819Stjr phy->ops.check_polarity = e1000_check_polarity_m88; 240133819Stjr phy->ops.get_info = e1000_get_phy_info_m88; 241133819Stjr if (phy->id == I347AT4_E_PHY_ID || 242133819Stjr phy->id == M88E1112_E_PHY_ID || 243133819Stjr phy->id == M88E1340M_E_PHY_ID) 244133819Stjr phy->ops.get_cable_length = 245133819Stjr e1000_get_cable_length_m88_gen2; 246133819Stjr else if (phy->id == M88E1543_E_PHY_ID || 247133819Stjr phy->id == M88E1512_E_PHY_ID) 248133819Stjr phy->ops.get_cable_length = 249133819Stjr e1000_get_cable_length_m88_gen2; 250133819Stjr else 251133819Stjr phy->ops.get_cable_length = e1000_get_cable_length_m88; 252133819Stjr phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 253133819Stjr /* Check if this PHY is confgured for media swap. */ 254133819Stjr if (phy->id == M88E1112_E_PHY_ID) { 255133819Stjr u16 data; 256133819Stjr 257133819Stjr ret_val = phy->ops.write_reg(hw, 258133819Stjr E1000_M88E1112_PAGE_ADDR, 259133819Stjr 2); 260133819Stjr if (ret_val) 261133819Stjr goto out; 262133819Stjr 263133819Stjr ret_val = phy->ops.read_reg(hw, 264133819Stjr E1000_M88E1112_MAC_CTRL_1, 265133819Stjr &data); 266133819Stjr if (ret_val) 267133819Stjr goto out; 268133819Stjr 269133819Stjr data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 270133819Stjr E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 271156919Snetchild if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 272156843Snetchild data == E1000_M88E1112_AUTO_COPPER_BASEX) 273156919Snetchild hw->mac.ops.check_for_link = 274156843Snetchild e1000_check_for_link_media_swap; 275133819Stjr } 276133819Stjr if (phy->id == M88E1512_E_PHY_ID) { 277133819Stjr ret_val = e1000_initialize_M88E1512_phy(hw); 278133819Stjr if (ret_val) 279133819Stjr goto out; 280133819Stjr } 281133819Stjr if (phy->id == M88E1543_E_PHY_ID) { 282133819Stjr ret_val = e1000_initialize_M88E1543_phy(hw); 283133819Stjr if (ret_val) 284133819Stjr goto out; 285133819Stjr } 286133819Stjr break; 287133819Stjr case IGP03E1000_E_PHY_ID: 288133819Stjr case IGP04E1000_E_PHY_ID: 289133819Stjr phy->type = e1000_phy_igp_3; 290133819Stjr phy->ops.check_polarity = e1000_check_polarity_igp; 291133819Stjr phy->ops.get_info = e1000_get_phy_info_igp; 292133819Stjr phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 293133819Stjr phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 294133819Stjr phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 295133819Stjr phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 296133819Stjr break; 297133819Stjr case I82580_I_PHY_ID: 298156843Snetchild case I350_I_PHY_ID: 299156843Snetchild phy->type = e1000_phy_82580; 300156843Snetchild phy->ops.check_polarity = e1000_check_polarity_82577; 301156843Snetchild phy->ops.force_speed_duplex = 302147142Ssobomax e1000_phy_force_speed_duplex_82577; 303147142Ssobomax phy->ops.get_cable_length = e1000_get_cable_length_82577; 304147142Ssobomax phy->ops.get_info = e1000_get_phy_info_82577; 305147142Ssobomax phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 306133819Stjr phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 307133819Stjr break; 308133819Stjr case I210_I_PHY_ID: 309133819Stjr phy->type = e1000_phy_i210; 310133819Stjr phy->ops.check_polarity = e1000_check_polarity_m88; 311133819Stjr phy->ops.get_info = e1000_get_phy_info_m88; 312133819Stjr phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 313133819Stjr phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 314133819Stjr phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 315133819Stjr phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 316133819Stjr break; 317133819Stjr default: 318133819Stjr ret_val = -E1000_ERR_PHY; 319133819Stjr goto out; 320133819Stjr } 321133819Stjr 322133819Stjrout: 323133819Stjr return ret_val; 324133819Stjr} 325133819Stjr 326133819Stjr/** 327133819Stjr * e1000_init_nvm_params_82575 - Init NVM func ptrs. 328133819Stjr * @hw: pointer to the HW structure 329133819Stjr **/ 330133819Stjrs32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 331133819Stjr{ 332133819Stjr struct e1000_nvm_info *nvm = &hw->nvm; 333133819Stjr u32 eecd = E1000_READ_REG(hw, E1000_EECD); 334133819Stjr u16 size; 335133819Stjr 336133819Stjr DEBUGFUNC("e1000_init_nvm_params_82575"); 337133819Stjr 338133819Stjr size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 339133819Stjr E1000_EECD_SIZE_EX_SHIFT); 340133819Stjr /* 341133819Stjr * Added to a constant, "size" becomes the left-shift value 342133819Stjr * for setting word_size. 343133819Stjr */ 344133819Stjr size += NVM_WORD_SIZE_BASE_SHIFT; 345133819Stjr 346133819Stjr /* Just in case size is out of range, cap it to the largest 347166730Sjkim * EEPROM size supported 348234360Sjkim */ 349166730Sjkim if (size > 15) 350133819Stjr size = 15; 351133819Stjr 352133819Stjr nvm->word_size = 1 << size; 353133819Stjr if (hw->mac.type < e1000_i210) { 354133819Stjr nvm->opcode_bits = 8; 355133819Stjr nvm->delay_usec = 1; 356133819Stjr 357133819Stjr switch (nvm->override) { 358133819Stjr case e1000_nvm_override_spi_large: 359133819Stjr nvm->page_size = 32; 360133819Stjr nvm->address_bits = 16; 361133819Stjr break; 362133819Stjr case e1000_nvm_override_spi_small: 363133819Stjr nvm->page_size = 8; 364133819Stjr nvm->address_bits = 8; 365133819Stjr break; 366133819Stjr default: 367133819Stjr nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 368133819Stjr nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 369133819Stjr 16 : 8; 370133819Stjr break; 371133819Stjr } 372133819Stjr if (nvm->word_size == (1 << 15)) 373133819Stjr nvm->page_size = 128; 374133819Stjr 375133819Stjr nvm->type = e1000_nvm_eeprom_spi; 376133819Stjr } else { 377133819Stjr nvm->type = e1000_nvm_flash_hw; 378133819Stjr } 379161309Snetchild 380218611Sdchagin /* Function Pointers */ 381161309Snetchild nvm->ops.acquire = e1000_acquire_nvm_82575; 382133819Stjr nvm->ops.release = e1000_release_nvm_82575; 383184790Sed if (nvm->word_size < (1 << 15)) 384184790Sed nvm->ops.read = e1000_read_nvm_eerd; 385184790Sed else 386184790Sed nvm->ops.read = e1000_read_nvm_spi; 387133819Stjr 388133819Stjr nvm->ops.write = e1000_write_nvm_spi; 389133819Stjr nvm->ops.validate = e1000_validate_nvm_checksum_generic; 390133819Stjr nvm->ops.update = e1000_update_nvm_checksum_generic; 391133819Stjr nvm->ops.valid_led_default = e1000_valid_led_default_82575; 392133819Stjr 393133819Stjr /* override generic family function pointers for specific descendants */ 394133819Stjr switch (hw->mac.type) { 395133819Stjr case e1000_82580: 396133819Stjr nvm->ops.validate = e1000_validate_nvm_checksum_82580; 397133819Stjr nvm->ops.update = e1000_update_nvm_checksum_82580; 398133819Stjr break; 399133819Stjr case e1000_i350: 400133819Stjr case e1000_i354: 401133819Stjr nvm->ops.validate = e1000_validate_nvm_checksum_i350; 402133819Stjr nvm->ops.update = e1000_update_nvm_checksum_i350; 403133819Stjr break; 404133819Stjr default: 405133819Stjr break; 406133819Stjr } 407133819Stjr 408133819Stjr return E1000_SUCCESS; 409133819Stjr} 410133819Stjr 411133819Stjr/** 412133819Stjr * e1000_init_mac_params_82575 - Init MAC func ptrs. 413133819Stjr * @hw: pointer to the HW structure 414133819Stjr **/ 415133819Stjrstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 416133819Stjr{ 417133819Stjr struct e1000_mac_info *mac = &hw->mac; 418133819Stjr struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 419133819Stjr 420133819Stjr DEBUGFUNC("e1000_init_mac_params_82575"); 421133819Stjr 422133819Stjr /* Derives media type */ 423133819Stjr e1000_get_media_type_82575(hw); 424133819Stjr /* Set mta register count */ 425133819Stjr mac->mta_reg_count = 128; 426133819Stjr /* Set uta register count */ 427133819Stjr mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 428133819Stjr /* Set rar entry count */ 429133819Stjr mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 430133819Stjr if (mac->type == e1000_82576) 431133819Stjr mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 432133819Stjr if (mac->type == e1000_82580) 433133819Stjr mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 434133819Stjr if (mac->type == e1000_i350 || mac->type == e1000_i354) 435133819Stjr mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 436133819Stjr 437133819Stjr /* Enable EEE default settings for EEE supported devices */ 438133819Stjr if (mac->type >= e1000_i350) 439133819Stjr dev_spec->eee_disable = FALSE; 440133819Stjr 441133819Stjr /* Allow a single clear of the SW semaphore on I210 and newer */ 442133819Stjr if (mac->type >= e1000_i210) 443133819Stjr dev_spec->clear_semaphore_once = TRUE; 444133819Stjr 445133819Stjr /* Set if part includes ASF firmware */ 446133819Stjr mac->asf_firmware_present = TRUE; 447133819Stjr /* FWSM register */ 448133819Stjr mac->has_fwsm = TRUE; 449133819Stjr /* ARC supported; valid only if manageability features are enabled. */ 450133819Stjr mac->arc_subsystem_valid = 451133819Stjr !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); 452133819Stjr 453133819Stjr /* Function pointers */ 454133819Stjr 455133819Stjr /* bus type/speed/width */ 456133819Stjr mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 457133819Stjr /* reset */ 458133819Stjr if (mac->type >= e1000_82580) 459133819Stjr mac->ops.reset_hw = e1000_reset_hw_82580; 460185439Skib else 461185439Skib mac->ops.reset_hw = e1000_reset_hw_82575; 462185439Skib /* hw initialization */ 463133819Stjr if ((mac->type == e1000_i210) || (mac->type == e1000_i211)) 464133819Stjr mac->ops.init_hw = e1000_init_hw_i210; 465185439Skib else 466185439Skib mac->ops.init_hw = e1000_init_hw_82575; 467185439Skib /* link setup */ 468133819Stjr mac->ops.setup_link = e1000_setup_link_generic; 469133819Stjr /* physical interface link setup */ 470133819Stjr mac->ops.setup_physical_interface = 471133819Stjr (hw->phy.media_type == e1000_media_type_copper) 472133819Stjr ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; 473133819Stjr /* physical interface shutdown */ 474133819Stjr mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 475133819Stjr /* physical interface power up */ 476133819Stjr mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 477133819Stjr /* check for link */ 478133819Stjr mac->ops.check_for_link = e1000_check_for_link_82575; 479133819Stjr /* read mac address */ 480133819Stjr mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 481133819Stjr /* configure collision distance */ 482133819Stjr mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 483133819Stjr /* multicast address update */ 484133819Stjr mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 485133819Stjr if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) { 486133819Stjr /* writing VFTA */ 487133819Stjr mac->ops.write_vfta = e1000_write_vfta_i350; 488133819Stjr /* clearing VFTA */ 489133819Stjr mac->ops.clear_vfta = e1000_clear_vfta_i350; 490133819Stjr } else { 491133819Stjr /* writing VFTA */ 492133819Stjr mac->ops.write_vfta = e1000_write_vfta_generic; 493133819Stjr /* clearing VFTA */ 494133819Stjr mac->ops.clear_vfta = e1000_clear_vfta_generic; 495133819Stjr } 496133819Stjr if (hw->mac.type >= e1000_82580) 497133819Stjr mac->ops.validate_mdi_setting = 498133819Stjr e1000_validate_mdi_setting_crossover_generic; 499133819Stjr /* ID LED init */ 500133819Stjr mac->ops.id_led_init = e1000_id_led_init_generic; 501133819Stjr /* blink LED */ 502133819Stjr mac->ops.blink_led = e1000_blink_led_generic; 503133819Stjr /* setup LED */ 504133819Stjr mac->ops.setup_led = e1000_setup_led_generic; 505133819Stjr /* cleanup LED */ 506133819Stjr mac->ops.cleanup_led = e1000_cleanup_led_generic; 507133819Stjr /* turn on/off LED */ 508133819Stjr mac->ops.led_on = e1000_led_on_generic; 509133819Stjr mac->ops.led_off = e1000_led_off_generic; 510133819Stjr /* clear hardware counters */ 511133819Stjr mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 512133819Stjr /* link info */ 513133819Stjr mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 514133819Stjr /* acquire SW_FW sync */ 515133819Stjr mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575; 516133819Stjr mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575; 517133819Stjr if (mac->type >= e1000_i210) { 518133819Stjr mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210; 519133819Stjr mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210; 520133819Stjr } 521133819Stjr 522133819Stjr /* set lan id for port to determine which phy lock to use */ 523133819Stjr hw->mac.ops.set_lan_id(hw); 524133819Stjr 525133819Stjr return E1000_SUCCESS; 526133819Stjr} 527133819Stjr 528133819Stjr/** 529133819Stjr * e1000_init_function_pointers_82575 - Init func ptrs. 530133819Stjr * @hw: pointer to the HW structure 531133819Stjr * 532133819Stjr * Called to initialize all function pointers and parameters. 533133819Stjr **/ 534163736Snetchildvoid e1000_init_function_pointers_82575(struct e1000_hw *hw) 535163736Snetchild{ 536163736Snetchild DEBUGFUNC("e1000_init_function_pointers_82575"); 537163736Snetchild 538163736Snetchild hw->mac.ops.init_params = e1000_init_mac_params_82575; 539133819Stjr hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 540133819Stjr hw->phy.ops.init_params = e1000_init_phy_params_82575; 541133819Stjr hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 542133819Stjr} 543133819Stjr 544133819Stjr/** 545133819Stjr * e1000_acquire_phy_82575 - Acquire rights to access PHY 546133819Stjr * @hw: pointer to the HW structure 547133819Stjr * 548133819Stjr * Acquire access rights to the correct PHY. 549133819Stjr **/ 550133819Stjrstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 551133819Stjr{ 552133819Stjr u16 mask = E1000_SWFW_PHY0_SM; 553133819Stjr 554133819Stjr DEBUGFUNC("e1000_acquire_phy_82575"); 555133819Stjr 556158407Snetchild if (hw->bus.func == E1000_FUNC_1) 557158407Snetchild mask = E1000_SWFW_PHY1_SM; 558133819Stjr else if (hw->bus.func == E1000_FUNC_2) 559133819Stjr mask = E1000_SWFW_PHY2_SM; 560165690Snetchild else if (hw->bus.func == E1000_FUNC_3) 561165690Snetchild mask = E1000_SWFW_PHY3_SM; 562165690Snetchild 563165690Snetchild return hw->mac.ops.acquire_swfw_sync(hw, mask); 564133819Stjr} 565133819Stjr 566133819Stjr/** 567133819Stjr * e1000_release_phy_82575 - Release rights to access PHY 568133819Stjr * @hw: pointer to the HW structure 569133819Stjr * 570133819Stjr * A wrapper to release access rights to the correct PHY. 571133819Stjr **/ 572133819Stjrstatic void e1000_release_phy_82575(struct e1000_hw *hw) 573133819Stjr{ 574133819Stjr u16 mask = E1000_SWFW_PHY0_SM; 575133819Stjr 576133819Stjr DEBUGFUNC("e1000_release_phy_82575"); 577133819Stjr 578133819Stjr if (hw->bus.func == E1000_FUNC_1) 579133819Stjr mask = E1000_SWFW_PHY1_SM; 580133819Stjr else if (hw->bus.func == E1000_FUNC_2) 581133819Stjr mask = E1000_SWFW_PHY2_SM; 582133819Stjr else if (hw->bus.func == E1000_FUNC_3) 583133819Stjr mask = E1000_SWFW_PHY3_SM; 584133819Stjr 585133819Stjr hw->mac.ops.release_swfw_sync(hw, mask); 586133819Stjr} 587133819Stjr 588133819Stjr/** 589133819Stjr * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 590133819Stjr * @hw: pointer to the HW structure 591133819Stjr * @offset: register offset to be read 592133819Stjr * @data: pointer to the read data 593133819Stjr * 594220030Savg * Reads the PHY register at offset using the serial gigabit media independent 595220030Savg * interface and stores the retrieved information in data. 596133819Stjr **/ 597133819Stjrstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 598220030Savg u16 *data) 599220030Savg{ 600133819Stjr s32 ret_val = -E1000_ERR_PARAM; 601133819Stjr 602133819Stjr DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 603133819Stjr 604133819Stjr if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 605133819Stjr DEBUGOUT1("PHY Address %u is out of range\n", offset); 606133819Stjr goto out; 607133819Stjr } 608133819Stjr 609133819Stjr ret_val = hw->phy.ops.acquire(hw); 610133819Stjr if (ret_val) 611133819Stjr goto out; 612133819Stjr 613133819Stjr ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 614133819Stjr 615133819Stjr hw->phy.ops.release(hw); 616133819Stjr 617133819Stjrout: 618133819Stjr return ret_val; 619133819Stjr} 620133819Stjr 621133819Stjr/** 622133819Stjr * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 623133819Stjr * @hw: pointer to the HW structure 624133819Stjr * @offset: register offset to write to 625133819Stjr * @data: data to write at register offset 626133819Stjr * 627133819Stjr * Writes the data to PHY register at the offset using the serial gigabit 628133819Stjr * media independent interface. 629133819Stjr **/ 630133819Stjrstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 631133819Stjr u16 data) 632234358Sjkim{ 633133819Stjr s32 ret_val = -E1000_ERR_PARAM; 634133819Stjr 635133819Stjr DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 636234358Sjkim 637133819Stjr if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 638133819Stjr DEBUGOUT1("PHY Address %d is out of range\n", offset); 639133819Stjr goto out; 640234358Sjkim } 641133819Stjr 642133819Stjr ret_val = hw->phy.ops.acquire(hw); 643133819Stjr if (ret_val) 644133819Stjr goto out; 645133819Stjr 646133819Stjr ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 647133819Stjr 648133819Stjr hw->phy.ops.release(hw); 649133819Stjr 650133819Stjrout: 651133819Stjr return ret_val; 652133819Stjr} 653133819Stjr 654133819Stjr/** 655133819Stjr * e1000_get_phy_id_82575 - Retrieve PHY addr and id 656133819Stjr * @hw: pointer to the HW structure 657133819Stjr * 658133819Stjr * Retrieves the PHY address and ID for both PHY's which do and do not use 659133819Stjr * sgmi interface. 660133819Stjr **/ 661133819Stjrstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 662133819Stjr{ 663133819Stjr struct e1000_phy_info *phy = &hw->phy; 664133819Stjr s32 ret_val = E1000_SUCCESS; 665133819Stjr u16 phy_id; 666133819Stjr u32 ctrl_ext; 667133819Stjr u32 mdic; 668133819Stjr 669133819Stjr DEBUGFUNC("e1000_get_phy_id_82575"); 670133819Stjr 671133819Stjr /* some i354 devices need an extra read for phy id */ 672133819Stjr if (hw->mac.type == e1000_i354) 673133819Stjr e1000_get_phy_id(hw); 674133819Stjr 675133819Stjr /* 676133819Stjr * For SGMII PHYs, we try the list of possible addresses until 677133819Stjr * we find one that works. For non-SGMII PHYs 678133819Stjr * (e.g. integrated copper PHYs), an address of 1 should 679133819Stjr * work. The result of this function should mean phy->phy_addr 680133819Stjr * and phy->id are set correctly. 681133819Stjr */ 682133819Stjr if (!e1000_sgmii_active_82575(hw)) { 683133819Stjr phy->addr = 1; 684133819Stjr ret_val = e1000_get_phy_id(hw); 685133819Stjr goto out; 686133819Stjr } 687133819Stjr 688133819Stjr if (e1000_sgmii_uses_mdio_82575(hw)) { 689133819Stjr switch (hw->mac.type) { 690133819Stjr case e1000_82575: 691133819Stjr case e1000_82576: 692161309Snetchild mdic = E1000_READ_REG(hw, E1000_MDIC); 693161309Snetchild mdic &= E1000_MDIC_PHY_MASK; 694161309Snetchild phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 695133819Stjr break; 696133819Stjr case e1000_82580: 697133819Stjr case e1000_i350: 698133819Stjr case e1000_i354: 699133819Stjr case e1000_i210: 700133819Stjr case e1000_i211: 701133819Stjr mdic = E1000_READ_REG(hw, E1000_MDICNFG); 702133819Stjr mdic &= E1000_MDICNFG_PHY_MASK; 703133819Stjr phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 704133819Stjr break; 705133819Stjr default: 706133819Stjr ret_val = -E1000_ERR_PHY; 707133819Stjr goto out; 708133819Stjr break; 709133819Stjr } 710133819Stjr ret_val = e1000_get_phy_id(hw); 711133819Stjr goto out; 712133819Stjr } 713133819Stjr 714133819Stjr /* Power on sgmii phy if it is disabled */ 715133819Stjr ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 716133819Stjr E1000_WRITE_REG(hw, E1000_CTRL_EXT, 717133819Stjr ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 718133819Stjr E1000_WRITE_FLUSH(hw); 719133819Stjr msec_delay(300); 720133819Stjr 721133819Stjr /* 722133819Stjr * The address field in the I2CCMD register is 3 bits and 0 is invalid. 723133819Stjr * Therefore, we need to test 1-7 724133819Stjr */ 725133819Stjr for (phy->addr = 1; phy->addr < 8; phy->addr++) { 726133819Stjr ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 727133819Stjr if (ret_val == E1000_SUCCESS) { 728133819Stjr DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 729133819Stjr phy_id, phy->addr); 730133819Stjr /* 731161309Snetchild * At the time of this writing, The M88 part is 732161309Snetchild * the only supported SGMII PHY product. 733161309Snetchild */ 734161309Snetchild if (phy_id == M88_VENDOR) 735161309Snetchild break; 736161309Snetchild } else { 737161309Snetchild DEBUGOUT1("PHY address %u was unreadable\n", 738218103Sdchagin phy->addr); 739161309Snetchild } 740218103Sdchagin } 741218103Sdchagin 742161309Snetchild /* A valid PHY type couldn't be found. */ 743177258Srdivacky if (phy->addr == 8) { 744177258Srdivacky phy->addr = 0; 745177258Srdivacky ret_val = -E1000_ERR_PHY; 746177258Srdivacky } else { 747177258Srdivacky ret_val = e1000_get_phy_id(hw); 748171999Skib } 749171999Skib 750171999Skib /* restore previous sfp cage power state */ 751171999Skib E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 752171999Skib 753168036Sjkimout: 754168036Sjkim return ret_val; 755168036Sjkim} 756133819Stjr 757228958Sjhb/** 758228958Sjhb * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 759228958Sjhb * @hw: pointer to the HW structure 760228958Sjhb * 761133819Stjr * Resets the PHY using the serial gigabit media independent interface. 762161309Snetchild **/ 763161309Snetchildstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 764161309Snetchild{ 765159801Snetchild s32 ret_val = E1000_SUCCESS; 766159801Snetchild struct e1000_phy_info *phy = &hw->phy; 767159801Snetchild 768159801Snetchild DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 769255676Srdivacky 770159801Snetchild /* 771159801Snetchild * This isn't a TRUE "hard" reset, but is the only reset 772255676Srdivacky * available to us at this time. 773159801Snetchild */ 774159801Snetchild 775255676Srdivacky DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 776159801Snetchild 777159801Snetchild if (!(hw->phy.ops.write_reg)) 778159801Snetchild goto out; 779159801Snetchild 780159801Snetchild /* 781161309Snetchild * SFP documentation requires the following to configure the SPF module 782159801Snetchild * to work on SGMII. No further documentation is given. 783159801Snetchild */ 784159801Snetchild ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 785159801Snetchild if (ret_val) 786159801Snetchild goto out; 787159801Snetchild 788159801Snetchild ret_val = hw->phy.ops.commit(hw); 789159801Snetchild if (ret_val) 790159801Snetchild goto out; 791159801Snetchild 792159801Snetchild if (phy->id == M88E1512_E_PHY_ID) 793159801Snetchild ret_val = e1000_initialize_M88E1512_phy(hw); 794159801Snetchildout: 795159801Snetchild return ret_val; 796159801Snetchild} 797159801Snetchild 798159801Snetchild/** 799161309Snetchild * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 800161309Snetchild * @hw: pointer to the HW structure 801159801Snetchild * @active: TRUE to enable LPLU, FALSE to disable 802159801Snetchild * 803161309Snetchild * Sets the LPLU D0 state according to the active flag. When 804161309Snetchild * activating LPLU this function also disables smart speed 805159801Snetchild * and vice versa. LPLU will not be activated unless the 806159801Snetchild * device autonegotiation advertisement meets standards of 807161309Snetchild * either 10 or 10/100 or 10/100/1000 at all duplexes. 808161309Snetchild * This is a function pointer entry point only called by 809159801Snetchild * PHY setup routines. 810159801Snetchild **/ 811161309Snetchildstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 812161309Snetchild{ 813161309Snetchild struct e1000_phy_info *phy = &hw->phy; 814161309Snetchild s32 ret_val = E1000_SUCCESS; 815159801Snetchild u16 data; 816159801Snetchild 817161666Snetchild DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 818172220Sdwmalone 819161666Snetchild if (!(hw->phy.ops.read_reg)) 820159801Snetchild goto out; 821159801Snetchild 822159801Snetchild ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 823159801Snetchild if (ret_val) 824159801Snetchild goto out; 825161309Snetchild 826161309Snetchild if (active) { 827161309Snetchild data |= IGP02E1000_PM_D0_LPLU; 828159801Snetchild ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 829159801Snetchild data); 830165690Snetchild if (ret_val) 831165690Snetchild goto out; 832159801Snetchild 833159801Snetchild /* When LPLU is enabled, we should disable SmartSpeed */ 834228958Sjhb ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 835228958Sjhb &data); 836228958Sjhb data &= ~IGP01E1000_PSCFR_SMART_SPEED; 837228958Sjhb ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 838159801Snetchild data); 839159801Snetchild if (ret_val) 840159801Snetchild goto out; 841159801Snetchild } else { 842159801Snetchild data &= ~IGP02E1000_PM_D0_LPLU; 843159801Snetchild ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 844159801Snetchild data); 845159801Snetchild /* 846159801Snetchild * LPLU and SmartSpeed are mutually exclusive. LPLU is used 847159801Snetchild * during Dx states where the power conservation is most 848159801Snetchild * important. During driver activity we should enable 849159801Snetchild * SmartSpeed, so performance is maintained. 850159801Snetchild */ 851159801Snetchild if (phy->smart_speed == e1000_smart_speed_on) { 852159801Snetchild ret_val = phy->ops.read_reg(hw, 853159801Snetchild IGP01E1000_PHY_PORT_CONFIG, 854159801Snetchild &data); 855159801Snetchild if (ret_val) 856159801Snetchild goto out; 857159801Snetchild 858159801Snetchild data |= IGP01E1000_PSCFR_SMART_SPEED; 859159801Snetchild ret_val = phy->ops.write_reg(hw, 860159801Snetchild IGP01E1000_PHY_PORT_CONFIG, 861159801Snetchild data); 862159801Snetchild if (ret_val) 863159801Snetchild goto out; 864159801Snetchild } else if (phy->smart_speed == e1000_smart_speed_off) { 865159801Snetchild ret_val = phy->ops.read_reg(hw, 866159801Snetchild IGP01E1000_PHY_PORT_CONFIG, 867159801Snetchild &data); 868159801Snetchild if (ret_val) 869159801Snetchild goto out; 870159801Snetchild 871159801Snetchild data &= ~IGP01E1000_PSCFR_SMART_SPEED; 872159801Snetchild ret_val = phy->ops.write_reg(hw, 873159801Snetchild IGP01E1000_PHY_PORT_CONFIG, 874159801Snetchild data); 875159801Snetchild if (ret_val) 876159801Snetchild goto out; 877159801Snetchild } 878159801Snetchild } 879159801Snetchild 880159801Snetchildout: 881159801Snetchild return ret_val; 882159801Snetchild} 883159801Snetchild 884159801Snetchild/** 885159801Snetchild * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 886159801Snetchild * @hw: pointer to the HW structure 887159801Snetchild * @active: TRUE to enable LPLU, FALSE to disable 888159801Snetchild * 889159801Snetchild * Sets the LPLU D0 state according to the active flag. When 890159801Snetchild * activating LPLU this function also disables smart speed 891159801Snetchild * and vice versa. LPLU will not be activated unless the 892159801Snetchild * device autonegotiation advertisement meets standards of 893159801Snetchild * either 10 or 10/100 or 10/100/1000 at all duplexes. 894159801Snetchild * This is a function pointer entry point only called by 895159801Snetchild * PHY setup routines. 896159801Snetchild **/ 897159801Snetchildstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 898159801Snetchild{ 899159801Snetchild struct e1000_phy_info *phy = &hw->phy; 900168014Sjulian u32 data; 901177999Skib 902168014Sjulian DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 903168014Sjulian 904159801Snetchild data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 905159801Snetchild 906177999Skib if (active) { 907177999Skib data |= E1000_82580_PM_D0_LPLU; 908177999Skib 909159801Snetchild /* When LPLU is enabled, we should disable SmartSpeed */ 910159801Snetchild data &= ~E1000_82580_PM_SPD; 911177999Skib } else { 912177999Skib data &= ~E1000_82580_PM_D0_LPLU; 913177999Skib 914177999Skib /* 915159801Snetchild * LPLU and SmartSpeed are mutually exclusive. LPLU is used 916159801Snetchild * during Dx states where the power conservation is most 917177999Skib * important. During driver activity we should enable 918177999Skib * SmartSpeed, so performance is maintained. 919177999Skib */ 920177999Skib if (phy->smart_speed == e1000_smart_speed_on) 921177999Skib data |= E1000_82580_PM_SPD; 922159801Snetchild else if (phy->smart_speed == e1000_smart_speed_off) 923159801Snetchild data &= ~E1000_82580_PM_SPD; 924177999Skib } 925177999Skib 926177999Skib E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 927159801Snetchild return E1000_SUCCESS; 928159801Snetchild} 929177999Skib 930177999Skib/** 931177999Skib * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 932177999Skib * @hw: pointer to the HW structure 933159801Snetchild * @active: boolean used to enable/disable lplu 934159801Snetchild * 935177999Skib * Success returns 0, Failure returns 1 936177999Skib * 937177999Skib * The low power link up (lplu) state is set to the power management level D3 938159801Snetchild * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 939159801Snetchild * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 940177999Skib * is used during Dx states where the power conservation is most important. 941177999Skib * During driver activity, SmartSpeed should be enabled so performance is 942177999Skib * maintained. 943177999Skib **/ 944159801Snetchilds32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 945159801Snetchild{ 946177999Skib struct e1000_phy_info *phy = &hw->phy; 947177999Skib u32 data; 948177999Skib 949177999Skib DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 950227694Sed 951159801Snetchild data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 952159801Snetchild 953177999Skib if (!active) { 954177999Skib data &= ~E1000_82580_PM_D3_LPLU; 955177999Skib /* 956159801Snetchild * LPLU and SmartSpeed are mutually exclusive. LPLU is used 957159801Snetchild * during Dx states where the power conservation is most 958177999Skib * important. During driver activity we should enable 959177999Skib * SmartSpeed, so performance is maintained. 960177999Skib */ 961177999Skib if (phy->smart_speed == e1000_smart_speed_on) 962159801Snetchild data |= E1000_82580_PM_SPD; 963159801Snetchild else if (phy->smart_speed == e1000_smart_speed_off) 964177999Skib data &= ~E1000_82580_PM_SPD; 965177999Skib } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 966177999Skib (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 967159801Snetchild (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 968159801Snetchild data |= E1000_82580_PM_D3_LPLU; 969177999Skib /* When LPLU is enabled, we should disable SmartSpeed */ 970177999Skib data &= ~E1000_82580_PM_SPD; 971227692Sed } 972227694Sed 973159801Snetchild E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 974159801Snetchild return E1000_SUCCESS; 975159801Snetchild} 976159801Snetchild 977159801Snetchild/** 978159801Snetchild * e1000_acquire_nvm_82575 - Request for access to EEPROM 979159801Snetchild * @hw: pointer to the HW structure 980159801Snetchild * 981159801Snetchild * Acquire the necessary semaphores for exclusive access to the EEPROM. 982159801Snetchild * Set the EEPROM access request bit and wait for EEPROM access grant bit. 983178258Sjkim * Return successful if access grant bit set, else clear the request for 984178977Srdivacky * EEPROM access and return -E1000_ERR_NVM (-1). 985178977Srdivacky **/ 986178258Sjkimstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 987178258Sjkim{ 988178977Srdivacky s32 ret_val = E1000_SUCCESS; 989178977Srdivacky 990178977Srdivacky DEBUGFUNC("e1000_acquire_nvm_82575"); 991178258Sjkim 992178258Sjkim ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 993178258Sjkim if (ret_val) 994178258Sjkim goto out; 995178258Sjkim 996178258Sjkim /* 997178258Sjkim * Check if there is some access 998178258Sjkim * error this access may hook on 999178258Sjkim */ 1000178258Sjkim if (hw->mac.type == e1000_i350) { 1001178258Sjkim u32 eecd = E1000_READ_REG(hw, E1000_EECD); 1002178258Sjkim if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT | 1003178258Sjkim E1000_EECD_TIMEOUT)) { 1004232800Snetchild /* Clear all access error flags */ 1005232800Snetchild E1000_WRITE_REG(hw, E1000_EECD, eecd | 1006232800Snetchild E1000_EECD_ERROR_CLR); 1007232800Snetchild DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 1008232800Snetchild } 1009232800Snetchild } 1010232800Snetchild 1011232800Snetchild if (hw->mac.type == e1000_82580) { 1012232800Snetchild u32 eecd = E1000_READ_REG(hw, E1000_EECD); 1013232800Snetchild if (eecd & E1000_EECD_BLOCKED) { 1014232800Snetchild /* Clear access error flag */ 1015232800Snetchild E1000_WRITE_REG(hw, E1000_EECD, eecd | 1016232800Snetchild E1000_EECD_BLOCKED); 1017232800Snetchild DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 1018232800Snetchild } 1019232800Snetchild } 1020232800Snetchild 1021232800Snetchild ret_val = e1000_acquire_nvm_generic(hw); 1022232800Snetchild if (ret_val) 1023232800Snetchild e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 1024232800Snetchild 1025232800Snetchildout: 1026232800Snetchild return ret_val; 1027232800Snetchild} 1028232800Snetchild 1029232800Snetchild/** 1030232800Snetchild * e1000_release_nvm_82575 - Release exclusive access to EEPROM 1031232800Snetchild * @hw: pointer to the HW structure 1032232800Snetchild * 1033232800Snetchild * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1034232800Snetchild * then release the semaphores acquired. 1035232800Snetchild **/ 1036232800Snetchildstatic void e1000_release_nvm_82575(struct e1000_hw *hw) 1037232800Snetchild{ 1038232800Snetchild DEBUGFUNC("e1000_release_nvm_82575"); 1039232800Snetchild 1040232800Snetchild e1000_release_nvm_generic(hw); 1041255676Srdivacky 1042232800Snetchild e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 1043232800Snetchild} 1044232800Snetchild 1045232800Snetchild/** 1046232800Snetchild * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1047234354Sjkim * @hw: pointer to the HW structure 1048234354Sjkim * @mask: specifies which semaphore to acquire 1049232800Snetchild * 1050232800Snetchild * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1051232800Snetchild * will also specify which port we're acquiring the lock for. 1052232800Snetchild **/ 1053232800Snetchildstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1054232800Snetchild{ 1055232800Snetchild u32 swfw_sync; 1056232800Snetchild u32 swmask = mask; 1057232800Snetchild u32 fwmask = mask << 16; 1058232800Snetchild s32 ret_val = E1000_SUCCESS; 1059232800Snetchild s32 i = 0, timeout = 200; 1060232800Snetchild 1061232800Snetchild DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 1062232800Snetchild 1063232800Snetchild while (i < timeout) { 1064232800Snetchild if (e1000_get_hw_semaphore_generic(hw)) { 1065232800Snetchild ret_val = -E1000_ERR_SWFW_SYNC; 1066232800Snetchild goto out; 1067232800Snetchild } 1068232800Snetchild 1069232800Snetchild swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1070232800Snetchild if (!(swfw_sync & (fwmask | swmask))) 1071232800Snetchild break; 1072232800Snetchild 1073232800Snetchild /* 1074232800Snetchild * Firmware currently using resource (fwmask) 1075232800Snetchild * or other software thread using resource (swmask) 1076232800Snetchild */ 1077232800Snetchild e1000_put_hw_semaphore_generic(hw); 1078232800Snetchild msec_delay_irq(5); 1079232800Snetchild i++; 1080232800Snetchild } 1081232800Snetchild 1082232800Snetchild if (i == timeout) { 1083232800Snetchild DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1084232800Snetchild ret_val = -E1000_ERR_SWFW_SYNC; 1085232800Snetchild goto out; 1086232800Snetchild } 1087232800Snetchild 1088232800Snetchild swfw_sync |= swmask; 1089232800Snetchild E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1090232800Snetchild 1091232800Snetchild e1000_put_hw_semaphore_generic(hw); 1092232800Snetchild 1093232800Snetchildout: 1094232800Snetchild return ret_val; 1095232800Snetchild} 1096232800Snetchild 1097232800Snetchild/** 1098232800Snetchild * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 1099232800Snetchild * @hw: pointer to the HW structure 1100232800Snetchild * @mask: specifies which semaphore to acquire 1101143198Ssobomax * 1102133819Stjr * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1103133819Stjr * will also specify which port we're releasing the lock for. 1104133819Stjr **/ 1105133819Stjrstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1106133819Stjr{ 1107133819Stjr u32 swfw_sync; 1108133819Stjr 1109133819Stjr DEBUGFUNC("e1000_release_swfw_sync_82575"); 1110133819Stjr 1111133819Stjr while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 1112133819Stjr ; /* Empty */ 1113133819Stjr 1114156919Snetchild swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1115133819Stjr swfw_sync &= ~mask; 1116133819Stjr E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1117133819Stjr 1118133819Stjr e1000_put_hw_semaphore_generic(hw); 1119133819Stjr} 1120133819Stjr 1121133819Stjr/** 1122133819Stjr * e1000_get_cfg_done_82575 - Read config done bit 1123133819Stjr * @hw: pointer to the HW structure 1124133819Stjr * 1125133819Stjr * Read the management control register for the config done bit for 1126133819Stjr * completion status. NOTE: silicon which is EEPROM-less will fail trying 1127133819Stjr * to read the config done bit, so an error is *ONLY* logged and returns 1128133819Stjr * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1129133819Stjr * would not be able to be reset or change link. 1130133819Stjr **/ 1131133819Stjrstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1132133819Stjr{ 1133133819Stjr s32 timeout = PHY_CFG_TIMEOUT; 1134133819Stjr u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1135133819Stjr 1136133819Stjr DEBUGFUNC("e1000_get_cfg_done_82575"); 1137133819Stjr 1138133819Stjr if (hw->bus.func == E1000_FUNC_1) 1139133819Stjr mask = E1000_NVM_CFG_DONE_PORT_1; 1140133819Stjr else if (hw->bus.func == E1000_FUNC_2) 1141133819Stjr mask = E1000_NVM_CFG_DONE_PORT_2; 1142133819Stjr else if (hw->bus.func == E1000_FUNC_3) 1143133819Stjr mask = E1000_NVM_CFG_DONE_PORT_3; 1144133819Stjr while (timeout) { 1145161309Snetchild if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1146133819Stjr break; 1147133819Stjr msec_delay(1); 1148133819Stjr timeout--; 1149133819Stjr } 1150133819Stjr if (!timeout) 1151133819Stjr DEBUGOUT("MNG configuration cycle has not completed.\n"); 1152133819Stjr 1153156843Snetchild /* If EEPROM is not marked present, init the PHY manually */ 1154133819Stjr if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 1155133819Stjr (hw->phy.type == e1000_phy_igp_3)) 1156133819Stjr e1000_phy_init_script_igp3(hw); 1157133819Stjr 1158133819Stjr return E1000_SUCCESS; 1159133819Stjr} 1160133819Stjr 1161133819Stjr/** 1162133819Stjr * e1000_get_link_up_info_82575 - Get link speed/duplex info 1163156919Snetchild * @hw: pointer to the HW structure 1164133819Stjr * @speed: stores the current speed 1165133819Stjr * @duplex: stores the current duplex 1166133819Stjr * 1167133819Stjr * This is a wrapper function, if using the serial gigabit media independent 1168133819Stjr * interface, use PCS to retrieve the link speed and duplex information. 1169156843Snetchild * Otherwise, use the generic function to get the link speed and duplex info. 1170147142Ssobomax **/ 1171133819Stjrstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1172133819Stjr u16 *duplex) 1173133819Stjr{ 1174133819Stjr s32 ret_val; 1175133819Stjr 1176133819Stjr DEBUGFUNC("e1000_get_link_up_info_82575"); 1177133819Stjr 1178133819Stjr if (hw->phy.media_type != e1000_media_type_copper) 1179133819Stjr ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1180133819Stjr duplex); 1181166730Sjkim else 1182133819Stjr ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1183133819Stjr duplex); 1184133819Stjr 1185133819Stjr return ret_val; 1186133819Stjr} 1187133819Stjr 1188133819Stjr/** 1189184790Sed * e1000_check_for_link_82575 - Check for link 1190133819Stjr * @hw: pointer to the HW structure 1191133819Stjr * 1192133819Stjr * If sgmii is enabled, then use the pcs register to determine link, otherwise 1193133819Stjr * use the generic interface for determining link. 1194133819Stjr **/ 1195133819Stjrstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1196133819Stjr{ 1197133819Stjr s32 ret_val; 1198133819Stjr u16 speed, duplex; 1199133819Stjr 1200133819Stjr DEBUGFUNC("e1000_check_for_link_82575"); 1201133819Stjr 1202133819Stjr if (hw->phy.media_type != e1000_media_type_copper) { 1203133819Stjr ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1204133819Stjr &duplex); 1205133819Stjr /* 1206133819Stjr * Use this flag to determine if link needs to be checked or 1207133819Stjr * not. If we have link clear the flag so that we do not 1208133819Stjr * continue to check for link. 1209133819Stjr */ 1210133819Stjr hw->mac.get_link_status = !hw->mac.serdes_has_link; 1211133819Stjr 1212133819Stjr /* 1213133819Stjr * Configure Flow Control now that Auto-Neg has completed. 1214133819Stjr * First, we need to restore the desired flow control 1215133819Stjr * settings because we may have had to re-autoneg with a 1216133819Stjr * different link partner. 1217133819Stjr */ 1218133819Stjr ret_val = e1000_config_fc_after_link_up_generic(hw); 1219133819Stjr if (ret_val) 1220133819Stjr DEBUGOUT("Error configuring flow control\n"); 1221133819Stjr } else { 1222133819Stjr ret_val = e1000_check_for_copper_link_generic(hw); 1223133819Stjr } 1224133819Stjr 1225133819Stjr return ret_val; 1226133819Stjr} 1227133819Stjr 1228133819Stjr/** 1229133819Stjr * e1000_check_for_link_media_swap - Check which M88E1112 interface linked 1230133819Stjr * @hw: pointer to the HW structure 1231133819Stjr * 1232133819Stjr * Poll the M88E1112 interfaces to see which interface achieved link. 1233133819Stjr */ 1234133819Stjrstatic s32 e1000_check_for_link_media_swap(struct e1000_hw *hw) 1235133819Stjr{ 1236133819Stjr struct e1000_phy_info *phy = &hw->phy; 1237133819Stjr s32 ret_val; 1238133819Stjr u16 data; 1239133819Stjr u8 port = 0; 1240133819Stjr 1241133819Stjr DEBUGFUNC("e1000_check_for_link_media_swap"); 1242133819Stjr 1243133819Stjr /* Check for copper. */ 1244133819Stjr ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1245133819Stjr if (ret_val) 1246133819Stjr return ret_val; 1247133819Stjr 1248133819Stjr ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 1249133819Stjr if (ret_val) 1250133819Stjr return ret_val; 1251133819Stjr 1252133819Stjr if (data & E1000_M88E1112_STATUS_LINK) 1253133819Stjr port = E1000_MEDIA_PORT_COPPER; 1254133819Stjr 1255133819Stjr /* Check for other. */ 1256133819Stjr ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 1257133819Stjr if (ret_val) 1258133819Stjr return ret_val; 1259133819Stjr 1260133819Stjr ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 1261133819Stjr if (ret_val) 1262161309Snetchild return ret_val; 1263133819Stjr 1264133819Stjr if (data & E1000_M88E1112_STATUS_LINK) 1265133819Stjr port = E1000_MEDIA_PORT_OTHER; 1266133819Stjr 1267133819Stjr /* Determine if a swap needs to happen. */ 1268133819Stjr if (port && (hw->dev_spec._82575.media_port != port)) { 1269133819Stjr hw->dev_spec._82575.media_port = port; 1270133819Stjr hw->dev_spec._82575.media_changed = TRUE; 1271133819Stjr } 1272133819Stjr 1273133819Stjr if (port == E1000_MEDIA_PORT_COPPER) { 1274133819Stjr /* reset page to 0 */ 1275161309Snetchild ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1276161309Snetchild if (ret_val) 1277177258Srdivacky return ret_val; 1278171999Skib e1000_check_for_link_82575(hw); 1279168036Sjkim } else { 1280133819Stjr e1000_check_for_link_82575(hw); 1281161309Snetchild /* reset page to 0 */ 1282159801Snetchild ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1283159801Snetchild if (ret_val) 1284159801Snetchild return ret_val; 1285159801Snetchild } 1286159801Snetchild 1287159801Snetchild return E1000_SUCCESS; 1288159801Snetchild} 1289159801Snetchild 1290159801Snetchild/** 1291159801Snetchild * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1292159801Snetchild * @hw: pointer to the HW structure 1293159801Snetchild **/ 1294159801Snetchildstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1295159801Snetchild{ 1296159801Snetchild u32 reg; 1297159801Snetchild 1298159801Snetchild DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1299159801Snetchild 1300159801Snetchild if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1301159801Snetchild !e1000_sgmii_active_82575(hw)) 1302159801Snetchild return; 1303159801Snetchild 1304159801Snetchild /* Enable PCS to turn on link */ 1305159801Snetchild reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1306159801Snetchild reg |= E1000_PCS_CFG_PCS_EN; 1307159801Snetchild E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1308159801Snetchild 1309159801Snetchild /* Power up the laser */ 1310159801Snetchild reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1311159801Snetchild reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1312159801Snetchild E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1313159801Snetchild 1314159801Snetchild /* flush the write to verify completion */ 1315159801Snetchild E1000_WRITE_FLUSH(hw); 1316159801Snetchild msec_delay(1); 1317159801Snetchild} 1318159801Snetchild 1319159801Snetchild/** 1320159801Snetchild * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1321159801Snetchild * @hw: pointer to the HW structure 1322159801Snetchild * @speed: stores the current speed 1323159801Snetchild * @duplex: stores the current duplex 1324159801Snetchild * 1325159801Snetchild * Using the physical coding sub-layer (PCS), retrieve the current speed and 1326159801Snetchild * duplex, then store the values in the pointers provided. 1327159801Snetchild **/ 1328159801Snetchildstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1329159801Snetchild u16 *speed, u16 *duplex) 1330159801Snetchild{ 1331159801Snetchild struct e1000_mac_info *mac = &hw->mac; 1332159801Snetchild u32 pcs; 1333159801Snetchild u32 status; 1334159801Snetchild 1335159801Snetchild DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1336159801Snetchild 1337159801Snetchild /* 1338178258Sjkim * Read the PCS Status register for link state. For non-copper mode, 1339178258Sjkim * the status register is not accurate. The PCS status register is 1340178258Sjkim * used instead. 1341178258Sjkim */ 1342178258Sjkim pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1343178258Sjkim 1344232800Snetchild /* 1345232800Snetchild * The link up bit determines when link is up on autoneg. 1346232800Snetchild */ 1347232800Snetchild if (pcs & E1000_PCS_LSTS_LINK_OK) { 1348232800Snetchild mac->serdes_has_link = TRUE; 1349232800Snetchild 1350232800Snetchild /* Detect and store PCS speed */ 1351232800Snetchild if (pcs & E1000_PCS_LSTS_SPEED_1000) 1352232800Snetchild *speed = SPEED_1000; 1353232800Snetchild else if (pcs & E1000_PCS_LSTS_SPEED_100) 1354232800Snetchild *speed = SPEED_100; 1355232800Snetchild else 1356232800Snetchild *speed = SPEED_10; 1357232800Snetchild 1358232800Snetchild /* Detect and store PCS duplex */ 1359232800Snetchild if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1360232800Snetchild *duplex = FULL_DUPLEX; 1361232800Snetchild else 1362232800Snetchild *duplex = HALF_DUPLEX; 1363232800Snetchild 1364232800Snetchild /* Check if it is an I354 2.5Gb backplane connection. */ 1365232800Snetchild if (mac->type == e1000_i354) { 1366232800Snetchild status = E1000_READ_REG(hw, E1000_STATUS); 1367232800Snetchild if ((status & E1000_STATUS_2P5_SKU) && 1368232800Snetchild !(status & E1000_STATUS_2P5_SKU_OVER)) { 1369232800Snetchild *speed = SPEED_2500; 1370232800Snetchild *duplex = FULL_DUPLEX; 1371232800Snetchild DEBUGOUT("2500 Mbs, "); 1372232800Snetchild DEBUGOUT("Full Duplex\n"); 1373232800Snetchild } 1374232800Snetchild } 1375232800Snetchild 1376133819Stjr } else { 1377133819Stjr mac->serdes_has_link = FALSE; 1378133819Stjr *speed = 0; 1379143198Ssobomax *duplex = 0; 1380133819Stjr } 1381133819Stjr 1382133819Stjr return E1000_SUCCESS; 1383133819Stjr} 1384133819Stjr 1385133819Stjr/** 1386143198Ssobomax * e1000_shutdown_serdes_link_82575 - Remove link during power down 1387133819Stjr * @hw: pointer to the HW structure 1388133819Stjr * 1389133819Stjr * In the case of serdes shut down sfp and PCS on driver unload 1390171999Skib * when management pass thru is not enabled. 1391171999Skib **/ 1392171999Skibvoid e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1393171999Skib{ 1394171999Skib u32 reg; 1395171999Skib 1396171999Skib DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1397197064Sdes 1398197064Sdes if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1399197064Sdes !e1000_sgmii_active_82575(hw)) 1400197064Sdes return; 1401197064Sdes 1402197064Sdes if (!e1000_enable_mng_pass_thru(hw)) { 1403197064Sdes /* Disable PCS to turn off link */ 1404161330Sjhb reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1405161330Sjhb reg &= ~E1000_PCS_CFG_PCS_EN; 1406161330Sjhb E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1407165610Srwatson 1408161330Sjhb /* shutdown the laser */ 1409161330Sjhb reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1410161330Sjhb reg |= E1000_CTRL_EXT_SDP3_DATA; 1411161330Sjhb E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1412161330Sjhb 1413161330Sjhb /* flush the write to verify completion */ 1414161330Sjhb E1000_WRITE_FLUSH(hw); 1415161330Sjhb msec_delay(1); 1416161330Sjhb } 1417161330Sjhb 1418161330Sjhb return; 1419161330Sjhb} 1420161330Sjhb 1421161330Sjhb/** 1422161330Sjhb * e1000_reset_hw_82575 - Reset hardware 1423161330Sjhb * @hw: pointer to the HW structure 1424161330Sjhb * 1425161330Sjhb * This resets the hardware into a known state. 1426161330Sjhb **/ 1427161330Sjhbstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1428161330Sjhb{ 1429161330Sjhb u32 ctrl; 1430161330Sjhb s32 ret_val; 1431161330Sjhb 1432161330Sjhb DEBUGFUNC("e1000_reset_hw_82575"); 1433161330Sjhb 1434161330Sjhb /* 1435161330Sjhb * Prevent the PCI-E bus from sticking if there is no TLP connection 1436161330Sjhb * on the last TLP read/write transaction when MAC is reset. 1437161330Sjhb */ 1438161330Sjhb ret_val = e1000_disable_pcie_master_generic(hw); 1439161330Sjhb if (ret_val) 1440161330Sjhb DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1441161330Sjhb 1442161330Sjhb /* set the completion timeout for interface */ 1443161330Sjhb ret_val = e1000_set_pcie_completion_timeout(hw); 1444161330Sjhb if (ret_val) 1445161330Sjhb DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1446161330Sjhb 1447161330Sjhb DEBUGOUT("Masking off all interrupts\n"); 1448161330Sjhb E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1449161330Sjhb 1450161330Sjhb E1000_WRITE_REG(hw, E1000_RCTL, 0); 1451161330Sjhb E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1452161330Sjhb E1000_WRITE_FLUSH(hw); 1453161330Sjhb 1454161330Sjhb msec_delay(10); 1455161330Sjhb 1456161330Sjhb ctrl = E1000_READ_REG(hw, E1000_CTRL); 1457161330Sjhb 1458161330Sjhb DEBUGOUT("Issuing a global reset to MAC\n"); 1459161330Sjhb E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1460161330Sjhb 1461161330Sjhb ret_val = e1000_get_auto_rd_done_generic(hw); 1462161330Sjhb if (ret_val) { 1463161330Sjhb /* 1464161330Sjhb * When auto config read does not complete, do not 1465161330Sjhb * return with an error. This can happen in situations 1466161330Sjhb * where there is no eeprom and prevents getting link. 1467161330Sjhb */ 1468165610Srwatson DEBUGOUT("Auto Read Done did not complete\n"); 1469161330Sjhb } 1470161330Sjhb 1471161330Sjhb /* If EEPROM is not present, run manual init scripts */ 1472161330Sjhb if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 1473161330Sjhb e1000_reset_init_script_82575(hw); 1474161330Sjhb 1475161330Sjhb /* Clear any pending interrupt events. */ 1476161330Sjhb E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1477161330Sjhb E1000_READ_REG(hw, E1000_ICR); 1478161330Sjhb 1479161330Sjhb /* Install any alternate MAC address into RAR0 */ 1480161330Sjhb ret_val = e1000_check_alt_mac_addr_generic(hw); 1481161330Sjhb 1482161330Sjhb return ret_val; 1483166730Sjkim} 1484161330Sjhb 1485161330Sjhb/** 1486161330Sjhb * e1000_init_hw_82575 - Initialize hardware 1487161330Sjhb * @hw: pointer to the HW structure 1488161330Sjhb * 1489161330Sjhb * This inits the hardware readying it for operation. 1490161330Sjhb **/ 1491184790Seds32 e1000_init_hw_82575(struct e1000_hw *hw) 1492161330Sjhb{ 1493161330Sjhb struct e1000_mac_info *mac = &hw->mac; 1494161330Sjhb s32 ret_val; 1495161330Sjhb u16 i, rar_count = mac->rar_entry_count; 1496161330Sjhb 1497161330Sjhb DEBUGFUNC("e1000_init_hw_82575"); 1498161330Sjhb 1499161330Sjhb /* Initialize identification LED */ 1500161330Sjhb ret_val = mac->ops.id_led_init(hw); 1501161330Sjhb if (ret_val) { 1502161330Sjhb DEBUGOUT("Error initializing identification LED\n"); 1503161330Sjhb /* This is not fatal and we should not stop init due to this */ 1504161330Sjhb } 1505161330Sjhb 1506161330Sjhb /* Disabling VLAN filtering */ 1507165610Srwatson DEBUGOUT("Initializing the IEEE VLAN\n"); 1508161330Sjhb mac->ops.clear_vfta(hw); 1509161330Sjhb 1510161330Sjhb /* Setup the receive address */ 1511161330Sjhb e1000_init_rx_addrs_generic(hw, rar_count); 1512161330Sjhb 1513161330Sjhb /* Zero out the Multicast HASH table */ 1514161330Sjhb DEBUGOUT("Zeroing the MTA\n"); 1515161330Sjhb for (i = 0; i < mac->mta_reg_count; i++) 1516161330Sjhb E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1517161330Sjhb 1518161330Sjhb /* Zero out the Unicast HASH table */ 1519161330Sjhb DEBUGOUT("Zeroing the UTA\n"); 1520161330Sjhb for (i = 0; i < mac->uta_reg_count; i++) 1521161330Sjhb E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1522161330Sjhb 1523161330Sjhb /* Setup link and flow control */ 1524161330Sjhb ret_val = mac->ops.setup_link(hw); 1525161330Sjhb 1526161330Sjhb /* Set the default MTU size */ 1527161330Sjhb hw->dev_spec._82575.mtu = 1500; 1528161330Sjhb 1529161330Sjhb /* 1530161330Sjhb * Clear all of the statistics registers (clear on read). It is 1531161330Sjhb * important that we do this after we have tried to establish link 1532161330Sjhb * because the symbol error count will increment wildly if there 1533161330Sjhb * is no link. 1534161330Sjhb */ 1535161330Sjhb e1000_clear_hw_cntrs_82575(hw); 1536161330Sjhb 1537161330Sjhb return ret_val; 1538161330Sjhb} 1539161330Sjhb 1540161330Sjhb/** 1541161330Sjhb * e1000_setup_copper_link_82575 - Configure copper link settings 1542161330Sjhb * @hw: pointer to the HW structure 1543161330Sjhb * 1544161330Sjhb * Configures the link for auto-neg or forced speed and duplex. Then we check 1545161330Sjhb * for link, once link is established calls to configure collision distance 1546161330Sjhb * and flow control are called. 1547161330Sjhb **/ 1548161330Sjhbstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1549161330Sjhb{ 1550161330Sjhb u32 ctrl; 1551161330Sjhb s32 ret_val; 1552161330Sjhb u32 phpm_reg; 1553161330Sjhb 1554161330Sjhb DEBUGFUNC("e1000_setup_copper_link_82575"); 1555161330Sjhb 1556161330Sjhb ctrl = E1000_READ_REG(hw, E1000_CTRL); 1557161330Sjhb ctrl |= E1000_CTRL_SLU; 1558161330Sjhb ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1559161330Sjhb E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1560161330Sjhb 1561161330Sjhb /* Clear Go Link Disconnect bit on supported devices */ 1562165610Srwatson switch (hw->mac.type) { 1563161330Sjhb case e1000_82580: 1564161330Sjhb case e1000_i350: 1565161330Sjhb case e1000_i210: 1566161330Sjhb case e1000_i211: 1567161330Sjhb phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1568161330Sjhb phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1569161330Sjhb E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1570161330Sjhb break; 1571161330Sjhb default: 1572161330Sjhb break; 1573161330Sjhb } 1574161330Sjhb 1575161330Sjhb ret_val = e1000_setup_serdes_link_82575(hw); 1576161330Sjhb if (ret_val) 1577161330Sjhb goto out; 1578161330Sjhb 1579177258Srdivacky if (e1000_sgmii_active_82575(hw)) { 1580171999Skib /* allow time for SFP cage time to power up phy */ 1581168036Sjkim msec_delay(300); 1582161330Sjhb 1583161330Sjhb ret_val = hw->phy.ops.reset(hw); 1584161330Sjhb if (ret_val) { 1585161330Sjhb DEBUGOUT("Error resetting the PHY.\n"); 1586161330Sjhb goto out; 1587161330Sjhb } 1588161330Sjhb } 1589161330Sjhb switch (hw->phy.type) { 1590161330Sjhb case e1000_phy_i210: 1591161330Sjhb case e1000_phy_m88: 1592161330Sjhb switch (hw->phy.id) { 1593161330Sjhb case I347AT4_E_PHY_ID: 1594161330Sjhb case M88E1112_E_PHY_ID: 1595161330Sjhb case M88E1340M_E_PHY_ID: 1596161330Sjhb case M88E1543_E_PHY_ID: 1597161330Sjhb case M88E1512_E_PHY_ID: 1598161330Sjhb case I210_I_PHY_ID: 1599165610Srwatson ret_val = e1000_copper_link_setup_m88_gen2(hw); 1600165610Srwatson break; 1601161330Sjhb default: 1602165610Srwatson ret_val = e1000_copper_link_setup_m88(hw); 1603161330Sjhb break; 1604161330Sjhb } 1605161330Sjhb break; 1606161330Sjhb case e1000_phy_igp_3: 1607161330Sjhb ret_val = e1000_copper_link_setup_igp(hw); 1608161330Sjhb break; 1609161330Sjhb case e1000_phy_82580: 1610161330Sjhb ret_val = e1000_copper_link_setup_82577(hw); 1611161330Sjhb break; 1612161330Sjhb default: 1613161330Sjhb ret_val = -E1000_ERR_PHY; 1614161330Sjhb break; 1615161330Sjhb } 1616161330Sjhb 1617161330Sjhb if (ret_val) 1618161330Sjhb goto out; 1619161330Sjhb 1620161330Sjhb ret_val = e1000_setup_copper_link_generic(hw); 1621161330Sjhbout: 1622161330Sjhb return ret_val; 1623161330Sjhb} 1624168014Sjulian 1625177999Skib/** 1626177999Skib * e1000_setup_serdes_link_82575 - Setup link for serdes 1627177999Skib * @hw: pointer to the HW structure 1628177999Skib * 1629177999Skib * Configure the physical coding sub-layer (PCS) link. The PCS link is 1630177999Skib * used on copper connections where the serialized gigabit media independent 1631177999Skib * interface (sgmii), or serdes fiber is being used. Configures the link 1632177999Skib * for auto-negotiation or forces speed/duplex. 1633177999Skib **/ 1634177999Skibstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1635177999Skib{ 1636177999Skib u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1637161330Sjhb bool pcs_autoneg; 1638161330Sjhb s32 ret_val = E1000_SUCCESS; 1639161330Sjhb u16 data; 1640178258Sjkim 1641178258Sjkim DEBUGFUNC("e1000_setup_serdes_link_82575"); 1642178258Sjkim 1643178258Sjkim if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1644178258Sjkim !e1000_sgmii_active_82575(hw)) 1645178258Sjkim return ret_val; 1646232800Snetchild 1647232800Snetchild /* 1648232800Snetchild * On the 82575, SerDes loopback mode persists until it is 1649232800Snetchild * explicitly turned off or a power cycle is performed. A read to 1650232800Snetchild * the register does not indicate its status. Therefore, we ensure 1651232800Snetchild * loopback mode is disabled during initialization. 1652232800Snetchild */ 1653232800Snetchild E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1654232800Snetchild 1655232800Snetchild /* power on the sfp cage if present */ 1656232800Snetchild ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1657232800Snetchild ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1658232800Snetchild E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1659232800Snetchild 1660232800Snetchild ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1661232800Snetchild ctrl_reg |= E1000_CTRL_SLU; 1662232800Snetchild 1663232800Snetchild /* set both sw defined pins on 82575/82576*/ 1664232800Snetchild if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1665232800Snetchild ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1666232800Snetchild 1667232800Snetchild reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1668232800Snetchild 1669232800Snetchild /* default pcs_autoneg to the same setting as mac autoneg */ 1670232800Snetchild pcs_autoneg = hw->mac.autoneg; 1671232800Snetchild 1672232800Snetchild switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1673232800Snetchild case E1000_CTRL_EXT_LINK_MODE_SGMII: 1674232800Snetchild /* sgmii mode lets the phy handle forcing speed/duplex */ 1675232800Snetchild pcs_autoneg = TRUE; 1676232800Snetchild /* autoneg time out should be disabled for SGMII mode */ 1677232800Snetchild reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1678161330Sjhb break; 1679133819Stjr case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1680133819Stjr /* disable PCS autoneg and support parallel detect only */ 1681133819Stjr pcs_autoneg = FALSE; 1682133819Stjr /* fall through to default case */ 1683133819Stjr default: 1684 if (hw->mac.type == e1000_82575 || 1685 hw->mac.type == e1000_82576) { 1686 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1687 if (ret_val) { 1688 DEBUGOUT("NVM Read Error\n"); 1689 return ret_val; 1690 } 1691 1692 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1693 pcs_autoneg = FALSE; 1694 } 1695 1696 /* 1697 * non-SGMII modes only supports a speed of 1000/Full for the 1698 * link so it is best to just force the MAC and let the pcs 1699 * link either autoneg or be forced to 1000/Full 1700 */ 1701 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1702 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1703 1704 /* set speed of 1000/Full if speed/duplex is forced */ 1705 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1706 break; 1707 } 1708 1709 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1710 1711 /* 1712 * New SerDes mode allows for forcing speed or autonegotiating speed 1713 * at 1gb. Autoneg should be default set by most drivers. This is the 1714 * mode that will be compatible with older link partners and switches. 1715 * However, both are supported by the hardware and some drivers/tools. 1716 */ 1717 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1718 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1719 1720 if (pcs_autoneg) { 1721 /* Set PCS register for autoneg */ 1722 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1723 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1724 1725 /* Disable force flow control for autoneg */ 1726 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1727 1728 /* Configure flow control advertisement for autoneg */ 1729 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1730 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1731 1732 switch (hw->fc.requested_mode) { 1733 case e1000_fc_full: 1734 case e1000_fc_rx_pause: 1735 anadv_reg |= E1000_TXCW_ASM_DIR; 1736 anadv_reg |= E1000_TXCW_PAUSE; 1737 break; 1738 case e1000_fc_tx_pause: 1739 anadv_reg |= E1000_TXCW_ASM_DIR; 1740 break; 1741 default: 1742 break; 1743 } 1744 1745 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); 1746 1747 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1748 } else { 1749 /* Set PCS register for forced link */ 1750 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1751 1752 /* Force flow control for forced link */ 1753 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1754 1755 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1756 } 1757 1758 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1759 1760 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) 1761 e1000_force_mac_fc_generic(hw); 1762 1763 return ret_val; 1764} 1765 1766/** 1767 * e1000_get_media_type_82575 - derives current media type. 1768 * @hw: pointer to the HW structure 1769 * 1770 * The media type is chosen reflecting few settings. 1771 * The following are taken into account: 1772 * - link mode set in the current port Init Control Word #3 1773 * - current link mode settings in CSR register 1774 * - MDIO vs. I2C PHY control interface chosen 1775 * - SFP module media type 1776 **/ 1777static s32 e1000_get_media_type_82575(struct e1000_hw *hw) 1778{ 1779 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1780 s32 ret_val = E1000_SUCCESS; 1781 u32 ctrl_ext = 0; 1782 u32 link_mode = 0; 1783 1784 /* Set internal phy as default */ 1785 dev_spec->sgmii_active = FALSE; 1786 dev_spec->module_plugged = FALSE; 1787 1788 /* Get CSR setting */ 1789 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1790 1791 /* extract link mode setting */ 1792 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 1793 1794 switch (link_mode) { 1795 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1796 hw->phy.media_type = e1000_media_type_internal_serdes; 1797 break; 1798 case E1000_CTRL_EXT_LINK_MODE_GMII: 1799 hw->phy.media_type = e1000_media_type_copper; 1800 break; 1801 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1802 /* Get phy control interface type set (MDIO vs. I2C)*/ 1803 if (e1000_sgmii_uses_mdio_82575(hw)) { 1804 hw->phy.media_type = e1000_media_type_copper; 1805 dev_spec->sgmii_active = TRUE; 1806 break; 1807 } 1808 /* fall through for I2C based SGMII */ 1809 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1810 /* read media type from SFP EEPROM */ 1811 ret_val = e1000_set_sfp_media_type_82575(hw); 1812 if ((ret_val != E1000_SUCCESS) || 1813 (hw->phy.media_type == e1000_media_type_unknown)) { 1814 /* 1815 * If media type was not identified then return media 1816 * type defined by the CTRL_EXT settings. 1817 */ 1818 hw->phy.media_type = e1000_media_type_internal_serdes; 1819 1820 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 1821 hw->phy.media_type = e1000_media_type_copper; 1822 dev_spec->sgmii_active = TRUE; 1823 } 1824 1825 break; 1826 } 1827 1828 /* do not change link mode for 100BaseFX */ 1829 if (dev_spec->eth_flags.e100_base_fx) 1830 break; 1831 1832 /* change current link mode setting */ 1833 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1834 1835 if (hw->phy.media_type == e1000_media_type_copper) 1836 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 1837 else 1838 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1839 1840 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1841 1842 break; 1843 } 1844 1845 return ret_val; 1846} 1847 1848/** 1849 * e1000_set_sfp_media_type_82575 - derives SFP module media type. 1850 * @hw: pointer to the HW structure 1851 * 1852 * The media type is chosen based on SFP module. 1853 * compatibility flags retrieved from SFP ID EEPROM. 1854 **/ 1855static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) 1856{ 1857 s32 ret_val = E1000_ERR_CONFIG; 1858 u32 ctrl_ext = 0; 1859 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1860 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; 1861 u8 tranceiver_type = 0; 1862 s32 timeout = 3; 1863 1864 /* Turn I2C interface ON and power on sfp cage */ 1865 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1866 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1867 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 1868 1869 E1000_WRITE_FLUSH(hw); 1870 1871 /* Read SFP module data */ 1872 while (timeout) { 1873 ret_val = e1000_read_sfp_data_byte(hw, 1874 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 1875 &tranceiver_type); 1876 if (ret_val == E1000_SUCCESS) 1877 break; 1878 msec_delay(100); 1879 timeout--; 1880 } 1881 if (ret_val != E1000_SUCCESS) 1882 goto out; 1883 1884 ret_val = e1000_read_sfp_data_byte(hw, 1885 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 1886 (u8 *)eth_flags); 1887 if (ret_val != E1000_SUCCESS) 1888 goto out; 1889 1890 /* Check if there is some SFP module plugged and powered */ 1891 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 1892 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 1893 dev_spec->module_plugged = TRUE; 1894 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 1895 hw->phy.media_type = e1000_media_type_internal_serdes; 1896 } else if (eth_flags->e100_base_fx) { 1897 dev_spec->sgmii_active = TRUE; 1898 hw->phy.media_type = e1000_media_type_internal_serdes; 1899 } else if (eth_flags->e1000_base_t) { 1900 dev_spec->sgmii_active = TRUE; 1901 hw->phy.media_type = e1000_media_type_copper; 1902 } else { 1903 hw->phy.media_type = e1000_media_type_unknown; 1904 DEBUGOUT("PHY module has not been recognized\n"); 1905 goto out; 1906 } 1907 } else { 1908 hw->phy.media_type = e1000_media_type_unknown; 1909 } 1910 ret_val = E1000_SUCCESS; 1911out: 1912 /* Restore I2C interface setting */ 1913 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1914 return ret_val; 1915} 1916 1917/** 1918 * e1000_valid_led_default_82575 - Verify a valid default LED config 1919 * @hw: pointer to the HW structure 1920 * @data: pointer to the NVM (EEPROM) 1921 * 1922 * Read the EEPROM for the current default LED configuration. If the 1923 * LED configuration is not valid, set to a valid LED configuration. 1924 **/ 1925static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1926{ 1927 s32 ret_val; 1928 1929 DEBUGFUNC("e1000_valid_led_default_82575"); 1930 1931 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1932 if (ret_val) { 1933 DEBUGOUT("NVM Read Error\n"); 1934 goto out; 1935 } 1936 1937 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1938 switch (hw->phy.media_type) { 1939 case e1000_media_type_internal_serdes: 1940 *data = ID_LED_DEFAULT_82575_SERDES; 1941 break; 1942 case e1000_media_type_copper: 1943 default: 1944 *data = ID_LED_DEFAULT; 1945 break; 1946 } 1947 } 1948out: 1949 return ret_val; 1950} 1951 1952/** 1953 * e1000_sgmii_active_82575 - Return sgmii state 1954 * @hw: pointer to the HW structure 1955 * 1956 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1957 * which can be enabled for use in the embedded applications. Simply 1958 * return the current state of the sgmii interface. 1959 **/ 1960static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1961{ 1962 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1963 return dev_spec->sgmii_active; 1964} 1965 1966/** 1967 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1968 * @hw: pointer to the HW structure 1969 * 1970 * Inits recommended HW defaults after a reset when there is no EEPROM 1971 * detected. This is only for the 82575. 1972 **/ 1973static s32 e1000_reset_init_script_82575(struct e1000_hw *hw) 1974{ 1975 DEBUGFUNC("e1000_reset_init_script_82575"); 1976 1977 if (hw->mac.type == e1000_82575) { 1978 DEBUGOUT("Running reset init script for 82575\n"); 1979 /* SerDes configuration via SERDESCTRL */ 1980 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1981 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1982 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1983 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1984 1985 /* CCM configuration via CCMCTL register */ 1986 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1987 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1988 1989 /* PCIe lanes configuration */ 1990 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1991 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1992 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1993 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1994 1995 /* PCIe PLL Configuration */ 1996 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1997 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1998 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1999 } 2000 2001 return E1000_SUCCESS; 2002} 2003 2004/** 2005 * e1000_read_mac_addr_82575 - Read device MAC address 2006 * @hw: pointer to the HW structure 2007 **/ 2008static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 2009{ 2010 s32 ret_val; 2011 2012 DEBUGFUNC("e1000_read_mac_addr_82575"); 2013 2014 /* 2015 * If there's an alternate MAC address place it in RAR0 2016 * so that it will override the Si installed default perm 2017 * address. 2018 */ 2019 ret_val = e1000_check_alt_mac_addr_generic(hw); 2020 if (ret_val) 2021 goto out; 2022 2023 ret_val = e1000_read_mac_addr_generic(hw); 2024 2025out: 2026 return ret_val; 2027} 2028 2029/** 2030 * e1000_config_collision_dist_82575 - Configure collision distance 2031 * @hw: pointer to the HW structure 2032 * 2033 * Configures the collision distance to the default value and is used 2034 * during link setup. 2035 **/ 2036static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 2037{ 2038 u32 tctl_ext; 2039 2040 DEBUGFUNC("e1000_config_collision_dist_82575"); 2041 2042 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 2043 2044 tctl_ext &= ~E1000_TCTL_EXT_COLD; 2045 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 2046 2047 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 2048 E1000_WRITE_FLUSH(hw); 2049} 2050 2051/** 2052 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 2053 * @hw: pointer to the HW structure 2054 * 2055 * In the case of a PHY power down to save power, or to turn off link during a 2056 * driver unload, or wake on lan is not enabled, remove the link. 2057 **/ 2058static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 2059{ 2060 struct e1000_phy_info *phy = &hw->phy; 2061 2062 if (!(phy->ops.check_reset_block)) 2063 return; 2064 2065 /* If the management interface is not enabled, then power down */ 2066 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 2067 e1000_power_down_phy_copper(hw); 2068 2069 return; 2070} 2071 2072/** 2073 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 2074 * @hw: pointer to the HW structure 2075 * 2076 * Clears the hardware counters by reading the counter registers. 2077 **/ 2078static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 2079{ 2080 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 2081 2082 e1000_clear_hw_cntrs_base_generic(hw); 2083 2084 E1000_READ_REG(hw, E1000_PRC64); 2085 E1000_READ_REG(hw, E1000_PRC127); 2086 E1000_READ_REG(hw, E1000_PRC255); 2087 E1000_READ_REG(hw, E1000_PRC511); 2088 E1000_READ_REG(hw, E1000_PRC1023); 2089 E1000_READ_REG(hw, E1000_PRC1522); 2090 E1000_READ_REG(hw, E1000_PTC64); 2091 E1000_READ_REG(hw, E1000_PTC127); 2092 E1000_READ_REG(hw, E1000_PTC255); 2093 E1000_READ_REG(hw, E1000_PTC511); 2094 E1000_READ_REG(hw, E1000_PTC1023); 2095 E1000_READ_REG(hw, E1000_PTC1522); 2096 2097 E1000_READ_REG(hw, E1000_ALGNERRC); 2098 E1000_READ_REG(hw, E1000_RXERRC); 2099 E1000_READ_REG(hw, E1000_TNCRS); 2100 E1000_READ_REG(hw, E1000_CEXTERR); 2101 E1000_READ_REG(hw, E1000_TSCTC); 2102 E1000_READ_REG(hw, E1000_TSCTFC); 2103 2104 E1000_READ_REG(hw, E1000_MGTPRC); 2105 E1000_READ_REG(hw, E1000_MGTPDC); 2106 E1000_READ_REG(hw, E1000_MGTPTC); 2107 2108 E1000_READ_REG(hw, E1000_IAC); 2109 E1000_READ_REG(hw, E1000_ICRXOC); 2110 2111 E1000_READ_REG(hw, E1000_ICRXPTC); 2112 E1000_READ_REG(hw, E1000_ICRXATC); 2113 E1000_READ_REG(hw, E1000_ICTXPTC); 2114 E1000_READ_REG(hw, E1000_ICTXATC); 2115 E1000_READ_REG(hw, E1000_ICTXQEC); 2116 E1000_READ_REG(hw, E1000_ICTXQMTC); 2117 E1000_READ_REG(hw, E1000_ICRXDMTC); 2118 2119 E1000_READ_REG(hw, E1000_CBTMPC); 2120 E1000_READ_REG(hw, E1000_HTDPMC); 2121 E1000_READ_REG(hw, E1000_CBRMPC); 2122 E1000_READ_REG(hw, E1000_RPTHC); 2123 E1000_READ_REG(hw, E1000_HGPTC); 2124 E1000_READ_REG(hw, E1000_HTCBDPC); 2125 E1000_READ_REG(hw, E1000_HGORCL); 2126 E1000_READ_REG(hw, E1000_HGORCH); 2127 E1000_READ_REG(hw, E1000_HGOTCL); 2128 E1000_READ_REG(hw, E1000_HGOTCH); 2129 E1000_READ_REG(hw, E1000_LENERRS); 2130 2131 /* This register should not be read in copper configurations */ 2132 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 2133 e1000_sgmii_active_82575(hw)) 2134 E1000_READ_REG(hw, E1000_SCVPC); 2135} 2136 2137/** 2138 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 2139 * @hw: pointer to the HW structure 2140 * 2141 * After Rx enable, if manageability is enabled then there is likely some 2142 * bad data at the start of the fifo and possibly in the DMA fifo. This 2143 * function clears the fifos and flushes any packets that came in as rx was 2144 * being enabled. 2145 **/ 2146void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 2147{ 2148 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 2149 int i, ms_wait; 2150 2151 DEBUGFUNC("e1000_rx_fifo_flush_82575"); 2152 2153 /* disable IPv6 options as per hardware errata */ 2154 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2155 rfctl |= E1000_RFCTL_IPV6_EX_DIS; 2156 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2157 2158 if (hw->mac.type != e1000_82575 || 2159 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 2160 return; 2161 2162 /* Disable all Rx queues */ 2163 for (i = 0; i < 4; i++) { 2164 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 2165 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 2166 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 2167 } 2168 /* Poll all queues to verify they have shut down */ 2169 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 2170 msec_delay(1); 2171 rx_enabled = 0; 2172 for (i = 0; i < 4; i++) 2173 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 2174 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2175 break; 2176 } 2177 2178 if (ms_wait == 10) 2179 DEBUGOUT("Queue disable timed out after 10ms\n"); 2180 2181 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2182 * incoming packets are rejected. Set enable and wait 2ms so that 2183 * any packet that was coming in as RCTL.EN was set is flushed 2184 */ 2185 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2186 2187 rlpml = E1000_READ_REG(hw, E1000_RLPML); 2188 E1000_WRITE_REG(hw, E1000_RLPML, 0); 2189 2190 rctl = E1000_READ_REG(hw, E1000_RCTL); 2191 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2192 temp_rctl |= E1000_RCTL_LPE; 2193 2194 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 2195 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2196 E1000_WRITE_FLUSH(hw); 2197 msec_delay(2); 2198 2199 /* Enable Rx queues that were previously enabled and restore our 2200 * previous state 2201 */ 2202 for (i = 0; i < 4; i++) 2203 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 2204 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2205 E1000_WRITE_FLUSH(hw); 2206 2207 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 2208 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2209 2210 /* Flush receive errors generated by workaround */ 2211 E1000_READ_REG(hw, E1000_ROC); 2212 E1000_READ_REG(hw, E1000_RNBC); 2213 E1000_READ_REG(hw, E1000_MPC); 2214} 2215 2216/** 2217 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 2218 * @hw: pointer to the HW structure 2219 * 2220 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2221 * however the hardware default for these parts is 500us to 1ms which is less 2222 * than the 10ms recommended by the pci-e spec. To address this we need to 2223 * increase the value to either 10ms to 200ms for capability version 1 config, 2224 * or 16ms to 55ms for version 2. 2225 **/ 2226static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 2227{ 2228 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 2229 s32 ret_val = E1000_SUCCESS; 2230 u16 pcie_devctl2; 2231 2232 /* only take action if timeout value is defaulted to 0 */ 2233 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2234 goto out; 2235 2236 /* 2237 * if capababilities version is type 1 we can write the 2238 * timeout of 10ms to 200ms through the GCR register 2239 */ 2240 if (!(gcr & E1000_GCR_CAP_VER2)) { 2241 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2242 goto out; 2243 } 2244 2245 /* 2246 * for version 2 capabilities we need to write the config space 2247 * directly in order to set the completion timeout value for 2248 * 16ms to 55ms 2249 */ 2250 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2251 &pcie_devctl2); 2252 if (ret_val) 2253 goto out; 2254 2255 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2256 2257 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2258 &pcie_devctl2); 2259out: 2260 /* disable completion timeout resend */ 2261 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2262 2263 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2264 return ret_val; 2265} 2266 2267/** 2268 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2269 * @hw: pointer to the hardware struct 2270 * @enable: state to enter, either enabled or disabled 2271 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2272 * 2273 * enables/disables L2 switch anti-spoofing functionality. 2274 **/ 2275void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2276{ 2277 u32 reg_val, reg_offset; 2278 2279 switch (hw->mac.type) { 2280 case e1000_82576: 2281 reg_offset = E1000_DTXSWC; 2282 break; 2283 case e1000_i350: 2284 case e1000_i354: 2285 reg_offset = E1000_TXSWC; 2286 break; 2287 default: 2288 return; 2289 } 2290 2291 reg_val = E1000_READ_REG(hw, reg_offset); 2292 if (enable) { 2293 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2294 E1000_DTXSWC_VLAN_SPOOF_MASK); 2295 /* The PF can spoof - it has to in order to 2296 * support emulation mode NICs 2297 */ 2298 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2299 } else { 2300 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2301 E1000_DTXSWC_VLAN_SPOOF_MASK); 2302 } 2303 E1000_WRITE_REG(hw, reg_offset, reg_val); 2304} 2305 2306/** 2307 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 2308 * @hw: pointer to the hardware struct 2309 * @enable: state to enter, either enabled or disabled 2310 * 2311 * enables/disables L2 switch loopback functionality. 2312 **/ 2313void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2314{ 2315 u32 dtxswc; 2316 2317 switch (hw->mac.type) { 2318 case e1000_82576: 2319 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2320 if (enable) 2321 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2322 else 2323 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2324 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2325 break; 2326 case e1000_i350: 2327 case e1000_i354: 2328 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2329 if (enable) 2330 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2331 else 2332 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2333 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2334 break; 2335 default: 2336 /* Currently no other hardware supports loopback */ 2337 break; 2338 } 2339 2340 2341} 2342 2343/** 2344 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 2345 * @hw: pointer to the hardware struct 2346 * @enable: state to enter, either enabled or disabled 2347 * 2348 * enables/disables replication of packets across multiple pools. 2349 **/ 2350void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2351{ 2352 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 2353 2354 if (enable) 2355 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2356 else 2357 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2358 2359 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 2360} 2361 2362/** 2363 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 2364 * @hw: pointer to the HW structure 2365 * @offset: register offset to be read 2366 * @data: pointer to the read data 2367 * 2368 * Reads the MDI control register in the PHY at offset and stores the 2369 * information read to data. 2370 **/ 2371static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2372{ 2373 s32 ret_val; 2374 2375 DEBUGFUNC("e1000_read_phy_reg_82580"); 2376 2377 ret_val = hw->phy.ops.acquire(hw); 2378 if (ret_val) 2379 goto out; 2380 2381 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 2382 2383 hw->phy.ops.release(hw); 2384 2385out: 2386 return ret_val; 2387} 2388 2389/** 2390 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 2391 * @hw: pointer to the HW structure 2392 * @offset: register offset to write to 2393 * @data: data to write to register at offset 2394 * 2395 * Writes data to MDI control register in the PHY at offset. 2396 **/ 2397static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2398{ 2399 s32 ret_val; 2400 2401 DEBUGFUNC("e1000_write_phy_reg_82580"); 2402 2403 ret_val = hw->phy.ops.acquire(hw); 2404 if (ret_val) 2405 goto out; 2406 2407 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 2408 2409 hw->phy.ops.release(hw); 2410 2411out: 2412 return ret_val; 2413} 2414 2415/** 2416 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2417 * @hw: pointer to the HW structure 2418 * 2419 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2420 * the values found in the EEPROM. This addresses an issue in which these 2421 * bits are not restored from EEPROM after reset. 2422 **/ 2423static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 2424{ 2425 s32 ret_val = E1000_SUCCESS; 2426 u32 mdicnfg; 2427 u16 nvm_data = 0; 2428 2429 DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2430 2431 if (hw->mac.type != e1000_82580) 2432 goto out; 2433 if (!e1000_sgmii_active_82575(hw)) 2434 goto out; 2435 2436 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2437 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2438 &nvm_data); 2439 if (ret_val) { 2440 DEBUGOUT("NVM Read Error\n"); 2441 goto out; 2442 } 2443 2444 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2445 if (nvm_data & NVM_WORD24_EXT_MDIO) 2446 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2447 if (nvm_data & NVM_WORD24_COM_MDIO) 2448 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2449 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2450out: 2451 return ret_val; 2452} 2453 2454/** 2455 * e1000_reset_hw_82580 - Reset hardware 2456 * @hw: pointer to the HW structure 2457 * 2458 * This resets function or entire device (all ports, etc.) 2459 * to a known state. 2460 **/ 2461static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2462{ 2463 s32 ret_val = E1000_SUCCESS; 2464 /* BH SW mailbox bit in SW_FW_SYNC */ 2465 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2466 u32 ctrl; 2467 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2468 2469 DEBUGFUNC("e1000_reset_hw_82580"); 2470 2471 hw->dev_spec._82575.global_device_reset = FALSE; 2472 2473 /* 82580 does not reliably do global_device_reset due to hw errata */ 2474 if (hw->mac.type == e1000_82580) 2475 global_device_reset = FALSE; 2476 2477 /* Get current control state. */ 2478 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2479 2480 /* 2481 * Prevent the PCI-E bus from sticking if there is no TLP connection 2482 * on the last TLP read/write transaction when MAC is reset. 2483 */ 2484 ret_val = e1000_disable_pcie_master_generic(hw); 2485 if (ret_val) 2486 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2487 2488 DEBUGOUT("Masking off all interrupts\n"); 2489 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2490 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2491 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2492 E1000_WRITE_FLUSH(hw); 2493 2494 msec_delay(10); 2495 2496 /* Determine whether or not a global dev reset is requested */ 2497 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, 2498 swmbsw_mask)) 2499 global_device_reset = FALSE; 2500 2501 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & 2502 E1000_STAT_DEV_RST_SET)) 2503 ctrl |= E1000_CTRL_DEV_RST; 2504 else 2505 ctrl |= E1000_CTRL_RST; 2506 2507 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2508 2509 switch (hw->device_id) { 2510 case E1000_DEV_ID_DH89XXCC_SGMII: 2511 break; 2512 default: 2513 E1000_WRITE_FLUSH(hw); 2514 break; 2515 } 2516 2517 /* Add delay to insure DEV_RST or RST has time to complete */ 2518 msec_delay(5); 2519 2520 ret_val = e1000_get_auto_rd_done_generic(hw); 2521 if (ret_val) { 2522 /* 2523 * When auto config read does not complete, do not 2524 * return with an error. This can happen in situations 2525 * where there is no eeprom and prevents getting link. 2526 */ 2527 DEBUGOUT("Auto Read Done did not complete\n"); 2528 } 2529 2530 /* clear global device reset status bit */ 2531 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2532 2533 /* Clear any pending interrupt events. */ 2534 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2535 E1000_READ_REG(hw, E1000_ICR); 2536 2537 ret_val = e1000_reset_mdicnfg_82580(hw); 2538 if (ret_val) 2539 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2540 2541 /* Install any alternate MAC address into RAR0 */ 2542 ret_val = e1000_check_alt_mac_addr_generic(hw); 2543 2544 /* Release semaphore */ 2545 if (global_device_reset) 2546 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2547 2548 return ret_val; 2549} 2550 2551/** 2552 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2553 * @data: data received by reading RXPBS register 2554 * 2555 * The 82580 uses a table based approach for packet buffer allocation sizes. 2556 * This function converts the retrieved value into the correct table value 2557 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2558 * 0x0 36 72 144 1 2 4 8 16 2559 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2560 */ 2561u16 e1000_rxpbs_adjust_82580(u32 data) 2562{ 2563 u16 ret_val = 0; 2564 2565 if (data < E1000_82580_RXPBS_TABLE_SIZE) 2566 ret_val = e1000_82580_rxpbs_table[data]; 2567 2568 return ret_val; 2569} 2570 2571/** 2572 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2573 * checksum 2574 * @hw: pointer to the HW structure 2575 * @offset: offset in words of the checksum protected region 2576 * 2577 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2578 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2579 **/ 2580s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2581{ 2582 s32 ret_val = E1000_SUCCESS; 2583 u16 checksum = 0; 2584 u16 i, nvm_data; 2585 2586 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2587 2588 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2589 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2590 if (ret_val) { 2591 DEBUGOUT("NVM Read Error\n"); 2592 goto out; 2593 } 2594 checksum += nvm_data; 2595 } 2596 2597 if (checksum != (u16) NVM_SUM) { 2598 DEBUGOUT("NVM Checksum Invalid\n"); 2599 ret_val = -E1000_ERR_NVM; 2600 goto out; 2601 } 2602 2603out: 2604 return ret_val; 2605} 2606 2607/** 2608 * e1000_update_nvm_checksum_with_offset - Update EEPROM 2609 * checksum 2610 * @hw: pointer to the HW structure 2611 * @offset: offset in words of the checksum protected region 2612 * 2613 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2614 * up to the checksum. Then calculates the EEPROM checksum and writes the 2615 * value to the EEPROM. 2616 **/ 2617s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2618{ 2619 s32 ret_val; 2620 u16 checksum = 0; 2621 u16 i, nvm_data; 2622 2623 DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2624 2625 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2626 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2627 if (ret_val) { 2628 DEBUGOUT("NVM Read Error while updating checksum.\n"); 2629 goto out; 2630 } 2631 checksum += nvm_data; 2632 } 2633 checksum = (u16) NVM_SUM - checksum; 2634 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2635 &checksum); 2636 if (ret_val) 2637 DEBUGOUT("NVM Write Error while updating checksum.\n"); 2638 2639out: 2640 return ret_val; 2641} 2642 2643/** 2644 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2645 * @hw: pointer to the HW structure 2646 * 2647 * Calculates the EEPROM section checksum by reading/adding each word of 2648 * the EEPROM and then verifies that the sum of the EEPROM is 2649 * equal to 0xBABA. 2650 **/ 2651static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2652{ 2653 s32 ret_val; 2654 u16 eeprom_regions_count = 1; 2655 u16 j, nvm_data; 2656 u16 nvm_offset; 2657 2658 DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2659 2660 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2661 if (ret_val) { 2662 DEBUGOUT("NVM Read Error\n"); 2663 goto out; 2664 } 2665 2666 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2667 /* if chekcsums compatibility bit is set validate checksums 2668 * for all 4 ports. */ 2669 eeprom_regions_count = 4; 2670 } 2671 2672 for (j = 0; j < eeprom_regions_count; j++) { 2673 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2674 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2675 nvm_offset); 2676 if (ret_val != E1000_SUCCESS) 2677 goto out; 2678 } 2679 2680out: 2681 return ret_val; 2682} 2683 2684/** 2685 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2686 * @hw: pointer to the HW structure 2687 * 2688 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2689 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2690 * checksum and writes the value to the EEPROM. 2691 **/ 2692static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2693{ 2694 s32 ret_val; 2695 u16 j, nvm_data; 2696 u16 nvm_offset; 2697 2698 DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2699 2700 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2701 if (ret_val) { 2702 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); 2703 goto out; 2704 } 2705 2706 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { 2707 /* set compatibility bit to validate checksums appropriately */ 2708 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2709 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2710 &nvm_data); 2711 if (ret_val) { 2712 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); 2713 goto out; 2714 } 2715 } 2716 2717 for (j = 0; j < 4; j++) { 2718 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2719 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2720 if (ret_val) 2721 goto out; 2722 } 2723 2724out: 2725 return ret_val; 2726} 2727 2728/** 2729 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2730 * @hw: pointer to the HW structure 2731 * 2732 * Calculates the EEPROM section checksum by reading/adding each word of 2733 * the EEPROM and then verifies that the sum of the EEPROM is 2734 * equal to 0xBABA. 2735 **/ 2736static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2737{ 2738 s32 ret_val = E1000_SUCCESS; 2739 u16 j; 2740 u16 nvm_offset; 2741 2742 DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2743 2744 for (j = 0; j < 4; j++) { 2745 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2746 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2747 nvm_offset); 2748 if (ret_val != E1000_SUCCESS) 2749 goto out; 2750 } 2751 2752out: 2753 return ret_val; 2754} 2755 2756/** 2757 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2758 * @hw: pointer to the HW structure 2759 * 2760 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2761 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2762 * checksum and writes the value to the EEPROM. 2763 **/ 2764static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2765{ 2766 s32 ret_val = E1000_SUCCESS; 2767 u16 j; 2768 u16 nvm_offset; 2769 2770 DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2771 2772 for (j = 0; j < 4; j++) { 2773 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2774 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2775 if (ret_val != E1000_SUCCESS) 2776 goto out; 2777 } 2778 2779out: 2780 return ret_val; 2781} 2782 2783/** 2784 * __e1000_access_emi_reg - Read/write EMI register 2785 * @hw: pointer to the HW structure 2786 * @addr: EMI address to program 2787 * @data: pointer to value to read/write from/to the EMI address 2788 * @read: boolean flag to indicate read or write 2789 **/ 2790static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address, 2791 u16 *data, bool read) 2792{ 2793 s32 ret_val; 2794 2795 DEBUGFUNC("__e1000_access_emi_reg"); 2796 2797 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2798 if (ret_val) 2799 return ret_val; 2800 2801 if (read) 2802 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2803 else 2804 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2805 2806 return ret_val; 2807} 2808 2809/** 2810 * e1000_read_emi_reg - Read Extended Management Interface register 2811 * @hw: pointer to the HW structure 2812 * @addr: EMI address to program 2813 * @data: value to be read from the EMI address 2814 **/ 2815s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2816{ 2817 DEBUGFUNC("e1000_read_emi_reg"); 2818 2819 return __e1000_access_emi_reg(hw, addr, data, TRUE); 2820} 2821 2822/** 2823 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY 2824 * @hw: pointer to the HW structure 2825 * 2826 * Initialize Marvell 1512 to work correctly with Avoton. 2827 **/ 2828s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw) 2829{ 2830 struct e1000_phy_info *phy = &hw->phy; 2831 s32 ret_val = E1000_SUCCESS; 2832 2833 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 2834 2835 /* Check if this is correct PHY. */ 2836 if (phy->id != M88E1512_E_PHY_ID) 2837 goto out; 2838 2839 /* Switch to PHY page 0xFF. */ 2840 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2841 if (ret_val) 2842 goto out; 2843 2844 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2845 if (ret_val) 2846 goto out; 2847 2848 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2849 if (ret_val) 2850 goto out; 2851 2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2853 if (ret_val) 2854 goto out; 2855 2856 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2857 if (ret_val) 2858 goto out; 2859 2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2861 if (ret_val) 2862 goto out; 2863 2864 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2865 if (ret_val) 2866 goto out; 2867 2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); 2869 if (ret_val) 2870 goto out; 2871 2872 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2873 if (ret_val) 2874 goto out; 2875 2876 /* Switch to PHY page 0xFB. */ 2877 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2878 if (ret_val) 2879 goto out; 2880 2881 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); 2882 if (ret_val) 2883 goto out; 2884 2885 /* Switch to PHY page 0x12. */ 2886 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2887 if (ret_val) 2888 goto out; 2889 2890 /* Change mode to SGMII-to-Copper */ 2891 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2892 if (ret_val) 2893 goto out; 2894 2895 /* Return the PHY to page 0. */ 2896 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2897 if (ret_val) 2898 goto out; 2899 2900 ret_val = phy->ops.commit(hw); 2901 if (ret_val) { 2902 DEBUGOUT("Error committing the PHY changes\n"); 2903 return ret_val; 2904 } 2905 2906 msec_delay(1000); 2907out: 2908 return ret_val; 2909} 2910 2911/** 2912 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY 2913 * @hw: pointer to the HW structure 2914 * 2915 * Initialize Marvell 1543 to work correctly with Avoton. 2916 **/ 2917s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw) 2918{ 2919 struct e1000_phy_info *phy = &hw->phy; 2920 s32 ret_val = E1000_SUCCESS; 2921 2922 DEBUGFUNC("e1000_initialize_M88E1543_phy"); 2923 2924 /* Check if this is correct PHY. */ 2925 if (phy->id != M88E1543_E_PHY_ID) 2926 goto out; 2927 2928 /* Switch to PHY page 0xFF. */ 2929 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2930 if (ret_val) 2931 goto out; 2932 2933 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2934 if (ret_val) 2935 goto out; 2936 2937 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2938 if (ret_val) 2939 goto out; 2940 2941 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2942 if (ret_val) 2943 goto out; 2944 2945 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2946 if (ret_val) 2947 goto out; 2948 2949 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2950 if (ret_val) 2951 goto out; 2952 2953 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2954 if (ret_val) 2955 goto out; 2956 2957 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C); 2958 if (ret_val) 2959 goto out; 2960 2961 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2962 if (ret_val) 2963 goto out; 2964 2965 /* Switch to PHY page 0xFB. */ 2966 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2967 if (ret_val) 2968 goto out; 2969 2970 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D); 2971 if (ret_val) 2972 goto out; 2973 2974 /* Switch to PHY page 0x12. */ 2975 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2976 if (ret_val) 2977 goto out; 2978 2979 /* Change mode to SGMII-to-Copper */ 2980 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2981 if (ret_val) 2982 goto out; 2983 2984 /* Switch to PHY page 1. */ 2985 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1); 2986 if (ret_val) 2987 goto out; 2988 2989 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */ 2990 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140); 2991 if (ret_val) 2992 goto out; 2993 2994 /* Return the PHY to page 0. */ 2995 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2996 if (ret_val) 2997 goto out; 2998 2999 ret_val = phy->ops.commit(hw); 3000 if (ret_val) { 3001 DEBUGOUT("Error committing the PHY changes\n"); 3002 return ret_val; 3003 } 3004 3005 msec_delay(1000); 3006out: 3007 return ret_val; 3008} 3009 3010/** 3011 * e1000_set_eee_i350 - Enable/disable EEE support 3012 * @hw: pointer to the HW structure 3013 * @adv1g: boolean flag enabling 1G EEE advertisement 3014 * @adv100m: boolean flag enabling 100M EEE advertisement 3015 * 3016 * Enable/disable EEE based on setting in dev_spec structure. 3017 * 3018 **/ 3019s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) 3020{ 3021 u32 ipcnfg, eeer; 3022 3023 DEBUGFUNC("e1000_set_eee_i350"); 3024 3025 if ((hw->mac.type < e1000_i350) || 3026 (hw->phy.media_type != e1000_media_type_copper)) 3027 goto out; 3028 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 3029 eeer = E1000_READ_REG(hw, E1000_EEER); 3030 3031 /* enable or disable per user setting */ 3032 if (!(hw->dev_spec._82575.eee_disable)) { 3033 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); 3034 3035 if (adv100M) 3036 ipcnfg |= E1000_IPCNFG_EEE_100M_AN; 3037 else 3038 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; 3039 3040 if (adv1G) 3041 ipcnfg |= E1000_IPCNFG_EEE_1G_AN; 3042 else 3043 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; 3044 3045 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 3046 E1000_EEER_LPI_FC); 3047 3048 /* This bit should not be set in normal operation. */ 3049 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 3050 DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 3051 } else { 3052 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 3053 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 3054 E1000_EEER_LPI_FC); 3055 } 3056 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 3057 E1000_WRITE_REG(hw, E1000_EEER, eeer); 3058 E1000_READ_REG(hw, E1000_IPCNFG); 3059 E1000_READ_REG(hw, E1000_EEER); 3060out: 3061 3062 return E1000_SUCCESS; 3063} 3064 3065/** 3066 * e1000_set_eee_i354 - Enable/disable EEE support 3067 * @hw: pointer to the HW structure 3068 * @adv1g: boolean flag enabling 1G EEE advertisement 3069 * @adv100m: boolean flag enabling 100M EEE advertisement 3070 * 3071 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 3072 * 3073 **/ 3074s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) 3075{ 3076 struct e1000_phy_info *phy = &hw->phy; 3077 s32 ret_val = E1000_SUCCESS; 3078 u16 phy_data; 3079 3080 DEBUGFUNC("e1000_set_eee_i354"); 3081 3082 if ((hw->phy.media_type != e1000_media_type_copper) || 3083 ((phy->id != M88E1543_E_PHY_ID) && 3084 (phy->id != M88E1512_E_PHY_ID))) 3085 goto out; 3086 3087 if (!hw->dev_spec._82575.eee_disable) { 3088 /* Switch to PHY page 18. */ 3089 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 3090 if (ret_val) 3091 goto out; 3092 3093 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 3094 &phy_data); 3095 if (ret_val) 3096 goto out; 3097 3098 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 3099 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 3100 phy_data); 3101 if (ret_val) 3102 goto out; 3103 3104 /* Return the PHY to page 0. */ 3105 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 3106 if (ret_val) 3107 goto out; 3108 3109 /* Turn on EEE advertisement. */ 3110 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3111 E1000_EEE_ADV_DEV_I354, 3112 &phy_data); 3113 if (ret_val) 3114 goto out; 3115 3116 if (adv100M) 3117 phy_data |= E1000_EEE_ADV_100_SUPPORTED; 3118 else 3119 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 3120 3121 if (adv1G) 3122 phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 3123 else 3124 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 3125 3126 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3127 E1000_EEE_ADV_DEV_I354, 3128 phy_data); 3129 } else { 3130 /* Turn off EEE advertisement. */ 3131 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3132 E1000_EEE_ADV_DEV_I354, 3133 &phy_data); 3134 if (ret_val) 3135 goto out; 3136 3137 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 3138 E1000_EEE_ADV_1000_SUPPORTED); 3139 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3140 E1000_EEE_ADV_DEV_I354, 3141 phy_data); 3142 } 3143 3144out: 3145 return ret_val; 3146} 3147 3148/** 3149 * e1000_get_eee_status_i354 - Get EEE status 3150 * @hw: pointer to the HW structure 3151 * @status: EEE status 3152 * 3153 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 3154 * been received. 3155 **/ 3156s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status) 3157{ 3158 struct e1000_phy_info *phy = &hw->phy; 3159 s32 ret_val = E1000_SUCCESS; 3160 u16 phy_data; 3161 3162 DEBUGFUNC("e1000_get_eee_status_i354"); 3163 3164 /* Check if EEE is supported on this device. */ 3165 if ((hw->phy.media_type != e1000_media_type_copper) || 3166 ((phy->id != M88E1543_E_PHY_ID) && 3167 (phy->id != M88E1512_E_PHY_ID))) 3168 goto out; 3169 3170 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 3171 E1000_PCS_STATUS_DEV_I354, 3172 &phy_data); 3173 if (ret_val) 3174 goto out; 3175 3176 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 3177 E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE; 3178 3179out: 3180 return ret_val; 3181} 3182 3183/* Due to a hw errata, if the host tries to configure the VFTA register 3184 * while performing queries from the BMC or DMA, then the VFTA in some 3185 * cases won't be written. 3186 */ 3187 3188/** 3189 * e1000_clear_vfta_i350 - Clear VLAN filter table 3190 * @hw: pointer to the HW structure 3191 * 3192 * Clears the register array which contains the VLAN filter table by 3193 * setting all the values to 0. 3194 **/ 3195void e1000_clear_vfta_i350(struct e1000_hw *hw) 3196{ 3197 u32 offset; 3198 int i; 3199 3200 DEBUGFUNC("e1000_clear_vfta_350"); 3201 3202 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 3203 for (i = 0; i < 10; i++) 3204 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 3205 3206 E1000_WRITE_FLUSH(hw); 3207 } 3208} 3209 3210/** 3211 * e1000_write_vfta_i350 - Write value to VLAN filter table 3212 * @hw: pointer to the HW structure 3213 * @offset: register offset in VLAN filter table 3214 * @value: register value written to VLAN filter table 3215 * 3216 * Writes value at the given offset in the register array which stores 3217 * the VLAN filter table. 3218 **/ 3219void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 3220{ 3221 int i; 3222 3223 DEBUGFUNC("e1000_write_vfta_350"); 3224 3225 for (i = 0; i < 10; i++) 3226 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 3227 3228 E1000_WRITE_FLUSH(hw); 3229} 3230 3231 3232/** 3233 * e1000_set_i2c_bb - Enable I2C bit-bang 3234 * @hw: pointer to the HW structure 3235 * 3236 * Enable I2C bit-bang interface 3237 * 3238 **/ 3239s32 e1000_set_i2c_bb(struct e1000_hw *hw) 3240{ 3241 s32 ret_val = E1000_SUCCESS; 3242 u32 ctrl_ext, i2cparams; 3243 3244 DEBUGFUNC("e1000_set_i2c_bb"); 3245 3246 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3247 ctrl_ext |= E1000_CTRL_I2C_ENA; 3248 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3249 E1000_WRITE_FLUSH(hw); 3250 3251 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); 3252 i2cparams |= E1000_I2CBB_EN; 3253 i2cparams |= E1000_I2C_DATA_OE_N; 3254 i2cparams |= E1000_I2C_CLK_OE_N; 3255 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); 3256 E1000_WRITE_FLUSH(hw); 3257 3258 return ret_val; 3259} 3260 3261/** 3262 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C 3263 * @hw: pointer to hardware structure 3264 * @byte_offset: byte offset to read 3265 * @dev_addr: device address 3266 * @data: value read 3267 * 3268 * Performs byte read operation over I2C interface at 3269 * a specified device address. 3270 **/ 3271s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3272 u8 dev_addr, u8 *data) 3273{ 3274 s32 status = E1000_SUCCESS; 3275 u32 max_retry = 10; 3276 u32 retry = 1; 3277 u16 swfw_mask = 0; 3278 3279 bool nack = TRUE; 3280 3281 DEBUGFUNC("e1000_read_i2c_byte_generic"); 3282 3283 swfw_mask = E1000_SWFW_PHY0_SM; 3284 3285 do { 3286 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 3287 != E1000_SUCCESS) { 3288 status = E1000_ERR_SWFW_SYNC; 3289 goto read_byte_out; 3290 } 3291 3292 e1000_i2c_start(hw); 3293 3294 /* Device Address and write indication */ 3295 status = e1000_clock_out_i2c_byte(hw, dev_addr); 3296 if (status != E1000_SUCCESS) 3297 goto fail; 3298 3299 status = e1000_get_i2c_ack(hw); 3300 if (status != E1000_SUCCESS) 3301 goto fail; 3302 3303 status = e1000_clock_out_i2c_byte(hw, byte_offset); 3304 if (status != E1000_SUCCESS) 3305 goto fail; 3306 3307 status = e1000_get_i2c_ack(hw); 3308 if (status != E1000_SUCCESS) 3309 goto fail; 3310 3311 e1000_i2c_start(hw); 3312 3313 /* Device Address and read indication */ 3314 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 3315 if (status != E1000_SUCCESS) 3316 goto fail; 3317 3318 status = e1000_get_i2c_ack(hw); 3319 if (status != E1000_SUCCESS) 3320 goto fail; 3321 3322 status = e1000_clock_in_i2c_byte(hw, data); 3323 if (status != E1000_SUCCESS) 3324 goto fail; 3325 3326 status = e1000_clock_out_i2c_bit(hw, nack); 3327 if (status != E1000_SUCCESS) 3328 goto fail; 3329 3330 e1000_i2c_stop(hw); 3331 break; 3332 3333fail: 3334 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3335 msec_delay(100); 3336 e1000_i2c_bus_clear(hw); 3337 retry++; 3338 if (retry < max_retry) 3339 DEBUGOUT("I2C byte read error - Retrying.\n"); 3340 else 3341 DEBUGOUT("I2C byte read error.\n"); 3342 3343 } while (retry < max_retry); 3344 3345 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3346 3347read_byte_out: 3348 3349 return status; 3350} 3351 3352/** 3353 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C 3354 * @hw: pointer to hardware structure 3355 * @byte_offset: byte offset to write 3356 * @dev_addr: device address 3357 * @data: value to write 3358 * 3359 * Performs byte write operation over I2C interface at 3360 * a specified device address. 3361 **/ 3362s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3363 u8 dev_addr, u8 data) 3364{ 3365 s32 status = E1000_SUCCESS; 3366 u32 max_retry = 1; 3367 u32 retry = 0; 3368 u16 swfw_mask = 0; 3369 3370 DEBUGFUNC("e1000_write_i2c_byte_generic"); 3371 3372 swfw_mask = E1000_SWFW_PHY0_SM; 3373 3374 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { 3375 status = E1000_ERR_SWFW_SYNC; 3376 goto write_byte_out; 3377 } 3378 3379 do { 3380 e1000_i2c_start(hw); 3381 3382 status = e1000_clock_out_i2c_byte(hw, dev_addr); 3383 if (status != E1000_SUCCESS) 3384 goto fail; 3385 3386 status = e1000_get_i2c_ack(hw); 3387 if (status != E1000_SUCCESS) 3388 goto fail; 3389 3390 status = e1000_clock_out_i2c_byte(hw, byte_offset); 3391 if (status != E1000_SUCCESS) 3392 goto fail; 3393 3394 status = e1000_get_i2c_ack(hw); 3395 if (status != E1000_SUCCESS) 3396 goto fail; 3397 3398 status = e1000_clock_out_i2c_byte(hw, data); 3399 if (status != E1000_SUCCESS) 3400 goto fail; 3401 3402 status = e1000_get_i2c_ack(hw); 3403 if (status != E1000_SUCCESS) 3404 goto fail; 3405 3406 e1000_i2c_stop(hw); 3407 break; 3408 3409fail: 3410 e1000_i2c_bus_clear(hw); 3411 retry++; 3412 if (retry < max_retry) 3413 DEBUGOUT("I2C byte write error - Retrying.\n"); 3414 else 3415 DEBUGOUT("I2C byte write error.\n"); 3416 } while (retry < max_retry); 3417 3418 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3419 3420write_byte_out: 3421 3422 return status; 3423} 3424 3425/** 3426 * e1000_i2c_start - Sets I2C start condition 3427 * @hw: pointer to hardware structure 3428 * 3429 * Sets I2C start condition (High -> Low on SDA while SCL is High) 3430 **/ 3431static void e1000_i2c_start(struct e1000_hw *hw) 3432{ 3433 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3434 3435 DEBUGFUNC("e1000_i2c_start"); 3436 3437 /* Start condition must begin with data and clock high */ 3438 e1000_set_i2c_data(hw, &i2cctl, 1); 3439 e1000_raise_i2c_clk(hw, &i2cctl); 3440 3441 /* Setup time for start condition (4.7us) */ 3442 usec_delay(E1000_I2C_T_SU_STA); 3443 3444 e1000_set_i2c_data(hw, &i2cctl, 0); 3445 3446 /* Hold time for start condition (4us) */ 3447 usec_delay(E1000_I2C_T_HD_STA); 3448 3449 e1000_lower_i2c_clk(hw, &i2cctl); 3450 3451 /* Minimum low period of clock is 4.7 us */ 3452 usec_delay(E1000_I2C_T_LOW); 3453 3454} 3455 3456/** 3457 * e1000_i2c_stop - Sets I2C stop condition 3458 * @hw: pointer to hardware structure 3459 * 3460 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 3461 **/ 3462static void e1000_i2c_stop(struct e1000_hw *hw) 3463{ 3464 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3465 3466 DEBUGFUNC("e1000_i2c_stop"); 3467 3468 /* Stop condition must begin with data low and clock high */ 3469 e1000_set_i2c_data(hw, &i2cctl, 0); 3470 e1000_raise_i2c_clk(hw, &i2cctl); 3471 3472 /* Setup time for stop condition (4us) */ 3473 usec_delay(E1000_I2C_T_SU_STO); 3474 3475 e1000_set_i2c_data(hw, &i2cctl, 1); 3476 3477 /* bus free time between stop and start (4.7us)*/ 3478 usec_delay(E1000_I2C_T_BUF); 3479} 3480 3481/** 3482 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C 3483 * @hw: pointer to hardware structure 3484 * @data: data byte to clock in 3485 * 3486 * Clocks in one byte data via I2C data/clock 3487 **/ 3488static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) 3489{ 3490 s32 i; 3491 bool bit = 0; 3492 3493 DEBUGFUNC("e1000_clock_in_i2c_byte"); 3494 3495 *data = 0; 3496 for (i = 7; i >= 0; i--) { 3497 e1000_clock_in_i2c_bit(hw, &bit); 3498 *data |= bit << i; 3499 } 3500 3501 return E1000_SUCCESS; 3502} 3503 3504/** 3505 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C 3506 * @hw: pointer to hardware structure 3507 * @data: data byte clocked out 3508 * 3509 * Clocks out one byte data via I2C data/clock 3510 **/ 3511static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) 3512{ 3513 s32 status = E1000_SUCCESS; 3514 s32 i; 3515 u32 i2cctl; 3516 bool bit = 0; 3517 3518 DEBUGFUNC("e1000_clock_out_i2c_byte"); 3519 3520 for (i = 7; i >= 0; i--) { 3521 bit = (data >> i) & 0x1; 3522 status = e1000_clock_out_i2c_bit(hw, bit); 3523 3524 if (status != E1000_SUCCESS) 3525 break; 3526 } 3527 3528 /* Release SDA line (set high) */ 3529 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3530 3531 i2cctl |= E1000_I2C_DATA_OE_N; 3532 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); 3533 E1000_WRITE_FLUSH(hw); 3534 3535 return status; 3536} 3537 3538/** 3539 * e1000_get_i2c_ack - Polls for I2C ACK 3540 * @hw: pointer to hardware structure 3541 * 3542 * Clocks in/out one bit via I2C data/clock 3543 **/ 3544static s32 e1000_get_i2c_ack(struct e1000_hw *hw) 3545{ 3546 s32 status = E1000_SUCCESS; 3547 u32 i = 0; 3548 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3549 u32 timeout = 10; 3550 bool ack = TRUE; 3551 3552 DEBUGFUNC("e1000_get_i2c_ack"); 3553 3554 e1000_raise_i2c_clk(hw, &i2cctl); 3555 3556 /* Minimum high period of clock is 4us */ 3557 usec_delay(E1000_I2C_T_HIGH); 3558 3559 /* Wait until SCL returns high */ 3560 for (i = 0; i < timeout; i++) { 3561 usec_delay(1); 3562 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3563 if (i2cctl & E1000_I2C_CLK_IN) 3564 break; 3565 } 3566 if (!(i2cctl & E1000_I2C_CLK_IN)) 3567 return E1000_ERR_I2C; 3568 3569 ack = e1000_get_i2c_data(&i2cctl); 3570 if (ack) { 3571 DEBUGOUT("I2C ack was not received.\n"); 3572 status = E1000_ERR_I2C; 3573 } 3574 3575 e1000_lower_i2c_clk(hw, &i2cctl); 3576 3577 /* Minimum low period of clock is 4.7 us */ 3578 usec_delay(E1000_I2C_T_LOW); 3579 3580 return status; 3581} 3582 3583/** 3584 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 3585 * @hw: pointer to hardware structure 3586 * @data: read data value 3587 * 3588 * Clocks in one bit via I2C data/clock 3589 **/ 3590static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) 3591{ 3592 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3593 3594 DEBUGFUNC("e1000_clock_in_i2c_bit"); 3595 3596 e1000_raise_i2c_clk(hw, &i2cctl); 3597 3598 /* Minimum high period of clock is 4us */ 3599 usec_delay(E1000_I2C_T_HIGH); 3600 3601 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3602 *data = e1000_get_i2c_data(&i2cctl); 3603 3604 e1000_lower_i2c_clk(hw, &i2cctl); 3605 3606 /* Minimum low period of clock is 4.7 us */ 3607 usec_delay(E1000_I2C_T_LOW); 3608 3609 return E1000_SUCCESS; 3610} 3611 3612/** 3613 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 3614 * @hw: pointer to hardware structure 3615 * @data: data value to write 3616 * 3617 * Clocks out one bit via I2C data/clock 3618 **/ 3619static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) 3620{ 3621 s32 status; 3622 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3623 3624 DEBUGFUNC("e1000_clock_out_i2c_bit"); 3625 3626 status = e1000_set_i2c_data(hw, &i2cctl, data); 3627 if (status == E1000_SUCCESS) { 3628 e1000_raise_i2c_clk(hw, &i2cctl); 3629 3630 /* Minimum high period of clock is 4us */ 3631 usec_delay(E1000_I2C_T_HIGH); 3632 3633 e1000_lower_i2c_clk(hw, &i2cctl); 3634 3635 /* Minimum low period of clock is 4.7 us. 3636 * This also takes care of the data hold time. 3637 */ 3638 usec_delay(E1000_I2C_T_LOW); 3639 } else { 3640 status = E1000_ERR_I2C; 3641 DEBUGOUT1("I2C data was not set to %X\n", data); 3642 } 3643 3644 return status; 3645} 3646/** 3647 * e1000_raise_i2c_clk - Raises the I2C SCL clock 3648 * @hw: pointer to hardware structure 3649 * @i2cctl: Current value of I2CCTL register 3650 * 3651 * Raises the I2C clock line '0'->'1' 3652 **/ 3653static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3654{ 3655 DEBUGFUNC("e1000_raise_i2c_clk"); 3656 3657 *i2cctl |= E1000_I2C_CLK_OUT; 3658 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3659 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3660 E1000_WRITE_FLUSH(hw); 3661 3662 /* SCL rise time (1000ns) */ 3663 usec_delay(E1000_I2C_T_RISE); 3664} 3665 3666/** 3667 * e1000_lower_i2c_clk - Lowers the I2C SCL clock 3668 * @hw: pointer to hardware structure 3669 * @i2cctl: Current value of I2CCTL register 3670 * 3671 * Lowers the I2C clock line '1'->'0' 3672 **/ 3673static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3674{ 3675 3676 DEBUGFUNC("e1000_lower_i2c_clk"); 3677 3678 *i2cctl &= ~E1000_I2C_CLK_OUT; 3679 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3680 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3681 E1000_WRITE_FLUSH(hw); 3682 3683 /* SCL fall time (300ns) */ 3684 usec_delay(E1000_I2C_T_FALL); 3685} 3686 3687/** 3688 * e1000_set_i2c_data - Sets the I2C data bit 3689 * @hw: pointer to hardware structure 3690 * @i2cctl: Current value of I2CCTL register 3691 * @data: I2C data value (0 or 1) to set 3692 * 3693 * Sets the I2C data bit 3694 **/ 3695static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) 3696{ 3697 s32 status = E1000_SUCCESS; 3698 3699 DEBUGFUNC("e1000_set_i2c_data"); 3700 3701 if (data) 3702 *i2cctl |= E1000_I2C_DATA_OUT; 3703 else 3704 *i2cctl &= ~E1000_I2C_DATA_OUT; 3705 3706 *i2cctl &= ~E1000_I2C_DATA_OE_N; 3707 *i2cctl |= E1000_I2C_CLK_OE_N; 3708 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3709 E1000_WRITE_FLUSH(hw); 3710 3711 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 3712 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA); 3713 3714 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3715 if (data != e1000_get_i2c_data(i2cctl)) { 3716 status = E1000_ERR_I2C; 3717 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 3718 } 3719 3720 return status; 3721} 3722 3723/** 3724 * e1000_get_i2c_data - Reads the I2C SDA data bit 3725 * @hw: pointer to hardware structure 3726 * @i2cctl: Current value of I2CCTL register 3727 * 3728 * Returns the I2C data bit value 3729 **/ 3730static bool e1000_get_i2c_data(u32 *i2cctl) 3731{ 3732 bool data; 3733 3734 DEBUGFUNC("e1000_get_i2c_data"); 3735 3736 if (*i2cctl & E1000_I2C_DATA_IN) 3737 data = 1; 3738 else 3739 data = 0; 3740 3741 return data; 3742} 3743 3744/** 3745 * e1000_i2c_bus_clear - Clears the I2C bus 3746 * @hw: pointer to hardware structure 3747 * 3748 * Clears the I2C bus by sending nine clock pulses. 3749 * Used when data line is stuck low. 3750 **/ 3751void e1000_i2c_bus_clear(struct e1000_hw *hw) 3752{ 3753 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3754 u32 i; 3755 3756 DEBUGFUNC("e1000_i2c_bus_clear"); 3757 3758 e1000_i2c_start(hw); 3759 3760 e1000_set_i2c_data(hw, &i2cctl, 1); 3761 3762 for (i = 0; i < 9; i++) { 3763 e1000_raise_i2c_clk(hw, &i2cctl); 3764 3765 /* Min high period of clock is 4us */ 3766 usec_delay(E1000_I2C_T_HIGH); 3767 3768 e1000_lower_i2c_clk(hw, &i2cctl); 3769 3770 /* Min low period of clock is 4.7us*/ 3771 usec_delay(E1000_I2C_T_LOW); 3772 } 3773 3774 e1000_i2c_start(hw); 3775 3776 /* Put the i2c bus back to default state */ 3777 e1000_i2c_stop(hw); 3778} 3779 3780