e1000_82543.c revision 181027
1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_82543.c 181027 2008-07-30 21:56:53Z jfv $*/ 34 35/* e1000_82543 36 * e1000_82544 37 */ 38 39#include "e1000_api.h" 40 41static s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 42static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 43static s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 44static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 45 u16 *data); 46static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 47 u16 data); 48static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 49static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 50static s32 e1000_reset_hw_82543(struct e1000_hw *hw); 51static s32 e1000_init_hw_82543(struct e1000_hw *hw); 52static s32 e1000_setup_link_82543(struct e1000_hw *hw); 53static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 54static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 55static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 56static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 57static s32 e1000_led_on_82543(struct e1000_hw *hw); 58static s32 e1000_led_off_82543(struct e1000_hw *hw); 59static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 60 u32 value); 61static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 62static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 63static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 64static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 65static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 66static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 67static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 68static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 69static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 70 u16 count); 71static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 72static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 73 74struct e1000_dev_spec_82543 { 75 u32 tbi_compatibility; 76 bool dma_fairness; 77 bool init_phy_disabled; 78}; 79 80/** 81 * e1000_init_phy_params_82543 - Init PHY func ptrs. 82 * @hw: pointer to the HW structure 83 * 84 * This is a function pointer entry point called by the api module. 85 **/ 86static s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 87{ 88 struct e1000_phy_info *phy = &hw->phy; 89 s32 ret_val = E1000_SUCCESS; 90 91 DEBUGFUNC("e1000_init_phy_params_82543"); 92 93 if (hw->phy.media_type != e1000_media_type_copper) { 94 phy->type = e1000_phy_none; 95 goto out; 96 } else { 97 phy->ops.power_up = e1000_power_up_phy_copper; 98 phy->ops.power_down = e1000_power_down_phy_copper; 99 } 100 101 phy->addr = 1; 102 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 103 phy->reset_delay_us = 10000; 104 phy->type = e1000_phy_m88; 105 106 /* Function Pointers */ 107 phy->ops.check_polarity = e1000_check_polarity_m88; 108 phy->ops.commit = e1000_phy_sw_reset_generic; 109 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; 110 phy->ops.get_cable_length = e1000_get_cable_length_m88; 111 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 112 phy->ops.read_reg = (hw->mac.type == e1000_82543) 113 ? e1000_read_phy_reg_82543 114 : e1000_read_phy_reg_m88; 115 phy->ops.reset = (hw->mac.type == e1000_82543) 116 ? e1000_phy_hw_reset_82543 117 : e1000_phy_hw_reset_generic; 118 phy->ops.write_reg = (hw->mac.type == e1000_82543) 119 ? e1000_write_phy_reg_82543 120 : e1000_write_phy_reg_m88; 121 phy->ops.get_info = e1000_get_phy_info_m88; 122 123 /* 124 * The external PHY of the 82543 can be in a funky state. 125 * Resetting helps us read the PHY registers for acquiring 126 * the PHY ID. 127 */ 128 if (!e1000_init_phy_disabled_82543(hw)) { 129 ret_val = phy->ops.reset(hw); 130 if (ret_val) { 131 DEBUGOUT("Resetting PHY during init failed.\n"); 132 goto out; 133 } 134 msec_delay(20); 135 } 136 137 ret_val = e1000_get_phy_id(hw); 138 if (ret_val) 139 goto out; 140 141 /* Verify phy id */ 142 switch (hw->mac.type) { 143 case e1000_82543: 144 if (phy->id != M88E1000_E_PHY_ID) { 145 ret_val = -E1000_ERR_PHY; 146 goto out; 147 } 148 break; 149 case e1000_82544: 150 if (phy->id != M88E1000_I_PHY_ID) { 151 ret_val = -E1000_ERR_PHY; 152 goto out; 153 } 154 break; 155 default: 156 ret_val = -E1000_ERR_PHY; 157 goto out; 158 break; 159 } 160 161out: 162 return ret_val; 163} 164 165/** 166 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 167 * @hw: pointer to the HW structure 168 * 169 * This is a function pointer entry point called by the api module. 170 **/ 171static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 172{ 173 struct e1000_nvm_info *nvm = &hw->nvm; 174 175 DEBUGFUNC("e1000_init_nvm_params_82543"); 176 177 nvm->type = e1000_nvm_eeprom_microwire; 178 nvm->word_size = 64; 179 nvm->delay_usec = 50; 180 nvm->address_bits = 6; 181 nvm->opcode_bits = 3; 182 183 /* Function Pointers */ 184 nvm->ops.read = e1000_read_nvm_microwire; 185 nvm->ops.update = e1000_update_nvm_checksum_generic; 186 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 187 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 188 nvm->ops.write = e1000_write_nvm_microwire; 189 190 return E1000_SUCCESS; 191} 192 193/** 194 * e1000_init_mac_params_82543 - Init MAC func ptrs. 195 * @hw: pointer to the HW structure 196 * 197 * This is a function pointer entry point called by the api module. 198 **/ 199static s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 200{ 201 struct e1000_mac_info *mac = &hw->mac; 202 s32 ret_val; 203 204 DEBUGFUNC("e1000_init_mac_params_82543"); 205 206 /* Set media type */ 207 switch (hw->device_id) { 208 case E1000_DEV_ID_82543GC_FIBER: 209 case E1000_DEV_ID_82544EI_FIBER: 210 hw->phy.media_type = e1000_media_type_fiber; 211 break; 212 default: 213 hw->phy.media_type = e1000_media_type_copper; 214 break; 215 } 216 217 /* Set mta register count */ 218 mac->mta_reg_count = 128; 219 /* Set rar entry count */ 220 mac->rar_entry_count = E1000_RAR_ENTRIES; 221 222 /* Function pointers */ 223 224 /* bus type/speed/width */ 225 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 226 /* reset */ 227 mac->ops.reset_hw = e1000_reset_hw_82543; 228 /* hw initialization */ 229 mac->ops.init_hw = e1000_init_hw_82543; 230 /* link setup */ 231 mac->ops.setup_link = e1000_setup_link_82543; 232 /* physical interface setup */ 233 mac->ops.setup_physical_interface = 234 (hw->phy.media_type == e1000_media_type_copper) 235 ? e1000_setup_copper_link_82543 236 : e1000_setup_fiber_link_82543; 237 /* check for link */ 238 mac->ops.check_for_link = 239 (hw->phy.media_type == e1000_media_type_copper) 240 ? e1000_check_for_copper_link_82543 241 : e1000_check_for_fiber_link_82543; 242 /* link info */ 243 mac->ops.get_link_up_info = 244 (hw->phy.media_type == e1000_media_type_copper) 245 ? e1000_get_speed_and_duplex_copper_generic 246 : e1000_get_speed_and_duplex_fiber_serdes_generic; 247 /* multicast address update */ 248 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 249 /* writing VFTA */ 250 mac->ops.write_vfta = e1000_write_vfta_82543; 251 /* clearing VFTA */ 252 mac->ops.clear_vfta = e1000_clear_vfta_generic; 253 /* setting MTA */ 254 mac->ops.mta_set = e1000_mta_set_82543; 255 /* turn on/off LED */ 256 mac->ops.led_on = e1000_led_on_82543; 257 mac->ops.led_off = e1000_led_off_82543; 258 /* remove device */ 259 mac->ops.remove_device = e1000_remove_device_generic; 260 /* clear hardware counters */ 261 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 262 263 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82543); 264 265 /* Device-specific structure allocation */ 266 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 267 if (ret_val) 268 goto out; 269 270 /* Set tbi compatibility */ 271 if ((hw->mac.type != e1000_82543) || 272 (hw->phy.media_type == e1000_media_type_fiber)) 273 e1000_set_tbi_compatibility_82543(hw, FALSE); 274 275out: 276 return ret_val; 277} 278 279/** 280 * e1000_init_function_pointers_82543 - Init func ptrs. 281 * @hw: pointer to the HW structure 282 * 283 * The only function explicitly called by the api module to initialize 284 * all function pointers and parameters. 285 **/ 286void e1000_init_function_pointers_82543(struct e1000_hw *hw) 287{ 288 DEBUGFUNC("e1000_init_function_pointers_82543"); 289 290 hw->mac.ops.init_params = e1000_init_mac_params_82543; 291 hw->nvm.ops.init_params = e1000_init_nvm_params_82543; 292 hw->phy.ops.init_params = e1000_init_phy_params_82543; 293} 294 295/** 296 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 297 * @hw: pointer to the HW structure 298 * 299 * Returns the current status of 10-bit Interface (TBI) compatibility 300 * (enabled/disabled). 301 **/ 302static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 303{ 304 struct e1000_dev_spec_82543 *dev_spec; 305 bool state = FALSE; 306 307 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 308 309 if (hw->mac.type != e1000_82543) { 310 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 311 goto out; 312 } 313 314 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 315 316 if (!dev_spec) { 317 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 318 goto out; 319 } 320 321 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 322 ? TRUE : FALSE; 323 324out: 325 return state; 326} 327 328/** 329 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 330 * @hw: pointer to the HW structure 331 * @state: enable/disable TBI compatibility 332 * 333 * Enables or disabled 10-bit Interface (TBI) compatibility. 334 **/ 335void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 336{ 337 struct e1000_dev_spec_82543 *dev_spec; 338 339 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 340 341 if (hw->mac.type != e1000_82543) { 342 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 343 goto out; 344 } 345 346 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 347 348 if (!dev_spec) { 349 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 350 goto out; 351 } 352 353 if (state) 354 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 355 else 356 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 357 358out: 359 return; 360} 361 362/** 363 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 364 * @hw: pointer to the HW structure 365 * 366 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 367 * (enabled/disabled). 368 **/ 369bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 370{ 371 struct e1000_dev_spec_82543 *dev_spec; 372 bool state = FALSE; 373 374 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 375 376 if (hw->mac.type != e1000_82543) { 377 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 378 goto out; 379 } 380 381 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 382 383 if (!dev_spec) { 384 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 385 goto out; 386 } 387 388 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 389 ? TRUE : FALSE; 390 391out: 392 return state; 393} 394 395/** 396 * e1000_set_tbi_sbp_82543 - Set TBI SBP 397 * @hw: pointer to the HW structure 398 * @state: enable/disable TBI store bad packet 399 * 400 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 401 **/ 402static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 403{ 404 struct e1000_dev_spec_82543 *dev_spec; 405 406 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 407 408 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 409 410 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 411 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 412 else 413 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 414 415 return; 416} 417 418/** 419 * e1000_init_phy_disabled_82543 - Returns init PHY status 420 * @hw: pointer to the HW structure 421 * 422 * Returns the current status of whether PHY initialization is disabled. 423 * True if PHY initialization is disabled else FALSE. 424 **/ 425static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 426{ 427 struct e1000_dev_spec_82543 *dev_spec; 428 bool ret_val; 429 430 DEBUGFUNC("e1000_init_phy_disabled_82543"); 431 432 if (hw->mac.type != e1000_82543) { 433 ret_val = FALSE; 434 goto out; 435 } 436 437 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 438 439 if (!dev_spec) { 440 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 441 ret_val = FALSE; 442 goto out; 443 } 444 445 ret_val = dev_spec->init_phy_disabled; 446 447out: 448 return ret_val; 449} 450 451/** 452 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 453 * @hw: pointer to the HW structure 454 * @stats: Struct containing statistic register values 455 * @frame_len: The length of the frame in question 456 * @mac_addr: The Ethernet destination address of the frame in question 457 * @max_frame_size: The maximum frame size 458 * 459 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 460 **/ 461void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 462 struct e1000_hw_stats *stats, u32 frame_len, 463 u8 *mac_addr, u32 max_frame_size) 464{ 465 if (!(e1000_tbi_sbp_enabled_82543(hw))) 466 goto out; 467 468 /* First adjust the frame length. */ 469 frame_len--; 470 /* 471 * We need to adjust the statistics counters, since the hardware 472 * counters overcount this packet as a CRC error and undercount 473 * the packet as a good packet 474 */ 475 /* This packet should not be counted as a CRC error. */ 476 stats->crcerrs--; 477 /* This packet does count as a Good Packet Received. */ 478 stats->gprc++; 479 480 /* Adjust the Good Octets received counters */ 481 stats->gorc += frame_len; 482 483 /* 484 * Is this a broadcast or multicast? Check broadcast first, 485 * since the test for a multicast frame will test positive on 486 * a broadcast frame. 487 */ 488 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 489 /* Broadcast packet */ 490 stats->bprc++; 491 else if (*mac_addr & 0x01) 492 /* Multicast packet */ 493 stats->mprc++; 494 495 /* 496 * In this case, the hardware has overcounted the number of 497 * oversize frames. 498 */ 499 if ((frame_len == max_frame_size) && (stats->roc > 0)) 500 stats->roc--; 501 502 /* 503 * Adjust the bin counters when the extra byte put the frame in the 504 * wrong bin. Remember that the frame_len was adjusted above. 505 */ 506 if (frame_len == 64) { 507 stats->prc64++; 508 stats->prc127--; 509 } else if (frame_len == 127) { 510 stats->prc127++; 511 stats->prc255--; 512 } else if (frame_len == 255) { 513 stats->prc255++; 514 stats->prc511--; 515 } else if (frame_len == 511) { 516 stats->prc511++; 517 stats->prc1023--; 518 } else if (frame_len == 1023) { 519 stats->prc1023++; 520 stats->prc1522--; 521 } else if (frame_len == 1522) { 522 stats->prc1522++; 523 } 524 525out: 526 return; 527} 528 529/** 530 * e1000_read_phy_reg_82543 - Read PHY register 531 * @hw: pointer to the HW structure 532 * @offset: register offset to be read 533 * @data: pointer to the read data 534 * 535 * Reads the PHY at offset and stores the information read to data. 536 **/ 537static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 538{ 539 u32 mdic; 540 s32 ret_val = E1000_SUCCESS; 541 542 DEBUGFUNC("e1000_read_phy_reg_82543"); 543 544 if (offset > MAX_PHY_REG_ADDRESS) { 545 DEBUGOUT1("PHY Address %d is out of range\n", offset); 546 ret_val = -E1000_ERR_PARAM; 547 goto out; 548 } 549 550 /* 551 * We must first send a preamble through the MDIO pin to signal the 552 * beginning of an MII instruction. This is done by sending 32 553 * consecutive "1" bits. 554 */ 555 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 556 557 /* 558 * Now combine the next few fields that are required for a read 559 * operation. We use this method instead of calling the 560 * e1000_shift_out_mdi_bits routine five different times. The format 561 * of an MII read instruction consists of a shift out of 14 bits and 562 * is defined as follows: 563 * <Preamble><SOF><Op Code><Phy Addr><Offset> 564 * followed by a shift in of 18 bits. This first two bits shifted in 565 * are TurnAround bits used to avoid contention on the MDIO pin when a 566 * READ operation is performed. These two bits are thrown away 567 * followed by a shift in of 16 bits which contains the desired data. 568 */ 569 mdic = (offset | (hw->phy.addr << 5) | 570 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 571 572 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 573 574 /* 575 * Now that we've shifted out the read command to the MII, we need to 576 * "shift in" the 16-bit value (18 total bits) of the requested PHY 577 * register address. 578 */ 579 *data = e1000_shift_in_mdi_bits_82543(hw); 580 581out: 582 return ret_val; 583} 584 585/** 586 * e1000_write_phy_reg_82543 - Write PHY register 587 * @hw: pointer to the HW structure 588 * @offset: register offset to be written 589 * @data: pointer to the data to be written at offset 590 * 591 * Writes data to the PHY at offset. 592 **/ 593static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 594{ 595 u32 mdic; 596 s32 ret_val = E1000_SUCCESS; 597 598 DEBUGFUNC("e1000_write_phy_reg_82543"); 599 600 if (offset > MAX_PHY_REG_ADDRESS) { 601 DEBUGOUT1("PHY Address %d is out of range\n", offset); 602 ret_val = -E1000_ERR_PARAM; 603 goto out; 604 } 605 606 /* 607 * We'll need to use the SW defined pins to shift the write command 608 * out to the PHY. We first send a preamble to the PHY to signal the 609 * beginning of the MII instruction. This is done by sending 32 610 * consecutive "1" bits. 611 */ 612 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 613 614 /* 615 * Now combine the remaining required fields that will indicate a 616 * write operation. We use this method instead of calling the 617 * e1000_shift_out_mdi_bits routine for each field in the command. The 618 * format of a MII write instruction is as follows: 619 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 620 */ 621 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 622 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 623 mdic <<= 16; 624 mdic |= (u32) data; 625 626 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 627 628out: 629 return ret_val; 630} 631 632/** 633 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 634 * @hw: pointer to the HW structure 635 * @ctrl: pointer to the control register 636 * 637 * Raise the management data input clock by setting the MDC bit in the control 638 * register. 639 **/ 640static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 641{ 642 /* 643 * Raise the clock input to the Management Data Clock (by setting the 644 * MDC bit), and then delay a sufficient amount of time. 645 */ 646 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 647 E1000_WRITE_FLUSH(hw); 648 usec_delay(10); 649} 650 651/** 652 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 653 * @hw: pointer to the HW structure 654 * @ctrl: pointer to the control register 655 * 656 * Lower the management data input clock by clearing the MDC bit in the 657 * control register. 658 **/ 659static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 660{ 661 /* 662 * Lower the clock input to the Management Data Clock (by clearing the 663 * MDC bit), and then delay a sufficient amount of time. 664 */ 665 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 666 E1000_WRITE_FLUSH(hw); 667 usec_delay(10); 668} 669 670/** 671 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 672 * @hw: pointer to the HW structure 673 * @data: data to send to the PHY 674 * @count: number of bits to shift out 675 * 676 * We need to shift 'count' bits out to the PHY. So, the value in the 677 * "data" parameter will be shifted out to the PHY one bit at a time. 678 * In order to do this, "data" must be broken down into bits. 679 **/ 680static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 681 u16 count) 682{ 683 u32 ctrl, mask; 684 685 /* 686 * We need to shift "count" number of bits out to the PHY. So, the 687 * value in the "data" parameter will be shifted out to the PHY one 688 * bit at a time. In order to do this, "data" must be broken down 689 * into bits. 690 */ 691 mask = 0x01; 692 mask <<= (count -1); 693 694 ctrl = E1000_READ_REG(hw, E1000_CTRL); 695 696 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 697 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 698 699 while (mask) { 700 /* 701 * A "1" is shifted out to the PHY by setting the MDIO bit to 702 * "1" and then raising and lowering the Management Data Clock. 703 * A "0" is shifted out to the PHY by setting the MDIO bit to 704 * "0" and then raising and lowering the clock. 705 */ 706 if (data & mask) ctrl |= E1000_CTRL_MDIO; 707 else ctrl &= ~E1000_CTRL_MDIO; 708 709 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 710 E1000_WRITE_FLUSH(hw); 711 712 usec_delay(10); 713 714 e1000_raise_mdi_clk_82543(hw, &ctrl); 715 e1000_lower_mdi_clk_82543(hw, &ctrl); 716 717 mask >>= 1; 718 } 719} 720 721/** 722 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 723 * @hw: pointer to the HW structure 724 * 725 * In order to read a register from the PHY, we need to shift 18 bits 726 * in from the PHY. Bits are "shifted in" by raising the clock input to 727 * the PHY (setting the MDC bit), and then reading the value of the data out 728 * MDIO bit. 729 **/ 730static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 731{ 732 u32 ctrl; 733 u16 data = 0; 734 u8 i; 735 736 /* 737 * In order to read a register from the PHY, we need to shift in a 738 * total of 18 bits from the PHY. The first two bit (turnaround) 739 * times are used to avoid contention on the MDIO pin when a read 740 * operation is performed. These two bits are ignored by us and 741 * thrown away. Bits are "shifted in" by raising the input to the 742 * Management Data Clock (setting the MDC bit) and then reading the 743 * value of the MDIO bit. 744 */ 745 ctrl = E1000_READ_REG(hw, E1000_CTRL); 746 747 /* 748 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 749 * input. 750 */ 751 ctrl &= ~E1000_CTRL_MDIO_DIR; 752 ctrl &= ~E1000_CTRL_MDIO; 753 754 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 755 E1000_WRITE_FLUSH(hw); 756 757 /* 758 * Raise and lower the clock before reading in the data. This accounts 759 * for the turnaround bits. The first clock occurred when we clocked 760 * out the last bit of the Register Address. 761 */ 762 e1000_raise_mdi_clk_82543(hw, &ctrl); 763 e1000_lower_mdi_clk_82543(hw, &ctrl); 764 765 for (data = 0, i = 0; i < 16; i++) { 766 data <<= 1; 767 e1000_raise_mdi_clk_82543(hw, &ctrl); 768 ctrl = E1000_READ_REG(hw, E1000_CTRL); 769 /* Check to see if we shifted in a "1". */ 770 if (ctrl & E1000_CTRL_MDIO) 771 data |= 1; 772 e1000_lower_mdi_clk_82543(hw, &ctrl); 773 } 774 775 e1000_raise_mdi_clk_82543(hw, &ctrl); 776 e1000_lower_mdi_clk_82543(hw, &ctrl); 777 778 return data; 779} 780 781/** 782 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 783 * @hw: pointer to the HW structure 784 * 785 * Calls the function to force speed and duplex for the m88 PHY, and 786 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 787 * then call the function for polarity reversal workaround. 788 **/ 789static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 790{ 791 s32 ret_val; 792 793 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 794 795 ret_val = e1000_phy_force_speed_duplex_m88(hw); 796 if (ret_val) 797 goto out; 798 799 if (!hw->mac.autoneg && 800 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 801 ret_val = e1000_polarity_reversal_workaround_82543(hw); 802 803out: 804 return ret_val; 805} 806 807/** 808 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 809 * @hw: pointer to the HW structure 810 * 811 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 812 * inadvertently. To workaround the issue, we disable the transmitter on 813 * the PHY until we have established the link partner's link parameters. 814 **/ 815static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 816{ 817 s32 ret_val = E1000_SUCCESS; 818 u16 mii_status_reg; 819 u16 i; 820 bool link; 821 822 if (!(hw->phy.ops.write_reg)) 823 goto out; 824 825 /* Polarity reversal workaround for forced 10F/10H links. */ 826 827 /* Disable the transmitter on the PHY */ 828 829 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 830 if (ret_val) 831 goto out; 832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 833 if (ret_val) 834 goto out; 835 836 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 837 if (ret_val) 838 goto out; 839 840 /* 841 * This loop will early-out if the NO link condition has been met. 842 * In other words, DO NOT use e1000_phy_has_link_generic() here. 843 */ 844 for (i = PHY_FORCE_TIME; i > 0; i--) { 845 /* 846 * Read the MII Status Register and wait for Link Status bit 847 * to be clear. 848 */ 849 850 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 851 if (ret_val) 852 goto out; 853 854 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 855 if (ret_val) 856 goto out; 857 858 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 859 break; 860 msec_delay_irq(100); 861 } 862 863 /* Recommended delay time after link has been lost */ 864 msec_delay_irq(1000); 865 866 /* Now we will re-enable the transmitter on the PHY */ 867 868 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 869 if (ret_val) 870 goto out; 871 msec_delay_irq(50); 872 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 873 if (ret_val) 874 goto out; 875 msec_delay_irq(50); 876 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 877 if (ret_val) 878 goto out; 879 msec_delay_irq(50); 880 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 881 if (ret_val) 882 goto out; 883 884 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 885 if (ret_val) 886 goto out; 887 888 /* 889 * Read the MII Status Register and wait for Link Status bit 890 * to be set. 891 */ 892 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 893 if (ret_val) 894 goto out; 895 896out: 897 return ret_val; 898} 899 900/** 901 * e1000_phy_hw_reset_82543 - PHY hardware reset 902 * @hw: pointer to the HW structure 903 * 904 * Sets the PHY_RESET_DIR bit in the extended device control register 905 * to put the PHY into a reset and waits for completion. Once the reset 906 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 907 * of reset. This is a function pointer entry point called by the api module. 908 **/ 909static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 910{ 911 u32 ctrl_ext; 912 s32 ret_val; 913 914 DEBUGFUNC("e1000_phy_hw_reset_82543"); 915 916 /* 917 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 918 * bit to put the PHY into reset... 919 */ 920 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 921 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 922 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 923 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 924 E1000_WRITE_FLUSH(hw); 925 926 msec_delay(10); 927 928 /* ...then take it out of reset. */ 929 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 930 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 931 E1000_WRITE_FLUSH(hw); 932 933 usec_delay(150); 934 935 if (!(hw->phy.ops.get_cfg_done)) 936 return E1000_SUCCESS; 937 938 ret_val = hw->phy.ops.get_cfg_done(hw); 939 940 return ret_val; 941} 942 943/** 944 * e1000_reset_hw_82543 - Reset hardware 945 * @hw: pointer to the HW structure 946 * 947 * This resets the hardware into a known state. This is a 948 * function pointer entry point called by the api module. 949 **/ 950static s32 e1000_reset_hw_82543(struct e1000_hw *hw) 951{ 952 u32 ctrl, icr; 953 s32 ret_val = E1000_SUCCESS; 954 955 DEBUGFUNC("e1000_reset_hw_82543"); 956 957 DEBUGOUT("Masking off all interrupts\n"); 958 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 959 960 E1000_WRITE_REG(hw, E1000_RCTL, 0); 961 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 962 E1000_WRITE_FLUSH(hw); 963 964 e1000_set_tbi_sbp_82543(hw, FALSE); 965 966 /* 967 * Delay to allow any outstanding PCI transactions to complete before 968 * resetting the device 969 */ 970 msec_delay(10); 971 972 ctrl = E1000_READ_REG(hw, E1000_CTRL); 973 974 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 975 if (hw->mac.type == e1000_82543) { 976 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 977 } else { 978 /* 979 * The 82544 can't ACK the 64-bit write when issuing the 980 * reset, so use IO-mapping as a workaround. 981 */ 982 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 983 } 984 985 /* 986 * After MAC reset, force reload of NVM to restore power-on 987 * settings to device. 988 */ 989 hw->nvm.ops.reload(hw); 990 msec_delay(2); 991 992 /* Masking off and clearing any pending interrupts */ 993 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 994 icr = E1000_READ_REG(hw, E1000_ICR); 995 996 return ret_val; 997} 998 999/** 1000 * e1000_init_hw_82543 - Initialize hardware 1001 * @hw: pointer to the HW structure 1002 * 1003 * This inits the hardware readying it for operation. 1004 **/ 1005static s32 e1000_init_hw_82543(struct e1000_hw *hw) 1006{ 1007 struct e1000_mac_info *mac = &hw->mac; 1008 struct e1000_dev_spec_82543 *dev_spec; 1009 u32 ctrl; 1010 s32 ret_val; 1011 u16 i; 1012 1013 DEBUGFUNC("e1000_init_hw_82543"); 1014 1015 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 1016 1017 if (!dev_spec) { 1018 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1019 ret_val = -E1000_ERR_CONFIG; 1020 goto out; 1021 } 1022 1023 /* Disabling VLAN filtering */ 1024 E1000_WRITE_REG(hw, E1000_VET, 0); 1025 mac->ops.clear_vfta(hw); 1026 1027 /* Setup the receive address. */ 1028 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1029 1030 /* Zero out the Multicast HASH table */ 1031 DEBUGOUT("Zeroing the MTA\n"); 1032 for (i = 0; i < mac->mta_reg_count; i++) { 1033 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1034 E1000_WRITE_FLUSH(hw); 1035 } 1036 1037 /* 1038 * Set the PCI priority bit correctly in the CTRL register. This 1039 * determines if the adapter gives priority to receives, or if it 1040 * gives equal priority to transmits and receives. 1041 */ 1042 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 1043 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1044 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 1045 } 1046 1047 e1000_pcix_mmrbc_workaround_generic(hw); 1048 1049 /* Setup link and flow control */ 1050 ret_val = mac->ops.setup_link(hw); 1051 1052 /* 1053 * Clear all of the statistics registers (clear on read). It is 1054 * important that we do this after we have tried to establish link 1055 * because the symbol error count will increment wildly if there 1056 * is no link. 1057 */ 1058 e1000_clear_hw_cntrs_82543(hw); 1059 1060out: 1061 return ret_val; 1062} 1063 1064/** 1065 * e1000_setup_link_82543 - Setup flow control and link settings 1066 * @hw: pointer to the HW structure 1067 * 1068 * Read the EEPROM to determine the initial polarity value and write the 1069 * extended device control register with the information before calling 1070 * the generic setup link function, which does the following: 1071 * Determines which flow control settings to use, then configures flow 1072 * control. Calls the appropriate media-specific link configuration 1073 * function. Assuming the adapter has a valid link partner, a valid link 1074 * should be established. Assumes the hardware has previously been reset 1075 * and the transmitter and receiver are not enabled. 1076 **/ 1077static s32 e1000_setup_link_82543(struct e1000_hw *hw) 1078{ 1079 u32 ctrl_ext; 1080 s32 ret_val; 1081 u16 data; 1082 1083 DEBUGFUNC("e1000_setup_link_82543"); 1084 1085 /* 1086 * Take the 4 bits from NVM word 0xF that determine the initial 1087 * polarity value for the SW controlled pins, and setup the 1088 * Extended Device Control reg with that info. 1089 * This is needed because one of the SW controlled pins is used for 1090 * signal detection. So this should be done before phy setup. 1091 */ 1092 if (hw->mac.type == e1000_82543) { 1093 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1094 if (ret_val) { 1095 DEBUGOUT("NVM Read Error\n"); 1096 ret_val = -E1000_ERR_NVM; 1097 goto out; 1098 } 1099 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1100 NVM_SWDPIO_EXT_SHIFT); 1101 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1102 } 1103 1104 ret_val = e1000_setup_link_generic(hw); 1105 1106out: 1107 return ret_val; 1108} 1109 1110/** 1111 * e1000_setup_copper_link_82543 - Configure copper link settings 1112 * @hw: pointer to the HW structure 1113 * 1114 * Configures the link for auto-neg or forced speed and duplex. Then we check 1115 * for link, once link is established calls to configure collision distance 1116 * and flow control are called. 1117 **/ 1118static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1119{ 1120 u32 ctrl; 1121 s32 ret_val; 1122 bool link; 1123 1124 DEBUGFUNC("e1000_setup_copper_link_82543"); 1125 1126 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1127 /* 1128 * With 82543, we need to force speed and duplex on the MAC 1129 * equal to what the PHY speed and duplex configuration is. 1130 * In addition, we need to perform a hardware reset on the 1131 * PHY to take it out of reset. 1132 */ 1133 if (hw->mac.type == e1000_82543) { 1134 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1135 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1136 ret_val = hw->phy.ops.reset(hw); 1137 if (ret_val) 1138 goto out; 1139 hw->phy.reset_disable = FALSE; 1140 } else { 1141 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1142 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1143 } 1144 1145 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1146 ret_val = e1000_copper_link_setup_m88(hw); 1147 if (ret_val) 1148 goto out; 1149 1150 if (hw->mac.autoneg) { 1151 /* 1152 * Setup autoneg and flow control advertisement and perform 1153 * autonegotiation. 1154 */ 1155 ret_val = e1000_copper_link_autoneg(hw); 1156 if (ret_val) 1157 goto out; 1158 } else { 1159 /* 1160 * PHY will be set to 10H, 10F, 100H or 100F 1161 * depending on user settings. 1162 */ 1163 DEBUGOUT("Forcing Speed and Duplex\n"); 1164 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1165 if (ret_val) { 1166 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1167 goto out; 1168 } 1169 } 1170 1171 /* 1172 * Check link status. Wait up to 100 microseconds for link to become 1173 * valid. 1174 */ 1175 ret_val = e1000_phy_has_link_generic(hw, 1176 COPPER_LINK_UP_LIMIT, 1177 10, 1178 &link); 1179 if (ret_val) 1180 goto out; 1181 1182 1183 if (link) { 1184 DEBUGOUT("Valid link established!!!\n"); 1185 /* Config the MAC and PHY after link is up */ 1186 if (hw->mac.type == e1000_82544) { 1187 e1000_config_collision_dist_generic(hw); 1188 } else { 1189 ret_val = e1000_config_mac_to_phy_82543(hw); 1190 if (ret_val) 1191 goto out; 1192 } 1193 ret_val = e1000_config_fc_after_link_up_generic(hw); 1194 } else { 1195 DEBUGOUT("Unable to establish link!!!\n"); 1196 } 1197 1198out: 1199 return ret_val; 1200} 1201 1202/** 1203 * e1000_setup_fiber_link_82543 - Setup link for fiber 1204 * @hw: pointer to the HW structure 1205 * 1206 * Configures collision distance and flow control for fiber links. Upon 1207 * successful setup, poll for link. 1208 **/ 1209static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1210{ 1211 u32 ctrl; 1212 s32 ret_val; 1213 1214 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1215 1216 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1217 1218 /* Take the link out of reset */ 1219 ctrl &= ~E1000_CTRL_LRST; 1220 1221 e1000_config_collision_dist_generic(hw); 1222 1223 ret_val = e1000_commit_fc_settings_generic(hw); 1224 if (ret_val) 1225 goto out; 1226 1227 DEBUGOUT("Auto-negotiation enabled\n"); 1228 1229 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1230 E1000_WRITE_FLUSH(hw); 1231 msec_delay(1); 1232 1233 /* 1234 * For these adapters, the SW definable pin 1 is cleared when the 1235 * optics detect a signal. If we have a signal, then poll for a 1236 * "Link-Up" indication. 1237 */ 1238 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1239 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1240 } else { 1241 DEBUGOUT("No signal detected\n"); 1242 } 1243 1244out: 1245 return ret_val; 1246} 1247 1248/** 1249 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1250 * @hw: pointer to the HW structure 1251 * 1252 * Checks the phy for link, if link exists, do the following: 1253 * - check for downshift 1254 * - do polarity workaround (if necessary) 1255 * - configure collision distance 1256 * - configure flow control after link up 1257 * - configure tbi compatibility 1258 **/ 1259static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1260{ 1261 struct e1000_mac_info *mac = &hw->mac; 1262 u32 icr, rctl; 1263 s32 ret_val; 1264 u16 speed, duplex; 1265 bool link; 1266 1267 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1268 1269 if (!mac->get_link_status) { 1270 ret_val = E1000_SUCCESS; 1271 goto out; 1272 } 1273 1274 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1275 if (ret_val) 1276 goto out; 1277 1278 if (!link) 1279 goto out; /* No link detected */ 1280 1281 mac->get_link_status = FALSE; 1282 1283 e1000_check_downshift_generic(hw); 1284 1285 /* 1286 * If we are forcing speed/duplex, then we can return since 1287 * we have already determined whether we have link or not. 1288 */ 1289 if (!mac->autoneg) { 1290 /* 1291 * If speed and duplex are forced to 10H or 10F, then we will 1292 * implement the polarity reversal workaround. We disable 1293 * interrupts first, and upon returning, place the devices 1294 * interrupt state to its previous value except for the link 1295 * status change interrupt which will happened due to the 1296 * execution of this workaround. 1297 */ 1298 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1299 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1300 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1301 icr = E1000_READ_REG(hw, E1000_ICR); 1302 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1303 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1304 } 1305 1306 ret_val = -E1000_ERR_CONFIG; 1307 goto out; 1308 } 1309 1310 /* 1311 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1312 * have Si on board that is 82544 or newer, Auto 1313 * Speed Detection takes care of MAC speed/duplex 1314 * configuration. So we only need to configure Collision 1315 * Distance in the MAC. Otherwise, we need to force 1316 * speed/duplex on the MAC to the current PHY speed/duplex 1317 * settings. 1318 */ 1319 if (mac->type == e1000_82544) 1320 e1000_config_collision_dist_generic(hw); 1321 else { 1322 ret_val = e1000_config_mac_to_phy_82543(hw); 1323 if (ret_val) { 1324 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1325 goto out; 1326 } 1327 } 1328 1329 /* 1330 * Configure Flow Control now that Auto-Neg has completed. 1331 * First, we need to restore the desired flow control 1332 * settings because we may have had to re-autoneg with a 1333 * different link partner. 1334 */ 1335 ret_val = e1000_config_fc_after_link_up_generic(hw); 1336 if (ret_val) { 1337 DEBUGOUT("Error configuring flow control\n"); 1338 } 1339 1340 /* 1341 * At this point we know that we are on copper and we have 1342 * auto-negotiated link. These are conditions for checking the link 1343 * partner capability register. We use the link speed to determine if 1344 * TBI compatibility needs to be turned on or off. If the link is not 1345 * at gigabit speed, then TBI compatibility is not needed. If we are 1346 * at gigabit speed, we turn on TBI compatibility. 1347 */ 1348 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1349 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1350 if (ret_val) { 1351 DEBUGOUT("Error getting link speed and duplex\n"); 1352 return ret_val; 1353 } 1354 if (speed != SPEED_1000) { 1355 /* 1356 * If link speed is not set to gigabit speed, 1357 * we do not need to enable TBI compatibility. 1358 */ 1359 if (e1000_tbi_sbp_enabled_82543(hw)) { 1360 /* 1361 * If we previously were in the mode, 1362 * turn it off. 1363 */ 1364 e1000_set_tbi_sbp_82543(hw, FALSE); 1365 rctl = E1000_READ_REG(hw, E1000_RCTL); 1366 rctl &= ~E1000_RCTL_SBP; 1367 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1368 } 1369 } else { 1370 /* 1371 * If TBI compatibility is was previously off, 1372 * turn it on. For compatibility with a TBI link 1373 * partner, we will store bad packets. Some 1374 * frames have an additional byte on the end and 1375 * will look like CRC errors to to the hardware. 1376 */ 1377 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1378 e1000_set_tbi_sbp_82543(hw, TRUE); 1379 rctl = E1000_READ_REG(hw, E1000_RCTL); 1380 rctl |= E1000_RCTL_SBP; 1381 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1382 } 1383 } 1384 } 1385out: 1386 return ret_val; 1387} 1388 1389/** 1390 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1391 * @hw: pointer to the HW structure 1392 * 1393 * Checks for link up on the hardware. If link is not up and we have 1394 * a signal, then we need to force link up. 1395 **/ 1396static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1397{ 1398 struct e1000_mac_info *mac = &hw->mac; 1399 u32 rxcw, ctrl, status; 1400 s32 ret_val = E1000_SUCCESS; 1401 1402 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1403 1404 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1405 status = E1000_READ_REG(hw, E1000_STATUS); 1406 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1407 1408 /* 1409 * If we don't have link (auto-negotiation failed or link partner 1410 * cannot auto-negotiate), the cable is plugged in (we have signal), 1411 * and our link partner is not trying to auto-negotiate with us (we 1412 * are receiving idles or data), we need to force link up. We also 1413 * need to give auto-negotiation time to complete, in case the cable 1414 * was just plugged in. The autoneg_failed flag does this. 1415 */ 1416 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1417 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1418 (!(status & E1000_STATUS_LU)) && 1419 (!(rxcw & E1000_RXCW_C))) { 1420 if (mac->autoneg_failed == 0) { 1421 mac->autoneg_failed = 1; 1422 ret_val = 0; 1423 goto out; 1424 } 1425 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1426 1427 /* Disable auto-negotiation in the TXCW register */ 1428 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1429 1430 /* Force link-up and also force full-duplex. */ 1431 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1432 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1433 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1434 1435 /* Configure Flow Control after forcing link up. */ 1436 ret_val = e1000_config_fc_after_link_up_generic(hw); 1437 if (ret_val) { 1438 DEBUGOUT("Error configuring flow control\n"); 1439 goto out; 1440 } 1441 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1442 /* 1443 * If we are forcing link and we are receiving /C/ ordered 1444 * sets, re-enable auto-negotiation in the TXCW register 1445 * and disable forced link in the Device Control register 1446 * in an attempt to auto-negotiate with our link partner. 1447 */ 1448 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1449 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1450 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1451 1452 mac->serdes_has_link = TRUE; 1453 } 1454 1455out: 1456 return ret_val; 1457} 1458 1459/** 1460 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1461 * @hw: pointer to the HW structure 1462 * 1463 * For the 82543 silicon, we need to set the MAC to match the settings 1464 * of the PHY, even if the PHY is auto-negotiating. 1465 **/ 1466static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1467{ 1468 u32 ctrl; 1469 s32 ret_val = E1000_SUCCESS; 1470 u16 phy_data; 1471 1472 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1473 1474 if (!(hw->phy.ops.read_reg)) 1475 goto out; 1476 1477 /* Set the bits to force speed and duplex */ 1478 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1479 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1480 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1481 1482 /* 1483 * Set up duplex in the Device Control and Transmit Control 1484 * registers depending on negotiated values. 1485 */ 1486 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1487 if (ret_val) 1488 goto out; 1489 1490 ctrl &= ~E1000_CTRL_FD; 1491 if (phy_data & M88E1000_PSSR_DPLX) 1492 ctrl |= E1000_CTRL_FD; 1493 1494 e1000_config_collision_dist_generic(hw); 1495 1496 /* 1497 * Set up speed in the Device Control register depending on 1498 * negotiated values. 1499 */ 1500 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1501 ctrl |= E1000_CTRL_SPD_1000; 1502 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1503 ctrl |= E1000_CTRL_SPD_100; 1504 1505 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1506 1507out: 1508 return ret_val; 1509} 1510 1511/** 1512 * e1000_write_vfta_82543 - Write value to VLAN filter table 1513 * @hw: pointer to the HW structure 1514 * @offset: the 32-bit offset in which to write the value to. 1515 * @value: the 32-bit value to write at location offset. 1516 * 1517 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1518 * table. 1519 **/ 1520static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1521{ 1522 u32 temp; 1523 1524 DEBUGFUNC("e1000_write_vfta_82543"); 1525 1526 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1527 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1528 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1529 E1000_WRITE_FLUSH(hw); 1530 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1531 E1000_WRITE_FLUSH(hw); 1532 } else { 1533 e1000_write_vfta_generic(hw, offset, value); 1534 } 1535} 1536 1537/** 1538 * e1000_mta_set_82543 - Set multicast filter table address 1539 * @hw: pointer to the HW structure 1540 * @hash_value: determines the MTA register and bit to set 1541 * 1542 * The multicast table address is a register array of 32-bit registers. 1543 * The hash_value is used to determine what register the bit is in, the 1544 * current value is read, the new bit is OR'd in and the new value is 1545 * written back into the register. 1546 **/ 1547static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1548{ 1549 u32 hash_bit, hash_reg, mta, temp; 1550 1551 DEBUGFUNC("e1000_mta_set_82543"); 1552 1553 hash_reg = (hash_value >> 5); 1554 1555 /* 1556 * If we are on an 82544 and we are trying to write an odd offset 1557 * in the MTA, save off the previous entry before writing and 1558 * restore the old value after writing. 1559 */ 1560 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1561 hash_reg &= (hw->mac.mta_reg_count - 1); 1562 hash_bit = hash_value & 0x1F; 1563 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1564 mta |= (1 << hash_bit); 1565 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1566 1567 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1568 E1000_WRITE_FLUSH(hw); 1569 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1570 E1000_WRITE_FLUSH(hw); 1571 } else { 1572 e1000_mta_set_generic(hw, hash_value); 1573 } 1574} 1575 1576/** 1577 * e1000_led_on_82543 - Turn on SW controllable LED 1578 * @hw: pointer to the HW structure 1579 * 1580 * Turns the SW defined LED on. This is a function pointer entry point 1581 * called by the api module. 1582 **/ 1583static s32 e1000_led_on_82543(struct e1000_hw *hw) 1584{ 1585 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1586 1587 DEBUGFUNC("e1000_led_on_82543"); 1588 1589 if (hw->mac.type == e1000_82544 && 1590 hw->phy.media_type == e1000_media_type_copper) { 1591 /* Clear SW-definable Pin 0 to turn on the LED */ 1592 ctrl &= ~E1000_CTRL_SWDPIN0; 1593 ctrl |= E1000_CTRL_SWDPIO0; 1594 } else { 1595 /* Fiber 82544 and all 82543 use this method */ 1596 ctrl |= E1000_CTRL_SWDPIN0; 1597 ctrl |= E1000_CTRL_SWDPIO0; 1598 } 1599 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1600 1601 return E1000_SUCCESS; 1602} 1603 1604/** 1605 * e1000_led_off_82543 - Turn off SW controllable LED 1606 * @hw: pointer to the HW structure 1607 * 1608 * Turns the SW defined LED off. This is a function pointer entry point 1609 * called by the api module. 1610 **/ 1611static s32 e1000_led_off_82543(struct e1000_hw *hw) 1612{ 1613 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1614 1615 DEBUGFUNC("e1000_led_off_82543"); 1616 1617 if (hw->mac.type == e1000_82544 && 1618 hw->phy.media_type == e1000_media_type_copper) { 1619 /* Set SW-definable Pin 0 to turn off the LED */ 1620 ctrl |= E1000_CTRL_SWDPIN0; 1621 ctrl |= E1000_CTRL_SWDPIO0; 1622 } else { 1623 ctrl &= ~E1000_CTRL_SWDPIN0; 1624 ctrl |= E1000_CTRL_SWDPIO0; 1625 } 1626 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1627 1628 return E1000_SUCCESS; 1629} 1630 1631/** 1632 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1633 * @hw: pointer to the HW structure 1634 * 1635 * Clears the hardware counters by reading the counter registers. 1636 **/ 1637static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1638{ 1639 volatile u32 temp; 1640 1641 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1642 1643 e1000_clear_hw_cntrs_base_generic(hw); 1644 1645 temp = E1000_READ_REG(hw, E1000_PRC64); 1646 temp = E1000_READ_REG(hw, E1000_PRC127); 1647 temp = E1000_READ_REG(hw, E1000_PRC255); 1648 temp = E1000_READ_REG(hw, E1000_PRC511); 1649 temp = E1000_READ_REG(hw, E1000_PRC1023); 1650 temp = E1000_READ_REG(hw, E1000_PRC1522); 1651 temp = E1000_READ_REG(hw, E1000_PTC64); 1652 temp = E1000_READ_REG(hw, E1000_PTC127); 1653 temp = E1000_READ_REG(hw, E1000_PTC255); 1654 temp = E1000_READ_REG(hw, E1000_PTC511); 1655 temp = E1000_READ_REG(hw, E1000_PTC1023); 1656 temp = E1000_READ_REG(hw, E1000_PTC1522); 1657 1658 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1659 temp = E1000_READ_REG(hw, E1000_RXERRC); 1660 temp = E1000_READ_REG(hw, E1000_TNCRS); 1661 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1662 temp = E1000_READ_REG(hw, E1000_TSCTC); 1663 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1664} 1665