e1000_82543.c revision 169248
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/em/e1000_82543.c 169248 2007-05-04 13:30:44Z rwatson $"); 36 37 38/* e1000_82543 39 * e1000_82544 40 */ 41 42#include "e1000_82543.h" 43 44void e1000_init_function_pointers_82543(struct e1000_hw *hw); 45 46STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 47STATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 48STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 49STATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 50 u16 *data); 51STATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 52 u16 data); 53STATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 54STATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 55STATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw); 56STATIC s32 e1000_init_hw_82543(struct e1000_hw *hw); 57STATIC s32 e1000_setup_link_82543(struct e1000_hw *hw); 58STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 59STATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 60STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 61STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 62STATIC s32 e1000_led_on_82543(struct e1000_hw *hw); 63STATIC s32 e1000_led_off_82543(struct e1000_hw *hw); 64STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 65 u32 value); 66STATIC void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 67STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 68static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 69static boolean_t e1000_init_phy_disabled_82543(struct e1000_hw *hw); 70static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 71static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 72static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 73static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 74static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 75 u16 count); 76static boolean_t e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 77static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, boolean_t state); 78 79struct e1000_dev_spec_82543 { 80 u32 tbi_compatibility; 81 boolean_t dma_fairness; 82 boolean_t init_phy_disabled; 83}; 84 85/** 86 * e1000_init_phy_params_82543 - Init PHY func ptrs. 87 * @hw - pointer to the HW structure 88 * 89 * This is a function pointer entry point called by the api module. 90 **/ 91STATIC s32 92e1000_init_phy_params_82543(struct e1000_hw *hw) 93{ 94 struct e1000_phy_info *phy = &hw->phy; 95 struct e1000_functions *func = &hw->func; 96 s32 ret_val = E1000_SUCCESS; 97 98 DEBUGFUNC("e1000_init_phy_params_82543"); 99 100 if (hw->media_type != e1000_media_type_copper) { 101 phy->type = e1000_phy_none; 102 goto out; 103 } 104 105 phy->addr = 1; 106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 107 phy->reset_delay_us = 10000; 108 phy->type = e1000_phy_m88; 109 110 /* Function Pointers */ 111 func->check_polarity = e1000_check_polarity_m88; 112 func->commit_phy = e1000_phy_sw_reset_generic; 113 func->force_speed_duplex = e1000_phy_force_speed_duplex_82543; 114 func->get_cable_length = e1000_get_cable_length_m88; 115 func->get_cfg_done = e1000_get_cfg_done_generic; 116 func->read_phy_reg = (hw->mac.type == e1000_82543) 117 ? e1000_read_phy_reg_82543 118 : e1000_read_phy_reg_m88; 119 func->reset_phy = (hw->mac.type == e1000_82543) 120 ? e1000_phy_hw_reset_82543 121 : e1000_phy_hw_reset_generic; 122 func->write_phy_reg = (hw->mac.type == e1000_82543) 123 ? e1000_write_phy_reg_82543 124 : e1000_write_phy_reg_m88; 125 func->get_phy_info = e1000_get_phy_info_m88; 126 127 /* The external PHY of the 82543 can be in a funky state. 128 * Resetting helps us read the PHY registers for acquiring 129 * the PHY ID. 130 */ 131 if (!e1000_init_phy_disabled_82543(hw)) { 132 ret_val = e1000_phy_hw_reset(hw); 133 if (ret_val) { 134 DEBUGOUT("Resetting PHY during init failed.\n"); 135 goto out; 136 } 137 msec_delay(20); 138 } 139 140 ret_val = e1000_get_phy_id(hw); 141 if (ret_val) 142 goto out; 143 144 /* Verify phy id */ 145 switch (hw->mac.type) { 146 case e1000_82543: 147 if (phy->id != M88E1000_E_PHY_ID) { 148 ret_val = -E1000_ERR_PHY; 149 goto out; 150 } 151 break; 152 case e1000_82544: 153 if (phy->id != M88E1000_I_PHY_ID) { 154 ret_val = -E1000_ERR_PHY; 155 goto out; 156 } 157 break; 158 default: 159 ret_val = -E1000_ERR_PHY; 160 goto out; 161 break; 162 } 163 164out: 165 return ret_val; 166} 167 168/** 169 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 170 * @hw - pointer to the HW structure 171 * 172 * This is a function pointer entry point called by the api module. 173 **/ 174STATIC s32 175e1000_init_nvm_params_82543(struct e1000_hw *hw) 176{ 177 struct e1000_nvm_info *nvm = &hw->nvm; 178 struct e1000_functions *func = &hw->func; 179 180 DEBUGFUNC("e1000_init_nvm_params_82543"); 181 182 nvm->type = e1000_nvm_eeprom_microwire; 183 nvm->word_size = 64; 184 nvm->delay_usec = 50; 185 nvm->address_bits = 6; 186 nvm->opcode_bits = 3; 187 188 /* Function Pointers */ 189 func->read_nvm = e1000_read_nvm_microwire; 190 func->update_nvm = e1000_update_nvm_checksum_generic; 191 func->valid_led_default = e1000_valid_led_default_generic; 192 func->validate_nvm = e1000_validate_nvm_checksum_generic; 193 func->write_nvm = e1000_write_nvm_microwire; 194 195 return E1000_SUCCESS; 196} 197 198/** 199 * e1000_init_mac_params_82543 - Init MAC func ptrs. 200 * @hw - pointer to the HW structure 201 * 202 * This is a function pointer entry point called by the api module. 203 **/ 204STATIC s32 205e1000_init_mac_params_82543(struct e1000_hw *hw) 206{ 207 struct e1000_mac_info *mac = &hw->mac; 208 struct e1000_functions *func = &hw->func; 209 s32 ret_val; 210 211 DEBUGFUNC("e1000_init_mac_params_82543"); 212 213 /* Set media type */ 214 switch (hw->device_id) { 215 case E1000_DEV_ID_82543GC_FIBER: 216 case E1000_DEV_ID_82544EI_FIBER: 217 hw->media_type = e1000_media_type_fiber; 218 break; 219 default: 220 hw->media_type = e1000_media_type_copper; 221 break; 222 } 223 224 /* Set mta register count */ 225 mac->mta_reg_count = 128; 226 /* Set rar entry count */ 227 mac->rar_entry_count = E1000_RAR_ENTRIES; 228 229 /* Function pointers */ 230 231 /* bus type/speed/width */ 232 func->get_bus_info = e1000_get_bus_info_pci_generic; 233 /* reset */ 234 func->reset_hw = e1000_reset_hw_82543; 235 /* hw initialization */ 236 func->init_hw = e1000_init_hw_82543; 237 /* link setup */ 238 func->setup_link = e1000_setup_link_82543; 239 /* physical interface setup */ 240 func->setup_physical_interface = 241 (hw->media_type == e1000_media_type_copper) 242 ? e1000_setup_copper_link_82543 243 : e1000_setup_fiber_link_82543; 244 /* check for link */ 245 func->check_for_link = 246 (hw->media_type == e1000_media_type_copper) 247 ? e1000_check_for_copper_link_82543 248 : e1000_check_for_fiber_link_82543; 249 /* link info */ 250 func->get_link_up_info = 251 (hw->media_type == e1000_media_type_copper) 252 ? e1000_get_speed_and_duplex_copper_generic 253 : e1000_get_speed_and_duplex_fiber_serdes_generic; 254 /* multicast address update */ 255 func->mc_addr_list_update = e1000_mc_addr_list_update_generic; 256 /* writing VFTA */ 257 func->write_vfta = e1000_write_vfta_82543; 258 /* clearing VFTA */ 259 func->clear_vfta = e1000_clear_vfta_generic; 260 /* setting MTA */ 261 func->mta_set = e1000_mta_set_82543; 262 /* turn on/off LED */ 263 func->led_on = e1000_led_on_82543; 264 func->led_off = e1000_led_off_82543; 265 /* remove device */ 266 func->remove_device = e1000_remove_device_generic; 267 /* clear hardware counters */ 268 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 269 270 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82543); 271 272 /* Device-specific structure allocation */ 273 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 274 if (ret_val) 275 goto out; 276 277 /* Set tbi compatibility */ 278 if ((hw->mac.type != e1000_82543) || 279 (hw->media_type == e1000_media_type_fiber)) 280 e1000_set_tbi_compatibility_82543(hw, FALSE); 281 282out: 283 return ret_val; 284} 285 286/** 287 * e1000_init_function_pointers_82543 - Init func ptrs. 288 * @hw - pointer to the HW structure 289 * 290 * The only function explicitly called by the api module to initialize 291 * all function pointers and parameters. 292 **/ 293void 294e1000_init_function_pointers_82543(struct e1000_hw *hw) 295{ 296 DEBUGFUNC("e1000_init_function_pointers_82543"); 297 298 hw->func.init_mac_params = e1000_init_mac_params_82543; 299 hw->func.init_nvm_params = e1000_init_nvm_params_82543; 300 hw->func.init_phy_params = e1000_init_phy_params_82543; 301} 302 303/** 304 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 305 * @hw - pointer to the HW structure 306 * 307 * Returns the curent status of 10-bit Interface (TBI) compatibility 308 * (enabled/disabled). 309 **/ 310static boolean_t 311e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 312{ 313 struct e1000_dev_spec_82543 *dev_spec; 314 boolean_t state = FALSE; 315 316 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 317 318 if (hw->mac.type != e1000_82543) { 319 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 320 goto out; 321 } 322 323 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 324 325 if (dev_spec == NULL) { 326 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 327 goto out; 328 } 329 330 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 331 ? TRUE : FALSE; 332 333out: 334 return state; 335} 336 337/** 338 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 339 * @hw - pointer to the HW structure 340 * @state - enable/disable TBI compatibility 341 * 342 * Enables or disabled 10-bit Interface (TBI) compatibility. 343 **/ 344void 345e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, boolean_t state) 346{ 347 struct e1000_dev_spec_82543 *dev_spec; 348 349 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 350 351 if (hw->mac.type != e1000_82543) { 352 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 353 goto out; 354 } 355 356 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 357 358 if (dev_spec == NULL) { 359 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 360 goto out; 361 } 362 363 if (state) 364 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 365 else 366 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 367 368out: 369 return; 370} 371 372/** 373 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 374 * @hw - pointer to the HW structure 375 * 376 * Returns the curent status of 10-bit Interface (TBI) store bad packet (SBP) 377 * (enabled/disabled). 378 **/ 379boolean_t 380e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 381{ 382 struct e1000_dev_spec_82543 *dev_spec; 383 boolean_t state = FALSE; 384 385 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 386 387 if (hw->mac.type != e1000_82543) { 388 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 389 goto out; 390 } 391 392 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 393 394 if (dev_spec == NULL) { 395 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 396 goto out; 397 } 398 399 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 400 ? TRUE : FALSE; 401 402out: 403 return state; 404} 405 406/** 407 * e1000_set_tbi_sbp_82543 - Set TBI SBP 408 * @hw - pointer to the HW structure 409 * @state - enable/disable TBI store bad packet 410 * 411 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 412 **/ 413static void 414e1000_set_tbi_sbp_82543(struct e1000_hw *hw, boolean_t state) 415{ 416 struct e1000_dev_spec_82543 *dev_spec; 417 418 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 419 420 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 421 422 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 423 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 424 else 425 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 426 427 return; 428} 429 430/** 431 * e1000_init_phy_disabled_82543 - Returns init PHY status 432 * @hw - pointer to the HW structure 433 * 434 * Returns the current status of whether PHY initialization is disabled. 435 * True if PHY initialization is disabled else false. 436 **/ 437static boolean_t 438e1000_init_phy_disabled_82543(struct e1000_hw *hw) 439{ 440 struct e1000_dev_spec_82543 *dev_spec; 441 boolean_t ret_val; 442 443 DEBUGFUNC("e1000_init_phy_disabled_82543"); 444 445 if (hw->mac.type != e1000_82543) { 446 ret_val = FALSE; 447 goto out; 448 } 449 450 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 451 452 if (dev_spec == NULL) { 453 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 454 ret_val = FALSE; 455 goto out; 456 } 457 458 ret_val = dev_spec->init_phy_disabled; 459 460out: 461 return ret_val; 462} 463 464/** 465 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 466 * @hw - pointer to the HW structure 467 * @stats - Struct containing statistic register values 468 * @frame_len - The length of the frame in question 469 * @mac_addr - The Ethernet destination address of the frame in question 470 * 471 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 472 **/ 473void 474e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, struct e1000_hw_stats *stats, 475 u32 frame_len, u8 *mac_addr) 476{ 477 u64 carry_bit; 478 479 if (e1000_tbi_sbp_enabled_82543(hw) == FALSE) 480 goto out; 481 482 /* First adjust the frame length. */ 483 frame_len--; 484 /* We need to adjust the statistics counters, since the hardware 485 * counters overcount this packet as a CRC error and undercount 486 * the packet as a good packet 487 */ 488 /* This packet should not be counted as a CRC error. */ 489 stats->crcerrs--; 490 /* This packet does count as a Good Packet Received. */ 491 stats->gprc++; 492 493 /* Adjust the Good Octets received counters */ 494 carry_bit = 0x80000000 & stats->gorcl; 495 stats->gorcl += frame_len; 496 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 497 * Received Count) was one before the addition, 498 * AND it is zero after, then we lost the carry out, 499 * need to add one to Gorch (Good Octets Received Count High). 500 * This could be simplified if all environments supported 501 * 64-bit integers. 502 */ 503 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 504 stats->gorch++; 505 /* Is this a broadcast or multicast? Check broadcast first, 506 * since the test for a multicast frame will test positive on 507 * a broadcast frame. 508 */ 509 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 510 /* Broadcast packet */ 511 stats->bprc++; 512 else if (*mac_addr & 0x01) 513 /* Multicast packet */ 514 stats->mprc++; 515 516 /* In this case, the hardware has overcounted the number of 517 * oversize frames. 518 */ 519 if ((frame_len == hw->mac.max_frame_size) && (stats->roc > 0)) 520 stats->roc--; 521 522 /* Adjust the bin counters when the extra byte put the frame in the 523 * wrong bin. Remember that the frame_len was adjusted above. 524 */ 525 if (frame_len == 64) { 526 stats->prc64++; 527 stats->prc127--; 528 } else if (frame_len == 127) { 529 stats->prc127++; 530 stats->prc255--; 531 } else if (frame_len == 255) { 532 stats->prc255++; 533 stats->prc511--; 534 } else if (frame_len == 511) { 535 stats->prc511++; 536 stats->prc1023--; 537 } else if (frame_len == 1023) { 538 stats->prc1023++; 539 stats->prc1522--; 540 } else if (frame_len == 1522) { 541 stats->prc1522++; 542 } 543 544out: 545 return; 546} 547 548/** 549 * e1000_read_phy_reg_82543 - Read PHY register 550 * @hw - pointer to the HW structure 551 * @offset - register offset to be read 552 * @data - pointer to the read data 553 * 554 * Reads the PHY at offset and stores the information read to data. 555 **/ 556STATIC s32 557e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 558{ 559 u32 mdic; 560 s32 ret_val = E1000_SUCCESS; 561 562 DEBUGFUNC("e1000_read_phy_reg_82543"); 563 564 if (offset > MAX_PHY_REG_ADDRESS) { 565 DEBUGOUT1("PHY Address %d is out of range\n", offset); 566 ret_val = -E1000_ERR_PARAM; 567 goto out; 568 } 569 570 /* We must first send a preamble through the MDIO pin to signal the 571 * beginning of an MII instruction. This is done by sending 32 572 * consecutive "1" bits. 573 */ 574 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 575 576 /* Now combine the next few fields that are required for a read 577 * operation. We use this method instead of calling the 578 * e1000_shift_out_mdi_bits routine five different times. The format 579 * of an MII read instruction consists of a shift out of 14 bits and 580 * is defined as follows: 581 * <Preamble><SOF><Op Code><Phy Addr><Offset> 582 * followed by a shift in of 18 bits. This first two bits shifted in 583 * are TurnAround bits used to avoid contention on the MDIO pin when a 584 * READ operation is performed. These two bits are thrown away 585 * followed by a shift in of 16 bits which contains the desired data. 586 */ 587 mdic = (offset | (hw->phy.addr << 5) | 588 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 589 590 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 591 592 /* Now that we've shifted out the read command to the MII, we need to 593 * "shift in" the 16-bit value (18 total bits) of the requested PHY 594 * register address. 595 */ 596 *data = e1000_shift_in_mdi_bits_82543(hw); 597 598out: 599 return ret_val; 600} 601 602/** 603 * e1000_write_phy_reg_82543 - Write PHY register 604 * @hw - pointer to the HW structure 605 * @offset - register offset to be written 606 * @data - pointer to the data to be written at offset 607 * 608 * Writes data to the PHY at offset. 609 **/ 610STATIC s32 611e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 612{ 613 u32 mdic; 614 s32 ret_val = E1000_SUCCESS; 615 616 DEBUGFUNC("e1000_write_phy_reg_82543"); 617 618 if (offset > MAX_PHY_REG_ADDRESS) { 619 DEBUGOUT1("PHY Address %d is out of range\n", offset); 620 ret_val = -E1000_ERR_PARAM; 621 goto out; 622 } 623 624 /* We'll need to use the SW defined pins to shift the write command 625 * out to the PHY. We first send a preamble to the PHY to signal the 626 * beginning of the MII instruction. This is done by sending 32 627 * consecutive "1" bits. 628 */ 629 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 630 631 /* Now combine the remaining required fields that will indicate a 632 * write operation. We use this method instead of calling the 633 * e1000_shift_out_mdi_bits routine for each field in the command. The 634 * format of a MII write instruction is as follows: 635 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 636 */ 637 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 638 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 639 mdic <<= 16; 640 mdic |= (u32) data; 641 642 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 643 644out: 645 return ret_val; 646} 647 648/** 649 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 650 * @hw - pointer to the HW structure 651 * @ctrl - pointer to the control register 652 * 653 * Raise the management data input clock by setting the MDC bit in the control 654 * register. 655 **/ 656static void 657e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 658{ 659 /* Raise the clock input to the Management Data Clock (by setting the 660 * MDC bit), and then delay a sufficient amount of time. 661 */ 662 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 663 E1000_WRITE_FLUSH(hw); 664 usec_delay(10); 665} 666 667/** 668 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 669 * @hw - pointer to the HW structure 670 * @ctrl - pointer to the control register 671 * 672 * Lower the management data input clock by clearing the MDC bit in the control 673 * register. 674 **/ 675static void 676e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 677{ 678 /* Lower the clock input to the Management Data Clock (by clearing the 679 * MDC bit), and then delay a sufficient amount of time. 680 */ 681 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 682 E1000_WRITE_FLUSH(hw); 683 usec_delay(10); 684} 685 686/** 687 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 688 * @hw - pointer to the HW structure 689 * @data - data to send to the PHY 690 * @count - number of bits to shift out 691 * 692 * We need to shift 'count' bits out to the PHY. So, the value in the 693 * "data" parameter will be shifted out to the PHY one bit at a time. 694 * In order to do this, "data" must be broken down into bits. 695 **/ 696static void 697e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, u16 count) 698{ 699 u32 ctrl, mask; 700 701 /* We need to shift "count" number of bits out to the PHY. So, the 702 * value in the "data" parameter will be shifted out to the PHY one 703 * bit at a time. In order to do this, "data" must be broken down 704 * into bits. 705 */ 706 mask = 0x01; 707 mask <<= (count -1); 708 709 ctrl = E1000_READ_REG(hw, E1000_CTRL); 710 711 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 712 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 713 714 while (mask) { 715 /* A "1" is shifted out to the PHY by setting the MDIO bit to 716 * "1" and then raising and lowering the Management Data Clock. 717 * A "0" is shifted out to the PHY by setting the MDIO bit to 718 * "0" and then raising and lowering the clock. 719 */ 720 if (data & mask) ctrl |= E1000_CTRL_MDIO; 721 else ctrl &= ~E1000_CTRL_MDIO; 722 723 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 724 E1000_WRITE_FLUSH(hw); 725 726 usec_delay(10); 727 728 e1000_raise_mdi_clk_82543(hw, &ctrl); 729 e1000_lower_mdi_clk_82543(hw, &ctrl); 730 731 mask >>= 1; 732 } 733} 734 735/** 736 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 737 * @hw - pointer to the HW structure 738 * 739 * In order to read a register from the PHY, we need to shift 18 bits 740 * in from the PHY. Bits are "shifted in" by raising the clock input to 741 * the PHY (setting the MDC bit), and then reading the value of the data out 742 * MDIO bit. 743 **/ 744static u16 745e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 746{ 747 u32 ctrl; 748 u16 data = 0; 749 u8 i; 750 751 /* In order to read a register from the PHY, we need to shift in a 752 * total of 18 bits from the PHY. The first two bit (turnaround) 753 * times are used to avoid contention on the MDIO pin when a read 754 * operation is performed. These two bits are ignored by us and 755 * thrown away. Bits are "shifted in" by raising the input to the 756 * Management Data Clock (setting the MDC bit) and then reading the 757 * value of the MDIO bit. 758 */ 759 ctrl = E1000_READ_REG(hw, E1000_CTRL); 760 761 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 762 * input. 763 */ 764 ctrl &= ~E1000_CTRL_MDIO_DIR; 765 ctrl &= ~E1000_CTRL_MDIO; 766 767 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 768 E1000_WRITE_FLUSH(hw); 769 770 /* Raise and lower the clock before reading in the data. This accounts 771 * for the turnaround bits. The first clock occurred when we clocked 772 * out the last bit of the Register Address. 773 */ 774 e1000_raise_mdi_clk_82543(hw, &ctrl); 775 e1000_lower_mdi_clk_82543(hw, &ctrl); 776 777 for (data = 0, i = 0; i < 16; i++) { 778 data <<= 1; 779 e1000_raise_mdi_clk_82543(hw, &ctrl); 780 ctrl = E1000_READ_REG(hw, E1000_CTRL); 781 /* Check to see if we shifted in a "1". */ 782 if (ctrl & E1000_CTRL_MDIO) 783 data |= 1; 784 e1000_lower_mdi_clk_82543(hw, &ctrl); 785 } 786 787 e1000_raise_mdi_clk_82543(hw, &ctrl); 788 e1000_lower_mdi_clk_82543(hw, &ctrl); 789 790 return data; 791} 792 793/** 794 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 795 * @hw - pointer to the HW structure 796 * 797 * Calls the function to force speed and duplex for the m88 PHY, and 798 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 799 * then call the function for polarity reversal workaround. 800 **/ 801STATIC s32 802e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 803{ 804 s32 ret_val; 805 806 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 807 808 ret_val = e1000_phy_force_speed_duplex_m88(hw); 809 if (ret_val) 810 goto out; 811 812 if (!hw->mac.autoneg && 813 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 814 ret_val = e1000_polarity_reversal_workaround_82543(hw); 815 816out: 817 return ret_val; 818} 819 820/** 821 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 822 * @hw - pointer to the HW structure 823 * 824 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 825 * inadvertantly. To workaround the issue, we disable the transmitter on 826 * the PHY until we have established the link partner's link parameters. 827 **/ 828static s32 829e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 830{ 831 s32 ret_val; 832 u16 mii_status_reg; 833 u16 i; 834 boolean_t link; 835 836 /* Polarity reversal workaround for forced 10F/10H links. */ 837 838 /* Disable the transmitter on the PHY */ 839 840 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 841 if (ret_val) 842 goto out; 843 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 844 if (ret_val) 845 goto out; 846 847 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 848 if (ret_val) 849 goto out; 850 851 /* This loop will early-out if the NO link condition has been met. 852 * In other words, DO NOT use e1000_phy_has_link_generic() here. 853 */ 854 for (i = PHY_FORCE_TIME; i > 0; i--) { 855 /* Read the MII Status Register and wait for Link Status bit 856 * to be clear. 857 */ 858 859 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 860 if (ret_val) 861 goto out; 862 863 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 864 if (ret_val) 865 goto out; 866 867 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 868 break; 869 msec_delay_irq(100); 870 } 871 872 /* Recommended delay time after link has been lost */ 873 msec_delay_irq(1000); 874 875 /* Now we will re-enable the transmitter on the PHY */ 876 877 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 878 if (ret_val) 879 goto out; 880 msec_delay_irq(50); 881 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 882 if (ret_val) 883 goto out; 884 msec_delay_irq(50); 885 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 886 if (ret_val) 887 goto out; 888 msec_delay_irq(50); 889 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 890 if (ret_val) 891 goto out; 892 893 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 894 if (ret_val) 895 goto out; 896 897 /* Read the MII Status Register and wait for Link Status bit 898 * to be set. 899 */ 900 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 901 if (ret_val) 902 goto out; 903 904out: 905 return ret_val; 906} 907 908/** 909 * e1000_phy_hw_reset_82543 - PHY hardware reset 910 * @hw - pointer to the HW structure 911 * 912 * Sets the PHY_RESET_DIR bit in the extended device control register 913 * to put the PHY into a reset and waits for completion. Once the reset 914 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 915 * of reset. This is a function pointer entry point called by the api module. 916 **/ 917STATIC s32 918e1000_phy_hw_reset_82543(struct e1000_hw *hw) 919{ 920 struct e1000_functions *func = &hw->func; 921 u32 ctrl_ext; 922 s32 ret_val; 923 924 DEBUGFUNC("e1000_phy_hw_reset_82543"); 925 926 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 927 * bit to put the PHY into reset... 928 */ 929 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 930 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 931 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 932 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 933 E1000_WRITE_FLUSH(hw); 934 935 msec_delay(10); 936 937 /* ...then take it out of reset. */ 938 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 939 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 940 E1000_WRITE_FLUSH(hw); 941 942 usec_delay(150); 943 944 ret_val = func->get_cfg_done(hw); 945 946 return ret_val; 947} 948 949/** 950 * e1000_reset_hw_82543 - Reset hardware 951 * @hw - pointer to the HW structure 952 * 953 * This resets the hardware into a known state. This is a 954 * function pointer entry point called by the api module. 955 **/ 956STATIC s32 957e1000_reset_hw_82543(struct e1000_hw *hw) 958{ 959 u32 ctrl, icr; 960 s32 ret_val = E1000_SUCCESS; 961 962 DEBUGFUNC("e1000_reset_hw_82543"); 963 964 DEBUGOUT("Masking off all interrupts\n"); 965 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 966 967 E1000_WRITE_REG(hw, E1000_RCTL, 0); 968 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 969 E1000_WRITE_FLUSH(hw); 970 971 e1000_set_tbi_sbp_82543(hw, FALSE); 972 973 /* Delay to allow any outstanding PCI transactions to complete before 974 * resetting the device 975 */ 976 msec_delay(10); 977 978 ctrl = E1000_READ_REG(hw, E1000_CTRL); 979 980 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 981 if (hw->mac.type == e1000_82543) { 982 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 983 } else { 984 /* The 82544 can't ACK the 64-bit write when issuing the 985 * reset, so use IO-mapping as a workaround. 986 */ 987 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 988 } 989 990 /* After MAC reset, force reload of NVM to restore power-on 991 * settings to device. 992 */ 993 e1000_reload_nvm(hw); 994 msec_delay(2); 995 996 /* Masking off and clearing any pending interrupts */ 997 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 998 icr = E1000_READ_REG(hw, E1000_ICR); 999 1000 return ret_val; 1001} 1002 1003/** 1004 * e1000_init_hw_82543 - Initialize hardware 1005 * @hw - pointer to the HW structure 1006 * 1007 * This inits the hardware readying it for operation. 1008 **/ 1009STATIC s32 1010e1000_init_hw_82543(struct e1000_hw *hw) 1011{ 1012 struct e1000_mac_info *mac = &hw->mac; 1013 struct e1000_dev_spec_82543 *dev_spec; 1014 u32 ctrl; 1015 s32 ret_val; 1016 u16 i; 1017 1018 DEBUGFUNC("e1000_init_hw_82543"); 1019 1020 dev_spec = (struct e1000_dev_spec_82543 *)hw->dev_spec; 1021 1022 if (dev_spec == NULL) { 1023 DEBUGOUT("dev_spec pointer is set to NULL.\n"); 1024 ret_val = -E1000_ERR_CONFIG; 1025 goto out; 1026 } 1027 1028 /* Disabling VLAN filtering */ 1029 E1000_WRITE_REG(hw, E1000_VET, 0); 1030 e1000_clear_vfta(hw); 1031 1032 /* Setup the receive address. */ 1033 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 1034 1035 /* Zero out the Multicast HASH table */ 1036 DEBUGOUT("Zeroing the MTA\n"); 1037 for (i = 0; i < mac->mta_reg_count; i++) { 1038 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1039 E1000_WRITE_FLUSH(hw); 1040 } 1041 1042 /* Set the PCI priority bit correctly in the CTRL register. This 1043 * determines if the adapter gives priority to receives, or if it 1044 * gives equal priority to transmits and receives. 1045 */ 1046 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 1047 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1048 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 1049 } 1050 1051 e1000_pcix_mmrbc_workaround_generic(hw); 1052 1053 /* Setup link and flow control */ 1054 ret_val = e1000_setup_link(hw); 1055 1056 /* Clear all of the statistics registers (clear on read). It is 1057 * important that we do this after we have tried to establish link 1058 * because the symbol error count will increment wildly if there 1059 * is no link. 1060 */ 1061 e1000_clear_hw_cntrs_82543(hw); 1062 1063out: 1064 return ret_val; 1065} 1066 1067/** 1068 * e1000_setup_link_82543 - Setup flow control and link settings 1069 * @hw - pointer to the HW structure 1070 * 1071 * Read the EEPROM to determine the initial polarity value and write the 1072 * extended device control register with the information before calling 1073 * the generic setup link function, which does the following: 1074 * Determines which flow control settings to use, then configures flow 1075 * control. Calls the appropriate media-specific link configuration 1076 * function. Assuming the adapter has a valid link partner, a valid link 1077 * should be established. Assumes the hardware has previously been reset 1078 * and the transmitter and receiver are not enabled. 1079 **/ 1080STATIC s32 1081e1000_setup_link_82543(struct e1000_hw *hw) 1082{ 1083 u32 ctrl_ext; 1084 s32 ret_val; 1085 u16 data; 1086 1087 DEBUGFUNC("e1000_setup_link_82543"); 1088 1089 /* Take the 4 bits from NVM word 0xF that determine the initial 1090 * polarity value for the SW controlled pins, and setup the 1091 * Extended Device Control reg with that info. 1092 * This is needed because one of the SW controlled pins is used for 1093 * signal detection. So this should be done before phy setup. 1094 */ 1095 if (hw->mac.type == e1000_82543) { 1096 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1097 if (ret_val) { 1098 DEBUGOUT("NVM Read Error\n"); 1099 ret_val = -E1000_ERR_NVM; 1100 goto out; 1101 } 1102 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1103 NVM_SWDPIO_EXT_SHIFT); 1104 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1105 } 1106 1107 ret_val = e1000_setup_link_generic(hw); 1108 1109out: 1110 return ret_val; 1111} 1112 1113/** 1114 * e1000_setup_copper_link_82543 - Configure copper link settings 1115 * @hw - pointer to the HW structure 1116 * 1117 * Configures the link for auto-neg or forced speed and duplex. Then we check 1118 * for link, once link is established calls to configure collision distance 1119 * and flow control are called. 1120 **/ 1121STATIC s32 1122e1000_setup_copper_link_82543(struct e1000_hw *hw) 1123{ 1124 u32 ctrl; 1125 s32 ret_val; 1126 boolean_t link; 1127 1128 DEBUGFUNC("e1000_setup_copper_link_82543"); 1129 1130 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1131 /* With 82543, we need to force speed and duplex on the MAC 1132 * equal to what the PHY speed and duplex configuration is. 1133 * In addition, we need to perform a hardware reset on the 1134 * PHY to take it out of reset. 1135 */ 1136 if (hw->mac.type == e1000_82543) { 1137 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1138 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1139 ret_val = e1000_phy_hw_reset(hw); 1140 if (ret_val) 1141 goto out; 1142 hw->phy.reset_disable = FALSE; 1143 } else { 1144 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1145 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1146 } 1147 1148 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1149 ret_val = e1000_copper_link_setup_m88(hw); 1150 if (ret_val) 1151 goto out; 1152 1153 if (hw->mac.autoneg) { 1154 /* Setup autoneg and flow control advertisement and perform 1155 * autonegotiation. */ 1156 ret_val = e1000_copper_link_autoneg(hw); 1157 if (ret_val) 1158 goto out; 1159 } else { 1160 /* PHY will be set to 10H, 10F, 100H or 100F 1161 * depending on user settings. */ 1162 DEBUGOUT("Forcing Speed and Duplex\n"); 1163 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1164 if (ret_val) { 1165 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1166 goto out; 1167 } 1168 } 1169 1170 /* Check link status. Wait up to 100 microseconds for link to become 1171 * valid. 1172 */ 1173 ret_val = e1000_phy_has_link_generic(hw, 1174 COPPER_LINK_UP_LIMIT, 1175 10, 1176 &link); 1177 if (ret_val) 1178 goto out; 1179 1180 1181 if (link) { 1182 DEBUGOUT("Valid link established!!!\n"); 1183 /* Config the MAC and PHY after link is up */ 1184 if (hw->mac.type == e1000_82544) 1185 e1000_config_collision_dist_generic(hw); 1186 else { 1187 ret_val = e1000_config_mac_to_phy_82543(hw); 1188 if (ret_val) 1189 goto out; 1190 } 1191 ret_val = e1000_config_fc_after_link_up_generic(hw); 1192 } else { 1193 DEBUGOUT("Unable to establish link!!!\n"); 1194 } 1195 1196out: 1197 return ret_val; 1198} 1199 1200/** 1201 * e1000_setup_fiber_link_82543 - Setup link for fiber 1202 * @hw - pointer to the HW structure 1203 * 1204 * Configures collision distance and flow control for fiber links. Upon 1205 * successful setup, poll for link. 1206 **/ 1207STATIC s32 1208e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1209{ 1210 u32 ctrl; 1211 s32 ret_val; 1212 1213 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1214 1215 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1216 1217 /* Take the link out of reset */ 1218 ctrl &= ~E1000_CTRL_LRST; 1219 1220 e1000_config_collision_dist_generic(hw); 1221 1222 ret_val = e1000_commit_fc_settings_generic(hw); 1223 if (ret_val) 1224 goto out; 1225 1226 DEBUGOUT("Auto-negotiation enabled\n"); 1227 1228 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1229 E1000_WRITE_FLUSH(hw); 1230 msec_delay(1); 1231 1232 /* For these adapters, the SW defineable pin 1 is cleared when the 1233 * optics detect a signal. If we have a signal, then poll for a 1234 * "Link-Up" indication. 1235 */ 1236 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1237 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1238 } else { 1239 DEBUGOUT("No signal detected\n"); 1240 } 1241 1242out: 1243 return ret_val; 1244} 1245 1246/** 1247 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1248 * @hw - pointer to the HW structure 1249 * 1250 * Checks the phy for link, if link exists, do the following: 1251 * - check for downshift 1252 * - do polarity workaround (if necessary) 1253 * - configure collision distance 1254 * - configure flow control after link up 1255 * - configure tbi compatibility 1256 **/ 1257STATIC s32 1258e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1259{ 1260 struct e1000_mac_info *mac = &hw->mac; 1261 u32 icr, rctl; 1262 s32 ret_val; 1263 u16 speed, duplex; 1264 boolean_t link; 1265 1266 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1267 1268 if (!mac->get_link_status) { 1269 ret_val = E1000_SUCCESS; 1270 goto out; 1271 } 1272 1273 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1274 if (ret_val) 1275 goto out; 1276 1277 if (!link) 1278 goto out; /* No link detected */ 1279 1280 mac->get_link_status = FALSE; 1281 1282 e1000_check_downshift_generic(hw); 1283 1284 /* If we are forcing speed/duplex, then we can return since 1285 * we have already determined whether we have link or not. 1286 */ 1287 if (!mac->autoneg) { 1288 /* If speed and duplex are forced to 10H or 10F, then we will 1289 * implement the polarity reversal workaround. We disable 1290 * interrupts first, and upon returning, place the devices 1291 * interrupt state to its previous value except for the link 1292 * status change interrupt which will happened due to the 1293 * execution of this workaround. 1294 */ 1295 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1296 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1297 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1298 icr = E1000_READ_REG(hw, E1000_ICR); 1299 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1300 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1301 } 1302 1303 ret_val = -E1000_ERR_CONFIG; 1304 goto out; 1305 } 1306 1307 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1308 * have Si on board that is 82544 or newer, Auto 1309 * Speed Detection takes care of MAC speed/duplex 1310 * configuration. So we only need to configure Collision 1311 * Distance in the MAC. Otherwise, we need to force 1312 * speed/duplex on the MAC to the current PHY speed/duplex 1313 * settings. 1314 */ 1315 if (mac->type == e1000_82544) 1316 e1000_config_collision_dist_generic(hw); 1317 else { 1318 ret_val = e1000_config_mac_to_phy_82543(hw); 1319 if (ret_val) { 1320 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1321 goto out; 1322 } 1323 } 1324 1325 /* Configure Flow Control now that Auto-Neg has completed. 1326 * First, we need to restore the desired flow control 1327 * settings because we may have had to re-autoneg with a 1328 * different link partner. 1329 */ 1330 ret_val = e1000_config_fc_after_link_up_generic(hw); 1331 if (ret_val) { 1332 DEBUGOUT("Error configuring flow control\n"); 1333 } 1334 1335 /* At this point we know that we are on copper and we have 1336 * auto-negotiated link. These are conditions for checking the link 1337 * partner capability register. We use the link speed to determine if 1338 * TBI compatibility needs to be turned on or off. If the link is not 1339 * at gigabit speed, then TBI compatibility is not needed. If we are 1340 * at gigabit speed, we turn on TBI compatibility. 1341 */ 1342 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1343 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1344 if (ret_val) { 1345 DEBUGOUT("Error getting link speed and duplex\n"); 1346 return ret_val; 1347 } 1348 if (speed != SPEED_1000) { 1349 /* If link speed is not set to gigabit speed, 1350 * we do not need to enable TBI compatibility. 1351 */ 1352 if (e1000_tbi_sbp_enabled_82543(hw)) { 1353 /* If we previously were in the mode, 1354 * turn it off. 1355 */ 1356 e1000_set_tbi_sbp_82543(hw, FALSE); 1357 rctl = E1000_READ_REG(hw, E1000_RCTL); 1358 rctl &= ~E1000_RCTL_SBP; 1359 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1360 } 1361 } else { 1362 /* If TBI compatibility is was previously off, 1363 * turn it on. For compatibility with a TBI link 1364 * partner, we will store bad packets. Some 1365 * frames have an additional byte on the end and 1366 * will look like CRC errors to to the hardware. 1367 */ 1368 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1369 e1000_set_tbi_sbp_82543(hw, TRUE); 1370 rctl = E1000_READ_REG(hw, E1000_RCTL); 1371 rctl |= E1000_RCTL_SBP; 1372 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1373 } 1374 } 1375 } 1376out: 1377 return ret_val; 1378} 1379 1380/** 1381 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1382 * @hw - pointer to the HW structure 1383 * 1384 * Checks for link up on the hardware. If link is not up and we have 1385 * a signal, then we need to force link up. 1386 **/ 1387STATIC s32 1388e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1389{ 1390 struct e1000_mac_info *mac = &hw->mac; 1391 u32 rxcw, ctrl, status; 1392 s32 ret_val = E1000_SUCCESS; 1393 1394 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1395 1396 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1397 status = E1000_READ_REG(hw, E1000_CTRL); 1398 rxcw = E1000_READ_REG(hw, E1000_CTRL); 1399 1400 /* If we don't have link (auto-negotiation failed or link partner 1401 * cannot auto-negotiate), the cable is plugged in (we have signal), 1402 * and our link partner is not trying to auto-negotiate with us (we 1403 * are receiving idles or data), we need to force link up. We also 1404 * need to give auto-negotiation time to complete, in case the cable 1405 * was just plugged in. The autoneg_failed flag does this. 1406 */ 1407 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1408 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1409 (!(status & E1000_STATUS_LU)) && 1410 (!(rxcw & E1000_RXCW_C))) { 1411 if (mac->autoneg_failed == 0) { 1412 mac->autoneg_failed = 1; 1413 ret_val = 0; 1414 goto out; 1415 } 1416 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1417 1418 /* Disable auto-negotiation in the TXCW register */ 1419 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1420 1421 /* Force link-up and also force full-duplex. */ 1422 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1423 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1424 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1425 1426 /* Configure Flow Control after forcing link up. */ 1427 ret_val = e1000_config_fc_after_link_up_generic(hw); 1428 if (ret_val) { 1429 DEBUGOUT("Error configuring flow control\n"); 1430 goto out; 1431 } 1432 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1433 /* If we are forcing link and we are receiving /C/ ordered 1434 * sets, re-enable auto-negotiation in the TXCW register 1435 * and disable forced link in the Device Control register 1436 * in an attempt to auto-negotiate with our link partner. 1437 */ 1438 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1439 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1440 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1441 1442 mac->serdes_has_link = TRUE; 1443 } 1444 1445out: 1446 return ret_val; 1447} 1448 1449/** 1450 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1451 * @hw - pointer to the HW structure 1452 * 1453 * For the 82543 silicon, we need to set the MAC to match the settings 1454 * of the PHY, even if the PHY is auto-negotiating. 1455 **/ 1456static s32 1457e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1458{ 1459 u32 ctrl; 1460 s32 ret_val; 1461 u16 phy_data; 1462 1463 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1464 1465 /* Set the bits to force speed and duplex */ 1466 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1467 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1468 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1469 1470 /* Set up duplex in the Device Control and Transmit Control 1471 * registers depending on negotiated values. 1472 */ 1473 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1474 if (ret_val) 1475 goto out; 1476 1477 ctrl &= ~E1000_CTRL_FD; 1478 if (phy_data & M88E1000_PSSR_DPLX) 1479 ctrl |= E1000_CTRL_FD; 1480 1481 e1000_config_collision_dist_generic(hw); 1482 1483 /* Set up speed in the Device Control register depending on 1484 * negotiated values. 1485 */ 1486 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1487 ctrl |= E1000_CTRL_SPD_1000; 1488 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1489 ctrl |= E1000_CTRL_SPD_100; 1490 1491 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1492 1493out: 1494 return ret_val; 1495} 1496 1497/** 1498 * e1000_write_vfta_82543 - Write value to VLAN filter table 1499 * @hw - pointer to the HW structure 1500 * @offset - the 32-bit offset in which to write the value to. 1501 * @value - the 32-bit value to write at location offset. 1502 * 1503 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1504 * table. 1505 **/ 1506STATIC void 1507e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1508{ 1509 u32 temp; 1510 1511 DEBUGFUNC("e1000_write_vfta_82543"); 1512 1513 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1514 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1515 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1516 E1000_WRITE_FLUSH(hw); 1517 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1518 E1000_WRITE_FLUSH(hw); 1519 } else 1520 e1000_write_vfta_generic(hw, offset, value); 1521} 1522 1523/** 1524 * e1000_mta_set_82543 - Set multicast filter table address 1525 * @hw - pointer to the HW structure 1526 * @hash_value - determines the MTA register and bit to set 1527 * 1528 * The multicast table address is a register array of 32-bit registers. 1529 * The hash_value is used to determine what register the bit is in, the 1530 * current value is read, the new bit is OR'd in and the new value is 1531 * written back into the register. 1532 **/ 1533STATIC void 1534e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1535{ 1536 u32 hash_bit, hash_reg, mta, temp; 1537 1538 DEBUGFUNC("e1000_mta_set_82543"); 1539 1540 hash_reg = (hash_value >> 5); 1541 1542 /* If we are on an 82544 and we are trying to write an odd offset 1543 * in the MTA, save off the previous entry before writing and 1544 * restore the old value after writing. 1545 */ 1546 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1547 hash_reg &= (hw->mac.mta_reg_count - 1); 1548 hash_bit = hash_value & 0x1F; 1549 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1550 mta |= (1 << hash_bit); 1551 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1552 1553 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1554 E1000_WRITE_FLUSH(hw); 1555 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1556 E1000_WRITE_FLUSH(hw); 1557 } else 1558 e1000_mta_set_generic(hw, hash_value); 1559} 1560 1561/** 1562 * e1000_led_on_82543 - Turn on SW controllable LED 1563 * @hw - pointer to the HW structure 1564 * 1565 * Turns the SW defined LED on. This is a function pointer entry point 1566 * called by the api module. 1567 **/ 1568STATIC s32 1569e1000_led_on_82543(struct e1000_hw *hw) 1570{ 1571 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1572 1573 DEBUGFUNC("e1000_led_on_82543"); 1574 1575 if (hw->mac.type == e1000_82544 && 1576 hw->media_type == e1000_media_type_copper) { 1577 /* Clear SW-defineable Pin 0 to turn on the LED */ 1578 ctrl &= ~E1000_CTRL_SWDPIN0; 1579 ctrl |= E1000_CTRL_SWDPIO0; 1580 } else { 1581 /* Fiber 82544 and all 82543 use this method */ 1582 ctrl |= E1000_CTRL_SWDPIN0; 1583 ctrl |= E1000_CTRL_SWDPIO0; 1584 } 1585 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1586 1587 return E1000_SUCCESS; 1588} 1589 1590/** 1591 * e1000_led_off_82543 - Turn off SW controllable LED 1592 * @hw - pointer to the HW structure 1593 * 1594 * Turns the SW defined LED off. This is a function pointer entry point 1595 * called by the api module. 1596 **/ 1597STATIC s32 1598e1000_led_off_82543(struct e1000_hw *hw) 1599{ 1600 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1601 1602 DEBUGFUNC("e1000_led_off_82543"); 1603 1604 if (hw->mac.type == e1000_82544 && 1605 hw->media_type == e1000_media_type_copper) { 1606 /* Set SW-defineable Pin 0 to turn off the LED */ 1607 ctrl |= E1000_CTRL_SWDPIN0; 1608 ctrl |= E1000_CTRL_SWDPIO0; 1609 } else { 1610 ctrl &= ~E1000_CTRL_SWDPIN0; 1611 ctrl |= E1000_CTRL_SWDPIO0; 1612 } 1613 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1614 1615 return E1000_SUCCESS; 1616} 1617 1618/** 1619 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1620 * @hw - pointer to the HW structure 1621 * 1622 * Clears the hardware counters by reading the counter registers. 1623 **/ 1624STATIC void 1625e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1626{ 1627 volatile u32 temp; 1628 1629 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1630 1631 e1000_clear_hw_cntrs_base_generic(hw); 1632 1633 temp = E1000_READ_REG(hw, E1000_PRC64); 1634 temp = E1000_READ_REG(hw, E1000_PRC127); 1635 temp = E1000_READ_REG(hw, E1000_PRC255); 1636 temp = E1000_READ_REG(hw, E1000_PRC511); 1637 temp = E1000_READ_REG(hw, E1000_PRC1023); 1638 temp = E1000_READ_REG(hw, E1000_PRC1522); 1639 temp = E1000_READ_REG(hw, E1000_PTC64); 1640 temp = E1000_READ_REG(hw, E1000_PTC127); 1641 temp = E1000_READ_REG(hw, E1000_PTC255); 1642 temp = E1000_READ_REG(hw, E1000_PTC511); 1643 temp = E1000_READ_REG(hw, E1000_PTC1023); 1644 temp = E1000_READ_REG(hw, E1000_PTC1522); 1645 1646 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1647 temp = E1000_READ_REG(hw, E1000_RXERRC); 1648 temp = E1000_READ_REG(hw, E1000_TNCRS); 1649 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1650 temp = E1000_READ_REG(hw, E1000_TSCTC); 1651 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1652} 1653