radeon_bios.c revision 255572
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $"); 31 32#include <dev/drm2/drmP.h> 33#include "radeon_reg.h" 34#include "radeon.h" 35#include "atom.h" 36 37/* 38 * BIOS. 39 */ 40 41/* If you boot an IGP board with a discrete card as the primary, 42 * the IGP rom is not accessible via the rom bar as the IGP rom is 43 * part of the system bios. On boot, the system bios puts a 44 * copy of the igp rom at the start of vram if a discrete card is 45 * present. 46 */ 47static bool igp_read_bios_from_vram(struct radeon_device *rdev) 48{ 49 drm_local_map_t bios_map; 50 uint8_t __iomem *bios; 51 resource_size_t vram_base; 52 resource_size_t size = 256 * 1024; /* ??? */ 53 54 DRM_INFO("%s: ===> Try IGP's VRAM...\n", __func__); 55 56 if (!(rdev->flags & RADEON_IS_IGP)) 57 if (!radeon_card_posted(rdev)) { 58 DRM_INFO("%s: not POSTed discrete card detected, skipping this method...\n", 59 __func__); 60 return false; 61 } 62 63 rdev->bios = NULL; 64 vram_base = drm_get_resource_start(rdev->ddev, 0); 65 DRM_INFO("%s: VRAM base address: 0x%jx\n", __func__, (uintmax_t)vram_base); 66 67 bios_map.offset = vram_base; 68 bios_map.size = size; 69 bios_map.type = 0; 70 bios_map.flags = 0; 71 bios_map.mtrr = 0; 72 drm_core_ioremap(&bios_map, rdev->ddev); 73 if (bios_map.virtual == NULL) { 74 DRM_INFO("%s: failed to ioremap\n", __func__); 75 return false; 76 } 77 bios = bios_map.virtual; 78 size = bios_map.size; 79 DRM_INFO("%s: Map address: %p (%ju bytes)\n", __func__, bios, (uintmax_t)size); 80 81 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 82 if (size == 0) { 83 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 84 } else { 85 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 86 __func__, bios[0], bios[1]); 87 } 88 drm_core_ioremapfree(&bios_map, rdev->ddev); 89 return false; 90 } 91 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK); 92 if (rdev->bios == NULL) { 93 drm_core_ioremapfree(&bios_map, rdev->ddev); 94 return false; 95 } 96 memcpy_fromio(rdev->bios, bios, size); 97 drm_core_ioremapfree(&bios_map, rdev->ddev); 98 return true; 99} 100 101static bool radeon_read_bios(struct radeon_device *rdev) 102{ 103 device_t vga_dev; 104 uint8_t __iomem *bios; 105 size_t size; 106 107 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__); 108 109 vga_dev = device_get_parent(rdev->dev); 110 rdev->bios = NULL; 111 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 112 bios = vga_pci_map_bios(vga_dev, &size); 113 if (!bios) { 114 return false; 115 } 116 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size); 117 118 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 119 if (size == 0) { 120 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 121 } else { 122 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 123 __func__, bios[0], bios[1]); 124 } 125 vga_pci_unmap_bios(vga_dev, bios); 126 } 127 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK); 128 memcpy(rdev->bios, bios, size); 129 vga_pci_unmap_bios(vga_dev, bios); 130 return true; 131} 132 133/* ATRM is used to get the BIOS on the discrete cards in 134 * dual-gpu systems. 135 */ 136/* retrieve the ROM in 4k blocks */ 137#define ATRM_BIOS_PAGE 4096 138/** 139 * radeon_atrm_call - fetch a chunk of the vbios 140 * 141 * @atrm_handle: acpi ATRM handle 142 * @bios: vbios image pointer 143 * @offset: offset of vbios image data to fetch 144 * @len: length of vbios image data to fetch 145 * 146 * Executes ATRM to fetch a chunk of the discrete 147 * vbios image on PX systems (all asics). 148 * Returns the length of the buffer fetched. 149 */ 150static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios, 151 int offset, int len) 152{ 153 ACPI_STATUS status; 154 ACPI_OBJECT atrm_arg_elements[2], *obj; 155 ACPI_OBJECT_LIST atrm_arg; 156 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 157 158 atrm_arg.Count = 2; 159 atrm_arg.Pointer = &atrm_arg_elements[0]; 160 161 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER; 162 atrm_arg_elements[0].Integer.Value = offset; 163 164 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER; 165 atrm_arg_elements[1].Integer.Value = len; 166 167 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer); 168 if (ACPI_FAILURE(status)) { 169 DRM_ERROR("failed to evaluate ATRM got %s\n", AcpiFormatException(status)); 170 return -ENODEV; 171 } 172 173 obj = (ACPI_OBJECT *)buffer.Pointer; 174 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length); 175 len = obj->Buffer.Length; 176 AcpiOsFree(buffer.Pointer); 177 return len; 178} 179 180static bool radeon_atrm_get_bios(struct radeon_device *rdev) 181{ 182 int ret; 183 int size = 256 * 1024; 184 int i; 185 device_t dev; 186 ACPI_HANDLE dhandle, atrm_handle; 187 ACPI_STATUS status; 188 bool found = false; 189 190 DRM_INFO("%s: ===> Try ATRM...\n", __func__); 191 192 /* ATRM is for the discrete card only */ 193 if (rdev->flags & RADEON_IS_IGP) { 194 DRM_INFO("%s: IGP card detected, skipping this method...\n", 195 __func__); 196 return false; 197 } 198 199#ifdef DUMBBELL_WIP 200 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 201#endif /* DUMBBELL_WIP */ 202 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) { 203 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n", 204 __func__, 205 pci_get_domain(dev), 206 pci_get_bus(dev), 207 pci_get_slot(dev), 208 pci_get_function(dev), 209 pci_get_vendor(dev), 210 pci_get_device(dev)); 211 DRM_INFO("%s: Get ACPI device handle\n", __func__); 212 dhandle = acpi_get_handle(dev); 213#ifdef DUMBBELL_WIP 214 if (!dhandle) 215 continue; 216#endif /* DUMBBELL_WIP */ 217 if (!dhandle) 218 return false; 219 220 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__); 221 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle); 222 if (!ACPI_FAILURE(status)) { 223 found = true; 224#ifdef DUMBBELL_WIP 225 break; 226#endif /* DUMBBELL_WIP */ 227 } else { 228 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n", 229 __func__, AcpiFormatException(status)); 230 } 231 } 232 233 if (!found) 234 return false; 235 236 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK); 237 if (!rdev->bios) { 238 DRM_ERROR("Unable to allocate bios\n"); 239 return false; 240 } 241 242 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 243 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__); 244 ret = radeon_atrm_call(atrm_handle, 245 rdev->bios, 246 (i * ATRM_BIOS_PAGE), 247 ATRM_BIOS_PAGE); 248 if (ret < ATRM_BIOS_PAGE) 249 break; 250 } 251 252 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 253 if (i == 0) { 254 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 255 } else { 256 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 257 __func__, rdev->bios[0], rdev->bios[1]); 258 } 259 free(rdev->bios, DRM_MEM_DRIVER); 260 return false; 261 } 262 return true; 263} 264 265static bool ni_read_disabled_bios(struct radeon_device *rdev) 266{ 267 u32 bus_cntl; 268 u32 d1vga_control; 269 u32 d2vga_control; 270 u32 vga_render_control; 271 u32 rom_cntl; 272 bool r; 273 274 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__); 275 276 bus_cntl = RREG32(R600_BUS_CNTL); 277 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 278 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 279 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 280 rom_cntl = RREG32(R600_ROM_CNTL); 281 282 /* enable the rom */ 283 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 284 /* Disable VGA mode */ 285 WREG32(AVIVO_D1VGA_CONTROL, 286 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 287 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 288 WREG32(AVIVO_D2VGA_CONTROL, 289 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 290 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 291 WREG32(AVIVO_VGA_RENDER_CONTROL, 292 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 293 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 294 295 r = radeon_read_bios(rdev); 296 297 /* restore regs */ 298 WREG32(R600_BUS_CNTL, bus_cntl); 299 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 300 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 301 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 302 WREG32(R600_ROM_CNTL, rom_cntl); 303 return r; 304} 305 306static bool r700_read_disabled_bios(struct radeon_device *rdev) 307{ 308 uint32_t viph_control; 309 uint32_t bus_cntl; 310 uint32_t d1vga_control; 311 uint32_t d2vga_control; 312 uint32_t vga_render_control; 313 uint32_t rom_cntl; 314 uint32_t cg_spll_func_cntl = 0; 315 uint32_t cg_spll_status; 316 bool r; 317 318 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__); 319 320 viph_control = RREG32(RADEON_VIPH_CONTROL); 321 bus_cntl = RREG32(R600_BUS_CNTL); 322 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 323 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 324 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 325 rom_cntl = RREG32(R600_ROM_CNTL); 326 327 /* disable VIP */ 328 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 329 /* enable the rom */ 330 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 331 /* Disable VGA mode */ 332 WREG32(AVIVO_D1VGA_CONTROL, 333 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 334 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 335 WREG32(AVIVO_D2VGA_CONTROL, 336 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 337 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 338 WREG32(AVIVO_VGA_RENDER_CONTROL, 339 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 340 341 if (rdev->family == CHIP_RV730) { 342 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 343 344 /* enable bypass mode */ 345 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 346 R600_SPLL_BYPASS_EN)); 347 348 /* wait for SPLL_CHG_STATUS to change to 1 */ 349 cg_spll_status = 0; 350 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 351 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 352 353 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 354 } else 355 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 356 357 r = radeon_read_bios(rdev); 358 359 /* restore regs */ 360 if (rdev->family == CHIP_RV730) { 361 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 362 363 /* wait for SPLL_CHG_STATUS to change to 1 */ 364 cg_spll_status = 0; 365 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 366 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 367 } 368 WREG32(RADEON_VIPH_CONTROL, viph_control); 369 WREG32(R600_BUS_CNTL, bus_cntl); 370 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 371 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 372 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 373 WREG32(R600_ROM_CNTL, rom_cntl); 374 return r; 375} 376 377static bool r600_read_disabled_bios(struct radeon_device *rdev) 378{ 379 uint32_t viph_control; 380 uint32_t bus_cntl; 381 uint32_t d1vga_control; 382 uint32_t d2vga_control; 383 uint32_t vga_render_control; 384 uint32_t rom_cntl; 385 uint32_t general_pwrmgt; 386 uint32_t low_vid_lower_gpio_cntl; 387 uint32_t medium_vid_lower_gpio_cntl; 388 uint32_t high_vid_lower_gpio_cntl; 389 uint32_t ctxsw_vid_lower_gpio_cntl; 390 uint32_t lower_gpio_enable; 391 bool r; 392 393 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__); 394 395 viph_control = RREG32(RADEON_VIPH_CONTROL); 396 bus_cntl = RREG32(R600_BUS_CNTL); 397 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 398 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 399 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 400 rom_cntl = RREG32(R600_ROM_CNTL); 401 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 402 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 403 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 404 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 405 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 406 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 407 408 /* disable VIP */ 409 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 410 /* enable the rom */ 411 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 412 /* Disable VGA mode */ 413 WREG32(AVIVO_D1VGA_CONTROL, 414 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 415 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 416 WREG32(AVIVO_D2VGA_CONTROL, 417 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 418 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 419 WREG32(AVIVO_VGA_RENDER_CONTROL, 420 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 421 422 WREG32(R600_ROM_CNTL, 423 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 424 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 425 R600_SCK_OVERWRITE)); 426 427 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 428 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 429 (low_vid_lower_gpio_cntl & ~0x400)); 430 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 431 (medium_vid_lower_gpio_cntl & ~0x400)); 432 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 433 (high_vid_lower_gpio_cntl & ~0x400)); 434 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 435 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 436 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 437 438 r = radeon_read_bios(rdev); 439 440 /* restore regs */ 441 WREG32(RADEON_VIPH_CONTROL, viph_control); 442 WREG32(R600_BUS_CNTL, bus_cntl); 443 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 444 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 445 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 446 WREG32(R600_ROM_CNTL, rom_cntl); 447 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 448 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 449 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 450 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 451 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 452 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 453 return r; 454} 455 456static bool avivo_read_disabled_bios(struct radeon_device *rdev) 457{ 458 uint32_t seprom_cntl1; 459 uint32_t viph_control; 460 uint32_t bus_cntl; 461 uint32_t d1vga_control; 462 uint32_t d2vga_control; 463 uint32_t vga_render_control; 464 uint32_t gpiopad_a; 465 uint32_t gpiopad_en; 466 uint32_t gpiopad_mask; 467 bool r; 468 469 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__); 470 471 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 472 viph_control = RREG32(RADEON_VIPH_CONTROL); 473 bus_cntl = RREG32(RV370_BUS_CNTL); 474 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 475 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 476 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 477 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 478 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 479 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 480 481 WREG32(RADEON_SEPROM_CNTL1, 482 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 483 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 484 WREG32(RADEON_GPIOPAD_A, 0); 485 WREG32(RADEON_GPIOPAD_EN, 0); 486 WREG32(RADEON_GPIOPAD_MASK, 0); 487 488 /* disable VIP */ 489 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 490 491 /* enable the rom */ 492 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 493 494 /* Disable VGA mode */ 495 WREG32(AVIVO_D1VGA_CONTROL, 496 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 497 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 498 WREG32(AVIVO_D2VGA_CONTROL, 499 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 500 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 501 WREG32(AVIVO_VGA_RENDER_CONTROL, 502 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 503 504 r = radeon_read_bios(rdev); 505 506 /* restore regs */ 507 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 508 WREG32(RADEON_VIPH_CONTROL, viph_control); 509 WREG32(RV370_BUS_CNTL, bus_cntl); 510 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 511 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 512 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 513 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 514 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 515 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 516 return r; 517} 518 519static bool legacy_read_disabled_bios(struct radeon_device *rdev) 520{ 521 uint32_t seprom_cntl1; 522 uint32_t viph_control; 523 uint32_t bus_cntl; 524 uint32_t crtc_gen_cntl; 525 uint32_t crtc2_gen_cntl; 526 uint32_t crtc_ext_cntl; 527 uint32_t fp2_gen_cntl; 528 bool r; 529 530 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__); 531 532 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 533 viph_control = RREG32(RADEON_VIPH_CONTROL); 534 if (rdev->flags & RADEON_IS_PCIE) 535 bus_cntl = RREG32(RV370_BUS_CNTL); 536 else 537 bus_cntl = RREG32(RADEON_BUS_CNTL); 538 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 539 crtc2_gen_cntl = 0; 540 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 541 fp2_gen_cntl = 0; 542 543#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 544 545 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 546 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 547 } 548 549 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 550 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 551 } 552 553 WREG32(RADEON_SEPROM_CNTL1, 554 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 555 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 556 557 /* disable VIP */ 558 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 559 560 /* enable the rom */ 561 if (rdev->flags & RADEON_IS_PCIE) 562 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 563 else 564 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 565 566 /* Turn off mem requests and CRTC for both controllers */ 567 WREG32(RADEON_CRTC_GEN_CNTL, 568 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 569 (RADEON_CRTC_DISP_REQ_EN_B | 570 RADEON_CRTC_EXT_DISP_EN))); 571 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 572 WREG32(RADEON_CRTC2_GEN_CNTL, 573 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 574 RADEON_CRTC2_DISP_REQ_EN_B)); 575 } 576 /* Turn off CRTC */ 577 WREG32(RADEON_CRTC_EXT_CNTL, 578 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 579 (RADEON_CRTC_SYNC_TRISTAT | 580 RADEON_CRTC_DISPLAY_DIS))); 581 582 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 583 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 584 } 585 586 r = radeon_read_bios(rdev); 587 588 /* restore regs */ 589 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 590 WREG32(RADEON_VIPH_CONTROL, viph_control); 591 if (rdev->flags & RADEON_IS_PCIE) 592 WREG32(RV370_BUS_CNTL, bus_cntl); 593 else 594 WREG32(RADEON_BUS_CNTL, bus_cntl); 595 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 596 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 597 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 598 } 599 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 600 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 601 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 602 } 603 return r; 604} 605 606static bool radeon_read_disabled_bios(struct radeon_device *rdev) 607{ 608 if (rdev->flags & RADEON_IS_IGP) 609 return igp_read_bios_from_vram(rdev); 610 else if (rdev->family >= CHIP_BARTS) 611 return ni_read_disabled_bios(rdev); 612 else if (rdev->family >= CHIP_RV770) 613 return r700_read_disabled_bios(rdev); 614 else if (rdev->family >= CHIP_R600) 615 return r600_read_disabled_bios(rdev); 616 else if (rdev->family >= CHIP_RS600) 617 return avivo_read_disabled_bios(rdev); 618 else 619 return legacy_read_disabled_bios(rdev); 620} 621 622static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 623{ 624 bool ret = false; 625 ACPI_TABLE_HEADER *hdr; 626 ACPI_SIZE tbl_size; 627 UEFI_ACPI_VFCT *vfct; 628 GOP_VBIOS_CONTENT *vbios; 629 VFCT_IMAGE_HEADER *vhdr; 630 ACPI_STATUS status; 631 632 DRM_INFO("%s: ===> Try VFCT...\n", __func__); 633 634 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__); 635 status = AcpiGetTable("VFCT", 1, &hdr); 636 if (!ACPI_SUCCESS(status)) { 637 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n", 638 __func__, AcpiFormatException(status)); 639 return false; 640 } 641 tbl_size = hdr->Length; 642 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 643 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 644 goto out_unmap; 645 } 646 647 vfct = (UEFI_ACPI_VFCT *)hdr; 648 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 649 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 650 goto out_unmap; 651 } 652 653 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 654 vhdr = &vbios->VbiosHeader; 655 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 656 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 657 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 658 659 if (vhdr->PCIBus != rdev->ddev->pci_bus || 660 vhdr->PCIDevice != rdev->ddev->pci_slot || 661 vhdr->PCIFunction != rdev->ddev->pci_func || 662 vhdr->VendorID != rdev->ddev->pci_vendor || 663 vhdr->DeviceID != rdev->ddev->pci_device) { 664 DRM_INFO("ACPI VFCT table is not for this card\n"); 665 goto out_unmap; 666 }; 667 668 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 669 DRM_ERROR("ACPI VFCT image truncated\n"); 670 goto out_unmap; 671 } 672 673 rdev->bios = malloc(vhdr->ImageLength, DRM_MEM_DRIVER, M_WAITOK); 674 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength); 675 ret = !!rdev->bios; 676 677out_unmap: 678 return ret; 679} 680 681bool radeon_get_bios(struct radeon_device *rdev) 682{ 683 bool r; 684 uint16_t tmp; 685 686 r = radeon_atrm_get_bios(rdev); 687 if (r == false) 688 r = radeon_acpi_vfct_bios(rdev); 689 if (r == false) 690 r = igp_read_bios_from_vram(rdev); 691 if (r == false) 692 r = radeon_read_bios(rdev); 693 if (r == false) { 694 r = radeon_read_disabled_bios(rdev); 695 } 696 if (r == false || rdev->bios == NULL) { 697 DRM_ERROR("Unable to locate a BIOS ROM\n"); 698 rdev->bios = NULL; 699 return false; 700 } 701 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 702 DRM_ERROR("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 703 goto free_bios; 704 } 705 706 tmp = RBIOS16(0x18); 707 if (RBIOS8(tmp + 0x14) != 0x0) { 708 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 709 goto free_bios; 710 } 711 712 rdev->bios_header_start = RBIOS16(0x48); 713 if (!rdev->bios_header_start) { 714 goto free_bios; 715 } 716 tmp = rdev->bios_header_start + 4; 717 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 718 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 719 rdev->is_atom_bios = true; 720 } else { 721 rdev->is_atom_bios = false; 722 } 723 724 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 725 return true; 726free_bios: 727 free(rdev->bios, DRM_MEM_DRIVER); 728 rdev->bios = NULL; 729 return false; 730} 731