radeon_bios.c revision 254885
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 254885 2013-08-25 19:37:15Z dumbbell $"); 31 32#include <dev/drm2/drmP.h> 33#include "radeon_reg.h" 34#include "radeon.h" 35#include "atom.h" 36 37/* 38 * BIOS. 39 */ 40 41/* If you boot an IGP board with a discrete card as the primary, 42 * the IGP rom is not accessible via the rom bar as the IGP rom is 43 * part of the system bios. On boot, the system bios puts a 44 * copy of the igp rom at the start of vram if a discrete card is 45 * present. 46 */ 47static bool igp_read_bios_from_vram(struct radeon_device *rdev) 48{ 49 drm_local_map_t bios_map; 50 uint8_t __iomem *bios; 51 resource_size_t vram_base; 52 resource_size_t size = 256 * 1024; /* ??? */ 53 54 DRM_INFO("%s: ===> Try IGP's VRAM...\n", __func__); 55 56 if (!(rdev->flags & RADEON_IS_IGP)) 57 if (!radeon_card_posted(rdev)) { 58 DRM_INFO("%s: not POSTed discrete card detected, skipping this method...\n", 59 __func__); 60 return false; 61 } 62 63 rdev->bios = NULL; 64 vram_base = drm_get_resource_start(rdev->ddev, 0); 65 DRM_INFO("%s: VRAM base address: 0x%jx\n", __func__, (uintmax_t)vram_base); 66 67 bios_map.offset = vram_base; 68 bios_map.size = size; 69 bios_map.type = 0; 70 bios_map.flags = 0; 71 bios_map.mtrr = 0; 72 drm_core_ioremap(&bios_map, rdev->ddev); 73 if (bios_map.virtual == NULL) { 74 DRM_INFO("%s: failed to ioremap\n", __func__); 75 return false; 76 } 77 bios = bios_map.virtual; 78 size = bios_map.size; 79 DRM_INFO("%s: Map address: %p (%ju bytes)\n", __func__, bios, (uintmax_t)size); 80 81 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 82 if (size == 0) { 83 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 84 } else { 85 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 86 __func__, bios[0], bios[1]); 87 } 88 drm_core_ioremapfree(&bios_map, rdev->ddev); 89 return false; 90 } 91 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK); 92 if (rdev->bios == NULL) { 93 drm_core_ioremapfree(&bios_map, rdev->ddev); 94 return false; 95 } 96 memcpy_fromio(rdev->bios, bios, size); 97 drm_core_ioremapfree(&bios_map, rdev->ddev); 98 return true; 99} 100 101static bool radeon_read_bios(struct radeon_device *rdev) 102{ 103 uint8_t __iomem *bios; 104 size_t size; 105 106 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__); 107 108 rdev->bios = NULL; 109 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 110 bios = vga_pci_map_bios(rdev->dev, &size); 111 if (!bios) { 112 return false; 113 } 114 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size); 115 116 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 117 if (size == 0) { 118 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 119 } else { 120 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 121 __func__, bios[0], bios[1]); 122 } 123 vga_pci_unmap_bios(rdev->dev, bios); 124 } 125 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK); 126 memcpy(rdev->bios, bios, size); 127 vga_pci_unmap_bios(rdev->dev, bios); 128 return true; 129} 130 131/* ATRM is used to get the BIOS on the discrete cards in 132 * dual-gpu systems. 133 */ 134/* retrieve the ROM in 4k blocks */ 135#define ATRM_BIOS_PAGE 4096 136/** 137 * radeon_atrm_call - fetch a chunk of the vbios 138 * 139 * @atrm_handle: acpi ATRM handle 140 * @bios: vbios image pointer 141 * @offset: offset of vbios image data to fetch 142 * @len: length of vbios image data to fetch 143 * 144 * Executes ATRM to fetch a chunk of the discrete 145 * vbios image on PX systems (all asics). 146 * Returns the length of the buffer fetched. 147 */ 148static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios, 149 int offset, int len) 150{ 151 ACPI_STATUS status; 152 ACPI_OBJECT atrm_arg_elements[2], *obj; 153 ACPI_OBJECT_LIST atrm_arg; 154 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 155 156 atrm_arg.Count = 2; 157 atrm_arg.Pointer = &atrm_arg_elements[0]; 158 159 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER; 160 atrm_arg_elements[0].Integer.Value = offset; 161 162 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER; 163 atrm_arg_elements[1].Integer.Value = len; 164 165 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer); 166 if (ACPI_FAILURE(status)) { 167 DRM_ERROR("failed to evaluate ATRM got %s\n", AcpiFormatException(status)); 168 return -ENODEV; 169 } 170 171 obj = (ACPI_OBJECT *)buffer.Pointer; 172 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length); 173 len = obj->Buffer.Length; 174 AcpiOsFree(buffer.Pointer); 175 return len; 176} 177 178static bool radeon_atrm_get_bios(struct radeon_device *rdev) 179{ 180 int ret; 181 int size = 256 * 1024; 182 int i; 183 device_t dev; 184 ACPI_HANDLE dhandle, atrm_handle; 185 ACPI_STATUS status; 186 bool found = false; 187 188 DRM_INFO("%s: ===> Try ATRM...\n", __func__); 189 190 /* ATRM is for the discrete card only */ 191 if (rdev->flags & RADEON_IS_IGP) { 192 DRM_INFO("%s: IGP card detected, skipping this method...\n", 193 __func__); 194 return false; 195 } 196 197#ifdef DUMBBELL_WIP 198 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 199#endif /* DUMBBELL_WIP */ 200 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) { 201 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n", 202 __func__, 203 pci_get_domain(dev), 204 pci_get_bus(dev), 205 pci_get_slot(dev), 206 pci_get_function(dev), 207 pci_get_vendor(dev), 208 pci_get_device(dev)); 209 DRM_INFO("%s: Get ACPI device handle\n", __func__); 210 dhandle = acpi_get_handle(dev); 211#ifdef DUMBBELL_WIP 212 if (!dhandle) 213 continue; 214#endif /* DUMBBELL_WIP */ 215 if (!dhandle) 216 return false; 217 218 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__); 219 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle); 220 if (!ACPI_FAILURE(status)) { 221 found = true; 222#ifdef DUMBBELL_WIP 223 break; 224#endif /* DUMBBELL_WIP */ 225 } else { 226 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n", 227 __func__, AcpiFormatException(status)); 228 } 229 } 230 231 if (!found) 232 return false; 233 234 rdev->bios = malloc(size, DRM_MEM_DRIVER, M_WAITOK); 235 if (!rdev->bios) { 236 DRM_ERROR("Unable to allocate bios\n"); 237 return false; 238 } 239 240 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 241 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__); 242 ret = radeon_atrm_call(atrm_handle, 243 rdev->bios, 244 (i * ATRM_BIOS_PAGE), 245 ATRM_BIOS_PAGE); 246 if (ret < ATRM_BIOS_PAGE) 247 break; 248 } 249 250 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 251 if (i == 0) { 252 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 253 } else { 254 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 255 __func__, rdev->bios[0], rdev->bios[1]); 256 } 257 free(rdev->bios, DRM_MEM_DRIVER); 258 return false; 259 } 260 return true; 261} 262 263static bool ni_read_disabled_bios(struct radeon_device *rdev) 264{ 265 u32 bus_cntl; 266 u32 d1vga_control; 267 u32 d2vga_control; 268 u32 vga_render_control; 269 u32 rom_cntl; 270 bool r; 271 272 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__); 273 274 bus_cntl = RREG32(R600_BUS_CNTL); 275 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 276 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 277 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 278 rom_cntl = RREG32(R600_ROM_CNTL); 279 280 /* enable the rom */ 281 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 282 /* Disable VGA mode */ 283 WREG32(AVIVO_D1VGA_CONTROL, 284 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 285 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 286 WREG32(AVIVO_D2VGA_CONTROL, 287 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 288 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 289 WREG32(AVIVO_VGA_RENDER_CONTROL, 290 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 291 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 292 293 r = radeon_read_bios(rdev); 294 295 /* restore regs */ 296 WREG32(R600_BUS_CNTL, bus_cntl); 297 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 298 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 299 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 300 WREG32(R600_ROM_CNTL, rom_cntl); 301 return r; 302} 303 304static bool r700_read_disabled_bios(struct radeon_device *rdev) 305{ 306 uint32_t viph_control; 307 uint32_t bus_cntl; 308 uint32_t d1vga_control; 309 uint32_t d2vga_control; 310 uint32_t vga_render_control; 311 uint32_t rom_cntl; 312 uint32_t cg_spll_func_cntl = 0; 313 uint32_t cg_spll_status; 314 bool r; 315 316 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__); 317 318 viph_control = RREG32(RADEON_VIPH_CONTROL); 319 bus_cntl = RREG32(R600_BUS_CNTL); 320 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 321 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 322 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 323 rom_cntl = RREG32(R600_ROM_CNTL); 324 325 /* disable VIP */ 326 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 327 /* enable the rom */ 328 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 329 /* Disable VGA mode */ 330 WREG32(AVIVO_D1VGA_CONTROL, 331 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 332 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 333 WREG32(AVIVO_D2VGA_CONTROL, 334 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 335 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 336 WREG32(AVIVO_VGA_RENDER_CONTROL, 337 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 338 339 if (rdev->family == CHIP_RV730) { 340 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 341 342 /* enable bypass mode */ 343 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 344 R600_SPLL_BYPASS_EN)); 345 346 /* wait for SPLL_CHG_STATUS to change to 1 */ 347 cg_spll_status = 0; 348 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 349 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 350 351 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 352 } else 353 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 354 355 r = radeon_read_bios(rdev); 356 357 /* restore regs */ 358 if (rdev->family == CHIP_RV730) { 359 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 360 361 /* wait for SPLL_CHG_STATUS to change to 1 */ 362 cg_spll_status = 0; 363 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 364 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 365 } 366 WREG32(RADEON_VIPH_CONTROL, viph_control); 367 WREG32(R600_BUS_CNTL, bus_cntl); 368 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 369 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 370 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 371 WREG32(R600_ROM_CNTL, rom_cntl); 372 return r; 373} 374 375static bool r600_read_disabled_bios(struct radeon_device *rdev) 376{ 377 uint32_t viph_control; 378 uint32_t bus_cntl; 379 uint32_t d1vga_control; 380 uint32_t d2vga_control; 381 uint32_t vga_render_control; 382 uint32_t rom_cntl; 383 uint32_t general_pwrmgt; 384 uint32_t low_vid_lower_gpio_cntl; 385 uint32_t medium_vid_lower_gpio_cntl; 386 uint32_t high_vid_lower_gpio_cntl; 387 uint32_t ctxsw_vid_lower_gpio_cntl; 388 uint32_t lower_gpio_enable; 389 bool r; 390 391 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__); 392 393 viph_control = RREG32(RADEON_VIPH_CONTROL); 394 bus_cntl = RREG32(R600_BUS_CNTL); 395 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 396 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 397 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 398 rom_cntl = RREG32(R600_ROM_CNTL); 399 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 400 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 401 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 402 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 403 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 404 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 405 406 /* disable VIP */ 407 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 408 /* enable the rom */ 409 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 410 /* Disable VGA mode */ 411 WREG32(AVIVO_D1VGA_CONTROL, 412 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 413 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 414 WREG32(AVIVO_D2VGA_CONTROL, 415 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 416 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 417 WREG32(AVIVO_VGA_RENDER_CONTROL, 418 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 419 420 WREG32(R600_ROM_CNTL, 421 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 422 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 423 R600_SCK_OVERWRITE)); 424 425 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 426 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 427 (low_vid_lower_gpio_cntl & ~0x400)); 428 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 429 (medium_vid_lower_gpio_cntl & ~0x400)); 430 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 431 (high_vid_lower_gpio_cntl & ~0x400)); 432 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 433 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 434 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 435 436 r = radeon_read_bios(rdev); 437 438 /* restore regs */ 439 WREG32(RADEON_VIPH_CONTROL, viph_control); 440 WREG32(R600_BUS_CNTL, bus_cntl); 441 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 442 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 443 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 444 WREG32(R600_ROM_CNTL, rom_cntl); 445 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 446 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 447 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 448 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 449 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 450 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 451 return r; 452} 453 454static bool avivo_read_disabled_bios(struct radeon_device *rdev) 455{ 456 uint32_t seprom_cntl1; 457 uint32_t viph_control; 458 uint32_t bus_cntl; 459 uint32_t d1vga_control; 460 uint32_t d2vga_control; 461 uint32_t vga_render_control; 462 uint32_t gpiopad_a; 463 uint32_t gpiopad_en; 464 uint32_t gpiopad_mask; 465 bool r; 466 467 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__); 468 469 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 470 viph_control = RREG32(RADEON_VIPH_CONTROL); 471 bus_cntl = RREG32(RV370_BUS_CNTL); 472 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 473 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 474 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 475 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 476 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 477 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 478 479 WREG32(RADEON_SEPROM_CNTL1, 480 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 481 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 482 WREG32(RADEON_GPIOPAD_A, 0); 483 WREG32(RADEON_GPIOPAD_EN, 0); 484 WREG32(RADEON_GPIOPAD_MASK, 0); 485 486 /* disable VIP */ 487 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 488 489 /* enable the rom */ 490 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 491 492 /* Disable VGA mode */ 493 WREG32(AVIVO_D1VGA_CONTROL, 494 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 495 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 496 WREG32(AVIVO_D2VGA_CONTROL, 497 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 498 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 499 WREG32(AVIVO_VGA_RENDER_CONTROL, 500 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 501 502 r = radeon_read_bios(rdev); 503 504 /* restore regs */ 505 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 506 WREG32(RADEON_VIPH_CONTROL, viph_control); 507 WREG32(RV370_BUS_CNTL, bus_cntl); 508 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 509 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 510 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 511 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 512 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 513 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 514 return r; 515} 516 517static bool legacy_read_disabled_bios(struct radeon_device *rdev) 518{ 519 uint32_t seprom_cntl1; 520 uint32_t viph_control; 521 uint32_t bus_cntl; 522 uint32_t crtc_gen_cntl; 523 uint32_t crtc2_gen_cntl; 524 uint32_t crtc_ext_cntl; 525 uint32_t fp2_gen_cntl; 526 bool r; 527 528 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__); 529 530 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 531 viph_control = RREG32(RADEON_VIPH_CONTROL); 532 if (rdev->flags & RADEON_IS_PCIE) 533 bus_cntl = RREG32(RV370_BUS_CNTL); 534 else 535 bus_cntl = RREG32(RADEON_BUS_CNTL); 536 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 537 crtc2_gen_cntl = 0; 538 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 539 fp2_gen_cntl = 0; 540 541#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 542 543 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 544 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 545 } 546 547 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 548 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 549 } 550 551 WREG32(RADEON_SEPROM_CNTL1, 552 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 553 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 554 555 /* disable VIP */ 556 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 557 558 /* enable the rom */ 559 if (rdev->flags & RADEON_IS_PCIE) 560 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 561 else 562 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 563 564 /* Turn off mem requests and CRTC for both controllers */ 565 WREG32(RADEON_CRTC_GEN_CNTL, 566 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 567 (RADEON_CRTC_DISP_REQ_EN_B | 568 RADEON_CRTC_EXT_DISP_EN))); 569 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 570 WREG32(RADEON_CRTC2_GEN_CNTL, 571 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 572 RADEON_CRTC2_DISP_REQ_EN_B)); 573 } 574 /* Turn off CRTC */ 575 WREG32(RADEON_CRTC_EXT_CNTL, 576 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 577 (RADEON_CRTC_SYNC_TRISTAT | 578 RADEON_CRTC_DISPLAY_DIS))); 579 580 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 581 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 582 } 583 584 r = radeon_read_bios(rdev); 585 586 /* restore regs */ 587 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 588 WREG32(RADEON_VIPH_CONTROL, viph_control); 589 if (rdev->flags & RADEON_IS_PCIE) 590 WREG32(RV370_BUS_CNTL, bus_cntl); 591 else 592 WREG32(RADEON_BUS_CNTL, bus_cntl); 593 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 594 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 595 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 596 } 597 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 598 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 599 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 600 } 601 return r; 602} 603 604static bool radeon_read_disabled_bios(struct radeon_device *rdev) 605{ 606 if (rdev->flags & RADEON_IS_IGP) 607 return igp_read_bios_from_vram(rdev); 608 else if (rdev->family >= CHIP_BARTS) 609 return ni_read_disabled_bios(rdev); 610 else if (rdev->family >= CHIP_RV770) 611 return r700_read_disabled_bios(rdev); 612 else if (rdev->family >= CHIP_R600) 613 return r600_read_disabled_bios(rdev); 614 else if (rdev->family >= CHIP_RS600) 615 return avivo_read_disabled_bios(rdev); 616 else 617 return legacy_read_disabled_bios(rdev); 618} 619 620static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 621{ 622 bool ret = false; 623 ACPI_TABLE_HEADER *hdr; 624 ACPI_SIZE tbl_size; 625 UEFI_ACPI_VFCT *vfct; 626 GOP_VBIOS_CONTENT *vbios; 627 VFCT_IMAGE_HEADER *vhdr; 628 ACPI_STATUS status; 629 630 DRM_INFO("%s: ===> Try VFCT...\n", __func__); 631 632 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__); 633 status = AcpiGetTable("VFCT", 1, &hdr); 634 if (!ACPI_SUCCESS(status)) { 635 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n", 636 __func__, AcpiFormatException(status)); 637 return false; 638 } 639 tbl_size = hdr->Length; 640 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 641 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 642 goto out_unmap; 643 } 644 645 vfct = (UEFI_ACPI_VFCT *)hdr; 646 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 647 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 648 goto out_unmap; 649 } 650 651 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 652 vhdr = &vbios->VbiosHeader; 653 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 654 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 655 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 656 657 if (vhdr->PCIBus != rdev->ddev->pci_bus || 658 vhdr->PCIDevice != rdev->ddev->pci_slot || 659 vhdr->PCIFunction != rdev->ddev->pci_func || 660 vhdr->VendorID != rdev->ddev->pci_vendor || 661 vhdr->DeviceID != rdev->ddev->pci_device) { 662 DRM_INFO("ACPI VFCT table is not for this card\n"); 663 goto out_unmap; 664 }; 665 666 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 667 DRM_ERROR("ACPI VFCT image truncated\n"); 668 goto out_unmap; 669 } 670 671 rdev->bios = malloc(vhdr->ImageLength, DRM_MEM_DRIVER, M_WAITOK); 672 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength); 673 ret = !!rdev->bios; 674 675out_unmap: 676 return ret; 677} 678 679bool radeon_get_bios(struct radeon_device *rdev) 680{ 681 bool r; 682 uint16_t tmp; 683 684 r = radeon_atrm_get_bios(rdev); 685 if (r == false) 686 r = radeon_acpi_vfct_bios(rdev); 687 if (r == false) 688 r = igp_read_bios_from_vram(rdev); 689 if (r == false) 690 r = radeon_read_bios(rdev); 691 if (r == false) { 692 r = radeon_read_disabled_bios(rdev); 693 } 694 if (r == false || rdev->bios == NULL) { 695 DRM_ERROR("Unable to locate a BIOS ROM\n"); 696 rdev->bios = NULL; 697 return false; 698 } 699 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 700 DRM_ERROR("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 701 goto free_bios; 702 } 703 704 tmp = RBIOS16(0x18); 705 if (RBIOS8(tmp + 0x14) != 0x0) { 706 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 707 goto free_bios; 708 } 709 710 rdev->bios_header_start = RBIOS16(0x48); 711 if (!rdev->bios_header_start) { 712 goto free_bios; 713 } 714 tmp = rdev->bios_header_start + 4; 715 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 716 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 717 rdev->is_atom_bios = true; 718 } else { 719 rdev->is_atom_bios = false; 720 } 721 722 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 723 return true; 724free_bios: 725 free(rdev->bios, DRM_MEM_DRIVER); 726 rdev->bios = NULL; 727 return false; 728} 729