1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2005 Nicolai Haehnle et al. 3254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Nicolai Haehnle 25254885Sdumbbell * Jerome Glisse 26254885Sdumbbell */ 27254885Sdumbbell#ifndef _R300_REG_H_ 28254885Sdumbbell#define _R300_REG_H_ 29254885Sdumbbell 30254885Sdumbbell#include <sys/cdefs.h> 31254885Sdumbbell__FBSDID("$FreeBSD: releng/11.0/sys/dev/drm2/radeon/r300_reg.h 300050 2016-05-17 12:52:31Z eadler $"); 32254885Sdumbbell 33254885Sdumbbell#define R300_SURF_TILE_MACRO (1<<16) 34254885Sdumbbell#define R300_SURF_TILE_MICRO (2<<16) 35254885Sdumbbell#define R300_SURF_TILE_BOTH (3<<16) 36254885Sdumbbell 37254885Sdumbbell 38254885Sdumbbell#define R300_MC_INIT_MISC_LAT_TIMER 0x180 39254885Sdumbbell# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 40254885Sdumbbell# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 41254885Sdumbbell# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 42254885Sdumbbell# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 43254885Sdumbbell# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 44254885Sdumbbell# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 45254885Sdumbbell# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 46254885Sdumbbell# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 47254885Sdumbbell 48254885Sdumbbell#define R300_MC_INIT_GFX_LAT_TIMER 0x154 49254885Sdumbbell# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 50254885Sdumbbell# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 51254885Sdumbbell# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 52254885Sdumbbell# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 53254885Sdumbbell# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 54254885Sdumbbell# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 55254885Sdumbbell# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 56254885Sdumbbell# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 57254885Sdumbbell 58254885Sdumbbell/* 59254885Sdumbbell * This file contains registers and constants for the R300. They have been 60254885Sdumbbell * found mostly by examining command buffers captured using glxtest, as well 61254885Sdumbbell * as by extrapolating some known registers and constants from the R200. 62254885Sdumbbell * I am fairly certain that they are correct unless stated otherwise 63254885Sdumbbell * in comments. 64254885Sdumbbell */ 65254885Sdumbbell 66254885Sdumbbell#define R300_SE_VPORT_XSCALE 0x1D98 67254885Sdumbbell#define R300_SE_VPORT_XOFFSET 0x1D9C 68254885Sdumbbell#define R300_SE_VPORT_YSCALE 0x1DA0 69254885Sdumbbell#define R300_SE_VPORT_YOFFSET 0x1DA4 70254885Sdumbbell#define R300_SE_VPORT_ZSCALE 0x1DA8 71254885Sdumbbell#define R300_SE_VPORT_ZOFFSET 0x1DAC 72254885Sdumbbell 73254885Sdumbbell 74254885Sdumbbell/* 75254885Sdumbbell * Vertex Array Processing (VAP) Control 76254885Sdumbbell * Stolen from r200 code from Christoph Brill (It's a guess!) 77254885Sdumbbell */ 78254885Sdumbbell#define R300_VAP_CNTL 0x2080 79254885Sdumbbell 80254885Sdumbbell/* This register is written directly and also starts data section 81254885Sdumbbell * in many 3d CP_PACKET3's 82254885Sdumbbell */ 83254885Sdumbbell#define R300_VAP_VF_CNTL 0x2084 84254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 85254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) 86254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) 87254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) 88254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) 89254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) 90254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) 91254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) 92254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) 93254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) 94254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) 95254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) 96254885Sdumbbell 97254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 98254885Sdumbbell /* State based - direct writes to registers trigger vertex 99254885Sdumbbell generation */ 100254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) 101254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) 102254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) 103254885Sdumbbell# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) 104254885Sdumbbell 105254885Sdumbbell /* I don't think I saw these three used.. */ 106254885Sdumbbell# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 107254885Sdumbbell# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 108254885Sdumbbell# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 109254885Sdumbbell 110254885Sdumbbell /* index size - when not set the indices are assumed to be 16 bit */ 111254885Sdumbbell# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) 112254885Sdumbbell /* number of vertices */ 113254885Sdumbbell# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 114254885Sdumbbell 115254885Sdumbbell/* BEGIN: Wild guesses */ 116254885Sdumbbell#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 117254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) 118254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) 119254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ 120254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ 121254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ 122254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ 123254885Sdumbbell 124254885Sdumbbell#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 125254885Sdumbbell /* each of the following is 3 bits wide, specifies number 126254885Sdumbbell of components */ 127254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 128254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 129254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 130254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 131254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 132254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 133254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 134254885Sdumbbell# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 135254885Sdumbbell/* END: Wild guesses */ 136254885Sdumbbell 137254885Sdumbbell#define R300_SE_VTE_CNTL 0x20b0 138254885Sdumbbell# define R300_VPORT_X_SCALE_ENA 0x00000001 139254885Sdumbbell# define R300_VPORT_X_OFFSET_ENA 0x00000002 140254885Sdumbbell# define R300_VPORT_Y_SCALE_ENA 0x00000004 141254885Sdumbbell# define R300_VPORT_Y_OFFSET_ENA 0x00000008 142254885Sdumbbell# define R300_VPORT_Z_SCALE_ENA 0x00000010 143254885Sdumbbell# define R300_VPORT_Z_OFFSET_ENA 0x00000020 144254885Sdumbbell# define R300_VTX_XY_FMT 0x00000100 145254885Sdumbbell# define R300_VTX_Z_FMT 0x00000200 146254885Sdumbbell# define R300_VTX_W0_FMT 0x00000400 147254885Sdumbbell# define R300_VTX_W0_NORMALIZE 0x00000800 148254885Sdumbbell# define R300_VTX_ST_DENORMALIZED 0x00001000 149254885Sdumbbell 150254885Sdumbbell/* BEGIN: Vertex data assembly - lots of uncertainties */ 151254885Sdumbbell 152254885Sdumbbell/* gap */ 153254885Sdumbbell 154254885Sdumbbell#define R300_VAP_CNTL_STATUS 0x2140 155254885Sdumbbell# define R300_VC_NO_SWAP (0 << 0) 156254885Sdumbbell# define R300_VC_16BIT_SWAP (1 << 0) 157254885Sdumbbell# define R300_VC_32BIT_SWAP (2 << 0) 158254885Sdumbbell# define R300_VAP_TCL_BYPASS (1 << 8) 159254885Sdumbbell 160254885Sdumbbell/* gap */ 161254885Sdumbbell 162254885Sdumbbell/* Where do we get our vertex data? 163254885Sdumbbell * 164254885Sdumbbell * Vertex data either comes either from immediate mode registers or from 165254885Sdumbbell * vertex arrays. 166254885Sdumbbell * There appears to be no mixed mode (though we can force the pitch of 167254885Sdumbbell * vertex arrays to 0, effectively reusing the same element over and over 168254885Sdumbbell * again). 169254885Sdumbbell * 170254885Sdumbbell * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure 171254885Sdumbbell * if these registers influence vertex array processing. 172254885Sdumbbell * 173254885Sdumbbell * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. 174254885Sdumbbell * 175254885Sdumbbell * In both cases, vertex attributes are then passed through INPUT_ROUTE. 176254885Sdumbbell * 177254885Sdumbbell * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data 178254885Sdumbbell * into the vertex processor's input registers. 179254885Sdumbbell * The first word routes the first input, the second word the second, etc. 180254885Sdumbbell * The corresponding input is routed into the register with the given index. 181254885Sdumbbell * The list is ended by a word with INPUT_ROUTE_END set. 182254885Sdumbbell * 183254885Sdumbbell * Always set COMPONENTS_4 in immediate mode. 184254885Sdumbbell */ 185254885Sdumbbell 186254885Sdumbbell#define R300_VAP_INPUT_ROUTE_0_0 0x2150 187254885Sdumbbell# define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0) 188254885Sdumbbell# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) 189254885Sdumbbell# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) 190254885Sdumbbell# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) 191254885Sdumbbell# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ 192254885Sdumbbell# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 193254885Sdumbbell# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ 194254885Sdumbbell# define R300_VAP_INPUT_ROUTE_END (1 << 13) 195254885Sdumbbell# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ 196254885Sdumbbell# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ 197254885Sdumbbell# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ 198254885Sdumbbell# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ 199254885Sdumbbell#define R300_VAP_INPUT_ROUTE_0_1 0x2154 200254885Sdumbbell#define R300_VAP_INPUT_ROUTE_0_2 0x2158 201254885Sdumbbell#define R300_VAP_INPUT_ROUTE_0_3 0x215C 202254885Sdumbbell#define R300_VAP_INPUT_ROUTE_0_4 0x2160 203254885Sdumbbell#define R300_VAP_INPUT_ROUTE_0_5 0x2164 204254885Sdumbbell#define R300_VAP_INPUT_ROUTE_0_6 0x2168 205254885Sdumbbell#define R300_VAP_INPUT_ROUTE_0_7 0x216C 206254885Sdumbbell 207254885Sdumbbell/* gap */ 208254885Sdumbbell 209254885Sdumbbell/* Notes: 210254885Sdumbbell * - always set up to produce at least two attributes: 211254885Sdumbbell * if vertex program uses only position, fglrx will set normal, too 212254885Sdumbbell * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. 213254885Sdumbbell */ 214254885Sdumbbell#define R300_VAP_INPUT_CNTL_0 0x2180 215254885Sdumbbell# define R300_INPUT_CNTL_0_COLOR 0x00000001 216254885Sdumbbell#define R300_VAP_INPUT_CNTL_1 0x2184 217254885Sdumbbell# define R300_INPUT_CNTL_POS 0x00000001 218254885Sdumbbell# define R300_INPUT_CNTL_NORMAL 0x00000002 219254885Sdumbbell# define R300_INPUT_CNTL_COLOR 0x00000004 220254885Sdumbbell# define R300_INPUT_CNTL_TC0 0x00000400 221254885Sdumbbell# define R300_INPUT_CNTL_TC1 0x00000800 222254885Sdumbbell# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ 223254885Sdumbbell# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ 224254885Sdumbbell# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ 225254885Sdumbbell# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ 226254885Sdumbbell# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ 227254885Sdumbbell# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ 228254885Sdumbbell 229254885Sdumbbell/* gap */ 230254885Sdumbbell 231254885Sdumbbell/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 232254885Sdumbbell * are set to a swizzling bit pattern, other words are 0. 233254885Sdumbbell * 234254885Sdumbbell * In immediate mode, the pattern is always set to xyzw. In vertex array 235254885Sdumbbell * mode, the swizzling pattern is e.g. used to set zw components in texture 236254885Sdumbbell * coordinates with only tweo components. 237254885Sdumbbell */ 238254885Sdumbbell#define R300_VAP_INPUT_ROUTE_1_0 0x21E0 239254885Sdumbbell# define R300_INPUT_ROUTE_SELECT_X 0 240254885Sdumbbell# define R300_INPUT_ROUTE_SELECT_Y 1 241254885Sdumbbell# define R300_INPUT_ROUTE_SELECT_Z 2 242254885Sdumbbell# define R300_INPUT_ROUTE_SELECT_W 3 243254885Sdumbbell# define R300_INPUT_ROUTE_SELECT_ZERO 4 244254885Sdumbbell# define R300_INPUT_ROUTE_SELECT_ONE 5 245254885Sdumbbell# define R300_INPUT_ROUTE_SELECT_MASK 7 246254885Sdumbbell# define R300_INPUT_ROUTE_X_SHIFT 0 247254885Sdumbbell# define R300_INPUT_ROUTE_Y_SHIFT 3 248254885Sdumbbell# define R300_INPUT_ROUTE_Z_SHIFT 6 249254885Sdumbbell# define R300_INPUT_ROUTE_W_SHIFT 9 250254885Sdumbbell# define R300_INPUT_ROUTE_ENABLE (15 << 12) 251254885Sdumbbell#define R300_VAP_INPUT_ROUTE_1_1 0x21E4 252254885Sdumbbell#define R300_VAP_INPUT_ROUTE_1_2 0x21E8 253254885Sdumbbell#define R300_VAP_INPUT_ROUTE_1_3 0x21EC 254254885Sdumbbell#define R300_VAP_INPUT_ROUTE_1_4 0x21F0 255254885Sdumbbell#define R300_VAP_INPUT_ROUTE_1_5 0x21F4 256254885Sdumbbell#define R300_VAP_INPUT_ROUTE_1_6 0x21F8 257254885Sdumbbell#define R300_VAP_INPUT_ROUTE_1_7 0x21FC 258254885Sdumbbell 259254885Sdumbbell/* END: Vertex data assembly */ 260254885Sdumbbell 261254885Sdumbbell/* gap */ 262254885Sdumbbell 263254885Sdumbbell/* BEGIN: Upload vertex program and data */ 264254885Sdumbbell 265254885Sdumbbell/* 266254885Sdumbbell * The programmable vertex shader unit has a memory bank of unknown size 267254885Sdumbbell * that can be written to in 16 byte units by writing the address into 268254885Sdumbbell * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). 269254885Sdumbbell * 270254885Sdumbbell * Pointers into the memory bank are always in multiples of 16 bytes. 271254885Sdumbbell * 272254885Sdumbbell * The memory bank is divided into areas with fixed meaning. 273254885Sdumbbell * 274254885Sdumbbell * Starting at address UPLOAD_PROGRAM: Vertex program instructions. 275254885Sdumbbell * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), 276254885Sdumbbell * whereas the difference between known addresses suggests size 512. 277254885Sdumbbell * 278254885Sdumbbell * Starting at address UPLOAD_PARAMETERS: Vertex program parameters. 279254885Sdumbbell * Native reported limits and the VPI layout suggest size 256, whereas 280254885Sdumbbell * difference between known addresses suggests size 512. 281254885Sdumbbell * 282254885Sdumbbell * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the 283254885Sdumbbell * floating point pointsize. The exact purpose of this state is uncertain, 284254885Sdumbbell * as there is also the R300_RE_POINTSIZE register. 285254885Sdumbbell * 286254885Sdumbbell * Multiple vertex programs and parameter sets can be loaded at once, 287254885Sdumbbell * which could explain the size discrepancy. 288254885Sdumbbell */ 289254885Sdumbbell#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 290254885Sdumbbell# define R300_PVS_UPLOAD_PROGRAM 0x00000000 291254885Sdumbbell# define R300_PVS_UPLOAD_PARAMETERS 0x00000200 292254885Sdumbbell# define R300_PVS_UPLOAD_POINTSIZE 0x00000406 293254885Sdumbbell 294254885Sdumbbell/* gap */ 295254885Sdumbbell 296254885Sdumbbell#define R300_VAP_PVS_UPLOAD_DATA 0x2208 297254885Sdumbbell 298254885Sdumbbell/* END: Upload vertex program and data */ 299254885Sdumbbell 300254885Sdumbbell/* gap */ 301254885Sdumbbell 302254885Sdumbbell/* I do not know the purpose of this register. However, I do know that 303254885Sdumbbell * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL 304254885Sdumbbell * for normal rendering. 305254885Sdumbbell */ 306254885Sdumbbell#define R300_VAP_UNKNOWN_221C 0x221C 307254885Sdumbbell# define R300_221C_NORMAL 0x00000000 308254885Sdumbbell# define R300_221C_CLEAR 0x0001C000 309254885Sdumbbell 310254885Sdumbbell/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first 311254885Sdumbbell * plane is per-pixel and the second plane is per-vertex. 312254885Sdumbbell * 313254885Sdumbbell * This was determined by experimentation alone but I believe it is correct. 314254885Sdumbbell * 315254885Sdumbbell * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. 316254885Sdumbbell */ 317254885Sdumbbell#define R300_VAP_CLIP_X_0 0x2220 318254885Sdumbbell#define R300_VAP_CLIP_X_1 0x2224 319254885Sdumbbell#define R300_VAP_CLIP_Y_0 0x2228 320254885Sdumbbell#define R300_VAP_CLIP_Y_1 0x2230 321254885Sdumbbell 322254885Sdumbbell/* gap */ 323254885Sdumbbell 324254885Sdumbbell/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between 325254885Sdumbbell * rendering commands and overwriting vertex program parameters. 326254885Sdumbbell * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and 327254885Sdumbbell * avoids bugs caused by still running shaders reading bad data from memory. 328254885Sdumbbell */ 329254885Sdumbbell#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 330254885Sdumbbell 331254885Sdumbbell/* Absolutely no clue what this register is about. */ 332254885Sdumbbell#define R300_VAP_UNKNOWN_2288 0x2288 333254885Sdumbbell# define R300_2288_R300 0x00750000 /* -- nh */ 334254885Sdumbbell# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ 335254885Sdumbbell 336254885Sdumbbell/* gap */ 337254885Sdumbbell 338254885Sdumbbell/* Addresses are relative to the vertex program instruction area of the 339254885Sdumbbell * memory bank. PROGRAM_END points to the last instruction of the active 340254885Sdumbbell * program 341254885Sdumbbell * 342254885Sdumbbell * The meaning of the two UNKNOWN fields is obviously not known. However, 343254885Sdumbbell * experiments so far have shown that both *must* point to an instruction 344254885Sdumbbell * inside the vertex program, otherwise the GPU locks up. 345254885Sdumbbell * 346254885Sdumbbell * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and 347254885Sdumbbell * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to 348254885Sdumbbell * position takes place. 349254885Sdumbbell * 350254885Sdumbbell * Most likely this is used to ignore rest of the program in cases 351254885Sdumbbell * where group of verts arent visible. For some reason this "section" 352254885Sdumbbell * is sometimes accepted other instruction that have no relationship with 353254885Sdumbbell * position calculations. 354254885Sdumbbell */ 355254885Sdumbbell#define R300_VAP_PVS_CNTL_1 0x22D0 356254885Sdumbbell# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 357254885Sdumbbell# define R300_PVS_CNTL_1_POS_END_SHIFT 10 358254885Sdumbbell# define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 359300050Seadler/* Addresses are relative the vertex program parameters area. */ 360254885Sdumbbell#define R300_VAP_PVS_CNTL_2 0x22D4 361254885Sdumbbell# define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 362254885Sdumbbell# define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 363254885Sdumbbell#define R300_VAP_PVS_CNTL_3 0x22D8 364254885Sdumbbell# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10 365254885Sdumbbell# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0 366254885Sdumbbell 367254885Sdumbbell/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for 368254885Sdumbbell * immediate vertices 369254885Sdumbbell */ 370254885Sdumbbell#define R300_VAP_VTX_COLOR_R 0x2464 371254885Sdumbbell#define R300_VAP_VTX_COLOR_G 0x2468 372254885Sdumbbell#define R300_VAP_VTX_COLOR_B 0x246C 373254885Sdumbbell#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ 374254885Sdumbbell#define R300_VAP_VTX_POS_0_Y_1 0x2494 375254885Sdumbbell#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ 376254885Sdumbbell#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ 377254885Sdumbbell#define R300_VAP_VTX_POS_0_Y_2 0x24A4 378254885Sdumbbell#define R300_VAP_VTX_POS_0_Z_2 0x24A8 379254885Sdumbbell/* write 0 to indicate end of packet? */ 380254885Sdumbbell#define R300_VAP_VTX_END_OF_PKT 0x24AC 381254885Sdumbbell 382254885Sdumbbell/* gap */ 383254885Sdumbbell 384254885Sdumbbell/* These are values from r300_reg/r300_reg.h - they are known to be correct 385254885Sdumbbell * and are here so we can use one register file instead of several 386254885Sdumbbell * - Vladimir 387254885Sdumbbell */ 388254885Sdumbbell#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 389254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) 390254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) 391254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) 392254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) 393254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) 394254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) 395254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) 396254885Sdumbbell 397254885Sdumbbell#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 398254885Sdumbbell /* each of the following is 3 bits wide, specifies number 399254885Sdumbbell of components */ 400254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 401254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 402254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 403254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 404254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 405254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 406254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 407254885Sdumbbell# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 408254885Sdumbbell 409254885Sdumbbell/* UNK30 seems to enables point to quad transformation on textures 410254885Sdumbbell * (or something closely related to that). 411254885Sdumbbell * This bit is rather fatal at the time being due to lackings at pixel 412254885Sdumbbell * shader side 413254885Sdumbbell */ 414254885Sdumbbell#define R300_GB_ENABLE 0x4008 415254885Sdumbbell# define R300_GB_POINT_STUFF_ENABLE (1<<0) 416254885Sdumbbell# define R300_GB_LINE_STUFF_ENABLE (1<<1) 417254885Sdumbbell# define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2) 418254885Sdumbbell# define R300_GB_STENCIL_AUTO_ENABLE (1<<4) 419254885Sdumbbell# define R300_GB_UNK31 (1<<31) 420254885Sdumbbell /* each of the following is 2 bits wide */ 421254885Sdumbbell#define R300_GB_TEX_REPLICATE 0 422254885Sdumbbell#define R300_GB_TEX_ST 1 423254885Sdumbbell#define R300_GB_TEX_STR 2 424254885Sdumbbell# define R300_GB_TEX0_SOURCE_SHIFT 16 425254885Sdumbbell# define R300_GB_TEX1_SOURCE_SHIFT 18 426254885Sdumbbell# define R300_GB_TEX2_SOURCE_SHIFT 20 427254885Sdumbbell# define R300_GB_TEX3_SOURCE_SHIFT 22 428254885Sdumbbell# define R300_GB_TEX4_SOURCE_SHIFT 24 429254885Sdumbbell# define R300_GB_TEX5_SOURCE_SHIFT 26 430254885Sdumbbell# define R300_GB_TEX6_SOURCE_SHIFT 28 431254885Sdumbbell# define R300_GB_TEX7_SOURCE_SHIFT 30 432254885Sdumbbell 433254885Sdumbbell/* MSPOS - positions for multisample antialiasing (?) */ 434254885Sdumbbell#define R300_GB_MSPOS0 0x4010 435254885Sdumbbell /* shifts - each of the fields is 4 bits */ 436254885Sdumbbell# define R300_GB_MSPOS0__MS_X0_SHIFT 0 437254885Sdumbbell# define R300_GB_MSPOS0__MS_Y0_SHIFT 4 438254885Sdumbbell# define R300_GB_MSPOS0__MS_X1_SHIFT 8 439254885Sdumbbell# define R300_GB_MSPOS0__MS_Y1_SHIFT 12 440254885Sdumbbell# define R300_GB_MSPOS0__MS_X2_SHIFT 16 441254885Sdumbbell# define R300_GB_MSPOS0__MS_Y2_SHIFT 20 442254885Sdumbbell# define R300_GB_MSPOS0__MSBD0_Y 24 443254885Sdumbbell# define R300_GB_MSPOS0__MSBD0_X 28 444254885Sdumbbell 445254885Sdumbbell#define R300_GB_MSPOS1 0x4014 446254885Sdumbbell# define R300_GB_MSPOS1__MS_X3_SHIFT 0 447254885Sdumbbell# define R300_GB_MSPOS1__MS_Y3_SHIFT 4 448254885Sdumbbell# define R300_GB_MSPOS1__MS_X4_SHIFT 8 449254885Sdumbbell# define R300_GB_MSPOS1__MS_Y4_SHIFT 12 450254885Sdumbbell# define R300_GB_MSPOS1__MS_X5_SHIFT 16 451254885Sdumbbell# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 452254885Sdumbbell# define R300_GB_MSPOS1__MSBD1 24 453254885Sdumbbell 454254885Sdumbbell 455254885Sdumbbell#define R300_GB_TILE_CONFIG 0x4018 456254885Sdumbbell# define R300_GB_TILE_ENABLE (1<<0) 457254885Sdumbbell# define R300_GB_TILE_PIPE_COUNT_RV300 0 458254885Sdumbbell# define R300_GB_TILE_PIPE_COUNT_R300 (3<<1) 459254885Sdumbbell# define R300_GB_TILE_PIPE_COUNT_R420 (7<<1) 460254885Sdumbbell# define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1) 461254885Sdumbbell# define R300_GB_TILE_SIZE_8 0 462254885Sdumbbell# define R300_GB_TILE_SIZE_16 (1<<4) 463254885Sdumbbell# define R300_GB_TILE_SIZE_32 (2<<4) 464254885Sdumbbell# define R300_GB_SUPER_SIZE_1 (0<<6) 465254885Sdumbbell# define R300_GB_SUPER_SIZE_2 (1<<6) 466254885Sdumbbell# define R300_GB_SUPER_SIZE_4 (2<<6) 467254885Sdumbbell# define R300_GB_SUPER_SIZE_8 (3<<6) 468254885Sdumbbell# define R300_GB_SUPER_SIZE_16 (4<<6) 469254885Sdumbbell# define R300_GB_SUPER_SIZE_32 (5<<6) 470254885Sdumbbell# define R300_GB_SUPER_SIZE_64 (6<<6) 471254885Sdumbbell# define R300_GB_SUPER_SIZE_128 (7<<6) 472254885Sdumbbell# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ 473254885Sdumbbell# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ 474254885Sdumbbell# define R300_GB_SUPER_TILE_A 0 475254885Sdumbbell# define R300_GB_SUPER_TILE_B (1<<15) 476254885Sdumbbell# define R300_GB_SUBPIXEL_1_12 0 477254885Sdumbbell# define R300_GB_SUBPIXEL_1_16 (1<<16) 478254885Sdumbbell 479254885Sdumbbell#define R300_GB_FIFO_SIZE 0x4024 480254885Sdumbbell /* each of the following is 2 bits wide */ 481254885Sdumbbell#define R300_GB_FIFO_SIZE_32 0 482254885Sdumbbell#define R300_GB_FIFO_SIZE_64 1 483254885Sdumbbell#define R300_GB_FIFO_SIZE_128 2 484254885Sdumbbell#define R300_GB_FIFO_SIZE_256 3 485254885Sdumbbell# define R300_SC_IFIFO_SIZE_SHIFT 0 486254885Sdumbbell# define R300_SC_TZFIFO_SIZE_SHIFT 2 487254885Sdumbbell# define R300_SC_BFIFO_SIZE_SHIFT 4 488254885Sdumbbell 489254885Sdumbbell# define R300_US_OFIFO_SIZE_SHIFT 12 490254885Sdumbbell# define R300_US_WFIFO_SIZE_SHIFT 14 491254885Sdumbbell /* the following use the same constants as above, but meaning is 492254885Sdumbbell is times 2 (i.e. instead of 32 words it means 64 */ 493254885Sdumbbell# define R300_RS_TFIFO_SIZE_SHIFT 6 494254885Sdumbbell# define R300_RS_CFIFO_SIZE_SHIFT 8 495254885Sdumbbell# define R300_US_RAM_SIZE_SHIFT 10 496254885Sdumbbell /* watermarks, 3 bits wide */ 497254885Sdumbbell# define R300_RS_HIGHWATER_COL_SHIFT 16 498254885Sdumbbell# define R300_RS_HIGHWATER_TEX_SHIFT 19 499254885Sdumbbell# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ 500254885Sdumbbell# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 501254885Sdumbbell 502254885Sdumbbell#define R300_GB_SELECT 0x401C 503254885Sdumbbell# define R300_GB_FOG_SELECT_C0A 0 504254885Sdumbbell# define R300_GB_FOG_SELECT_C1A 1 505254885Sdumbbell# define R300_GB_FOG_SELECT_C2A 2 506254885Sdumbbell# define R300_GB_FOG_SELECT_C3A 3 507254885Sdumbbell# define R300_GB_FOG_SELECT_1_1_W 4 508254885Sdumbbell# define R300_GB_FOG_SELECT_Z 5 509254885Sdumbbell# define R300_GB_DEPTH_SELECT_Z 0 510254885Sdumbbell# define R300_GB_DEPTH_SELECT_1_1_W (1<<3) 511254885Sdumbbell# define R300_GB_W_SELECT_1_W 0 512254885Sdumbbell# define R300_GB_W_SELECT_1 (1<<4) 513254885Sdumbbell 514254885Sdumbbell#define R300_GB_AA_CONFIG 0x4020 515254885Sdumbbell# define R300_AA_DISABLE 0x00 516254885Sdumbbell# define R300_AA_ENABLE 0x01 517254885Sdumbbell# define R300_AA_SUBSAMPLES_2 0 518254885Sdumbbell# define R300_AA_SUBSAMPLES_3 (1<<1) 519254885Sdumbbell# define R300_AA_SUBSAMPLES_4 (2<<1) 520254885Sdumbbell# define R300_AA_SUBSAMPLES_6 (3<<1) 521254885Sdumbbell 522254885Sdumbbell/* gap */ 523254885Sdumbbell 524254885Sdumbbell/* Zero to flush caches. */ 525254885Sdumbbell#define R300_TX_INVALTAGS 0x4100 526254885Sdumbbell#define R300_TX_FLUSH 0x0 527254885Sdumbbell 528254885Sdumbbell/* The upper enable bits are guessed, based on fglrx reported limits. */ 529254885Sdumbbell#define R300_TX_ENABLE 0x4104 530254885Sdumbbell# define R300_TX_ENABLE_0 (1 << 0) 531254885Sdumbbell# define R300_TX_ENABLE_1 (1 << 1) 532254885Sdumbbell# define R300_TX_ENABLE_2 (1 << 2) 533254885Sdumbbell# define R300_TX_ENABLE_3 (1 << 3) 534254885Sdumbbell# define R300_TX_ENABLE_4 (1 << 4) 535254885Sdumbbell# define R300_TX_ENABLE_5 (1 << 5) 536254885Sdumbbell# define R300_TX_ENABLE_6 (1 << 6) 537254885Sdumbbell# define R300_TX_ENABLE_7 (1 << 7) 538254885Sdumbbell# define R300_TX_ENABLE_8 (1 << 8) 539254885Sdumbbell# define R300_TX_ENABLE_9 (1 << 9) 540254885Sdumbbell# define R300_TX_ENABLE_10 (1 << 10) 541254885Sdumbbell# define R300_TX_ENABLE_11 (1 << 11) 542254885Sdumbbell# define R300_TX_ENABLE_12 (1 << 12) 543254885Sdumbbell# define R300_TX_ENABLE_13 (1 << 13) 544254885Sdumbbell# define R300_TX_ENABLE_14 (1 << 14) 545254885Sdumbbell# define R300_TX_ENABLE_15 (1 << 15) 546254885Sdumbbell 547254885Sdumbbell/* The pointsize is given in multiples of 6. The pointsize can be 548254885Sdumbbell * enormous: Clear() renders a single point that fills the entire 549254885Sdumbbell * framebuffer. 550254885Sdumbbell */ 551254885Sdumbbell#define R300_RE_POINTSIZE 0x421C 552254885Sdumbbell# define R300_POINTSIZE_Y_SHIFT 0 553254885Sdumbbell# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ 554254885Sdumbbell# define R300_POINTSIZE_X_SHIFT 16 555254885Sdumbbell# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ 556254885Sdumbbell# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) 557254885Sdumbbell 558254885Sdumbbell/* The line width is given in multiples of 6. 559254885Sdumbbell * In default mode lines are classified as vertical lines. 560254885Sdumbbell * HO: horizontal 561254885Sdumbbell * VE: vertical or horizontal 562254885Sdumbbell * HO & VE: no classification 563254885Sdumbbell */ 564254885Sdumbbell#define R300_RE_LINE_CNT 0x4234 565254885Sdumbbell# define R300_LINESIZE_SHIFT 0 566254885Sdumbbell# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ 567254885Sdumbbell# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) 568254885Sdumbbell# define R300_LINE_CNT_HO (1 << 16) 569254885Sdumbbell# define R300_LINE_CNT_VE (1 << 17) 570254885Sdumbbell 571254885Sdumbbell/* Some sort of scale or clamp value for texcoordless textures. */ 572254885Sdumbbell#define R300_RE_UNK4238 0x4238 573254885Sdumbbell 574254885Sdumbbell/* Something shade related */ 575254885Sdumbbell#define R300_RE_SHADE 0x4274 576254885Sdumbbell 577254885Sdumbbell#define R300_RE_SHADE_MODEL 0x4278 578254885Sdumbbell# define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa 579254885Sdumbbell# define R300_RE_SHADE_MODEL_FLAT 0x39595 580254885Sdumbbell 581254885Sdumbbell/* Dangerous */ 582254885Sdumbbell#define R300_RE_POLYGON_MODE 0x4288 583254885Sdumbbell# define R300_PM_ENABLED (1 << 0) 584254885Sdumbbell# define R300_PM_FRONT_POINT (0 << 0) 585254885Sdumbbell# define R300_PM_BACK_POINT (0 << 0) 586254885Sdumbbell# define R300_PM_FRONT_LINE (1 << 4) 587254885Sdumbbell# define R300_PM_FRONT_FILL (1 << 5) 588254885Sdumbbell# define R300_PM_BACK_LINE (1 << 7) 589254885Sdumbbell# define R300_PM_BACK_FILL (1 << 8) 590254885Sdumbbell 591254885Sdumbbell/* Fog parameters */ 592254885Sdumbbell#define R300_RE_FOG_SCALE 0x4294 593254885Sdumbbell#define R300_RE_FOG_START 0x4298 594254885Sdumbbell 595254885Sdumbbell/* Not sure why there are duplicate of factor and constant values. 596254885Sdumbbell * My best guess so far is that there are separate zbiases for test and write. 597254885Sdumbbell * Ordering might be wrong. 598254885Sdumbbell * Some of the tests indicate that fgl has a fallback implementation of zbias 599254885Sdumbbell * via pixel shaders. 600254885Sdumbbell */ 601254885Sdumbbell#define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */ 602254885Sdumbbell#define R300_RE_ZBIAS_T_FACTOR 0x42A4 603254885Sdumbbell#define R300_RE_ZBIAS_T_CONSTANT 0x42A8 604254885Sdumbbell#define R300_RE_ZBIAS_W_FACTOR 0x42AC 605254885Sdumbbell#define R300_RE_ZBIAS_W_CONSTANT 0x42B0 606254885Sdumbbell 607254885Sdumbbell/* This register needs to be set to (1<<1) for RV350 to correctly 608254885Sdumbbell * perform depth test (see --vb-triangles in r300_demo) 609254885Sdumbbell * Don't know about other chips. - Vladimir 610254885Sdumbbell * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. 611254885Sdumbbell * My guess is that there are two bits for each zbias primitive 612254885Sdumbbell * (FILL, LINE, POINT). 613254885Sdumbbell * One to enable depth test and one for depth write. 614254885Sdumbbell * Yet this doesn't explain why depth writes work ... 615254885Sdumbbell */ 616254885Sdumbbell#define R300_RE_OCCLUSION_CNTL 0x42B4 617254885Sdumbbell# define R300_OCCLUSION_ON (1<<1) 618254885Sdumbbell 619254885Sdumbbell#define R300_RE_CULL_CNTL 0x42B8 620254885Sdumbbell# define R300_CULL_FRONT (1 << 0) 621254885Sdumbbell# define R300_CULL_BACK (1 << 1) 622254885Sdumbbell# define R300_FRONT_FACE_CCW (0 << 2) 623254885Sdumbbell# define R300_FRONT_FACE_CW (1 << 2) 624254885Sdumbbell 625254885Sdumbbell 626254885Sdumbbell/* BEGIN: Rasterization / Interpolators - many guesses */ 627254885Sdumbbell 628254885Sdumbbell/* 0_UNKNOWN_18 has always been set except for clear operations. 629254885Sdumbbell * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends 630254885Sdumbbell * on the vertex program, *not* the fragment program) 631254885Sdumbbell */ 632254885Sdumbbell#define R300_RS_CNTL_0 0x4300 633254885Sdumbbell# define R300_RS_CNTL_TC_CNT_SHIFT 2 634254885Sdumbbell# define R300_RS_CNTL_TC_CNT_MASK (7 << 2) 635254885Sdumbbell /* number of color interpolators used */ 636254885Sdumbbell# define R300_RS_CNTL_CI_CNT_SHIFT 7 637254885Sdumbbell# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) 638254885Sdumbbell /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n 639254885Sdumbbell register. */ 640254885Sdumbbell#define R300_RS_CNTL_1 0x4304 641254885Sdumbbell 642254885Sdumbbell/* gap */ 643254885Sdumbbell 644254885Sdumbbell/* Only used for texture coordinates. 645254885Sdumbbell * Use the source field to route texture coordinate input from the 646254885Sdumbbell * vertex program to the desired interpolator. Note that the source 647254885Sdumbbell * field is relative to the outputs the vertex program *actually* 648254885Sdumbbell * writes. If a vertex program only writes texcoord[1], this will 649254885Sdumbbell * be source index 0. 650254885Sdumbbell * Set INTERP_USED on all interpolators that produce data used by 651254885Sdumbbell * the fragment program. INTERP_USED looks like a swizzling mask, 652254885Sdumbbell * but I haven't seen it used that way. 653254885Sdumbbell * 654254885Sdumbbell * Note: The _UNKNOWN constants are always set in their respective 655254885Sdumbbell * register. I don't know if this is necessary. 656254885Sdumbbell */ 657254885Sdumbbell#define R300_RS_INTERP_0 0x4310 658254885Sdumbbell#define R300_RS_INTERP_1 0x4314 659254885Sdumbbell# define R300_RS_INTERP_1_UNKNOWN 0x40 660254885Sdumbbell#define R300_RS_INTERP_2 0x4318 661254885Sdumbbell# define R300_RS_INTERP_2_UNKNOWN 0x80 662254885Sdumbbell#define R300_RS_INTERP_3 0x431C 663254885Sdumbbell# define R300_RS_INTERP_3_UNKNOWN 0xC0 664254885Sdumbbell#define R300_RS_INTERP_4 0x4320 665254885Sdumbbell#define R300_RS_INTERP_5 0x4324 666254885Sdumbbell#define R300_RS_INTERP_6 0x4328 667254885Sdumbbell#define R300_RS_INTERP_7 0x432C 668254885Sdumbbell# define R300_RS_INTERP_SRC_SHIFT 2 669254885Sdumbbell# define R300_RS_INTERP_SRC_MASK (7 << 2) 670254885Sdumbbell# define R300_RS_INTERP_USED 0x00D10000 671254885Sdumbbell 672254885Sdumbbell/* These DWORDs control how vertex data is routed into fragment program 673254885Sdumbbell * registers, after interpolators. 674254885Sdumbbell */ 675254885Sdumbbell#define R300_RS_ROUTE_0 0x4330 676254885Sdumbbell#define R300_RS_ROUTE_1 0x4334 677254885Sdumbbell#define R300_RS_ROUTE_2 0x4338 678254885Sdumbbell#define R300_RS_ROUTE_3 0x433C /* GUESS */ 679254885Sdumbbell#define R300_RS_ROUTE_4 0x4340 /* GUESS */ 680254885Sdumbbell#define R300_RS_ROUTE_5 0x4344 /* GUESS */ 681254885Sdumbbell#define R300_RS_ROUTE_6 0x4348 /* GUESS */ 682254885Sdumbbell#define R300_RS_ROUTE_7 0x434C /* GUESS */ 683254885Sdumbbell# define R300_RS_ROUTE_SOURCE_INTERP_0 0 684254885Sdumbbell# define R300_RS_ROUTE_SOURCE_INTERP_1 1 685254885Sdumbbell# define R300_RS_ROUTE_SOURCE_INTERP_2 2 686254885Sdumbbell# define R300_RS_ROUTE_SOURCE_INTERP_3 3 687254885Sdumbbell# define R300_RS_ROUTE_SOURCE_INTERP_4 4 688254885Sdumbbell# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ 689254885Sdumbbell# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ 690254885Sdumbbell# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ 691254885Sdumbbell# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ 692254885Sdumbbell# define R300_RS_ROUTE_DEST_SHIFT 6 693254885Sdumbbell# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ 694254885Sdumbbell 695254885Sdumbbell/* Special handling for color: When the fragment program uses color, 696254885Sdumbbell * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the 697254885Sdumbbell * color register index. 698254885Sdumbbell * 699254885Sdumbbell * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any 700254885Sdumbbell * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state. 701254885Sdumbbell * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly 702254885Sdumbbell * correct or not. - Oliver. 703254885Sdumbbell */ 704254885Sdumbbell# define R300_RS_ROUTE_0_COLOR (1 << 14) 705254885Sdumbbell# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 706254885Sdumbbell# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ 707254885Sdumbbell/* As above, but for secondary color */ 708254885Sdumbbell# define R300_RS_ROUTE_1_COLOR1 (1 << 14) 709254885Sdumbbell# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 710254885Sdumbbell# define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) 711254885Sdumbbell# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 712254885Sdumbbell/* END: Rasterization / Interpolators - many guesses */ 713254885Sdumbbell 714254885Sdumbbell/* Hierarchical Z Enable */ 715254885Sdumbbell#define R300_SC_HYPERZ 0x43a4 716254885Sdumbbell# define R300_SC_HYPERZ_DISABLE (0 << 0) 717254885Sdumbbell# define R300_SC_HYPERZ_ENABLE (1 << 0) 718254885Sdumbbell# define R300_SC_HYPERZ_MIN (0 << 1) 719254885Sdumbbell# define R300_SC_HYPERZ_MAX (1 << 1) 720254885Sdumbbell# define R300_SC_HYPERZ_ADJ_256 (0 << 2) 721254885Sdumbbell# define R300_SC_HYPERZ_ADJ_128 (1 << 2) 722254885Sdumbbell# define R300_SC_HYPERZ_ADJ_64 (2 << 2) 723254885Sdumbbell# define R300_SC_HYPERZ_ADJ_32 (3 << 2) 724254885Sdumbbell# define R300_SC_HYPERZ_ADJ_16 (4 << 2) 725254885Sdumbbell# define R300_SC_HYPERZ_ADJ_8 (5 << 2) 726254885Sdumbbell# define R300_SC_HYPERZ_ADJ_4 (6 << 2) 727254885Sdumbbell# define R300_SC_HYPERZ_ADJ_2 (7 << 2) 728254885Sdumbbell# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) 729254885Sdumbbell# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) 730254885Sdumbbell# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) 731254885Sdumbbell# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) 732254885Sdumbbell 733254885Sdumbbell#define R300_SC_EDGERULE 0x43a8 734254885Sdumbbell 735254885Sdumbbell/* BEGIN: Scissors and cliprects */ 736254885Sdumbbell 737254885Sdumbbell/* There are four clipping rectangles. Their corner coordinates are inclusive. 738254885Sdumbbell * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending 739254885Sdumbbell * on whether the pixel is inside cliprects 0-3, respectively. For example, 740254885Sdumbbell * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned 741254885Sdumbbell * the number 3 (binary 0011). 742254885Sdumbbell * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, 743254885Sdumbbell * the pixel is rasterized. 744254885Sdumbbell * 745254885Sdumbbell * In addition to this, there is a scissors rectangle. Only pixels inside the 746254885Sdumbbell * scissors rectangle are drawn. (coordinates are inclusive) 747254885Sdumbbell * 748254885Sdumbbell * For some reason, the top-left corner of the framebuffer is at (1440, 1440) 749254885Sdumbbell * for the purpose of clipping and scissors. 750254885Sdumbbell */ 751254885Sdumbbell#define R300_RE_CLIPRECT_TL_0 0x43B0 752254885Sdumbbell#define R300_RE_CLIPRECT_BR_0 0x43B4 753254885Sdumbbell#define R300_RE_CLIPRECT_TL_1 0x43B8 754254885Sdumbbell#define R300_RE_CLIPRECT_BR_1 0x43BC 755254885Sdumbbell#define R300_RE_CLIPRECT_TL_2 0x43C0 756254885Sdumbbell#define R300_RE_CLIPRECT_BR_2 0x43C4 757254885Sdumbbell#define R300_RE_CLIPRECT_TL_3 0x43C8 758254885Sdumbbell#define R300_RE_CLIPRECT_BR_3 0x43CC 759254885Sdumbbell# define R300_CLIPRECT_OFFSET 1440 760254885Sdumbbell# define R300_CLIPRECT_MASK 0x1FFF 761254885Sdumbbell# define R300_CLIPRECT_X_SHIFT 0 762254885Sdumbbell# define R300_CLIPRECT_X_MASK (0x1FFF << 0) 763254885Sdumbbell# define R300_CLIPRECT_Y_SHIFT 13 764254885Sdumbbell# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) 765254885Sdumbbell#define R300_RE_CLIPRECT_CNTL 0x43D0 766254885Sdumbbell# define R300_CLIP_OUT (1 << 0) 767254885Sdumbbell# define R300_CLIP_0 (1 << 1) 768254885Sdumbbell# define R300_CLIP_1 (1 << 2) 769254885Sdumbbell# define R300_CLIP_10 (1 << 3) 770254885Sdumbbell# define R300_CLIP_2 (1 << 4) 771254885Sdumbbell# define R300_CLIP_20 (1 << 5) 772254885Sdumbbell# define R300_CLIP_21 (1 << 6) 773254885Sdumbbell# define R300_CLIP_210 (1 << 7) 774254885Sdumbbell# define R300_CLIP_3 (1 << 8) 775254885Sdumbbell# define R300_CLIP_30 (1 << 9) 776254885Sdumbbell# define R300_CLIP_31 (1 << 10) 777254885Sdumbbell# define R300_CLIP_310 (1 << 11) 778254885Sdumbbell# define R300_CLIP_32 (1 << 12) 779254885Sdumbbell# define R300_CLIP_320 (1 << 13) 780254885Sdumbbell# define R300_CLIP_321 (1 << 14) 781254885Sdumbbell# define R300_CLIP_3210 (1 << 15) 782254885Sdumbbell 783254885Sdumbbell/* gap */ 784254885Sdumbbell 785254885Sdumbbell#define R300_RE_SCISSORS_TL 0x43E0 786254885Sdumbbell#define R300_RE_SCISSORS_BR 0x43E4 787254885Sdumbbell# define R300_SCISSORS_OFFSET 1440 788254885Sdumbbell# define R300_SCISSORS_X_SHIFT 0 789254885Sdumbbell# define R300_SCISSORS_X_MASK (0x1FFF << 0) 790254885Sdumbbell# define R300_SCISSORS_Y_SHIFT 13 791254885Sdumbbell# define R300_SCISSORS_Y_MASK (0x1FFF << 13) 792254885Sdumbbell/* END: Scissors and cliprects */ 793254885Sdumbbell 794254885Sdumbbell/* BEGIN: Texture specification */ 795254885Sdumbbell 796254885Sdumbbell/* 797254885Sdumbbell * The texture specification dwords are grouped by meaning and not by texture 798254885Sdumbbell * unit. This means that e.g. the offset for texture image unit N is found in 799254885Sdumbbell * register TX_OFFSET_0 + (4*N) 800254885Sdumbbell */ 801254885Sdumbbell#define R300_TX_FILTER_0 0x4400 802254885Sdumbbell# define R300_TX_REPEAT 0 803254885Sdumbbell# define R300_TX_MIRRORED 1 804254885Sdumbbell# define R300_TX_CLAMP 4 805254885Sdumbbell# define R300_TX_CLAMP_TO_EDGE 2 806254885Sdumbbell# define R300_TX_CLAMP_TO_BORDER 6 807254885Sdumbbell# define R300_TX_WRAP_S_SHIFT 0 808254885Sdumbbell# define R300_TX_WRAP_S_MASK (7 << 0) 809254885Sdumbbell# define R300_TX_WRAP_T_SHIFT 3 810254885Sdumbbell# define R300_TX_WRAP_T_MASK (7 << 3) 811254885Sdumbbell# define R300_TX_WRAP_Q_SHIFT 6 812254885Sdumbbell# define R300_TX_WRAP_Q_MASK (7 << 6) 813254885Sdumbbell# define R300_TX_MAG_FILTER_NEAREST (1 << 9) 814254885Sdumbbell# define R300_TX_MAG_FILTER_LINEAR (2 << 9) 815254885Sdumbbell# define R300_TX_MAG_FILTER_MASK (3 << 9) 816254885Sdumbbell# define R300_TX_MIN_FILTER_NEAREST (1 << 11) 817254885Sdumbbell# define R300_TX_MIN_FILTER_LINEAR (2 << 11) 818254885Sdumbbell# define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11) 819254885Sdumbbell# define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11) 820254885Sdumbbell# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) 821254885Sdumbbell# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) 822254885Sdumbbell 823254885Sdumbbell/* NOTE: NEAREST doesn't seem to exist. 824254885Sdumbbell * Im not seting MAG_FILTER_MASK and (3 << 11) on for all 825254885Sdumbbell * anisotropy modes because that would void selected mag filter 826254885Sdumbbell */ 827254885Sdumbbell# define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13) 828254885Sdumbbell# define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13) 829254885Sdumbbell# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13) 830254885Sdumbbell# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13) 831254885Sdumbbell# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) 832254885Sdumbbell# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) 833254885Sdumbbell# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) 834254885Sdumbbell# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) 835254885Sdumbbell# define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) 836254885Sdumbbell# define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) 837254885Sdumbbell# define R300_TX_MAX_ANISO_MASK (14 << 21) 838254885Sdumbbell 839254885Sdumbbell#define R300_TX_FILTER1_0 0x4440 840254885Sdumbbell# define R300_CHROMA_KEY_MODE_DISABLE 0 841254885Sdumbbell# define R300_CHROMA_KEY_FORCE 1 842254885Sdumbbell# define R300_CHROMA_KEY_BLEND 2 843254885Sdumbbell# define R300_MC_ROUND_NORMAL (0<<2) 844254885Sdumbbell# define R300_MC_ROUND_MPEG4 (1<<2) 845254885Sdumbbell# define R300_LOD_BIAS_MASK 0x1fff 846254885Sdumbbell# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) 847254885Sdumbbell# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) 848254885Sdumbbell# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) 849254885Sdumbbell# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) 850254885Sdumbbell# define R300_TX_TRI_PERF_0_8 (0<<15) 851254885Sdumbbell# define R300_TX_TRI_PERF_1_8 (1<<15) 852254885Sdumbbell# define R300_TX_TRI_PERF_1_4 (2<<15) 853254885Sdumbbell# define R300_TX_TRI_PERF_3_8 (3<<15) 854254885Sdumbbell# define R300_ANISO_THRESHOLD_MASK (7<<17) 855254885Sdumbbell 856254885Sdumbbell#define R300_TX_SIZE_0 0x4480 857254885Sdumbbell# define R300_TX_WIDTHMASK_SHIFT 0 858254885Sdumbbell# define R300_TX_WIDTHMASK_MASK (2047 << 0) 859254885Sdumbbell# define R300_TX_HEIGHTMASK_SHIFT 11 860254885Sdumbbell# define R300_TX_HEIGHTMASK_MASK (2047 << 11) 861254885Sdumbbell# define R300_TX_UNK23 (1 << 23) 862254885Sdumbbell# define R300_TX_MAX_MIP_LEVEL_SHIFT 26 863254885Sdumbbell# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26) 864254885Sdumbbell# define R300_TX_SIZE_PROJECTED (1<<30) 865254885Sdumbbell# define R300_TX_SIZE_TXPITCH_EN (1<<31) 866254885Sdumbbell#define R300_TX_FORMAT_0 0x44C0 867254885Sdumbbell /* The interpretation of the format word by Wladimir van der Laan */ 868254885Sdumbbell /* The X, Y, Z and W refer to the layout of the components. 869254885Sdumbbell They are given meanings as R, G, B and Alpha by the swizzle 870254885Sdumbbell specification */ 871254885Sdumbbell# define R300_TX_FORMAT_X8 0x0 872254885Sdumbbell# define R300_TX_FORMAT_X16 0x1 873254885Sdumbbell# define R300_TX_FORMAT_Y4X4 0x2 874254885Sdumbbell# define R300_TX_FORMAT_Y8X8 0x3 875254885Sdumbbell# define R300_TX_FORMAT_Y16X16 0x4 876254885Sdumbbell# define R300_TX_FORMAT_Z3Y3X2 0x5 877254885Sdumbbell# define R300_TX_FORMAT_Z5Y6X5 0x6 878254885Sdumbbell# define R300_TX_FORMAT_Z6Y5X5 0x7 879254885Sdumbbell# define R300_TX_FORMAT_Z11Y11X10 0x8 880254885Sdumbbell# define R300_TX_FORMAT_Z10Y11X11 0x9 881254885Sdumbbell# define R300_TX_FORMAT_W4Z4Y4X4 0xA 882254885Sdumbbell# define R300_TX_FORMAT_W1Z5Y5X5 0xB 883254885Sdumbbell# define R300_TX_FORMAT_W8Z8Y8X8 0xC 884254885Sdumbbell# define R300_TX_FORMAT_W2Z10Y10X10 0xD 885254885Sdumbbell# define R300_TX_FORMAT_W16Z16Y16X16 0xE 886254885Sdumbbell# define R300_TX_FORMAT_DXT1 0xF 887254885Sdumbbell# define R300_TX_FORMAT_DXT3 0x10 888254885Sdumbbell# define R300_TX_FORMAT_DXT5 0x11 889254885Sdumbbell# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ 890254885Sdumbbell# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ 891254885Sdumbbell# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ 892254885Sdumbbell# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ 893254885Sdumbbell /* 0x16 - some 16 bit green format.. ?? */ 894254885Sdumbbell# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ 895254885Sdumbbell# define R300_TX_FORMAT_CUBIC_MAP (1 << 26) 896254885Sdumbbell 897254885Sdumbbell /* gap */ 898254885Sdumbbell /* Floating point formats */ 899254885Sdumbbell /* Note - hardware supports both 16 and 32 bit floating point */ 900254885Sdumbbell# define R300_TX_FORMAT_FL_I16 0x18 901254885Sdumbbell# define R300_TX_FORMAT_FL_I16A16 0x19 902254885Sdumbbell# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A 903254885Sdumbbell# define R300_TX_FORMAT_FL_I32 0x1B 904254885Sdumbbell# define R300_TX_FORMAT_FL_I32A32 0x1C 905254885Sdumbbell# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D 906254885Sdumbbell# define R300_TX_FORMAT_ATI2N 0x1F 907254885Sdumbbell /* alpha modes, convenience mostly */ 908254885Sdumbbell /* if you have alpha, pick constant appropriate to the 909254885Sdumbbell number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ 910254885Sdumbbell# define R300_TX_FORMAT_ALPHA_1CH 0x000 911254885Sdumbbell# define R300_TX_FORMAT_ALPHA_2CH 0x200 912254885Sdumbbell# define R300_TX_FORMAT_ALPHA_4CH 0x600 913254885Sdumbbell# define R300_TX_FORMAT_ALPHA_NONE 0xA00 914254885Sdumbbell /* Swizzling */ 915254885Sdumbbell /* constants */ 916254885Sdumbbell# define R300_TX_FORMAT_X 0 917254885Sdumbbell# define R300_TX_FORMAT_Y 1 918254885Sdumbbell# define R300_TX_FORMAT_Z 2 919254885Sdumbbell# define R300_TX_FORMAT_W 3 920254885Sdumbbell# define R300_TX_FORMAT_ZERO 4 921254885Sdumbbell# define R300_TX_FORMAT_ONE 5 922254885Sdumbbell /* 2.0*Z, everything above 1.0 is set to 0.0 */ 923254885Sdumbbell# define R300_TX_FORMAT_CUT_Z 6 924254885Sdumbbell /* 2.0*W, everything above 1.0 is set to 0.0 */ 925254885Sdumbbell# define R300_TX_FORMAT_CUT_W 7 926254885Sdumbbell 927254885Sdumbbell# define R300_TX_FORMAT_B_SHIFT 18 928254885Sdumbbell# define R300_TX_FORMAT_G_SHIFT 15 929254885Sdumbbell# define R300_TX_FORMAT_R_SHIFT 12 930254885Sdumbbell# define R300_TX_FORMAT_A_SHIFT 9 931254885Sdumbbell /* Convenience macro to take care of layout and swizzling */ 932254885Sdumbbell# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ 933254885Sdumbbell ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ 934254885Sdumbbell | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ 935254885Sdumbbell | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ 936254885Sdumbbell | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ 937254885Sdumbbell | (R300_TX_FORMAT_##FMT) \ 938254885Sdumbbell ) 939254885Sdumbbell /* These can be ORed with result of R300_EASY_TX_FORMAT() 940254885Sdumbbell We don't really know what they do. Take values from a 941254885Sdumbbell constant color ? */ 942254885Sdumbbell# define R300_TX_FORMAT_CONST_X (1<<5) 943254885Sdumbbell# define R300_TX_FORMAT_CONST_Y (2<<5) 944254885Sdumbbell# define R300_TX_FORMAT_CONST_Z (4<<5) 945254885Sdumbbell# define R300_TX_FORMAT_CONST_W (8<<5) 946254885Sdumbbell 947254885Sdumbbell# define R300_TX_FORMAT_YUV_MODE 0x00800000 948254885Sdumbbell 949254885Sdumbbell#define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */ 950254885Sdumbbell#define R300_TX_OFFSET_0 0x4540 951254885Sdumbbell /* BEGIN: Guess from R200 */ 952254885Sdumbbell# define R300_TXO_ENDIAN_NO_SWAP (0 << 0) 953254885Sdumbbell# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) 954254885Sdumbbell# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) 955254885Sdumbbell# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 956254885Sdumbbell# define R300_TXO_MACRO_TILE (1 << 2) 957254885Sdumbbell# define R300_TXO_MICRO_TILE (1 << 3) 958254885Sdumbbell# define R300_TXO_MICRO_TILE_SQUARE (2 << 3) 959254885Sdumbbell# define R300_TXO_OFFSET_MASK 0xffffffe0 960254885Sdumbbell# define R300_TXO_OFFSET_SHIFT 5 961254885Sdumbbell /* END: Guess from R200 */ 962254885Sdumbbell 963254885Sdumbbell/* 32 bit chroma key */ 964254885Sdumbbell#define R300_TX_CHROMA_KEY_0 0x4580 965254885Sdumbbell/* ff00ff00 == { 0, 1.0, 0, 1.0 } */ 966254885Sdumbbell#define R300_TX_BORDER_COLOR_0 0x45C0 967254885Sdumbbell 968254885Sdumbbell/* END: Texture specification */ 969254885Sdumbbell 970254885Sdumbbell/* BEGIN: Fragment program instruction set */ 971254885Sdumbbell 972254885Sdumbbell/* Fragment programs are written directly into register space. 973254885Sdumbbell * There are separate instruction streams for texture instructions and ALU 974254885Sdumbbell * instructions. 975254885Sdumbbell * In order to synchronize these streams, the program is divided into up 976254885Sdumbbell * to 4 nodes. Each node begins with a number of TEX operations, followed 977254885Sdumbbell * by a number of ALU operations. 978254885Sdumbbell * The first node can have zero TEX ops, all subsequent nodes must have at 979254885Sdumbbell * least 980254885Sdumbbell * one TEX ops. 981254885Sdumbbell * All nodes must have at least one ALU op. 982254885Sdumbbell * 983254885Sdumbbell * The index of the last node is stored in PFS_CNTL_0: A value of 0 means 984254885Sdumbbell * 1 node, a value of 3 means 4 nodes. 985254885Sdumbbell * The total amount of instructions is defined in PFS_CNTL_2. The offsets are 986254885Sdumbbell * offsets into the respective instruction streams, while *_END points to the 987254885Sdumbbell * last instruction relative to this offset. 988254885Sdumbbell */ 989254885Sdumbbell#define R300_PFS_CNTL_0 0x4600 990254885Sdumbbell# define R300_PFS_CNTL_LAST_NODES_SHIFT 0 991254885Sdumbbell# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) 992254885Sdumbbell# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) 993254885Sdumbbell#define R300_PFS_CNTL_1 0x4604 994254885Sdumbbell/* There is an unshifted value here which has so far always been equal to the 995254885Sdumbbell * index of the highest used temporary register. 996254885Sdumbbell */ 997254885Sdumbbell#define R300_PFS_CNTL_2 0x4608 998254885Sdumbbell# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 999254885Sdumbbell# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) 1000254885Sdumbbell# define R300_PFS_CNTL_ALU_END_SHIFT 6 1001254885Sdumbbell# define R300_PFS_CNTL_ALU_END_MASK (63 << 6) 1002254885Sdumbbell# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 1003254885Sdumbbell# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ 1004254885Sdumbbell# define R300_PFS_CNTL_TEX_END_SHIFT 18 1005254885Sdumbbell# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ 1006254885Sdumbbell 1007254885Sdumbbell/* gap */ 1008254885Sdumbbell 1009254885Sdumbbell/* Nodes are stored backwards. The last active node is always stored in 1010254885Sdumbbell * PFS_NODE_3. 1011254885Sdumbbell * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The 1012254885Sdumbbell * first node is stored in NODE_2, the second node is stored in NODE_3. 1013254885Sdumbbell * 1014254885Sdumbbell * Offsets are relative to the master offset from PFS_CNTL_2. 1015254885Sdumbbell */ 1016254885Sdumbbell#define R300_PFS_NODE_0 0x4610 1017254885Sdumbbell#define R300_PFS_NODE_1 0x4614 1018254885Sdumbbell#define R300_PFS_NODE_2 0x4618 1019254885Sdumbbell#define R300_PFS_NODE_3 0x461C 1020254885Sdumbbell# define R300_PFS_NODE_ALU_OFFSET_SHIFT 0 1021254885Sdumbbell# define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0) 1022254885Sdumbbell# define R300_PFS_NODE_ALU_END_SHIFT 6 1023254885Sdumbbell# define R300_PFS_NODE_ALU_END_MASK (63 << 6) 1024254885Sdumbbell# define R300_PFS_NODE_TEX_OFFSET_SHIFT 12 1025254885Sdumbbell# define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) 1026254885Sdumbbell# define R300_PFS_NODE_TEX_END_SHIFT 17 1027254885Sdumbbell# define R300_PFS_NODE_TEX_END_MASK (31 << 17) 1028254885Sdumbbell# define R300_PFS_NODE_OUTPUT_COLOR (1 << 22) 1029254885Sdumbbell# define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23) 1030254885Sdumbbell 1031254885Sdumbbell/* TEX 1032254885Sdumbbell * As far as I can tell, texture instructions cannot write into output 1033254885Sdumbbell * registers directly. A subsequent ALU instruction is always necessary, 1034254885Sdumbbell * even if it's just MAD o0, r0, 1, 0 1035254885Sdumbbell */ 1036254885Sdumbbell#define R300_PFS_TEXI_0 0x4620 1037254885Sdumbbell# define R300_FPITX_SRC_SHIFT 0 1038254885Sdumbbell# define R300_FPITX_SRC_MASK (31 << 0) 1039254885Sdumbbell /* GUESS */ 1040254885Sdumbbell# define R300_FPITX_SRC_CONST (1 << 5) 1041254885Sdumbbell# define R300_FPITX_DST_SHIFT 6 1042254885Sdumbbell# define R300_FPITX_DST_MASK (31 << 6) 1043254885Sdumbbell# define R300_FPITX_IMAGE_SHIFT 11 1044254885Sdumbbell /* GUESS based on layout and native limits */ 1045254885Sdumbbell# define R300_FPITX_IMAGE_MASK (15 << 11) 1046254885Sdumbbell/* Unsure if these are opcodes, or some kind of bitfield, but this is how 1047254885Sdumbbell * they were set when I checked 1048254885Sdumbbell */ 1049254885Sdumbbell# define R300_FPITX_OPCODE_SHIFT 15 1050254885Sdumbbell# define R300_FPITX_OP_TEX 1 1051254885Sdumbbell# define R300_FPITX_OP_KIL 2 1052254885Sdumbbell# define R300_FPITX_OP_TXP 3 1053254885Sdumbbell# define R300_FPITX_OP_TXB 4 1054254885Sdumbbell# define R300_FPITX_OPCODE_MASK (7 << 15) 1055254885Sdumbbell 1056254885Sdumbbell/* ALU 1057254885Sdumbbell * The ALU instructions register blocks are enumerated according to the order 1058254885Sdumbbell * in which fglrx. I assume there is space for 64 instructions, since 1059254885Sdumbbell * each block has space for a maximum of 64 DWORDs, and this matches reported 1060254885Sdumbbell * native limits. 1061254885Sdumbbell * 1062254885Sdumbbell * The basic functional block seems to be one MAD for each color and alpha, 1063254885Sdumbbell * and an adder that adds all components after the MUL. 1064254885Sdumbbell * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands 1065254885Sdumbbell * - DP4: Use OUTC_DP4, OUTA_DP4 1066254885Sdumbbell * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands 1067254885Sdumbbell * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands 1068254885Sdumbbell * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1 1069254885Sdumbbell * - CMP: If ARG2 < 0, return ARG1, else return ARG0 1070254885Sdumbbell * - FLR: use FRC+MAD 1071254885Sdumbbell * - XPD: use MAD+MAD 1072254885Sdumbbell * - SGE, SLT: use MAD+CMP 1073254885Sdumbbell * - RSQ: use ABS modifier for argument 1074254885Sdumbbell * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation 1075254885Sdumbbell * (e.g. RCP) into color register 1076254885Sdumbbell * - apparently, there's no quick DST operation 1077254885Sdumbbell * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" 1078254885Sdumbbell * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" 1079254885Sdumbbell * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" 1080254885Sdumbbell * 1081254885Sdumbbell * Operand selection 1082254885Sdumbbell * First stage selects three sources from the available registers and 1083254885Sdumbbell * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). 1084254885Sdumbbell * fglrx sorts the three source fields: Registers before constants, 1085254885Sdumbbell * lower indices before higher indices; I do not know whether this is 1086254885Sdumbbell * necessary. 1087254885Sdumbbell * 1088254885Sdumbbell * fglrx fills unused sources with "read constant 0" 1089254885Sdumbbell * According to specs, you cannot select more than two different constants. 1090254885Sdumbbell * 1091254885Sdumbbell * Second stage selects the operands from the sources. This is defined in 1092254885Sdumbbell * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants 1093254885Sdumbbell * zero and one. 1094254885Sdumbbell * Swizzling and negation happens in this stage, as well. 1095254885Sdumbbell * 1096254885Sdumbbell * Important: Color and alpha seem to be mostly separate, i.e. their sources 1097254885Sdumbbell * selection appears to be fully independent (the register storage is probably 1098254885Sdumbbell * physically split into a color and an alpha section). 1099254885Sdumbbell * However (because of the apparent physical split), there is some interaction 1100254885Sdumbbell * WRT swizzling. If, for example, you want to load an R component into an 1101254885Sdumbbell * Alpha operand, this R component is taken from a *color* source, not from 1102254885Sdumbbell * an alpha source. The corresponding register doesn't even have to appear in 1103254885Sdumbbell * the alpha sources list. (I hope this all makes sense to you) 1104254885Sdumbbell * 1105254885Sdumbbell * Destination selection 1106254885Sdumbbell * The destination register index is in FPI1 (color) and FPI3 (alpha) 1107254885Sdumbbell * together with enable bits. 1108254885Sdumbbell * There are separate enable bits for writing into temporary registers 1109254885Sdumbbell * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* 1110254885Sdumbbell * /DSTA_OUTPUT). You can write to both at once, or not write at all (the 1111254885Sdumbbell * same index must be used for both). 1112254885Sdumbbell * 1113254885Sdumbbell * Note: There is a special form for LRP 1114254885Sdumbbell * - Argument order is the same as in ARB_fragment_program. 1115254885Sdumbbell * - Operation is MAD 1116254885Sdumbbell * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP 1117254885Sdumbbell * - Set FPI0/FPI2_SPECIAL_LRP 1118254885Sdumbbell * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD 1119254885Sdumbbell */ 1120254885Sdumbbell#define R300_PFS_INSTR1_0 0x46C0 1121254885Sdumbbell# define R300_FPI1_SRC0C_SHIFT 0 1122254885Sdumbbell# define R300_FPI1_SRC0C_MASK (31 << 0) 1123254885Sdumbbell# define R300_FPI1_SRC0C_CONST (1 << 5) 1124254885Sdumbbell# define R300_FPI1_SRC1C_SHIFT 6 1125254885Sdumbbell# define R300_FPI1_SRC1C_MASK (31 << 6) 1126254885Sdumbbell# define R300_FPI1_SRC1C_CONST (1 << 11) 1127254885Sdumbbell# define R300_FPI1_SRC2C_SHIFT 12 1128254885Sdumbbell# define R300_FPI1_SRC2C_MASK (31 << 12) 1129254885Sdumbbell# define R300_FPI1_SRC2C_CONST (1 << 17) 1130254885Sdumbbell# define R300_FPI1_SRC_MASK 0x0003ffff 1131254885Sdumbbell# define R300_FPI1_DSTC_SHIFT 18 1132254885Sdumbbell# define R300_FPI1_DSTC_MASK (31 << 18) 1133254885Sdumbbell# define R300_FPI1_DSTC_REG_MASK_SHIFT 23 1134254885Sdumbbell# define R300_FPI1_DSTC_REG_X (1 << 23) 1135254885Sdumbbell# define R300_FPI1_DSTC_REG_Y (1 << 24) 1136254885Sdumbbell# define R300_FPI1_DSTC_REG_Z (1 << 25) 1137254885Sdumbbell# define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 26 1138254885Sdumbbell# define R300_FPI1_DSTC_OUTPUT_X (1 << 26) 1139254885Sdumbbell# define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) 1140254885Sdumbbell# define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) 1141254885Sdumbbell 1142254885Sdumbbell#define R300_PFS_INSTR3_0 0x47C0 1143254885Sdumbbell# define R300_FPI3_SRC0A_SHIFT 0 1144254885Sdumbbell# define R300_FPI3_SRC0A_MASK (31 << 0) 1145254885Sdumbbell# define R300_FPI3_SRC0A_CONST (1 << 5) 1146254885Sdumbbell# define R300_FPI3_SRC1A_SHIFT 6 1147254885Sdumbbell# define R300_FPI3_SRC1A_MASK (31 << 6) 1148254885Sdumbbell# define R300_FPI3_SRC1A_CONST (1 << 11) 1149254885Sdumbbell# define R300_FPI3_SRC2A_SHIFT 12 1150254885Sdumbbell# define R300_FPI3_SRC2A_MASK (31 << 12) 1151254885Sdumbbell# define R300_FPI3_SRC2A_CONST (1 << 17) 1152254885Sdumbbell# define R300_FPI3_SRC_MASK 0x0003ffff 1153254885Sdumbbell# define R300_FPI3_DSTA_SHIFT 18 1154254885Sdumbbell# define R300_FPI3_DSTA_MASK (31 << 18) 1155254885Sdumbbell# define R300_FPI3_DSTA_REG (1 << 23) 1156254885Sdumbbell# define R300_FPI3_DSTA_OUTPUT (1 << 24) 1157254885Sdumbbell# define R300_FPI3_DSTA_DEPTH (1 << 27) 1158254885Sdumbbell 1159254885Sdumbbell#define R300_PFS_INSTR0_0 0x48C0 1160254885Sdumbbell# define R300_FPI0_ARGC_SRC0C_XYZ 0 1161254885Sdumbbell# define R300_FPI0_ARGC_SRC0C_XXX 1 1162254885Sdumbbell# define R300_FPI0_ARGC_SRC0C_YYY 2 1163254885Sdumbbell# define R300_FPI0_ARGC_SRC0C_ZZZ 3 1164254885Sdumbbell# define R300_FPI0_ARGC_SRC1C_XYZ 4 1165254885Sdumbbell# define R300_FPI0_ARGC_SRC1C_XXX 5 1166254885Sdumbbell# define R300_FPI0_ARGC_SRC1C_YYY 6 1167254885Sdumbbell# define R300_FPI0_ARGC_SRC1C_ZZZ 7 1168254885Sdumbbell# define R300_FPI0_ARGC_SRC2C_XYZ 8 1169254885Sdumbbell# define R300_FPI0_ARGC_SRC2C_XXX 9 1170254885Sdumbbell# define R300_FPI0_ARGC_SRC2C_YYY 10 1171254885Sdumbbell# define R300_FPI0_ARGC_SRC2C_ZZZ 11 1172254885Sdumbbell# define R300_FPI0_ARGC_SRC0A 12 1173254885Sdumbbell# define R300_FPI0_ARGC_SRC1A 13 1174254885Sdumbbell# define R300_FPI0_ARGC_SRC2A 14 1175254885Sdumbbell# define R300_FPI0_ARGC_SRC1C_LRP 15 1176254885Sdumbbell# define R300_FPI0_ARGC_ZERO 20 1177254885Sdumbbell# define R300_FPI0_ARGC_ONE 21 1178254885Sdumbbell /* GUESS */ 1179254885Sdumbbell# define R300_FPI0_ARGC_HALF 22 1180254885Sdumbbell# define R300_FPI0_ARGC_SRC0C_YZX 23 1181254885Sdumbbell# define R300_FPI0_ARGC_SRC1C_YZX 24 1182254885Sdumbbell# define R300_FPI0_ARGC_SRC2C_YZX 25 1183254885Sdumbbell# define R300_FPI0_ARGC_SRC0C_ZXY 26 1184254885Sdumbbell# define R300_FPI0_ARGC_SRC1C_ZXY 27 1185254885Sdumbbell# define R300_FPI0_ARGC_SRC2C_ZXY 28 1186254885Sdumbbell# define R300_FPI0_ARGC_SRC0CA_WZY 29 1187254885Sdumbbell# define R300_FPI0_ARGC_SRC1CA_WZY 30 1188254885Sdumbbell# define R300_FPI0_ARGC_SRC2CA_WZY 31 1189254885Sdumbbell 1190254885Sdumbbell# define R300_FPI0_ARG0C_SHIFT 0 1191254885Sdumbbell# define R300_FPI0_ARG0C_MASK (31 << 0) 1192254885Sdumbbell# define R300_FPI0_ARG0C_NEG (1 << 5) 1193254885Sdumbbell# define R300_FPI0_ARG0C_ABS (1 << 6) 1194254885Sdumbbell# define R300_FPI0_ARG1C_SHIFT 7 1195254885Sdumbbell# define R300_FPI0_ARG1C_MASK (31 << 7) 1196254885Sdumbbell# define R300_FPI0_ARG1C_NEG (1 << 12) 1197254885Sdumbbell# define R300_FPI0_ARG1C_ABS (1 << 13) 1198254885Sdumbbell# define R300_FPI0_ARG2C_SHIFT 14 1199254885Sdumbbell# define R300_FPI0_ARG2C_MASK (31 << 14) 1200254885Sdumbbell# define R300_FPI0_ARG2C_NEG (1 << 19) 1201254885Sdumbbell# define R300_FPI0_ARG2C_ABS (1 << 20) 1202254885Sdumbbell# define R300_FPI0_SPECIAL_LRP (1 << 21) 1203254885Sdumbbell# define R300_FPI0_OUTC_MAD (0 << 23) 1204254885Sdumbbell# define R300_FPI0_OUTC_DP3 (1 << 23) 1205254885Sdumbbell# define R300_FPI0_OUTC_DP4 (2 << 23) 1206254885Sdumbbell# define R300_FPI0_OUTC_MIN (4 << 23) 1207254885Sdumbbell# define R300_FPI0_OUTC_MAX (5 << 23) 1208254885Sdumbbell# define R300_FPI0_OUTC_CMPH (7 << 23) 1209254885Sdumbbell# define R300_FPI0_OUTC_CMP (8 << 23) 1210254885Sdumbbell# define R300_FPI0_OUTC_FRC (9 << 23) 1211254885Sdumbbell# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) 1212254885Sdumbbell# define R300_FPI0_OUTC_SAT (1 << 30) 1213258780Seadler# define R300_FPI0_INSERT_NOP (1U << 31) 1214254885Sdumbbell 1215254885Sdumbbell#define R300_PFS_INSTR2_0 0x49C0 1216254885Sdumbbell# define R300_FPI2_ARGA_SRC0C_X 0 1217254885Sdumbbell# define R300_FPI2_ARGA_SRC0C_Y 1 1218254885Sdumbbell# define R300_FPI2_ARGA_SRC0C_Z 2 1219254885Sdumbbell# define R300_FPI2_ARGA_SRC1C_X 3 1220254885Sdumbbell# define R300_FPI2_ARGA_SRC1C_Y 4 1221254885Sdumbbell# define R300_FPI2_ARGA_SRC1C_Z 5 1222254885Sdumbbell# define R300_FPI2_ARGA_SRC2C_X 6 1223254885Sdumbbell# define R300_FPI2_ARGA_SRC2C_Y 7 1224254885Sdumbbell# define R300_FPI2_ARGA_SRC2C_Z 8 1225254885Sdumbbell# define R300_FPI2_ARGA_SRC0A 9 1226254885Sdumbbell# define R300_FPI2_ARGA_SRC1A 10 1227254885Sdumbbell# define R300_FPI2_ARGA_SRC2A 11 1228254885Sdumbbell# define R300_FPI2_ARGA_SRC1A_LRP 15 1229254885Sdumbbell# define R300_FPI2_ARGA_ZERO 16 1230254885Sdumbbell# define R300_FPI2_ARGA_ONE 17 1231254885Sdumbbell /* GUESS */ 1232254885Sdumbbell# define R300_FPI2_ARGA_HALF 18 1233254885Sdumbbell# define R300_FPI2_ARG0A_SHIFT 0 1234254885Sdumbbell# define R300_FPI2_ARG0A_MASK (31 << 0) 1235254885Sdumbbell# define R300_FPI2_ARG0A_NEG (1 << 5) 1236254885Sdumbbell /* GUESS */ 1237254885Sdumbbell# define R300_FPI2_ARG0A_ABS (1 << 6) 1238254885Sdumbbell# define R300_FPI2_ARG1A_SHIFT 7 1239254885Sdumbbell# define R300_FPI2_ARG1A_MASK (31 << 7) 1240254885Sdumbbell# define R300_FPI2_ARG1A_NEG (1 << 12) 1241254885Sdumbbell /* GUESS */ 1242254885Sdumbbell# define R300_FPI2_ARG1A_ABS (1 << 13) 1243254885Sdumbbell# define R300_FPI2_ARG2A_SHIFT 14 1244254885Sdumbbell# define R300_FPI2_ARG2A_MASK (31 << 14) 1245254885Sdumbbell# define R300_FPI2_ARG2A_NEG (1 << 19) 1246254885Sdumbbell /* GUESS */ 1247254885Sdumbbell# define R300_FPI2_ARG2A_ABS (1 << 20) 1248254885Sdumbbell# define R300_FPI2_SPECIAL_LRP (1 << 21) 1249254885Sdumbbell# define R300_FPI2_OUTA_MAD (0 << 23) 1250254885Sdumbbell# define R300_FPI2_OUTA_DP4 (1 << 23) 1251254885Sdumbbell# define R300_FPI2_OUTA_MIN (2 << 23) 1252254885Sdumbbell# define R300_FPI2_OUTA_MAX (3 << 23) 1253254885Sdumbbell# define R300_FPI2_OUTA_CMP (6 << 23) 1254254885Sdumbbell# define R300_FPI2_OUTA_FRC (7 << 23) 1255254885Sdumbbell# define R300_FPI2_OUTA_EX2 (8 << 23) 1256254885Sdumbbell# define R300_FPI2_OUTA_LG2 (9 << 23) 1257254885Sdumbbell# define R300_FPI2_OUTA_RCP (10 << 23) 1258254885Sdumbbell# define R300_FPI2_OUTA_RSQ (11 << 23) 1259254885Sdumbbell# define R300_FPI2_OUTA_SAT (1 << 30) 1260258780Seadler# define R300_FPI2_UNKNOWN_31 (1U << 31) 1261254885Sdumbbell/* END: Fragment program instruction set */ 1262254885Sdumbbell 1263254885Sdumbbell/* Fog state and color */ 1264254885Sdumbbell#define R300_RE_FOG_STATE 0x4BC0 1265254885Sdumbbell# define R300_FOG_ENABLE (1 << 0) 1266254885Sdumbbell# define R300_FOG_MODE_LINEAR (0 << 1) 1267254885Sdumbbell# define R300_FOG_MODE_EXP (1 << 1) 1268254885Sdumbbell# define R300_FOG_MODE_EXP2 (2 << 1) 1269254885Sdumbbell# define R300_FOG_MODE_MASK (3 << 1) 1270254885Sdumbbell#define R300_FOG_COLOR_R 0x4BC8 1271254885Sdumbbell#define R300_FOG_COLOR_G 0x4BCC 1272254885Sdumbbell#define R300_FOG_COLOR_B 0x4BD0 1273254885Sdumbbell 1274254885Sdumbbell#define R300_PP_ALPHA_TEST 0x4BD4 1275254885Sdumbbell# define R300_REF_ALPHA_MASK 0x000000ff 1276254885Sdumbbell# define R300_ALPHA_TEST_FAIL (0 << 8) 1277254885Sdumbbell# define R300_ALPHA_TEST_LESS (1 << 8) 1278254885Sdumbbell# define R300_ALPHA_TEST_LEQUAL (3 << 8) 1279254885Sdumbbell# define R300_ALPHA_TEST_EQUAL (2 << 8) 1280254885Sdumbbell# define R300_ALPHA_TEST_GEQUAL (6 << 8) 1281254885Sdumbbell# define R300_ALPHA_TEST_GREATER (4 << 8) 1282254885Sdumbbell# define R300_ALPHA_TEST_NEQUAL (5 << 8) 1283254885Sdumbbell# define R300_ALPHA_TEST_PASS (7 << 8) 1284254885Sdumbbell# define R300_ALPHA_TEST_OP_MASK (7 << 8) 1285254885Sdumbbell# define R300_ALPHA_TEST_ENABLE (1 << 11) 1286254885Sdumbbell 1287254885Sdumbbell/* gap */ 1288254885Sdumbbell 1289254885Sdumbbell/* Fragment program parameters in 7.16 floating point */ 1290254885Sdumbbell#define R300_PFS_PARAM_0_X 0x4C00 1291254885Sdumbbell#define R300_PFS_PARAM_0_Y 0x4C04 1292254885Sdumbbell#define R300_PFS_PARAM_0_Z 0x4C08 1293254885Sdumbbell#define R300_PFS_PARAM_0_W 0x4C0C 1294254885Sdumbbell/* GUESS: PARAM_31 is last, based on native limits reported by fglrx */ 1295254885Sdumbbell#define R300_PFS_PARAM_31_X 0x4DF0 1296254885Sdumbbell#define R300_PFS_PARAM_31_Y 0x4DF4 1297254885Sdumbbell#define R300_PFS_PARAM_31_Z 0x4DF8 1298254885Sdumbbell#define R300_PFS_PARAM_31_W 0x4DFC 1299254885Sdumbbell 1300254885Sdumbbell/* Notes: 1301254885Sdumbbell * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in 1302254885Sdumbbell * the application 1303254885Sdumbbell * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND 1304254885Sdumbbell * are set to the same 1305254885Sdumbbell * function (both registers are always set up completely in any case) 1306254885Sdumbbell * - Most blend flags are simply copied from R200 and not tested yet 1307254885Sdumbbell */ 1308254885Sdumbbell#define R300_RB3D_CBLEND 0x4E04 1309254885Sdumbbell#define R300_RB3D_ABLEND 0x4E08 1310254885Sdumbbell/* the following only appear in CBLEND */ 1311254885Sdumbbell# define R300_BLEND_ENABLE (1 << 0) 1312254885Sdumbbell# define R300_BLEND_UNKNOWN (3 << 1) 1313254885Sdumbbell# define R300_BLEND_NO_SEPARATE (1 << 3) 1314254885Sdumbbell/* the following are shared between CBLEND and ABLEND */ 1315254885Sdumbbell# define R300_FCN_MASK (3 << 12) 1316254885Sdumbbell# define R300_COMB_FCN_ADD_CLAMP (0 << 12) 1317254885Sdumbbell# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) 1318254885Sdumbbell# define R300_COMB_FCN_SUB_CLAMP (2 << 12) 1319254885Sdumbbell# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) 1320254885Sdumbbell# define R300_COMB_FCN_MIN (4 << 12) 1321254885Sdumbbell# define R300_COMB_FCN_MAX (5 << 12) 1322254885Sdumbbell# define R300_COMB_FCN_RSUB_CLAMP (6 << 12) 1323254885Sdumbbell# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12) 1324254885Sdumbbell# define R300_BLEND_GL_ZERO (32) 1325254885Sdumbbell# define R300_BLEND_GL_ONE (33) 1326254885Sdumbbell# define R300_BLEND_GL_SRC_COLOR (34) 1327254885Sdumbbell# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35) 1328254885Sdumbbell# define R300_BLEND_GL_DST_COLOR (36) 1329254885Sdumbbell# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37) 1330254885Sdumbbell# define R300_BLEND_GL_SRC_ALPHA (38) 1331254885Sdumbbell# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) 1332254885Sdumbbell# define R300_BLEND_GL_DST_ALPHA (40) 1333254885Sdumbbell# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41) 1334254885Sdumbbell# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42) 1335254885Sdumbbell# define R300_BLEND_GL_CONST_COLOR (43) 1336254885Sdumbbell# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44) 1337254885Sdumbbell# define R300_BLEND_GL_CONST_ALPHA (45) 1338254885Sdumbbell# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) 1339254885Sdumbbell# define R300_BLEND_MASK (63) 1340254885Sdumbbell# define R300_SRC_BLEND_SHIFT (16) 1341254885Sdumbbell# define R300_DST_BLEND_SHIFT (24) 1342254885Sdumbbell#define R300_RB3D_BLEND_COLOR 0x4E10 1343254885Sdumbbell#define R300_RB3D_COLORMASK 0x4E0C 1344254885Sdumbbell# define R300_COLORMASK0_B (1<<0) 1345254885Sdumbbell# define R300_COLORMASK0_G (1<<1) 1346254885Sdumbbell# define R300_COLORMASK0_R (1<<2) 1347254885Sdumbbell# define R300_COLORMASK0_A (1<<3) 1348254885Sdumbbell 1349254885Sdumbbell/* gap */ 1350254885Sdumbbell 1351254885Sdumbbell#define R300_RB3D_COLOROFFSET0 0x4E28 1352254885Sdumbbell# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ 1353254885Sdumbbell#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ 1354254885Sdumbbell#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ 1355254885Sdumbbell#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ 1356254885Sdumbbell 1357254885Sdumbbell/* gap */ 1358254885Sdumbbell 1359254885Sdumbbell/* Bit 16: Larger tiles 1360254885Sdumbbell * Bit 17: 4x2 tiles 1361254885Sdumbbell * Bit 18: Extremely weird tile like, but some pixels duplicated? 1362254885Sdumbbell */ 1363254885Sdumbbell#define R300_RB3D_COLORPITCH0 0x4E38 1364254885Sdumbbell# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ 1365254885Sdumbbell# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ 1366254885Sdumbbell# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1367254885Sdumbbell# define R300_COLOR_MICROTILE_SQUARE_ENABLE (2 << 17) 1368254885Sdumbbell# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1369254885Sdumbbell# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1370254885Sdumbbell# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1371254885Sdumbbell# define R300_COLOR_FORMAT_RGB565 (2 << 22) 1372254885Sdumbbell# define R300_COLOR_FORMAT_ARGB8888 (3 << 22) 1373254885Sdumbbell#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ 1374254885Sdumbbell#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ 1375254885Sdumbbell#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ 1376254885Sdumbbell 1377254885Sdumbbell#define R300_RB3D_AARESOLVE_OFFSET 0x4E80 1378254885Sdumbbell#define R300_RB3D_AARESOLVE_PITCH 0x4E84 1379254885Sdumbbell#define R300_RB3D_AARESOLVE_CTL 0x4E88 1380254885Sdumbbell/* gap */ 1381254885Sdumbbell 1382254885Sdumbbell/* Guess by Vladimir. 1383254885Sdumbbell * Set to 0A before 3D operations, set to 02 afterwards. 1384254885Sdumbbell */ 1385254885Sdumbbell/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/ 1386254885Sdumbbell# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 1387254885Sdumbbell# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A 1388254885Sdumbbell 1389254885Sdumbbell/* gap */ 1390254885Sdumbbell/* There seems to be no "write only" setting, so use Z-test = ALWAYS 1391254885Sdumbbell * for this. 1392254885Sdumbbell * Bit (1<<8) is the "test" bit. so plain write is 6 - vd 1393254885Sdumbbell */ 1394254885Sdumbbell#define R300_ZB_CNTL 0x4F00 1395254885Sdumbbell# define R300_STENCIL_ENABLE (1 << 0) 1396254885Sdumbbell# define R300_Z_ENABLE (1 << 1) 1397254885Sdumbbell# define R300_Z_WRITE_ENABLE (1 << 2) 1398254885Sdumbbell# define R300_Z_SIGNED_COMPARE (1 << 3) 1399254885Sdumbbell# define R300_STENCIL_FRONT_BACK (1 << 4) 1400254885Sdumbbell 1401254885Sdumbbell#define R300_ZB_ZSTENCILCNTL 0x4f04 1402254885Sdumbbell /* functions */ 1403254885Sdumbbell# define R300_ZS_NEVER 0 1404254885Sdumbbell# define R300_ZS_LESS 1 1405254885Sdumbbell# define R300_ZS_LEQUAL 2 1406254885Sdumbbell# define R300_ZS_EQUAL 3 1407254885Sdumbbell# define R300_ZS_GEQUAL 4 1408254885Sdumbbell# define R300_ZS_GREATER 5 1409254885Sdumbbell# define R300_ZS_NOTEQUAL 6 1410254885Sdumbbell# define R300_ZS_ALWAYS 7 1411254885Sdumbbell# define R300_ZS_MASK 7 1412254885Sdumbbell /* operations */ 1413254885Sdumbbell# define R300_ZS_KEEP 0 1414254885Sdumbbell# define R300_ZS_ZERO 1 1415254885Sdumbbell# define R300_ZS_REPLACE 2 1416254885Sdumbbell# define R300_ZS_INCR 3 1417254885Sdumbbell# define R300_ZS_DECR 4 1418254885Sdumbbell# define R300_ZS_INVERT 5 1419254885Sdumbbell# define R300_ZS_INCR_WRAP 6 1420254885Sdumbbell# define R300_ZS_DECR_WRAP 7 1421254885Sdumbbell# define R300_Z_FUNC_SHIFT 0 1422254885Sdumbbell /* front and back refer to operations done for front 1423254885Sdumbbell and back faces, i.e. separate stencil function support */ 1424254885Sdumbbell# define R300_S_FRONT_FUNC_SHIFT 3 1425254885Sdumbbell# define R300_S_FRONT_SFAIL_OP_SHIFT 6 1426254885Sdumbbell# define R300_S_FRONT_ZPASS_OP_SHIFT 9 1427254885Sdumbbell# define R300_S_FRONT_ZFAIL_OP_SHIFT 12 1428254885Sdumbbell# define R300_S_BACK_FUNC_SHIFT 15 1429254885Sdumbbell# define R300_S_BACK_SFAIL_OP_SHIFT 18 1430254885Sdumbbell# define R300_S_BACK_ZPASS_OP_SHIFT 21 1431254885Sdumbbell# define R300_S_BACK_ZFAIL_OP_SHIFT 24 1432254885Sdumbbell 1433254885Sdumbbell#define R300_ZB_STENCILREFMASK 0x4f08 1434254885Sdumbbell# define R300_STENCILREF_SHIFT 0 1435254885Sdumbbell# define R300_STENCILREF_MASK 0x000000ff 1436254885Sdumbbell# define R300_STENCILMASK_SHIFT 8 1437254885Sdumbbell# define R300_STENCILMASK_MASK 0x0000ff00 1438254885Sdumbbell# define R300_STENCILWRITEMASK_SHIFT 16 1439254885Sdumbbell# define R300_STENCILWRITEMASK_MASK 0x00ff0000 1440254885Sdumbbell 1441254885Sdumbbell/* gap */ 1442254885Sdumbbell 1443254885Sdumbbell#define R300_ZB_FORMAT 0x4f10 1444254885Sdumbbell# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) 1445254885Sdumbbell# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) 1446254885Sdumbbell# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) 1447254885Sdumbbell/* reserved up to (15 << 0) */ 1448254885Sdumbbell# define R300_INVERT_13E3_LEADING_ONES (0 << 4) 1449254885Sdumbbell# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) 1450254885Sdumbbell 1451254885Sdumbbell#define R300_ZB_ZTOP 0x4F14 1452254885Sdumbbell# define R300_ZTOP_DISABLE (0 << 0) 1453254885Sdumbbell# define R300_ZTOP_ENABLE (1 << 0) 1454254885Sdumbbell 1455254885Sdumbbell/* gap */ 1456254885Sdumbbell 1457254885Sdumbbell#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 1458254885Sdumbbell# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) 1459254885Sdumbbell# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) 1460254885Sdumbbell# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) 1461254885Sdumbbell# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) 1462254885Sdumbbell# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) 1463258780Seadler# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31) 1464254885Sdumbbell 1465254885Sdumbbell#define R300_ZB_BW_CNTL 0x4f1c 1466254885Sdumbbell# define R300_HIZ_DISABLE (0 << 0) 1467254885Sdumbbell# define R300_HIZ_ENABLE (1 << 0) 1468254885Sdumbbell# define R300_HIZ_MIN (0 << 1) 1469254885Sdumbbell# define R300_HIZ_MAX (1 << 1) 1470254885Sdumbbell# define R300_FAST_FILL_DISABLE (0 << 2) 1471254885Sdumbbell# define R300_FAST_FILL_ENABLE (1 << 2) 1472254885Sdumbbell# define R300_RD_COMP_DISABLE (0 << 3) 1473254885Sdumbbell# define R300_RD_COMP_ENABLE (1 << 3) 1474254885Sdumbbell# define R300_WR_COMP_DISABLE (0 << 4) 1475254885Sdumbbell# define R300_WR_COMP_ENABLE (1 << 4) 1476254885Sdumbbell# define R300_ZB_CB_CLEAR_RMW (0 << 5) 1477254885Sdumbbell# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5) 1478254885Sdumbbell# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) 1479254885Sdumbbell# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) 1480254885Sdumbbell 1481254885Sdumbbell# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) 1482254885Sdumbbell# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) 1483254885Sdumbbell# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) 1484254885Sdumbbell# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) 1485254885Sdumbbell 1486254885Sdumbbell# define R500_BMASK_ENABLE (0 << 10) 1487254885Sdumbbell# define R500_BMASK_DISABLE (1 << 10) 1488254885Sdumbbell# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) 1489254885Sdumbbell# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) 1490254885Sdumbbell# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) 1491254885Sdumbbell# define R500_HIZ_FP_EXP_BITS_1 (1 << 12) 1492254885Sdumbbell# define R500_HIZ_FP_EXP_BITS_2 (2 << 12) 1493254885Sdumbbell# define R500_HIZ_FP_EXP_BITS_3 (3 << 12) 1494254885Sdumbbell# define R500_HIZ_FP_EXP_BITS_4 (4 << 12) 1495254885Sdumbbell# define R500_HIZ_FP_EXP_BITS_5 (5 << 12) 1496254885Sdumbbell# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) 1497254885Sdumbbell# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) 1498254885Sdumbbell# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) 1499254885Sdumbbell# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) 1500254885Sdumbbell# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) 1501254885Sdumbbell# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) 1502254885Sdumbbell# define R500_PEQ_PACKING_DISABLE (0 << 18) 1503254885Sdumbbell# define R500_PEQ_PACKING_ENABLE (1 << 18) 1504254885Sdumbbell# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) 1505254885Sdumbbell# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) 1506254885Sdumbbell 1507254885Sdumbbell 1508254885Sdumbbell/* gap */ 1509254885Sdumbbell 1510254885Sdumbbell/* Z Buffer Address Offset. 1511254885Sdumbbell * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. 1512254885Sdumbbell */ 1513254885Sdumbbell#define R300_ZB_DEPTHOFFSET 0x4f20 1514254885Sdumbbell 1515254885Sdumbbell/* Z Buffer Pitch and Endian Control */ 1516254885Sdumbbell#define R300_ZB_DEPTHPITCH 0x4f24 1517254885Sdumbbell# define R300_DEPTHPITCH_MASK 0x00003FFC 1518254885Sdumbbell# define R300_DEPTHMACROTILE_DISABLE (0 << 16) 1519254885Sdumbbell# define R300_DEPTHMACROTILE_ENABLE (1 << 16) 1520254885Sdumbbell# define R300_DEPTHMICROTILE_LINEAR (0 << 17) 1521254885Sdumbbell# define R300_DEPTHMICROTILE_TILED (1 << 17) 1522254885Sdumbbell# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) 1523254885Sdumbbell# define R300_DEPTHENDIAN_NO_SWAP (0 << 18) 1524254885Sdumbbell# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) 1525254885Sdumbbell# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) 1526254885Sdumbbell# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) 1527254885Sdumbbell 1528254885Sdumbbell/* Z Buffer Clear Value */ 1529254885Sdumbbell#define R300_ZB_DEPTHCLEARVALUE 0x4f28 1530254885Sdumbbell 1531254885Sdumbbell#define R300_ZB_ZMASK_OFFSET 0x4f30 1532254885Sdumbbell#define R300_ZB_ZMASK_PITCH 0x4f34 1533254885Sdumbbell#define R300_ZB_ZMASK_WRINDEX 0x4f38 1534254885Sdumbbell#define R300_ZB_ZMASK_DWORD 0x4f3c 1535254885Sdumbbell#define R300_ZB_ZMASK_RDINDEX 0x4f40 1536254885Sdumbbell 1537254885Sdumbbell/* Hierarchical Z Memory Offset */ 1538254885Sdumbbell#define R300_ZB_HIZ_OFFSET 0x4f44 1539254885Sdumbbell 1540254885Sdumbbell/* Hierarchical Z Write Index */ 1541254885Sdumbbell#define R300_ZB_HIZ_WRINDEX 0x4f48 1542254885Sdumbbell 1543254885Sdumbbell/* Hierarchical Z Data */ 1544254885Sdumbbell#define R300_ZB_HIZ_DWORD 0x4f4c 1545254885Sdumbbell 1546254885Sdumbbell/* Hierarchical Z Read Index */ 1547254885Sdumbbell#define R300_ZB_HIZ_RDINDEX 0x4f50 1548254885Sdumbbell 1549254885Sdumbbell/* Hierarchical Z Pitch */ 1550254885Sdumbbell#define R300_ZB_HIZ_PITCH 0x4f54 1551254885Sdumbbell 1552254885Sdumbbell/* Z Buffer Z Pass Counter Data */ 1553254885Sdumbbell#define R300_ZB_ZPASS_DATA 0x4f58 1554254885Sdumbbell 1555254885Sdumbbell/* Z Buffer Z Pass Counter Address */ 1556254885Sdumbbell#define R300_ZB_ZPASS_ADDR 0x4f5c 1557254885Sdumbbell 1558254885Sdumbbell/* Depth buffer X and Y coordinate offset */ 1559254885Sdumbbell#define R300_ZB_DEPTHXY_OFFSET 0x4f60 1560254885Sdumbbell# define R300_DEPTHX_OFFSET_SHIFT 1 1561254885Sdumbbell# define R300_DEPTHX_OFFSET_MASK 0x000007FE 1562254885Sdumbbell# define R300_DEPTHY_OFFSET_SHIFT 17 1563254885Sdumbbell# define R300_DEPTHY_OFFSET_MASK 0x07FE0000 1564254885Sdumbbell 1565254885Sdumbbell/* Sets the fifo sizes */ 1566254885Sdumbbell#define R500_ZB_FIFO_SIZE 0x4fd0 1567254885Sdumbbell# define R500_OP_FIFO_SIZE_FULL (0 << 0) 1568254885Sdumbbell# define R500_OP_FIFO_SIZE_HALF (1 << 0) 1569254885Sdumbbell# define R500_OP_FIFO_SIZE_QUATER (2 << 0) 1570254885Sdumbbell# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) 1571254885Sdumbbell 1572254885Sdumbbell/* Stencil Reference Value and Mask for backfacing quads */ 1573254885Sdumbbell/* R300_ZB_STENCILREFMASK handles front face */ 1574254885Sdumbbell#define R500_ZB_STENCILREFMASK_BF 0x4fd4 1575254885Sdumbbell# define R500_STENCILREF_SHIFT 0 1576254885Sdumbbell# define R500_STENCILREF_MASK 0x000000ff 1577254885Sdumbbell# define R500_STENCILMASK_SHIFT 8 1578254885Sdumbbell# define R500_STENCILMASK_MASK 0x0000ff00 1579254885Sdumbbell# define R500_STENCILWRITEMASK_SHIFT 16 1580254885Sdumbbell# define R500_STENCILWRITEMASK_MASK 0x00ff0000 1581254885Sdumbbell 1582254885Sdumbbell/* BEGIN: Vertex program instruction set */ 1583254885Sdumbbell 1584254885Sdumbbell/* Every instruction is four dwords long: 1585254885Sdumbbell * DWORD 0: output and opcode 1586254885Sdumbbell * DWORD 1: first argument 1587254885Sdumbbell * DWORD 2: second argument 1588254885Sdumbbell * DWORD 3: third argument 1589254885Sdumbbell * 1590254885Sdumbbell * Notes: 1591254885Sdumbbell * - ABS r, a is implemented as MAX r, a, -a 1592254885Sdumbbell * - MOV is implemented as ADD to zero 1593254885Sdumbbell * - XPD is implemented as MUL + MAD 1594254885Sdumbbell * - FLR is implemented as FRC + ADD 1595254885Sdumbbell * - apparently, fglrx tries to schedule instructions so that there is at 1596254885Sdumbbell * least one instruction between the write to a temporary and the first 1597254885Sdumbbell * read from said temporary; however, violations of this scheduling are 1598254885Sdumbbell * allowed 1599254885Sdumbbell * - register indices seem to be unrelated with OpenGL aliasing to 1600254885Sdumbbell * conventional state 1601254885Sdumbbell * - only one attribute and one parameter can be loaded at a time; however, 1602254885Sdumbbell * the same attribute/parameter can be used for more than one argument 1603254885Sdumbbell * - the second software argument for POW is the third hardware argument 1604254885Sdumbbell * (no idea why) 1605254885Sdumbbell * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 1606254885Sdumbbell * 1607254885Sdumbbell * There is some magic surrounding LIT: 1608254885Sdumbbell * The single argument is replicated across all three inputs, but swizzled: 1609254885Sdumbbell * First argument: xyzy 1610254885Sdumbbell * Second argument: xyzx 1611254885Sdumbbell * Third argument: xyzw 1612254885Sdumbbell * Whenever the result is used later in the fragment program, fglrx forces 1613254885Sdumbbell * x and w to be 1.0 in the input selection; I don't know whether this is 1614254885Sdumbbell * strictly necessary 1615254885Sdumbbell */ 1616254885Sdumbbell#define R300_VPI_OUT_OP_DOT (1 << 0) 1617254885Sdumbbell#define R300_VPI_OUT_OP_MUL (2 << 0) 1618254885Sdumbbell#define R300_VPI_OUT_OP_ADD (3 << 0) 1619254885Sdumbbell#define R300_VPI_OUT_OP_MAD (4 << 0) 1620254885Sdumbbell#define R300_VPI_OUT_OP_DST (5 << 0) 1621254885Sdumbbell#define R300_VPI_OUT_OP_FRC (6 << 0) 1622254885Sdumbbell#define R300_VPI_OUT_OP_MAX (7 << 0) 1623254885Sdumbbell#define R300_VPI_OUT_OP_MIN (8 << 0) 1624254885Sdumbbell#define R300_VPI_OUT_OP_SGE (9 << 0) 1625254885Sdumbbell#define R300_VPI_OUT_OP_SLT (10 << 0) 1626254885Sdumbbell /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ 1627254885Sdumbbell#define R300_VPI_OUT_OP_UNK12 (12 << 0) 1628254885Sdumbbell#define R300_VPI_OUT_OP_ARL (13 << 0) 1629254885Sdumbbell#define R300_VPI_OUT_OP_EXP (65 << 0) 1630254885Sdumbbell#define R300_VPI_OUT_OP_LOG (66 << 0) 1631254885Sdumbbell /* Used in fog computations, scalar(scalar) */ 1632254885Sdumbbell#define R300_VPI_OUT_OP_UNK67 (67 << 0) 1633254885Sdumbbell#define R300_VPI_OUT_OP_LIT (68 << 0) 1634254885Sdumbbell#define R300_VPI_OUT_OP_POW (69 << 0) 1635254885Sdumbbell#define R300_VPI_OUT_OP_RCP (70 << 0) 1636254885Sdumbbell#define R300_VPI_OUT_OP_RSQ (72 << 0) 1637254885Sdumbbell /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ 1638254885Sdumbbell#define R300_VPI_OUT_OP_UNK73 (73 << 0) 1639254885Sdumbbell#define R300_VPI_OUT_OP_EX2 (75 << 0) 1640254885Sdumbbell#define R300_VPI_OUT_OP_LG2 (76 << 0) 1641254885Sdumbbell#define R300_VPI_OUT_OP_MAD_2 (128 << 0) 1642254885Sdumbbell /* all temps, vector(scalar, vector, vector) */ 1643254885Sdumbbell#define R300_VPI_OUT_OP_UNK129 (129 << 0) 1644254885Sdumbbell 1645254885Sdumbbell#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) 1646254885Sdumbbell#define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8) 1647254885Sdumbbell#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) 1648254885Sdumbbell#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) 1649254885Sdumbbell 1650254885Sdumbbell#define R300_VPI_OUT_REG_INDEX_SHIFT 13 1651254885Sdumbbell /* GUESS based on fglrx native limits */ 1652254885Sdumbbell#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) 1653254885Sdumbbell 1654254885Sdumbbell#define R300_VPI_OUT_WRITE_X (1 << 20) 1655254885Sdumbbell#define R300_VPI_OUT_WRITE_Y (1 << 21) 1656254885Sdumbbell#define R300_VPI_OUT_WRITE_Z (1 << 22) 1657254885Sdumbbell#define R300_VPI_OUT_WRITE_W (1 << 23) 1658254885Sdumbbell 1659254885Sdumbbell#define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0) 1660254885Sdumbbell#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) 1661254885Sdumbbell#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) 1662254885Sdumbbell#define R300_VPI_IN_REG_CLASS_NONE (9 << 0) 1663254885Sdumbbell#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) 1664254885Sdumbbell 1665254885Sdumbbell#define R300_VPI_IN_REG_INDEX_SHIFT 5 1666254885Sdumbbell /* GUESS based on fglrx native limits */ 1667254885Sdumbbell#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) 1668254885Sdumbbell 1669254885Sdumbbell/* The R300 can select components from the input register arbitrarily. 1670254885Sdumbbell * Use the following constants, shifted by the component shift you 1671254885Sdumbbell * want to select 1672254885Sdumbbell */ 1673254885Sdumbbell#define R300_VPI_IN_SELECT_X 0 1674254885Sdumbbell#define R300_VPI_IN_SELECT_Y 1 1675254885Sdumbbell#define R300_VPI_IN_SELECT_Z 2 1676254885Sdumbbell#define R300_VPI_IN_SELECT_W 3 1677254885Sdumbbell#define R300_VPI_IN_SELECT_ZERO 4 1678254885Sdumbbell#define R300_VPI_IN_SELECT_ONE 5 1679254885Sdumbbell#define R300_VPI_IN_SELECT_MASK 7 1680254885Sdumbbell 1681254885Sdumbbell#define R300_VPI_IN_X_SHIFT 13 1682254885Sdumbbell#define R300_VPI_IN_Y_SHIFT 16 1683254885Sdumbbell#define R300_VPI_IN_Z_SHIFT 19 1684254885Sdumbbell#define R300_VPI_IN_W_SHIFT 22 1685254885Sdumbbell 1686254885Sdumbbell#define R300_VPI_IN_NEG_X (1 << 25) 1687254885Sdumbbell#define R300_VPI_IN_NEG_Y (1 << 26) 1688254885Sdumbbell#define R300_VPI_IN_NEG_Z (1 << 27) 1689254885Sdumbbell#define R300_VPI_IN_NEG_W (1 << 28) 1690254885Sdumbbell/* END: Vertex program instruction set */ 1691254885Sdumbbell 1692254885Sdumbbell/* BEGIN: Packet 3 commands */ 1693254885Sdumbbell 1694254885Sdumbbell/* A primitive emission dword. */ 1695254885Sdumbbell#define R300_PRIM_TYPE_NONE (0 << 0) 1696254885Sdumbbell#define R300_PRIM_TYPE_POINT (1 << 0) 1697254885Sdumbbell#define R300_PRIM_TYPE_LINE (2 << 0) 1698254885Sdumbbell#define R300_PRIM_TYPE_LINE_STRIP (3 << 0) 1699254885Sdumbbell#define R300_PRIM_TYPE_TRI_LIST (4 << 0) 1700254885Sdumbbell#define R300_PRIM_TYPE_TRI_FAN (5 << 0) 1701254885Sdumbbell#define R300_PRIM_TYPE_TRI_STRIP (6 << 0) 1702254885Sdumbbell#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1703254885Sdumbbell#define R300_PRIM_TYPE_RECT_LIST (8 << 0) 1704254885Sdumbbell#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1705254885Sdumbbell#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1706254885Sdumbbell /* GUESS (based on r200) */ 1707254885Sdumbbell#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) 1708254885Sdumbbell#define R300_PRIM_TYPE_LINE_LOOP (12 << 0) 1709254885Sdumbbell#define R300_PRIM_TYPE_QUADS (13 << 0) 1710254885Sdumbbell#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) 1711254885Sdumbbell#define R300_PRIM_TYPE_POLYGON (15 << 0) 1712254885Sdumbbell#define R300_PRIM_TYPE_MASK 0xF 1713254885Sdumbbell#define R300_PRIM_WALK_IND (1 << 4) 1714254885Sdumbbell#define R300_PRIM_WALK_LIST (2 << 4) 1715254885Sdumbbell#define R300_PRIM_WALK_RING (3 << 4) 1716254885Sdumbbell#define R300_PRIM_WALK_MASK (3 << 4) 1717254885Sdumbbell /* GUESS (based on r200) */ 1718254885Sdumbbell#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) 1719254885Sdumbbell#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) 1720254885Sdumbbell#define R300_PRIM_NUM_VERTICES_SHIFT 16 1721254885Sdumbbell#define R300_PRIM_NUM_VERTICES_MASK 0xffff 1722254885Sdumbbell 1723254885Sdumbbell/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. 1724254885Sdumbbell * Two parameter dwords: 1725254885Sdumbbell * 0. The first parameter appears to be always 0 1726254885Sdumbbell * 1. The second parameter is a standard primitive emission dword. 1727254885Sdumbbell */ 1728254885Sdumbbell#define R300_PACKET3_3D_DRAW_VBUF 0x00002800 1729254885Sdumbbell 1730254885Sdumbbell/* Specify the full set of vertex arrays as (address, stride). 1731254885Sdumbbell * The first parameter is the number of vertex arrays specified. 1732254885Sdumbbell * The rest of the command is a variable length list of blocks, where 1733254885Sdumbbell * each block is three dwords long and specifies two arrays. 1734254885Sdumbbell * The first dword of a block is split into two words, the lower significant 1735254885Sdumbbell * word refers to the first array, the more significant word to the second 1736254885Sdumbbell * array in the block. 1737254885Sdumbbell * The low byte of each word contains the size of an array entry in dwords, 1738254885Sdumbbell * the high byte contains the stride of the array. 1739254885Sdumbbell * The second dword of a block contains the pointer to the first array, 1740254885Sdumbbell * the third dword of a block contains the pointer to the second array. 1741254885Sdumbbell * Note that if the total number of arrays is odd, the third dword of 1742254885Sdumbbell * the last block is omitted. 1743254885Sdumbbell */ 1744254885Sdumbbell#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 1745254885Sdumbbell 1746254885Sdumbbell#define R300_PACKET3_INDX_BUFFER 0x00003300 1747254885Sdumbbell# define R300_EB_UNK1_SHIFT 24 1748254885Sdumbbell# define R300_EB_UNK1 (0x80<<24) 1749254885Sdumbbell# define R300_EB_UNK2 0x0810 1750254885Sdumbbell#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 1751254885Sdumbbell#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 1752254885Sdumbbell 1753254885Sdumbbell/* END: Packet 3 commands */ 1754254885Sdumbbell 1755254885Sdumbbell 1756254885Sdumbbell/* Color formats for 2d packets 1757254885Sdumbbell */ 1758254885Sdumbbell#define R300_CP_COLOR_FORMAT_CI8 2 1759254885Sdumbbell#define R300_CP_COLOR_FORMAT_ARGB1555 3 1760254885Sdumbbell#define R300_CP_COLOR_FORMAT_RGB565 4 1761254885Sdumbbell#define R300_CP_COLOR_FORMAT_ARGB8888 6 1762254885Sdumbbell#define R300_CP_COLOR_FORMAT_RGB332 7 1763254885Sdumbbell#define R300_CP_COLOR_FORMAT_RGB8 9 1764254885Sdumbbell#define R300_CP_COLOR_FORMAT_ARGB4444 15 1765254885Sdumbbell 1766254885Sdumbbell/* 1767254885Sdumbbell * CP type-3 packets 1768254885Sdumbbell */ 1769254885Sdumbbell#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 1770254885Sdumbbell 1771254885Sdumbbell#define R500_VAP_INDEX_OFFSET 0x208c 1772254885Sdumbbell 1773254885Sdumbbell#define R500_GA_US_VECTOR_INDEX 0x4250 1774254885Sdumbbell#define R500_GA_US_VECTOR_DATA 0x4254 1775254885Sdumbbell 1776254885Sdumbbell#define R500_RS_IP_0 0x4074 1777254885Sdumbbell#define R500_RS_INST_0 0x4320 1778254885Sdumbbell 1779254885Sdumbbell#define R500_US_CONFIG 0x4600 1780254885Sdumbbell 1781254885Sdumbbell#define R500_US_FC_CTRL 0x4624 1782254885Sdumbbell#define R500_US_CODE_ADDR 0x4630 1783254885Sdumbbell 1784254885Sdumbbell#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 1785254885Sdumbbell#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 1786254885Sdumbbell 1787254885Sdumbbell#define R300_SU_REG_DEST 0x42c8 1788254885Sdumbbell#define RV530_FG_ZBREG_DEST 0x4be8 1789254885Sdumbbell#define R300_ZB_ZPASS_DATA 0x4f58 1790254885Sdumbbell#define R300_ZB_ZPASS_ADDR 0x4f5c 1791254885Sdumbbell 1792254885Sdumbbell#endif /* _R300_REG_H */ 1793