1296548Sdumbbell/* 2235783Skib * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3235783Skib * All Rights Reserved. 4235783Skib * 5235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 6235783Skib * copy of this software and associated documentation files (the 7235783Skib * "Software"), to deal in the Software without restriction, including 8235783Skib * without limitation the rights to use, copy, modify, merge, publish, 9235783Skib * distribute, sub license, and/or sell copies of the Software, and to 10235783Skib * permit persons to whom the Software is furnished to do so, subject to 11235783Skib * the following conditions: 12235783Skib * 13235783Skib * The above copyright notice and this permission notice (including the 14235783Skib * next paragraph) shall be included in all copies or substantial portions 15235783Skib * of the Software. 16235783Skib * 17235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18235783Skib * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19235783Skib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20235783Skib * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21235783Skib * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22235783Skib * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23235783Skib * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24235783Skib * 25235783Skib */ 26235783Skib 27296548Sdumbbell#ifndef _UAPI_I915_DRM_H_ 28296548Sdumbbell#define _UAPI_I915_DRM_H_ 29296548Sdumbbell 30235783Skib#include <sys/cdefs.h> 31235783Skib__FBSDID("$FreeBSD: releng/11.0/sys/dev/drm2/i915/i915_drm.h 298955 2016-05-03 03:41:25Z pfg $"); 32235783Skib 33296548Sdumbbell#include <dev/drm2/drm.h> 34235783Skib 35235783Skib/* Please note that modifications to all structs defined here are 36235783Skib * subject to backwards-compatibility constraints. 37235783Skib */ 38235783Skib 39235783Skib 40235783Skib/* Each region is a minimum of 16k, and there are at most 255 of them. 41235783Skib */ 42235783Skib#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 43235783Skib * of chars for next/prev indices */ 44235783Skib#define I915_LOG_MIN_TEX_REGION_SIZE 14 45235783Skib 46235783Skibtypedef struct _drm_i915_init { 47235783Skib enum { 48235783Skib I915_INIT_DMA = 0x01, 49235783Skib I915_CLEANUP_DMA = 0x02, 50296548Sdumbbell I915_RESUME_DMA = 0x03 51235783Skib } func; 52235783Skib unsigned int mmio_offset; 53235783Skib int sarea_priv_offset; 54235783Skib unsigned int ring_start; 55235783Skib unsigned int ring_end; 56235783Skib unsigned int ring_size; 57235783Skib unsigned int front_offset; 58235783Skib unsigned int back_offset; 59235783Skib unsigned int depth_offset; 60235783Skib unsigned int w; 61235783Skib unsigned int h; 62235783Skib unsigned int pitch; 63235783Skib unsigned int pitch_bits; 64235783Skib unsigned int back_pitch; 65235783Skib unsigned int depth_pitch; 66235783Skib unsigned int cpp; 67235783Skib unsigned int chipset; 68235783Skib} drm_i915_init_t; 69235783Skib 70280183Sdumbbelltypedef struct _drm_i915_sarea { 71235783Skib struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 72235783Skib int last_upload; /* last time texture was uploaded */ 73235783Skib int last_enqueue; /* last time a buffer was enqueued */ 74235783Skib int last_dispatch; /* age of the most recently dispatched buffer */ 75235783Skib int ctxOwner; /* last context to upload state */ 76235783Skib int texAge; 77235783Skib int pf_enabled; /* is pageflipping allowed? */ 78235783Skib int pf_active; 79235783Skib int pf_current_page; /* which buffer is being displayed? */ 80235783Skib int perf_boxes; /* performance boxes to be displayed */ 81235783Skib int width, height; /* screen size in pixels */ 82235783Skib 83235783Skib drm_handle_t front_handle; 84235783Skib int front_offset; 85235783Skib int front_size; 86235783Skib 87235783Skib drm_handle_t back_handle; 88235783Skib int back_offset; 89235783Skib int back_size; 90235783Skib 91235783Skib drm_handle_t depth_handle; 92235783Skib int depth_offset; 93235783Skib int depth_size; 94235783Skib 95235783Skib drm_handle_t tex_handle; 96235783Skib int tex_offset; 97235783Skib int tex_size; 98235783Skib int log_tex_granularity; 99235783Skib int pitch; 100235783Skib int rotation; /* 0, 90, 180 or 270 */ 101235783Skib int rotated_offset; 102235783Skib int rotated_size; 103235783Skib int rotated_pitch; 104235783Skib int virtualX, virtualY; 105235783Skib 106235783Skib unsigned int front_tiled; 107235783Skib unsigned int back_tiled; 108235783Skib unsigned int depth_tiled; 109235783Skib unsigned int rotated_tiled; 110235783Skib unsigned int rotated2_tiled; 111235783Skib 112280183Sdumbbell int pipeA_x; 113280183Sdumbbell int pipeA_y; 114280183Sdumbbell int pipeA_w; 115280183Sdumbbell int pipeA_h; 116280183Sdumbbell int pipeB_x; 117280183Sdumbbell int pipeB_y; 118280183Sdumbbell int pipeB_w; 119280183Sdumbbell int pipeB_h; 120235783Skib 121296548Sdumbbell /* fill out some space for old userspace triple buffer */ 122296548Sdumbbell drm_handle_t unused_handle; 123296548Sdumbbell __u32 unused1, unused2, unused3; 124235783Skib 125296548Sdumbbell /* buffer object handles for static buffers. May change 126296548Sdumbbell * over the lifetime of the client. 127235783Skib */ 128291431Sdumbbell __u32 front_bo_handle; 129291431Sdumbbell __u32 back_bo_handle; 130296548Sdumbbell __u32 unused_bo_handle; 131291431Sdumbbell __u32 depth_bo_handle; 132296548Sdumbbell 133235783Skib} drm_i915_sarea_t; 134235783Skib 135280183Sdumbbell/* due to userspace building against these headers we need some compat here */ 136280183Sdumbbell#define planeA_x pipeA_x 137280183Sdumbbell#define planeA_y pipeA_y 138280183Sdumbbell#define planeA_w pipeA_w 139280183Sdumbbell#define planeA_h pipeA_h 140280183Sdumbbell#define planeB_x pipeB_x 141280183Sdumbbell#define planeB_y pipeB_y 142280183Sdumbbell#define planeB_w pipeB_w 143280183Sdumbbell#define planeB_h pipeB_h 144280183Sdumbbell 145235783Skib/* Flags for perf_boxes 146235783Skib */ 147235783Skib#define I915_BOX_RING_EMPTY 0x1 148235783Skib#define I915_BOX_FLIP 0x2 149235783Skib#define I915_BOX_WAIT 0x4 150235783Skib#define I915_BOX_TEXTURE_LOAD 0x8 151235783Skib#define I915_BOX_LOST_CONTEXT 0x10 152235783Skib 153235783Skib/* I915 specific ioctls 154235783Skib * The device specific ioctl range is 0x40 to 0x79. 155235783Skib */ 156235783Skib#define DRM_I915_INIT 0x00 157235783Skib#define DRM_I915_FLUSH 0x01 158235783Skib#define DRM_I915_FLIP 0x02 159235783Skib#define DRM_I915_BATCHBUFFER 0x03 160235783Skib#define DRM_I915_IRQ_EMIT 0x04 161235783Skib#define DRM_I915_IRQ_WAIT 0x05 162235783Skib#define DRM_I915_GETPARAM 0x06 163235783Skib#define DRM_I915_SETPARAM 0x07 164235783Skib#define DRM_I915_ALLOC 0x08 165235783Skib#define DRM_I915_FREE 0x09 166235783Skib#define DRM_I915_INIT_HEAP 0x0a 167235783Skib#define DRM_I915_CMDBUFFER 0x0b 168235783Skib#define DRM_I915_DESTROY_HEAP 0x0c 169235783Skib#define DRM_I915_SET_VBLANK_PIPE 0x0d 170235783Skib#define DRM_I915_GET_VBLANK_PIPE 0x0e 171235783Skib#define DRM_I915_VBLANK_SWAP 0x0f 172235783Skib#define DRM_I915_HWS_ADDR 0x11 173235783Skib#define DRM_I915_GEM_INIT 0x13 174235783Skib#define DRM_I915_GEM_EXECBUFFER 0x14 175235783Skib#define DRM_I915_GEM_PIN 0x15 176235783Skib#define DRM_I915_GEM_UNPIN 0x16 177235783Skib#define DRM_I915_GEM_BUSY 0x17 178235783Skib#define DRM_I915_GEM_THROTTLE 0x18 179235783Skib#define DRM_I915_GEM_ENTERVT 0x19 180235783Skib#define DRM_I915_GEM_LEAVEVT 0x1a 181235783Skib#define DRM_I915_GEM_CREATE 0x1b 182235783Skib#define DRM_I915_GEM_PREAD 0x1c 183235783Skib#define DRM_I915_GEM_PWRITE 0x1d 184235783Skib#define DRM_I915_GEM_MMAP 0x1e 185235783Skib#define DRM_I915_GEM_SET_DOMAIN 0x1f 186235783Skib#define DRM_I915_GEM_SW_FINISH 0x20 187235783Skib#define DRM_I915_GEM_SET_TILING 0x21 188235783Skib#define DRM_I915_GEM_GET_TILING 0x22 189235783Skib#define DRM_I915_GEM_GET_APERTURE 0x23 190235783Skib#define DRM_I915_GEM_MMAP_GTT 0x24 191235783Skib#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 192235783Skib#define DRM_I915_GEM_MADVISE 0x26 193235783Skib#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 194235783Skib#define DRM_I915_OVERLAY_ATTRS 0x28 195235783Skib#define DRM_I915_GEM_EXECBUFFER2 0x29 196296548Sdumbbell#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 197296548Sdumbbell#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 198296548Sdumbbell#define DRM_I915_GEM_WAIT 0x2c 199271705Sdumbbell#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 200271705Sdumbbell#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 201296548Sdumbbell#define DRM_I915_GEM_SET_CACHING 0x2f 202296548Sdumbbell#define DRM_I915_GEM_GET_CACHING 0x30 203296548Sdumbbell#define DRM_I915_REG_READ 0x31 204235783Skib 205235783Skib#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 206235783Skib#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 207296548Sdumbbell#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 208235783Skib#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 209235783Skib#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 210235783Skib#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 211235783Skib#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 212235783Skib#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 213235783Skib#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 214235783Skib#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 215235783Skib#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 216235783Skib#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 217235783Skib#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 218235783Skib#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 219235783Skib#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 220235783Skib#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 221296548Sdumbbell#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 222235783Skib#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 223235783Skib#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 224235783Skib#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 225235783Skib#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 226235783Skib#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 227235783Skib#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 228296548Sdumbbell#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 229296548Sdumbbell#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 230235783Skib#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 231235783Skib#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 232235783Skib#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 233235783Skib#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 234235783Skib#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 235235783Skib#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 236235783Skib#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 237235783Skib#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 238235783Skib#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 239235783Skib#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 240235783Skib#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 241235783Skib#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 242235783Skib#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 243235783Skib#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 244235783Skib#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 245296548Sdumbbell#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 246235783Skib#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 247235783Skib#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 248235783Skib#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 249296548Sdumbbell#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 250271705Sdumbbell#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 251271705Sdumbbell#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 252296548Sdumbbell#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 253235783Skib 254235783Skib/* Allow drivers to submit batchbuffers directly to hardware, relying 255235783Skib * on the security mechanisms provided by hardware. 256235783Skib */ 257235783Skibtypedef struct drm_i915_batchbuffer { 258235783Skib int start; /* agp offset */ 259235783Skib int used; /* nr bytes in use */ 260235783Skib int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 261235783Skib int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 262235783Skib int num_cliprects; /* mulitpass with multiple cliprects? */ 263235783Skib struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 264235783Skib} drm_i915_batchbuffer_t; 265235783Skib 266235783Skib/* As above, but pass a pointer to userspace buffer which can be 267235783Skib * validated by the kernel prior to sending to hardware. 268235783Skib */ 269235783Skibtypedef struct _drm_i915_cmdbuffer { 270235783Skib char __user *buf; /* pointer to userspace command buffer */ 271235783Skib int sz; /* nr bytes in buf */ 272235783Skib int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 273235783Skib int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 274235783Skib int num_cliprects; /* mulitpass with multiple cliprects? */ 275235783Skib struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 276235783Skib} drm_i915_cmdbuffer_t; 277235783Skib 278235783Skib/* Userspace can request & wait on irq's: 279235783Skib */ 280235783Skibtypedef struct drm_i915_irq_emit { 281235783Skib int __user *irq_seq; 282235783Skib} drm_i915_irq_emit_t; 283235783Skib 284235783Skibtypedef struct drm_i915_irq_wait { 285235783Skib int irq_seq; 286235783Skib} drm_i915_irq_wait_t; 287235783Skib 288235783Skib/* Ioctl to query kernel params: 289235783Skib */ 290296548Sdumbbell#define I915_PARAM_IRQ_ACTIVE 1 291296548Sdumbbell#define I915_PARAM_ALLOW_BATCHBUFFER 2 292296548Sdumbbell#define I915_PARAM_LAST_DISPATCH 3 293296548Sdumbbell#define I915_PARAM_CHIPSET_ID 4 294296548Sdumbbell#define I915_PARAM_HAS_GEM 5 295296548Sdumbbell#define I915_PARAM_NUM_FENCES_AVAIL 6 296296548Sdumbbell#define I915_PARAM_HAS_OVERLAY 7 297235783Skib#define I915_PARAM_HAS_PAGEFLIPPING 8 298296548Sdumbbell#define I915_PARAM_HAS_EXECBUF2 9 299235783Skib#define I915_PARAM_HAS_BSD 10 300235783Skib#define I915_PARAM_HAS_BLT 11 301235783Skib#define I915_PARAM_HAS_RELAXED_FENCING 12 302235783Skib#define I915_PARAM_HAS_COHERENT_RINGS 13 303235783Skib#define I915_PARAM_HAS_EXEC_CONSTANTS 14 304235783Skib#define I915_PARAM_HAS_RELAXED_DELTA 15 305235783Skib#define I915_PARAM_HAS_GEN7_SOL_RESET 16 306296548Sdumbbell#define I915_PARAM_HAS_LLC 17 307277487Skib#define I915_PARAM_HAS_ALIASING_PPGTT 18 308296548Sdumbbell#define I915_PARAM_HAS_WAIT_TIMEOUT 19 309296548Sdumbbell#define I915_PARAM_HAS_SEMAPHORES 20 310296548Sdumbbell#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 311296548Sdumbbell#define I915_PARAM_RSVD_FOR_FUTURE_USE 22 312296548Sdumbbell#define I915_PARAM_HAS_SECURE_BATCHES 23 313296548Sdumbbell#define I915_PARAM_HAS_PINNED_BATCHES 24 314235783Skib 315235783Skibtypedef struct drm_i915_getparam { 316235783Skib int param; 317235783Skib int __user *value; 318235783Skib} drm_i915_getparam_t; 319235783Skib 320235783Skib/* Ioctl to set kernel params: 321235783Skib */ 322235783Skib#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 323235783Skib#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 324235783Skib#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 325235783Skib#define I915_SETPARAM_NUM_USED_FENCES 4 326235783Skib 327235783Skibtypedef struct drm_i915_setparam { 328235783Skib int param; 329235783Skib int value; 330235783Skib} drm_i915_setparam_t; 331235783Skib 332235783Skib/* A memory manager for regions of shared memory: 333235783Skib */ 334235783Skib#define I915_MEM_REGION_AGP 1 335235783Skib 336235783Skibtypedef struct drm_i915_mem_alloc { 337235783Skib int region; 338235783Skib int alignment; 339235783Skib int size; 340235783Skib int __user *region_offset; /* offset from start of fb or agp */ 341235783Skib} drm_i915_mem_alloc_t; 342235783Skib 343235783Skibtypedef struct drm_i915_mem_free { 344235783Skib int region; 345235783Skib int region_offset; 346235783Skib} drm_i915_mem_free_t; 347235783Skib 348235783Skibtypedef struct drm_i915_mem_init_heap { 349235783Skib int region; 350235783Skib int size; 351235783Skib int start; 352235783Skib} drm_i915_mem_init_heap_t; 353235783Skib 354235783Skib/* Allow memory manager to be torn down and re-initialized (eg on 355235783Skib * rotate): 356235783Skib */ 357235783Skibtypedef struct drm_i915_mem_destroy_heap { 358235783Skib int region; 359235783Skib} drm_i915_mem_destroy_heap_t; 360235783Skib 361235783Skib/* Allow X server to configure which pipes to monitor for vblank signals 362235783Skib */ 363235783Skib#define DRM_I915_VBLANK_PIPE_A 1 364235783Skib#define DRM_I915_VBLANK_PIPE_B 2 365235783Skib 366235783Skibtypedef struct drm_i915_vblank_pipe { 367235783Skib int pipe; 368235783Skib} drm_i915_vblank_pipe_t; 369235783Skib 370235783Skib/* Schedule buffer swap at given vertical blank: 371235783Skib */ 372235783Skibtypedef struct drm_i915_vblank_swap { 373235783Skib drm_drawable_t drawable; 374235783Skib enum drm_vblank_seq_type seqtype; 375235783Skib unsigned int sequence; 376235783Skib} drm_i915_vblank_swap_t; 377235783Skib 378235783Skibtypedef struct drm_i915_hws_addr { 379291431Sdumbbell __u64 addr; 380235783Skib} drm_i915_hws_addr_t; 381235783Skib 382235783Skibstruct drm_i915_gem_init { 383235783Skib /** 384235783Skib * Beginning offset in the GTT to be managed by the DRM memory 385235783Skib * manager. 386235783Skib */ 387291431Sdumbbell __u64 gtt_start; 388235783Skib /** 389235783Skib * Ending offset in the GTT to be managed by the DRM memory 390235783Skib * manager. 391235783Skib */ 392291431Sdumbbell __u64 gtt_end; 393235783Skib}; 394235783Skib 395235783Skibstruct drm_i915_gem_create { 396235783Skib /** 397235783Skib * Requested size for the object. 398235783Skib * 399235783Skib * The (page-aligned) allocated size for the object will be returned. 400235783Skib */ 401291431Sdumbbell __u64 size; 402235783Skib /** 403235783Skib * Returned handle for the object. 404235783Skib * 405235783Skib * Object handles are nonzero. 406235783Skib */ 407291431Sdumbbell __u32 handle; 408291431Sdumbbell __u32 pad; 409235783Skib}; 410235783Skib 411235783Skibstruct drm_i915_gem_pread { 412235783Skib /** Handle for the object being read. */ 413291431Sdumbbell __u32 handle; 414291431Sdumbbell __u32 pad; 415235783Skib /** Offset into the object to read from */ 416291431Sdumbbell __u64 offset; 417235783Skib /** Length of data to read */ 418291431Sdumbbell __u64 size; 419296548Sdumbbell /** 420296548Sdumbbell * Pointer to write the data into. 421296548Sdumbbell * 422296548Sdumbbell * This is a fixed-size type for 32/64 compatibility. 423296548Sdumbbell */ 424296548Sdumbbell __u64 data_ptr; 425235783Skib}; 426235783Skib 427235783Skibstruct drm_i915_gem_pwrite { 428235783Skib /** Handle for the object being written to. */ 429291431Sdumbbell __u32 handle; 430291431Sdumbbell __u32 pad; 431235783Skib /** Offset into the object to write to */ 432291431Sdumbbell __u64 offset; 433235783Skib /** Length of data to write */ 434291431Sdumbbell __u64 size; 435296548Sdumbbell /** 436296548Sdumbbell * Pointer to read the data from. 437296548Sdumbbell * 438296548Sdumbbell * This is a fixed-size type for 32/64 compatibility. 439296548Sdumbbell */ 440296548Sdumbbell __u64 data_ptr; 441235783Skib}; 442235783Skib 443235783Skibstruct drm_i915_gem_mmap { 444235783Skib /** Handle for the object being mapped. */ 445291431Sdumbbell __u32 handle; 446291431Sdumbbell __u32 pad; 447235783Skib /** Offset in the object to map. */ 448291431Sdumbbell __u64 offset; 449235783Skib /** 450235783Skib * Length of data to map. 451235783Skib * 452235783Skib * The value will be page-aligned. 453235783Skib */ 454291431Sdumbbell __u64 size; 455296548Sdumbbell /** 456296548Sdumbbell * Returned pointer the data was mapped at. 457296548Sdumbbell * 458296548Sdumbbell * This is a fixed-size type for 32/64 compatibility. 459296548Sdumbbell */ 460296548Sdumbbell __u64 addr_ptr; 461235783Skib}; 462235783Skib 463235783Skibstruct drm_i915_gem_mmap_gtt { 464235783Skib /** Handle for the object being mapped. */ 465291431Sdumbbell __u32 handle; 466291431Sdumbbell __u32 pad; 467235783Skib /** 468235783Skib * Fake offset to use for subsequent mmap call 469235783Skib * 470235783Skib * This is a fixed-size type for 32/64 compatibility. 471235783Skib */ 472291431Sdumbbell __u64 offset; 473235783Skib}; 474235783Skib 475235783Skibstruct drm_i915_gem_set_domain { 476235783Skib /** Handle for the object */ 477291431Sdumbbell __u32 handle; 478235783Skib 479235783Skib /** New read domains */ 480291431Sdumbbell __u32 read_domains; 481235783Skib 482235783Skib /** New write domain */ 483291431Sdumbbell __u32 write_domain; 484235783Skib}; 485235783Skib 486235783Skibstruct drm_i915_gem_sw_finish { 487235783Skib /** Handle for the object */ 488291431Sdumbbell __u32 handle; 489235783Skib}; 490235783Skib 491235783Skibstruct drm_i915_gem_relocation_entry { 492235783Skib /** 493235783Skib * Handle of the buffer being pointed to by this relocation entry. 494235783Skib * 495235783Skib * It's appealing to make this be an index into the mm_validate_entry 496235783Skib * list to refer to the buffer, but this allows the driver to create 497235783Skib * a relocation list for state buffers and not re-write it per 498235783Skib * exec using the buffer. 499235783Skib */ 500291431Sdumbbell __u32 target_handle; 501235783Skib 502235783Skib /** 503235783Skib * Value to be added to the offset of the target buffer to make up 504235783Skib * the relocation entry. 505235783Skib */ 506291431Sdumbbell __u32 delta; 507235783Skib 508235783Skib /** Offset in the buffer the relocation entry will be written into */ 509291431Sdumbbell __u64 offset; 510235783Skib 511235783Skib /** 512235783Skib * Offset value of the target buffer that the relocation entry was last 513235783Skib * written as. 514235783Skib * 515235783Skib * If the buffer has the same offset as last time, we can skip syncing 516235783Skib * and writing the relocation. This value is written back out by 517235783Skib * the execbuffer ioctl when the relocation is written. 518235783Skib */ 519291431Sdumbbell __u64 presumed_offset; 520235783Skib 521235783Skib /** 522235783Skib * Target memory domains read by this operation. 523235783Skib */ 524291431Sdumbbell __u32 read_domains; 525235783Skib 526235783Skib /** 527235783Skib * Target memory domains written by this operation. 528235783Skib * 529235783Skib * Note that only one domain may be written by the whole 530235783Skib * execbuffer operation, so that where there are conflicts, 531235783Skib * the application will get -EINVAL back. 532235783Skib */ 533291431Sdumbbell __u32 write_domain; 534235783Skib}; 535235783Skib 536235783Skib/** @{ 537235783Skib * Intel memory domains 538235783Skib * 539235783Skib * Most of these just align with the various caches in 540235783Skib * the system and are used to flush and invalidate as 541235783Skib * objects end up cached in different domains. 542235783Skib */ 543235783Skib/** CPU cache */ 544235783Skib#define I915_GEM_DOMAIN_CPU 0x00000001 545235783Skib/** Render cache, used by 2D and 3D drawing */ 546235783Skib#define I915_GEM_DOMAIN_RENDER 0x00000002 547235783Skib/** Sampler cache, used by texture engine */ 548235783Skib#define I915_GEM_DOMAIN_SAMPLER 0x00000004 549235783Skib/** Command queue, used to load batch buffers */ 550235783Skib#define I915_GEM_DOMAIN_COMMAND 0x00000008 551235783Skib/** Instruction cache, used by shader programs */ 552235783Skib#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 553235783Skib/** Vertex address cache */ 554235783Skib#define I915_GEM_DOMAIN_VERTEX 0x00000020 555235783Skib/** GTT domain - aperture and scanout */ 556235783Skib#define I915_GEM_DOMAIN_GTT 0x00000040 557235783Skib/** @} */ 558235783Skib 559235783Skibstruct drm_i915_gem_exec_object { 560235783Skib /** 561235783Skib * User's handle for a buffer to be bound into the GTT for this 562235783Skib * operation. 563235783Skib */ 564291431Sdumbbell __u32 handle; 565235783Skib 566235783Skib /** Number of relocations to be performed on this buffer */ 567291431Sdumbbell __u32 relocation_count; 568235783Skib /** 569235783Skib * Pointer to array of struct drm_i915_gem_relocation_entry containing 570235783Skib * the relocations to be performed in this buffer. 571235783Skib */ 572291431Sdumbbell __u64 relocs_ptr; 573235783Skib 574235783Skib /** Required alignment in graphics aperture */ 575291431Sdumbbell __u64 alignment; 576235783Skib 577235783Skib /** 578235783Skib * Returned value of the updated offset of the object, for future 579235783Skib * presumed_offset writes. 580235783Skib */ 581291431Sdumbbell __u64 offset; 582235783Skib}; 583235783Skib 584235783Skibstruct drm_i915_gem_execbuffer { 585235783Skib /** 586235783Skib * List of buffers to be validated with their relocations to be 587235783Skib * performend on them. 588235783Skib * 589235783Skib * This is a pointer to an array of struct drm_i915_gem_validate_entry. 590235783Skib * 591235783Skib * These buffers must be listed in an order such that all relocations 592235783Skib * a buffer is performing refer to buffers that have already appeared 593235783Skib * in the validate list. 594235783Skib */ 595291431Sdumbbell __u64 buffers_ptr; 596291431Sdumbbell __u32 buffer_count; 597235783Skib 598235783Skib /** Offset in the batchbuffer to start execution from. */ 599291431Sdumbbell __u32 batch_start_offset; 600235783Skib /** Bytes used in batchbuffer from batch_start_offset */ 601291431Sdumbbell __u32 batch_len; 602291431Sdumbbell __u32 DR1; 603291431Sdumbbell __u32 DR4; 604291431Sdumbbell __u32 num_cliprects; 605296548Sdumbbell /** This is a struct drm_clip_rect *cliprects */ 606296548Sdumbbell __u64 cliprects_ptr; 607235783Skib}; 608235783Skib 609235783Skibstruct drm_i915_gem_exec_object2 { 610235783Skib /** 611235783Skib * User's handle for a buffer to be bound into the GTT for this 612235783Skib * operation. 613235783Skib */ 614291431Sdumbbell __u32 handle; 615235783Skib 616235783Skib /** Number of relocations to be performed on this buffer */ 617291431Sdumbbell __u32 relocation_count; 618235783Skib /** 619235783Skib * Pointer to array of struct drm_i915_gem_relocation_entry containing 620235783Skib * the relocations to be performed in this buffer. 621235783Skib */ 622291431Sdumbbell __u64 relocs_ptr; 623235783Skib 624235783Skib /** Required alignment in graphics aperture */ 625291431Sdumbbell __u64 alignment; 626235783Skib 627235783Skib /** 628235783Skib * Returned value of the updated offset of the object, for future 629235783Skib * presumed_offset writes. 630235783Skib */ 631291431Sdumbbell __u64 offset; 632235783Skib 633235783Skib#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 634291431Sdumbbell __u64 flags; 635296548Sdumbbell __u64 rsvd1; 636291431Sdumbbell __u64 rsvd2; 637235783Skib}; 638235783Skib 639235783Skibstruct drm_i915_gem_execbuffer2 { 640235783Skib /** 641235783Skib * List of gem_exec_object2 structs 642235783Skib */ 643291431Sdumbbell __u64 buffers_ptr; 644291431Sdumbbell __u32 buffer_count; 645235783Skib 646235783Skib /** Offset in the batchbuffer to start execution from. */ 647291431Sdumbbell __u32 batch_start_offset; 648235783Skib /** Bytes used in batchbuffer from batch_start_offset */ 649291431Sdumbbell __u32 batch_len; 650291431Sdumbbell __u32 DR1; 651291431Sdumbbell __u32 DR4; 652291431Sdumbbell __u32 num_cliprects; 653235783Skib /** This is a struct drm_clip_rect *cliprects */ 654291431Sdumbbell __u64 cliprects_ptr; 655235783Skib#define I915_EXEC_RING_MASK (7<<0) 656235783Skib#define I915_EXEC_DEFAULT (0<<0) 657235783Skib#define I915_EXEC_RENDER (1<<0) 658235783Skib#define I915_EXEC_BSD (2<<0) 659235783Skib#define I915_EXEC_BLT (3<<0) 660235783Skib 661235783Skib/* Used for switching the constants addressing mode on gen4+ RENDER ring. 662235783Skib * Gen6+ only supports relative addressing to dynamic state (default) and 663235783Skib * absolute addressing. 664235783Skib * 665235783Skib * These flags are ignored for the BSD and BLT rings. 666235783Skib */ 667235783Skib#define I915_EXEC_CONSTANTS_MASK (3<<6) 668235783Skib#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 669235783Skib#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 670235783Skib#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 671291431Sdumbbell __u64 flags; 672296548Sdumbbell __u64 rsvd1; /* now used for context info */ 673291431Sdumbbell __u64 rsvd2; 674235783Skib}; 675235783Skib 676235783Skib/** Resets the SO write offset registers for transform feedback on gen7. */ 677235783Skib#define I915_EXEC_GEN7_SOL_RESET (1<<8) 678235783Skib 679296548Sdumbbell/** Request a privileged ("secure") batch buffer. Note only available for 680296548Sdumbbell * DRM_ROOT_ONLY | DRM_MASTER processes. 681296548Sdumbbell */ 682296548Sdumbbell#define I915_EXEC_SECURE (1<<9) 683296548Sdumbbell 684296548Sdumbbell/** Inform the kernel that the batch is and will always be pinned. This 685296548Sdumbbell * negates the requirement for a workaround to be performed to avoid 686296548Sdumbbell * an incoherent CS (such as can be found on 830/845). If this flag is 687296548Sdumbbell * not passed, the kernel will endeavour to make sure the batch is 688296548Sdumbbell * coherent with the CS before execution. If this flag is passed, 689296548Sdumbbell * userspace assumes the responsibility for ensuring the same. 690296548Sdumbbell */ 691296548Sdumbbell#define I915_EXEC_IS_PINNED (1<<10) 692296548Sdumbbell 693271705Sdumbbell#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 694271705Sdumbbell#define i915_execbuffer2_set_context_id(eb2, context) \ 695271705Sdumbbell (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 696271705Sdumbbell#define i915_execbuffer2_get_context_id(eb2) \ 697271705Sdumbbell ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 698271705Sdumbbell 699235783Skibstruct drm_i915_gem_pin { 700235783Skib /** Handle of the buffer to be pinned. */ 701291431Sdumbbell __u32 handle; 702291431Sdumbbell __u32 pad; 703235783Skib 704235783Skib /** alignment required within the aperture */ 705291431Sdumbbell __u64 alignment; 706235783Skib 707235783Skib /** Returned GTT offset of the buffer. */ 708291431Sdumbbell __u64 offset; 709235783Skib}; 710235783Skib 711235783Skibstruct drm_i915_gem_unpin { 712235783Skib /** Handle of the buffer to be unpinned. */ 713291431Sdumbbell __u32 handle; 714291431Sdumbbell __u32 pad; 715235783Skib}; 716235783Skib 717235783Skibstruct drm_i915_gem_busy { 718235783Skib /** Handle of the buffer to check for busy */ 719291431Sdumbbell __u32 handle; 720235783Skib 721296548Sdumbbell /** Return busy status (1 if busy, 0 if idle). 722296548Sdumbbell * The high word is used to indicate on which rings the object 723296548Sdumbbell * currently resides: 724296548Sdumbbell * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 725296548Sdumbbell */ 726291431Sdumbbell __u32 busy; 727235783Skib}; 728235783Skib 729296548Sdumbbell#define I915_CACHING_NONE 0 730296548Sdumbbell#define I915_CACHING_CACHED 1 731296548Sdumbbell 732296548Sdumbbellstruct drm_i915_gem_caching { 733296548Sdumbbell /** 734296548Sdumbbell * Handle of the buffer to set/get the caching level of. */ 735296548Sdumbbell __u32 handle; 736296548Sdumbbell 737296548Sdumbbell /** 738298955Spfg * Caching level to apply or return value 739296548Sdumbbell * 740296548Sdumbbell * bits0-15 are for generic caching control (i.e. the above defined 741296548Sdumbbell * values). bits16-31 are reserved for platform-specific variations 742296548Sdumbbell * (e.g. l3$ caching on gen7). */ 743296548Sdumbbell __u32 caching; 744296548Sdumbbell}; 745296548Sdumbbell 746235783Skib#define I915_TILING_NONE 0 747235783Skib#define I915_TILING_X 1 748235783Skib#define I915_TILING_Y 2 749235783Skib 750235783Skib#define I915_BIT_6_SWIZZLE_NONE 0 751235783Skib#define I915_BIT_6_SWIZZLE_9 1 752235783Skib#define I915_BIT_6_SWIZZLE_9_10 2 753235783Skib#define I915_BIT_6_SWIZZLE_9_11 3 754235783Skib#define I915_BIT_6_SWIZZLE_9_10_11 4 755235783Skib/* Not seen by userland */ 756235783Skib#define I915_BIT_6_SWIZZLE_UNKNOWN 5 757235783Skib/* Seen by userland. */ 758235783Skib#define I915_BIT_6_SWIZZLE_9_17 6 759235783Skib#define I915_BIT_6_SWIZZLE_9_10_17 7 760235783Skib 761235783Skibstruct drm_i915_gem_set_tiling { 762235783Skib /** Handle of the buffer to have its tiling state updated */ 763291431Sdumbbell __u32 handle; 764235783Skib 765235783Skib /** 766235783Skib * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 767235783Skib * I915_TILING_Y). 768235783Skib * 769235783Skib * This value is to be set on request, and will be updated by the 770235783Skib * kernel on successful return with the actual chosen tiling layout. 771235783Skib * 772235783Skib * The tiling mode may be demoted to I915_TILING_NONE when the system 773235783Skib * has bit 6 swizzling that can't be managed correctly by GEM. 774235783Skib * 775235783Skib * Buffer contents become undefined when changing tiling_mode. 776235783Skib */ 777291431Sdumbbell __u32 tiling_mode; 778235783Skib 779235783Skib /** 780235783Skib * Stride in bytes for the object when in I915_TILING_X or 781235783Skib * I915_TILING_Y. 782235783Skib */ 783291431Sdumbbell __u32 stride; 784235783Skib 785235783Skib /** 786235783Skib * Returned address bit 6 swizzling required for CPU access through 787235783Skib * mmap mapping. 788235783Skib */ 789291431Sdumbbell __u32 swizzle_mode; 790235783Skib}; 791235783Skib 792235783Skibstruct drm_i915_gem_get_tiling { 793235783Skib /** Handle of the buffer to get tiling state for. */ 794291431Sdumbbell __u32 handle; 795235783Skib 796235783Skib /** 797235783Skib * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 798235783Skib * I915_TILING_Y). 799235783Skib */ 800291431Sdumbbell __u32 tiling_mode; 801235783Skib 802235783Skib /** 803235783Skib * Returned address bit 6 swizzling required for CPU access through 804235783Skib * mmap mapping. 805235783Skib */ 806291431Sdumbbell __u32 swizzle_mode; 807235783Skib}; 808235783Skib 809235783Skibstruct drm_i915_gem_get_aperture { 810235783Skib /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 811291431Sdumbbell __u64 aper_size; 812235783Skib 813235783Skib /** 814235783Skib * Available space in the aperture used by i915_gem_execbuffer, in 815235783Skib * bytes 816235783Skib */ 817291431Sdumbbell __u64 aper_available_size; 818235783Skib}; 819235783Skib 820235783Skibstruct drm_i915_get_pipe_from_crtc_id { 821291431Sdumbbell /** ID of CRTC being requested **/ 822291431Sdumbbell __u32 crtc_id; 823235783Skib 824291431Sdumbbell /** pipe of requested CRTC **/ 825291431Sdumbbell __u32 pipe; 826235783Skib}; 827235783Skib 828235783Skib#define I915_MADV_WILLNEED 0 829235783Skib#define I915_MADV_DONTNEED 1 830296548Sdumbbell#define __I915_MADV_PURGED 2 /* internal state */ 831235783Skib 832235783Skibstruct drm_i915_gem_madvise { 833235783Skib /** Handle of the buffer to change the backing store advice */ 834291431Sdumbbell __u32 handle; 835235783Skib 836235783Skib /* Advice: either the buffer will be needed again in the near future, 837235783Skib * or wont be and could be discarded under memory pressure. 838235783Skib */ 839291431Sdumbbell __u32 madv; 840235783Skib 841235783Skib /** Whether the backing store still exists. */ 842291431Sdumbbell __u32 retained; 843235783Skib}; 844235783Skib 845296548Sdumbbell/* flags */ 846235783Skib#define I915_OVERLAY_TYPE_MASK 0xff 847235783Skib#define I915_OVERLAY_YUV_PLANAR 0x01 848235783Skib#define I915_OVERLAY_YUV_PACKED 0x02 849235783Skib#define I915_OVERLAY_RGB 0x03 850235783Skib 851235783Skib#define I915_OVERLAY_DEPTH_MASK 0xff00 852235783Skib#define I915_OVERLAY_RGB24 0x1000 853235783Skib#define I915_OVERLAY_RGB16 0x2000 854235783Skib#define I915_OVERLAY_RGB15 0x3000 855235783Skib#define I915_OVERLAY_YUV422 0x0100 856235783Skib#define I915_OVERLAY_YUV411 0x0200 857235783Skib#define I915_OVERLAY_YUV420 0x0300 858235783Skib#define I915_OVERLAY_YUV410 0x0400 859235783Skib 860235783Skib#define I915_OVERLAY_SWAP_MASK 0xff0000 861235783Skib#define I915_OVERLAY_NO_SWAP 0x000000 862235783Skib#define I915_OVERLAY_UV_SWAP 0x010000 863235783Skib#define I915_OVERLAY_Y_SWAP 0x020000 864235783Skib#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 865235783Skib 866235783Skib#define I915_OVERLAY_FLAGS_MASK 0xff000000 867235783Skib#define I915_OVERLAY_ENABLE 0x01000000 868235783Skib 869235783Skibstruct drm_intel_overlay_put_image { 870235783Skib /* various flags and src format description */ 871291431Sdumbbell __u32 flags; 872235783Skib /* source picture description */ 873291431Sdumbbell __u32 bo_handle; 874235783Skib /* stride values and offsets are in bytes, buffer relative */ 875291431Sdumbbell __u16 stride_Y; /* stride for packed formats */ 876291431Sdumbbell __u16 stride_UV; 877291431Sdumbbell __u32 offset_Y; /* offset for packet formats */ 878291431Sdumbbell __u32 offset_U; 879291431Sdumbbell __u32 offset_V; 880235783Skib /* in pixels */ 881291431Sdumbbell __u16 src_width; 882291431Sdumbbell __u16 src_height; 883235783Skib /* to compensate the scaling factors for partially covered surfaces */ 884291431Sdumbbell __u16 src_scan_width; 885291431Sdumbbell __u16 src_scan_height; 886235783Skib /* output crtc description */ 887291431Sdumbbell __u32 crtc_id; 888291431Sdumbbell __u16 dst_x; 889291431Sdumbbell __u16 dst_y; 890291431Sdumbbell __u16 dst_width; 891291431Sdumbbell __u16 dst_height; 892235783Skib}; 893235783Skib 894235783Skib/* flags */ 895235783Skib#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 896235783Skib#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 897235783Skibstruct drm_intel_overlay_attrs { 898291431Sdumbbell __u32 flags; 899291431Sdumbbell __u32 color_key; 900291431Sdumbbell __s32 brightness; 901291431Sdumbbell __u32 contrast; 902291431Sdumbbell __u32 saturation; 903291431Sdumbbell __u32 gamma0; 904291431Sdumbbell __u32 gamma1; 905291431Sdumbbell __u32 gamma2; 906291431Sdumbbell __u32 gamma3; 907291431Sdumbbell __u32 gamma4; 908291431Sdumbbell __u32 gamma5; 909235783Skib}; 910235783Skib 911235783Skib/* 912235783Skib * Intel sprite handling 913235783Skib * 914235783Skib * Color keying works with a min/mask/max tuple. Both source and destination 915235783Skib * color keying is allowed. 916235783Skib * 917235783Skib * Source keying: 918235783Skib * Sprite pixels within the min & max values, masked against the color channels 919235783Skib * specified in the mask field, will be transparent. All other pixels will 920235783Skib * be displayed on top of the primary plane. For RGB surfaces, only the min 921235783Skib * and mask fields will be used; ranged compares are not allowed. 922235783Skib * 923235783Skib * Destination keying: 924235783Skib * Primary plane pixels that match the min value, masked against the color 925235783Skib * channels specified in the mask field, will be replaced by corresponding 926235783Skib * pixels from the sprite plane. 927235783Skib * 928235783Skib * Note that source & destination keying are exclusive; only one can be 929235783Skib * active on a given plane. 930235783Skib */ 931235783Skib 932235783Skib#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 933235783Skib#define I915_SET_COLORKEY_DESTINATION (1<<1) 934235783Skib#define I915_SET_COLORKEY_SOURCE (1<<2) 935235783Skibstruct drm_intel_sprite_colorkey { 936291431Sdumbbell __u32 plane_id; 937291431Sdumbbell __u32 min_value; 938291431Sdumbbell __u32 channel_mask; 939291431Sdumbbell __u32 max_value; 940291431Sdumbbell __u32 flags; 941235783Skib}; 942235783Skib 943296548Sdumbbellstruct drm_i915_gem_wait { 944296548Sdumbbell /** Handle of BO we shall wait on */ 945296548Sdumbbell __u32 bo_handle; 946296548Sdumbbell __u32 flags; 947296548Sdumbbell /** Number of nanoseconds to wait, Returns time remaining. */ 948296548Sdumbbell __s64 timeout_ns; 949296548Sdumbbell}; 950296548Sdumbbell 951271705Sdumbbellstruct drm_i915_gem_context_create { 952271705Sdumbbell /* output: id of new context*/ 953291431Sdumbbell __u32 ctx_id; 954291431Sdumbbell __u32 pad; 955271705Sdumbbell}; 956271705Sdumbbell 957271705Sdumbbellstruct drm_i915_gem_context_destroy { 958291431Sdumbbell __u32 ctx_id; 959291431Sdumbbell __u32 pad; 960271705Sdumbbell}; 961271705Sdumbbell 962296548Sdumbbellstruct drm_i915_reg_read { 963296548Sdumbbell __u64 offset; 964296548Sdumbbell __u64 val; /* Return value */ 965296548Sdumbbell}; 966296548Sdumbbell 967296548Sdumbbell/* For use by IPS driver */ 968296548Sdumbbellextern unsigned long i915_read_mch_val(void); 969296548Sdumbbellextern bool i915_gpu_raise(void); 970296548Sdumbbellextern bool i915_gpu_lower(void); 971296548Sdumbbellextern bool i915_gpu_busy(void); 972296548Sdumbbellextern bool i915_gpu_turbo_disable(void); 973296548Sdumbbell#endif /* _UAPI_I915_DRM_H_ */ 974