radeon_drv.h revision 182080
1152909Sanholt/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2152909Sanholt * 395584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 495584Sanholt * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 595584Sanholt * All rights reserved. 695584Sanholt * 795584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 895584Sanholt * copy of this software and associated documentation files (the "Software"), 995584Sanholt * to deal in the Software without restriction, including without limitation 1095584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1195584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1295584Sanholt * Software is furnished to do so, subject to the following conditions: 1395584Sanholt * 1495584Sanholt * The above copyright notice and this permission notice (including the next 1595584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1695584Sanholt * Software. 1795584Sanholt * 1895584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1995584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2095584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2195584Sanholt * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2295584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2395584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2495584Sanholt * DEALINGS IN THE SOFTWARE. 2595584Sanholt * 2695584Sanholt * Authors: 2795584Sanholt * Kevin E. Martin <martin@valinux.com> 2895584Sanholt * Gareth Hughes <gareth@valinux.com> 2995584Sanholt */ 3095584Sanholt 31152909Sanholt#include <sys/cdefs.h> 32152909Sanholt__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 182080 2008-08-23 20:59:12Z rnoland $"); 33152909Sanholt 3495584Sanholt#ifndef __RADEON_DRV_H__ 3595584Sanholt#define __RADEON_DRV_H__ 3695584Sanholt 37145132Sanholt/* General customization: 38145132Sanholt */ 39145132Sanholt 40145132Sanholt#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41145132Sanholt 42145132Sanholt#define DRIVER_NAME "radeon" 43145132Sanholt#define DRIVER_DESC "ATI Radeon" 44182080Srnoland#define DRIVER_DATE "20080613" 45145132Sanholt 46145132Sanholt/* Interface history: 47145132Sanholt * 48145132Sanholt * 1.1 - ?? 49145132Sanholt * 1.2 - Add vertex2 ioctl (keith) 50145132Sanholt * - Add stencil capability to clear ioctl (gareth, keith) 51145132Sanholt * - Increase MAX_TEXTURE_LEVELS (brian) 52145132Sanholt * 1.3 - Add cmdbuf ioctl (keith) 53145132Sanholt * - Add support for new radeon packets (keith) 54145132Sanholt * - Add getparam ioctl (keith) 55145132Sanholt * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56145132Sanholt * 1.4 - Add scratch registers to get_param ioctl. 57145132Sanholt * 1.5 - Add r200 packets to cmdbuf ioctl 58145132Sanholt * - Add r200 function to init ioctl 59145132Sanholt * - Add 'scalar2' instruction to cmdbuf 60145132Sanholt * 1.6 - Add static GART memory manager 61145132Sanholt * Add irq handler (won't be turned on unless X server knows to) 62145132Sanholt * Add irq ioctls and irq_active getparam. 63145132Sanholt * Add wait command for cmdbuf ioctl 64145132Sanholt * Add GART offset query for getparam 65145132Sanholt * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66145132Sanholt * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67145132Sanholt * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68145132Sanholt * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69145132Sanholt * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70145132Sanholt * Add 'GET' queries for starting additional clients on different VT's. 71145132Sanholt * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72145132Sanholt * Add texture rectangle support for r100. 73145132Sanholt * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74145132Sanholt * clients use to tell the DRM where they think the framebuffer is 75145132Sanholt * located in the card's address space 76145132Sanholt * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77145132Sanholt * and GL_EXT_blend_[func|equation]_separate on r200 78145132Sanholt * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79145132Sanholt * (No 3D support yet - just microcode loading). 80145132Sanholt * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81145132Sanholt * - Add hyperz support, add hyperz flags to clear ioctl. 82145132Sanholt * 1.14- Add support for color tiling 83145132Sanholt * - Add R100/R200 surface allocation/free support 84145132Sanholt * 1.15- Add support for texture micro tiling 85145132Sanholt * - Add support for r100 cube maps 86145132Sanholt * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87145132Sanholt * texture filtering on r200 88152909Sanholt * 1.17- Add initial support for R300 (3D). 89157617Sanholt * 1.18- Add support for GL_ATI_fragment_shader, new packets 90157617Sanholt * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91157617Sanholt * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92157617Sanholt * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93152909Sanholt * 1.19- Add support for gart table in FB memory and PCIE r300 94157617Sanholt * 1.20- Add support for r300 texrect 95157617Sanholt * 1.21- Add support for card type getparam 96157617Sanholt * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97157617Sanholt * 1.23- Add new radeon memory map work from benh 98157617Sanholt * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99162132Sanholt * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100162132Sanholt * new packet type) 101182080Srnoland * 1.26- Add support for variable size PCI(E) gart aperture 102182080Srnoland * 1.27- Add support for IGP GART 103182080Srnoland * 1.28- Add support for VBL on CRTC2 104182080Srnoland * 1.29- R500 3D cmd buffer support 105145132Sanholt */ 106145132Sanholt 107145132Sanholt#define DRIVER_MAJOR 1 108182080Srnoland#define DRIVER_MINOR 29 109145132Sanholt#define DRIVER_PATCHLEVEL 0 110145132Sanholt 111157617Sanholt/* 112157617Sanholt * Radeon chip families 113157617Sanholt */ 114145132Sanholtenum radeon_family { 115145132Sanholt CHIP_R100, 116157617Sanholt CHIP_RV100, 117145132Sanholt CHIP_RS100, 118152909Sanholt CHIP_RV200, 119157617Sanholt CHIP_RS200, 120145132Sanholt CHIP_R200, 121145132Sanholt CHIP_RV250, 122157617Sanholt CHIP_RS300, 123145132Sanholt CHIP_RV280, 124145132Sanholt CHIP_R300, 125148211Sanholt CHIP_R350, 126145132Sanholt CHIP_RV350, 127157617Sanholt CHIP_RV380, 128148211Sanholt CHIP_R420, 129157617Sanholt CHIP_RV410, 130157617Sanholt CHIP_RS400, 131182080Srnoland CHIP_RS480, 132182080Srnoland CHIP_RS690, 133182080Srnoland CHIP_RV515, 134182080Srnoland CHIP_R520, 135182080Srnoland CHIP_RV530, 136182080Srnoland CHIP_RV560, 137182080Srnoland CHIP_RV570, 138182080Srnoland CHIP_R580, 139145132Sanholt CHIP_LAST, 140145132Sanholt}; 141145132Sanholt 142145132Sanholt/* 143145132Sanholt * Chip flags 144145132Sanholt */ 145145132Sanholtenum radeon_chip_flags { 146182080Srnoland RADEON_FAMILY_MASK = 0x0000ffffUL, 147182080Srnoland RADEON_FLAGS_MASK = 0xffff0000UL, 148182080Srnoland RADEON_IS_MOBILITY = 0x00010000UL, 149182080Srnoland RADEON_IS_IGP = 0x00020000UL, 150182080Srnoland RADEON_SINGLE_CRTC = 0x00040000UL, 151182080Srnoland RADEON_IS_AGP = 0x00080000UL, 152182080Srnoland RADEON_HAS_HIERZ = 0x00100000UL, 153182080Srnoland RADEON_IS_PCIE = 0x00200000UL, 154182080Srnoland RADEON_NEW_MEMMAP = 0x00400000UL, 155182080Srnoland RADEON_IS_PCI = 0x00800000UL, 156182080Srnoland RADEON_IS_IGPGART = 0x01000000UL, 157145132Sanholt}; 158145132Sanholt 159157617Sanholt#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 160157617Sanholt DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) 161113995Sanholt#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 162112015Sanholt 16395584Sanholttypedef struct drm_radeon_freelist { 164145132Sanholt unsigned int age; 165182080Srnoland struct drm_buf *buf; 166145132Sanholt struct drm_radeon_freelist *next; 167145132Sanholt struct drm_radeon_freelist *prev; 16895584Sanholt} drm_radeon_freelist_t; 16995584Sanholt 17095584Sanholttypedef struct drm_radeon_ring_buffer { 17195584Sanholt u32 *start; 17295584Sanholt u32 *end; 173182080Srnoland int size; /* Double Words */ 174182080Srnoland int size_l2qw; /* log2 Quad Words */ 17595584Sanholt 176182080Srnoland int rptr_update; /* Double Words */ 177182080Srnoland int rptr_update_l2qw; /* log2 Quad Words */ 178182080Srnoland 179182080Srnoland int fetch_size; /* Double Words */ 180182080Srnoland int fetch_size_l2ow; /* log2 Oct Words */ 181182080Srnoland 18295584Sanholt u32 tail; 18395584Sanholt u32 tail_mask; 18495584Sanholt int space; 18595584Sanholt 18695584Sanholt int high_mark; 18795584Sanholt} drm_radeon_ring_buffer_t; 18895584Sanholt 18995584Sanholttypedef struct drm_radeon_depth_clear_t { 19095584Sanholt u32 rb3d_cntl; 19195584Sanholt u32 rb3d_zstencilcntl; 19295584Sanholt u32 se_cntl; 19395584Sanholt} drm_radeon_depth_clear_t; 19495584Sanholt 195145132Sanholtstruct drm_radeon_driver_file_fields { 196145132Sanholt int64_t radeon_fb_delta; 197145132Sanholt}; 198112015Sanholt 199112015Sanholtstruct mem_block { 200112015Sanholt struct mem_block *next; 201112015Sanholt struct mem_block *prev; 202112015Sanholt int start; 203112015Sanholt int size; 204182080Srnoland struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 205112015Sanholt}; 206112015Sanholt 207145132Sanholtstruct radeon_surface { 208145132Sanholt int refcount; 209145132Sanholt u32 lower; 210145132Sanholt u32 upper; 211145132Sanholt u32 flags; 212145132Sanholt}; 213145132Sanholt 214145132Sanholtstruct radeon_virt_surface { 215145132Sanholt int surface_index; 216145132Sanholt u32 lower; 217145132Sanholt u32 upper; 218145132Sanholt u32 flags; 219182080Srnoland struct drm_file *file_priv; 220145132Sanholt}; 221145132Sanholt 222182080Srnoland#define RADEON_FLUSH_EMITED (1 < 0) 223182080Srnoland#define RADEON_PURGE_EMITED (1 < 1) 224182080Srnoland 22595584Sanholttypedef struct drm_radeon_private { 226145132Sanholt 22795584Sanholt drm_radeon_ring_buffer_t ring; 22895584Sanholt drm_radeon_sarea_t *sarea_priv; 22995584Sanholt 230122580Sanholt u32 fb_location; 231157617Sanholt u32 fb_size; 232157617Sanholt int new_memmap; 233122580Sanholt 234119895Sanholt int gart_size; 235119895Sanholt u32 gart_vm_start; 236119895Sanholt unsigned long gart_buffers_offset; 23795584Sanholt 23895584Sanholt int cp_mode; 23995584Sanholt int cp_running; 24095584Sanholt 241145132Sanholt drm_radeon_freelist_t *head; 242145132Sanholt drm_radeon_freelist_t *tail; 24395584Sanholt int last_buf; 24495584Sanholt volatile u32 *scratch; 245112015Sanholt int writeback_works; 24695584Sanholt 24795584Sanholt int usec_timeout; 248112015Sanholt 249112015Sanholt struct { 250112015Sanholt u32 boxes; 251112015Sanholt int freelist_timeouts; 252112015Sanholt int freelist_loops; 253112015Sanholt int requested_bufs; 254112015Sanholt int last_frame_reads; 255112015Sanholt int last_clear_reads; 256112015Sanholt int clears; 257112015Sanholt int texture_uploads; 258112015Sanholt } stats; 25995584Sanholt 260112015Sanholt int do_boxes; 26195584Sanholt int page_flipping; 26295584Sanholt 26395584Sanholt u32 color_fmt; 26495584Sanholt unsigned int front_offset; 26595584Sanholt unsigned int front_pitch; 26695584Sanholt unsigned int back_offset; 26795584Sanholt unsigned int back_pitch; 26895584Sanholt 26995584Sanholt u32 depth_fmt; 27095584Sanholt unsigned int depth_offset; 27195584Sanholt unsigned int depth_pitch; 27295584Sanholt 27395584Sanholt u32 front_pitch_offset; 27495584Sanholt u32 back_pitch_offset; 27595584Sanholt u32 depth_pitch_offset; 27695584Sanholt 27795584Sanholt drm_radeon_depth_clear_t depth_clear; 278145132Sanholt 279113995Sanholt unsigned long ring_offset; 280113995Sanholt unsigned long ring_rptr_offset; 281113995Sanholt unsigned long buffers_offset; 282119895Sanholt unsigned long gart_textures_offset; 28395584Sanholt 284112015Sanholt drm_local_map_t *sarea; 285112015Sanholt drm_local_map_t *mmio; 286112015Sanholt drm_local_map_t *cp_ring; 287112015Sanholt drm_local_map_t *ring_rptr; 288119895Sanholt drm_local_map_t *gart_textures; 289112015Sanholt 290119895Sanholt struct mem_block *gart_heap; 291112015Sanholt struct mem_block *fb_heap; 292112015Sanholt 293112015Sanholt /* SW interrupt */ 294145132Sanholt wait_queue_head_t swi_queue; 295145132Sanholt atomic_t swi_emitted; 296182080Srnoland int vblank_crtc; 297182080Srnoland uint32_t irq_enable_reg; 298182080Srnoland int irq_enabled; 299182080Srnoland uint32_t r500_disp_irq_reg; 300112015Sanholt 301145132Sanholt struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 302182080Srnoland struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 303152909Sanholt 304152909Sanholt unsigned long pcigart_offset; 305182080Srnoland unsigned int pcigart_offset_set; 306182080Srnoland struct drm_ati_pcigart_info gart_info; 307157617Sanholt 308157617Sanholt u32 scratch_ages[5]; 309157617Sanholt 310182080Srnoland unsigned int crtc_last_cnt; 311182080Srnoland unsigned int crtc2_last_cnt; 312182080Srnoland 313145132Sanholt /* starting from here on, data is preserved accross an open */ 314145132Sanholt uint32_t flags; /* see radeon_chip_flags */ 315182080Srnoland unsigned long fb_aper_offset; 316145132Sanholt 317182080Srnoland int num_gb_pipes; 318182080Srnoland int track_flush; 319182080Srnoland uint32_t chip_family; /* extract from flags */ 32095584Sanholt} drm_radeon_private_t; 32195584Sanholt 32295584Sanholttypedef struct drm_radeon_buf_priv { 32395584Sanholt u32 age; 32495584Sanholt} drm_radeon_buf_priv_t; 32595584Sanholt 326157617Sanholttypedef struct drm_radeon_kcmd_buffer { 327157617Sanholt int bufsz; 328157617Sanholt char *buf; 329157617Sanholt int nbox; 330182080Srnoland struct drm_clip_rect __user *boxes; 331157617Sanholt} drm_radeon_kcmd_buffer_t; 332157617Sanholt 333152909Sanholtextern int radeon_no_wb; 334182080Srnolandextern struct drm_ioctl_desc radeon_ioctls[]; 335152909Sanholtextern int radeon_max_ioctl; 336152909Sanholt 337182080Srnoland/* Check whether the given hardware address is inside the framebuffer or the 338182080Srnoland * GART area. 339182080Srnoland */ 340182080Srnolandstatic __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 341182080Srnoland u64 off) 342182080Srnoland{ 343182080Srnoland u32 fb_start = dev_priv->fb_location; 344182080Srnoland u32 fb_end = fb_start + dev_priv->fb_size - 1; 345182080Srnoland u32 gart_start = dev_priv->gart_vm_start; 346182080Srnoland u32 gart_end = gart_start + dev_priv->gart_size - 1; 347182080Srnoland 348182080Srnoland return ((off >= fb_start && off <= fb_end) || 349182080Srnoland (off >= gart_start && off <= gart_end)); 350182080Srnoland} 351182080Srnoland 35295584Sanholt /* radeon_cp.c */ 353182080Srnolandextern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 354182080Srnolandextern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 355182080Srnolandextern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 356182080Srnolandextern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 357182080Srnolandextern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 358182080Srnolandextern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 359182080Srnolandextern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 360182080Srnolandextern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 361182080Srnolandextern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 362182080Srnolandextern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 36395584Sanholt 364182080Srnolandextern void radeon_freelist_reset(struct drm_device * dev); 365182080Srnolandextern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 36695584Sanholt 367145132Sanholtextern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 36895584Sanholt 369145132Sanholtextern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 37095584Sanholt 371182080Srnolandextern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 372182080Srnolandextern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 373182080Srnolandextern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 374145132Sanholtextern void radeon_mem_takedown(struct mem_block **heap); 375182080Srnolandextern void radeon_mem_release(struct drm_file *file_priv, 376182080Srnoland struct mem_block *heap); 37795584Sanholt 378112015Sanholt /* radeon_irq.c */ 379182080Srnolandextern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 380182080Srnolandextern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 381182080Srnolandextern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 382112015Sanholt 383182080Srnolandextern void radeon_do_release(struct drm_device * dev); 384182080Srnolandextern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 385182080Srnolandextern int radeon_enable_vblank(struct drm_device *dev, int crtc); 386182080Srnolandextern void radeon_disable_vblank(struct drm_device *dev, int crtc); 387145132Sanholtextern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 388182080Srnolandextern void radeon_driver_irq_preinstall(struct drm_device * dev); 389182080Srnolandextern int radeon_driver_irq_postinstall(struct drm_device * dev); 390182080Srnolandextern void radeon_driver_irq_uninstall(struct drm_device * dev); 391182080Srnolandextern int radeon_vblank_crtc_get(struct drm_device *dev); 392182080Srnolandextern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 393112015Sanholt 394152909Sanholtextern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 395152909Sanholtextern int radeon_driver_unload(struct drm_device *dev); 396152909Sanholtextern int radeon_driver_firstopen(struct drm_device *dev); 397182080Srnolandextern void radeon_driver_preclose(struct drm_device * dev, 398182080Srnoland struct drm_file *file_priv); 399182080Srnolandextern void radeon_driver_postclose(struct drm_device * dev, 400182080Srnoland struct drm_file *file_priv); 401182080Srnolandextern void radeon_driver_lastclose(struct drm_device * dev); 402182080Srnolandextern int radeon_driver_open(struct drm_device * dev, 403182080Srnoland struct drm_file * file_priv); 404152909Sanholtextern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 405152909Sanholt unsigned long arg); 406152909Sanholt 407148211Sanholt/* r300_cmdbuf.c */ 408182080Srnolandextern void r300_init_reg_flags(struct drm_device *dev); 409148211Sanholt 410182080Srnolandextern int r300_do_cp_cmdbuf(struct drm_device *dev, 411182080Srnoland struct drm_file *file_priv, 412182080Srnoland drm_radeon_kcmd_buffer_t *cmdbuf); 413148211Sanholt 414112015Sanholt/* Flags for stats.boxes 415112015Sanholt */ 416112015Sanholt#define RADEON_BOX_DMA_IDLE 0x1 417112015Sanholt#define RADEON_BOX_RING_FULL 0x2 418112015Sanholt#define RADEON_BOX_FLIP 0x4 419112015Sanholt#define RADEON_BOX_WAIT_IDLE 0x8 420112015Sanholt#define RADEON_BOX_TEXTURE_LOAD 0x10 421112015Sanholt 42295584Sanholt/* Register definitions, register access macros and drmAddMap constants 42395584Sanholt * for Radeon kernel driver. 42495584Sanholt */ 425145132Sanholt#define RADEON_AGP_COMMAND 0x0f60 426145132Sanholt#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 427145132Sanholt# define RADEON_AGP_ENABLE (1<<8) 42895584Sanholt#define RADEON_AUX_SCISSOR_CNTL 0x26f0 42995584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 43095584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 43195584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 43295584Sanholt# define RADEON_SCISSOR_0_ENABLE (1 << 28) 43395584Sanholt# define RADEON_SCISSOR_1_ENABLE (1 << 29) 43495584Sanholt# define RADEON_SCISSOR_2_ENABLE (1 << 30) 43595584Sanholt 43695584Sanholt#define RADEON_BUS_CNTL 0x0030 43795584Sanholt# define RADEON_BUS_MASTER_DIS (1 << 6) 43895584Sanholt 43995584Sanholt#define RADEON_CLOCK_CNTL_DATA 0x000c 44095584Sanholt# define RADEON_PLL_WR_EN (1 << 7) 44195584Sanholt#define RADEON_CLOCK_CNTL_INDEX 0x0008 44295584Sanholt#define RADEON_CONFIG_APER_SIZE 0x0108 443157617Sanholt#define RADEON_CONFIG_MEMSIZE 0x00f8 44495584Sanholt#define RADEON_CRTC_OFFSET 0x0224 44595584Sanholt#define RADEON_CRTC_OFFSET_CNTL 0x0228 44695584Sanholt# define RADEON_CRTC_TILE_EN (1 << 15) 44795584Sanholt# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 448112015Sanholt#define RADEON_CRTC2_OFFSET 0x0324 449112015Sanholt#define RADEON_CRTC2_OFFSET_CNTL 0x0328 45095584Sanholt 451148211Sanholt#define RADEON_PCIE_INDEX 0x0030 452148211Sanholt#define RADEON_PCIE_DATA 0x0034 453148211Sanholt#define RADEON_PCIE_TX_GART_CNTL 0x10 454182080Srnoland# define RADEON_PCIE_TX_GART_EN (1 << 0) 455182080Srnoland# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 456182080Srnoland# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 457182080Srnoland# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 458182080Srnoland# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 459182080Srnoland# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 460182080Srnoland# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 461182080Srnoland# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 462148211Sanholt#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 463148211Sanholt#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 464182080Srnoland#define RADEON_PCIE_TX_GART_BASE 0x13 465148211Sanholt#define RADEON_PCIE_TX_GART_START_LO 0x14 466148211Sanholt#define RADEON_PCIE_TX_GART_START_HI 0x15 467148211Sanholt#define RADEON_PCIE_TX_GART_END_LO 0x16 468148211Sanholt#define RADEON_PCIE_TX_GART_END_HI 0x17 469148211Sanholt 470182080Srnoland#define RS480_NB_MC_INDEX 0x168 471182080Srnoland# define RS480_NB_MC_IND_WR_EN (1 << 8) 472182080Srnoland#define RS480_NB_MC_DATA 0x16c 473182080Srnoland 474182080Srnoland#define RS690_MC_INDEX 0x78 475182080Srnoland# define RS690_MC_INDEX_MASK 0x1ff 476182080Srnoland# define RS690_MC_INDEX_WR_EN (1 << 9) 477182080Srnoland# define RS690_MC_INDEX_WR_ACK 0x7f 478182080Srnoland#define RS690_MC_DATA 0x7c 479182080Srnoland 480182080Srnoland/* MC indirect registers */ 481182080Srnoland#define RS480_MC_MISC_CNTL 0x18 482182080Srnoland# define RS480_DISABLE_GTW (1 << 1) 483182080Srnoland/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 484182080Srnoland# define RS480_GART_INDEX_REG_EN (1 << 12) 485182080Srnoland# define RS690_BLOCK_GFX_D3_EN (1 << 14) 486182080Srnoland#define RS480_K8_FB_LOCATION 0x1e 487182080Srnoland#define RS480_GART_FEATURE_ID 0x2b 488182080Srnoland# define RS480_HANG_EN (1 << 11) 489182080Srnoland# define RS480_TLB_ENABLE (1 << 18) 490182080Srnoland# define RS480_P2P_ENABLE (1 << 19) 491182080Srnoland# define RS480_GTW_LAC_EN (1 << 25) 492182080Srnoland# define RS480_2LEVEL_GART (0 << 30) 493182080Srnoland# define RS480_1LEVEL_GART (1 << 30) 494182080Srnoland# define RS480_PDC_EN (1 << 31) 495182080Srnoland#define RS480_GART_BASE 0x2c 496182080Srnoland#define RS480_GART_CACHE_CNTRL 0x2e 497182080Srnoland# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 498182080Srnoland#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 499182080Srnoland# define RS480_GART_EN (1 << 0) 500182080Srnoland# define RS480_VA_SIZE_32MB (0 << 1) 501182080Srnoland# define RS480_VA_SIZE_64MB (1 << 1) 502182080Srnoland# define RS480_VA_SIZE_128MB (2 << 1) 503182080Srnoland# define RS480_VA_SIZE_256MB (3 << 1) 504182080Srnoland# define RS480_VA_SIZE_512MB (4 << 1) 505182080Srnoland# define RS480_VA_SIZE_1GB (5 << 1) 506182080Srnoland# define RS480_VA_SIZE_2GB (6 << 1) 507182080Srnoland#define RS480_AGP_MODE_CNTL 0x39 508182080Srnoland# define RS480_POST_GART_Q_SIZE (1 << 18) 509182080Srnoland# define RS480_NONGART_SNOOP (1 << 19) 510182080Srnoland# define RS480_AGP_RD_BUF_SIZE (1 << 20) 511182080Srnoland# define RS480_REQ_TYPE_SNOOP_SHIFT 22 512182080Srnoland# define RS480_REQ_TYPE_SNOOP_MASK 0x3 513182080Srnoland# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 514182080Srnoland#define RS480_MC_MISC_UMA_CNTL 0x5f 515182080Srnoland#define RS480_MC_MCLK_CNTL 0x7a 516182080Srnoland#define RS480_MC_UMA_DUALCH_CNTL 0x86 517182080Srnoland 518182080Srnoland#define RS690_MC_FB_LOCATION 0x100 519182080Srnoland#define RS690_MC_AGP_LOCATION 0x101 520182080Srnoland#define RS690_MC_AGP_BASE 0x102 521182080Srnoland#define RS690_MC_AGP_BASE_2 0x103 522182080Srnoland 523182080Srnoland#define R520_MC_IND_INDEX 0x70 524182080Srnoland#define R520_MC_IND_WR_EN (1 << 24) 525182080Srnoland#define R520_MC_IND_DATA 0x74 526182080Srnoland 527182080Srnoland#define RV515_MC_FB_LOCATION 0x01 528182080Srnoland#define RV515_MC_AGP_LOCATION 0x02 529182080Srnoland#define RV515_MC_AGP_BASE 0x03 530182080Srnoland#define RV515_MC_AGP_BASE_2 0x04 531182080Srnoland 532182080Srnoland#define R520_MC_FB_LOCATION 0x04 533182080Srnoland#define R520_MC_AGP_LOCATION 0x05 534182080Srnoland#define R520_MC_AGP_BASE 0x06 535182080Srnoland#define R520_MC_AGP_BASE_2 0x07 536182080Srnoland 537145132Sanholt#define RADEON_MPP_TB_CONFIG 0x01c0 538145132Sanholt#define RADEON_MEM_CNTL 0x0140 539145132Sanholt#define RADEON_MEM_SDRAM_MODE_REG 0x0158 540182080Srnoland#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 541182080Srnoland#define RS480_AGP_BASE_2 0x0164 542145132Sanholt#define RADEON_AGP_BASE 0x0170 543145132Sanholt 544182080Srnoland/* pipe config regs */ 545182080Srnoland#define R400_GB_PIPE_SELECT 0x402c 546182080Srnoland#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 547182080Srnoland#define R500_SU_REG_DEST 0x42c8 548182080Srnoland#define R300_GB_TILE_CONFIG 0x4018 549182080Srnoland# define R300_ENABLE_TILING (1 << 0) 550182080Srnoland# define R300_PIPE_COUNT_RV350 (0 << 1) 551182080Srnoland# define R300_PIPE_COUNT_R300 (3 << 1) 552182080Srnoland# define R300_PIPE_COUNT_R420_3P (6 << 1) 553182080Srnoland# define R300_PIPE_COUNT_R420 (7 << 1) 554182080Srnoland# define R300_TILE_SIZE_8 (0 << 4) 555182080Srnoland# define R300_TILE_SIZE_16 (1 << 4) 556182080Srnoland# define R300_TILE_SIZE_32 (2 << 4) 557182080Srnoland# define R300_SUBPIXEL_1_12 (0 << 16) 558182080Srnoland# define R300_SUBPIXEL_1_16 (1 << 16) 559182080Srnoland#define R300_DST_PIPE_CONFIG 0x170c 560182080Srnoland# define R300_PIPE_AUTO_CONFIG (1 << 31) 561182080Srnoland#define R300_RB2D_DSTCACHE_MODE 0x3428 562182080Srnoland# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 563182080Srnoland# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 564182080Srnoland 565122580Sanholt#define RADEON_RB3D_COLOROFFSET 0x1c40 56695584Sanholt#define RADEON_RB3D_COLORPITCH 0x1c48 56795584Sanholt 568182080Srnoland#define RADEON_SRC_X_Y 0x1590 569182080Srnoland 57095584Sanholt#define RADEON_DP_GUI_MASTER_CNTL 0x146c 57195584Sanholt# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 57295584Sanholt# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 57395584Sanholt# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 57495584Sanholt# define RADEON_GMC_BRUSH_NONE (15 << 4) 57595584Sanholt# define RADEON_GMC_DST_16BPP (4 << 8) 57695584Sanholt# define RADEON_GMC_DST_24BPP (5 << 8) 57795584Sanholt# define RADEON_GMC_DST_32BPP (6 << 8) 57895584Sanholt# define RADEON_GMC_DST_DATATYPE_SHIFT 8 57995584Sanholt# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 58095584Sanholt# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 58195584Sanholt# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 58295584Sanholt# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 58395584Sanholt# define RADEON_GMC_WR_MSK_DIS (1 << 30) 58495584Sanholt# define RADEON_ROP3_S 0x00cc0000 58595584Sanholt# define RADEON_ROP3_P 0x00f00000 58695584Sanholt#define RADEON_DP_WRITE_MASK 0x16cc 587182080Srnoland#define RADEON_SRC_PITCH_OFFSET 0x1428 58895584Sanholt#define RADEON_DST_PITCH_OFFSET 0x142c 58995584Sanholt#define RADEON_DST_PITCH_OFFSET_C 0x1c80 59095584Sanholt# define RADEON_DST_TILE_LINEAR (0 << 30) 59195584Sanholt# define RADEON_DST_TILE_MACRO (1 << 30) 59295584Sanholt# define RADEON_DST_TILE_MICRO (2 << 30) 59395584Sanholt# define RADEON_DST_TILE_BOTH (3 << 30) 59495584Sanholt 59595584Sanholt#define RADEON_SCRATCH_REG0 0x15e0 59695584Sanholt#define RADEON_SCRATCH_REG1 0x15e4 59795584Sanholt#define RADEON_SCRATCH_REG2 0x15e8 59895584Sanholt#define RADEON_SCRATCH_REG3 0x15ec 59995584Sanholt#define RADEON_SCRATCH_REG4 0x15f0 60095584Sanholt#define RADEON_SCRATCH_REG5 0x15f4 60195584Sanholt#define RADEON_SCRATCH_UMSK 0x0770 60295584Sanholt#define RADEON_SCRATCH_ADDR 0x0774 60395584Sanholt 604112015Sanholt#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 605112015Sanholt 606112015Sanholt#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 607112015Sanholt ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 608112015Sanholt : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 609112015Sanholt 610182080Srnoland#define RADEON_CRTC_CRNT_FRAME 0x0214 611182080Srnoland#define RADEON_CRTC2_CRNT_FRAME 0x0314 612182080Srnoland 613182080Srnoland#define RADEON_CRTC_STATUS 0x005c 614182080Srnoland#define RADEON_CRTC2_STATUS 0x03fc 615182080Srnoland 616112015Sanholt#define RADEON_GEN_INT_CNTL 0x0040 617112015Sanholt# define RADEON_CRTC_VBLANK_MASK (1 << 0) 618182080Srnoland# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 619112015Sanholt# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 620112015Sanholt# define RADEON_SW_INT_ENABLE (1 << 25) 621112015Sanholt 622112015Sanholt#define RADEON_GEN_INT_STATUS 0x0044 623112015Sanholt# define RADEON_CRTC_VBLANK_STAT (1 << 0) 624182080Srnoland# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 625182080Srnoland# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 626182080Srnoland# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 627112015Sanholt# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 628112015Sanholt# define RADEON_SW_INT_TEST (1 << 25) 629182080Srnoland# define RADEON_SW_INT_TEST_ACK (1 << 25) 630112015Sanholt# define RADEON_SW_INT_FIRE (1 << 26) 631182080Srnoland# define R500_DISPLAY_INT_STATUS (1 << 0) 632112015Sanholt 633182080Srnoland 63495584Sanholt#define RADEON_HOST_PATH_CNTL 0x0130 63595584Sanholt# define RADEON_HDP_SOFT_RESET (1 << 26) 63695584Sanholt# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 63795584Sanholt# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 63895584Sanholt 63995584Sanholt#define RADEON_ISYNC_CNTL 0x1724 64095584Sanholt# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 64195584Sanholt# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 64295584Sanholt# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 64395584Sanholt# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 64495584Sanholt# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 64595584Sanholt# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 64695584Sanholt 647112015Sanholt#define RADEON_RBBM_GUICNTL 0x172c 648112015Sanholt# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 649112015Sanholt# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 650112015Sanholt# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 651112015Sanholt# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 652112015Sanholt 65395584Sanholt#define RADEON_MC_AGP_LOCATION 0x014c 65495584Sanholt#define RADEON_MC_FB_LOCATION 0x0148 65595584Sanholt#define RADEON_MCLK_CNTL 0x0012 65695584Sanholt# define RADEON_FORCEON_MCLKA (1 << 16) 65795584Sanholt# define RADEON_FORCEON_MCLKB (1 << 17) 65895584Sanholt# define RADEON_FORCEON_YCLKA (1 << 18) 65995584Sanholt# define RADEON_FORCEON_YCLKB (1 << 19) 66095584Sanholt# define RADEON_FORCEON_MC (1 << 20) 66195584Sanholt# define RADEON_FORCEON_AIC (1 << 21) 66295584Sanholt 66395584Sanholt#define RADEON_PP_BORDER_COLOR_0 0x1d40 66495584Sanholt#define RADEON_PP_BORDER_COLOR_1 0x1d44 66595584Sanholt#define RADEON_PP_BORDER_COLOR_2 0x1d48 66695584Sanholt#define RADEON_PP_CNTL 0x1c38 66795584Sanholt# define RADEON_SCISSOR_ENABLE (1 << 1) 66895584Sanholt#define RADEON_PP_LUM_MATRIX 0x1d00 66995584Sanholt#define RADEON_PP_MISC 0x1c14 67095584Sanholt#define RADEON_PP_ROT_MATRIX_0 0x1d58 67195584Sanholt#define RADEON_PP_TXFILTER_0 0x1c54 672122580Sanholt#define RADEON_PP_TXOFFSET_0 0x1c5c 67395584Sanholt#define RADEON_PP_TXFILTER_1 0x1c6c 67495584Sanholt#define RADEON_PP_TXFILTER_2 0x1c84 67595584Sanholt 676182080Srnoland#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 677182080Srnoland#define R300_DSTCACHE_CTLSTAT 0x1714 678182080Srnoland# define R300_RB2D_DC_FLUSH (3 << 0) 679182080Srnoland# define R300_RB2D_DC_FREE (3 << 2) 680182080Srnoland# define R300_RB2D_DC_FLUSH_ALL 0xf 681182080Srnoland# define R300_RB2D_DC_BUSY (1 << 31) 68295584Sanholt#define RADEON_RB3D_CNTL 0x1c3c 68395584Sanholt# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 68495584Sanholt# define RADEON_PLANE_MASK_ENABLE (1 << 1) 68595584Sanholt# define RADEON_DITHER_ENABLE (1 << 2) 68695584Sanholt# define RADEON_ROUND_ENABLE (1 << 3) 68795584Sanholt# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 68895584Sanholt# define RADEON_DITHER_INIT (1 << 5) 68995584Sanholt# define RADEON_ROP_ENABLE (1 << 6) 69095584Sanholt# define RADEON_STENCIL_ENABLE (1 << 7) 69195584Sanholt# define RADEON_Z_ENABLE (1 << 8) 692145132Sanholt# define RADEON_ZBLOCK16 (1 << 15) 69395584Sanholt#define RADEON_RB3D_DEPTHOFFSET 0x1c24 694145132Sanholt#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 695112015Sanholt#define RADEON_RB3D_DEPTHPITCH 0x1c28 69695584Sanholt#define RADEON_RB3D_PLANEMASK 0x1d84 69795584Sanholt#define RADEON_RB3D_STENCILREFMASK 0x1d7c 69895584Sanholt#define RADEON_RB3D_ZCACHE_MODE 0x3250 69995584Sanholt#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 70095584Sanholt# define RADEON_RB3D_ZC_FLUSH (1 << 0) 70195584Sanholt# define RADEON_RB3D_ZC_FREE (1 << 2) 70295584Sanholt# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 70395584Sanholt# define RADEON_RB3D_ZC_BUSY (1 << 31) 704182080Srnoland#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 705182080Srnoland# define R300_ZC_FLUSH (1 << 0) 706182080Srnoland# define R300_ZC_FREE (1 << 1) 707182080Srnoland# define R300_ZC_BUSY (1 << 31) 708162132Sanholt#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 709162132Sanholt# define RADEON_RB3D_DC_FLUSH (3 << 0) 710162132Sanholt# define RADEON_RB3D_DC_FREE (3 << 2) 711162132Sanholt# define RADEON_RB3D_DC_FLUSH_ALL 0xf 712162132Sanholt# define RADEON_RB3D_DC_BUSY (1 << 31) 713182080Srnoland#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 714182080Srnoland# define R300_RB3D_DC_FLUSH (2 << 0) 715182080Srnoland# define R300_RB3D_DC_FREE (2 << 2) 716182080Srnoland# define R300_RB3D_DC_FINISH (1 << 4) 71795584Sanholt#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 71895584Sanholt# define RADEON_Z_TEST_MASK (7 << 4) 71995584Sanholt# define RADEON_Z_TEST_ALWAYS (7 << 4) 720145132Sanholt# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 72195584Sanholt# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 722112015Sanholt# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 723112015Sanholt# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 724112015Sanholt# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 725145132Sanholt# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 726145132Sanholt# define RADEON_FORCE_Z_DIRTY (1 << 29) 72795584Sanholt# define RADEON_Z_WRITE_ENABLE (1 << 30) 728145132Sanholt# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 72995584Sanholt#define RADEON_RBBM_SOFT_RESET 0x00f0 73095584Sanholt# define RADEON_SOFT_RESET_CP (1 << 0) 73195584Sanholt# define RADEON_SOFT_RESET_HI (1 << 1) 73295584Sanholt# define RADEON_SOFT_RESET_SE (1 << 2) 73395584Sanholt# define RADEON_SOFT_RESET_RE (1 << 3) 73495584Sanholt# define RADEON_SOFT_RESET_PP (1 << 4) 73595584Sanholt# define RADEON_SOFT_RESET_E2 (1 << 5) 73695584Sanholt# define RADEON_SOFT_RESET_RB (1 << 6) 73795584Sanholt# define RADEON_SOFT_RESET_HDP (1 << 7) 738182080Srnoland/* 739182080Srnoland * 6:0 Available slots in the FIFO 740182080Srnoland * 8 Host Interface active 741182080Srnoland * 9 CP request active 742182080Srnoland * 10 FIFO request active 743182080Srnoland * 11 Host Interface retry active 744182080Srnoland * 12 CP retry active 745182080Srnoland * 13 FIFO retry active 746182080Srnoland * 14 FIFO pipeline busy 747182080Srnoland * 15 Event engine busy 748182080Srnoland * 16 CP command stream busy 749182080Srnoland * 17 2D engine busy 750182080Srnoland * 18 2D portion of render backend busy 751182080Srnoland * 20 3D setup engine busy 752182080Srnoland * 26 GA engine busy 753182080Srnoland * 27 CBA 2D engine busy 754182080Srnoland * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 755182080Srnoland * command stream queue not empty or Ring Buffer not empty 756182080Srnoland */ 75795584Sanholt#define RADEON_RBBM_STATUS 0x0e40 758182080Srnoland/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 759182080Srnoland/* #define RADEON_RBBM_STATUS 0x1740 */ 760182080Srnoland/* bits 6:0 are dword slots available in the cmd fifo */ 76195584Sanholt# define RADEON_RBBM_FIFOCNT_MASK 0x007f 762182080Srnoland# define RADEON_HIRQ_ON_RBB (1 << 8) 763182080Srnoland# define RADEON_CPRQ_ON_RBB (1 << 9) 764182080Srnoland# define RADEON_CFRQ_ON_RBB (1 << 10) 765182080Srnoland# define RADEON_HIRQ_IN_RTBUF (1 << 11) 766182080Srnoland# define RADEON_CPRQ_IN_RTBUF (1 << 12) 767182080Srnoland# define RADEON_CFRQ_IN_RTBUF (1 << 13) 768182080Srnoland# define RADEON_PIPE_BUSY (1 << 14) 769182080Srnoland# define RADEON_ENG_EV_BUSY (1 << 15) 770182080Srnoland# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 771182080Srnoland# define RADEON_E2_BUSY (1 << 17) 772182080Srnoland# define RADEON_RB2D_BUSY (1 << 18) 773182080Srnoland# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 774182080Srnoland# define RADEON_VAP_BUSY (1 << 20) 775182080Srnoland# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 776182080Srnoland# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 777182080Srnoland# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 778182080Srnoland# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 779182080Srnoland# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 780182080Srnoland# define RADEON_GA_BUSY (1 << 26) 781182080Srnoland# define RADEON_CBA2D_BUSY (1 << 27) 782182080Srnoland# define RADEON_RBBM_ACTIVE (1 << 31) 78395584Sanholt#define RADEON_RE_LINE_PATTERN 0x1cd0 78495584Sanholt#define RADEON_RE_MISC 0x26c4 78595584Sanholt#define RADEON_RE_TOP_LEFT 0x26c0 78695584Sanholt#define RADEON_RE_WIDTH_HEIGHT 0x1c44 78795584Sanholt#define RADEON_RE_STIPPLE_ADDR 0x1cc8 78895584Sanholt#define RADEON_RE_STIPPLE_DATA 0x1ccc 78995584Sanholt 79095584Sanholt#define RADEON_SCISSOR_TL_0 0x1cd8 79195584Sanholt#define RADEON_SCISSOR_BR_0 0x1cdc 79295584Sanholt#define RADEON_SCISSOR_TL_1 0x1ce0 79395584Sanholt#define RADEON_SCISSOR_BR_1 0x1ce4 79495584Sanholt#define RADEON_SCISSOR_TL_2 0x1ce8 79595584Sanholt#define RADEON_SCISSOR_BR_2 0x1cec 79695584Sanholt#define RADEON_SE_COORD_FMT 0x1c50 79795584Sanholt#define RADEON_SE_CNTL 0x1c4c 79895584Sanholt# define RADEON_FFACE_CULL_CW (0 << 0) 79995584Sanholt# define RADEON_BFACE_SOLID (3 << 1) 80095584Sanholt# define RADEON_FFACE_SOLID (3 << 3) 80195584Sanholt# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 80295584Sanholt# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 80395584Sanholt# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 80495584Sanholt# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 80595584Sanholt# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 80695584Sanholt# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 80795584Sanholt# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 80895584Sanholt# define RADEON_FOG_SHADE_FLAT (1 << 14) 80995584Sanholt# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 81095584Sanholt# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 81195584Sanholt# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 81295584Sanholt# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 81395584Sanholt# define RADEON_ROUND_MODE_TRUNC (0 << 28) 81495584Sanholt# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 81595584Sanholt#define RADEON_SE_CNTL_STATUS 0x2140 81695584Sanholt#define RADEON_SE_LINE_WIDTH 0x1db8 81795584Sanholt#define RADEON_SE_VPORT_XSCALE 0x1d98 818112015Sanholt#define RADEON_SE_ZBIAS_FACTOR 0x1db0 819112015Sanholt#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 820112015Sanholt#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 821112015Sanholt#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 822112015Sanholt# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 823112015Sanholt# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 824112015Sanholt#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 825112015Sanholt#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 826112015Sanholt# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 827112015Sanholt#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 82895584Sanholt#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 82995584Sanholt#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 83095584Sanholt#define RADEON_SURFACE_CNTL 0x0b00 83195584Sanholt# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 83295584Sanholt# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 83395584Sanholt# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 83495584Sanholt# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 83595584Sanholt# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 83695584Sanholt# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 83795584Sanholt# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 83895584Sanholt# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 83995584Sanholt# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 84095584Sanholt#define RADEON_SURFACE0_INFO 0x0b0c 84195584Sanholt# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 84295584Sanholt# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 84395584Sanholt# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 84495584Sanholt# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 84595584Sanholt# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 84695584Sanholt# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 84795584Sanholt#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 84895584Sanholt#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 849145132Sanholt# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 85095584Sanholt#define RADEON_SURFACE1_INFO 0x0b1c 85195584Sanholt#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 85295584Sanholt#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 85395584Sanholt#define RADEON_SURFACE2_INFO 0x0b2c 85495584Sanholt#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 85595584Sanholt#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 85695584Sanholt#define RADEON_SURFACE3_INFO 0x0b3c 85795584Sanholt#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 85895584Sanholt#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 85995584Sanholt#define RADEON_SURFACE4_INFO 0x0b4c 86095584Sanholt#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 86195584Sanholt#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 86295584Sanholt#define RADEON_SURFACE5_INFO 0x0b5c 86395584Sanholt#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 86495584Sanholt#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 86595584Sanholt#define RADEON_SURFACE6_INFO 0x0b6c 86695584Sanholt#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 86795584Sanholt#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 86895584Sanholt#define RADEON_SURFACE7_INFO 0x0b7c 86995584Sanholt#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 87095584Sanholt#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 87195584Sanholt#define RADEON_SW_SEMAPHORE 0x013c 87295584Sanholt 87395584Sanholt#define RADEON_WAIT_UNTIL 0x1720 87495584Sanholt# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 875148211Sanholt# define RADEON_WAIT_2D_IDLE (1 << 14) 876148211Sanholt# define RADEON_WAIT_3D_IDLE (1 << 15) 87795584Sanholt# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 87895584Sanholt# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 87995584Sanholt# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 88095584Sanholt 881145132Sanholt#define RADEON_RB3D_ZMASKOFFSET 0x3234 88295584Sanholt#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 88395584Sanholt# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 88495584Sanholt# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 88595584Sanholt 88695584Sanholt/* CP registers */ 88795584Sanholt#define RADEON_CP_ME_RAM_ADDR 0x07d4 88895584Sanholt#define RADEON_CP_ME_RAM_RADDR 0x07d8 88995584Sanholt#define RADEON_CP_ME_RAM_DATAH 0x07dc 89095584Sanholt#define RADEON_CP_ME_RAM_DATAL 0x07e0 89195584Sanholt 89295584Sanholt#define RADEON_CP_RB_BASE 0x0700 89395584Sanholt#define RADEON_CP_RB_CNTL 0x0704 894112015Sanholt# define RADEON_BUF_SWAP_32BIT (2 << 16) 895162132Sanholt# define RADEON_RB_NO_UPDATE (1 << 27) 89695584Sanholt#define RADEON_CP_RB_RPTR_ADDR 0x070c 89795584Sanholt#define RADEON_CP_RB_RPTR 0x0710 89895584Sanholt#define RADEON_CP_RB_WPTR 0x0714 89995584Sanholt 90095584Sanholt#define RADEON_CP_RB_WPTR_DELAY 0x0718 90195584Sanholt# define RADEON_PRE_WRITE_TIMER_SHIFT 0 90295584Sanholt# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 90395584Sanholt 90495584Sanholt#define RADEON_CP_IB_BASE 0x0738 90595584Sanholt 90695584Sanholt#define RADEON_CP_CSQ_CNTL 0x0740 90795584Sanholt# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 90895584Sanholt# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 90995584Sanholt# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 91095584Sanholt# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 91195584Sanholt# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 91295584Sanholt# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 91395584Sanholt# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 91495584Sanholt 91595584Sanholt#define RADEON_AIC_CNTL 0x01d0 91695584Sanholt# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 91795584Sanholt#define RADEON_AIC_STAT 0x01d4 91895584Sanholt#define RADEON_AIC_PT_BASE 0x01d8 91995584Sanholt#define RADEON_AIC_LO_ADDR 0x01dc 92095584Sanholt#define RADEON_AIC_HI_ADDR 0x01e0 92195584Sanholt#define RADEON_AIC_TLB_ADDR 0x01e4 92295584Sanholt#define RADEON_AIC_TLB_DATA 0x01e8 92395584Sanholt 92495584Sanholt/* CP command packets */ 92595584Sanholt#define RADEON_CP_PACKET0 0x00000000 92695584Sanholt# define RADEON_ONE_REG_WR (1 << 15) 92795584Sanholt#define RADEON_CP_PACKET1 0x40000000 92895584Sanholt#define RADEON_CP_PACKET2 0x80000000 92995584Sanholt#define RADEON_CP_PACKET3 0xC0000000 930148211Sanholt# define RADEON_CP_NOP 0x00001000 931148211Sanholt# define RADEON_CP_NEXT_CHAR 0x00001900 932148211Sanholt# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 933148211Sanholt# define RADEON_CP_SET_SCISSORS 0x00001E00 934148211Sanholt /* GEN_INDX_PRIM is unsupported starting with R300 */ 93595584Sanholt# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 93695584Sanholt# define RADEON_WAIT_FOR_IDLE 0x00002600 937112015Sanholt# define RADEON_3D_DRAW_VBUF 0x00002800 93895584Sanholt# define RADEON_3D_DRAW_IMMD 0x00002900 939112015Sanholt# define RADEON_3D_DRAW_INDX 0x00002A00 940148211Sanholt# define RADEON_CP_LOAD_PALETTE 0x00002C00 941112015Sanholt# define RADEON_3D_LOAD_VBPNTR 0x00002F00 942145132Sanholt# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 943145132Sanholt# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 944145132Sanholt# define RADEON_3D_CLEAR_ZMASK 0x00003200 945148211Sanholt# define RADEON_CP_INDX_BUFFER 0x00003300 946148211Sanholt# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 947148211Sanholt# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 948148211Sanholt# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 949145132Sanholt# define RADEON_3D_CLEAR_HIZ 0x00003700 950148211Sanholt# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 95195584Sanholt# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 95295584Sanholt# define RADEON_CNTL_PAINT_MULTI 0x00009A00 95395584Sanholt# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 954112015Sanholt# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 95595584Sanholt 95695584Sanholt#define RADEON_CP_PACKET_MASK 0xC0000000 95795584Sanholt#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 95895584Sanholt#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 95995584Sanholt#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 96095584Sanholt#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 96195584Sanholt 96295584Sanholt#define RADEON_VTX_Z_PRESENT (1 << 31) 963112015Sanholt#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 96495584Sanholt 96595584Sanholt#define RADEON_PRIM_TYPE_NONE (0 << 0) 96695584Sanholt#define RADEON_PRIM_TYPE_POINT (1 << 0) 96795584Sanholt#define RADEON_PRIM_TYPE_LINE (2 << 0) 96895584Sanholt#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 96995584Sanholt#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 97095584Sanholt#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 97195584Sanholt#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 97295584Sanholt#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 97395584Sanholt#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 97495584Sanholt#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 97595584Sanholt#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 976112015Sanholt#define RADEON_PRIM_TYPE_MASK 0xf 97795584Sanholt#define RADEON_PRIM_WALK_IND (1 << 4) 97895584Sanholt#define RADEON_PRIM_WALK_LIST (2 << 4) 97995584Sanholt#define RADEON_PRIM_WALK_RING (3 << 4) 98095584Sanholt#define RADEON_COLOR_ORDER_BGRA (0 << 6) 98195584Sanholt#define RADEON_COLOR_ORDER_RGBA (1 << 6) 98295584Sanholt#define RADEON_MAOS_ENABLE (1 << 7) 98395584Sanholt#define RADEON_VTX_FMT_R128_MODE (0 << 8) 98495584Sanholt#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 98595584Sanholt#define RADEON_NUM_VERTICES_SHIFT 16 98695584Sanholt 98795584Sanholt#define RADEON_COLOR_FORMAT_CI8 2 98895584Sanholt#define RADEON_COLOR_FORMAT_ARGB1555 3 98995584Sanholt#define RADEON_COLOR_FORMAT_RGB565 4 99095584Sanholt#define RADEON_COLOR_FORMAT_ARGB8888 6 99195584Sanholt#define RADEON_COLOR_FORMAT_RGB332 7 99295584Sanholt#define RADEON_COLOR_FORMAT_RGB8 9 99395584Sanholt#define RADEON_COLOR_FORMAT_ARGB4444 15 99495584Sanholt 99595584Sanholt#define RADEON_TXFORMAT_I8 0 99695584Sanholt#define RADEON_TXFORMAT_AI88 1 99795584Sanholt#define RADEON_TXFORMAT_RGB332 2 99895584Sanholt#define RADEON_TXFORMAT_ARGB1555 3 99995584Sanholt#define RADEON_TXFORMAT_RGB565 4 100095584Sanholt#define RADEON_TXFORMAT_ARGB4444 5 100195584Sanholt#define RADEON_TXFORMAT_ARGB8888 6 100295584Sanholt#define RADEON_TXFORMAT_RGBA8888 7 1003119098Sanholt#define RADEON_TXFORMAT_Y8 8 1004112015Sanholt#define RADEON_TXFORMAT_VYUY422 10 1005112015Sanholt#define RADEON_TXFORMAT_YVYU422 11 1006112015Sanholt#define RADEON_TXFORMAT_DXT1 12 1007112015Sanholt#define RADEON_TXFORMAT_DXT23 14 1008112015Sanholt#define RADEON_TXFORMAT_DXT45 15 100995584Sanholt 1010112015Sanholt#define R200_PP_TXCBLEND_0 0x2f00 1011112015Sanholt#define R200_PP_TXCBLEND_1 0x2f10 1012112015Sanholt#define R200_PP_TXCBLEND_2 0x2f20 1013112015Sanholt#define R200_PP_TXCBLEND_3 0x2f30 1014112015Sanholt#define R200_PP_TXCBLEND_4 0x2f40 1015112015Sanholt#define R200_PP_TXCBLEND_5 0x2f50 1016112015Sanholt#define R200_PP_TXCBLEND_6 0x2f60 1017112015Sanholt#define R200_PP_TXCBLEND_7 0x2f70 1018145132Sanholt#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1019112015Sanholt#define R200_PP_TFACTOR_0 0x2ee0 1020112015Sanholt#define R200_SE_VTX_FMT_0 0x2088 1021112015Sanholt#define R200_SE_VAP_CNTL 0x2080 1022112015Sanholt#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1023145132Sanholt#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1024145132Sanholt#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1025145132Sanholt#define R200_PP_TXFILTER_5 0x2ca0 1026145132Sanholt#define R200_PP_TXFILTER_4 0x2c80 1027145132Sanholt#define R200_PP_TXFILTER_3 0x2c60 1028145132Sanholt#define R200_PP_TXFILTER_2 0x2c40 1029145132Sanholt#define R200_PP_TXFILTER_1 0x2c20 1030145132Sanholt#define R200_PP_TXFILTER_0 0x2c00 1031112015Sanholt#define R200_PP_TXOFFSET_5 0x2d78 1032112015Sanholt#define R200_PP_TXOFFSET_4 0x2d60 1033112015Sanholt#define R200_PP_TXOFFSET_3 0x2d48 1034112015Sanholt#define R200_PP_TXOFFSET_2 0x2d30 1035112015Sanholt#define R200_PP_TXOFFSET_1 0x2d18 1036112015Sanholt#define R200_PP_TXOFFSET_0 0x2d00 1037112015Sanholt 1038112015Sanholt#define R200_PP_CUBIC_FACES_0 0x2c18 1039112015Sanholt#define R200_PP_CUBIC_FACES_1 0x2c38 1040112015Sanholt#define R200_PP_CUBIC_FACES_2 0x2c58 1041112015Sanholt#define R200_PP_CUBIC_FACES_3 0x2c78 1042112015Sanholt#define R200_PP_CUBIC_FACES_4 0x2c98 1043112015Sanholt#define R200_PP_CUBIC_FACES_5 0x2cb8 1044112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1045112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1046112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1047112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1048112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1049112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1050112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1051112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1052112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1053112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1054112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1055112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1056112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1057112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1058112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1059112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1060112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1061112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1062112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1063112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1064112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1065112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1066112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1067112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1068112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1069112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1070112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1071112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1072112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1073112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1074112015Sanholt 1075112015Sanholt#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1076112015Sanholt#define R200_SE_VTE_CNTL 0x20b0 1077112015Sanholt#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1078112015Sanholt#define R200_PP_TAM_DEBUG3 0x2d9c 1079112015Sanholt#define R200_PP_CNTL_X 0x2cc4 1080112015Sanholt#define R200_SE_VAP_CNTL_STATUS 0x2140 1081112015Sanholt#define R200_RE_SCISSOR_TL_0 0x1cd8 1082112015Sanholt#define R200_RE_SCISSOR_TL_1 0x1ce0 1083112015Sanholt#define R200_RE_SCISSOR_TL_2 0x1ce8 1084145132Sanholt#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1085112015Sanholt#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1086112015Sanholt#define R200_SE_VTX_STATE_CNTL 0x2180 1087112015Sanholt#define R200_RE_POINTSIZE 0x2648 1088112015Sanholt#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1089112015Sanholt 1090145132Sanholt#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1091119098Sanholt#define RADEON_PP_TEX_SIZE_1 0x1d0c 1092119098Sanholt#define RADEON_PP_TEX_SIZE_2 0x1d14 1093112015Sanholt 1094145132Sanholt#define RADEON_PP_CUBIC_FACES_0 0x1d24 1095145132Sanholt#define RADEON_PP_CUBIC_FACES_1 0x1d28 1096145132Sanholt#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1097145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1098145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1099145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1100119098Sanholt 1101162132Sanholt#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1102162132Sanholt 1103112015Sanholt#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1104112015Sanholt#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1105112015Sanholt#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1106112015Sanholt#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1107112015Sanholt#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1108112015Sanholt#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1109112015Sanholt#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1110112015Sanholt#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1111112015Sanholt#define R200_3D_DRAW_IMMD_2 0xC0003500 1112112015Sanholt#define R200_SE_VTX_FMT_1 0x208c 1113145132Sanholt#define R200_RE_CNTL 0x1c50 1114112015Sanholt 1115130331Sanholt#define R200_RB3D_BLENDCOLOR 0x3218 1116112015Sanholt 1117145132Sanholt#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1118145132Sanholt 1119145132Sanholt#define R200_PP_TRI_PERF 0x2cf8 1120145132Sanholt 1121152909Sanholt#define R200_PP_AFS_0 0x2f80 1122152909Sanholt#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1123152909Sanholt 1124162132Sanholt#define R200_VAP_PVS_CNTL_1 0x22D0 1125162132Sanholt 1126152909Sanholt/* MPEG settings from VHA code */ 1127152909Sanholt#define RADEON_VHA_SETTO16_1 0x2694 1128152909Sanholt#define RADEON_VHA_SETTO16_2 0x2680 1129152909Sanholt#define RADEON_VHA_SETTO0_1 0x1840 1130152909Sanholt#define RADEON_VHA_FB_OFFSET 0x19e4 1131152909Sanholt#define RADEON_VHA_SETTO1AND70S 0x19d8 1132152909Sanholt#define RADEON_VHA_DST_PITCH 0x1408 1133152909Sanholt 1134152909Sanholt// set as reference header 1135152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 1136152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 1137152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 1138152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 1139152909Sanholt#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 1140152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 1141152909Sanholt#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 1142152909Sanholt#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 1143152909Sanholt#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 1144152909Sanholt#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 1145152909Sanholt#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 1146152909Sanholt#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 1147152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 1148152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 1149152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 1150152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 1151152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 1152152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 1153152909Sanholt 1154182080Srnoland#define R500_D1CRTC_STATUS 0x609c 1155182080Srnoland#define R500_D2CRTC_STATUS 0x689c 1156182080Srnoland#define R500_CRTC_V_BLANK (1<<0) 1157152909Sanholt 1158182080Srnoland#define R500_D1CRTC_FRAME_COUNT 0x60a4 1159182080Srnoland#define R500_D2CRTC_FRAME_COUNT 0x68a4 1160152909Sanholt 1161182080Srnoland#define R500_D1MODE_V_COUNTER 0x6530 1162182080Srnoland#define R500_D2MODE_V_COUNTER 0x6d30 1163182080Srnoland 1164182080Srnoland#define R500_D1MODE_VBLANK_STATUS 0x6534 1165182080Srnoland#define R500_D2MODE_VBLANK_STATUS 0x6d34 1166182080Srnoland#define R500_VBLANK_OCCURED (1<<0) 1167182080Srnoland#define R500_VBLANK_ACK (1<<4) 1168182080Srnoland#define R500_VBLANK_STAT (1<<12) 1169182080Srnoland#define R500_VBLANK_INT (1<<16) 1170182080Srnoland 1171182080Srnoland#define R500_DxMODE_INT_MASK 0x6540 1172182080Srnoland#define R500_D1MODE_INT_MASK (1<<0) 1173182080Srnoland#define R500_D2MODE_INT_MASK (1<<8) 1174182080Srnoland 1175182080Srnoland#define R500_DISP_INTERRUPT_STATUS 0x7edc 1176182080Srnoland#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1177182080Srnoland#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1178182080Srnoland 117995584Sanholt/* Constants */ 118095584Sanholt#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 118195584Sanholt 118295584Sanholt#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 118395584Sanholt#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 118495584Sanholt#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1185112015Sanholt#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 118695584Sanholt#define RADEON_LAST_DISPATCH 1 118795584Sanholt 118895584Sanholt#define RADEON_MAX_VB_AGE 0x7fffffff 118995584Sanholt#define RADEON_MAX_VB_VERTS (0xffff) 119095584Sanholt 119195584Sanholt#define RADEON_RING_HIGH_MARK 128 119295584Sanholt 1193152909Sanholt#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1194152909Sanholt 1195182080Srnoland#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1196182080Srnoland#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 1197112015Sanholt#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1198112015Sanholt#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 119995584Sanholt 120095584Sanholt#define RADEON_WRITE_PLL( addr, val ) \ 120195584Sanholtdo { \ 120295584Sanholt RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 120395584Sanholt ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 120495584Sanholt RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 120595584Sanholt} while (0) 120695584Sanholt 1207148211Sanholt#define RADEON_WRITE_PCIE( addr, val ) \ 1208148211Sanholtdo { \ 1209148211Sanholt RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1210148211Sanholt ((addr) & 0xff)); \ 1211148211Sanholt RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1212148211Sanholt} while (0) 1213148211Sanholt 1214182080Srnoland#define R500_WRITE_MCIND( addr, val ) \ 1215182080Srnolanddo { \ 1216182080Srnoland RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1217182080Srnoland RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1218182080Srnoland RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1219182080Srnoland} while (0) 1220182080Srnoland 1221182080Srnoland#define RS480_WRITE_MCIND( addr, val ) \ 1222182080Srnolanddo { \ 1223182080Srnoland RADEON_WRITE( RS480_NB_MC_INDEX, \ 1224182080Srnoland ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1225182080Srnoland RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \ 1226182080Srnoland RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \ 1227182080Srnoland} while (0) 1228182080Srnoland 1229182080Srnoland#define RS690_WRITE_MCIND( addr, val ) \ 1230182080Srnolanddo { \ 1231182080Srnoland RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1232182080Srnoland RADEON_WRITE(RS690_MC_DATA, val); \ 1233182080Srnoland RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1234182080Srnoland} while (0) 1235182080Srnoland 1236182080Srnoland#define IGP_WRITE_MCIND( addr, val ) \ 1237182080Srnolanddo { \ 1238182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ 1239182080Srnoland RS690_WRITE_MCIND( addr, val ); \ 1240182080Srnoland else \ 1241182080Srnoland RS480_WRITE_MCIND( addr, val ); \ 1242182080Srnoland} while (0) 1243182080Srnoland 124495584Sanholt#define CP_PACKET0( reg, n ) \ 124595584Sanholt (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 124695584Sanholt#define CP_PACKET0_TABLE( reg, n ) \ 124795584Sanholt (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 124895584Sanholt#define CP_PACKET1( reg0, reg1 ) \ 124995584Sanholt (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 125095584Sanholt#define CP_PACKET2() \ 125195584Sanholt (RADEON_CP_PACKET2) 125295584Sanholt#define CP_PACKET3( pkt, n ) \ 125395584Sanholt (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 125495584Sanholt 125595584Sanholt/* ================================================================ 125695584Sanholt * Engine control helper macros 125795584Sanholt */ 125895584Sanholt 125995584Sanholt#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 126095584Sanholt OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 126195584Sanholt OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 126295584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 126395584Sanholt} while (0) 126495584Sanholt 126595584Sanholt#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 126695584Sanholt OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 126795584Sanholt OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 126895584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 126995584Sanholt} while (0) 127095584Sanholt 127195584Sanholt#define RADEON_WAIT_UNTIL_IDLE() do { \ 127295584Sanholt OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 127395584Sanholt OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 127495584Sanholt RADEON_WAIT_3D_IDLECLEAN | \ 127595584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 127695584Sanholt} while (0) 127795584Sanholt 127895584Sanholt#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 127995584Sanholt OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 128095584Sanholt OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 128195584Sanholt} while (0) 128295584Sanholt 128395584Sanholt#define RADEON_FLUSH_CACHE() do { \ 1284182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1285182080Srnoland OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1286182080Srnoland OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1287182080Srnoland } else { \ 1288182080Srnoland OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1289182080Srnoland OUT_RING(R300_RB3D_DC_FLUSH); \ 1290182080Srnoland } \ 129195584Sanholt} while (0) 129295584Sanholt 129395584Sanholt#define RADEON_PURGE_CACHE() do { \ 1294182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1295182080Srnoland OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1296182080Srnoland OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1297182080Srnoland } else { \ 1298182080Srnoland OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1299182080Srnoland OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ 1300182080Srnoland } \ 130195584Sanholt} while (0) 130295584Sanholt 130395584Sanholt#define RADEON_FLUSH_ZCACHE() do { \ 1304182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1305182080Srnoland OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1306182080Srnoland OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1307182080Srnoland } else { \ 1308182080Srnoland OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) ); \ 1309182080Srnoland OUT_RING( R300_ZC_FLUSH ); \ 1310182080Srnoland } \ 131195584Sanholt} while (0) 131295584Sanholt 131395584Sanholt#define RADEON_PURGE_ZCACHE() do { \ 1314182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1315182080Srnoland OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1316182080Srnoland OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1317182080Srnoland } else { \ 1318182080Srnoland OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1319182080Srnoland OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1320182080Srnoland } \ 132195584Sanholt} while (0) 132295584Sanholt 132395584Sanholt/* ================================================================ 132495584Sanholt * Misc helper macros 132595584Sanholt */ 132695584Sanholt 1327145132Sanholt/* Perfbox functionality only. 1328112015Sanholt */ 132995584Sanholt#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 133095584Sanholtdo { \ 1331112015Sanholt if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1332113995Sanholt u32 head = GET_RING_HEAD( dev_priv ); \ 1333112015Sanholt if (head == dev_priv->ring.tail) \ 1334112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 133595584Sanholt } \ 133695584Sanholt} while (0) 133795584Sanholt 133895584Sanholt#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 133995584Sanholtdo { \ 134095584Sanholt drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 134195584Sanholt if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 134295584Sanholt int __ret = radeon_do_cp_idle( dev_priv ); \ 134395584Sanholt if ( __ret ) return __ret; \ 134495584Sanholt sarea_priv->last_dispatch = 0; \ 134595584Sanholt radeon_freelist_reset( dev ); \ 134695584Sanholt } \ 134795584Sanholt} while (0) 134895584Sanholt 134995584Sanholt#define RADEON_DISPATCH_AGE( age ) do { \ 135095584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 135195584Sanholt OUT_RING( age ); \ 135295584Sanholt} while (0) 135395584Sanholt 135495584Sanholt#define RADEON_FRAME_AGE( age ) do { \ 135595584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 135695584Sanholt OUT_RING( age ); \ 135795584Sanholt} while (0) 135895584Sanholt 135995584Sanholt#define RADEON_CLEAR_AGE( age ) do { \ 136095584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 136195584Sanholt OUT_RING( age ); \ 136295584Sanholt} while (0) 136395584Sanholt 136495584Sanholt/* ================================================================ 136595584Sanholt * Ring control 136695584Sanholt */ 136795584Sanholt 136895584Sanholt#define RADEON_VERBOSE 0 136995584Sanholt 1370112015Sanholt#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 137195584Sanholt 137295584Sanholt#define BEGIN_RING( n ) do { \ 137395584Sanholt if ( RADEON_VERBOSE ) { \ 1374182080Srnoland DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 137595584Sanholt } \ 137695584Sanholt if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1377162132Sanholt COMMIT_RING(); \ 137895584Sanholt radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 137995584Sanholt } \ 1380112015Sanholt _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 138195584Sanholt ring = dev_priv->ring.start; \ 138295584Sanholt write = dev_priv->ring.tail; \ 138395584Sanholt mask = dev_priv->ring.tail_mask; \ 138495584Sanholt} while (0) 138595584Sanholt 138695584Sanholt#define ADVANCE_RING() do { \ 138795584Sanholt if ( RADEON_VERBOSE ) { \ 138895584Sanholt DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 138995584Sanholt write, dev_priv->ring.tail ); \ 139095584Sanholt } \ 1391112015Sanholt if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1392182080Srnoland DRM_ERROR( \ 1393112015Sanholt "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1394112015Sanholt ((dev_priv->ring.tail + _nr) & mask), \ 1395112015Sanholt write, __LINE__); \ 1396112015Sanholt } else \ 1397112015Sanholt dev_priv->ring.tail = write; \ 139895584Sanholt} while (0) 139995584Sanholt 1400112015Sanholt#define COMMIT_RING() do { \ 1401112015Sanholt /* Flush writes to ring */ \ 1402119098Sanholt DRM_MEMORYBARRIER(); \ 1403113995Sanholt GET_RING_HEAD( dev_priv ); \ 1404112015Sanholt RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 1405112015Sanholt /* read from PCI bus to ensure correct posting */ \ 1406112015Sanholt RADEON_READ( RADEON_CP_RB_RPTR ); \ 1407112015Sanholt} while (0) 1408112015Sanholt 140995584Sanholt#define OUT_RING( x ) do { \ 141095584Sanholt if ( RADEON_VERBOSE ) { \ 141195584Sanholt DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 141295584Sanholt (unsigned int)(x), write ); \ 141395584Sanholt } \ 141495584Sanholt ring[write++] = (x); \ 141595584Sanholt write &= mask; \ 141695584Sanholt} while (0) 141795584Sanholt 1418112015Sanholt#define OUT_RING_REG( reg, val ) do { \ 1419112015Sanholt OUT_RING( CP_PACKET0( reg, 0 ) ); \ 1420112015Sanholt OUT_RING( val ); \ 1421112015Sanholt} while (0) 142295584Sanholt 1423145132Sanholt#define OUT_RING_TABLE( tab, sz ) do { \ 1424112015Sanholt int _size = (sz); \ 1425145132Sanholt int *_tab = (int *)(tab); \ 1426112015Sanholt \ 1427112015Sanholt if (write + _size > mask) { \ 1428145132Sanholt int _i = (mask+1) - write; \ 1429145132Sanholt _size -= _i; \ 1430145132Sanholt while (_i > 0) { \ 1431145132Sanholt *(int *)(ring + write) = *_tab++; \ 1432145132Sanholt write++; \ 1433145132Sanholt _i--; \ 1434145132Sanholt } \ 1435112015Sanholt write = 0; \ 1436145132Sanholt _tab += _i; \ 1437112015Sanholt } \ 1438145132Sanholt while (_size > 0) { \ 1439145132Sanholt *(ring + write) = *_tab++; \ 1440145132Sanholt write++; \ 1441145132Sanholt _size--; \ 1442145132Sanholt } \ 1443112015Sanholt write &= mask; \ 1444112015Sanholt} while (0) 1445112015Sanholt 1446145132Sanholt#endif /* __RADEON_DRV_H__ */ 1447