radeon_drv.h revision 157617
1152909Sanholt/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2152909Sanholt * 395584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 495584Sanholt * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 595584Sanholt * All rights reserved. 695584Sanholt * 795584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 895584Sanholt * copy of this software and associated documentation files (the "Software"), 995584Sanholt * to deal in the Software without restriction, including without limitation 1095584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1195584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1295584Sanholt * Software is furnished to do so, subject to the following conditions: 1395584Sanholt * 1495584Sanholt * The above copyright notice and this permission notice (including the next 1595584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1695584Sanholt * Software. 1795584Sanholt * 1895584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1995584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2095584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2195584Sanholt * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2295584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2395584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2495584Sanholt * DEALINGS IN THE SOFTWARE. 2595584Sanholt * 2695584Sanholt * Authors: 2795584Sanholt * Kevin E. Martin <martin@valinux.com> 2895584Sanholt * Gareth Hughes <gareth@valinux.com> 2995584Sanholt */ 3095584Sanholt 31152909Sanholt#include <sys/cdefs.h> 32152909Sanholt__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 157617 2006-04-09 20:45:45Z anholt $"); 33152909Sanholt 3495584Sanholt#ifndef __RADEON_DRV_H__ 3595584Sanholt#define __RADEON_DRV_H__ 3695584Sanholt 37145132Sanholt/* General customization: 38145132Sanholt */ 39145132Sanholt 40145132Sanholt#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41145132Sanholt 42145132Sanholt#define DRIVER_NAME "radeon" 43145132Sanholt#define DRIVER_DESC "ATI Radeon" 44157617Sanholt#define DRIVER_DATE "20060225" 45145132Sanholt 46145132Sanholt/* Interface history: 47145132Sanholt * 48145132Sanholt * 1.1 - ?? 49145132Sanholt * 1.2 - Add vertex2 ioctl (keith) 50145132Sanholt * - Add stencil capability to clear ioctl (gareth, keith) 51145132Sanholt * - Increase MAX_TEXTURE_LEVELS (brian) 52145132Sanholt * 1.3 - Add cmdbuf ioctl (keith) 53145132Sanholt * - Add support for new radeon packets (keith) 54145132Sanholt * - Add getparam ioctl (keith) 55145132Sanholt * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56145132Sanholt * 1.4 - Add scratch registers to get_param ioctl. 57145132Sanholt * 1.5 - Add r200 packets to cmdbuf ioctl 58145132Sanholt * - Add r200 function to init ioctl 59145132Sanholt * - Add 'scalar2' instruction to cmdbuf 60145132Sanholt * 1.6 - Add static GART memory manager 61145132Sanholt * Add irq handler (won't be turned on unless X server knows to) 62145132Sanholt * Add irq ioctls and irq_active getparam. 63145132Sanholt * Add wait command for cmdbuf ioctl 64145132Sanholt * Add GART offset query for getparam 65145132Sanholt * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66145132Sanholt * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67145132Sanholt * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68145132Sanholt * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69145132Sanholt * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70145132Sanholt * Add 'GET' queries for starting additional clients on different VT's. 71145132Sanholt * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72145132Sanholt * Add texture rectangle support for r100. 73145132Sanholt * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74145132Sanholt * clients use to tell the DRM where they think the framebuffer is 75145132Sanholt * located in the card's address space 76145132Sanholt * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77145132Sanholt * and GL_EXT_blend_[func|equation]_separate on r200 78145132Sanholt * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79145132Sanholt * (No 3D support yet - just microcode loading). 80145132Sanholt * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81145132Sanholt * - Add hyperz support, add hyperz flags to clear ioctl. 82145132Sanholt * 1.14- Add support for color tiling 83145132Sanholt * - Add R100/R200 surface allocation/free support 84145132Sanholt * 1.15- Add support for texture micro tiling 85145132Sanholt * - Add support for r100 cube maps 86145132Sanholt * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87145132Sanholt * texture filtering on r200 88152909Sanholt * 1.17- Add initial support for R300 (3D). 89157617Sanholt * 1.18- Add support for GL_ATI_fragment_shader, new packets 90157617Sanholt * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91157617Sanholt * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92157617Sanholt * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93152909Sanholt * 1.19- Add support for gart table in FB memory and PCIE r300 94157617Sanholt * 1.20- Add support for r300 texrect 95157617Sanholt * 1.21- Add support for card type getparam 96157617Sanholt * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97157617Sanholt * 1.23- Add new radeon memory map work from benh 98157617Sanholt * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99145132Sanholt */ 100145132Sanholt 101145132Sanholt#define DRIVER_MAJOR 1 102157617Sanholt#define DRIVER_MINOR 24 103145132Sanholt#define DRIVER_PATCHLEVEL 0 104145132Sanholt 105157617Sanholt/* 106157617Sanholt * Radeon chip families 107157617Sanholt */ 108145132Sanholtenum radeon_family { 109145132Sanholt CHIP_R100, 110157617Sanholt CHIP_RV100, 111145132Sanholt CHIP_RS100, 112152909Sanholt CHIP_RV200, 113157617Sanholt CHIP_RS200, 114145132Sanholt CHIP_R200, 115145132Sanholt CHIP_RV250, 116157617Sanholt CHIP_RS300, 117145132Sanholt CHIP_RV280, 118145132Sanholt CHIP_R300, 119148211Sanholt CHIP_R350, 120145132Sanholt CHIP_RV350, 121157617Sanholt CHIP_RV380, 122148211Sanholt CHIP_R420, 123157617Sanholt CHIP_RV410, 124157617Sanholt CHIP_RS400, 125145132Sanholt CHIP_LAST, 126145132Sanholt}; 127145132Sanholt 128145132Sanholtenum radeon_cp_microcode_version { 129145132Sanholt UCODE_R100, 130145132Sanholt UCODE_R200, 131145132Sanholt UCODE_R300, 132145132Sanholt}; 133145132Sanholt 134145132Sanholt/* 135145132Sanholt * Chip flags 136145132Sanholt */ 137145132Sanholtenum radeon_chip_flags { 138145132Sanholt CHIP_FAMILY_MASK = 0x0000ffffUL, 139145132Sanholt CHIP_FLAGS_MASK = 0xffff0000UL, 140145132Sanholt CHIP_IS_MOBILITY = 0x00010000UL, 141145132Sanholt CHIP_IS_IGP = 0x00020000UL, 142145132Sanholt CHIP_SINGLE_CRTC = 0x00040000UL, 143145132Sanholt CHIP_IS_AGP = 0x00080000UL, 144157617Sanholt CHIP_HAS_HIERZ = 0x00100000UL, 145148211Sanholt CHIP_IS_PCIE = 0x00200000UL, 146157617Sanholt CHIP_NEW_MEMMAP = 0x00400000UL, 147145132Sanholt}; 148145132Sanholt 149157617Sanholt#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 150157617Sanholt DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) 151113995Sanholt#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 152112015Sanholt 15395584Sanholttypedef struct drm_radeon_freelist { 154145132Sanholt unsigned int age; 155145132Sanholt drm_buf_t *buf; 156145132Sanholt struct drm_radeon_freelist *next; 157145132Sanholt struct drm_radeon_freelist *prev; 15895584Sanholt} drm_radeon_freelist_t; 15995584Sanholt 16095584Sanholttypedef struct drm_radeon_ring_buffer { 16195584Sanholt u32 *start; 16295584Sanholt u32 *end; 16395584Sanholt int size; 16495584Sanholt int size_l2qw; 16595584Sanholt 16695584Sanholt u32 tail; 16795584Sanholt u32 tail_mask; 16895584Sanholt int space; 16995584Sanholt 17095584Sanholt int high_mark; 17195584Sanholt} drm_radeon_ring_buffer_t; 17295584Sanholt 17395584Sanholttypedef struct drm_radeon_depth_clear_t { 17495584Sanholt u32 rb3d_cntl; 17595584Sanholt u32 rb3d_zstencilcntl; 17695584Sanholt u32 se_cntl; 17795584Sanholt} drm_radeon_depth_clear_t; 17895584Sanholt 179145132Sanholtstruct drm_radeon_driver_file_fields { 180145132Sanholt int64_t radeon_fb_delta; 181145132Sanholt}; 182112015Sanholt 183112015Sanholtstruct mem_block { 184112015Sanholt struct mem_block *next; 185112015Sanholt struct mem_block *prev; 186112015Sanholt int start; 187112015Sanholt int size; 188113995Sanholt DRMFILE filp; /* 0: free, -1: heap, other: real files */ 189112015Sanholt}; 190112015Sanholt 191145132Sanholtstruct radeon_surface { 192145132Sanholt int refcount; 193145132Sanholt u32 lower; 194145132Sanholt u32 upper; 195145132Sanholt u32 flags; 196145132Sanholt}; 197145132Sanholt 198145132Sanholtstruct radeon_virt_surface { 199145132Sanholt int surface_index; 200145132Sanholt u32 lower; 201145132Sanholt u32 upper; 202145132Sanholt u32 flags; 203145132Sanholt DRMFILE filp; 204145132Sanholt}; 205145132Sanholt 20695584Sanholttypedef struct drm_radeon_private { 207145132Sanholt 20895584Sanholt drm_radeon_ring_buffer_t ring; 20995584Sanholt drm_radeon_sarea_t *sarea_priv; 21095584Sanholt 211122580Sanholt u32 fb_location; 212157617Sanholt u32 fb_size; 213157617Sanholt int new_memmap; 214122580Sanholt 215119895Sanholt int gart_size; 216119895Sanholt u32 gart_vm_start; 217119895Sanholt unsigned long gart_buffers_offset; 21895584Sanholt 21995584Sanholt int cp_mode; 22095584Sanholt int cp_running; 22195584Sanholt 222145132Sanholt drm_radeon_freelist_t *head; 223145132Sanholt drm_radeon_freelist_t *tail; 22495584Sanholt int last_buf; 22595584Sanholt volatile u32 *scratch; 226112015Sanholt int writeback_works; 22795584Sanholt 22895584Sanholt int usec_timeout; 229112015Sanholt 230145132Sanholt int microcode_version; 231112015Sanholt 232112015Sanholt struct { 233112015Sanholt u32 boxes; 234112015Sanholt int freelist_timeouts; 235112015Sanholt int freelist_loops; 236112015Sanholt int requested_bufs; 237112015Sanholt int last_frame_reads; 238112015Sanholt int last_clear_reads; 239112015Sanholt int clears; 240112015Sanholt int texture_uploads; 241112015Sanholt } stats; 24295584Sanholt 243112015Sanholt int do_boxes; 24495584Sanholt int page_flipping; 24595584Sanholt int current_page; 24695584Sanholt 24795584Sanholt u32 color_fmt; 24895584Sanholt unsigned int front_offset; 24995584Sanholt unsigned int front_pitch; 25095584Sanholt unsigned int back_offset; 25195584Sanholt unsigned int back_pitch; 25295584Sanholt 25395584Sanholt u32 depth_fmt; 25495584Sanholt unsigned int depth_offset; 25595584Sanholt unsigned int depth_pitch; 25695584Sanholt 25795584Sanholt u32 front_pitch_offset; 25895584Sanholt u32 back_pitch_offset; 25995584Sanholt u32 depth_pitch_offset; 26095584Sanholt 26195584Sanholt drm_radeon_depth_clear_t depth_clear; 262145132Sanholt 263113995Sanholt unsigned long ring_offset; 264113995Sanholt unsigned long ring_rptr_offset; 265113995Sanholt unsigned long buffers_offset; 266119895Sanholt unsigned long gart_textures_offset; 26795584Sanholt 268112015Sanholt drm_local_map_t *sarea; 269112015Sanholt drm_local_map_t *mmio; 270112015Sanholt drm_local_map_t *cp_ring; 271112015Sanholt drm_local_map_t *ring_rptr; 272119895Sanholt drm_local_map_t *gart_textures; 273112015Sanholt 274119895Sanholt struct mem_block *gart_heap; 275112015Sanholt struct mem_block *fb_heap; 276112015Sanholt 277112015Sanholt /* SW interrupt */ 278145132Sanholt wait_queue_head_t swi_queue; 279145132Sanholt atomic_t swi_emitted; 280112015Sanholt 281145132Sanholt struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 282145132Sanholt struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; 283152909Sanholt 284152909Sanholt unsigned long pcigart_offset; 285152909Sanholt drm_ati_pcigart_info gart_info; 286157617Sanholt 287157617Sanholt u32 scratch_ages[5]; 288157617Sanholt 289145132Sanholt /* starting from here on, data is preserved accross an open */ 290145132Sanholt uint32_t flags; /* see radeon_chip_flags */ 291145132Sanholt 29295584Sanholt} drm_radeon_private_t; 29395584Sanholt 29495584Sanholttypedef struct drm_radeon_buf_priv { 29595584Sanholt u32 age; 29695584Sanholt} drm_radeon_buf_priv_t; 29795584Sanholt 298157617Sanholttypedef struct drm_radeon_kcmd_buffer { 299157617Sanholt int bufsz; 300157617Sanholt char *buf; 301157617Sanholt int nbox; 302157617Sanholt drm_clip_rect_t __user *boxes; 303157617Sanholt} drm_radeon_kcmd_buffer_t; 304157617Sanholt 305152909Sanholtextern int radeon_no_wb; 306152909Sanholtextern drm_ioctl_desc_t radeon_ioctls[]; 307152909Sanholtextern int radeon_max_ioctl; 308152909Sanholt 30995584Sanholt /* radeon_cp.c */ 310145132Sanholtextern int radeon_cp_init(DRM_IOCTL_ARGS); 311145132Sanholtextern int radeon_cp_start(DRM_IOCTL_ARGS); 312145132Sanholtextern int radeon_cp_stop(DRM_IOCTL_ARGS); 313145132Sanholtextern int radeon_cp_reset(DRM_IOCTL_ARGS); 314145132Sanholtextern int radeon_cp_idle(DRM_IOCTL_ARGS); 315145132Sanholtextern int radeon_cp_resume(DRM_IOCTL_ARGS); 316145132Sanholtextern int radeon_engine_reset(DRM_IOCTL_ARGS); 317145132Sanholtextern int radeon_fullscreen(DRM_IOCTL_ARGS); 318145132Sanholtextern int radeon_cp_buffers(DRM_IOCTL_ARGS); 31995584Sanholt 320145132Sanholtextern void radeon_freelist_reset(drm_device_t * dev); 321145132Sanholtextern drm_buf_t *radeon_freelist_get(drm_device_t * dev); 32295584Sanholt 323145132Sanholtextern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 32495584Sanholt 325145132Sanholtextern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 32695584Sanholt 327145132Sanholtextern int radeon_mem_alloc(DRM_IOCTL_ARGS); 328145132Sanholtextern int radeon_mem_free(DRM_IOCTL_ARGS); 329145132Sanholtextern int radeon_mem_init_heap(DRM_IOCTL_ARGS); 330145132Sanholtextern void radeon_mem_takedown(struct mem_block **heap); 331145132Sanholtextern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); 33295584Sanholt 333112015Sanholt /* radeon_irq.c */ 334145132Sanholtextern int radeon_irq_emit(DRM_IOCTL_ARGS); 335145132Sanholtextern int radeon_irq_wait(DRM_IOCTL_ARGS); 336112015Sanholt 337145132Sanholtextern void radeon_do_release(drm_device_t * dev); 338145132Sanholtextern int radeon_driver_vblank_wait(drm_device_t * dev, 339145132Sanholt unsigned int *sequence); 340145132Sanholtextern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 341145132Sanholtextern void radeon_driver_irq_preinstall(drm_device_t * dev); 342145132Sanholtextern void radeon_driver_irq_postinstall(drm_device_t * dev); 343145132Sanholtextern void radeon_driver_irq_uninstall(drm_device_t * dev); 344112015Sanholt 345152909Sanholtextern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 346152909Sanholtextern int radeon_driver_unload(struct drm_device *dev); 347152909Sanholtextern int radeon_driver_firstopen(struct drm_device *dev); 348152909Sanholtextern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp); 349152909Sanholtextern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp); 350152909Sanholtextern void radeon_driver_lastclose(drm_device_t * dev); 351152909Sanholtextern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv); 352152909Sanholtextern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 353152909Sanholt unsigned long arg); 354152909Sanholt 355148211Sanholt/* r300_cmdbuf.c */ 356148211Sanholtextern void r300_init_reg_flags(void); 357148211Sanholt 358157617Sanholtextern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, 359157617Sanholt drm_file_t* filp_priv, 360157617Sanholt drm_radeon_kcmd_buffer_t* cmdbuf); 361148211Sanholt 362112015Sanholt/* Flags for stats.boxes 363112015Sanholt */ 364112015Sanholt#define RADEON_BOX_DMA_IDLE 0x1 365112015Sanholt#define RADEON_BOX_RING_FULL 0x2 366112015Sanholt#define RADEON_BOX_FLIP 0x4 367112015Sanholt#define RADEON_BOX_WAIT_IDLE 0x8 368112015Sanholt#define RADEON_BOX_TEXTURE_LOAD 0x10 369112015Sanholt 37095584Sanholt/* Register definitions, register access macros and drmAddMap constants 37195584Sanholt * for Radeon kernel driver. 37295584Sanholt */ 373145132Sanholt#define RADEON_AGP_COMMAND 0x0f60 374145132Sanholt#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 375145132Sanholt# define RADEON_AGP_ENABLE (1<<8) 37695584Sanholt#define RADEON_AUX_SCISSOR_CNTL 0x26f0 37795584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 37895584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 37995584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 38095584Sanholt# define RADEON_SCISSOR_0_ENABLE (1 << 28) 38195584Sanholt# define RADEON_SCISSOR_1_ENABLE (1 << 29) 38295584Sanholt# define RADEON_SCISSOR_2_ENABLE (1 << 30) 38395584Sanholt 38495584Sanholt#define RADEON_BUS_CNTL 0x0030 38595584Sanholt# define RADEON_BUS_MASTER_DIS (1 << 6) 38695584Sanholt 38795584Sanholt#define RADEON_CLOCK_CNTL_DATA 0x000c 38895584Sanholt# define RADEON_PLL_WR_EN (1 << 7) 38995584Sanholt#define RADEON_CLOCK_CNTL_INDEX 0x0008 39095584Sanholt#define RADEON_CONFIG_APER_SIZE 0x0108 391157617Sanholt#define RADEON_CONFIG_MEMSIZE 0x00f8 39295584Sanholt#define RADEON_CRTC_OFFSET 0x0224 39395584Sanholt#define RADEON_CRTC_OFFSET_CNTL 0x0228 39495584Sanholt# define RADEON_CRTC_TILE_EN (1 << 15) 39595584Sanholt# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 396112015Sanholt#define RADEON_CRTC2_OFFSET 0x0324 397112015Sanholt#define RADEON_CRTC2_OFFSET_CNTL 0x0328 39895584Sanholt 399148211Sanholt#define RADEON_PCIE_INDEX 0x0030 400148211Sanholt#define RADEON_PCIE_DATA 0x0034 401148211Sanholt#define RADEON_PCIE_TX_GART_CNTL 0x10 402148211Sanholt# define RADEON_PCIE_TX_GART_EN (1 << 0) 403148211Sanholt# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 404148211Sanholt# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 405148211Sanholt# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 406148211Sanholt# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 407148211Sanholt# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 408148211Sanholt# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 409148211Sanholt# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 410148211Sanholt#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 411148211Sanholt#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 412148211Sanholt#define RADEON_PCIE_TX_GART_BASE 0x13 413148211Sanholt#define RADEON_PCIE_TX_GART_START_LO 0x14 414148211Sanholt#define RADEON_PCIE_TX_GART_START_HI 0x15 415148211Sanholt#define RADEON_PCIE_TX_GART_END_LO 0x16 416148211Sanholt#define RADEON_PCIE_TX_GART_END_HI 0x17 417148211Sanholt 418145132Sanholt#define RADEON_MPP_TB_CONFIG 0x01c0 419145132Sanholt#define RADEON_MEM_CNTL 0x0140 420145132Sanholt#define RADEON_MEM_SDRAM_MODE_REG 0x0158 421145132Sanholt#define RADEON_AGP_BASE 0x0170 422145132Sanholt 423122580Sanholt#define RADEON_RB3D_COLOROFFSET 0x1c40 42495584Sanholt#define RADEON_RB3D_COLORPITCH 0x1c48 42595584Sanholt 42695584Sanholt#define RADEON_DP_GUI_MASTER_CNTL 0x146c 42795584Sanholt# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 42895584Sanholt# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 42995584Sanholt# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 43095584Sanholt# define RADEON_GMC_BRUSH_NONE (15 << 4) 43195584Sanholt# define RADEON_GMC_DST_16BPP (4 << 8) 43295584Sanholt# define RADEON_GMC_DST_24BPP (5 << 8) 43395584Sanholt# define RADEON_GMC_DST_32BPP (6 << 8) 43495584Sanholt# define RADEON_GMC_DST_DATATYPE_SHIFT 8 43595584Sanholt# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 43695584Sanholt# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 43795584Sanholt# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 43895584Sanholt# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 43995584Sanholt# define RADEON_GMC_WR_MSK_DIS (1 << 30) 44095584Sanholt# define RADEON_ROP3_S 0x00cc0000 44195584Sanholt# define RADEON_ROP3_P 0x00f00000 44295584Sanholt#define RADEON_DP_WRITE_MASK 0x16cc 44395584Sanholt#define RADEON_DST_PITCH_OFFSET 0x142c 44495584Sanholt#define RADEON_DST_PITCH_OFFSET_C 0x1c80 44595584Sanholt# define RADEON_DST_TILE_LINEAR (0 << 30) 44695584Sanholt# define RADEON_DST_TILE_MACRO (1 << 30) 44795584Sanholt# define RADEON_DST_TILE_MICRO (2 << 30) 44895584Sanholt# define RADEON_DST_TILE_BOTH (3 << 30) 44995584Sanholt 45095584Sanholt#define RADEON_SCRATCH_REG0 0x15e0 45195584Sanholt#define RADEON_SCRATCH_REG1 0x15e4 45295584Sanholt#define RADEON_SCRATCH_REG2 0x15e8 45395584Sanholt#define RADEON_SCRATCH_REG3 0x15ec 45495584Sanholt#define RADEON_SCRATCH_REG4 0x15f0 45595584Sanholt#define RADEON_SCRATCH_REG5 0x15f4 45695584Sanholt#define RADEON_SCRATCH_UMSK 0x0770 45795584Sanholt#define RADEON_SCRATCH_ADDR 0x0774 45895584Sanholt 459112015Sanholt#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 460112015Sanholt 461112015Sanholt#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 462112015Sanholt ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 463112015Sanholt : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 464112015Sanholt 465112015Sanholt#define RADEON_GEN_INT_CNTL 0x0040 466112015Sanholt# define RADEON_CRTC_VBLANK_MASK (1 << 0) 467112015Sanholt# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 468112015Sanholt# define RADEON_SW_INT_ENABLE (1 << 25) 469112015Sanholt 470112015Sanholt#define RADEON_GEN_INT_STATUS 0x0044 471112015Sanholt# define RADEON_CRTC_VBLANK_STAT (1 << 0) 472112015Sanholt# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 473112015Sanholt# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 474112015Sanholt# define RADEON_SW_INT_TEST (1 << 25) 475112015Sanholt# define RADEON_SW_INT_TEST_ACK (1 << 25) 476112015Sanholt# define RADEON_SW_INT_FIRE (1 << 26) 477112015Sanholt 47895584Sanholt#define RADEON_HOST_PATH_CNTL 0x0130 47995584Sanholt# define RADEON_HDP_SOFT_RESET (1 << 26) 48095584Sanholt# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 48195584Sanholt# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 48295584Sanholt 48395584Sanholt#define RADEON_ISYNC_CNTL 0x1724 48495584Sanholt# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 48595584Sanholt# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 48695584Sanholt# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 48795584Sanholt# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 48895584Sanholt# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 48995584Sanholt# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 49095584Sanholt 491112015Sanholt#define RADEON_RBBM_GUICNTL 0x172c 492112015Sanholt# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 493112015Sanholt# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 494112015Sanholt# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 495112015Sanholt# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 496112015Sanholt 49795584Sanholt#define RADEON_MC_AGP_LOCATION 0x014c 49895584Sanholt#define RADEON_MC_FB_LOCATION 0x0148 49995584Sanholt#define RADEON_MCLK_CNTL 0x0012 50095584Sanholt# define RADEON_FORCEON_MCLKA (1 << 16) 50195584Sanholt# define RADEON_FORCEON_MCLKB (1 << 17) 50295584Sanholt# define RADEON_FORCEON_YCLKA (1 << 18) 50395584Sanholt# define RADEON_FORCEON_YCLKB (1 << 19) 50495584Sanholt# define RADEON_FORCEON_MC (1 << 20) 50595584Sanholt# define RADEON_FORCEON_AIC (1 << 21) 50695584Sanholt 50795584Sanholt#define RADEON_PP_BORDER_COLOR_0 0x1d40 50895584Sanholt#define RADEON_PP_BORDER_COLOR_1 0x1d44 50995584Sanholt#define RADEON_PP_BORDER_COLOR_2 0x1d48 51095584Sanholt#define RADEON_PP_CNTL 0x1c38 51195584Sanholt# define RADEON_SCISSOR_ENABLE (1 << 1) 51295584Sanholt#define RADEON_PP_LUM_MATRIX 0x1d00 51395584Sanholt#define RADEON_PP_MISC 0x1c14 51495584Sanholt#define RADEON_PP_ROT_MATRIX_0 0x1d58 51595584Sanholt#define RADEON_PP_TXFILTER_0 0x1c54 516122580Sanholt#define RADEON_PP_TXOFFSET_0 0x1c5c 51795584Sanholt#define RADEON_PP_TXFILTER_1 0x1c6c 51895584Sanholt#define RADEON_PP_TXFILTER_2 0x1c84 51995584Sanholt 52095584Sanholt#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 52195584Sanholt# define RADEON_RB2D_DC_FLUSH (3 << 0) 52295584Sanholt# define RADEON_RB2D_DC_FREE (3 << 2) 52395584Sanholt# define RADEON_RB2D_DC_FLUSH_ALL 0xf 52495584Sanholt# define RADEON_RB2D_DC_BUSY (1 << 31) 52595584Sanholt#define RADEON_RB3D_CNTL 0x1c3c 52695584Sanholt# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 52795584Sanholt# define RADEON_PLANE_MASK_ENABLE (1 << 1) 52895584Sanholt# define RADEON_DITHER_ENABLE (1 << 2) 52995584Sanholt# define RADEON_ROUND_ENABLE (1 << 3) 53095584Sanholt# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 53195584Sanholt# define RADEON_DITHER_INIT (1 << 5) 53295584Sanholt# define RADEON_ROP_ENABLE (1 << 6) 53395584Sanholt# define RADEON_STENCIL_ENABLE (1 << 7) 53495584Sanholt# define RADEON_Z_ENABLE (1 << 8) 535145132Sanholt# define RADEON_ZBLOCK16 (1 << 15) 53695584Sanholt#define RADEON_RB3D_DEPTHOFFSET 0x1c24 537145132Sanholt#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 538112015Sanholt#define RADEON_RB3D_DEPTHPITCH 0x1c28 53995584Sanholt#define RADEON_RB3D_PLANEMASK 0x1d84 54095584Sanholt#define RADEON_RB3D_STENCILREFMASK 0x1d7c 54195584Sanholt#define RADEON_RB3D_ZCACHE_MODE 0x3250 54295584Sanholt#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 54395584Sanholt# define RADEON_RB3D_ZC_FLUSH (1 << 0) 54495584Sanholt# define RADEON_RB3D_ZC_FREE (1 << 2) 54595584Sanholt# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 54695584Sanholt# define RADEON_RB3D_ZC_BUSY (1 << 31) 54795584Sanholt#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 54895584Sanholt# define RADEON_Z_TEST_MASK (7 << 4) 54995584Sanholt# define RADEON_Z_TEST_ALWAYS (7 << 4) 550145132Sanholt# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 55195584Sanholt# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 552112015Sanholt# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 553112015Sanholt# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 554112015Sanholt# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 555145132Sanholt# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 556145132Sanholt# define RADEON_FORCE_Z_DIRTY (1 << 29) 55795584Sanholt# define RADEON_Z_WRITE_ENABLE (1 << 30) 558145132Sanholt# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 55995584Sanholt#define RADEON_RBBM_SOFT_RESET 0x00f0 56095584Sanholt# define RADEON_SOFT_RESET_CP (1 << 0) 56195584Sanholt# define RADEON_SOFT_RESET_HI (1 << 1) 56295584Sanholt# define RADEON_SOFT_RESET_SE (1 << 2) 56395584Sanholt# define RADEON_SOFT_RESET_RE (1 << 3) 56495584Sanholt# define RADEON_SOFT_RESET_PP (1 << 4) 56595584Sanholt# define RADEON_SOFT_RESET_E2 (1 << 5) 56695584Sanholt# define RADEON_SOFT_RESET_RB (1 << 6) 56795584Sanholt# define RADEON_SOFT_RESET_HDP (1 << 7) 56895584Sanholt#define RADEON_RBBM_STATUS 0x0e40 56995584Sanholt# define RADEON_RBBM_FIFOCNT_MASK 0x007f 57095584Sanholt# define RADEON_RBBM_ACTIVE (1 << 31) 57195584Sanholt#define RADEON_RE_LINE_PATTERN 0x1cd0 57295584Sanholt#define RADEON_RE_MISC 0x26c4 57395584Sanholt#define RADEON_RE_TOP_LEFT 0x26c0 57495584Sanholt#define RADEON_RE_WIDTH_HEIGHT 0x1c44 57595584Sanholt#define RADEON_RE_STIPPLE_ADDR 0x1cc8 57695584Sanholt#define RADEON_RE_STIPPLE_DATA 0x1ccc 57795584Sanholt 57895584Sanholt#define RADEON_SCISSOR_TL_0 0x1cd8 57995584Sanholt#define RADEON_SCISSOR_BR_0 0x1cdc 58095584Sanholt#define RADEON_SCISSOR_TL_1 0x1ce0 58195584Sanholt#define RADEON_SCISSOR_BR_1 0x1ce4 58295584Sanholt#define RADEON_SCISSOR_TL_2 0x1ce8 58395584Sanholt#define RADEON_SCISSOR_BR_2 0x1cec 58495584Sanholt#define RADEON_SE_COORD_FMT 0x1c50 58595584Sanholt#define RADEON_SE_CNTL 0x1c4c 58695584Sanholt# define RADEON_FFACE_CULL_CW (0 << 0) 58795584Sanholt# define RADEON_BFACE_SOLID (3 << 1) 58895584Sanholt# define RADEON_FFACE_SOLID (3 << 3) 58995584Sanholt# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 59095584Sanholt# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 59195584Sanholt# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 59295584Sanholt# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 59395584Sanholt# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 59495584Sanholt# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 59595584Sanholt# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 59695584Sanholt# define RADEON_FOG_SHADE_FLAT (1 << 14) 59795584Sanholt# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 59895584Sanholt# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 59995584Sanholt# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 60095584Sanholt# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 60195584Sanholt# define RADEON_ROUND_MODE_TRUNC (0 << 28) 60295584Sanholt# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 60395584Sanholt#define RADEON_SE_CNTL_STATUS 0x2140 60495584Sanholt#define RADEON_SE_LINE_WIDTH 0x1db8 60595584Sanholt#define RADEON_SE_VPORT_XSCALE 0x1d98 606112015Sanholt#define RADEON_SE_ZBIAS_FACTOR 0x1db0 607112015Sanholt#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 608112015Sanholt#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 609112015Sanholt#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 610112015Sanholt# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 611112015Sanholt# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 612112015Sanholt#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 613112015Sanholt#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 614112015Sanholt# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 615112015Sanholt#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 61695584Sanholt#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 61795584Sanholt#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 61895584Sanholt#define RADEON_SURFACE_CNTL 0x0b00 61995584Sanholt# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 62095584Sanholt# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 62195584Sanholt# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 62295584Sanholt# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 62395584Sanholt# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 62495584Sanholt# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 62595584Sanholt# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 62695584Sanholt# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 62795584Sanholt# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 62895584Sanholt#define RADEON_SURFACE0_INFO 0x0b0c 62995584Sanholt# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 63095584Sanholt# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 63195584Sanholt# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 63295584Sanholt# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 63395584Sanholt# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 63495584Sanholt# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 63595584Sanholt#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 63695584Sanholt#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 637145132Sanholt# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 63895584Sanholt#define RADEON_SURFACE1_INFO 0x0b1c 63995584Sanholt#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 64095584Sanholt#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 64195584Sanholt#define RADEON_SURFACE2_INFO 0x0b2c 64295584Sanholt#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 64395584Sanholt#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 64495584Sanholt#define RADEON_SURFACE3_INFO 0x0b3c 64595584Sanholt#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 64695584Sanholt#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 64795584Sanholt#define RADEON_SURFACE4_INFO 0x0b4c 64895584Sanholt#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 64995584Sanholt#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 65095584Sanholt#define RADEON_SURFACE5_INFO 0x0b5c 65195584Sanholt#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 65295584Sanholt#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 65395584Sanholt#define RADEON_SURFACE6_INFO 0x0b6c 65495584Sanholt#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 65595584Sanholt#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 65695584Sanholt#define RADEON_SURFACE7_INFO 0x0b7c 65795584Sanholt#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 65895584Sanholt#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 65995584Sanholt#define RADEON_SW_SEMAPHORE 0x013c 66095584Sanholt 66195584Sanholt#define RADEON_WAIT_UNTIL 0x1720 66295584Sanholt# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 663148211Sanholt# define RADEON_WAIT_2D_IDLE (1 << 14) 664148211Sanholt# define RADEON_WAIT_3D_IDLE (1 << 15) 66595584Sanholt# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 66695584Sanholt# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 66795584Sanholt# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 66895584Sanholt 669145132Sanholt#define RADEON_RB3D_ZMASKOFFSET 0x3234 67095584Sanholt#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 67195584Sanholt# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 67295584Sanholt# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 67395584Sanholt 67495584Sanholt/* CP registers */ 67595584Sanholt#define RADEON_CP_ME_RAM_ADDR 0x07d4 67695584Sanholt#define RADEON_CP_ME_RAM_RADDR 0x07d8 67795584Sanholt#define RADEON_CP_ME_RAM_DATAH 0x07dc 67895584Sanholt#define RADEON_CP_ME_RAM_DATAL 0x07e0 67995584Sanholt 68095584Sanholt#define RADEON_CP_RB_BASE 0x0700 68195584Sanholt#define RADEON_CP_RB_CNTL 0x0704 682112015Sanholt# define RADEON_BUF_SWAP_32BIT (2 << 16) 68395584Sanholt#define RADEON_CP_RB_RPTR_ADDR 0x070c 68495584Sanholt#define RADEON_CP_RB_RPTR 0x0710 68595584Sanholt#define RADEON_CP_RB_WPTR 0x0714 68695584Sanholt 68795584Sanholt#define RADEON_CP_RB_WPTR_DELAY 0x0718 68895584Sanholt# define RADEON_PRE_WRITE_TIMER_SHIFT 0 68995584Sanholt# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 69095584Sanholt 69195584Sanholt#define RADEON_CP_IB_BASE 0x0738 69295584Sanholt 69395584Sanholt#define RADEON_CP_CSQ_CNTL 0x0740 69495584Sanholt# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 69595584Sanholt# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 69695584Sanholt# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 69795584Sanholt# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 69895584Sanholt# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 69995584Sanholt# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 70095584Sanholt# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 70195584Sanholt 70295584Sanholt#define RADEON_AIC_CNTL 0x01d0 70395584Sanholt# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 70495584Sanholt#define RADEON_AIC_STAT 0x01d4 70595584Sanholt#define RADEON_AIC_PT_BASE 0x01d8 70695584Sanholt#define RADEON_AIC_LO_ADDR 0x01dc 70795584Sanholt#define RADEON_AIC_HI_ADDR 0x01e0 70895584Sanholt#define RADEON_AIC_TLB_ADDR 0x01e4 70995584Sanholt#define RADEON_AIC_TLB_DATA 0x01e8 71095584Sanholt 71195584Sanholt/* CP command packets */ 71295584Sanholt#define RADEON_CP_PACKET0 0x00000000 71395584Sanholt# define RADEON_ONE_REG_WR (1 << 15) 71495584Sanholt#define RADEON_CP_PACKET1 0x40000000 71595584Sanholt#define RADEON_CP_PACKET2 0x80000000 71695584Sanholt#define RADEON_CP_PACKET3 0xC0000000 717148211Sanholt# define RADEON_CP_NOP 0x00001000 718148211Sanholt# define RADEON_CP_NEXT_CHAR 0x00001900 719148211Sanholt# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 720148211Sanholt# define RADEON_CP_SET_SCISSORS 0x00001E00 721148211Sanholt /* GEN_INDX_PRIM is unsupported starting with R300 */ 72295584Sanholt# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 72395584Sanholt# define RADEON_WAIT_FOR_IDLE 0x00002600 724112015Sanholt# define RADEON_3D_DRAW_VBUF 0x00002800 72595584Sanholt# define RADEON_3D_DRAW_IMMD 0x00002900 726112015Sanholt# define RADEON_3D_DRAW_INDX 0x00002A00 727148211Sanholt# define RADEON_CP_LOAD_PALETTE 0x00002C00 728112015Sanholt# define RADEON_3D_LOAD_VBPNTR 0x00002F00 729145132Sanholt# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 730145132Sanholt# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 731145132Sanholt# define RADEON_3D_CLEAR_ZMASK 0x00003200 732148211Sanholt# define RADEON_CP_INDX_BUFFER 0x00003300 733148211Sanholt# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 734148211Sanholt# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 735148211Sanholt# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 736145132Sanholt# define RADEON_3D_CLEAR_HIZ 0x00003700 737148211Sanholt# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 73895584Sanholt# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 73995584Sanholt# define RADEON_CNTL_PAINT_MULTI 0x00009A00 74095584Sanholt# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 741112015Sanholt# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 74295584Sanholt 74395584Sanholt#define RADEON_CP_PACKET_MASK 0xC0000000 74495584Sanholt#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 74595584Sanholt#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 74695584Sanholt#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 74795584Sanholt#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 74895584Sanholt 74995584Sanholt#define RADEON_VTX_Z_PRESENT (1 << 31) 750112015Sanholt#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 75195584Sanholt 75295584Sanholt#define RADEON_PRIM_TYPE_NONE (0 << 0) 75395584Sanholt#define RADEON_PRIM_TYPE_POINT (1 << 0) 75495584Sanholt#define RADEON_PRIM_TYPE_LINE (2 << 0) 75595584Sanholt#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 75695584Sanholt#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 75795584Sanholt#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 75895584Sanholt#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 75995584Sanholt#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 76095584Sanholt#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 76195584Sanholt#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 76295584Sanholt#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 763112015Sanholt#define RADEON_PRIM_TYPE_MASK 0xf 76495584Sanholt#define RADEON_PRIM_WALK_IND (1 << 4) 76595584Sanholt#define RADEON_PRIM_WALK_LIST (2 << 4) 76695584Sanholt#define RADEON_PRIM_WALK_RING (3 << 4) 76795584Sanholt#define RADEON_COLOR_ORDER_BGRA (0 << 6) 76895584Sanholt#define RADEON_COLOR_ORDER_RGBA (1 << 6) 76995584Sanholt#define RADEON_MAOS_ENABLE (1 << 7) 77095584Sanholt#define RADEON_VTX_FMT_R128_MODE (0 << 8) 77195584Sanholt#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 77295584Sanholt#define RADEON_NUM_VERTICES_SHIFT 16 77395584Sanholt 77495584Sanholt#define RADEON_COLOR_FORMAT_CI8 2 77595584Sanholt#define RADEON_COLOR_FORMAT_ARGB1555 3 77695584Sanholt#define RADEON_COLOR_FORMAT_RGB565 4 77795584Sanholt#define RADEON_COLOR_FORMAT_ARGB8888 6 77895584Sanholt#define RADEON_COLOR_FORMAT_RGB332 7 77995584Sanholt#define RADEON_COLOR_FORMAT_RGB8 9 78095584Sanholt#define RADEON_COLOR_FORMAT_ARGB4444 15 78195584Sanholt 78295584Sanholt#define RADEON_TXFORMAT_I8 0 78395584Sanholt#define RADEON_TXFORMAT_AI88 1 78495584Sanholt#define RADEON_TXFORMAT_RGB332 2 78595584Sanholt#define RADEON_TXFORMAT_ARGB1555 3 78695584Sanholt#define RADEON_TXFORMAT_RGB565 4 78795584Sanholt#define RADEON_TXFORMAT_ARGB4444 5 78895584Sanholt#define RADEON_TXFORMAT_ARGB8888 6 78995584Sanholt#define RADEON_TXFORMAT_RGBA8888 7 790119098Sanholt#define RADEON_TXFORMAT_Y8 8 791112015Sanholt#define RADEON_TXFORMAT_VYUY422 10 792112015Sanholt#define RADEON_TXFORMAT_YVYU422 11 793112015Sanholt#define RADEON_TXFORMAT_DXT1 12 794112015Sanholt#define RADEON_TXFORMAT_DXT23 14 795112015Sanholt#define RADEON_TXFORMAT_DXT45 15 79695584Sanholt 797112015Sanholt#define R200_PP_TXCBLEND_0 0x2f00 798112015Sanholt#define R200_PP_TXCBLEND_1 0x2f10 799112015Sanholt#define R200_PP_TXCBLEND_2 0x2f20 800112015Sanholt#define R200_PP_TXCBLEND_3 0x2f30 801112015Sanholt#define R200_PP_TXCBLEND_4 0x2f40 802112015Sanholt#define R200_PP_TXCBLEND_5 0x2f50 803112015Sanholt#define R200_PP_TXCBLEND_6 0x2f60 804112015Sanholt#define R200_PP_TXCBLEND_7 0x2f70 805145132Sanholt#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 806112015Sanholt#define R200_PP_TFACTOR_0 0x2ee0 807112015Sanholt#define R200_SE_VTX_FMT_0 0x2088 808112015Sanholt#define R200_SE_VAP_CNTL 0x2080 809112015Sanholt#define R200_SE_TCL_MATRIX_SEL_0 0x2230 810145132Sanholt#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 811145132Sanholt#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 812145132Sanholt#define R200_PP_TXFILTER_5 0x2ca0 813145132Sanholt#define R200_PP_TXFILTER_4 0x2c80 814145132Sanholt#define R200_PP_TXFILTER_3 0x2c60 815145132Sanholt#define R200_PP_TXFILTER_2 0x2c40 816145132Sanholt#define R200_PP_TXFILTER_1 0x2c20 817145132Sanholt#define R200_PP_TXFILTER_0 0x2c00 818112015Sanholt#define R200_PP_TXOFFSET_5 0x2d78 819112015Sanholt#define R200_PP_TXOFFSET_4 0x2d60 820112015Sanholt#define R200_PP_TXOFFSET_3 0x2d48 821112015Sanholt#define R200_PP_TXOFFSET_2 0x2d30 822112015Sanholt#define R200_PP_TXOFFSET_1 0x2d18 823112015Sanholt#define R200_PP_TXOFFSET_0 0x2d00 824112015Sanholt 825112015Sanholt#define R200_PP_CUBIC_FACES_0 0x2c18 826112015Sanholt#define R200_PP_CUBIC_FACES_1 0x2c38 827112015Sanholt#define R200_PP_CUBIC_FACES_2 0x2c58 828112015Sanholt#define R200_PP_CUBIC_FACES_3 0x2c78 829112015Sanholt#define R200_PP_CUBIC_FACES_4 0x2c98 830112015Sanholt#define R200_PP_CUBIC_FACES_5 0x2cb8 831112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 832112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 833112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 834112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 835112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 836112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 837112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 838112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 839112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 840112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 841112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 842112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 843112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 844112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 845112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 846112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 847112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 848112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 849112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 850112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 851112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 852112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 853112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 854112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 855112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 856112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 857112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 858112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 859112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 860112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 861112015Sanholt 862112015Sanholt#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 863112015Sanholt#define R200_SE_VTE_CNTL 0x20b0 864112015Sanholt#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 865112015Sanholt#define R200_PP_TAM_DEBUG3 0x2d9c 866112015Sanholt#define R200_PP_CNTL_X 0x2cc4 867112015Sanholt#define R200_SE_VAP_CNTL_STATUS 0x2140 868112015Sanholt#define R200_RE_SCISSOR_TL_0 0x1cd8 869112015Sanholt#define R200_RE_SCISSOR_TL_1 0x1ce0 870112015Sanholt#define R200_RE_SCISSOR_TL_2 0x1ce8 871145132Sanholt#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 872112015Sanholt#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 873112015Sanholt#define R200_SE_VTX_STATE_CNTL 0x2180 874112015Sanholt#define R200_RE_POINTSIZE 0x2648 875112015Sanholt#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 876112015Sanholt 877145132Sanholt#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 878119098Sanholt#define RADEON_PP_TEX_SIZE_1 0x1d0c 879119098Sanholt#define RADEON_PP_TEX_SIZE_2 0x1d14 880112015Sanholt 881145132Sanholt#define RADEON_PP_CUBIC_FACES_0 0x1d24 882145132Sanholt#define RADEON_PP_CUBIC_FACES_1 0x1d28 883145132Sanholt#define RADEON_PP_CUBIC_FACES_2 0x1d2c 884145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 885145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 886145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 887119098Sanholt 888112015Sanholt#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 889112015Sanholt#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 890112015Sanholt#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 891112015Sanholt#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 892112015Sanholt#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 893112015Sanholt#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 894112015Sanholt#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 895112015Sanholt#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 896112015Sanholt#define R200_3D_DRAW_IMMD_2 0xC0003500 897112015Sanholt#define R200_SE_VTX_FMT_1 0x208c 898145132Sanholt#define R200_RE_CNTL 0x1c50 899112015Sanholt 900130331Sanholt#define R200_RB3D_BLENDCOLOR 0x3218 901112015Sanholt 902145132Sanholt#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 903145132Sanholt 904145132Sanholt#define R200_PP_TRI_PERF 0x2cf8 905145132Sanholt 906152909Sanholt#define R200_PP_AFS_0 0x2f80 907152909Sanholt#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 908152909Sanholt 909152909Sanholt/* MPEG settings from VHA code */ 910152909Sanholt#define RADEON_VHA_SETTO16_1 0x2694 911152909Sanholt#define RADEON_VHA_SETTO16_2 0x2680 912152909Sanholt#define RADEON_VHA_SETTO0_1 0x1840 913152909Sanholt#define RADEON_VHA_FB_OFFSET 0x19e4 914152909Sanholt#define RADEON_VHA_SETTO1AND70S 0x19d8 915152909Sanholt#define RADEON_VHA_DST_PITCH 0x1408 916152909Sanholt 917152909Sanholt// set as reference header 918152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 919152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 920152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 921152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 922152909Sanholt#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 923152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 924152909Sanholt#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 925152909Sanholt#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 926152909Sanholt#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 927152909Sanholt#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 928152909Sanholt#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 929152909Sanholt#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 930152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 931152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 932152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 933152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 934152909Sanholt#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 935152909Sanholt#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 936152909Sanholt 937152909Sanholt 938152909Sanholt 93995584Sanholt/* Constants */ 94095584Sanholt#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 94195584Sanholt 94295584Sanholt#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 94395584Sanholt#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 94495584Sanholt#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 945112015Sanholt#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 94695584Sanholt#define RADEON_LAST_DISPATCH 1 94795584Sanholt 94895584Sanholt#define RADEON_MAX_VB_AGE 0x7fffffff 94995584Sanholt#define RADEON_MAX_VB_VERTS (0xffff) 95095584Sanholt 95195584Sanholt#define RADEON_RING_HIGH_MARK 128 95295584Sanholt 953152909Sanholt#define RADEON_PCIGART_TABLE_SIZE (32*1024) 954152909Sanholt 955112015Sanholt#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 956112015Sanholt#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 957112015Sanholt#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 958112015Sanholt#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 95995584Sanholt 96095584Sanholt#define RADEON_WRITE_PLL( addr, val ) \ 96195584Sanholtdo { \ 96295584Sanholt RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 96395584Sanholt ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 96495584Sanholt RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 96595584Sanholt} while (0) 96695584Sanholt 967148211Sanholt#define RADEON_WRITE_PCIE( addr, val ) \ 968148211Sanholtdo { \ 969148211Sanholt RADEON_WRITE8( RADEON_PCIE_INDEX, \ 970148211Sanholt ((addr) & 0xff)); \ 971148211Sanholt RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 972148211Sanholt} while (0) 973148211Sanholt 97495584Sanholt#define CP_PACKET0( reg, n ) \ 97595584Sanholt (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 97695584Sanholt#define CP_PACKET0_TABLE( reg, n ) \ 97795584Sanholt (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 97895584Sanholt#define CP_PACKET1( reg0, reg1 ) \ 97995584Sanholt (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 98095584Sanholt#define CP_PACKET2() \ 98195584Sanholt (RADEON_CP_PACKET2) 98295584Sanholt#define CP_PACKET3( pkt, n ) \ 98395584Sanholt (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 98495584Sanholt 98595584Sanholt/* ================================================================ 98695584Sanholt * Engine control helper macros 98795584Sanholt */ 98895584Sanholt 98995584Sanholt#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 99095584Sanholt OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 99195584Sanholt OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 99295584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 99395584Sanholt} while (0) 99495584Sanholt 99595584Sanholt#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 99695584Sanholt OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 99795584Sanholt OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 99895584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 99995584Sanholt} while (0) 100095584Sanholt 100195584Sanholt#define RADEON_WAIT_UNTIL_IDLE() do { \ 100295584Sanholt OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 100395584Sanholt OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 100495584Sanholt RADEON_WAIT_3D_IDLECLEAN | \ 100595584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 100695584Sanholt} while (0) 100795584Sanholt 100895584Sanholt#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 100995584Sanholt OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 101095584Sanholt OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 101195584Sanholt} while (0) 101295584Sanholt 101395584Sanholt#define RADEON_FLUSH_CACHE() do { \ 101495584Sanholt OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 101595584Sanholt OUT_RING( RADEON_RB2D_DC_FLUSH ); \ 101695584Sanholt} while (0) 101795584Sanholt 101895584Sanholt#define RADEON_PURGE_CACHE() do { \ 101995584Sanholt OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 102095584Sanholt OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ 102195584Sanholt} while (0) 102295584Sanholt 102395584Sanholt#define RADEON_FLUSH_ZCACHE() do { \ 102495584Sanholt OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 102595584Sanholt OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 102695584Sanholt} while (0) 102795584Sanholt 102895584Sanholt#define RADEON_PURGE_ZCACHE() do { \ 102995584Sanholt OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 103095584Sanholt OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 103195584Sanholt} while (0) 103295584Sanholt 103395584Sanholt/* ================================================================ 103495584Sanholt * Misc helper macros 103595584Sanholt */ 103695584Sanholt 1037145132Sanholt/* Perfbox functionality only. 1038112015Sanholt */ 103995584Sanholt#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 104095584Sanholtdo { \ 1041112015Sanholt if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1042113995Sanholt u32 head = GET_RING_HEAD( dev_priv ); \ 1043112015Sanholt if (head == dev_priv->ring.tail) \ 1044112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 104595584Sanholt } \ 104695584Sanholt} while (0) 104795584Sanholt 104895584Sanholt#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 104995584Sanholtdo { \ 105095584Sanholt drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 105195584Sanholt if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 105295584Sanholt int __ret = radeon_do_cp_idle( dev_priv ); \ 105395584Sanholt if ( __ret ) return __ret; \ 105495584Sanholt sarea_priv->last_dispatch = 0; \ 105595584Sanholt radeon_freelist_reset( dev ); \ 105695584Sanholt } \ 105795584Sanholt} while (0) 105895584Sanholt 105995584Sanholt#define RADEON_DISPATCH_AGE( age ) do { \ 106095584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 106195584Sanholt OUT_RING( age ); \ 106295584Sanholt} while (0) 106395584Sanholt 106495584Sanholt#define RADEON_FRAME_AGE( age ) do { \ 106595584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 106695584Sanholt OUT_RING( age ); \ 106795584Sanholt} while (0) 106895584Sanholt 106995584Sanholt#define RADEON_CLEAR_AGE( age ) do { \ 107095584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 107195584Sanholt OUT_RING( age ); \ 107295584Sanholt} while (0) 107395584Sanholt 107495584Sanholt/* ================================================================ 107595584Sanholt * Ring control 107695584Sanholt */ 107795584Sanholt 107895584Sanholt#define RADEON_VERBOSE 0 107995584Sanholt 1080112015Sanholt#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 108195584Sanholt 108295584Sanholt#define BEGIN_RING( n ) do { \ 108395584Sanholt if ( RADEON_VERBOSE ) { \ 108495584Sanholt DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 1085112015Sanholt n, __FUNCTION__ ); \ 108695584Sanholt } \ 108795584Sanholt if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1088112015Sanholt COMMIT_RING(); \ 108995584Sanholt radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 109095584Sanholt } \ 1091112015Sanholt _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 109295584Sanholt ring = dev_priv->ring.start; \ 109395584Sanholt write = dev_priv->ring.tail; \ 109495584Sanholt mask = dev_priv->ring.tail_mask; \ 109595584Sanholt} while (0) 109695584Sanholt 109795584Sanholt#define ADVANCE_RING() do { \ 109895584Sanholt if ( RADEON_VERBOSE ) { \ 109995584Sanholt DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 110095584Sanholt write, dev_priv->ring.tail ); \ 110195584Sanholt } \ 1102112015Sanholt if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1103112015Sanholt DRM_ERROR( \ 1104112015Sanholt "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1105112015Sanholt ((dev_priv->ring.tail + _nr) & mask), \ 1106112015Sanholt write, __LINE__); \ 1107112015Sanholt } else \ 1108112015Sanholt dev_priv->ring.tail = write; \ 110995584Sanholt} while (0) 111095584Sanholt 1111112015Sanholt#define COMMIT_RING() do { \ 1112112015Sanholt /* Flush writes to ring */ \ 1113119098Sanholt DRM_MEMORYBARRIER(); \ 1114113995Sanholt GET_RING_HEAD( dev_priv ); \ 1115112015Sanholt RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 1116112015Sanholt /* read from PCI bus to ensure correct posting */ \ 1117112015Sanholt RADEON_READ( RADEON_CP_RB_RPTR ); \ 1118112015Sanholt} while (0) 1119112015Sanholt 112095584Sanholt#define OUT_RING( x ) do { \ 112195584Sanholt if ( RADEON_VERBOSE ) { \ 112295584Sanholt DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 112395584Sanholt (unsigned int)(x), write ); \ 112495584Sanholt } \ 112595584Sanholt ring[write++] = (x); \ 112695584Sanholt write &= mask; \ 112795584Sanholt} while (0) 112895584Sanholt 1129112015Sanholt#define OUT_RING_REG( reg, val ) do { \ 1130112015Sanholt OUT_RING( CP_PACKET0( reg, 0 ) ); \ 1131112015Sanholt OUT_RING( val ); \ 1132112015Sanholt} while (0) 113395584Sanholt 1134145132Sanholt#define OUT_RING_TABLE( tab, sz ) do { \ 1135112015Sanholt int _size = (sz); \ 1136145132Sanholt int *_tab = (int *)(tab); \ 1137112015Sanholt \ 1138112015Sanholt if (write + _size > mask) { \ 1139145132Sanholt int _i = (mask+1) - write; \ 1140145132Sanholt _size -= _i; \ 1141145132Sanholt while (_i > 0) { \ 1142145132Sanholt *(int *)(ring + write) = *_tab++; \ 1143145132Sanholt write++; \ 1144145132Sanholt _i--; \ 1145145132Sanholt } \ 1146112015Sanholt write = 0; \ 1147145132Sanholt _tab += _i; \ 1148112015Sanholt } \ 1149145132Sanholt while (_size > 0) { \ 1150145132Sanholt *(ring + write) = *_tab++; \ 1151145132Sanholt write++; \ 1152145132Sanholt _size--; \ 1153145132Sanholt } \ 1154112015Sanholt write &= mask; \ 1155112015Sanholt} while (0) 1156112015Sanholt 1157145132Sanholt#endif /* __RADEON_DRV_H__ */ 1158