mga_drv.h revision 119098
1/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: head/sys/dev/drm/mga_drv.h 119098 2003-08-19 02:57:31Z anholt $ 31 */ 32 33#ifndef __MGA_DRV_H__ 34#define __MGA_DRV_H__ 35 36typedef struct drm_mga_primary_buffer { 37 u8 *start; 38 u8 *end; 39 int size; 40 41 u32 tail; 42 int space; 43 volatile long wrapped; 44 45 volatile u32 *status; 46 47 u32 last_flush; 48 u32 last_wrap; 49 50 u32 high_mark; 51} drm_mga_primary_buffer_t; 52 53typedef struct drm_mga_freelist { 54 struct drm_mga_freelist *next; 55 struct drm_mga_freelist *prev; 56 drm_mga_age_t age; 57 drm_buf_t *buf; 58} drm_mga_freelist_t; 59 60typedef struct { 61 drm_mga_freelist_t *list_entry; 62 int discard; 63 int dispatched; 64} drm_mga_buf_priv_t; 65 66typedef struct drm_mga_private { 67 drm_mga_primary_buffer_t prim; 68 drm_mga_sarea_t *sarea_priv; 69 70 drm_mga_freelist_t *head; 71 drm_mga_freelist_t *tail; 72 73 unsigned int warp_pipe; 74 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 75 76 int chipset; 77 int usec_timeout; 78 79 u32 clear_cmd; 80 u32 maccess; 81 82 unsigned int fb_cpp; 83 unsigned int front_offset; 84 unsigned int front_pitch; 85 unsigned int back_offset; 86 unsigned int back_pitch; 87 88 unsigned int depth_cpp; 89 unsigned int depth_offset; 90 unsigned int depth_pitch; 91 92 unsigned int texture_offset; 93 unsigned int texture_size; 94 95 drm_local_map_t *sarea; 96 drm_local_map_t *fb; 97 drm_local_map_t *mmio; 98 drm_local_map_t *status; 99 drm_local_map_t *warp; 100 drm_local_map_t *primary; 101 drm_local_map_t *buffers; 102 drm_local_map_t *agp_textures; 103} drm_mga_private_t; 104 105 /* mga_dma.c */ 106extern int mga_dma_init( DRM_IOCTL_ARGS ); 107extern int mga_dma_flush( DRM_IOCTL_ARGS ); 108extern int mga_dma_reset( DRM_IOCTL_ARGS ); 109extern int mga_dma_buffers( DRM_IOCTL_ARGS ); 110 111extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ); 112extern int mga_do_dma_idle( drm_mga_private_t *dev_priv ); 113extern int mga_do_dma_reset( drm_mga_private_t *dev_priv ); 114extern int mga_do_engine_reset( drm_mga_private_t *dev_priv ); 115extern int mga_do_cleanup_dma( drm_device_t *dev ); 116 117extern void mga_do_dma_flush( drm_mga_private_t *dev_priv ); 118extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ); 119extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ); 120 121extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); 122 123 /* mga_state.c */ 124extern int mga_dma_clear( DRM_IOCTL_ARGS ); 125extern int mga_dma_swap( DRM_IOCTL_ARGS ); 126extern int mga_dma_vertex( DRM_IOCTL_ARGS ); 127extern int mga_dma_indices( DRM_IOCTL_ARGS ); 128extern int mga_dma_iload( DRM_IOCTL_ARGS ); 129extern int mga_dma_blit( DRM_IOCTL_ARGS ); 130extern int mga_getparam( DRM_IOCTL_ARGS ); 131 132 /* mga_warp.c */ 133extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); 134extern int mga_warp_init( drm_mga_private_t *dev_priv ); 135 136#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() 137 138#if defined(__linux__) && defined(__alpha__) 139#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) 140#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) 141 142#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) 143#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) 144 145#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) 146#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) 147#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) 148#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) 149 150static inline u32 _MGA_READ(u32 *addr) 151{ 152 DRM_MEMORYBARRIER(); 153 return *(volatile u32 *)addr; 154} 155#else 156#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) 157#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) 158#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 159#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 160#endif 161 162#define DWGREG0 0x1c00 163#define DWGREG0_END 0x1dff 164#define DWGREG1 0x2c00 165#define DWGREG1_END 0x2dff 166 167#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) 168#define DMAREG0(r) (u8)((r - DWGREG0) >> 2) 169#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 170#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 171 172 173 174/* ================================================================ 175 * Helper macross... 176 */ 177 178#define MGA_EMIT_STATE( dev_priv, dirty ) \ 179do { \ 180 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ 181 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \ 182 mga_g400_emit_state( dev_priv ); \ 183 } else { \ 184 mga_g200_emit_state( dev_priv ); \ 185 } \ 186 } \ 187} while (0) 188 189#define WRAP_TEST_WITH_RETURN( dev_priv ) \ 190do { \ 191 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 192 if ( mga_is_idle( dev_priv ) ) { \ 193 mga_do_dma_wrap_end( dev_priv ); \ 194 } else if ( dev_priv->prim.space < \ 195 dev_priv->prim.high_mark ) { \ 196 if ( MGA_DMA_DEBUG ) \ 197 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ 198 return DRM_ERR(EBUSY); \ 199 } \ 200 } \ 201} while (0) 202 203#define WRAP_WAIT_WITH_RETURN( dev_priv ) \ 204do { \ 205 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 206 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ 207 if ( MGA_DMA_DEBUG ) \ 208 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ 209 return DRM_ERR(EBUSY); \ 210 } \ 211 mga_do_dma_wrap_end( dev_priv ); \ 212 } \ 213} while (0) 214 215 216/* ================================================================ 217 * Primary DMA command stream 218 */ 219 220#define MGA_VERBOSE 0 221 222#define DMA_LOCALS unsigned int write; volatile u8 *prim; 223 224#define DMA_BLOCK_SIZE (5 * sizeof(u32)) 225 226#define BEGIN_DMA( n ) \ 227do { \ 228 if ( MGA_VERBOSE ) { \ 229 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ 230 (n), __FUNCTION__ ); \ 231 DRM_INFO( " space=0x%x req=0x%Zx\n", \ 232 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ 233 } \ 234 prim = dev_priv->prim.start; \ 235 write = dev_priv->prim.tail; \ 236} while (0) 237 238#define BEGIN_DMA_WRAP() \ 239do { \ 240 if ( MGA_VERBOSE ) { \ 241 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ 242 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ 243 } \ 244 prim = dev_priv->prim.start; \ 245 write = dev_priv->prim.tail; \ 246} while (0) 247 248#define ADVANCE_DMA() \ 249do { \ 250 dev_priv->prim.tail = write; \ 251 if ( MGA_VERBOSE ) { \ 252 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ 253 write, dev_priv->prim.space ); \ 254 } \ 255} while (0) 256 257#define FLUSH_DMA() \ 258do { \ 259 if ( 0 ) { \ 260 DRM_INFO( "%s:\n", __FUNCTION__ ); \ 261 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ 262 dev_priv->prim.tail, \ 263 MGA_READ( MGA_PRIMADDRESS ) - \ 264 dev_priv->primary->offset ); \ 265 } \ 266 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 267 if ( dev_priv->prim.space < \ 268 dev_priv->prim.high_mark ) { \ 269 mga_do_dma_wrap_start( dev_priv ); \ 270 } else { \ 271 mga_do_dma_flush( dev_priv ); \ 272 } \ 273 } \ 274} while (0) 275 276/* Never use this, always use DMA_BLOCK(...) for primary DMA output. 277 */ 278#define DMA_WRITE( offset, val ) \ 279do { \ 280 if ( MGA_VERBOSE ) { \ 281 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ 282 (u32)(val), write + (offset) * sizeof(u32) ); \ 283 } \ 284 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ 285} while (0) 286 287#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ 288do { \ 289 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ 290 (DMAREG( reg1 ) << 8) | \ 291 (DMAREG( reg2 ) << 16) | \ 292 (DMAREG( reg3 ) << 24)) ); \ 293 DMA_WRITE( 1, val0 ); \ 294 DMA_WRITE( 2, val1 ); \ 295 DMA_WRITE( 3, val2 ); \ 296 DMA_WRITE( 4, val3 ); \ 297 write += DMA_BLOCK_SIZE; \ 298} while (0) 299 300 301/* Buffer aging via primary DMA stream head pointer. 302 */ 303 304#define SET_AGE( age, h, w ) \ 305do { \ 306 (age)->head = h; \ 307 (age)->wrap = w; \ 308} while (0) 309 310#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ 311 ( (age)->wrap == w && \ 312 (age)->head < h ) ) 313 314#define AGE_BUFFER( buf_priv ) \ 315do { \ 316 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ 317 if ( (buf_priv)->dispatched ) { \ 318 entry->age.head = (dev_priv->prim.tail + \ 319 dev_priv->primary->offset); \ 320 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ 321 } else { \ 322 entry->age.head = 0; \ 323 entry->age.wrap = 0; \ 324 } \ 325} while (0) 326 327 328#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 329 MGA_DWGENGSTS | \ 330 MGA_ENDPRDMASTS) 331#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ 332 MGA_ENDPRDMASTS) 333 334#define MGA_DMA_DEBUG 0 335 336 337 338/* A reduced set of the mga registers. 339 */ 340#define MGA_CRTC_INDEX 0x1fd4 341#define MGA_CRTC_DATA 0x1fd5 342 343/* CRTC11 */ 344#define MGA_VINTCLR (1 << 4) 345#define MGA_VINTEN (1 << 5) 346 347#define MGA_ALPHACTRL 0x2c7c 348#define MGA_AR0 0x1c60 349#define MGA_AR1 0x1c64 350#define MGA_AR2 0x1c68 351#define MGA_AR3 0x1c6c 352#define MGA_AR4 0x1c70 353#define MGA_AR5 0x1c74 354#define MGA_AR6 0x1c78 355 356#define MGA_CXBNDRY 0x1c80 357#define MGA_CXLEFT 0x1ca0 358#define MGA_CXRIGHT 0x1ca4 359 360#define MGA_DMAPAD 0x1c54 361#define MGA_DSTORG 0x2cb8 362#define MGA_DWGCTL 0x1c00 363# define MGA_OPCOD_MASK (15 << 0) 364# define MGA_OPCOD_TRAP (4 << 0) 365# define MGA_OPCOD_TEXTURE_TRAP (6 << 0) 366# define MGA_OPCOD_BITBLT (8 << 0) 367# define MGA_OPCOD_ILOAD (9 << 0) 368# define MGA_ATYPE_MASK (7 << 4) 369# define MGA_ATYPE_RPL (0 << 4) 370# define MGA_ATYPE_RSTR (1 << 4) 371# define MGA_ATYPE_ZI (3 << 4) 372# define MGA_ATYPE_BLK (4 << 4) 373# define MGA_ATYPE_I (7 << 4) 374# define MGA_LINEAR (1 << 7) 375# define MGA_ZMODE_MASK (7 << 8) 376# define MGA_ZMODE_NOZCMP (0 << 8) 377# define MGA_ZMODE_ZE (2 << 8) 378# define MGA_ZMODE_ZNE (3 << 8) 379# define MGA_ZMODE_ZLT (4 << 8) 380# define MGA_ZMODE_ZLTE (5 << 8) 381# define MGA_ZMODE_ZGT (6 << 8) 382# define MGA_ZMODE_ZGTE (7 << 8) 383# define MGA_SOLID (1 << 11) 384# define MGA_ARZERO (1 << 12) 385# define MGA_SGNZERO (1 << 13) 386# define MGA_SHIFTZERO (1 << 14) 387# define MGA_BOP_MASK (15 << 16) 388# define MGA_BOP_ZERO (0 << 16) 389# define MGA_BOP_DST (10 << 16) 390# define MGA_BOP_SRC (12 << 16) 391# define MGA_BOP_ONE (15 << 16) 392# define MGA_TRANS_SHIFT 20 393# define MGA_TRANS_MASK (15 << 20) 394# define MGA_BLTMOD_MASK (15 << 25) 395# define MGA_BLTMOD_BMONOLEF (0 << 25) 396# define MGA_BLTMOD_BMONOWF (4 << 25) 397# define MGA_BLTMOD_PLAN (1 << 25) 398# define MGA_BLTMOD_BFCOL (2 << 25) 399# define MGA_BLTMOD_BU32BGR (3 << 25) 400# define MGA_BLTMOD_BU32RGB (7 << 25) 401# define MGA_BLTMOD_BU24BGR (11 << 25) 402# define MGA_BLTMOD_BU24RGB (15 << 25) 403# define MGA_PATTERN (1 << 29) 404# define MGA_TRANSC (1 << 30) 405# define MGA_CLIPDIS (1 << 31) 406#define MGA_DWGSYNC 0x2c4c 407 408#define MGA_FCOL 0x1c24 409#define MGA_FIFOSTATUS 0x1e10 410#define MGA_FOGCOL 0x1cf4 411#define MGA_FXBNDRY 0x1c84 412#define MGA_FXLEFT 0x1ca8 413#define MGA_FXRIGHT 0x1cac 414 415#define MGA_ICLEAR 0x1e18 416# define MGA_SOFTRAPICLR (1 << 0) 417# define MGA_VLINEICLR (1 << 5) 418#define MGA_IEN 0x1e1c 419# define MGA_SOFTRAPIEN (1 << 0) 420# define MGA_VLINEIEN (1 << 5) 421 422#define MGA_LEN 0x1c5c 423 424#define MGA_MACCESS 0x1c04 425 426#define MGA_PITCH 0x1c8c 427#define MGA_PLNWT 0x1c1c 428#define MGA_PRIMADDRESS 0x1e58 429# define MGA_DMA_GENERAL (0 << 0) 430# define MGA_DMA_BLIT (1 << 0) 431# define MGA_DMA_VECTOR (2 << 0) 432# define MGA_DMA_VERTEX (3 << 0) 433#define MGA_PRIMEND 0x1e5c 434# define MGA_PRIMNOSTART (1 << 0) 435# define MGA_PAGPXFER (1 << 1) 436#define MGA_PRIMPTR 0x1e50 437# define MGA_PRIMPTREN0 (1 << 0) 438# define MGA_PRIMPTREN1 (1 << 1) 439 440#define MGA_RST 0x1e40 441# define MGA_SOFTRESET (1 << 0) 442# define MGA_SOFTEXTRST (1 << 1) 443 444#define MGA_SECADDRESS 0x2c40 445#define MGA_SECEND 0x2c44 446#define MGA_SETUPADDRESS 0x2cd0 447#define MGA_SETUPEND 0x2cd4 448#define MGA_SGN 0x1c58 449#define MGA_SOFTRAP 0x2c48 450#define MGA_SRCORG 0x2cb4 451# define MGA_SRMMAP_MASK (1 << 0) 452# define MGA_SRCMAP_FB (0 << 0) 453# define MGA_SRCMAP_SYSMEM (1 << 0) 454# define MGA_SRCACC_MASK (1 << 1) 455# define MGA_SRCACC_PCI (0 << 1) 456# define MGA_SRCACC_AGP (1 << 1) 457#define MGA_STATUS 0x1e14 458# define MGA_SOFTRAPEN (1 << 0) 459# define MGA_VSYNCPEN (1 << 4) 460# define MGA_VLINEPEN (1 << 5) 461# define MGA_DWGENGSTS (1 << 16) 462# define MGA_ENDPRDMASTS (1 << 17) 463#define MGA_STENCIL 0x2cc8 464#define MGA_STENCILCTL 0x2ccc 465 466#define MGA_TDUALSTAGE0 0x2cf8 467#define MGA_TDUALSTAGE1 0x2cfc 468#define MGA_TEXBORDERCOL 0x2c5c 469#define MGA_TEXCTL 0x2c30 470#define MGA_TEXCTL2 0x2c3c 471# define MGA_DUALTEX (1 << 7) 472# define MGA_G400_TC2_MAGIC (1 << 15) 473# define MGA_MAP1_ENABLE (1 << 31) 474#define MGA_TEXFILTER 0x2c58 475#define MGA_TEXHEIGHT 0x2c2c 476#define MGA_TEXORG 0x2c24 477# define MGA_TEXORGMAP_MASK (1 << 0) 478# define MGA_TEXORGMAP_FB (0 << 0) 479# define MGA_TEXORGMAP_SYSMEM (1 << 0) 480# define MGA_TEXORGACC_MASK (1 << 1) 481# define MGA_TEXORGACC_PCI (0 << 1) 482# define MGA_TEXORGACC_AGP (1 << 1) 483#define MGA_TEXORG1 0x2ca4 484#define MGA_TEXORG2 0x2ca8 485#define MGA_TEXORG3 0x2cac 486#define MGA_TEXORG4 0x2cb0 487#define MGA_TEXTRANS 0x2c34 488#define MGA_TEXTRANSHIGH 0x2c38 489#define MGA_TEXWIDTH 0x2c28 490 491#define MGA_WACCEPTSEQ 0x1dd4 492#define MGA_WCODEADDR 0x1e6c 493#define MGA_WFLAG 0x1dc4 494#define MGA_WFLAG1 0x1de0 495#define MGA_WFLAGNB 0x1e64 496#define MGA_WFLAGNB1 0x1e08 497#define MGA_WGETMSB 0x1dc8 498#define MGA_WIADDR 0x1dc0 499#define MGA_WIADDR2 0x1dd8 500# define MGA_WMODE_SUSPEND (0 << 0) 501# define MGA_WMODE_RESUME (1 << 0) 502# define MGA_WMODE_JUMP (2 << 0) 503# define MGA_WMODE_START (3 << 0) 504# define MGA_WAGP_ENABLE (1 << 2) 505#define MGA_WMISC 0x1e70 506# define MGA_WUCODECACHE_ENABLE (1 << 0) 507# define MGA_WMASTER_ENABLE (1 << 1) 508# define MGA_WCACHEFLUSH_ENABLE (1 << 3) 509#define MGA_WVRTXSZ 0x1dcc 510 511#define MGA_YBOT 0x1c9c 512#define MGA_YDST 0x1c90 513#define MGA_YDSTLEN 0x1c88 514#define MGA_YDSTORG 0x1c94 515#define MGA_YTOP 0x1c98 516 517#define MGA_ZORG 0x1c0c 518 519/* This finishes the current batch of commands 520 */ 521#define MGA_EXEC 0x0100 522 523/* Warp registers 524 */ 525#define MGA_WR0 0x2d00 526#define MGA_WR1 0x2d04 527#define MGA_WR2 0x2d08 528#define MGA_WR3 0x2d0c 529#define MGA_WR4 0x2d10 530#define MGA_WR5 0x2d14 531#define MGA_WR6 0x2d18 532#define MGA_WR7 0x2d1c 533#define MGA_WR8 0x2d20 534#define MGA_WR9 0x2d24 535#define MGA_WR10 0x2d28 536#define MGA_WR11 0x2d2c 537#define MGA_WR12 0x2d30 538#define MGA_WR13 0x2d34 539#define MGA_WR14 0x2d38 540#define MGA_WR15 0x2d3c 541#define MGA_WR16 0x2d40 542#define MGA_WR17 0x2d44 543#define MGA_WR18 0x2d48 544#define MGA_WR19 0x2d4c 545#define MGA_WR20 0x2d50 546#define MGA_WR21 0x2d54 547#define MGA_WR22 0x2d58 548#define MGA_WR23 0x2d5c 549#define MGA_WR24 0x2d60 550#define MGA_WR25 0x2d64 551#define MGA_WR26 0x2d68 552#define MGA_WR27 0x2d6c 553#define MGA_WR28 0x2d70 554#define MGA_WR29 0x2d74 555#define MGA_WR30 0x2d78 556#define MGA_WR31 0x2d7c 557#define MGA_WR32 0x2d80 558#define MGA_WR33 0x2d84 559#define MGA_WR34 0x2d88 560#define MGA_WR35 0x2d8c 561#define MGA_WR36 0x2d90 562#define MGA_WR37 0x2d94 563#define MGA_WR38 0x2d98 564#define MGA_WR39 0x2d9c 565#define MGA_WR40 0x2da0 566#define MGA_WR41 0x2da4 567#define MGA_WR42 0x2da8 568#define MGA_WR43 0x2dac 569#define MGA_WR44 0x2db0 570#define MGA_WR45 0x2db4 571#define MGA_WR46 0x2db8 572#define MGA_WR47 0x2dbc 573#define MGA_WR48 0x2dc0 574#define MGA_WR49 0x2dc4 575#define MGA_WR50 0x2dc8 576#define MGA_WR51 0x2dcc 577#define MGA_WR52 0x2dd0 578#define MGA_WR53 0x2dd4 579#define MGA_WR54 0x2dd8 580#define MGA_WR55 0x2ddc 581#define MGA_WR56 0x2de0 582#define MGA_WR57 0x2de4 583#define MGA_WR58 0x2de8 584#define MGA_WR59 0x2dec 585#define MGA_WR60 0x2df0 586#define MGA_WR61 0x2df4 587#define MGA_WR62 0x2df8 588#define MGA_WR63 0x2dfc 589# define MGA_G400_WR_MAGIC (1 << 6) 590# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 591 592 593#define MGA_ILOAD_ALIGN 64 594#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 595 596#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ 597 MGA_ATYPE_I | \ 598 MGA_ZMODE_NOZCMP | \ 599 MGA_ARZERO | \ 600 MGA_SGNZERO | \ 601 MGA_BOP_SRC | \ 602 (15 << MGA_TRANS_SHIFT)) 603 604#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ 605 MGA_ZMODE_NOZCMP | \ 606 MGA_SOLID | \ 607 MGA_ARZERO | \ 608 MGA_SGNZERO | \ 609 MGA_SHIFTZERO | \ 610 MGA_BOP_SRC | \ 611 (0 << MGA_TRANS_SHIFT) | \ 612 MGA_BLTMOD_BMONOLEF | \ 613 MGA_TRANSC | \ 614 MGA_CLIPDIS) 615 616#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ 617 MGA_ATYPE_RPL | \ 618 MGA_SGNZERO | \ 619 MGA_SHIFTZERO | \ 620 MGA_BOP_SRC | \ 621 (0 << MGA_TRANS_SHIFT) | \ 622 MGA_BLTMOD_BFCOL | \ 623 MGA_CLIPDIS) 624 625/* Simple idle test. 626 */ 627static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) 628{ 629 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 630 return ( status == MGA_ENDPRDMASTS ); 631} 632 633#endif 634