mga_drv.h revision 112015
15191Swollman/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- 25191Swollman * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 35191Swollman * 45191Swollman * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 55191Swollman * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 65191Swollman * All rights reserved. 75191Swollman * 85191Swollman * Permission is hereby granted, free of charge, to any person obtaining a 95191Swollman * copy of this software and associated documentation files (the "Software"), 105191Swollman * to deal in the Software without restriction, including without limitation 115191Swollman * the rights to use, copy, modify, merge, publish, distribute, sublicense, 125191Swollman * and/or sell copies of the Software, and to permit persons to whom the 135191Swollman * Software is furnished to do so, subject to the following conditions: 145191Swollman * 155191Swollman * The above copyright notice and this permission notice (including the next 165191Swollman * paragraph) shall be included in all copies or substantial portions of the 175191Swollman * Software. 185191Swollman * 195191Swollman * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 205191Swollman * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 215191Swollman * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 225191Swollman * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 235191Swollman * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 245191Swollman * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 255191Swollman * OTHER DEALINGS IN THE SOFTWARE. 265191Swollman * 275191Swollman * Authors: 285191Swollman * Gareth Hughes <gareth@valinux.com> 295191Swollman * 305191Swollman * $FreeBSD: head/sys/dev/drm/mga_drv.h 112015 2003-03-09 02:08:30Z anholt $ 315191Swollman */ 325191Swollman 335191Swollman#ifndef __MGA_DRV_H__ 3450477Speter#define __MGA_DRV_H__ 355191Swollman 365191Swollmantypedef struct drm_mga_primary_buffer { 375191Swollman u8 *start; 385191Swollman u8 *end; 395191Swollman int size; 405191Swollman 415191Swollman u32 tail; 425191Swollman int space; 435191Swollman volatile long wrapped; 445191Swollman 4571862Speter volatile u32 *status; 465191Swollman 475191Swollman u32 last_flush; 4824204Sbde u32 last_wrap; 495191Swollman 505191Swollman u32 high_mark; 515191Swollman} drm_mga_primary_buffer_t; 525191Swollman 535191Swollmantypedef struct drm_mga_freelist { 545191Swollman struct drm_mga_freelist *next; 5532350Seivind struct drm_mga_freelist *prev; 5654263Sshin drm_mga_age_t age; 575191Swollman drm_buf_t *buf; 585191Swollman} drm_mga_freelist_t; 595191Swollman 605191Swollmantypedef struct { 615191Swollman drm_mga_freelist_t *list_entry; 625191Swollman int discard; 635191Swollman int dispatched; 6478351Smarkm} drm_mga_buf_priv_t; 6510429Sbde 6678351Smarkmtypedef struct drm_mga_private { 6778351Smarkm drm_mga_primary_buffer_t prim; 6878351Smarkm drm_mga_sarea_t *sarea_priv; 6985074Sru 7078351Smarkm drm_mga_freelist_t *head; 715191Swollman drm_mga_freelist_t *tail; 725191Swollman 7378351Smarkm unsigned int warp_pipe; 745191Swollman unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 7578351Smarkm 765191Swollman int chipset; 775191Swollman int usec_timeout; 785191Swollman 795191Swollman u32 clear_cmd; 8041757Seivind u32 maccess; 8141757Seivind 825191Swollman unsigned int fb_cpp; 835191Swollman unsigned int front_offset; 845191Swollman unsigned int front_pitch; 8553115Sphk unsigned int back_offset; 865191Swollman unsigned int back_pitch; 8713937Swollman 885191Swollman unsigned int depth_cpp; 895191Swollman unsigned int depth_offset; 905191Swollman unsigned int depth_pitch; 9171862Speter 9271862Speter unsigned int texture_offset; 9371862Speter unsigned int texture_size; 9471862Speter 9571862Speter drm_local_map_t *sarea; 9671862Speter drm_local_map_t *fb; 9771862Speter drm_local_map_t *mmio; 9871862Speter drm_local_map_t *status; 9971862Speter drm_local_map_t *warp; 10071862Speter drm_local_map_t *primary; 10171862Speter drm_local_map_t *buffers; 10271862Speter drm_local_map_t *agp_textures; 10371862Speter} drm_mga_private_t; 10471862Speter 10571862Speter /* mga_dma.c */ 10671862Speterextern int mga_dma_init( DRM_IOCTL_ARGS ); 10771862Speterextern int mga_dma_flush( DRM_IOCTL_ARGS ); 10871862Speterextern int mga_dma_reset( DRM_IOCTL_ARGS ); 10971862Speterextern int mga_dma_buffers( DRM_IOCTL_ARGS ); 11071862Speter 11171862Speterextern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ); 11271862Speterextern int mga_do_dma_idle( drm_mga_private_t *dev_priv ); 11378351Smarkmextern int mga_do_dma_reset( drm_mga_private_t *dev_priv ); 11478351Smarkmextern int mga_do_engine_reset( drm_mga_private_t *dev_priv ); 1155191Swollmanextern int mga_do_cleanup_dma( drm_device_t *dev ); 1165191Swollman 11741757Seivindextern void mga_do_dma_flush( drm_mga_private_t *dev_priv ); 11810957Swollmanextern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ); 11910957Swollmanextern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ); 12010957Swollman 12110957Swollmanextern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); 12210957Swollman 12310957Swollman /* mga_state.c */ 12410957Swollmanextern int mga_dma_clear( DRM_IOCTL_ARGS ); 12510957Swollmanextern int mga_dma_swap( DRM_IOCTL_ARGS ); 12641757Seivindextern int mga_dma_vertex( DRM_IOCTL_ARGS ); 1275191Swollmanextern int mga_dma_indices( DRM_IOCTL_ARGS ); 1285191Swollmanextern int mga_dma_iload( DRM_IOCTL_ARGS ); 1295191Swollmanextern int mga_dma_blit( DRM_IOCTL_ARGS ); 1305191Swollmanextern int mga_getparam( DRM_IOCTL_ARGS ); 1315191Swollman 1325191Swollman /* mga_warp.c */ 1335191Swollmanextern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); 1345191Swollmanextern int mga_warp_init( drm_mga_private_t *dev_priv ); 1355191Swollman 1365191Swollman#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->primary) 1375191Swollman 1385191Swollman#if defined(__linux__) && defined(__alpha__) 1395191Swollman#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) 1408876Srgrimes#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) 14141757Seivind 1425191Swollman#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) 1435191Swollman#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) 1445191Swollman 1455191Swollman#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) 1465191Swollman#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) 1475191Swollman#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF( reg ) = val; } while (0) 1485191Swollman#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF8( reg ) = val; } while (0) 1495191Swollman 1505191Swollmanstatic inline u32 _MGA_READ(u32 *addr) 1515191Swollman{ 1525191Swollman DRM_READMEMORYBARRIER(dev_priv->mmio); 1535191Swollman return *(volatile u32 *)addr; 15485074Sru} 1555191Swollman#else 1565191Swollman#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) 1575191Swollman#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) 1585191Swollman#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 1595191Swollman#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 1605191Swollman#endif 1615191Swollman 1625191Swollman#define DWGREG0 0x1c00 16312611Sbde#define DWGREG0_END 0x1dff 16478351Smarkm#define DWGREG1 0x2c00 1655191Swollman#define DWGREG1_END 0x2dff 16678351Smarkm 16778351Smarkm#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) 16878351Smarkm#define DMAREG0(r) (u8)((r - DWGREG0) >> 2) 1695191Swollman#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 1705191Swollman#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 1715191Swollman 1725191Swollman 1735191Swollman 1745191Swollman/* ================================================================ 1755191Swollman * Helper macross... 17641757Seivind */ 1775191Swollman 1785191Swollman#define MGA_EMIT_STATE( dev_priv, dirty ) \ 1795191Swollmando { \ 1805191Swollman if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ 1815191Swollman if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \ 1825191Swollman mga_g400_emit_state( dev_priv ); \ 1835191Swollman } else { \ 1845191Swollman mga_g200_emit_state( dev_priv ); \ 1855191Swollman } \ 1865191Swollman } \ 1875191Swollman} while (0) 1885191Swollman 1895191Swollman#define LOCK_TEST_WITH_RETURN( dev ) \ 1905191Swollmando { \ 1915191Swollman if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ 1925191Swollman dev->lock.pid != DRM_CURRENTPID ) { \ 1935191Swollman DRM_ERROR( "%s called without lock held\n", \ 19454263Sshin __FUNCTION__ ); \ 19554263Sshin return DRM_ERR(EINVAL); \ 19654263Sshin } \ 19754263Sshin} while (0) 1985191Swollman 1995191Swollman#define WRAP_TEST_WITH_RETURN( dev_priv ) \ 2005191Swollmando { \ 2015191Swollman if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 2025191Swollman if ( mga_is_idle( dev_priv ) ) { \ 2035191Swollman mga_do_dma_wrap_end( dev_priv ); \ 2045191Swollman } else if ( dev_priv->prim.space < \ 2055191Swollman dev_priv->prim.high_mark ) { \ 2065191Swollman if ( MGA_DMA_DEBUG ) \ 2075191Swollman DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ 2085191Swollman return DRM_ERR(EBUSY); \ 2095191Swollman } \ 2105191Swollman } \ 2115191Swollman} while (0) 21287912Sjlemon 2135191Swollman#define WRAP_WAIT_WITH_RETURN( dev_priv ) \ 214do { \ 215 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 216 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ 217 if ( MGA_DMA_DEBUG ) \ 218 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ 219 return DRM_ERR(EBUSY); \ 220 } \ 221 mga_do_dma_wrap_end( dev_priv ); \ 222 } \ 223} while (0) 224 225 226/* ================================================================ 227 * Primary DMA command stream 228 */ 229 230#define MGA_VERBOSE 0 231 232#define DMA_LOCALS unsigned int write; volatile u8 *prim; 233 234#define DMA_BLOCK_SIZE (5 * sizeof(u32)) 235 236#define BEGIN_DMA( n ) \ 237do { \ 238 if ( MGA_VERBOSE ) { \ 239 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ 240 (n), __FUNCTION__ ); \ 241 DRM_INFO( " space=0x%x req=0x%x\n", \ 242 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ 243 } \ 244 prim = dev_priv->prim.start; \ 245 write = dev_priv->prim.tail; \ 246} while (0) 247 248#define BEGIN_DMA_WRAP() \ 249do { \ 250 if ( MGA_VERBOSE ) { \ 251 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ 252 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ 253 } \ 254 prim = dev_priv->prim.start; \ 255 write = dev_priv->prim.tail; \ 256} while (0) 257 258#define ADVANCE_DMA() \ 259do { \ 260 dev_priv->prim.tail = write; \ 261 if ( MGA_VERBOSE ) { \ 262 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ 263 write, dev_priv->prim.space ); \ 264 } \ 265} while (0) 266 267#define FLUSH_DMA() \ 268do { \ 269 if ( 0 ) { \ 270 DRM_INFO( "%s:\n", __FUNCTION__ ); \ 271 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ 272 dev_priv->prim.tail, \ 273 MGA_READ( MGA_PRIMADDRESS ) - \ 274 dev_priv->primary->offset ); \ 275 } \ 276 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 277 if ( dev_priv->prim.space < \ 278 dev_priv->prim.high_mark ) { \ 279 mga_do_dma_wrap_start( dev_priv ); \ 280 } else { \ 281 mga_do_dma_flush( dev_priv ); \ 282 } \ 283 } \ 284} while (0) 285 286/* Never use this, always use DMA_BLOCK(...) for primary DMA output. 287 */ 288#define DMA_WRITE( offset, val ) \ 289do { \ 290 if ( MGA_VERBOSE ) { \ 291 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04x\n", \ 292 (u32)(val), write + (offset) * sizeof(u32) ); \ 293 } \ 294 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ 295} while (0) 296 297#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ 298do { \ 299 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ 300 (DMAREG( reg1 ) << 8) | \ 301 (DMAREG( reg2 ) << 16) | \ 302 (DMAREG( reg3 ) << 24)) ); \ 303 DMA_WRITE( 1, val0 ); \ 304 DMA_WRITE( 2, val1 ); \ 305 DMA_WRITE( 3, val2 ); \ 306 DMA_WRITE( 4, val3 ); \ 307 write += DMA_BLOCK_SIZE; \ 308} while (0) 309 310 311/* Buffer aging via primary DMA stream head pointer. 312 */ 313 314#define SET_AGE( age, h, w ) \ 315do { \ 316 (age)->head = h; \ 317 (age)->wrap = w; \ 318} while (0) 319 320#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ 321 ( (age)->wrap == w && \ 322 (age)->head < h ) ) 323 324#define AGE_BUFFER( buf_priv ) \ 325do { \ 326 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ 327 if ( (buf_priv)->dispatched ) { \ 328 entry->age.head = (dev_priv->prim.tail + \ 329 dev_priv->primary->offset); \ 330 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ 331 } else { \ 332 entry->age.head = 0; \ 333 entry->age.wrap = 0; \ 334 } \ 335} while (0) 336 337 338#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 339 MGA_DWGENGSTS | \ 340 MGA_ENDPRDMASTS) 341#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ 342 MGA_ENDPRDMASTS) 343 344#define MGA_DMA_DEBUG 0 345 346 347 348/* A reduced set of the mga registers. 349 */ 350#define MGA_CRTC_INDEX 0x1fd4 351#define MGA_CRTC_DATA 0x1fd5 352 353/* CRTC11 */ 354#define MGA_VINTCLR (1 << 4) 355#define MGA_VINTEN (1 << 5) 356 357#define MGA_ALPHACTRL 0x2c7c 358#define MGA_AR0 0x1c60 359#define MGA_AR1 0x1c64 360#define MGA_AR2 0x1c68 361#define MGA_AR3 0x1c6c 362#define MGA_AR4 0x1c70 363#define MGA_AR5 0x1c74 364#define MGA_AR6 0x1c78 365 366#define MGA_CXBNDRY 0x1c80 367#define MGA_CXLEFT 0x1ca0 368#define MGA_CXRIGHT 0x1ca4 369 370#define MGA_DMAPAD 0x1c54 371#define MGA_DSTORG 0x2cb8 372#define MGA_DWGCTL 0x1c00 373# define MGA_OPCOD_MASK (15 << 0) 374# define MGA_OPCOD_TRAP (4 << 0) 375# define MGA_OPCOD_TEXTURE_TRAP (6 << 0) 376# define MGA_OPCOD_BITBLT (8 << 0) 377# define MGA_OPCOD_ILOAD (9 << 0) 378# define MGA_ATYPE_MASK (7 << 4) 379# define MGA_ATYPE_RPL (0 << 4) 380# define MGA_ATYPE_RSTR (1 << 4) 381# define MGA_ATYPE_ZI (3 << 4) 382# define MGA_ATYPE_BLK (4 << 4) 383# define MGA_ATYPE_I (7 << 4) 384# define MGA_LINEAR (1 << 7) 385# define MGA_ZMODE_MASK (7 << 8) 386# define MGA_ZMODE_NOZCMP (0 << 8) 387# define MGA_ZMODE_ZE (2 << 8) 388# define MGA_ZMODE_ZNE (3 << 8) 389# define MGA_ZMODE_ZLT (4 << 8) 390# define MGA_ZMODE_ZLTE (5 << 8) 391# define MGA_ZMODE_ZGT (6 << 8) 392# define MGA_ZMODE_ZGTE (7 << 8) 393# define MGA_SOLID (1 << 11) 394# define MGA_ARZERO (1 << 12) 395# define MGA_SGNZERO (1 << 13) 396# define MGA_SHIFTZERO (1 << 14) 397# define MGA_BOP_MASK (15 << 16) 398# define MGA_BOP_ZERO (0 << 16) 399# define MGA_BOP_DST (10 << 16) 400# define MGA_BOP_SRC (12 << 16) 401# define MGA_BOP_ONE (15 << 16) 402# define MGA_TRANS_SHIFT 20 403# define MGA_TRANS_MASK (15 << 20) 404# define MGA_BLTMOD_MASK (15 << 25) 405# define MGA_BLTMOD_BMONOLEF (0 << 25) 406# define MGA_BLTMOD_BMONOWF (4 << 25) 407# define MGA_BLTMOD_PLAN (1 << 25) 408# define MGA_BLTMOD_BFCOL (2 << 25) 409# define MGA_BLTMOD_BU32BGR (3 << 25) 410# define MGA_BLTMOD_BU32RGB (7 << 25) 411# define MGA_BLTMOD_BU24BGR (11 << 25) 412# define MGA_BLTMOD_BU24RGB (15 << 25) 413# define MGA_PATTERN (1 << 29) 414# define MGA_TRANSC (1 << 30) 415# define MGA_CLIPDIS (1 << 31) 416#define MGA_DWGSYNC 0x2c4c 417 418#define MGA_FCOL 0x1c24 419#define MGA_FIFOSTATUS 0x1e10 420#define MGA_FOGCOL 0x1cf4 421#define MGA_FXBNDRY 0x1c84 422#define MGA_FXLEFT 0x1ca8 423#define MGA_FXRIGHT 0x1cac 424 425#define MGA_ICLEAR 0x1e18 426# define MGA_SOFTRAPICLR (1 << 0) 427# define MGA_VLINEICLR (1 << 5) 428#define MGA_IEN 0x1e1c 429# define MGA_SOFTRAPIEN (1 << 0) 430# define MGA_VLINEIEN (1 << 5) 431 432#define MGA_LEN 0x1c5c 433 434#define MGA_MACCESS 0x1c04 435 436#define MGA_PITCH 0x1c8c 437#define MGA_PLNWT 0x1c1c 438#define MGA_PRIMADDRESS 0x1e58 439# define MGA_DMA_GENERAL (0 << 0) 440# define MGA_DMA_BLIT (1 << 0) 441# define MGA_DMA_VECTOR (2 << 0) 442# define MGA_DMA_VERTEX (3 << 0) 443#define MGA_PRIMEND 0x1e5c 444# define MGA_PRIMNOSTART (1 << 0) 445# define MGA_PAGPXFER (1 << 1) 446#define MGA_PRIMPTR 0x1e50 447# define MGA_PRIMPTREN0 (1 << 0) 448# define MGA_PRIMPTREN1 (1 << 1) 449 450#define MGA_RST 0x1e40 451# define MGA_SOFTRESET (1 << 0) 452# define MGA_SOFTEXTRST (1 << 1) 453 454#define MGA_SECADDRESS 0x2c40 455#define MGA_SECEND 0x2c44 456#define MGA_SETUPADDRESS 0x2cd0 457#define MGA_SETUPEND 0x2cd4 458#define MGA_SGN 0x1c58 459#define MGA_SOFTRAP 0x2c48 460#define MGA_SRCORG 0x2cb4 461# define MGA_SRMMAP_MASK (1 << 0) 462# define MGA_SRCMAP_FB (0 << 0) 463# define MGA_SRCMAP_SYSMEM (1 << 0) 464# define MGA_SRCACC_MASK (1 << 1) 465# define MGA_SRCACC_PCI (0 << 1) 466# define MGA_SRCACC_AGP (1 << 1) 467#define MGA_STATUS 0x1e14 468# define MGA_SOFTRAPEN (1 << 0) 469# define MGA_VSYNCPEN (1 << 4) 470# define MGA_VLINEPEN (1 << 5) 471# define MGA_DWGENGSTS (1 << 16) 472# define MGA_ENDPRDMASTS (1 << 17) 473#define MGA_STENCIL 0x2cc8 474#define MGA_STENCILCTL 0x2ccc 475 476#define MGA_TDUALSTAGE0 0x2cf8 477#define MGA_TDUALSTAGE1 0x2cfc 478#define MGA_TEXBORDERCOL 0x2c5c 479#define MGA_TEXCTL 0x2c30 480#define MGA_TEXCTL2 0x2c3c 481# define MGA_DUALTEX (1 << 7) 482# define MGA_G400_TC2_MAGIC (1 << 15) 483# define MGA_MAP1_ENABLE (1 << 31) 484#define MGA_TEXFILTER 0x2c58 485#define MGA_TEXHEIGHT 0x2c2c 486#define MGA_TEXORG 0x2c24 487# define MGA_TEXORGMAP_MASK (1 << 0) 488# define MGA_TEXORGMAP_FB (0 << 0) 489# define MGA_TEXORGMAP_SYSMEM (1 << 0) 490# define MGA_TEXORGACC_MASK (1 << 1) 491# define MGA_TEXORGACC_PCI (0 << 1) 492# define MGA_TEXORGACC_AGP (1 << 1) 493#define MGA_TEXORG1 0x2ca4 494#define MGA_TEXORG2 0x2ca8 495#define MGA_TEXORG3 0x2cac 496#define MGA_TEXORG4 0x2cb0 497#define MGA_TEXTRANS 0x2c34 498#define MGA_TEXTRANSHIGH 0x2c38 499#define MGA_TEXWIDTH 0x2c28 500 501#define MGA_WACCEPTSEQ 0x1dd4 502#define MGA_WCODEADDR 0x1e6c 503#define MGA_WFLAG 0x1dc4 504#define MGA_WFLAG1 0x1de0 505#define MGA_WFLAGNB 0x1e64 506#define MGA_WFLAGNB1 0x1e08 507#define MGA_WGETMSB 0x1dc8 508#define MGA_WIADDR 0x1dc0 509#define MGA_WIADDR2 0x1dd8 510# define MGA_WMODE_SUSPEND (0 << 0) 511# define MGA_WMODE_RESUME (1 << 0) 512# define MGA_WMODE_JUMP (2 << 0) 513# define MGA_WMODE_START (3 << 0) 514# define MGA_WAGP_ENABLE (1 << 2) 515#define MGA_WMISC 0x1e70 516# define MGA_WUCODECACHE_ENABLE (1 << 0) 517# define MGA_WMASTER_ENABLE (1 << 1) 518# define MGA_WCACHEFLUSH_ENABLE (1 << 3) 519#define MGA_WVRTXSZ 0x1dcc 520 521#define MGA_YBOT 0x1c9c 522#define MGA_YDST 0x1c90 523#define MGA_YDSTLEN 0x1c88 524#define MGA_YDSTORG 0x1c94 525#define MGA_YTOP 0x1c98 526 527#define MGA_ZORG 0x1c0c 528 529/* This finishes the current batch of commands 530 */ 531#define MGA_EXEC 0x0100 532 533/* Warp registers 534 */ 535#define MGA_WR0 0x2d00 536#define MGA_WR1 0x2d04 537#define MGA_WR2 0x2d08 538#define MGA_WR3 0x2d0c 539#define MGA_WR4 0x2d10 540#define MGA_WR5 0x2d14 541#define MGA_WR6 0x2d18 542#define MGA_WR7 0x2d1c 543#define MGA_WR8 0x2d20 544#define MGA_WR9 0x2d24 545#define MGA_WR10 0x2d28 546#define MGA_WR11 0x2d2c 547#define MGA_WR12 0x2d30 548#define MGA_WR13 0x2d34 549#define MGA_WR14 0x2d38 550#define MGA_WR15 0x2d3c 551#define MGA_WR16 0x2d40 552#define MGA_WR17 0x2d44 553#define MGA_WR18 0x2d48 554#define MGA_WR19 0x2d4c 555#define MGA_WR20 0x2d50 556#define MGA_WR21 0x2d54 557#define MGA_WR22 0x2d58 558#define MGA_WR23 0x2d5c 559#define MGA_WR24 0x2d60 560#define MGA_WR25 0x2d64 561#define MGA_WR26 0x2d68 562#define MGA_WR27 0x2d6c 563#define MGA_WR28 0x2d70 564#define MGA_WR29 0x2d74 565#define MGA_WR30 0x2d78 566#define MGA_WR31 0x2d7c 567#define MGA_WR32 0x2d80 568#define MGA_WR33 0x2d84 569#define MGA_WR34 0x2d88 570#define MGA_WR35 0x2d8c 571#define MGA_WR36 0x2d90 572#define MGA_WR37 0x2d94 573#define MGA_WR38 0x2d98 574#define MGA_WR39 0x2d9c 575#define MGA_WR40 0x2da0 576#define MGA_WR41 0x2da4 577#define MGA_WR42 0x2da8 578#define MGA_WR43 0x2dac 579#define MGA_WR44 0x2db0 580#define MGA_WR45 0x2db4 581#define MGA_WR46 0x2db8 582#define MGA_WR47 0x2dbc 583#define MGA_WR48 0x2dc0 584#define MGA_WR49 0x2dc4 585#define MGA_WR50 0x2dc8 586#define MGA_WR51 0x2dcc 587#define MGA_WR52 0x2dd0 588#define MGA_WR53 0x2dd4 589#define MGA_WR54 0x2dd8 590#define MGA_WR55 0x2ddc 591#define MGA_WR56 0x2de0 592#define MGA_WR57 0x2de4 593#define MGA_WR58 0x2de8 594#define MGA_WR59 0x2dec 595#define MGA_WR60 0x2df0 596#define MGA_WR61 0x2df4 597#define MGA_WR62 0x2df8 598#define MGA_WR63 0x2dfc 599# define MGA_G400_WR_MAGIC (1 << 6) 600# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 601 602 603#define MGA_ILOAD_ALIGN 64 604#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 605 606#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ 607 MGA_ATYPE_I | \ 608 MGA_ZMODE_NOZCMP | \ 609 MGA_ARZERO | \ 610 MGA_SGNZERO | \ 611 MGA_BOP_SRC | \ 612 (15 << MGA_TRANS_SHIFT)) 613 614#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ 615 MGA_ZMODE_NOZCMP | \ 616 MGA_SOLID | \ 617 MGA_ARZERO | \ 618 MGA_SGNZERO | \ 619 MGA_SHIFTZERO | \ 620 MGA_BOP_SRC | \ 621 (0 << MGA_TRANS_SHIFT) | \ 622 MGA_BLTMOD_BMONOLEF | \ 623 MGA_TRANSC | \ 624 MGA_CLIPDIS) 625 626#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ 627 MGA_ATYPE_RPL | \ 628 MGA_SGNZERO | \ 629 MGA_SHIFTZERO | \ 630 MGA_BOP_SRC | \ 631 (0 << MGA_TRANS_SHIFT) | \ 632 MGA_BLTMOD_BFCOL | \ 633 MGA_CLIPDIS) 634 635/* Simple idle test. 636 */ 637static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) 638{ 639 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 640 return ( status == MGA_ENDPRDMASTS ); 641} 642 643#endif 644