i915_drv.h revision 189047
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drv.h 189047 2009-02-25 18:22:57Z rnoland $"); 32 33#ifndef _I915_DRV_H_ 34#define _I915_DRV_H_ 35 36/* General customization: 37 */ 38 39#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 40 41#define DRIVER_NAME "i915" 42#define DRIVER_DESC "Intel Graphics" 43#define DRIVER_DATE "20080730" 44 45#if defined(__linux__) 46#define I915_HAVE_FENCE 47#define I915_HAVE_BUFFER 48#define I915_HAVE_GEM 49#endif 50 51/* Interface history: 52 * 53 * 1.1: Original. 54 * 1.2: Add Power Management 55 * 1.3: Add vblank support 56 * 1.4: Fix cmdbuffer path, add heap destroy 57 * 1.5: Add vblank pipe configuration 58 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 59 * - Support vertical blank on secondary display pipe 60 * 1.8: New ioctl for ARB_Occlusion_Query 61 * 1.9: Usable page flipping and triple buffering 62 * 1.10: Plane/pipe disentangling 63 * 1.11: TTM superioctl 64 * 1.12: TTM relocation optimization 65 */ 66#define DRIVER_MAJOR 1 67#if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER) 68#define DRIVER_MINOR 13 69#else 70#define DRIVER_MINOR 6 71#endif 72#define DRIVER_PATCHLEVEL 0 73 74enum pipe { 75 PIPE_A = 0, 76 PIPE_B, 77}; 78 79#ifdef I915_HAVE_BUFFER 80#define I915_MAX_VALIDATE_BUFFERS 4096 81struct drm_i915_validate_buffer; 82#endif 83 84#define WATCH_COHERENCY 0 85#define WATCH_BUF 0 86#define WATCH_EXEC 0 87#define WATCH_LRU 0 88#define WATCH_RELOC 0 89#define WATCH_INACTIVE 0 90#define WATCH_PWRITE 0 91 92typedef struct _drm_i915_ring_buffer { 93 int tail_mask; 94 unsigned long Size; 95 u8 *virtual_start; 96 int head; 97 int tail; 98 int space; 99 drm_local_map_t map; 100 struct drm_gem_object *ring_obj; 101} drm_i915_ring_buffer_t; 102 103struct mem_block { 104 struct mem_block *next; 105 struct mem_block *prev; 106 int start; 107 int size; 108 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 109}; 110 111typedef struct _drm_i915_vbl_swap { 112 struct list_head head; 113 drm_drawable_t drw_id; 114 unsigned int plane; 115 unsigned int sequence; 116 int flip; 117} drm_i915_vbl_swap_t; 118 119#ifdef __linux__ 120struct opregion_header; 121struct opregion_acpi; 122struct opregion_swsci; 123struct opregion_asle; 124 125struct intel_opregion { 126 struct opregion_header *header; 127 struct opregion_acpi *acpi; 128 struct opregion_swsci *swsci; 129 struct opregion_asle *asle; 130 131 int enabled; 132}; 133#endif 134 135typedef struct drm_i915_private { 136 struct drm_device *dev; 137 138 drm_local_map_t *sarea; 139 drm_local_map_t *mmio_map; 140 141 drm_i915_sarea_t *sarea_priv; 142 drm_i915_ring_buffer_t ring; 143 144 drm_dma_handle_t *status_page_dmah; 145 void *hw_status_page; 146 dma_addr_t dma_status_page; 147 uint32_t counter; 148 unsigned int status_gfx_addr; 149 drm_local_map_t hws_map; 150 struct drm_gem_object *hws_obj; 151 152 unsigned int cpp; 153 154 wait_queue_head_t irq_queue; 155 atomic_t irq_received; 156 157 int tex_lru_log_granularity; 158 int allow_batchbuffer; 159 struct mem_block *agp_heap; 160 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 161 int vblank_pipe; 162 DRM_SPINTYPE user_irq_lock; 163 int user_irq_refcount; 164 int fence_irq_on; 165 uint32_t irq_mask_reg; 166 int irq_enabled; 167 168#ifdef I915_HAVE_FENCE 169 uint32_t flush_sequence; 170 uint32_t flush_flags; 171 uint32_t flush_pending; 172 uint32_t saved_flush_status; 173#endif 174#ifdef I915_HAVE_BUFFER 175 void *agp_iomap; 176 unsigned int max_validate_buffers; 177 struct mutex cmdbuf_mutex; 178 struct drm_i915_validate_buffer *val_bufs; 179#endif 180 181#if defined(I915_HAVE_BUFFER) 182 /* DRI2 sarea */ 183 struct drm_buffer_object *sarea_bo; 184 struct drm_bo_kmap_obj sarea_kmap; 185#endif 186 187#ifdef __linux__ 188 struct intel_opregion opregion; 189#endif 190 191 /* Register state */ 192 u8 saveLBB; 193 u32 saveDSPACNTR; 194 u32 saveDSPBCNTR; 195 u32 saveDSPARB; 196 u32 savePIPEACONF; 197 u32 savePIPEBCONF; 198 u32 savePIPEASRC; 199 u32 savePIPEBSRC; 200 u32 saveFPA0; 201 u32 saveFPA1; 202 u32 saveDPLL_A; 203 u32 saveDPLL_A_MD; 204 u32 saveHTOTAL_A; 205 u32 saveHBLANK_A; 206 u32 saveHSYNC_A; 207 u32 saveVTOTAL_A; 208 u32 saveVBLANK_A; 209 u32 saveVSYNC_A; 210 u32 saveBCLRPAT_A; 211 u32 savePIPEASTAT; 212 u32 saveDSPASTRIDE; 213 u32 saveDSPASIZE; 214 u32 saveDSPAPOS; 215 u32 saveDSPAADDR; 216 u32 saveDSPASURF; 217 u32 saveDSPATILEOFF; 218 u32 savePFIT_PGM_RATIOS; 219 u32 saveBLC_PWM_CTL; 220 u32 saveBLC_PWM_CTL2; 221 u32 saveFPB0; 222 u32 saveFPB1; 223 u32 saveDPLL_B; 224 u32 saveDPLL_B_MD; 225 u32 saveHTOTAL_B; 226 u32 saveHBLANK_B; 227 u32 saveHSYNC_B; 228 u32 saveVTOTAL_B; 229 u32 saveVBLANK_B; 230 u32 saveVSYNC_B; 231 u32 saveBCLRPAT_B; 232 u32 savePIPEBSTAT; 233 u32 saveDSPBSTRIDE; 234 u32 saveDSPBSIZE; 235 u32 saveDSPBPOS; 236 u32 saveDSPBADDR; 237 u32 saveDSPBSURF; 238 u32 saveDSPBTILEOFF; 239 u32 saveVGA0; 240 u32 saveVGA1; 241 u32 saveVGA_PD; 242 u32 saveVGACNTRL; 243 u32 saveADPA; 244 u32 saveLVDS; 245 u32 savePP_ON_DELAYS; 246 u32 savePP_OFF_DELAYS; 247 u32 saveDVOA; 248 u32 saveDVOB; 249 u32 saveDVOC; 250 u32 savePP_ON; 251 u32 savePP_OFF; 252 u32 savePP_CONTROL; 253 u32 savePP_DIVISOR; 254 u32 savePFIT_CONTROL; 255 u32 save_palette_a[256]; 256 u32 save_palette_b[256]; 257 u32 saveFBC_CFB_BASE; 258 u32 saveFBC_LL_BASE; 259 u32 saveFBC_CONTROL; 260 u32 saveFBC_CONTROL2; 261 u32 saveIER; 262 u32 saveIIR; 263 u32 saveIMR; 264 u32 saveCACHE_MODE_0; 265 u32 saveD_STATE; 266 u32 saveCG_2D_DIS; 267 u32 saveMI_ARB_STATE; 268 u32 saveSWF0[16]; 269 u32 saveSWF1[16]; 270 u32 saveSWF2[3]; 271 u8 saveMSR; 272 u8 saveSR[8]; 273 u8 saveGR[25]; 274 u8 saveAR_INDEX; 275 u8 saveAR[21]; 276 u8 saveDACMASK; 277 u8 saveDACDATA[256*3]; /* 256 3-byte colors */ 278 u8 saveCR[37]; 279 280 struct { 281#ifdef __linux__ 282 struct drm_mm gtt_space; 283#endif 284 /** 285 * List of objects currently involved in rendering from the 286 * ringbuffer. 287 * 288 * A reference is held on the buffer while on this list. 289 */ 290 struct list_head active_list; 291 292 /** 293 * List of objects which are not in the ringbuffer but which 294 * still have a write_domain which needs to be flushed before 295 * unbinding. 296 * 297 * A reference is held on the buffer while on this list. 298 */ 299 struct list_head flushing_list; 300 301 /** 302 * LRU list of objects which are not in the ringbuffer and 303 * are ready to unbind, but are still in the GTT. 304 * 305 * A reference is not held on the buffer while on this list, 306 * as merely being GTT-bound shouldn't prevent its being 307 * freed, and we'll pull it off the list in the free path. 308 */ 309 struct list_head inactive_list; 310 311 /** 312 * List of breadcrumbs associated with GPU requests currently 313 * outstanding. 314 */ 315 struct list_head request_list; 316#ifdef __linux__ 317 /** 318 * We leave the user IRQ off as much as possible, 319 * but this means that requests will finish and never 320 * be retired once the system goes idle. Set a timer to 321 * fire periodically while the ring is running. When it 322 * fires, go retire requests. 323 */ 324 struct delayed_work retire_work; 325#endif 326 uint32_t next_gem_seqno; 327 328 /** 329 * Waiting sequence number, if any 330 */ 331 uint32_t waiting_gem_seqno; 332 333 /** 334 * Last seq seen at irq time 335 */ 336 uint32_t irq_gem_seqno; 337 338 /** 339 * Flag if the X Server, and thus DRM, is not currently in 340 * control of the device. 341 * 342 * This is set between LeaveVT and EnterVT. It needs to be 343 * replaced with a semaphore. It also needs to be 344 * transitioned away from for kernel modesetting. 345 */ 346 int suspended; 347 348 /** 349 * Flag if the hardware appears to be wedged. 350 * 351 * This is set when attempts to idle the device timeout. 352 * It prevents command submission from occuring and makes 353 * every pending request fail 354 */ 355 int wedged; 356 357 /** Bit 6 swizzling required for X tiling */ 358 uint32_t bit_6_swizzle_x; 359 /** Bit 6 swizzling required for Y tiling */ 360 uint32_t bit_6_swizzle_y; 361 } mm; 362} drm_i915_private_t; 363 364struct drm_i915_file_private { 365 struct { 366 uint32_t last_gem_seqno; 367 uint32_t last_gem_throttle_seqno; 368 } mm; 369}; 370 371enum intel_chip_family { 372 CHIP_I8XX = 0x01, 373 CHIP_I9XX = 0x02, 374 CHIP_I915 = 0x04, 375 CHIP_I965 = 0x08, 376}; 377 378/** driver private structure attached to each drm_gem_object */ 379struct drm_i915_gem_object { 380 struct drm_gem_object *obj; 381 382 /** Current space allocated to this object in the GTT, if any. */ 383 struct drm_mm_node *gtt_space; 384 385 /** This object's place on the active/flushing/inactive lists */ 386 struct list_head list; 387 388 /** 389 * This is set if the object is on the active or flushing lists 390 * (has pending rendering), and is not set if it's on inactive (ready 391 * to be unbound). 392 */ 393 int active; 394 395 /** 396 * This is set if the object has been written to since last bound 397 * to the GTT 398 */ 399 int dirty; 400 401 /** AGP memory structure for our GTT binding. */ 402 DRM_AGP_MEM *agp_mem; 403 404 struct page **page_list; 405 406 /** 407 * Current offset of the object in GTT space. 408 * 409 * This is the same as gtt_space->start 410 */ 411 uint32_t gtt_offset; 412 413 /** Boolean whether this object has a valid gtt offset. */ 414 int gtt_bound; 415 416 /** How many users have pinned this object in GTT space */ 417 int pin_count; 418 419 /** Breadcrumb of last rendering to the buffer. */ 420 uint32_t last_rendering_seqno; 421 422 /** Current tiling mode for the object. */ 423 uint32_t tiling_mode; 424 425 /** 426 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 427 * GEM_DOMAIN_CPU is not in the object's read domain. 428 */ 429 uint8_t *page_cpu_valid; 430}; 431 432/** 433 * Request queue structure. 434 * 435 * The request queue allows us to note sequence numbers that have been emitted 436 * and may be associated with active buffers to be retired. 437 * 438 * By keeping this list, we can avoid having to do questionable 439 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 440 * an emission time with seqnos for tracking how far ahead of the GPU we are. 441 */ 442struct drm_i915_gem_request { 443 /** GEM sequence number associated with this request. */ 444 uint32_t seqno; 445 446 /** Time at which this request was emitted, in jiffies. */ 447 unsigned long emitted_jiffies; 448 449 /** Cache domains that were flushed at the start of the request. */ 450 uint32_t flush_domains; 451 452 struct list_head list; 453}; 454 455extern struct drm_ioctl_desc i915_ioctls[]; 456extern int i915_max_ioctl; 457 458 /* i915_dma.c */ 459extern void i915_kernel_lost_context(struct drm_device * dev); 460extern int i915_driver_load(struct drm_device *, unsigned long flags); 461extern int i915_driver_unload(struct drm_device *); 462extern void i915_driver_lastclose(struct drm_device * dev); 463extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 464extern void i915_driver_preclose(struct drm_device *dev, 465 struct drm_file *file_priv); 466extern void i915_driver_postclose(struct drm_device *dev, 467 struct drm_file *file_priv); 468extern int i915_driver_device_is_agp(struct drm_device * dev); 469extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 470 unsigned long arg); 471extern void i915_emit_breadcrumb(struct drm_device *dev); 472extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync); 473extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush); 474extern int i915_driver_firstopen(struct drm_device *dev); 475extern int i915_dispatch_batchbuffer(struct drm_device * dev, 476 drm_i915_batchbuffer_t * batch); 477extern int i915_quiescent(struct drm_device *dev); 478extern int i915_init_hardware_status(struct drm_device *dev); 479extern void i915_free_hardware_status(struct drm_device *dev); 480 481int i915_emit_box(struct drm_device * dev, 482 struct drm_clip_rect __user * boxes, 483 int i, int DR1, int DR4); 484 485/* i915_irq.c */ 486extern int i915_irq_emit(struct drm_device *dev, void *data, 487 struct drm_file *file_priv); 488extern int i915_irq_wait(struct drm_device *dev, void *data, 489 struct drm_file *file_priv); 490 491extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 492extern void i915_driver_irq_preinstall(struct drm_device * dev); 493extern int i915_driver_irq_postinstall(struct drm_device * dev); 494extern void i915_driver_irq_uninstall(struct drm_device * dev); 495extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 496 struct drm_file *file_priv); 497extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 498 struct drm_file *file_priv); 499extern int i915_emit_irq(struct drm_device * dev); 500extern int i915_wait_irq(struct drm_device * dev, int irq_nr); 501extern int i915_enable_vblank(struct drm_device *dev, int crtc); 502extern void i915_disable_vblank(struct drm_device *dev, int crtc); 503extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 504extern int i915_vblank_swap(struct drm_device *dev, void *data, 505 struct drm_file *file_priv); 506extern void i915_user_irq_on(drm_i915_private_t *dev_priv); 507extern void i915_user_irq_off(drm_i915_private_t *dev_priv); 508 509/* i915_mem.c */ 510extern int i915_mem_alloc(struct drm_device *dev, void *data, 511 struct drm_file *file_priv); 512extern int i915_mem_free(struct drm_device *dev, void *data, 513 struct drm_file *file_priv); 514extern int i915_mem_init_heap(struct drm_device *dev, void *data, 515 struct drm_file *file_priv); 516extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 517 struct drm_file *file_priv); 518extern void i915_mem_takedown(struct mem_block **heap); 519extern void i915_mem_release(struct drm_device * dev, 520 struct drm_file *file_priv, 521 struct mem_block *heap); 522 523/* i915_suspend.c */ 524extern int i915_save_state(struct drm_device *dev); 525extern int i915_restore_state(struct drm_device *dev); 526 527#ifdef I915_HAVE_FENCE 528/* i915_fence.c */ 529extern void i915_fence_handler(struct drm_device *dev); 530extern void i915_invalidate_reported_sequence(struct drm_device *dev); 531 532#endif 533 534#ifdef I915_HAVE_BUFFER 535/* i915_buffer.c */ 536extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev); 537extern int i915_fence_type(struct drm_buffer_object *bo, uint32_t *fclass, 538 uint32_t *type); 539extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags); 540extern int i915_init_mem_type(struct drm_device *dev, uint32_t type, 541 struct drm_mem_type_manager *man); 542extern uint64_t i915_evict_flags(struct drm_buffer_object *bo); 543extern int i915_move(struct drm_buffer_object *bo, int evict, 544 int no_wait, struct drm_bo_mem_reg *new_mem); 545void i915_flush_ttm(struct drm_ttm *ttm); 546/* i915_execbuf.c */ 547int i915_execbuffer(struct drm_device *dev, void *data, 548 struct drm_file *file_priv); 549/* i915_gem.c */ 550int i915_gem_init_ioctl(struct drm_device *dev, void *data, 551 struct drm_file *file_priv); 552int i915_gem_create_ioctl(struct drm_device *dev, void *data, 553 struct drm_file *file_priv); 554int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 555 struct drm_file *file_priv); 556int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 557 struct drm_file *file_priv); 558int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 559 struct drm_file *file_priv); 560int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 561 struct drm_file *file_priv); 562int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 563 struct drm_file *file_priv); 564int i915_gem_execbuffer(struct drm_device *dev, void *data, 565 struct drm_file *file_priv); 566int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 567 struct drm_file *file_priv); 568int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 569 struct drm_file *file_priv); 570int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 571 struct drm_file *file_priv); 572int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 573 struct drm_file *file_priv); 574int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 575 struct drm_file *file_priv); 576int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 577 struct drm_file *file_priv); 578int i915_gem_set_tiling(struct drm_device *dev, void *data, 579 struct drm_file *file_priv); 580int i915_gem_get_tiling(struct drm_device *dev, void *data, 581 struct drm_file *file_priv); 582void i915_gem_load(struct drm_device *dev); 583int i915_gem_proc_init(struct drm_minor *minor); 584void i915_gem_proc_cleanup(struct drm_minor *minor); 585int i915_gem_init_object(struct drm_gem_object *obj); 586void i915_gem_free_object(struct drm_gem_object *obj); 587int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 588void i915_gem_object_unpin(struct drm_gem_object *obj); 589void i915_gem_lastclose(struct drm_device *dev); 590uint32_t i915_get_gem_seqno(struct drm_device *dev); 591void i915_gem_retire_requests(struct drm_device *dev); 592void i915_gem_retire_work_handler(struct work_struct *work); 593void i915_gem_clflush_object(struct drm_gem_object *obj); 594#endif 595 596/* i915_gem_tiling.c */ 597void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 598 599/* i915_gem_debug.c */ 600#if WATCH_INACTIVE 601void i915_verify_inactive(struct drm_device *dev, char *file, int line); 602#else 603#define i915_verify_inactive(dev,file,line) 604#endif 605void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 606void i915_gem_dump_object(struct drm_gem_object *obj, int len, 607 const char *where, uint32_t mark); 608void i915_dump_lru(struct drm_device *dev, const char *where); 609 610#ifdef __linux__ 611/* i915_opregion.c */ 612extern int intel_opregion_init(struct drm_device *dev); 613extern void intel_opregion_free(struct drm_device *dev); 614extern void opregion_asle_intr(struct drm_device *dev); 615extern void opregion_enable_asle(struct drm_device *dev); 616#endif 617 618#ifdef __linux__ 619#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) 620extern void intel_init_chipset_flush_compat(struct drm_device *dev); 621extern void intel_fini_chipset_flush_compat(struct drm_device *dev); 622#endif 623#endif 624 625#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 626#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 627#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 628#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 629#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg)) 630#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val)) 631 632#if defined(__FreeBSD__) 633typedef boolean_t bool; 634#endif 635 636#define I915_VERBOSE 0 637#define I915_RING_VALIDATE 0 638 639#define PRIMARY_RINGBUFFER_SIZE (128*1024) 640 641#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 642 volatile char *virt; 643 644#if I915_RING_VALIDATE 645void i915_ring_validate(struct drm_device *dev, const char *func, int line); 646#define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__) 647#else 648#define I915_RING_DO_VALIDATE(dev) 649#endif 650 651#define BEGIN_LP_RING(n) do { \ 652 if (I915_VERBOSE) \ 653 DRM_DEBUG("BEGIN_LP_RING(%d)\n", \ 654 (n)); \ 655 I915_RING_DO_VALIDATE(dev); \ 656 if (dev_priv->ring.space < (n)*4) \ 657 i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 658 outcount = 0; \ 659 outring = dev_priv->ring.tail; \ 660 ringmask = dev_priv->ring.tail_mask; \ 661 virt = dev_priv->ring.virtual_start; \ 662} while (0) 663 664#define OUT_RING(n) do { \ 665 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 666 *(volatile unsigned int *)(virt + outring) = (n); \ 667 outcount++; \ 668 outring += 4; \ 669 outring &= ringmask; \ 670} while (0) 671 672#define ADVANCE_LP_RING() do { \ 673 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 674 I915_RING_DO_VALIDATE(dev); \ 675 dev_priv->ring.tail = outring; \ 676 dev_priv->ring.space -= outcount * 4; \ 677 I915_WRITE(PRB0_TAIL, outring); \ 678} while(0) 679 680extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 681 682#define BREADCRUMB_BITS 31 683#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1) 684 685#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) 686/** 687 * Reads a dword out of the status page, which is written to from the command 688 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 689 * MI_STORE_DATA_IMM. 690 * 691 * The following dwords have a reserved meaning: 692 * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 693 * 4: ring 0 head pointer 694 * 5: ring 1 head pointer (915-class) 695 * 6: ring 2 head pointer (915-class) 696 * 697 * The area from dword 0x10 to 0x3ff is available for driver usage. 698 */ 699#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 700#define I915_GEM_HWS_INDEX 0x10 701 702/* MCH MMIO space */ 703/** 915-945 and GM965 MCH register controlling DRAM channel access */ 704#define DCC 0x200 705#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 706#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 707#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 708#define DCC_ADDRESSING_MODE_MASK (3 << 0) 709#define DCC_CHANNEL_XOR_DISABLE (1 << 10) 710 711/** 965 MCH register controlling DRAM channel configuration */ 712#define CHDECMISC 0x111 713#define CHDECMISC_FLEXMEMORY (1 << 1) 714 715/* 716 * The Bridge device's PCI config space has information about the 717 * fb aperture size and the amount of pre-reserved memory. 718 */ 719#define INTEL_GMCH_CTRL 0x52 720#define INTEL_GMCH_ENABLED 0x4 721#define INTEL_GMCH_MEM_MASK 0x1 722#define INTEL_GMCH_MEM_64M 0x1 723#define INTEL_GMCH_MEM_128M 0 724 725#define INTEL_855_GMCH_GMS_MASK (0x7 << 4) 726#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) 727#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) 728#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) 729#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) 730#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) 731#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) 732 733#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) 734#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) 735 736/* PCI config space */ 737 738#define HPLLCC 0xc0 /* 855 only */ 739#define GC_CLOCK_CONTROL_MASK (3 << 0) 740#define GC_CLOCK_133_200 (0 << 0) 741#define GC_CLOCK_100_200 (1 << 0) 742#define GC_CLOCK_100_133 (2 << 0) 743#define GC_CLOCK_166_250 (3 << 0) 744#define GCFGC 0xf0 /* 915+ only */ 745#define GC_LOW_FREQUENCY_ENABLE (1 << 7) 746#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 747#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 748#define GC_DISPLAY_CLOCK_MASK (7 << 4) 749#define LBB 0xf4 750 751/* VGA stuff */ 752 753#define VGA_ST01_MDA 0x3ba 754#define VGA_ST01_CGA 0x3da 755 756#define VGA_MSR_WRITE 0x3c2 757#define VGA_MSR_READ 0x3cc 758#define VGA_MSR_MEM_EN (1<<1) 759#define VGA_MSR_CGA_MODE (1<<0) 760 761#define VGA_SR_INDEX 0x3c4 762#define VGA_SR_DATA 0x3c5 763 764#define VGA_AR_INDEX 0x3c0 765#define VGA_AR_VID_EN (1<<5) 766#define VGA_AR_DATA_WRITE 0x3c0 767#define VGA_AR_DATA_READ 0x3c1 768 769#define VGA_GR_INDEX 0x3ce 770#define VGA_GR_DATA 0x3cf 771/* GR05 */ 772#define VGA_GR_MEM_READ_MODE_SHIFT 3 773#define VGA_GR_MEM_READ_MODE_PLANE 1 774/* GR06 */ 775#define VGA_GR_MEM_MODE_MASK 0xc 776#define VGA_GR_MEM_MODE_SHIFT 2 777#define VGA_GR_MEM_A0000_AFFFF 0 778#define VGA_GR_MEM_A0000_BFFFF 1 779#define VGA_GR_MEM_B0000_B7FFF 2 780#define VGA_GR_MEM_B0000_BFFFF 3 781 782#define VGA_DACMASK 0x3c6 783#define VGA_DACRX 0x3c7 784#define VGA_DACWX 0x3c8 785#define VGA_DACDATA 0x3c9 786 787#define VGA_CR_INDEX_MDA 0x3b4 788#define VGA_CR_DATA_MDA 0x3b5 789#define VGA_CR_INDEX_CGA 0x3d4 790#define VGA_CR_DATA_CGA 0x3d5 791 792/* 793 * Memory interface instructions used by the kernel 794 */ 795#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 796 797#define MI_NOOP MI_INSTR(0, 0) 798#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 799#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 800#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 801#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 802#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 803#define MI_FLUSH MI_INSTR(0x04, 0) 804#define MI_READ_FLUSH (1 << 0) 805#define MI_EXE_FLUSH (1 << 1) 806#define MI_NO_WRITE_FLUSH (1 << 2) 807#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 808#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 809#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 810#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 811#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 812#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 813#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 814#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 815#define MI_STORE_DWORD_INDEX_SHIFT 2 816#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) 817#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 818#define MI_BATCH_NON_SECURE (1) 819#define MI_BATCH_NON_SECURE_I965 (1<<8) 820#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 821 822/* 823 * 3D instructions used by the kernel 824 */ 825#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 826 827#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 828#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 829#define SC_UPDATE_SCISSOR (0x1<<1) 830#define SC_ENABLE_MASK (0x1<<0) 831#define SC_ENABLE (0x1<<0) 832#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 833#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 834#define SCI_YMIN_MASK (0xffff<<16) 835#define SCI_XMIN_MASK (0xffff<<0) 836#define SCI_YMAX_MASK (0xffff<<16) 837#define SCI_XMAX_MASK (0xffff<<0) 838#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 839#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 840#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 841#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 842#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 843#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 844#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 845#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 846#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 847#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 848#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 849#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 850#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 851#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 852#define BLT_DEPTH_8 (0<<24) 853#define BLT_DEPTH_16_565 (1<<24) 854#define BLT_DEPTH_16_1555 (2<<24) 855#define BLT_DEPTH_32 (3<<24) 856#define BLT_ROP_GXCOPY (0xcc<<16) 857#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 858#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 859#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 860#define ASYNC_FLIP (1<<22) 861#define DISPLAY_PLANE_A (0<<20) 862#define DISPLAY_PLANE_B (1<<20) 863 864/* 865 * Instruction and interrupt control regs 866 */ 867 868#define PRB0_TAIL 0x02030 869#define PRB0_HEAD 0x02034 870#define PRB0_START 0x02038 871#define PRB0_CTL 0x0203c 872#define TAIL_ADDR 0x001FFFF8 873#define HEAD_WRAP_COUNT 0xFFE00000 874#define HEAD_WRAP_ONE 0x00200000 875#define HEAD_ADDR 0x001FFFFC 876#define RING_NR_PAGES 0x001FF000 877#define RING_REPORT_MASK 0x00000006 878#define RING_REPORT_64K 0x00000002 879#define RING_REPORT_128K 0x00000004 880#define RING_NO_REPORT 0x00000000 881#define RING_VALID_MASK 0x00000001 882#define RING_VALID 0x00000001 883#define RING_INVALID 0x00000000 884#define PRB1_TAIL 0x02040 /* 915+ only */ 885#define PRB1_HEAD 0x02044 /* 915+ only */ 886#define PRB1_START 0x02048 /* 915+ only */ 887#define PRB1_CTL 0x0204c /* 915+ only */ 888#define ACTHD_I965 0x02074 889#define HWS_PGA 0x02080 890#define HWS_ADDRESS_MASK 0xfffff000 891#define HWS_START_ADDRESS_SHIFT 4 892#define IPEIR 0x02088 893#define NOPID 0x02094 894#define HWSTAM 0x02098 895#define SCPD0 0x0209c /* 915+ only */ 896#define IER 0x020a0 897#define IIR 0x020a4 898#define IMR 0x020a8 899#define ISR 0x020ac 900#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 901#define I915_DISPLAY_PORT_INTERRUPT (1<<17) 902#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 903#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 904#define I915_HWB_OOM_INTERRUPT (1<<13) 905#define I915_SYNC_STATUS_INTERRUPT (1<<12) 906#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 907#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 908#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 909#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 910#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 911#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 912#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 913#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 914#define I915_DEBUG_INTERRUPT (1<<2) 915#define I915_USER_INTERRUPT (1<<1) 916#define I915_ASLE_INTERRUPT (1<<0) 917#define EIR 0x020b0 918#define EMR 0x020b4 919#define ESR 0x020b8 920#define INSTPM 0x020c0 921#define ACTHD 0x020c8 922#define FW_BLC 0x020d8 923#define FW_BLC_SELF 0x020e0 /* 915+ only */ 924#define MI_ARB_STATE 0x020e4 /* 915+ only */ 925#define CACHE_MODE_0 0x02120 /* 915+ only */ 926#define CM0_MASK_SHIFT 16 927#define CM0_IZ_OPT_DISABLE (1<<6) 928#define CM0_ZR_OPT_DISABLE (1<<5) 929#define CM0_DEPTH_EVICT_DISABLE (1<<4) 930#define CM0_COLOR_EVICT_DISABLE (1<<3) 931#define CM0_DEPTH_WRITE_DISABLE (1<<1) 932#define CM0_RC_OP_FLUSH_DISABLE (1<<0) 933#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 934 935/* 936 * Framebuffer compression (915+ only) 937 */ 938 939#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 940#define FBC_LL_BASE 0x03204 /* 4k page aligned */ 941#define FBC_CONTROL 0x03208 942#define FBC_CTL_EN (1<<31) 943#define FBC_CTL_PERIODIC (1<<30) 944#define FBC_CTL_INTERVAL_SHIFT (16) 945#define FBC_CTL_UNCOMPRESSIBLE (1<<14) 946#define FBC_CTL_STRIDE_SHIFT (5) 947#define FBC_CTL_FENCENO (1<<0) 948#define FBC_COMMAND 0x0320c 949#define FBC_CMD_COMPRESS (1<<0) 950#define FBC_STATUS 0x03210 951#define FBC_STAT_COMPRESSING (1<<31) 952#define FBC_STAT_COMPRESSED (1<<30) 953#define FBC_STAT_MODIFIED (1<<29) 954#define FBC_STAT_CURRENT_LINE (1<<0) 955#define FBC_CONTROL2 0x03214 956#define FBC_CTL_FENCE_DBL (0<<4) 957#define FBC_CTL_IDLE_IMM (0<<2) 958#define FBC_CTL_IDLE_FULL (1<<2) 959#define FBC_CTL_IDLE_LINE (2<<2) 960#define FBC_CTL_IDLE_DEBUG (3<<2) 961#define FBC_CTL_CPU_FENCE (1<<1) 962#define FBC_CTL_PLANEA (0<<0) 963#define FBC_CTL_PLANEB (1<<0) 964#define FBC_FENCE_OFF 0x0321b 965 966#define FBC_LL_SIZE (1536) 967 968/* 969 * GPIO regs 970 */ 971#define GPIOA 0x5010 972#define GPIOB 0x5014 973#define GPIOC 0x5018 974#define GPIOD 0x501c 975#define GPIOE 0x5020 976#define GPIOF 0x5024 977#define GPIOG 0x5028 978#define GPIOH 0x502c 979# define GPIO_CLOCK_DIR_MASK (1 << 0) 980# define GPIO_CLOCK_DIR_IN (0 << 1) 981# define GPIO_CLOCK_DIR_OUT (1 << 1) 982# define GPIO_CLOCK_VAL_MASK (1 << 2) 983# define GPIO_CLOCK_VAL_OUT (1 << 3) 984# define GPIO_CLOCK_VAL_IN (1 << 4) 985# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 986# define GPIO_DATA_DIR_MASK (1 << 8) 987# define GPIO_DATA_DIR_IN (0 << 9) 988# define GPIO_DATA_DIR_OUT (1 << 9) 989# define GPIO_DATA_VAL_MASK (1 << 10) 990# define GPIO_DATA_VAL_OUT (1 << 11) 991# define GPIO_DATA_VAL_IN (1 << 12) 992# define GPIO_DATA_PULLUP_DISABLE (1 << 13) 993 994/* 995 * Clock control & power management 996 */ 997 998#define VGA0 0x6000 999#define VGA1 0x6004 1000#define VGA_PD 0x6010 1001#define VGA0_PD_P2_DIV_4 (1 << 7) 1002#define VGA0_PD_P1_DIV_2 (1 << 5) 1003#define VGA0_PD_P1_SHIFT 0 1004#define VGA0_PD_P1_MASK (0x1f << 0) 1005#define VGA1_PD_P2_DIV_4 (1 << 15) 1006#define VGA1_PD_P1_DIV_2 (1 << 13) 1007#define VGA1_PD_P1_SHIFT 8 1008#define VGA1_PD_P1_MASK (0x1f << 8) 1009#define DPLL_A 0x06014 1010#define DPLL_B 0x06018 1011#define DPLL_VCO_ENABLE (1 << 31) 1012#define DPLL_DVO_HIGH_SPEED (1 << 30) 1013#define DPLL_SYNCLOCK_ENABLE (1 << 29) 1014#define DPLL_VGA_MODE_DIS (1 << 28) 1015#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1016#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1017#define DPLL_MODE_MASK (3 << 26) 1018#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1019#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1020#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1021#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1022#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1023#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1024 1025#define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 1026#define I915_CRC_ERROR_ENABLE (1UL<<29) 1027#define I915_CRC_DONE_ENABLE (1UL<<28) 1028#define I915_GMBUS_EVENT_ENABLE (1UL<<27) 1029#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 1030#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 1031#define I915_DPST_EVENT_ENABLE (1UL<<23) 1032#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 1033#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 1034#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 1035#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 1036#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 1037#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 1038#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 1039#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 1040#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 1041#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 1042#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 1043#define I915_DPST_EVENT_STATUS (1UL<<7) 1044#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 1045#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 1046#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 1047#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1048#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) 1049#define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 1050 1051#define SRX_INDEX 0x3c4 1052#define SRX_DATA 0x3c5 1053#define SR01 1 1054#define SR01_SCREEN_OFF (1<<5) 1055 1056#define PPCR 0x61204 1057#define PPCR_ON (1<<0) 1058 1059#define DVOB 0x61140 1060#define DVOB_ON (1<<31) 1061#define DVOC 0x61160 1062#define DVOC_ON (1<<31) 1063#define LVDS 0x61180 1064#define LVDS_ON (1<<31) 1065 1066#define ADPA 0x61100 1067#define ADPA_DPMS_MASK (~(3<<10)) 1068#define ADPA_DPMS_ON (0<<10) 1069#define ADPA_DPMS_SUSPEND (1<<10) 1070#define ADPA_DPMS_STANDBY (2<<10) 1071#define ADPA_DPMS_OFF (3<<10) 1072 1073#define RING_TAIL 0x00 1074#define TAIL_ADDR 0x001FFFF8 1075#define RING_HEAD 0x04 1076#define HEAD_WRAP_COUNT 0xFFE00000 1077#define HEAD_WRAP_ONE 0x00200000 1078#define HEAD_ADDR 0x001FFFFC 1079#define RING_START 0x08 1080#define START_ADDR 0xFFFFF000 1081#define RING_LEN 0x0C 1082#define RING_NR_PAGES 0x001FF000 1083#define RING_REPORT_MASK 0x00000006 1084#define RING_REPORT_64K 0x00000002 1085#define RING_REPORT_128K 0x00000004 1086#define RING_NO_REPORT 0x00000000 1087#define RING_VALID_MASK 0x00000001 1088#define RING_VALID 0x00000001 1089#define RING_INVALID 0x00000000 1090 1091/* Scratch pad debug 0 reg: 1092 */ 1093#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1094/* 1095 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1096 * this field (only one bit may be set). 1097 */ 1098#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1099#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1100/* i830, required in DVO non-gang */ 1101#define PLL_P2_DIVIDE_BY_4 (1 << 23) 1102#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1103#define PLL_REF_INPUT_DREFCLK (0 << 13) 1104#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1105#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1106#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1107#define PLL_REF_INPUT_MASK (3 << 13) 1108#define PLL_LOAD_PULSE_PHASE_SHIFT 9 1109/* 1110 * Parallel to Serial Load Pulse phase selection. 1111 * Selects the phase for the 10X DPLL clock for the PCIe 1112 * digital display port. The range is 4 to 13; 10 or more 1113 * is just a flip delay. The default is 6 1114 */ 1115#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1116#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1117/* 1118 * SDVO multiplier for 945G/GM. Not used on 965. 1119 */ 1120#define SDVO_MULTIPLIER_MASK 0x000000ff 1121#define SDVO_MULTIPLIER_SHIFT_HIRES 4 1122#define SDVO_MULTIPLIER_SHIFT_VGA 0 1123#define DPLL_A_MD 0x0601c /* 965+ only */ 1124/* 1125 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1126 * 1127 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1128 */ 1129#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1130#define DPLL_MD_UDI_DIVIDER_SHIFT 24 1131/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1132#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1133#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1134/* 1135 * SDVO/UDI pixel multiplier. 1136 * 1137 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1138 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1139 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1140 * dummy bytes in the datastream at an increased clock rate, with both sides of 1141 * the link knowing how many bytes are fill. 1142 * 1143 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1144 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1145 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1146 * through an SDVO command. 1147 * 1148 * This register field has values of multiplication factor minus 1, with 1149 * a maximum multiplier of 5 for SDVO. 1150 */ 1151#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1152#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1153/* 1154 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1155 * This best be set to the default value (3) or the CRT won't work. No, 1156 * I don't entirely understand what this does... 1157 */ 1158#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1159#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1160#define DPLL_B_MD 0x06020 /* 965+ only */ 1161#define FPA0 0x06040 1162#define FPA1 0x06044 1163#define FPB0 0x06048 1164#define FPB1 0x0604c 1165#define FP_N_DIV_MASK 0x003f0000 1166#define FP_N_DIV_SHIFT 16 1167#define FP_M1_DIV_MASK 0x00003f00 1168#define FP_M1_DIV_SHIFT 8 1169#define FP_M2_DIV_MASK 0x0000003f 1170#define FP_M2_DIV_SHIFT 0 1171#define DPLL_TEST 0x606c 1172#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1173#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1174#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1175#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1176#define DPLLB_TEST_N_BYPASS (1 << 19) 1177#define DPLLB_TEST_M_BYPASS (1 << 18) 1178#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1179#define DPLLA_TEST_N_BYPASS (1 << 3) 1180#define DPLLA_TEST_M_BYPASS (1 << 2) 1181#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1182#define D_STATE 0x6104 1183#define CG_2D_DIS 0x6200 1184#define CG_3D_DIS 0x6204 1185 1186/* 1187 * Palette regs 1188 */ 1189 1190#define PALETTE_A 0x0a000 1191#define PALETTE_B 0x0a800 1192 1193/* 1194 * Overlay regs 1195 */ 1196 1197#define OVADD 0x30000 1198#define DOVSTA 0x30008 1199#define OC_BUF (0x3<<20) 1200#define OGAMC5 0x30010 1201#define OGAMC4 0x30014 1202#define OGAMC3 0x30018 1203#define OGAMC2 0x3001c 1204#define OGAMC1 0x30020 1205#define OGAMC0 0x30024 1206 1207/* 1208 * Display engine regs 1209 */ 1210 1211/* Pipe A timing regs */ 1212#define HTOTAL_A 0x60000 1213#define HBLANK_A 0x60004 1214#define HSYNC_A 0x60008 1215#define VTOTAL_A 0x6000c 1216#define VBLANK_A 0x60010 1217#define VSYNC_A 0x60014 1218#define PIPEASRC 0x6001c 1219#define BCLRPAT_A 0x60020 1220 1221/* Pipe B timing regs */ 1222#define HTOTAL_B 0x61000 1223#define HBLANK_B 0x61004 1224#define HSYNC_B 0x61008 1225#define VTOTAL_B 0x6100c 1226#define VBLANK_B 0x61010 1227#define VSYNC_B 0x61014 1228#define PIPEBSRC 0x6101c 1229#define BCLRPAT_B 0x61020 1230 1231/* VGA port control */ 1232#define ADPA 0x61100 1233#define ADPA_DAC_ENABLE (1<<31) 1234#define ADPA_DAC_DISABLE 0 1235#define ADPA_PIPE_SELECT_MASK (1<<30) 1236#define ADPA_PIPE_A_SELECT 0 1237#define ADPA_PIPE_B_SELECT (1<<30) 1238#define ADPA_USE_VGA_HVPOLARITY (1<<15) 1239#define ADPA_SETS_HVPOLARITY 0 1240#define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1241#define ADPA_VSYNC_CNTL_ENABLE 0 1242#define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1243#define ADPA_HSYNC_CNTL_ENABLE 0 1244#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1245#define ADPA_VSYNC_ACTIVE_LOW 0 1246#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1247#define ADPA_HSYNC_ACTIVE_LOW 0 1248#define ADPA_DPMS_MASK (~(3<<10)) 1249#define ADPA_DPMS_ON (0<<10) 1250#define ADPA_DPMS_SUSPEND (1<<10) 1251#define ADPA_DPMS_STANDBY (2<<10) 1252#define ADPA_DPMS_OFF (3<<10) 1253 1254/* Hotplug control (945+ only) */ 1255#define PORT_HOTPLUG_EN 0x61110 1256#define SDVOB_HOTPLUG_INT_EN (1 << 26) 1257#define SDVOC_HOTPLUG_INT_EN (1 << 25) 1258#define TV_HOTPLUG_INT_EN (1 << 18) 1259#define CRT_HOTPLUG_INT_EN (1 << 9) 1260#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1261 1262#define PORT_HOTPLUG_STAT 0x61114 1263#define CRT_HOTPLUG_INT_STATUS (1 << 11) 1264#define TV_HOTPLUG_INT_STATUS (1 << 10) 1265#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1266#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1267#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1268#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1269#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1270#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1271 1272/* SDVO port control */ 1273#define SDVOB 0x61140 1274#define SDVOC 0x61160 1275#define SDVO_ENABLE (1 << 31) 1276#define SDVO_PIPE_B_SELECT (1 << 30) 1277#define SDVO_STALL_SELECT (1 << 29) 1278#define SDVO_INTERRUPT_ENABLE (1 << 26) 1279/** 1280 * 915G/GM SDVO pixel multiplier. 1281 * 1282 * Programmed value is multiplier - 1, up to 5x. 1283 * 1284 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1285 */ 1286#define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1287#define SDVO_PORT_MULTIPLY_SHIFT 23 1288#define SDVO_PHASE_SELECT_MASK (15 << 19) 1289#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1290#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1291#define SDVOC_GANG_MODE (1 << 16) 1292#define SDVO_BORDER_ENABLE (1 << 7) 1293#define SDVOB_PCIE_CONCURRENCY (1 << 3) 1294#define SDVO_DETECTED (1 << 2) 1295/* Bits to be preserved when writing */ 1296#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1297#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1298 1299/* DVO port control */ 1300#define DVOA 0x61120 1301#define DVOB 0x61140 1302#define DVOC 0x61160 1303#define DVO_ENABLE (1 << 31) 1304#define DVO_PIPE_B_SELECT (1 << 30) 1305#define DVO_PIPE_STALL_UNUSED (0 << 28) 1306#define DVO_PIPE_STALL (1 << 28) 1307#define DVO_PIPE_STALL_TV (2 << 28) 1308#define DVO_PIPE_STALL_MASK (3 << 28) 1309#define DVO_USE_VGA_SYNC (1 << 15) 1310#define DVO_DATA_ORDER_I740 (0 << 14) 1311#define DVO_DATA_ORDER_FP (1 << 14) 1312#define DVO_VSYNC_DISABLE (1 << 11) 1313#define DVO_HSYNC_DISABLE (1 << 10) 1314#define DVO_VSYNC_TRISTATE (1 << 9) 1315#define DVO_HSYNC_TRISTATE (1 << 8) 1316#define DVO_BORDER_ENABLE (1 << 7) 1317#define DVO_DATA_ORDER_GBRG (1 << 6) 1318#define DVO_DATA_ORDER_RGGB (0 << 6) 1319#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1320#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1321#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1322#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1323#define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1324#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1325#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1326#define DVO_PRESERVE_MASK (0x7<<24) 1327#define DVOA_SRCDIM 0x61124 1328#define DVOB_SRCDIM 0x61144 1329#define DVOC_SRCDIM 0x61164 1330#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1331#define DVO_SRCDIM_VERTICAL_SHIFT 0 1332 1333/* LVDS port control */ 1334#define LVDS 0x61180 1335/* 1336 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1337 * the DPLL semantics change when the LVDS is assigned to that pipe. 1338 */ 1339#define LVDS_PORT_EN (1 << 31) 1340/* Selects pipe B for LVDS data. Must be set on pre-965. */ 1341#define LVDS_PIPEB_SELECT (1 << 30) 1342/* 1343 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1344 * pixel. 1345 */ 1346#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1347#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1348#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1349/* 1350 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1351 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1352 * on. 1353 */ 1354#define LVDS_A3_POWER_MASK (3 << 6) 1355#define LVDS_A3_POWER_DOWN (0 << 6) 1356#define LVDS_A3_POWER_UP (3 << 6) 1357/* 1358 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1359 * is set. 1360 */ 1361#define LVDS_CLKB_POWER_MASK (3 << 4) 1362#define LVDS_CLKB_POWER_DOWN (0 << 4) 1363#define LVDS_CLKB_POWER_UP (3 << 4) 1364/* 1365 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1366 * setting for whether we are in dual-channel mode. The B3 pair will 1367 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1368 */ 1369#define LVDS_B0B3_POWER_MASK (3 << 2) 1370#define LVDS_B0B3_POWER_DOWN (0 << 2) 1371#define LVDS_B0B3_POWER_UP (3 << 2) 1372 1373/* Panel power sequencing */ 1374#define PP_STATUS 0x61200 1375#define PP_ON (1 << 31) 1376/* 1377 * Indicates that all dependencies of the panel are on: 1378 * 1379 * - PLL enabled 1380 * - pipe enabled 1381 * - LVDS/DVOB/DVOC on 1382 */ 1383#define PP_READY (1 << 30) 1384#define PP_SEQUENCE_NONE (0 << 28) 1385#define PP_SEQUENCE_ON (1 << 28) 1386#define PP_SEQUENCE_OFF (2 << 28) 1387#define PP_SEQUENCE_MASK 0x30000000 1388#define PP_CONTROL 0x61204 1389#define POWER_TARGET_ON (1 << 0) 1390#define PP_ON_DELAYS 0x61208 1391#define PP_OFF_DELAYS 0x6120c 1392#define PP_DIVISOR 0x61210 1393 1394/* Panel fitting */ 1395#define PFIT_CONTROL 0x61230 1396#define PFIT_ENABLE (1 << 31) 1397#define PFIT_PIPE_MASK (3 << 29) 1398#define PFIT_PIPE_SHIFT 29 1399#define VERT_INTERP_DISABLE (0 << 10) 1400#define VERT_INTERP_BILINEAR (1 << 10) 1401#define VERT_INTERP_MASK (3 << 10) 1402#define VERT_AUTO_SCALE (1 << 9) 1403#define HORIZ_INTERP_DISABLE (0 << 6) 1404#define HORIZ_INTERP_BILINEAR (1 << 6) 1405#define HORIZ_INTERP_MASK (3 << 6) 1406#define HORIZ_AUTO_SCALE (1 << 5) 1407#define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1408#define PFIT_PGM_RATIOS 0x61234 1409#define PFIT_VERT_SCALE_MASK 0xfff00000 1410#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1411#define PFIT_AUTO_RATIOS 0x61238 1412 1413/* Backlight control */ 1414#define BLC_PWM_CTL 0x61254 1415#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1416#define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1417/* 1418 * This is the most significant 15 bits of the number of backlight cycles in a 1419 * complete cycle of the modulated backlight control. 1420 * 1421 * The actual value is this field multiplied by two. 1422 */ 1423#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1424#define BLM_LEGACY_MODE (1 << 16) 1425/* 1426 * This is the number of cycles out of the backlight modulation cycle for which 1427 * the backlight is on. 1428 * 1429 * This field must be no greater than the number of cycles in the complete 1430 * backlight modulation cycle. 1431 */ 1432#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1433#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1434 1435/* TV port control */ 1436#define TV_CTL 0x68000 1437/** Enables the TV encoder */ 1438# define TV_ENC_ENABLE (1 << 31) 1439/** Sources the TV encoder input from pipe B instead of A. */ 1440# define TV_ENC_PIPEB_SELECT (1 << 30) 1441/** Outputs composite video (DAC A only) */ 1442# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1443/** Outputs SVideo video (DAC B/C) */ 1444# define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1445/** Outputs Component video (DAC A/B/C) */ 1446# define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1447/** Outputs Composite and SVideo (DAC A/B/C) */ 1448# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1449# define TV_TRILEVEL_SYNC (1 << 21) 1450/** Enables slow sync generation (945GM only) */ 1451# define TV_SLOW_SYNC (1 << 20) 1452/** Selects 4x oversampling for 480i and 576p */ 1453# define TV_OVERSAMPLE_4X (0 << 18) 1454/** Selects 2x oversampling for 720p and 1080i */ 1455# define TV_OVERSAMPLE_2X (1 << 18) 1456/** Selects no oversampling for 1080p */ 1457# define TV_OVERSAMPLE_NONE (2 << 18) 1458/** Selects 8x oversampling */ 1459# define TV_OVERSAMPLE_8X (3 << 18) 1460/** Selects progressive mode rather than interlaced */ 1461# define TV_PROGRESSIVE (1 << 17) 1462/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1463# define TV_PAL_BURST (1 << 16) 1464/** Field for setting delay of Y compared to C */ 1465# define TV_YC_SKEW_MASK (7 << 12) 1466/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1467# define TV_ENC_SDP_FIX (1 << 11) 1468/** 1469 * Enables a fix for the 915GM only. 1470 * 1471 * Not sure what it does. 1472 */ 1473# define TV_ENC_C0_FIX (1 << 10) 1474/** Bits that must be preserved by software */ 1475# define TV_CTL_SAVE ((3 << 8) | (3 << 6)) 1476# define TV_FUSE_STATE_MASK (3 << 4) 1477/** Read-only state that reports all features enabled */ 1478# define TV_FUSE_STATE_ENABLED (0 << 4) 1479/** Read-only state that reports that Macrovision is disabled in hardware*/ 1480# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1481/** Read-only state that reports that TV-out is disabled in hardware. */ 1482# define TV_FUSE_STATE_DISABLED (2 << 4) 1483/** Normal operation */ 1484# define TV_TEST_MODE_NORMAL (0 << 0) 1485/** Encoder test pattern 1 - combo pattern */ 1486# define TV_TEST_MODE_PATTERN_1 (1 << 0) 1487/** Encoder test pattern 2 - full screen vertical 75% color bars */ 1488# define TV_TEST_MODE_PATTERN_2 (2 << 0) 1489/** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1490# define TV_TEST_MODE_PATTERN_3 (3 << 0) 1491/** Encoder test pattern 4 - random noise */ 1492# define TV_TEST_MODE_PATTERN_4 (4 << 0) 1493/** Encoder test pattern 5 - linear color ramps */ 1494# define TV_TEST_MODE_PATTERN_5 (5 << 0) 1495/** 1496 * This test mode forces the DACs to 50% of full output. 1497 * 1498 * This is used for load detection in combination with TVDAC_SENSE_MASK 1499 */ 1500# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1501# define TV_TEST_MODE_MASK (7 << 0) 1502 1503#define TV_DAC 0x68004 1504/** 1505 * Reports that DAC state change logic has reported change (RO). 1506 * 1507 * This gets cleared when TV_DAC_STATE_EN is cleared 1508*/ 1509# define TVDAC_STATE_CHG (1 << 31) 1510# define TVDAC_SENSE_MASK (7 << 28) 1511/** Reports that DAC A voltage is above the detect threshold */ 1512# define TVDAC_A_SENSE (1 << 30) 1513/** Reports that DAC B voltage is above the detect threshold */ 1514# define TVDAC_B_SENSE (1 << 29) 1515/** Reports that DAC C voltage is above the detect threshold */ 1516# define TVDAC_C_SENSE (1 << 28) 1517/** 1518 * Enables DAC state detection logic, for load-based TV detection. 1519 * 1520 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1521 * to off, for load detection to work. 1522 */ 1523# define TVDAC_STATE_CHG_EN (1 << 27) 1524/** Sets the DAC A sense value to high */ 1525# define TVDAC_A_SENSE_CTL (1 << 26) 1526/** Sets the DAC B sense value to high */ 1527# define TVDAC_B_SENSE_CTL (1 << 25) 1528/** Sets the DAC C sense value to high */ 1529# define TVDAC_C_SENSE_CTL (1 << 24) 1530/** Overrides the ENC_ENABLE and DAC voltage levels */ 1531# define DAC_CTL_OVERRIDE (1 << 7) 1532/** Sets the slew rate. Must be preserved in software */ 1533# define ENC_TVDAC_SLEW_FAST (1 << 6) 1534# define DAC_A_1_3_V (0 << 4) 1535# define DAC_A_1_1_V (1 << 4) 1536# define DAC_A_0_7_V (2 << 4) 1537# define DAC_A_OFF (3 << 4) 1538# define DAC_B_1_3_V (0 << 2) 1539# define DAC_B_1_1_V (1 << 2) 1540# define DAC_B_0_7_V (2 << 2) 1541# define DAC_B_OFF (3 << 2) 1542# define DAC_C_1_3_V (0 << 0) 1543# define DAC_C_1_1_V (1 << 0) 1544# define DAC_C_0_7_V (2 << 0) 1545# define DAC_C_OFF (3 << 0) 1546 1547/** 1548 * CSC coefficients are stored in a floating point format with 9 bits of 1549 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1550 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1551 * -1 (0x3) being the only legal negative value. 1552 */ 1553#define TV_CSC_Y 0x68010 1554# define TV_RY_MASK 0x07ff0000 1555# define TV_RY_SHIFT 16 1556# define TV_GY_MASK 0x00000fff 1557# define TV_GY_SHIFT 0 1558 1559#define TV_CSC_Y2 0x68014 1560# define TV_BY_MASK 0x07ff0000 1561# define TV_BY_SHIFT 16 1562/** 1563 * Y attenuation for component video. 1564 * 1565 * Stored in 1.9 fixed point. 1566 */ 1567# define TV_AY_MASK 0x000003ff 1568# define TV_AY_SHIFT 0 1569 1570#define TV_CSC_U 0x68018 1571# define TV_RU_MASK 0x07ff0000 1572# define TV_RU_SHIFT 16 1573# define TV_GU_MASK 0x000007ff 1574# define TV_GU_SHIFT 0 1575 1576#define TV_CSC_U2 0x6801c 1577# define TV_BU_MASK 0x07ff0000 1578# define TV_BU_SHIFT 16 1579/** 1580 * U attenuation for component video. 1581 * 1582 * Stored in 1.9 fixed point. 1583 */ 1584# define TV_AU_MASK 0x000003ff 1585# define TV_AU_SHIFT 0 1586 1587#define TV_CSC_V 0x68020 1588# define TV_RV_MASK 0x0fff0000 1589# define TV_RV_SHIFT 16 1590# define TV_GV_MASK 0x000007ff 1591# define TV_GV_SHIFT 0 1592 1593#define TV_CSC_V2 0x68024 1594# define TV_BV_MASK 0x07ff0000 1595# define TV_BV_SHIFT 16 1596/** 1597 * V attenuation for component video. 1598 * 1599 * Stored in 1.9 fixed point. 1600 */ 1601# define TV_AV_MASK 0x000007ff 1602# define TV_AV_SHIFT 0 1603 1604#define TV_CLR_KNOBS 0x68028 1605/** 2s-complement brightness adjustment */ 1606# define TV_BRIGHTNESS_MASK 0xff000000 1607# define TV_BRIGHTNESS_SHIFT 24 1608/** Contrast adjustment, as a 2.6 unsigned floating point number */ 1609# define TV_CONTRAST_MASK 0x00ff0000 1610# define TV_CONTRAST_SHIFT 16 1611/** Saturation adjustment, as a 2.6 unsigned floating point number */ 1612# define TV_SATURATION_MASK 0x0000ff00 1613# define TV_SATURATION_SHIFT 8 1614/** Hue adjustment, as an integer phase angle in degrees */ 1615# define TV_HUE_MASK 0x000000ff 1616# define TV_HUE_SHIFT 0 1617 1618#define TV_CLR_LEVEL 0x6802c 1619/** Controls the DAC level for black */ 1620# define TV_BLACK_LEVEL_MASK 0x01ff0000 1621# define TV_BLACK_LEVEL_SHIFT 16 1622/** Controls the DAC level for blanking */ 1623# define TV_BLANK_LEVEL_MASK 0x000001ff 1624# define TV_BLANK_LEVEL_SHIFT 0 1625 1626#define TV_H_CTL_1 0x68030 1627/** Number of pixels in the hsync. */ 1628# define TV_HSYNC_END_MASK 0x1fff0000 1629# define TV_HSYNC_END_SHIFT 16 1630/** Total number of pixels minus one in the line (display and blanking). */ 1631# define TV_HTOTAL_MASK 0x00001fff 1632# define TV_HTOTAL_SHIFT 0 1633 1634#define TV_H_CTL_2 0x68034 1635/** Enables the colorburst (needed for non-component color) */ 1636# define TV_BURST_ENA (1 << 31) 1637/** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1638# define TV_HBURST_START_SHIFT 16 1639# define TV_HBURST_START_MASK 0x1fff0000 1640/** Length of the colorburst */ 1641# define TV_HBURST_LEN_SHIFT 0 1642# define TV_HBURST_LEN_MASK 0x0001fff 1643 1644#define TV_H_CTL_3 0x68038 1645/** End of hblank, measured in pixels minus one from start of hsync */ 1646# define TV_HBLANK_END_SHIFT 16 1647# define TV_HBLANK_END_MASK 0x1fff0000 1648/** Start of hblank, measured in pixels minus one from start of hsync */ 1649# define TV_HBLANK_START_SHIFT 0 1650# define TV_HBLANK_START_MASK 0x0001fff 1651 1652#define TV_V_CTL_1 0x6803c 1653/** XXX */ 1654# define TV_NBR_END_SHIFT 16 1655# define TV_NBR_END_MASK 0x07ff0000 1656/** XXX */ 1657# define TV_VI_END_F1_SHIFT 8 1658# define TV_VI_END_F1_MASK 0x00003f00 1659/** XXX */ 1660# define TV_VI_END_F2_SHIFT 0 1661# define TV_VI_END_F2_MASK 0x0000003f 1662 1663#define TV_V_CTL_2 0x68040 1664/** Length of vsync, in half lines */ 1665# define TV_VSYNC_LEN_MASK 0x07ff0000 1666# define TV_VSYNC_LEN_SHIFT 16 1667/** Offset of the start of vsync in field 1, measured in one less than the 1668 * number of half lines. 1669 */ 1670# define TV_VSYNC_START_F1_MASK 0x00007f00 1671# define TV_VSYNC_START_F1_SHIFT 8 1672/** 1673 * Offset of the start of vsync in field 2, measured in one less than the 1674 * number of half lines. 1675 */ 1676# define TV_VSYNC_START_F2_MASK 0x0000007f 1677# define TV_VSYNC_START_F2_SHIFT 0 1678 1679#define TV_V_CTL_3 0x68044 1680/** Enables generation of the equalization signal */ 1681# define TV_EQUAL_ENA (1 << 31) 1682/** Length of vsync, in half lines */ 1683# define TV_VEQ_LEN_MASK 0x007f0000 1684# define TV_VEQ_LEN_SHIFT 16 1685/** Offset of the start of equalization in field 1, measured in one less than 1686 * the number of half lines. 1687 */ 1688# define TV_VEQ_START_F1_MASK 0x0007f00 1689# define TV_VEQ_START_F1_SHIFT 8 1690/** 1691 * Offset of the start of equalization in field 2, measured in one less than 1692 * the number of half lines. 1693 */ 1694# define TV_VEQ_START_F2_MASK 0x000007f 1695# define TV_VEQ_START_F2_SHIFT 0 1696 1697#define TV_V_CTL_4 0x68048 1698/** 1699 * Offset to start of vertical colorburst, measured in one less than the 1700 * number of lines from vertical start. 1701 */ 1702# define TV_VBURST_START_F1_MASK 0x003f0000 1703# define TV_VBURST_START_F1_SHIFT 16 1704/** 1705 * Offset to the end of vertical colorburst, measured in one less than the 1706 * number of lines from the start of NBR. 1707 */ 1708# define TV_VBURST_END_F1_MASK 0x000000ff 1709# define TV_VBURST_END_F1_SHIFT 0 1710 1711#define TV_V_CTL_5 0x6804c 1712/** 1713 * Offset to start of vertical colorburst, measured in one less than the 1714 * number of lines from vertical start. 1715 */ 1716# define TV_VBURST_START_F2_MASK 0x003f0000 1717# define TV_VBURST_START_F2_SHIFT 16 1718/** 1719 * Offset to the end of vertical colorburst, measured in one less than the 1720 * number of lines from the start of NBR. 1721 */ 1722# define TV_VBURST_END_F2_MASK 0x000000ff 1723# define TV_VBURST_END_F2_SHIFT 0 1724 1725#define TV_V_CTL_6 0x68050 1726/** 1727 * Offset to start of vertical colorburst, measured in one less than the 1728 * number of lines from vertical start. 1729 */ 1730# define TV_VBURST_START_F3_MASK 0x003f0000 1731# define TV_VBURST_START_F3_SHIFT 16 1732/** 1733 * Offset to the end of vertical colorburst, measured in one less than the 1734 * number of lines from the start of NBR. 1735 */ 1736# define TV_VBURST_END_F3_MASK 0x000000ff 1737# define TV_VBURST_END_F3_SHIFT 0 1738 1739#define TV_V_CTL_7 0x68054 1740/** 1741 * Offset to start of vertical colorburst, measured in one less than the 1742 * number of lines from vertical start. 1743 */ 1744# define TV_VBURST_START_F4_MASK 0x003f0000 1745# define TV_VBURST_START_F4_SHIFT 16 1746/** 1747 * Offset to the end of vertical colorburst, measured in one less than the 1748 * number of lines from the start of NBR. 1749 */ 1750# define TV_VBURST_END_F4_MASK 0x000000ff 1751# define TV_VBURST_END_F4_SHIFT 0 1752 1753#define TV_SC_CTL_1 0x68060 1754/** Turns on the first subcarrier phase generation DDA */ 1755# define TV_SC_DDA1_EN (1 << 31) 1756/** Turns on the first subcarrier phase generation DDA */ 1757# define TV_SC_DDA2_EN (1 << 30) 1758/** Turns on the first subcarrier phase generation DDA */ 1759# define TV_SC_DDA3_EN (1 << 29) 1760/** Sets the subcarrier DDA to reset frequency every other field */ 1761# define TV_SC_RESET_EVERY_2 (0 << 24) 1762/** Sets the subcarrier DDA to reset frequency every fourth field */ 1763# define TV_SC_RESET_EVERY_4 (1 << 24) 1764/** Sets the subcarrier DDA to reset frequency every eighth field */ 1765# define TV_SC_RESET_EVERY_8 (2 << 24) 1766/** Sets the subcarrier DDA to never reset the frequency */ 1767# define TV_SC_RESET_NEVER (3 << 24) 1768/** Sets the peak amplitude of the colorburst.*/ 1769# define TV_BURST_LEVEL_MASK 0x00ff0000 1770# define TV_BURST_LEVEL_SHIFT 16 1771/** Sets the increment of the first subcarrier phase generation DDA */ 1772# define TV_SCDDA1_INC_MASK 0x00000fff 1773# define TV_SCDDA1_INC_SHIFT 0 1774 1775#define TV_SC_CTL_2 0x68064 1776/** Sets the rollover for the second subcarrier phase generation DDA */ 1777# define TV_SCDDA2_SIZE_MASK 0x7fff0000 1778# define TV_SCDDA2_SIZE_SHIFT 16 1779/** Sets the increent of the second subcarrier phase generation DDA */ 1780# define TV_SCDDA2_INC_MASK 0x00007fff 1781# define TV_SCDDA2_INC_SHIFT 0 1782 1783#define TV_SC_CTL_3 0x68068 1784/** Sets the rollover for the third subcarrier phase generation DDA */ 1785# define TV_SCDDA3_SIZE_MASK 0x7fff0000 1786# define TV_SCDDA3_SIZE_SHIFT 16 1787/** Sets the increent of the third subcarrier phase generation DDA */ 1788# define TV_SCDDA3_INC_MASK 0x00007fff 1789# define TV_SCDDA3_INC_SHIFT 0 1790 1791#define TV_WIN_POS 0x68070 1792/** X coordinate of the display from the start of horizontal active */ 1793# define TV_XPOS_MASK 0x1fff0000 1794# define TV_XPOS_SHIFT 16 1795/** Y coordinate of the display from the start of vertical active (NBR) */ 1796# define TV_YPOS_MASK 0x00000fff 1797# define TV_YPOS_SHIFT 0 1798 1799#define TV_WIN_SIZE 0x68074 1800/** Horizontal size of the display window, measured in pixels*/ 1801# define TV_XSIZE_MASK 0x1fff0000 1802# define TV_XSIZE_SHIFT 16 1803/** 1804 * Vertical size of the display window, measured in pixels. 1805 * 1806 * Must be even for interlaced modes. 1807 */ 1808# define TV_YSIZE_MASK 0x00000fff 1809# define TV_YSIZE_SHIFT 0 1810 1811#define TV_FILTER_CTL_1 0x68080 1812/** 1813 * Enables automatic scaling calculation. 1814 * 1815 * If set, the rest of the registers are ignored, and the calculated values can 1816 * be read back from the register. 1817 */ 1818# define TV_AUTO_SCALE (1 << 31) 1819/** 1820 * Disables the vertical filter. 1821 * 1822 * This is required on modes more than 1024 pixels wide */ 1823# define TV_V_FILTER_BYPASS (1 << 29) 1824/** Enables adaptive vertical filtering */ 1825# define TV_VADAPT (1 << 28) 1826# define TV_VADAPT_MODE_MASK (3 << 26) 1827/** Selects the least adaptive vertical filtering mode */ 1828# define TV_VADAPT_MODE_LEAST (0 << 26) 1829/** Selects the moderately adaptive vertical filtering mode */ 1830# define TV_VADAPT_MODE_MODERATE (1 << 26) 1831/** Selects the most adaptive vertical filtering mode */ 1832# define TV_VADAPT_MODE_MOST (3 << 26) 1833/** 1834 * Sets the horizontal scaling factor. 1835 * 1836 * This should be the fractional part of the horizontal scaling factor divided 1837 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 1838 * 1839 * (src width - 1) / ((oversample * dest width) - 1) 1840 */ 1841# define TV_HSCALE_FRAC_MASK 0x00003fff 1842# define TV_HSCALE_FRAC_SHIFT 0 1843 1844#define TV_FILTER_CTL_2 0x68084 1845/** 1846 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1847 * 1848 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 1849 */ 1850# define TV_VSCALE_INT_MASK 0x00038000 1851# define TV_VSCALE_INT_SHIFT 15 1852/** 1853 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1854 * 1855 * \sa TV_VSCALE_INT_MASK 1856 */ 1857# define TV_VSCALE_FRAC_MASK 0x00007fff 1858# define TV_VSCALE_FRAC_SHIFT 0 1859 1860#define TV_FILTER_CTL_3 0x68088 1861/** 1862 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1863 * 1864 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 1865 * 1866 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1867 */ 1868# define TV_VSCALE_IP_INT_MASK 0x00038000 1869# define TV_VSCALE_IP_INT_SHIFT 15 1870/** 1871 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1872 * 1873 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1874 * 1875 * \sa TV_VSCALE_IP_INT_MASK 1876 */ 1877# define TV_VSCALE_IP_FRAC_MASK 0x00007fff 1878# define TV_VSCALE_IP_FRAC_SHIFT 0 1879 1880#define TV_CC_CONTROL 0x68090 1881# define TV_CC_ENABLE (1 << 31) 1882/** 1883 * Specifies which field to send the CC data in. 1884 * 1885 * CC data is usually sent in field 0. 1886 */ 1887# define TV_CC_FID_MASK (1 << 27) 1888# define TV_CC_FID_SHIFT 27 1889/** Sets the horizontal position of the CC data. Usually 135. */ 1890# define TV_CC_HOFF_MASK 0x03ff0000 1891# define TV_CC_HOFF_SHIFT 16 1892/** Sets the vertical position of the CC data. Usually 21 */ 1893# define TV_CC_LINE_MASK 0x0000003f 1894# define TV_CC_LINE_SHIFT 0 1895 1896#define TV_CC_DATA 0x68094 1897# define TV_CC_RDY (1 << 31) 1898/** Second word of CC data to be transmitted. */ 1899# define TV_CC_DATA_2_MASK 0x007f0000 1900# define TV_CC_DATA_2_SHIFT 16 1901/** First word of CC data to be transmitted. */ 1902# define TV_CC_DATA_1_MASK 0x0000007f 1903# define TV_CC_DATA_1_SHIFT 0 1904 1905#define TV_H_LUMA_0 0x68100 1906#define TV_H_LUMA_59 0x681ec 1907#define TV_H_CHROMA_0 0x68200 1908#define TV_H_CHROMA_59 0x682ec 1909#define TV_V_LUMA_0 0x68300 1910#define TV_V_LUMA_42 0x683a8 1911#define TV_V_CHROMA_0 0x68400 1912#define TV_V_CHROMA_42 0x684a8 1913 1914/* Display & cursor control */ 1915 1916/* Pipe A */ 1917#define PIPEADSL 0x70000 1918#define PIPEACONF 0x70008 1919#define PIPEACONF_ENABLE (1<<31) 1920#define PIPEACONF_DISABLE 0 1921#define PIPEACONF_DOUBLE_WIDE (1<<30) 1922#define I965_PIPECONF_ACTIVE (1<<30) 1923#define PIPEACONF_SINGLE_WIDE 0 1924#define PIPEACONF_PIPE_UNLOCKED 0 1925#define PIPEACONF_PIPE_LOCKED (1<<25) 1926#define PIPEACONF_PALETTE 0 1927#define PIPEACONF_GAMMA (1<<24) 1928#define PIPECONF_FORCE_BORDER (1<<25) 1929#define PIPECONF_PROGRESSIVE (0 << 21) 1930#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 1931#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 1932#define PIPEASTAT 0x70024 1933#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 1934#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 1935#define PIPE_CRC_DONE_ENABLE (1UL<<28) 1936#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 1937#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 1938#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 1939#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 1940#define PIPE_DPST_EVENT_ENABLE (1UL<<23) 1941#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 1942#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 1943#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 1944#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 1945#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 1946#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 1947#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 1948#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 1949#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 1950#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 1951#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 1952#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 1953#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 1954#define PIPE_DPST_EVENT_STATUS (1UL<<7) 1955#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 1956#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 1957#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 1958#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 1959#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1960#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 1961#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 1962 1963#define DSPARB 0x70030 1964#define DSPARB_CSTART_MASK (0x7f << 7) 1965#define DSPARB_CSTART_SHIFT 7 1966#define DSPARB_BSTART_MASK (0x7f) 1967#define DSPARB_BSTART_SHIFT 0 1968/* 1969 * The two pipe frame counter registers are not synchronized, so 1970 * reading a stable value is somewhat tricky. The following code 1971 * should work: 1972 * 1973 * do { 1974 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1975 * PIPE_FRAME_HIGH_SHIFT; 1976 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 1977 * PIPE_FRAME_LOW_SHIFT); 1978 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1979 * PIPE_FRAME_HIGH_SHIFT); 1980 * } while (high1 != high2); 1981 * frame = (high1 << 8) | low1; 1982 */ 1983#define PIPEAFRAMEHIGH 0x70040 1984#define PIPE_FRAME_HIGH_MASK 0x0000ffff 1985#define PIPE_FRAME_HIGH_SHIFT 0 1986#define PIPEAFRAMEPIXEL 0x70044 1987#define PIPE_FRAME_LOW_MASK 0xff000000 1988#define PIPE_FRAME_LOW_SHIFT 24 1989#define PIPE_PIXEL_MASK 0x00ffffff 1990#define PIPE_PIXEL_SHIFT 0 1991 1992/* Cursor A & B regs */ 1993#define CURACNTR 0x70080 1994#define CURSOR_MODE_DISABLE 0x00 1995#define CURSOR_MODE_64_32B_AX 0x07 1996#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 1997#define MCURSOR_GAMMA_ENABLE (1 << 26) 1998#define CURABASE 0x70084 1999#define CURAPOS 0x70088 2000#define CURSOR_POS_MASK 0x007FF 2001#define CURSOR_POS_SIGN 0x8000 2002#define CURSOR_X_SHIFT 0 2003#define CURSOR_Y_SHIFT 16 2004#define CURBCNTR 0x700c0 2005#define CURBBASE 0x700c4 2006#define CURBPOS 0x700c8 2007 2008/* Display A control */ 2009#define DSPACNTR 0x70180 2010#define DISPLAY_PLANE_ENABLE (1<<31) 2011#define DISPLAY_PLANE_DISABLE 0 2012#define DISPPLANE_GAMMA_ENABLE (1<<30) 2013#define DISPPLANE_GAMMA_DISABLE 0 2014#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2015#define DISPPLANE_8BPP (0x2<<26) 2016#define DISPPLANE_15_16BPP (0x4<<26) 2017#define DISPPLANE_16BPP (0x5<<26) 2018#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2019#define DISPPLANE_32BPP (0x7<<26) 2020#define DISPPLANE_STEREO_ENABLE (1<<25) 2021#define DISPPLANE_STEREO_DISABLE 0 2022#define DISPPLANE_SEL_PIPE_MASK (1<<24) 2023#define DISPPLANE_SEL_PIPE_A 0 2024#define DISPPLANE_SEL_PIPE_B (1<<24) 2025#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2026#define DISPPLANE_SRC_KEY_DISABLE 0 2027#define DISPPLANE_LINE_DOUBLE (1<<20) 2028#define DISPPLANE_NO_LINE_DOUBLE 0 2029#define DISPPLANE_STEREO_POLARITY_FIRST 0 2030#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2031#define DSPAADDR 0x70184 2032#define DSPASTRIDE 0x70188 2033#define DSPAPOS 0x7018C /* reserved */ 2034#define DSPASIZE 0x70190 2035#define DSPASURF 0x7019C /* 965+ only */ 2036#define DSPATILEOFF 0x701A4 /* 965+ only */ 2037 2038/* VBIOS flags */ 2039#define SWF00 0x71410 2040#define SWF01 0x71414 2041#define SWF02 0x71418 2042#define SWF03 0x7141c 2043#define SWF04 0x71420 2044#define SWF05 0x71424 2045#define SWF06 0x71428 2046#define SWF10 0x70410 2047#define SWF11 0x70414 2048#define SWF14 0x71420 2049#define SWF30 0x72414 2050#define SWF31 0x72418 2051#define SWF32 0x7241c 2052 2053/* Pipe B */ 2054#define PIPEBDSL 0x71000 2055#define PIPEBCONF 0x71008 2056#define PIPEBSTAT 0x71024 2057#define PIPEBFRAMEHIGH 0x71040 2058#define PIPEBFRAMEPIXEL 0x71044 2059 2060/* Display B control */ 2061#define DSPBCNTR 0x71180 2062#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2063#define DISPPLANE_ALPHA_TRANS_DISABLE 0 2064#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2065#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2066#define DSPBADDR 0x71184 2067#define DSPBSTRIDE 0x71188 2068#define DSPBPOS 0x7118C 2069#define DSPBSIZE 0x71190 2070#define DSPBSURF 0x7119C 2071#define DSPBTILEOFF 0x711A4 2072 2073/* VBIOS regs */ 2074#define VGACNTRL 0x71400 2075# define VGA_DISP_DISABLE (1 << 31) 2076# define VGA_2X_MODE (1 << 30) 2077# define VGA_PIPE_B_SELECT (1 << 29) 2078 2079/* Chipset type macros */ 2080 2081#define IS_I830(dev) ((dev)->pci_device == 0x3577) 2082#define IS_845G(dev) ((dev)->pci_device == 0x2562) 2083#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 2084#define IS_I855(dev) ((dev)->pci_device == 0x3582) 2085#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 2086 2087#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 2088#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 2089#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 2090#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 2091 (dev)->pci_device == 0x27AE) 2092#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 2093 (dev)->pci_device == 0x2982 || \ 2094 (dev)->pci_device == 0x2992 || \ 2095 (dev)->pci_device == 0x29A2 || \ 2096 (dev)->pci_device == 0x2A02 || \ 2097 (dev)->pci_device == 0x2A12 || \ 2098 (dev)->pci_device == 0x2A42 || \ 2099 (dev)->pci_device == 0x2E02 || \ 2100 (dev)->pci_device == 0x2E12 || \ 2101 (dev)->pci_device == 0x2E22) 2102 2103#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 2104 2105#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 2106 2107#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 2108 (dev)->pci_device == 0x2E12 || \ 2109 (dev)->pci_device == 0x2E22) 2110 2111#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 2112 (dev)->pci_device == 0x29B2 || \ 2113 (dev)->pci_device == 0x29D2) 2114 2115#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 2116 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 2117 2118#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 2119 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 2120 2121#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 2122 2123#endif 2124