t5fw_cfg_uwire.txt revision 285527
1252661Snp# Chelsio T5 Factory Default configuration file. 2252661Snp# 3285527Snp# Copyright (C) 2010-2015 Chelsio Communications. All rights reserved. 4252661Snp# 5285527Snp# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6285527Snp# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7285527Snp# TO ADAPTERS. 8252661Snp 9285527Snp 10285527Snp# This file provides the default, power-on configuration for 4-port T5-based 11252661Snp# adapters shipped from the factory. These defaults are designed to address 12285527Snp# the needs of the vast majority of Terminator customers. The basic idea is to 13285527Snp# have a default configuration which allows a customer to plug a Terminator 14285527Snp# adapter in and have it work regardless of OS, driver or application except in 15285527Snp# the most unusual and/or demanding customer applications. 16252661Snp# 17285527Snp# Many of the Terminator resources which are described by this configuration 18285527Snp# are finite. This requires balancing the configuration/operation needs of 19252661Snp# device drivers across OSes and a large number of customer application. 20252661Snp# 21252661Snp# Some of the more important resources to allocate and their constaints are: 22285527Snp# 1. Virtual Interfaces: 256. 23285527Snp# 2. Ingress Queues with Free Lists: 1024. 24285527Snp# 3. Egress Queues: 128K. 25285527Snp# 4. MSI-X Vectors: 1088. 26252661Snp# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27252661Snp# address matching on Ingress Packets. 28252661Snp# 29252661Snp# Some of the important OS/Driver resource needs are: 30252661Snp# 6. Some OS Drivers will manage all resources through a single Physical 31285527Snp# Function (currently PF4 but it could be any Physical Function). 32252661Snp# 7. Some OS Drivers will manage different ports and functions (NIC, 33252661Snp# storage, etc.) on different Physical Functions. For example, NIC 34252661Snp# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 35252661Snp# 36252661Snp# Some of the customer application needs which need to be accommodated: 37252661Snp# 8. Some customers will want to support large CPU count systems with 38252661Snp# good scaling. Thus, we'll need to accommodate a number of 39252661Snp# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40252661Snp# to be involved per port and per application function. For example, 41252661Snp# in the case where all ports and application functions will be 42252661Snp# managed via a single Unified PF and we want to accommodate scaling up 43252661Snp# to 8 CPUs, we would want: 44252661Snp# 45252661Snp# 4 ports * 46252661Snp# 3 application functions (NIC, FCoE, iSCSI) per port * 47252661Snp# 8 Ingress Queue/MSI-X Vectors per application function 48252661Snp# 49252661Snp# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50252661Snp# (Plus a few for Firmware Event Queues, etc.) 51252661Snp# 52285527Snp# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53285527Snp# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54285527Snp# and "PCI Device Passthrough" -- this is especially true for the NIC 55285527Snp# application functionality. 56252661Snp# 57252661Snp 58252661Snp 59252661Snp# Global configuration settings. 60252661Snp# 61252661Snp[global] 62252661Snp rss_glb_config_mode = basicvirtual 63252661Snp rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64252661Snp 65252661Snp # PL_TIMEOUT register 66285527Snp pl_timeout_value = 10000 # the timeout value in units of us 67252661Snp 68252661Snp # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69252661Snp # Page Size and a 64B L1 Cache Line Size. It programs the 70252661Snp # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71252661Snp # If a Master PF Driver finds itself on a machine with different 72252661Snp # parameters, then the Master PF Driver is responsible for initializing 73252661Snp # these parameters to appropriate values. 74252661Snp # 75252661Snp # Notes: 76252661Snp # 1. The Free List Buffer Sizes below are raw and the firmware will 77252661Snp # round them up to the Ingress Padding Boundary. 78252661Snp # 2. The SGE Timer Values below are expressed below in microseconds. 79252661Snp # The firmware will convert these values to Core Clock Ticks when 80252661Snp # it processes the configuration parameters. 81252661Snp # 82252661Snp reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 83252661Snp reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84252661Snp reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85252661Snp reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86252661Snp reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87252661Snp reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88252661Snp reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89252661Snp reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90252661Snp reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91252661Snp reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92252661Snp reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93252661Snp reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94252661Snp reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 95252661Snp reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL 96252661Snp 97252661Snp # SGE_THROTTLE_CONTROL 98252661Snp bar2throttlecount = 500 # bar2throttlecount in us 99252661Snp 100252661Snp sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 101252661Snp 102252661Snp 103252661Snp reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if 104252661Snp # SGE_VFIFO_SIZE is not set, then 105252661Snp # firmware will set it up in function 106252661Snp # of number of egress queues used 107252661Snp 108252661Snp reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch 109252661Snp # threshold set to queue depth 110252661Snp # minus 128-entries for FL and HP 111252661Snp # queues, and 0xfff for LP which 112252661Snp # prompts the firmware to set it up 113252661Snp # in function of egress queues 114252661Snp # used 115252661Snp 116252661Snp reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which 117252661Snp # prompts the firmware to set it up in 118252661Snp # function of number of egress queues 119252661Snp # used 120252661Snp 121256459Snp # enable TP_OUT_CONFIG.IPIDSPLITMODE 122256459Snp reg[0x7d04] = 0x00010000/0x00010000 123256459Snp 124285527Snp reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 125252661Snp 126256459Snp # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 127256459Snp # filter control: compact, fcoemask 128256459Snp # server sram : srvrsram 129256459Snp # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 130256459Snp # protocol, tos, vlan, vnic_id, port, fcoe 131256459Snp # valid filterModes are described the Terminator 5 Data Book 132285527Snp filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 133256459Snp 134256459Snp # filter tuples enforced in LE active region (equal to or subset of filterMode) 135252661Snp filterMask = protocol, fcoe 136252661Snp 137252661Snp # Percentage of dynamic memory (in either the EDRAM or external MEM) 138252661Snp # to use for TP RX payload 139285527Snp tp_pmrx = 30 140252661Snp 141252661Snp # TP RX payload page size 142252661Snp tp_pmrx_pagesize = 64K 143252661Snp 144252661Snp # TP number of RX channels 145252661Snp tp_nrxch = 0 # 0 (auto) = 1 146252661Snp 147252661Snp # Percentage of dynamic memory (in either the EDRAM or external MEM) 148252661Snp # to use for TP TX payload 149285527Snp tp_pmtx = 50 150252661Snp 151252661Snp # TP TX payload page size 152252661Snp tp_pmtx_pagesize = 64K 153252661Snp 154252661Snp # TP number of TX channels 155252661Snp tp_ntxch = 0 # 0 (auto) = equal number of ports 156252661Snp 157256459Snp # TP OFLD MTUs 158256459Snp tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 159256459Snp 160252661Snp # TP_GLOBAL_CONFIG 161252661Snp reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 162252661Snp 163267757Snp # TP_PC_CONFIG 164267757Snp reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 165267757Snp 166256459Snp # TP_PARA_REG0 167256459Snp reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 168256459Snp 169285527Snp # ULPRX iSCSI Page Sizes 170285527Snp reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 171285527Snp 172252661Snp # LE_DB_CONFIG 173252661Snp reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable 174252661Snp 175256459Snp # MC configuration 176256459Snp mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 177256459Snp mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC 178256459Snp 179252661Snp# Some "definitions" to make the rest of this a bit more readable. We support 180252661Snp# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 181252661Snp# per function per port ... 182252661Snp# 183252661Snp# NMSIX = 1088 # available MSI-X Vectors 184252661Snp# NVI = 128 # available Virtual Interfaces 185252661Snp# NMPSTCAM = 336 # MPS TCAM entries 186252661Snp# 187252661Snp# NPORTS = 4 # ports 188252661Snp# NCPUS = 8 # CPUs we want to support scalably 189252661Snp# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 190252661Snp 191252661Snp# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 192252661Snp# PF" which many OS Drivers will use to manage most or all functions. 193252661Snp# 194252661Snp# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 195252661Snp# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 196252661Snp# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 197252661Snp# will be specified as the "Ingress Queue Asynchronous Destination Index." 198252661Snp# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 199252661Snp# than or equal to the number of Ingress Queues ... 200252661Snp# 201252661Snp# NVI_NIC = 4 # NIC access to NPORTS 202252661Snp# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 203252661Snp# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 204252661Snp# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 205252661Snp# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 206252661Snp# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 207285527Snp# 208252661Snp# NVI_OFLD = 0 # Offload uses NIC function to access ports 209252661Snp# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 210252661Snp# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 211252661Snp# NEQ_OFLD = 16 # Offload Egress Queues (FL) 212252661Snp# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 213252661Snp# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 214252661Snp# 215252661Snp# NVI_RDMA = 0 # RDMA uses NIC function to access ports 216252661Snp# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 217252661Snp# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 218252661Snp# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 219252661Snp# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 220252661Snp# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 221252661Snp# 222252661Snp# NEQ_WD = 128 # Wire Direct TX Queues and FLs 223252661Snp# NETHCTRL_WD = 64 # Wire Direct TX Queues 224252661Snp# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 225252661Snp# 226252661Snp# NVI_ISCSI = 4 # ISCSI access to NPORTS 227252661Snp# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 228252661Snp# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 229252661Snp# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 230252661Snp# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 231252661Snp# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 232252661Snp# 233252661Snp# NVI_FCOE = 4 # FCOE access to NPORTS 234252661Snp# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 235252661Snp# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 236252661Snp# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 237252661Snp# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 238252661Snp# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 239252661Snp 240252661Snp# Two extra Ingress Queues per function for Firmware Events and Forwarded 241252661Snp# Interrupts, and two extra interrupts per function for Firmware Events (or a 242252661Snp# Forwarded Interrupt Queue) and General Interrupts per function. 243252661Snp# 244252661Snp# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 245252661Snp# # Forwarded Interrupts 246252661Snp# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 247252661Snp# # General Interrupts 248252661Snp 249252661Snp# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 250252661Snp# their interrupts forwarded to another set of Forwarded Interrupt Queues. 251252661Snp# 252252661Snp# NVI_HYPERV = 16 # VMs we want to support 253252661Snp# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 254252661Snp# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 255252661Snp# NEQ_HYPERV = 32 # VIQs Free Lists 256252661Snp# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 257252661Snp# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 258252661Snp 259252661Snp# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 260252661Snp# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 261252661Snp# 262252661Snp# NVI_UNIFIED = 28 263252661Snp# NFLIQ_UNIFIED = 106 264252661Snp# NETHCTRL_UNIFIED = 32 265252661Snp# NEQ_UNIFIED = 124 266252661Snp# NMPSTCAM_UNIFIED = 40 267252661Snp# 268252661Snp# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 269252661Snp# that up to 128 to make sure the Unified PF doesn't run out of resources. 270252661Snp# 271252661Snp# NMSIX_UNIFIED = 128 272252661Snp# 273252661Snp# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 274252661Snp# which is 34 but they're probably safe with 32. 275252661Snp# 276252661Snp# NMSIX_STORAGE = 32 277252661Snp 278252661Snp# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 279252661Snp# associated with it. Thus, the MSI-X Vector allocations we give to the 280252661Snp# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 281252661Snp# provision many more Virtual Functions than we can if the UnifiedPF were 282252661Snp# one of PF0-3. 283252661Snp# 284252661Snp 285252661Snp# All of the below PCI-E parameters are actually stored in various *_init.txt 286252661Snp# files. We include them below essentially as comments. 287252661Snp# 288252661Snp# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 289252661Snp# ports 0-3. 290252661Snp# 291252661Snp# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 292252661Snp# 293252661Snp# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 294252661Snp# storage applications across all four possible ports. 295252661Snp# 296252661Snp# Additionally, since the UnifiedPF isn't one of the per-port Physical 297252661Snp# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 298252661Snp# different PCI Device IDs which will allow Unified and Per-Port Drivers 299252661Snp# to directly select the type of Physical Function to which they wish to be 300252661Snp# attached. 301252661Snp# 302252661Snp# Note that the actual values used for the PCI-E Intelectual Property will be 303252661Snp# 1 less than those below since that's the way it "counts" things. For 304252661Snp# readability, we use the number we actually mean ... 305252661Snp# 306252661Snp# PF0_INT = 8 # NCPUS 307252661Snp# PF1_INT = 8 # NCPUS 308252661Snp# PF2_INT = 8 # NCPUS 309252661Snp# PF3_INT = 8 # NCPUS 310252661Snp# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 311285527Snp# 312252661Snp# PF4_INT = 128 # NMSIX_UNIFIED 313252661Snp# PF5_INT = 32 # NMSIX_STORAGE 314252661Snp# PF6_INT = 32 # NMSIX_STORAGE 315252661Snp# PF7_INT = 0 # Nothing Assigned 316252661Snp# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 317285527Snp# 318252661Snp# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 319285527Snp# 320252661Snp# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 321252661Snp# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 322252661Snp# 323252661Snp# NVF = 16 324252661Snp 325285527Snp 326252661Snp# For those OSes which manage different ports on different PFs, we need 327252661Snp# only enough resources to support a single port's NIC application functions 328252661Snp# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 329252661Snp# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 330252661Snp# managed on the "storage PFs" (see below). 331252661Snp# 332252661Snp[function "0"] 333252661Snp nvf = 16 # NVF on this function 334252661Snp wx_caps = all # write/execute permissions for all commands 335252661Snp r_caps = all # read permissions for all commands 336252661Snp nvi = 1 # 1 port 337252661Snp niqflint = 8 # NCPUS "Queue Sets" 338252661Snp nethctrl = 8 # NCPUS "Queue Sets" 339252661Snp neq = 16 # niqflint + nethctrl Egress Queues 340252661Snp nexactf = 8 # number of exact MPSTCAM MAC filters 341252661Snp cmask = all # access to all channels 342252661Snp pmask = 0x1 # access to only one port 343252661Snp 344285527Snp 345252661Snp[function "1"] 346252661Snp nvf = 16 # NVF on this function 347252661Snp wx_caps = all # write/execute permissions for all commands 348252661Snp r_caps = all # read permissions for all commands 349252661Snp nvi = 1 # 1 port 350252661Snp niqflint = 8 # NCPUS "Queue Sets" 351252661Snp nethctrl = 8 # NCPUS "Queue Sets" 352252661Snp neq = 16 # niqflint + nethctrl Egress Queues 353252661Snp nexactf = 8 # number of exact MPSTCAM MAC filters 354252661Snp cmask = all # access to all channels 355252661Snp pmask = 0x2 # access to only one port 356252661Snp 357285527Snp 358252661Snp[function "2"] 359252661Snp nvf = 16 # NVF on this function 360252661Snp wx_caps = all # write/execute permissions for all commands 361252661Snp r_caps = all # read permissions for all commands 362252661Snp nvi = 1 # 1 port 363252661Snp niqflint = 8 # NCPUS "Queue Sets" 364252661Snp nethctrl = 8 # NCPUS "Queue Sets" 365252661Snp neq = 16 # niqflint + nethctrl Egress Queues 366252661Snp nexactf = 8 # number of exact MPSTCAM MAC filters 367252661Snp cmask = all # access to all channels 368252661Snp pmask = 0x4 # access to only one port 369252661Snp 370285527Snp 371252661Snp[function "3"] 372252661Snp nvf = 16 # NVF on this function 373252661Snp wx_caps = all # write/execute permissions for all commands 374252661Snp r_caps = all # read permissions for all commands 375252661Snp nvi = 1 # 1 port 376252661Snp niqflint = 8 # NCPUS "Queue Sets" 377252661Snp nethctrl = 8 # NCPUS "Queue Sets" 378252661Snp neq = 16 # niqflint + nethctrl Egress Queues 379252661Snp nexactf = 8 # number of exact MPSTCAM MAC filters 380252661Snp cmask = all # access to all channels 381252661Snp pmask = 0x8 # access to only one port 382252661Snp 383285527Snp 384252661Snp# Some OS Drivers manage all application functions for all ports via PF4. 385252661Snp# Thus we need to provide a large number of resources here. For Egress 386252661Snp# Queues we need to account for both TX Queues as well as Free List Queues 387252661Snp# (because the host is responsible for producing Free List Buffers for the 388252661Snp# hardware to consume). 389252661Snp# 390252661Snp[function "4"] 391252661Snp wx_caps = all # write/execute permissions for all commands 392252661Snp r_caps = all # read permissions for all commands 393252661Snp nvi = 28 # NVI_UNIFIED 394252661Snp niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 395252661Snp nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 396252661Snp neq = 256 # NEQ_UNIFIED + NEQ_WD 397285527Snp nqpcq = 12288 398252661Snp nexactf = 40 # NMPSTCAM_UNIFIED 399252661Snp cmask = all # access to all channels 400252661Snp pmask = all # access to all four ports ... 401252661Snp nethofld = 1024 # number of user mode ethernet flow contexts 402252661Snp nroute = 32 # number of routing region entries 403252661Snp nclip = 32 # number of clip region entries 404252661Snp nfilter = 496 # number of filter region entries 405252661Snp nserver = 496 # number of server region entries 406252661Snp nhash = 12288 # number of hash region entries 407285527Snp protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif 408252661Snp tp_l2t = 3072 409252661Snp tp_ddp = 2 410252661Snp tp_ddp_iscsi = 2 411252661Snp tp_stag = 2 412252661Snp tp_pbl = 5 413252661Snp tp_rq = 7 414252661Snp 415285527Snp 416252661Snp# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 417252661Snp# need to have Virtual Interfaces on each of the four ports with up to NCPUS 418252661Snp# "Queue Sets" each. 419252661Snp# 420252661Snp[function "5"] 421252661Snp wx_caps = all # write/execute permissions for all commands 422252661Snp r_caps = all # read permissions for all commands 423252661Snp nvi = 4 # NPORTS 424252661Snp niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 425252661Snp nethctrl = 32 # NPORTS*NCPUS 426252661Snp neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 427285527Snp nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 428252661Snp cmask = all # access to all channels 429252661Snp pmask = all # access to all four ports ... 430252661Snp nserver = 16 431252661Snp nhash = 2048 432267757Snp tp_l2t = 1020 433252661Snp protocol = iscsi_initiator_fofld 434252661Snp tp_ddp_iscsi = 2 435252661Snp iscsi_ntask = 2048 436252661Snp iscsi_nsess = 2048 437252661Snp iscsi_nconn_per_session = 1 438252661Snp iscsi_ninitiator_instance = 64 439252661Snp 440285527Snp 441252661Snp[function "6"] 442252661Snp wx_caps = all # write/execute permissions for all commands 443252661Snp r_caps = all # read permissions for all commands 444252661Snp nvi = 4 # NPORTS 445252661Snp niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 446252661Snp nethctrl = 32 # NPORTS*NCPUS 447252661Snp neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 448252661Snp nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 449252661Snp # which is OK since < MIN(SUM PF0..3, PF4) 450252661Snp # and we never load PF0..3 and PF4 concurrently 451252661Snp cmask = all # access to all channels 452252661Snp pmask = all # access to all four ports ... 453252661Snp nhash = 2048 454267757Snp tp_l2t = 4 455252661Snp protocol = fcoe_initiator 456252661Snp tp_ddp = 2 457252661Snp fcoe_nfcf = 16 458252661Snp fcoe_nvnp = 32 459252661Snp fcoe_nssn = 1024 460285527Snp fcoe_nfcb = 256 461252661Snp 462285527Snp 463252661Snp# The following function, 1023, is not an actual PCIE function but is used to 464252661Snp# configure and reserve firmware internal resources that come from the global 465252661Snp# resource pool. 466252661Snp# 467252661Snp[function "1023"] 468252661Snp wx_caps = all # write/execute permissions for all commands 469252661Snp r_caps = all # read permissions for all commands 470252661Snp nvi = 4 # NVI_UNIFIED 471252661Snp cmask = all # access to all channels 472252661Snp pmask = all # access to all four ports ... 473252661Snp nexactf = 8 # NPORTS + DCBX + 474252661Snp nfilter = 16 # number of filter region entries 475252661Snp 476285527Snp 477252661Snp# For Virtual functions, we only allow NIC functionality and we only allow 478252661Snp# access to one port (1 << PF). Note that because of limitations in the 479252661Snp# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 480252661Snp# and GTS registers, the number of Ingress and Egress Queues must be a power 481252661Snp# of 2. 482252661Snp# 483252661Snp[function "0/*"] # NVF 484252661Snp wx_caps = 0x82 # DMAQ | VF 485252661Snp r_caps = 0x86 # DMAQ | VF | PORT 486252661Snp nvi = 1 # 1 port 487252661Snp niqflint = 4 # 2 "Queue Sets" + NXIQ 488252661Snp nethctrl = 2 # 2 "Queue Sets" 489252661Snp neq = 4 # 2 "Queue Sets" * 2 490252661Snp nexactf = 4 491252661Snp cmask = all # access to all channels 492252661Snp pmask = 0x1 # access to only one port ... 493252661Snp 494285527Snp 495252661Snp[function "1/*"] # NVF 496252661Snp wx_caps = 0x82 # DMAQ | VF 497252661Snp r_caps = 0x86 # DMAQ | VF | PORT 498252661Snp nvi = 1 # 1 port 499252661Snp niqflint = 4 # 2 "Queue Sets" + NXIQ 500252661Snp nethctrl = 2 # 2 "Queue Sets" 501252661Snp neq = 4 # 2 "Queue Sets" * 2 502252661Snp nexactf = 4 503252661Snp cmask = all # access to all channels 504252661Snp pmask = 0x2 # access to only one port ... 505252661Snp 506285527Snp 507252661Snp[function "2/*"] # NVF 508252661Snp wx_caps = 0x82 # DMAQ | VF 509252661Snp r_caps = 0x86 # DMAQ | VF | PORT 510252661Snp nvi = 1 # 1 port 511252661Snp niqflint = 4 # 2 "Queue Sets" + NXIQ 512252661Snp nethctrl = 2 # 2 "Queue Sets" 513252661Snp neq = 4 # 2 "Queue Sets" * 2 514252661Snp nexactf = 4 515252661Snp cmask = all # access to all channels 516252661Snp pmask = 0x4 # access to only one port ... 517252661Snp 518285527Snp 519252661Snp[function "3/*"] # NVF 520252661Snp wx_caps = 0x82 # DMAQ | VF 521252661Snp r_caps = 0x86 # DMAQ | VF | PORT 522252661Snp nvi = 1 # 1 port 523252661Snp niqflint = 4 # 2 "Queue Sets" + NXIQ 524252661Snp nethctrl = 2 # 2 "Queue Sets" 525252661Snp neq = 4 # 2 "Queue Sets" * 2 526252661Snp nexactf = 4 527252661Snp cmask = all # access to all channels 528252661Snp pmask = 0x8 # access to only one port ... 529252661Snp 530285527Snp 531252661Snp# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 532252661Snp# for packets from the wire as well as the loopback path of the L2 switch. The 533252661Snp# folling params control how the buffer memory is distributed and the L2 flow 534252661Snp# control settings: 535252661Snp# 536252661Snp# bg_mem: %-age of mem to use for port/buffer group 537252661Snp# lpbk_mem: %-age of port/bg mem to use for loopback 538252661Snp# hwm: high watermark; bytes available when starting to send pause 539252661Snp# frames (in units of 0.1 MTU) 540252661Snp# lwm: low watermark; bytes remaining when sending 'unpause' frame 541252661Snp# (in inuits of 0.1 MTU) 542252661Snp# dwm: minimum delta between high and low watermark (in units of 100 543252661Snp# Bytes) 544252661Snp# 545252661Snp[port "0"] 546252661Snp dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 547252661Snp bg_mem = 25 548252661Snp lpbk_mem = 25 549252661Snp hwm = 30 550252661Snp lwm = 15 551252661Snp dwm = 30 552267757Snp dcb_app_tlv[0] = 0x8906, ethertype, 3 553267757Snp dcb_app_tlv[1] = 0x8914, ethertype, 3 554267757Snp dcb_app_tlv[2] = 3260, socketnum, 5 555252661Snp 556285527Snp 557252661Snp[port "1"] 558252661Snp dcb = ppp, dcbx 559252661Snp bg_mem = 25 560252661Snp lpbk_mem = 25 561252661Snp hwm = 30 562252661Snp lwm = 15 563252661Snp dwm = 30 564267757Snp dcb_app_tlv[0] = 0x8906, ethertype, 3 565267757Snp dcb_app_tlv[1] = 0x8914, ethertype, 3 566267757Snp dcb_app_tlv[2] = 3260, socketnum, 5 567252661Snp 568285527Snp 569252661Snp[port "2"] 570252661Snp dcb = ppp, dcbx 571252661Snp bg_mem = 25 572252661Snp lpbk_mem = 25 573252661Snp hwm = 30 574252661Snp lwm = 15 575252661Snp dwm = 30 576267757Snp dcb_app_tlv[0] = 0x8906, ethertype, 3 577267757Snp dcb_app_tlv[1] = 0x8914, ethertype, 3 578267757Snp dcb_app_tlv[2] = 3260, socketnum, 5 579252661Snp 580285527Snp 581252661Snp[port "3"] 582252661Snp dcb = ppp, dcbx 583252661Snp bg_mem = 25 584252661Snp lpbk_mem = 25 585252661Snp hwm = 30 586252661Snp lwm = 15 587252661Snp dwm = 30 588267757Snp dcb_app_tlv[0] = 0x8906, ethertype, 3 589267757Snp dcb_app_tlv[1] = 0x8914, ethertype, 3 590267757Snp dcb_app_tlv[2] = 3260, socketnum, 5 591252661Snp 592285527Snp 593252661Snp[fini] 594285527Snp version = 0x1425001c 595285527Snp checksum = 0xb1c3ae38 596252661Snp 597252661Snp# Total resources used by above allocations: 598252661Snp# Virtual Interfaces: 104 599252661Snp# Ingress Queues/w Free Lists and Interrupts: 526 600252661Snp# Egress Queues: 702 601252661Snp# MPS TCAM Entries: 336 602252661Snp# MSI-X Vectors: 736 603252661Snp# Virtual Functions: 64 604252661Snp# 605252661Snp# $FreeBSD: head/sys/dev/cxgbe/firmware/t5fw_cfg_uwire.txt 285527 2015-07-14 08:02:05Z np $ 606252661Snp# 607