cxgb_main.c revision 202671
1/************************************************************************** 2 3Copyright (c) 2007-2009, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28***************************************************************************/ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_main.c 202671 2010-01-20 03:40:43Z np $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/module.h> 38#include <sys/pciio.h> 39#include <sys/conf.h> 40#include <machine/bus.h> 41#include <machine/resource.h> 42#include <sys/bus_dma.h> 43#include <sys/ktr.h> 44#include <sys/rman.h> 45#include <sys/ioccom.h> 46#include <sys/mbuf.h> 47#include <sys/linker.h> 48#include <sys/firmware.h> 49#include <sys/socket.h> 50#include <sys/sockio.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <sys/syslog.h> 54#include <sys/queue.h> 55#include <sys/taskqueue.h> 56#include <sys/proc.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64#include <net/if_types.h> 65#include <net/if_vlan_var.h> 66 67#include <netinet/in_systm.h> 68#include <netinet/in.h> 69#include <netinet/if_ether.h> 70#include <netinet/ip.h> 71#include <netinet/ip.h> 72#include <netinet/tcp.h> 73#include <netinet/udp.h> 74 75#include <dev/pci/pcireg.h> 76#include <dev/pci/pcivar.h> 77#include <dev/pci/pci_private.h> 78 79#include <cxgb_include.h> 80 81#ifdef PRIV_SUPPORTED 82#include <sys/priv.h> 83#endif 84 85static int cxgb_setup_interrupts(adapter_t *); 86static void cxgb_teardown_interrupts(adapter_t *); 87static void cxgb_init(void *); 88static int cxgb_init_locked(struct port_info *); 89static int cxgb_uninit_locked(struct port_info *); 90static int cxgb_uninit_synchronized(struct port_info *); 91static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 92static int cxgb_media_change(struct ifnet *); 93static int cxgb_ifm_type(int); 94static void cxgb_build_medialist(struct port_info *); 95static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 96static int setup_sge_qsets(adapter_t *); 97static void cxgb_async_intr(void *); 98static void cxgb_ext_intr_handler(void *, int); 99static void cxgb_tick_handler(void *, int); 100static void cxgb_tick(void *); 101static void setup_rss(adapter_t *sc); 102 103/* Attachment glue for the PCI controller end of the device. Each port of 104 * the device is attached separately, as defined later. 105 */ 106static int cxgb_controller_probe(device_t); 107static int cxgb_controller_attach(device_t); 108static int cxgb_controller_detach(device_t); 109static void cxgb_free(struct adapter *); 110static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 111 unsigned int end); 112static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf); 113static int cxgb_get_regs_len(void); 114static int offload_open(struct port_info *pi); 115static void touch_bars(device_t dev); 116static int offload_close(struct t3cdev *tdev); 117static void cxgb_update_mac_settings(struct port_info *p); 118 119static device_method_t cxgb_controller_methods[] = { 120 DEVMETHOD(device_probe, cxgb_controller_probe), 121 DEVMETHOD(device_attach, cxgb_controller_attach), 122 DEVMETHOD(device_detach, cxgb_controller_detach), 123 124 /* bus interface */ 125 DEVMETHOD(bus_print_child, bus_generic_print_child), 126 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 127 128 { 0, 0 } 129}; 130 131static driver_t cxgb_controller_driver = { 132 "cxgbc", 133 cxgb_controller_methods, 134 sizeof(struct adapter) 135}; 136 137static devclass_t cxgb_controller_devclass; 138DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 139 140/* 141 * Attachment glue for the ports. Attachment is done directly to the 142 * controller device. 143 */ 144static int cxgb_port_probe(device_t); 145static int cxgb_port_attach(device_t); 146static int cxgb_port_detach(device_t); 147 148static device_method_t cxgb_port_methods[] = { 149 DEVMETHOD(device_probe, cxgb_port_probe), 150 DEVMETHOD(device_attach, cxgb_port_attach), 151 DEVMETHOD(device_detach, cxgb_port_detach), 152 { 0, 0 } 153}; 154 155static driver_t cxgb_port_driver = { 156 "cxgb", 157 cxgb_port_methods, 158 0 159}; 160 161static d_ioctl_t cxgb_extension_ioctl; 162static d_open_t cxgb_extension_open; 163static d_close_t cxgb_extension_close; 164 165static struct cdevsw cxgb_cdevsw = { 166 .d_version = D_VERSION, 167 .d_flags = 0, 168 .d_open = cxgb_extension_open, 169 .d_close = cxgb_extension_close, 170 .d_ioctl = cxgb_extension_ioctl, 171 .d_name = "cxgb", 172}; 173 174static devclass_t cxgb_port_devclass; 175DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 176 177/* 178 * The driver uses the best interrupt scheme available on a platform in the 179 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 180 * of these schemes the driver may consider as follows: 181 * 182 * msi = 2: choose from among all three options 183 * msi = 1 : only consider MSI and pin interrupts 184 * msi = 0: force pin interrupts 185 */ 186static int msi_allowed = 2; 187 188TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 189SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 190SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 191 "MSI-X, MSI, INTx selector"); 192 193/* 194 * The driver enables offload as a default. 195 * To disable it, use ofld_disable = 1. 196 */ 197static int ofld_disable = 0; 198TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 199SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 200 "disable ULP offload"); 201 202/* 203 * The driver uses an auto-queue algorithm by default. 204 * To disable it and force a single queue-set per port, use multiq = 0 205 */ 206static int multiq = 1; 207TUNABLE_INT("hw.cxgb.multiq", &multiq); 208SYSCTL_UINT(_hw_cxgb, OID_AUTO, multiq, CTLFLAG_RDTUN, &multiq, 0, 209 "use min(ncpus/ports, 8) queue-sets per port"); 210 211/* 212 * By default the driver will not update the firmware unless 213 * it was compiled against a newer version 214 * 215 */ 216static int force_fw_update = 0; 217TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 218SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 219 "update firmware even if up to date"); 220 221int cxgb_use_16k_clusters = 1; 222TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 223SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 224 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 225 226/* 227 * Tune the size of the output queue. 228 */ 229int cxgb_snd_queue_len = IFQ_MAXLEN; 230TUNABLE_INT("hw.cxgb.snd_queue_len", &cxgb_snd_queue_len); 231SYSCTL_UINT(_hw_cxgb, OID_AUTO, snd_queue_len, CTLFLAG_RDTUN, 232 &cxgb_snd_queue_len, 0, "send queue size "); 233 234 235enum { 236 MAX_TXQ_ENTRIES = 16384, 237 MAX_CTRL_TXQ_ENTRIES = 1024, 238 MAX_RSPQ_ENTRIES = 16384, 239 MAX_RX_BUFFERS = 16384, 240 MAX_RX_JUMBO_BUFFERS = 16384, 241 MIN_TXQ_ENTRIES = 4, 242 MIN_CTRL_TXQ_ENTRIES = 4, 243 MIN_RSPQ_ENTRIES = 32, 244 MIN_FL_ENTRIES = 32, 245 MIN_FL_JUMBO_ENTRIES = 32 246}; 247 248struct filter_info { 249 u32 sip; 250 u32 sip_mask; 251 u32 dip; 252 u16 sport; 253 u16 dport; 254 u32 vlan:12; 255 u32 vlan_prio:3; 256 u32 mac_hit:1; 257 u32 mac_idx:4; 258 u32 mac_vld:1; 259 u32 pkt_type:2; 260 u32 report_filter_id:1; 261 u32 pass:1; 262 u32 rss:1; 263 u32 qset:3; 264 u32 locked:1; 265 u32 valid:1; 266}; 267 268enum { FILTER_NO_VLAN_PRI = 7 }; 269 270#define EEPROM_MAGIC 0x38E2F10C 271 272#define PORT_MASK ((1 << MAX_NPORTS) - 1) 273 274/* Table for probing the cards. The desc field isn't actually used */ 275struct cxgb_ident { 276 uint16_t vendor; 277 uint16_t device; 278 int index; 279 char *desc; 280} cxgb_identifiers[] = { 281 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 282 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 283 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 284 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 285 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 286 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 287 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 288 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 289 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 290 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 291 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 292 {PCI_VENDOR_ID_CHELSIO, 0x0035, 6, "T3C10"}, 293 {PCI_VENDOR_ID_CHELSIO, 0x0036, 3, "S320E-CR"}, 294 {PCI_VENDOR_ID_CHELSIO, 0x0037, 7, "N320E-G2"}, 295 {0, 0, 0, NULL} 296}; 297 298static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 299 300 301static __inline char 302t3rev2char(struct adapter *adapter) 303{ 304 char rev = 'z'; 305 306 switch(adapter->params.rev) { 307 case T3_REV_A: 308 rev = 'a'; 309 break; 310 case T3_REV_B: 311 case T3_REV_B2: 312 rev = 'b'; 313 break; 314 case T3_REV_C: 315 rev = 'c'; 316 break; 317 } 318 return rev; 319} 320 321static struct cxgb_ident * 322cxgb_get_ident(device_t dev) 323{ 324 struct cxgb_ident *id; 325 326 for (id = cxgb_identifiers; id->desc != NULL; id++) { 327 if ((id->vendor == pci_get_vendor(dev)) && 328 (id->device == pci_get_device(dev))) { 329 return (id); 330 } 331 } 332 return (NULL); 333} 334 335static const struct adapter_info * 336cxgb_get_adapter_info(device_t dev) 337{ 338 struct cxgb_ident *id; 339 const struct adapter_info *ai; 340 341 id = cxgb_get_ident(dev); 342 if (id == NULL) 343 return (NULL); 344 345 ai = t3_get_adapter_info(id->index); 346 347 return (ai); 348} 349 350static int 351cxgb_controller_probe(device_t dev) 352{ 353 const struct adapter_info *ai; 354 char *ports, buf[80]; 355 int nports; 356 357 ai = cxgb_get_adapter_info(dev); 358 if (ai == NULL) 359 return (ENXIO); 360 361 nports = ai->nports0 + ai->nports1; 362 if (nports == 1) 363 ports = "port"; 364 else 365 ports = "ports"; 366 367 snprintf(buf, sizeof(buf), "%s, %d %s", ai->desc, nports, ports); 368 device_set_desc_copy(dev, buf); 369 return (BUS_PROBE_DEFAULT); 370} 371 372#define FW_FNAME "cxgb_t3fw" 373#define TPEEPROM_NAME "cxgb_t3%c_tp_eeprom" 374#define TPSRAM_NAME "cxgb_t3%c_protocol_sram" 375 376static int 377upgrade_fw(adapter_t *sc) 378{ 379#ifdef FIRMWARE_LATEST 380 const struct firmware *fw; 381#else 382 struct firmware *fw; 383#endif 384 int status; 385 386 if ((fw = firmware_get(FW_FNAME)) == NULL) { 387 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 388 return (ENOENT); 389 } else 390 device_printf(sc->dev, "updating firmware on card\n"); 391 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 392 393 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 394 395 firmware_put(fw, FIRMWARE_UNLOAD); 396 397 return (status); 398} 399 400/* 401 * The cxgb_controller_attach function is responsible for the initial 402 * bringup of the device. Its responsibilities include: 403 * 404 * 1. Determine if the device supports MSI or MSI-X. 405 * 2. Allocate bus resources so that we can access the Base Address Register 406 * 3. Create and initialize mutexes for the controller and its control 407 * logic such as SGE and MDIO. 408 * 4. Call hardware specific setup routine for the adapter as a whole. 409 * 5. Allocate the BAR for doing MSI-X. 410 * 6. Setup the line interrupt iff MSI-X is not supported. 411 * 7. Create the driver's taskq. 412 * 8. Start one task queue service thread. 413 * 9. Check if the firmware and SRAM are up-to-date. They will be 414 * auto-updated later (before FULL_INIT_DONE), if required. 415 * 10. Create a child device for each MAC (port) 416 * 11. Initialize T3 private state. 417 * 12. Trigger the LED 418 * 13. Setup offload iff supported. 419 * 14. Reset/restart the tick callout. 420 * 15. Attach sysctls 421 * 422 * NOTE: Any modification or deviation from this list MUST be reflected in 423 * the above comment. Failure to do so will result in problems on various 424 * error conditions including link flapping. 425 */ 426static int 427cxgb_controller_attach(device_t dev) 428{ 429 device_t child; 430 const struct adapter_info *ai; 431 struct adapter *sc; 432 int i, error = 0; 433 uint32_t vers; 434 int port_qsets = 1; 435#ifdef MSI_SUPPORTED 436 int msi_needed, reg; 437#endif 438 char buf[80]; 439 440 sc = device_get_softc(dev); 441 sc->dev = dev; 442 sc->msi_count = 0; 443 ai = cxgb_get_adapter_info(dev); 444 445 /* 446 * XXX not really related but a recent addition 447 */ 448#ifdef MSI_SUPPORTED 449 /* find the PCIe link width and set max read request to 4KB*/ 450 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 451 uint16_t lnk, pectl; 452 lnk = pci_read_config(dev, reg + 0x12, 2); 453 sc->link_width = (lnk >> 4) & 0x3f; 454 455 pectl = pci_read_config(dev, reg + 0x8, 2); 456 pectl = (pectl & ~0x7000) | (5 << 12); 457 pci_write_config(dev, reg + 0x8, pectl, 2); 458 } 459 460 if (sc->link_width != 0 && sc->link_width <= 4 && 461 (ai->nports0 + ai->nports1) <= 2) { 462 device_printf(sc->dev, 463 "PCIe x%d Link, expect reduced performance\n", 464 sc->link_width); 465 } 466#endif 467 touch_bars(dev); 468 pci_enable_busmaster(dev); 469 /* 470 * Allocate the registers and make them available to the driver. 471 * The registers that we care about for NIC mode are in BAR 0 472 */ 473 sc->regs_rid = PCIR_BAR(0); 474 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 475 &sc->regs_rid, RF_ACTIVE)) == NULL) { 476 device_printf(dev, "Cannot allocate BAR region 0\n"); 477 return (ENXIO); 478 } 479 sc->udbs_rid = PCIR_BAR(2); 480 sc->udbs_res = NULL; 481 if (is_offload(sc) && 482 ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 483 &sc->udbs_rid, RF_ACTIVE)) == NULL)) { 484 device_printf(dev, "Cannot allocate BAR region 1\n"); 485 error = ENXIO; 486 goto out; 487 } 488 489 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 490 device_get_unit(dev)); 491 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 492 493 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 494 device_get_unit(dev)); 495 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 496 device_get_unit(dev)); 497 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 498 device_get_unit(dev)); 499 500 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 501 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 502 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 503 504 sc->bt = rman_get_bustag(sc->regs_res); 505 sc->bh = rman_get_bushandle(sc->regs_res); 506 sc->mmio_len = rman_get_size(sc->regs_res); 507 508 for (i = 0; i < MAX_NPORTS; i++) 509 sc->port[i].adapter = sc; 510 511 if (t3_prep_adapter(sc, ai, 1) < 0) { 512 printf("prep adapter failed\n"); 513 error = ENODEV; 514 goto out; 515 } 516 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 517 * enough messages for the queue sets. If that fails, try falling 518 * back to MSI. If that fails, then try falling back to the legacy 519 * interrupt pin model. 520 */ 521#ifdef MSI_SUPPORTED 522 523 sc->msix_regs_rid = 0x20; 524 if ((msi_allowed >= 2) && 525 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 526 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 527 528 if (multiq) 529 port_qsets = min(SGE_QSETS/sc->params.nports, mp_ncpus); 530 msi_needed = sc->msi_count = sc->params.nports * port_qsets + 1; 531 532 if (pci_msix_count(dev) == 0 || 533 (error = pci_alloc_msix(dev, &sc->msi_count)) != 0 || 534 sc->msi_count != msi_needed) { 535 device_printf(dev, "alloc msix failed - " 536 "msi_count=%d, msi_needed=%d, err=%d; " 537 "will try MSI\n", sc->msi_count, 538 msi_needed, error); 539 sc->msi_count = 0; 540 port_qsets = 1; 541 pci_release_msi(dev); 542 bus_release_resource(dev, SYS_RES_MEMORY, 543 sc->msix_regs_rid, sc->msix_regs_res); 544 sc->msix_regs_res = NULL; 545 } else { 546 sc->flags |= USING_MSIX; 547 sc->cxgb_intr = cxgb_async_intr; 548 device_printf(dev, 549 "using MSI-X interrupts (%u vectors)\n", 550 sc->msi_count); 551 } 552 } 553 554 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 555 sc->msi_count = 1; 556 if ((error = pci_alloc_msi(dev, &sc->msi_count)) != 0) { 557 device_printf(dev, "alloc msi failed - " 558 "err=%d; will try INTx\n", error); 559 sc->msi_count = 0; 560 port_qsets = 1; 561 pci_release_msi(dev); 562 } else { 563 sc->flags |= USING_MSI; 564 sc->cxgb_intr = t3_intr_msi; 565 device_printf(dev, "using MSI interrupts\n"); 566 } 567 } 568#endif 569 if (sc->msi_count == 0) { 570 device_printf(dev, "using line interrupts\n"); 571 sc->cxgb_intr = t3b_intr; 572 } 573 574 /* Create a private taskqueue thread for handling driver events */ 575#ifdef TASKQUEUE_CURRENT 576 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 577 taskqueue_thread_enqueue, &sc->tq); 578#else 579 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 580 taskqueue_thread_enqueue, &sc->tq); 581#endif 582 if (sc->tq == NULL) { 583 device_printf(dev, "failed to allocate controller task queue\n"); 584 goto out; 585 } 586 587 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 588 device_get_nameunit(dev)); 589 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 590 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 591 592 593 /* Create a periodic callout for checking adapter status */ 594 callout_init(&sc->cxgb_tick_ch, TRUE); 595 596 if (t3_check_fw_version(sc) < 0 || force_fw_update) { 597 /* 598 * Warn user that a firmware update will be attempted in init. 599 */ 600 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 601 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 602 sc->flags &= ~FW_UPTODATE; 603 } else { 604 sc->flags |= FW_UPTODATE; 605 } 606 607 if (t3_check_tpsram_version(sc) < 0) { 608 /* 609 * Warn user that a firmware update will be attempted in init. 610 */ 611 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 612 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 613 sc->flags &= ~TPS_UPTODATE; 614 } else { 615 sc->flags |= TPS_UPTODATE; 616 } 617 618 /* 619 * Create a child device for each MAC. The ethernet attachment 620 * will be done in these children. 621 */ 622 for (i = 0; i < (sc)->params.nports; i++) { 623 struct port_info *pi; 624 625 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 626 device_printf(dev, "failed to add child port\n"); 627 error = EINVAL; 628 goto out; 629 } 630 pi = &sc->port[i]; 631 pi->adapter = sc; 632 pi->nqsets = port_qsets; 633 pi->first_qset = i*port_qsets; 634 pi->port_id = i; 635 pi->tx_chan = i >= ai->nports0; 636 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 637 sc->rxpkt_map[pi->txpkt_intf] = i; 638 sc->port[i].tx_chan = i >= ai->nports0; 639 sc->portdev[i] = child; 640 device_set_softc(child, pi); 641 } 642 if ((error = bus_generic_attach(dev)) != 0) 643 goto out; 644 645 /* initialize sge private state */ 646 t3_sge_init_adapter(sc); 647 648 t3_led_ready(sc); 649 650 cxgb_offload_init(); 651 if (is_offload(sc)) { 652 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 653 cxgb_adapter_ofld(sc); 654 } 655 error = t3_get_fw_version(sc, &vers); 656 if (error) 657 goto out; 658 659 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 660 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 661 G_FW_VERSION_MICRO(vers)); 662 663 snprintf(buf, sizeof(buf), "%s %sNIC\t E/C: %s S/N: %s", 664 ai->desc, is_offload(sc) ? "R" : "", 665 sc->params.vpd.ec, sc->params.vpd.sn); 666 device_set_desc_copy(dev, buf); 667 668 snprintf(&sc->port_types[0], sizeof(sc->port_types), "%x%x%x%x", 669 sc->params.vpd.port_type[0], sc->params.vpd.port_type[1], 670 sc->params.vpd.port_type[2], sc->params.vpd.port_type[3]); 671 672 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 673 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 674 t3_add_attach_sysctls(sc); 675out: 676 if (error) 677 cxgb_free(sc); 678 679 return (error); 680} 681 682/* 683 * The cxgb_controller_detach routine is called with the device is 684 * unloaded from the system. 685 */ 686 687static int 688cxgb_controller_detach(device_t dev) 689{ 690 struct adapter *sc; 691 692 sc = device_get_softc(dev); 693 694 cxgb_free(sc); 695 696 return (0); 697} 698 699/* 700 * The cxgb_free() is called by the cxgb_controller_detach() routine 701 * to tear down the structures that were built up in 702 * cxgb_controller_attach(), and should be the final piece of work 703 * done when fully unloading the driver. 704 * 705 * 706 * 1. Shutting down the threads started by the cxgb_controller_attach() 707 * routine. 708 * 2. Stopping the lower level device and all callouts (cxgb_down_locked()). 709 * 3. Detaching all of the port devices created during the 710 * cxgb_controller_attach() routine. 711 * 4. Removing the device children created via cxgb_controller_attach(). 712 * 5. Releasing PCI resources associated with the device. 713 * 6. Turning off the offload support, iff it was turned on. 714 * 7. Destroying the mutexes created in cxgb_controller_attach(). 715 * 716 */ 717static void 718cxgb_free(struct adapter *sc) 719{ 720 int i; 721 722 ADAPTER_LOCK(sc); 723 sc->flags |= CXGB_SHUTDOWN; 724 ADAPTER_UNLOCK(sc); 725 726 /* 727 * Make sure all child devices are gone. 728 */ 729 bus_generic_detach(sc->dev); 730 for (i = 0; i < (sc)->params.nports; i++) { 731 if (sc->portdev[i] && 732 device_delete_child(sc->dev, sc->portdev[i]) != 0) 733 device_printf(sc->dev, "failed to delete child port\n"); 734 } 735 736 /* 737 * At this point, it is as if cxgb_port_detach has run on all ports, and 738 * cxgb_down has run on the adapter. All interrupts have been silenced, 739 * all open devices have been closed. 740 */ 741 KASSERT(sc->open_device_map == 0, ("%s: device(s) still open (%x)", 742 __func__, sc->open_device_map)); 743 for (i = 0; i < sc->params.nports; i++) { 744 KASSERT(sc->port[i].ifp == NULL, ("%s: port %i undead!", 745 __func__, i)); 746 } 747 748 /* 749 * Finish off the adapter's callouts. 750 */ 751 callout_drain(&sc->cxgb_tick_ch); 752 callout_drain(&sc->sge_timer_ch); 753 754 /* 755 * Release resources grabbed under FULL_INIT_DONE by cxgb_up. The 756 * sysctls are cleaned up by the kernel linker. 757 */ 758 if (sc->flags & FULL_INIT_DONE) { 759 t3_free_sge_resources(sc); 760 sc->flags &= ~FULL_INIT_DONE; 761 } 762 763 /* 764 * Release all interrupt resources. 765 */ 766 cxgb_teardown_interrupts(sc); 767#ifdef MSI_SUPPORTED 768 if (sc->flags & (USING_MSI | USING_MSIX)) { 769 device_printf(sc->dev, "releasing msi message(s)\n"); 770 pci_release_msi(sc->dev); 771 } else { 772 device_printf(sc->dev, "no msi message to release\n"); 773 } 774 775 if (sc->msix_regs_res != NULL) { 776 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 777 sc->msix_regs_res); 778 } 779#endif 780 781 /* 782 * Free the adapter's taskqueue. 783 */ 784 if (sc->tq != NULL) { 785 taskqueue_free(sc->tq); 786 sc->tq = NULL; 787 } 788 789 if (is_offload(sc)) { 790 clrbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 791 cxgb_adapter_unofld(sc); 792 } 793 794#ifdef notyet 795 if (sc->flags & CXGB_OFLD_INIT) 796 cxgb_offload_deactivate(sc); 797#endif 798 free(sc->filters, M_DEVBUF); 799 t3_sge_free(sc); 800 801 cxgb_offload_exit(); 802 803 if (sc->udbs_res != NULL) 804 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 805 sc->udbs_res); 806 807 if (sc->regs_res != NULL) 808 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 809 sc->regs_res); 810 811 MTX_DESTROY(&sc->mdio_lock); 812 MTX_DESTROY(&sc->sge.reg_lock); 813 MTX_DESTROY(&sc->elmer_lock); 814 ADAPTER_LOCK_DEINIT(sc); 815} 816 817/** 818 * setup_sge_qsets - configure SGE Tx/Rx/response queues 819 * @sc: the controller softc 820 * 821 * Determines how many sets of SGE queues to use and initializes them. 822 * We support multiple queue sets per port if we have MSI-X, otherwise 823 * just one queue set per port. 824 */ 825static int 826setup_sge_qsets(adapter_t *sc) 827{ 828 int i, j, err, irq_idx = 0, qset_idx = 0; 829 u_int ntxq = SGE_TXQ_PER_SET; 830 831 if ((err = t3_sge_alloc(sc)) != 0) { 832 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 833 return (err); 834 } 835 836 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 837 irq_idx = -1; 838 839 for (i = 0; i < (sc)->params.nports; i++) { 840 struct port_info *pi = &sc->port[i]; 841 842 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 843 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 844 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 845 &sc->params.sge.qset[qset_idx], ntxq, pi); 846 if (err) { 847 t3_free_sge_resources(sc); 848 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 849 err); 850 return (err); 851 } 852 } 853 } 854 855 return (0); 856} 857 858static void 859cxgb_teardown_interrupts(adapter_t *sc) 860{ 861 int i; 862 863 for (i = 0; i < SGE_QSETS; i++) { 864 if (sc->msix_intr_tag[i] == NULL) { 865 866 /* Should have been setup fully or not at all */ 867 KASSERT(sc->msix_irq_res[i] == NULL && 868 sc->msix_irq_rid[i] == 0, 869 ("%s: half-done interrupt (%d).", __func__, i)); 870 871 continue; 872 } 873 874 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 875 sc->msix_intr_tag[i]); 876 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->msix_irq_rid[i], 877 sc->msix_irq_res[i]); 878 879 sc->msix_irq_res[i] = sc->msix_intr_tag[i] = NULL; 880 sc->msix_irq_rid[i] = 0; 881 } 882 883 if (sc->intr_tag) { 884 KASSERT(sc->irq_res != NULL, 885 ("%s: half-done interrupt.", __func__)); 886 887 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 888 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 889 sc->irq_res); 890 891 sc->irq_res = sc->intr_tag = NULL; 892 sc->irq_rid = 0; 893 } 894} 895 896static int 897cxgb_setup_interrupts(adapter_t *sc) 898{ 899 struct resource *res; 900 void *tag; 901 int i, rid, err, intr_flag = sc->flags & (USING_MSI | USING_MSIX); 902 903 sc->irq_rid = intr_flag ? 1 : 0; 904 sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irq_rid, 905 RF_SHAREABLE | RF_ACTIVE); 906 if (sc->irq_res == NULL) { 907 device_printf(sc->dev, "Cannot allocate interrupt (%x, %u)\n", 908 intr_flag, sc->irq_rid); 909 err = EINVAL; 910 sc->irq_rid = 0; 911 } else { 912 err = bus_setup_intr(sc->dev, sc->irq_res, 913 INTR_MPSAFE | INTR_TYPE_NET, 914#ifdef INTR_FILTERS 915 NULL, 916#endif 917 sc->cxgb_intr, sc, &sc->intr_tag); 918 919 if (err) { 920 device_printf(sc->dev, 921 "Cannot set up interrupt (%x, %u, %d)\n", 922 intr_flag, sc->irq_rid, err); 923 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 924 sc->irq_res); 925 sc->irq_res = sc->intr_tag = NULL; 926 sc->irq_rid = 0; 927 } 928 } 929 930 /* That's all for INTx or MSI */ 931 if (!(intr_flag & USING_MSIX) || err) 932 return (err); 933 934 for (i = 0; i < sc->msi_count - 1; i++) { 935 rid = i + 2; 936 res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, 937 RF_SHAREABLE | RF_ACTIVE); 938 if (res == NULL) { 939 device_printf(sc->dev, "Cannot allocate interrupt " 940 "for message %d\n", rid); 941 err = EINVAL; 942 break; 943 } 944 945 err = bus_setup_intr(sc->dev, res, INTR_MPSAFE | INTR_TYPE_NET, 946#ifdef INTR_FILTERS 947 NULL, 948#endif 949 t3_intr_msix, &sc->sge.qs[i], &tag); 950 if (err) { 951 device_printf(sc->dev, "Cannot set up interrupt " 952 "for message %d (%d)\n", rid, err); 953 bus_release_resource(sc->dev, SYS_RES_IRQ, rid, res); 954 break; 955 } 956 957 sc->msix_irq_rid[i] = rid; 958 sc->msix_irq_res[i] = res; 959 sc->msix_intr_tag[i] = tag; 960 } 961 962 if (err) 963 cxgb_teardown_interrupts(sc); 964 965 return (err); 966} 967 968 969static int 970cxgb_port_probe(device_t dev) 971{ 972 struct port_info *p; 973 char buf[80]; 974 const char *desc; 975 976 p = device_get_softc(dev); 977 desc = p->phy.desc; 978 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 979 device_set_desc_copy(dev, buf); 980 return (0); 981} 982 983 984static int 985cxgb_makedev(struct port_info *pi) 986{ 987 988 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 989 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 990 991 if (pi->port_cdev == NULL) 992 return (ENOMEM); 993 994 pi->port_cdev->si_drv1 = (void *)pi; 995 996 return (0); 997} 998 999#ifndef LRO_SUPPORTED 1000#ifdef IFCAP_LRO 1001#undef IFCAP_LRO 1002#endif 1003#define IFCAP_LRO 0x0 1004#endif 1005 1006#ifdef TSO_SUPPORTED 1007#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO) 1008/* Don't enable TSO6 yet */ 1009#define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_LRO) 1010#else 1011#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 1012/* Don't enable TSO6 yet */ 1013#define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 1014#define IFCAP_TSO4 0x0 1015#define IFCAP_TSO6 0x0 1016#define CSUM_TSO 0x0 1017#endif 1018 1019 1020static int 1021cxgb_port_attach(device_t dev) 1022{ 1023 struct port_info *p; 1024 struct ifnet *ifp; 1025 int err; 1026 struct adapter *sc; 1027 1028 1029 p = device_get_softc(dev); 1030 sc = p->adapter; 1031 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 1032 device_get_unit(device_get_parent(dev)), p->port_id); 1033 PORT_LOCK_INIT(p, p->lockbuf); 1034 1035 /* Allocate an ifnet object and set it up */ 1036 ifp = p->ifp = if_alloc(IFT_ETHER); 1037 if (ifp == NULL) { 1038 device_printf(dev, "Cannot allocate ifnet\n"); 1039 return (ENOMEM); 1040 } 1041 1042 /* 1043 * Note that there is currently no watchdog timer. 1044 */ 1045 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1046 ifp->if_init = cxgb_init; 1047 ifp->if_softc = p; 1048 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1049 ifp->if_ioctl = cxgb_ioctl; 1050 ifp->if_start = cxgb_start; 1051 1052 ifp->if_snd.ifq_drv_maxlen = cxgb_snd_queue_len; 1053 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1054 IFQ_SET_READY(&ifp->if_snd); 1055 1056 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 1057 ifp->if_capabilities |= CXGB_CAP; 1058 ifp->if_capenable |= CXGB_CAP_ENABLE; 1059 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 1060 /* 1061 * disable TSO on 4-port - it isn't supported by the firmware yet 1062 */ 1063 if (p->adapter->params.nports > 2) { 1064 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 1065 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 1066 ifp->if_hwassist &= ~CSUM_TSO; 1067 } 1068 1069 ether_ifattach(ifp, p->hw_addr); 1070 ifp->if_transmit = cxgb_transmit; 1071 ifp->if_qflush = cxgb_qflush; 1072 1073 /* 1074 * Only default to jumbo frames on 10GigE 1075 */ 1076 if (p->adapter->params.nports <= 2) 1077 ifp->if_mtu = ETHERMTU_JUMBO; 1078 if ((err = cxgb_makedev(p)) != 0) { 1079 printf("makedev failed %d\n", err); 1080 return (err); 1081 } 1082 1083 /* Create a list of media supported by this port */ 1084 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 1085 cxgb_media_status); 1086 cxgb_build_medialist(p); 1087 1088 t3_sge_init_port(p); 1089 1090 return (err); 1091} 1092 1093/* 1094 * cxgb_port_detach() is called via the device_detach methods when 1095 * cxgb_free() calls the bus_generic_detach. It is responsible for 1096 * removing the device from the view of the kernel, i.e. from all 1097 * interfaces lists etc. This routine is only called when the driver is 1098 * being unloaded, not when the link goes down. 1099 */ 1100static int 1101cxgb_port_detach(device_t dev) 1102{ 1103 struct port_info *p; 1104 struct adapter *sc; 1105 int i; 1106 1107 p = device_get_softc(dev); 1108 sc = p->adapter; 1109 1110 /* Tell cxgb_ioctl and if_init that the port is going away */ 1111 ADAPTER_LOCK(sc); 1112 SET_DOOMED(p); 1113 wakeup(&sc->flags); 1114 while (IS_BUSY(sc)) 1115 mtx_sleep(&sc->flags, &sc->lock, 0, "cxgbdtch", 0); 1116 SET_BUSY(sc); 1117 ADAPTER_UNLOCK(sc); 1118 1119 if (p->port_cdev != NULL) 1120 destroy_dev(p->port_cdev); 1121 1122 cxgb_uninit_synchronized(p); 1123 ether_ifdetach(p->ifp); 1124 1125 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { 1126 struct sge_qset *qs = &sc->sge.qs[i]; 1127 struct sge_txq *txq = &qs->txq[TXQ_ETH]; 1128 1129 callout_drain(&txq->txq_watchdog); 1130 callout_drain(&txq->txq_timer); 1131 } 1132 1133 PORT_LOCK_DEINIT(p); 1134 if_free(p->ifp); 1135 p->ifp = NULL; 1136 1137 ADAPTER_LOCK(sc); 1138 CLR_BUSY(sc); 1139 wakeup_one(&sc->flags); 1140 ADAPTER_UNLOCK(sc); 1141 return (0); 1142} 1143 1144void 1145t3_fatal_err(struct adapter *sc) 1146{ 1147 u_int fw_status[4]; 1148 1149 if (sc->flags & FULL_INIT_DONE) { 1150 t3_sge_stop(sc); 1151 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1152 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1153 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1154 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1155 t3_intr_disable(sc); 1156 } 1157 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1158 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1159 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1160 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1161} 1162 1163int 1164t3_os_find_pci_capability(adapter_t *sc, int cap) 1165{ 1166 device_t dev; 1167 struct pci_devinfo *dinfo; 1168 pcicfgregs *cfg; 1169 uint32_t status; 1170 uint8_t ptr; 1171 1172 dev = sc->dev; 1173 dinfo = device_get_ivars(dev); 1174 cfg = &dinfo->cfg; 1175 1176 status = pci_read_config(dev, PCIR_STATUS, 2); 1177 if (!(status & PCIM_STATUS_CAPPRESENT)) 1178 return (0); 1179 1180 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1181 case 0: 1182 case 1: 1183 ptr = PCIR_CAP_PTR; 1184 break; 1185 case 2: 1186 ptr = PCIR_CAP_PTR_2; 1187 break; 1188 default: 1189 return (0); 1190 break; 1191 } 1192 ptr = pci_read_config(dev, ptr, 1); 1193 1194 while (ptr != 0) { 1195 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1196 return (ptr); 1197 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1198 } 1199 1200 return (0); 1201} 1202 1203int 1204t3_os_pci_save_state(struct adapter *sc) 1205{ 1206 device_t dev; 1207 struct pci_devinfo *dinfo; 1208 1209 dev = sc->dev; 1210 dinfo = device_get_ivars(dev); 1211 1212 pci_cfg_save(dev, dinfo, 0); 1213 return (0); 1214} 1215 1216int 1217t3_os_pci_restore_state(struct adapter *sc) 1218{ 1219 device_t dev; 1220 struct pci_devinfo *dinfo; 1221 1222 dev = sc->dev; 1223 dinfo = device_get_ivars(dev); 1224 1225 pci_cfg_restore(dev, dinfo); 1226 return (0); 1227} 1228 1229/** 1230 * t3_os_link_changed - handle link status changes 1231 * @sc: the adapter associated with the link change 1232 * @port_id: the port index whose link status has changed 1233 * @link_status: the new status of the link 1234 * @speed: the new speed setting 1235 * @duplex: the new duplex setting 1236 * @fc: the new flow-control setting 1237 * 1238 * This is the OS-dependent handler for link status changes. The OS 1239 * neutral handler takes care of most of the processing for these events, 1240 * then calls this handler for any OS-specific processing. 1241 */ 1242void 1243t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1244 int duplex, int fc, int mac_was_reset) 1245{ 1246 struct port_info *pi = &adapter->port[port_id]; 1247 struct ifnet *ifp = pi->ifp; 1248 1249 /* no race with detach, so ifp should always be good */ 1250 KASSERT(ifp, ("%s: if detached.", __func__)); 1251 1252 /* Reapply mac settings if they were lost due to a reset */ 1253 if (mac_was_reset) { 1254 PORT_LOCK(pi); 1255 cxgb_update_mac_settings(pi); 1256 PORT_UNLOCK(pi); 1257 } 1258 1259 if (link_status) { 1260 ifp->if_baudrate = IF_Mbps(speed); 1261 if_link_state_change(ifp, LINK_STATE_UP); 1262 } else 1263 if_link_state_change(ifp, LINK_STATE_DOWN); 1264} 1265 1266/** 1267 * t3_os_phymod_changed - handle PHY module changes 1268 * @phy: the PHY reporting the module change 1269 * @mod_type: new module type 1270 * 1271 * This is the OS-dependent handler for PHY module changes. It is 1272 * invoked when a PHY module is removed or inserted for any OS-specific 1273 * processing. 1274 */ 1275void t3_os_phymod_changed(struct adapter *adap, int port_id) 1276{ 1277 static const char *mod_str[] = { 1278 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown" 1279 }; 1280 struct port_info *pi = &adap->port[port_id]; 1281 int mod = pi->phy.modtype; 1282 1283 if (mod != pi->media.ifm_cur->ifm_data) 1284 cxgb_build_medialist(pi); 1285 1286 if (mod == phy_modtype_none) 1287 if_printf(pi->ifp, "PHY module unplugged\n"); 1288 else { 1289 KASSERT(mod < ARRAY_SIZE(mod_str), 1290 ("invalid PHY module type %d", mod)); 1291 if_printf(pi->ifp, "%s PHY module inserted\n", mod_str[mod]); 1292 } 1293} 1294 1295/* 1296 * Interrupt-context handler for external (PHY) interrupts. 1297 */ 1298void 1299t3_os_ext_intr_handler(adapter_t *sc) 1300{ 1301 if (cxgb_debug) 1302 printf("t3_os_ext_intr_handler\n"); 1303 /* 1304 * Schedule a task to handle external interrupts as they may be slow 1305 * and we use a mutex to protect MDIO registers. We disable PHY 1306 * interrupts in the meantime and let the task reenable them when 1307 * it's done. 1308 */ 1309 if (sc->slow_intr_mask) { 1310 ADAPTER_LOCK(sc); 1311 sc->slow_intr_mask &= ~F_T3DBG; 1312 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1313 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1314 ADAPTER_UNLOCK(sc); 1315 } 1316} 1317 1318void 1319t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1320{ 1321 1322 /* 1323 * The ifnet might not be allocated before this gets called, 1324 * as this is called early on in attach by t3_prep_adapter 1325 * save the address off in the port structure 1326 */ 1327 if (cxgb_debug) 1328 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1329 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1330} 1331 1332/* 1333 * Programs the XGMAC based on the settings in the ifnet. These settings 1334 * include MTU, MAC address, mcast addresses, etc. 1335 */ 1336static void 1337cxgb_update_mac_settings(struct port_info *p) 1338{ 1339 struct ifnet *ifp = p->ifp; 1340 struct t3_rx_mode rm; 1341 struct cmac *mac = &p->mac; 1342 int mtu, hwtagging; 1343 1344 PORT_LOCK_ASSERT_OWNED(p); 1345 1346 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN); 1347 1348 mtu = ifp->if_mtu; 1349 if (ifp->if_capenable & IFCAP_VLAN_MTU) 1350 mtu += ETHER_VLAN_ENCAP_LEN; 1351 1352 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0; 1353 1354 t3_mac_set_mtu(mac, mtu); 1355 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging); 1356 t3_mac_set_address(mac, 0, p->hw_addr); 1357 t3_init_rx_mode(&rm, p); 1358 t3_mac_set_rx_mode(mac, &rm); 1359} 1360 1361 1362static int 1363await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1364 unsigned long n) 1365{ 1366 int attempts = 5; 1367 1368 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1369 if (!--attempts) 1370 return (ETIMEDOUT); 1371 t3_os_sleep(10); 1372 } 1373 return 0; 1374} 1375 1376static int 1377init_tp_parity(struct adapter *adap) 1378{ 1379 int i; 1380 struct mbuf *m; 1381 struct cpl_set_tcb_field *greq; 1382 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1383 1384 t3_tp_set_offload_mode(adap, 1); 1385 1386 for (i = 0; i < 16; i++) { 1387 struct cpl_smt_write_req *req; 1388 1389 m = m_gethdr(M_WAITOK, MT_DATA); 1390 req = mtod(m, struct cpl_smt_write_req *); 1391 m->m_len = m->m_pkthdr.len = sizeof(*req); 1392 memset(req, 0, sizeof(*req)); 1393 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1394 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1395 req->iff = i; 1396 t3_mgmt_tx(adap, m); 1397 } 1398 1399 for (i = 0; i < 2048; i++) { 1400 struct cpl_l2t_write_req *req; 1401 1402 m = m_gethdr(M_WAITOK, MT_DATA); 1403 req = mtod(m, struct cpl_l2t_write_req *); 1404 m->m_len = m->m_pkthdr.len = sizeof(*req); 1405 memset(req, 0, sizeof(*req)); 1406 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1407 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1408 req->params = htonl(V_L2T_W_IDX(i)); 1409 t3_mgmt_tx(adap, m); 1410 } 1411 1412 for (i = 0; i < 2048; i++) { 1413 struct cpl_rte_write_req *req; 1414 1415 m = m_gethdr(M_WAITOK, MT_DATA); 1416 req = mtod(m, struct cpl_rte_write_req *); 1417 m->m_len = m->m_pkthdr.len = sizeof(*req); 1418 memset(req, 0, sizeof(*req)); 1419 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1420 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1421 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1422 t3_mgmt_tx(adap, m); 1423 } 1424 1425 m = m_gethdr(M_WAITOK, MT_DATA); 1426 greq = mtod(m, struct cpl_set_tcb_field *); 1427 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1428 memset(greq, 0, sizeof(*greq)); 1429 greq->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1430 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1431 greq->mask = htobe64(1); 1432 t3_mgmt_tx(adap, m); 1433 1434 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1435 t3_tp_set_offload_mode(adap, 0); 1436 return (i); 1437} 1438 1439/** 1440 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1441 * @adap: the adapter 1442 * 1443 * Sets up RSS to distribute packets to multiple receive queues. We 1444 * configure the RSS CPU lookup table to distribute to the number of HW 1445 * receive queues, and the response queue lookup table to narrow that 1446 * down to the response queues actually configured for each port. 1447 * We always configure the RSS mapping for two ports since the mapping 1448 * table has plenty of entries. 1449 */ 1450static void 1451setup_rss(adapter_t *adap) 1452{ 1453 int i; 1454 u_int nq[2]; 1455 uint8_t cpus[SGE_QSETS + 1]; 1456 uint16_t rspq_map[RSS_TABLE_SIZE]; 1457 1458 for (i = 0; i < SGE_QSETS; ++i) 1459 cpus[i] = i; 1460 cpus[SGE_QSETS] = 0xff; 1461 1462 nq[0] = nq[1] = 0; 1463 for_each_port(adap, i) { 1464 const struct port_info *pi = adap2pinfo(adap, i); 1465 1466 nq[pi->tx_chan] += pi->nqsets; 1467 } 1468 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1469 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1470 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1471 } 1472 1473 /* Calculate the reverse RSS map table */ 1474 for (i = 0; i < SGE_QSETS; ++i) 1475 adap->rrss_map[i] = 0xff; 1476 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1477 if (adap->rrss_map[rspq_map[i]] == 0xff) 1478 adap->rrss_map[rspq_map[i]] = i; 1479 1480 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1481 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1482 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1483 cpus, rspq_map); 1484 1485} 1486 1487/* 1488 * Sends an mbuf to an offload queue driver 1489 * after dealing with any active network taps. 1490 */ 1491static inline int 1492offload_tx(struct t3cdev *tdev, struct mbuf *m) 1493{ 1494 int ret; 1495 1496 ret = t3_offload_tx(tdev, m); 1497 return (ret); 1498} 1499 1500static int 1501write_smt_entry(struct adapter *adapter, int idx) 1502{ 1503 struct port_info *pi = &adapter->port[idx]; 1504 struct cpl_smt_write_req *req; 1505 struct mbuf *m; 1506 1507 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1508 return (ENOMEM); 1509 1510 req = mtod(m, struct cpl_smt_write_req *); 1511 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1512 1513 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1514 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1515 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1516 req->iff = idx; 1517 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1518 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1519 1520 m_set_priority(m, 1); 1521 1522 offload_tx(&adapter->tdev, m); 1523 1524 return (0); 1525} 1526 1527static int 1528init_smt(struct adapter *adapter) 1529{ 1530 int i; 1531 1532 for_each_port(adapter, i) 1533 write_smt_entry(adapter, i); 1534 return 0; 1535} 1536 1537static void 1538init_port_mtus(adapter_t *adapter) 1539{ 1540 unsigned int mtus = ETHERMTU | (ETHERMTU << 16); 1541 1542 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1543} 1544 1545static void 1546send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1547 int hi, int port) 1548{ 1549 struct mbuf *m; 1550 struct mngt_pktsched_wr *req; 1551 1552 m = m_gethdr(M_DONTWAIT, MT_DATA); 1553 if (m) { 1554 req = mtod(m, struct mngt_pktsched_wr *); 1555 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1556 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1557 req->sched = sched; 1558 req->idx = qidx; 1559 req->min = lo; 1560 req->max = hi; 1561 req->binding = port; 1562 m->m_len = m->m_pkthdr.len = sizeof(*req); 1563 t3_mgmt_tx(adap, m); 1564 } 1565} 1566 1567static void 1568bind_qsets(adapter_t *sc) 1569{ 1570 int i, j; 1571 1572 for (i = 0; i < (sc)->params.nports; ++i) { 1573 const struct port_info *pi = adap2pinfo(sc, i); 1574 1575 for (j = 0; j < pi->nqsets; ++j) { 1576 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1577 -1, pi->tx_chan); 1578 1579 } 1580 } 1581} 1582 1583static void 1584update_tpeeprom(struct adapter *adap) 1585{ 1586#ifdef FIRMWARE_LATEST 1587 const struct firmware *tpeeprom; 1588#else 1589 struct firmware *tpeeprom; 1590#endif 1591 1592 uint32_t version; 1593 unsigned int major, minor; 1594 int ret, len; 1595 char rev, name[32]; 1596 1597 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1598 1599 major = G_TP_VERSION_MAJOR(version); 1600 minor = G_TP_VERSION_MINOR(version); 1601 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1602 return; 1603 1604 rev = t3rev2char(adap); 1605 snprintf(name, sizeof(name), TPEEPROM_NAME, rev); 1606 1607 tpeeprom = firmware_get(name); 1608 if (tpeeprom == NULL) { 1609 device_printf(adap->dev, 1610 "could not load TP EEPROM: unable to load %s\n", 1611 name); 1612 return; 1613 } 1614 1615 len = tpeeprom->datasize - 4; 1616 1617 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1618 if (ret) 1619 goto release_tpeeprom; 1620 1621 if (len != TP_SRAM_LEN) { 1622 device_printf(adap->dev, 1623 "%s length is wrong len=%d expected=%d\n", name, 1624 len, TP_SRAM_LEN); 1625 return; 1626 } 1627 1628 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1629 TP_SRAM_OFFSET); 1630 1631 if (!ret) { 1632 device_printf(adap->dev, 1633 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1634 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1635 } else 1636 device_printf(adap->dev, 1637 "Protocol SRAM image update in EEPROM failed\n"); 1638 1639release_tpeeprom: 1640 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1641 1642 return; 1643} 1644 1645static int 1646update_tpsram(struct adapter *adap) 1647{ 1648#ifdef FIRMWARE_LATEST 1649 const struct firmware *tpsram; 1650#else 1651 struct firmware *tpsram; 1652#endif 1653 int ret; 1654 char rev, name[32]; 1655 1656 rev = t3rev2char(adap); 1657 snprintf(name, sizeof(name), TPSRAM_NAME, rev); 1658 1659 update_tpeeprom(adap); 1660 1661 tpsram = firmware_get(name); 1662 if (tpsram == NULL){ 1663 device_printf(adap->dev, "could not load TP SRAM\n"); 1664 return (EINVAL); 1665 } else 1666 device_printf(adap->dev, "updating TP SRAM\n"); 1667 1668 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1669 if (ret) 1670 goto release_tpsram; 1671 1672 ret = t3_set_proto_sram(adap, tpsram->data); 1673 if (ret) 1674 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1675 1676release_tpsram: 1677 firmware_put(tpsram, FIRMWARE_UNLOAD); 1678 1679 return ret; 1680} 1681 1682/** 1683 * cxgb_up - enable the adapter 1684 * @adap: adapter being enabled 1685 * 1686 * Called when the first port is enabled, this function performs the 1687 * actions necessary to make an adapter operational, such as completing 1688 * the initialization of HW modules, and enabling interrupts. 1689 */ 1690static int 1691cxgb_up(struct adapter *sc) 1692{ 1693 int err = 0; 1694 1695 KASSERT(sc->open_device_map == 0, ("%s: device(s) already open (%x)", 1696 __func__, sc->open_device_map)); 1697 1698 if ((sc->flags & FULL_INIT_DONE) == 0) { 1699 1700 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1701 1702 if ((sc->flags & FW_UPTODATE) == 0) 1703 if ((err = upgrade_fw(sc))) 1704 goto out; 1705 1706 if ((sc->flags & TPS_UPTODATE) == 0) 1707 if ((err = update_tpsram(sc))) 1708 goto out; 1709 1710 err = t3_init_hw(sc, 0); 1711 if (err) 1712 goto out; 1713 1714 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1715 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1716 1717 err = setup_sge_qsets(sc); 1718 if (err) 1719 goto out; 1720 1721 setup_rss(sc); 1722 1723 t3_intr_clear(sc); 1724 err = cxgb_setup_interrupts(sc); 1725 if (err) 1726 goto out; 1727 1728 t3_add_configured_sysctls(sc); 1729 sc->flags |= FULL_INIT_DONE; 1730 } 1731 1732 t3_intr_clear(sc); 1733 t3_sge_start(sc); 1734 t3_intr_enable(sc); 1735 1736 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1737 is_offload(sc) && init_tp_parity(sc) == 0) 1738 sc->flags |= TP_PARITY_INIT; 1739 1740 if (sc->flags & TP_PARITY_INIT) { 1741 t3_write_reg(sc, A_TP_INT_CAUSE, F_CMCACHEPERR | F_ARPLUTPERR); 1742 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1743 } 1744 1745 if (!(sc->flags & QUEUES_BOUND)) { 1746 bind_qsets(sc); 1747 sc->flags |= QUEUES_BOUND; 1748 } 1749 1750 t3_sge_reset_adapter(sc); 1751out: 1752 return (err); 1753} 1754 1755/* 1756 * Called when the last open device is closed. Does NOT undo all of cxgb_up's 1757 * work. Specifically, the resources grabbed under FULL_INIT_DONE are released 1758 * during controller_detach, not here. 1759 */ 1760static void 1761cxgb_down(struct adapter *sc) 1762{ 1763 t3_sge_stop(sc); 1764 t3_intr_disable(sc); 1765} 1766 1767static int 1768offload_open(struct port_info *pi) 1769{ 1770 struct adapter *sc = pi->adapter; 1771 struct t3cdev *tdev = &sc->tdev; 1772 1773 setbit(&sc->open_device_map, OFFLOAD_DEVMAP_BIT); 1774 1775 t3_tp_set_offload_mode(sc, 1); 1776 tdev->lldev = pi->ifp; 1777 init_port_mtus(sc); 1778 t3_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd, 1779 sc->params.rev == 0 ? sc->port[0].ifp->if_mtu : 0xffff); 1780 init_smt(sc); 1781 cxgb_add_clients(tdev); 1782 1783 return (0); 1784} 1785 1786static int 1787offload_close(struct t3cdev *tdev) 1788{ 1789 struct adapter *adapter = tdev2adap(tdev); 1790 1791 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1792 return (0); 1793 1794 /* Call back all registered clients */ 1795 cxgb_remove_clients(tdev); 1796 1797 tdev->lldev = NULL; 1798 cxgb_set_dummy_ops(tdev); 1799 t3_tp_set_offload_mode(adapter, 0); 1800 1801 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1802 1803 return (0); 1804} 1805 1806/* 1807 * if_init for cxgb ports. 1808 */ 1809static void 1810cxgb_init(void *arg) 1811{ 1812 struct port_info *p = arg; 1813 struct adapter *sc = p->adapter; 1814 1815 ADAPTER_LOCK(sc); 1816 cxgb_init_locked(p); /* releases adapter lock */ 1817 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1818} 1819 1820static int 1821cxgb_init_locked(struct port_info *p) 1822{ 1823 struct adapter *sc = p->adapter; 1824 struct ifnet *ifp = p->ifp; 1825 struct cmac *mac = &p->mac; 1826 int i, rc = 0, may_sleep = 0; 1827 1828 ADAPTER_LOCK_ASSERT_OWNED(sc); 1829 1830 while (!IS_DOOMED(p) && IS_BUSY(sc)) { 1831 if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, "cxgbinit", 0)) { 1832 rc = EINTR; 1833 goto done; 1834 } 1835 } 1836 if (IS_DOOMED(p)) { 1837 rc = ENXIO; 1838 goto done; 1839 } 1840 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 1841 1842 /* 1843 * The code that runs during one-time adapter initialization can sleep 1844 * so it's important not to hold any locks across it. 1845 */ 1846 may_sleep = sc->flags & FULL_INIT_DONE ? 0 : 1; 1847 1848 if (may_sleep) { 1849 SET_BUSY(sc); 1850 ADAPTER_UNLOCK(sc); 1851 } 1852 1853 if (sc->open_device_map == 0) { 1854 if ((rc = cxgb_up(sc)) != 0) 1855 goto done; 1856 1857 if (is_offload(sc) && !ofld_disable && offload_open(p)) 1858 log(LOG_WARNING, 1859 "Could not initialize offload capabilities\n"); 1860 } 1861 1862 PORT_LOCK(p); 1863 if (isset(&sc->open_device_map, p->port_id) && 1864 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1865 PORT_UNLOCK(p); 1866 goto done; 1867 } 1868 t3_port_intr_enable(sc, p->port_id); 1869 if (!mac->multiport) 1870 t3_mac_init(mac); 1871 cxgb_update_mac_settings(p); 1872 t3_link_start(&p->phy, mac, &p->link_config); 1873 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1874 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1875 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1876 PORT_UNLOCK(p); 1877 1878 t3_link_changed(sc, p->port_id); 1879 1880 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { 1881 struct sge_qset *qs = &sc->sge.qs[i]; 1882 struct sge_txq *txq = &qs->txq[TXQ_ETH]; 1883 1884 callout_reset_on(&txq->txq_watchdog, hz, cxgb_tx_watchdog, qs, 1885 txq->txq_watchdog.c_cpu); 1886 } 1887 1888 /* all ok */ 1889 setbit(&sc->open_device_map, p->port_id); 1890 1891done: 1892 if (may_sleep) { 1893 ADAPTER_LOCK(sc); 1894 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 1895 CLR_BUSY(sc); 1896 wakeup_one(&sc->flags); 1897 } 1898 ADAPTER_UNLOCK(sc); 1899 return (rc); 1900} 1901 1902static int 1903cxgb_uninit_locked(struct port_info *p) 1904{ 1905 struct adapter *sc = p->adapter; 1906 int rc; 1907 1908 ADAPTER_LOCK_ASSERT_OWNED(sc); 1909 1910 while (!IS_DOOMED(p) && IS_BUSY(sc)) { 1911 if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, "cxgbunin", 0)) { 1912 rc = EINTR; 1913 goto done; 1914 } 1915 } 1916 if (IS_DOOMED(p)) { 1917 rc = ENXIO; 1918 goto done; 1919 } 1920 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 1921 SET_BUSY(sc); 1922 ADAPTER_UNLOCK(sc); 1923 1924 rc = cxgb_uninit_synchronized(p); 1925 1926 ADAPTER_LOCK(sc); 1927 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 1928 CLR_BUSY(sc); 1929 wakeup_one(&sc->flags); 1930done: 1931 ADAPTER_UNLOCK(sc); 1932 return (rc); 1933} 1934 1935/* 1936 * Called on "ifconfig down", and from port_detach 1937 */ 1938static int 1939cxgb_uninit_synchronized(struct port_info *pi) 1940{ 1941 struct adapter *sc = pi->adapter; 1942 struct ifnet *ifp = pi->ifp; 1943 1944 /* 1945 * taskqueue_drain may cause a deadlock if the adapter lock is held. 1946 */ 1947 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1948 1949 /* 1950 * Clear this port's bit from the open device map, and then drain all 1951 * the tasks that can access/manipulate this port's port_info or ifp. 1952 * We disable this port's interrupts here and so the the slow/ext 1953 * interrupt tasks won't be enqueued. The tick task will continue to 1954 * be enqueued every second but the runs after this drain will not see 1955 * this port in the open device map. 1956 * 1957 * A well behaved task must take open_device_map into account and ignore 1958 * ports that are not open. 1959 */ 1960 clrbit(&sc->open_device_map, pi->port_id); 1961 t3_port_intr_disable(sc, pi->port_id); 1962 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1963 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1964 taskqueue_drain(sc->tq, &sc->tick_task); 1965 1966 PORT_LOCK(pi); 1967 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1968 1969 /* disable pause frames */ 1970 t3_set_reg_field(sc, A_XGM_TX_CFG + pi->mac.offset, F_TXPAUSEEN, 0); 1971 1972 /* Reset RX FIFO HWM */ 1973 t3_set_reg_field(sc, A_XGM_RXFIFO_CFG + pi->mac.offset, 1974 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); 1975 1976 DELAY(100 * 1000); 1977 1978 /* Wait for TXFIFO empty */ 1979 t3_wait_op_done(sc, A_XGM_TXFIFO_CFG + pi->mac.offset, 1980 F_TXFIFO_EMPTY, 1, 20, 5); 1981 1982 DELAY(100 * 1000); 1983 t3_mac_disable(&pi->mac, MAC_DIRECTION_RX); 1984 1985 1986 pi->phy.ops->power_down(&pi->phy, 1); 1987 1988 PORT_UNLOCK(pi); 1989 1990 pi->link_config.link_ok = 0; 1991 t3_os_link_changed(sc, pi->port_id, 0, 0, 0, 0, 0); 1992 1993 if ((sc->open_device_map & PORT_MASK) == 0) 1994 offload_close(&sc->tdev); 1995 1996 if (sc->open_device_map == 0) 1997 cxgb_down(pi->adapter); 1998 1999 return (0); 2000} 2001 2002#ifdef LRO_SUPPORTED 2003/* 2004 * Mark lro enabled or disabled in all qsets for this port 2005 */ 2006static int 2007cxgb_set_lro(struct port_info *p, int enabled) 2008{ 2009 int i; 2010 struct adapter *adp = p->adapter; 2011 struct sge_qset *q; 2012 2013 PORT_LOCK_ASSERT_OWNED(p); 2014 for (i = 0; i < p->nqsets; i++) { 2015 q = &adp->sge.qs[p->first_qset + i]; 2016 q->lro.enabled = (enabled != 0); 2017 } 2018 return (0); 2019} 2020#endif 2021 2022static int 2023cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 2024{ 2025 struct port_info *p = ifp->if_softc; 2026 struct adapter *sc = p->adapter; 2027 struct ifreq *ifr = (struct ifreq *)data; 2028 int flags, error = 0, mtu; 2029 uint32_t mask; 2030 2031 switch (command) { 2032 case SIOCSIFMTU: 2033 ADAPTER_LOCK(sc); 2034 error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2035 if (error) { 2036fail: 2037 ADAPTER_UNLOCK(sc); 2038 return (error); 2039 } 2040 2041 mtu = ifr->ifr_mtu; 2042 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) { 2043 error = EINVAL; 2044 } else { 2045 ifp->if_mtu = mtu; 2046 PORT_LOCK(p); 2047 cxgb_update_mac_settings(p); 2048 PORT_UNLOCK(p); 2049 } 2050 ADAPTER_UNLOCK(sc); 2051 break; 2052 case SIOCSIFFLAGS: 2053 ADAPTER_LOCK(sc); 2054 if (IS_DOOMED(p)) { 2055 error = ENXIO; 2056 goto fail; 2057 } 2058 if (ifp->if_flags & IFF_UP) { 2059 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2060 flags = p->if_flags; 2061 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 2062 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) { 2063 if (IS_BUSY(sc)) { 2064 error = EBUSY; 2065 goto fail; 2066 } 2067 PORT_LOCK(p); 2068 cxgb_update_mac_settings(p); 2069 PORT_UNLOCK(p); 2070 } 2071 ADAPTER_UNLOCK(sc); 2072 } else 2073 error = cxgb_init_locked(p); 2074 p->if_flags = ifp->if_flags; 2075 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2076 error = cxgb_uninit_locked(p); 2077 2078 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2079 break; 2080 case SIOCADDMULTI: 2081 case SIOCDELMULTI: 2082 ADAPTER_LOCK(sc); 2083 error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2084 if (error) 2085 goto fail; 2086 2087 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2088 PORT_LOCK(p); 2089 cxgb_update_mac_settings(p); 2090 PORT_UNLOCK(p); 2091 } 2092 ADAPTER_UNLOCK(sc); 2093 2094 break; 2095 case SIOCSIFCAP: 2096 ADAPTER_LOCK(sc); 2097 error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2098 if (error) 2099 goto fail; 2100 2101 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2102 if (mask & IFCAP_TXCSUM) { 2103 if (IFCAP_TXCSUM & ifp->if_capenable) { 2104 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 2105 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 2106 | CSUM_IP | CSUM_TSO); 2107 } else { 2108 ifp->if_capenable |= IFCAP_TXCSUM; 2109 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP 2110 | CSUM_IP); 2111 } 2112 } 2113 if (mask & IFCAP_RXCSUM) { 2114 ifp->if_capenable ^= IFCAP_RXCSUM; 2115 } 2116 if (mask & IFCAP_TSO4) { 2117 if (IFCAP_TSO4 & ifp->if_capenable) { 2118 ifp->if_capenable &= ~IFCAP_TSO4; 2119 ifp->if_hwassist &= ~CSUM_TSO; 2120 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 2121 ifp->if_capenable |= IFCAP_TSO4; 2122 ifp->if_hwassist |= CSUM_TSO; 2123 } else 2124 error = EINVAL; 2125 } 2126#ifdef LRO_SUPPORTED 2127 if (mask & IFCAP_LRO) { 2128 ifp->if_capenable ^= IFCAP_LRO; 2129 2130 /* Safe to do this even if cxgb_up not called yet */ 2131 cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO); 2132 } 2133#endif 2134 if (mask & IFCAP_VLAN_HWTAGGING) { 2135 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2136 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2137 PORT_LOCK(p); 2138 cxgb_update_mac_settings(p); 2139 PORT_UNLOCK(p); 2140 } 2141 } 2142 if (mask & IFCAP_VLAN_MTU) { 2143 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2144 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2145 PORT_LOCK(p); 2146 cxgb_update_mac_settings(p); 2147 PORT_UNLOCK(p); 2148 } 2149 } 2150 if (mask & IFCAP_VLAN_HWCSUM) 2151 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2152 2153#ifdef VLAN_CAPABILITIES 2154 VLAN_CAPABILITIES(ifp); 2155#endif 2156 ADAPTER_UNLOCK(sc); 2157 break; 2158 case SIOCSIFMEDIA: 2159 case SIOCGIFMEDIA: 2160 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 2161 break; 2162 default: 2163 error = ether_ioctl(ifp, command, data); 2164 } 2165 2166 return (error); 2167} 2168 2169static int 2170cxgb_media_change(struct ifnet *ifp) 2171{ 2172 return (EOPNOTSUPP); 2173} 2174 2175/* 2176 * Translates phy->modtype to the correct Ethernet media subtype. 2177 */ 2178static int 2179cxgb_ifm_type(int mod) 2180{ 2181 switch (mod) { 2182 case phy_modtype_sr: 2183 return (IFM_10G_SR); 2184 case phy_modtype_lr: 2185 return (IFM_10G_LR); 2186 case phy_modtype_lrm: 2187 return (IFM_10G_LRM); 2188 case phy_modtype_twinax: 2189 return (IFM_10G_TWINAX); 2190 case phy_modtype_twinax_long: 2191 return (IFM_10G_TWINAX_LONG); 2192 case phy_modtype_none: 2193 return (IFM_NONE); 2194 case phy_modtype_unknown: 2195 return (IFM_UNKNOWN); 2196 } 2197 2198 KASSERT(0, ("%s: modtype %d unknown", __func__, mod)); 2199 return (IFM_UNKNOWN); 2200} 2201 2202/* 2203 * Rebuilds the ifmedia list for this port, and sets the current media. 2204 */ 2205static void 2206cxgb_build_medialist(struct port_info *p) 2207{ 2208 struct cphy *phy = &p->phy; 2209 struct ifmedia *media = &p->media; 2210 int mod = phy->modtype; 2211 int m = IFM_ETHER | IFM_FDX; 2212 2213 PORT_LOCK(p); 2214 2215 ifmedia_removeall(media); 2216 if (phy->caps & SUPPORTED_TP && phy->caps & SUPPORTED_Autoneg) { 2217 /* Copper (RJ45) */ 2218 2219 if (phy->caps & SUPPORTED_10000baseT_Full) 2220 ifmedia_add(media, m | IFM_10G_T, mod, NULL); 2221 2222 if (phy->caps & SUPPORTED_1000baseT_Full) 2223 ifmedia_add(media, m | IFM_1000_T, mod, NULL); 2224 2225 if (phy->caps & SUPPORTED_100baseT_Full) 2226 ifmedia_add(media, m | IFM_100_TX, mod, NULL); 2227 2228 if (phy->caps & SUPPORTED_10baseT_Full) 2229 ifmedia_add(media, m | IFM_10_T, mod, NULL); 2230 2231 ifmedia_add(media, IFM_ETHER | IFM_AUTO, mod, NULL); 2232 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 2233 2234 } else if (phy->caps & SUPPORTED_TP) { 2235 /* Copper (CX4) */ 2236 2237 KASSERT(phy->caps & SUPPORTED_10000baseT_Full, 2238 ("%s: unexpected cap 0x%x", __func__, phy->caps)); 2239 2240 ifmedia_add(media, m | IFM_10G_CX4, mod, NULL); 2241 ifmedia_set(media, m | IFM_10G_CX4); 2242 2243 } else if (phy->caps & SUPPORTED_FIBRE && 2244 phy->caps & SUPPORTED_10000baseT_Full) { 2245 /* 10G optical (but includes SFP+ twinax) */ 2246 2247 m |= cxgb_ifm_type(mod); 2248 if (IFM_SUBTYPE(m) == IFM_NONE) 2249 m &= ~IFM_FDX; 2250 2251 ifmedia_add(media, m, mod, NULL); 2252 ifmedia_set(media, m); 2253 2254 } else if (phy->caps & SUPPORTED_FIBRE && 2255 phy->caps & SUPPORTED_1000baseT_Full) { 2256 /* 1G optical */ 2257 2258 /* XXX: Lie and claim to be SX, could actually be any 1G-X */ 2259 ifmedia_add(media, m | IFM_1000_SX, mod, NULL); 2260 ifmedia_set(media, m | IFM_1000_SX); 2261 2262 } else { 2263 KASSERT(0, ("%s: don't know how to handle 0x%x.", __func__, 2264 phy->caps)); 2265 } 2266 2267 PORT_UNLOCK(p); 2268} 2269 2270static void 2271cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2272{ 2273 struct port_info *p = ifp->if_softc; 2274 struct ifmedia_entry *cur = p->media.ifm_cur; 2275 int speed = p->link_config.speed; 2276 2277 if (cur->ifm_data != p->phy.modtype) { 2278 cxgb_build_medialist(p); 2279 cur = p->media.ifm_cur; 2280 } 2281 2282 ifmr->ifm_status = IFM_AVALID; 2283 if (!p->link_config.link_ok) 2284 return; 2285 2286 ifmr->ifm_status |= IFM_ACTIVE; 2287 2288 /* 2289 * active and current will differ iff current media is autoselect. That 2290 * can happen only for copper RJ45. 2291 */ 2292 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2293 return; 2294 KASSERT(p->phy.caps & SUPPORTED_TP && p->phy.caps & SUPPORTED_Autoneg, 2295 ("%s: unexpected PHY caps 0x%x", __func__, p->phy.caps)); 2296 2297 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2298 if (speed == SPEED_10000) 2299 ifmr->ifm_active |= IFM_10G_T; 2300 else if (speed == SPEED_1000) 2301 ifmr->ifm_active |= IFM_1000_T; 2302 else if (speed == SPEED_100) 2303 ifmr->ifm_active |= IFM_100_TX; 2304 else if (speed == SPEED_10) 2305 ifmr->ifm_active |= IFM_10_T; 2306 else 2307 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 2308 speed)); 2309} 2310 2311static void 2312cxgb_async_intr(void *data) 2313{ 2314 adapter_t *sc = data; 2315 2316 if (cxgb_debug) 2317 device_printf(sc->dev, "cxgb_async_intr\n"); 2318 /* 2319 * May need to sleep - defer to taskqueue 2320 */ 2321 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2322} 2323 2324static void 2325cxgb_ext_intr_handler(void *arg, int count) 2326{ 2327 adapter_t *sc = (adapter_t *)arg; 2328 2329 if (cxgb_debug) 2330 printf("cxgb_ext_intr_handler\n"); 2331 2332 t3_phy_intr_handler(sc); 2333 2334 /* Now reenable external interrupts */ 2335 ADAPTER_LOCK(sc); 2336 if (sc->slow_intr_mask) { 2337 sc->slow_intr_mask |= F_T3DBG; 2338 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2339 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2340 } 2341 ADAPTER_UNLOCK(sc); 2342} 2343 2344static inline int 2345link_poll_needed(struct port_info *p) 2346{ 2347 struct cphy *phy = &p->phy; 2348 2349 if (phy->caps & POLL_LINK_1ST_TIME) { 2350 p->phy.caps &= ~POLL_LINK_1ST_TIME; 2351 return (1); 2352 } 2353 2354 return (p->link_fault || !(phy->caps & SUPPORTED_LINK_IRQ)); 2355} 2356 2357static void 2358check_link_status(adapter_t *sc) 2359{ 2360 int i; 2361 2362 for (i = 0; i < (sc)->params.nports; ++i) { 2363 struct port_info *p = &sc->port[i]; 2364 2365 if (!isset(&sc->open_device_map, p->port_id)) 2366 continue; 2367 2368 if (link_poll_needed(p)) 2369 t3_link_changed(sc, i); 2370 } 2371} 2372 2373static void 2374check_t3b2_mac(struct adapter *sc) 2375{ 2376 int i; 2377 2378 if (sc->flags & CXGB_SHUTDOWN) 2379 return; 2380 2381 for_each_port(sc, i) { 2382 struct port_info *p = &sc->port[i]; 2383 int status; 2384#ifdef INVARIANTS 2385 struct ifnet *ifp = p->ifp; 2386#endif 2387 2388 if (!isset(&sc->open_device_map, p->port_id) || p->link_fault || 2389 !p->link_config.link_ok) 2390 continue; 2391 2392 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, 2393 ("%s: state mismatch (drv_flags %x, device_map %x)", 2394 __func__, ifp->if_drv_flags, sc->open_device_map)); 2395 2396 PORT_LOCK(p); 2397 status = t3b2_mac_watchdog_task(&p->mac); 2398 if (status == 1) 2399 p->mac.stats.num_toggled++; 2400 else if (status == 2) { 2401 struct cmac *mac = &p->mac; 2402 2403 cxgb_update_mac_settings(p); 2404 t3_link_start(&p->phy, mac, &p->link_config); 2405 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2406 t3_port_intr_enable(sc, p->port_id); 2407 p->mac.stats.num_resets++; 2408 } 2409 PORT_UNLOCK(p); 2410 } 2411} 2412 2413static void 2414cxgb_tick(void *arg) 2415{ 2416 adapter_t *sc = (adapter_t *)arg; 2417 2418 if (sc->flags & CXGB_SHUTDOWN) 2419 return; 2420 2421 taskqueue_enqueue(sc->tq, &sc->tick_task); 2422 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 2423} 2424 2425static void 2426cxgb_tick_handler(void *arg, int count) 2427{ 2428 adapter_t *sc = (adapter_t *)arg; 2429 const struct adapter_params *p = &sc->params; 2430 int i; 2431 uint32_t cause, reset; 2432 2433 if (sc->flags & CXGB_SHUTDOWN || !(sc->flags & FULL_INIT_DONE)) 2434 return; 2435 2436 check_link_status(sc); 2437 2438 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2439 check_t3b2_mac(sc); 2440 2441 cause = t3_read_reg(sc, A_SG_INT_CAUSE); 2442 reset = 0; 2443 if (cause & F_FLEMPTY) { 2444 struct sge_qset *qs = &sc->sge.qs[0]; 2445 2446 i = 0; 2447 reset |= F_FLEMPTY; 2448 2449 cause = (t3_read_reg(sc, A_SG_RSPQ_FL_STATUS) >> 2450 S_FL0EMPTY) & 0xffff; 2451 while (cause) { 2452 qs->fl[i].empty += (cause & 1); 2453 if (i) 2454 qs++; 2455 i ^= 1; 2456 cause >>= 1; 2457 } 2458 } 2459 t3_write_reg(sc, A_SG_INT_CAUSE, reset); 2460 2461 for (i = 0; i < sc->params.nports; i++) { 2462 struct port_info *pi = &sc->port[i]; 2463 struct ifnet *ifp = pi->ifp; 2464 struct cmac *mac = &pi->mac; 2465 struct mac_stats *mstats = &mac->stats; 2466 2467 if (!isset(&sc->open_device_map, pi->port_id)) 2468 continue; 2469 2470 PORT_LOCK(pi); 2471 t3_mac_update_stats(mac); 2472 PORT_UNLOCK(pi); 2473 2474 ifp->if_opackets = 2475 mstats->tx_frames_64 + 2476 mstats->tx_frames_65_127 + 2477 mstats->tx_frames_128_255 + 2478 mstats->tx_frames_256_511 + 2479 mstats->tx_frames_512_1023 + 2480 mstats->tx_frames_1024_1518 + 2481 mstats->tx_frames_1519_max; 2482 2483 ifp->if_ipackets = 2484 mstats->rx_frames_64 + 2485 mstats->rx_frames_65_127 + 2486 mstats->rx_frames_128_255 + 2487 mstats->rx_frames_256_511 + 2488 mstats->rx_frames_512_1023 + 2489 mstats->rx_frames_1024_1518 + 2490 mstats->rx_frames_1519_max; 2491 2492 ifp->if_obytes = mstats->tx_octets; 2493 ifp->if_ibytes = mstats->rx_octets; 2494 ifp->if_omcasts = mstats->tx_mcast_frames; 2495 ifp->if_imcasts = mstats->rx_mcast_frames; 2496 2497 ifp->if_collisions = 2498 mstats->tx_total_collisions; 2499 2500 ifp->if_iqdrops = mstats->rx_cong_drops; 2501 2502 ifp->if_oerrors = 2503 mstats->tx_excess_collisions + 2504 mstats->tx_underrun + 2505 mstats->tx_len_errs + 2506 mstats->tx_mac_internal_errs + 2507 mstats->tx_excess_deferral + 2508 mstats->tx_fcs_errs; 2509 ifp->if_ierrors = 2510 mstats->rx_jabber + 2511 mstats->rx_data_errs + 2512 mstats->rx_sequence_errs + 2513 mstats->rx_runt + 2514 mstats->rx_too_long + 2515 mstats->rx_mac_internal_errs + 2516 mstats->rx_short + 2517 mstats->rx_fcs_errs; 2518 2519 if (mac->multiport) 2520 continue; 2521 2522 /* Count rx fifo overflows, once per second */ 2523 cause = t3_read_reg(sc, A_XGM_INT_CAUSE + mac->offset); 2524 reset = 0; 2525 if (cause & F_RXFIFO_OVERFLOW) { 2526 mac->stats.rx_fifo_ovfl++; 2527 reset |= F_RXFIFO_OVERFLOW; 2528 } 2529 t3_write_reg(sc, A_XGM_INT_CAUSE + mac->offset, reset); 2530 } 2531} 2532 2533static void 2534touch_bars(device_t dev) 2535{ 2536 /* 2537 * Don't enable yet 2538 */ 2539#if !defined(__LP64__) && 0 2540 u32 v; 2541 2542 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2543 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2544 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2545 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2546 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2547 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2548#endif 2549} 2550 2551static int 2552set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2553{ 2554 uint8_t *buf; 2555 int err = 0; 2556 u32 aligned_offset, aligned_len, *p; 2557 struct adapter *adapter = pi->adapter; 2558 2559 2560 aligned_offset = offset & ~3; 2561 aligned_len = (len + (offset & 3) + 3) & ~3; 2562 2563 if (aligned_offset != offset || aligned_len != len) { 2564 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2565 if (!buf) 2566 return (ENOMEM); 2567 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2568 if (!err && aligned_len > 4) 2569 err = t3_seeprom_read(adapter, 2570 aligned_offset + aligned_len - 4, 2571 (u32 *)&buf[aligned_len - 4]); 2572 if (err) 2573 goto out; 2574 memcpy(buf + (offset & 3), data, len); 2575 } else 2576 buf = (uint8_t *)(uintptr_t)data; 2577 2578 err = t3_seeprom_wp(adapter, 0); 2579 if (err) 2580 goto out; 2581 2582 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2583 err = t3_seeprom_write(adapter, aligned_offset, *p); 2584 aligned_offset += 4; 2585 } 2586 2587 if (!err) 2588 err = t3_seeprom_wp(adapter, 1); 2589out: 2590 if (buf != data) 2591 free(buf, M_DEVBUF); 2592 return err; 2593} 2594 2595 2596static int 2597in_range(int val, int lo, int hi) 2598{ 2599 return val < 0 || (val <= hi && val >= lo); 2600} 2601 2602static int 2603cxgb_extension_open(struct cdev *dev, int flags, int fmp, struct thread *td) 2604{ 2605 return (0); 2606} 2607 2608static int 2609cxgb_extension_close(struct cdev *dev, int flags, int fmt, struct thread *td) 2610{ 2611 return (0); 2612} 2613 2614static int 2615cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2616 int fflag, struct thread *td) 2617{ 2618 int mmd, error = 0; 2619 struct port_info *pi = dev->si_drv1; 2620 adapter_t *sc = pi->adapter; 2621 2622#ifdef PRIV_SUPPORTED 2623 if (priv_check(td, PRIV_DRIVER)) { 2624 if (cxgb_debug) 2625 printf("user does not have access to privileged ioctls\n"); 2626 return (EPERM); 2627 } 2628#else 2629 if (suser(td)) { 2630 if (cxgb_debug) 2631 printf("user does not have access to privileged ioctls\n"); 2632 return (EPERM); 2633 } 2634#endif 2635 2636 switch (cmd) { 2637 case CHELSIO_GET_MIIREG: { 2638 uint32_t val; 2639 struct cphy *phy = &pi->phy; 2640 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2641 2642 if (!phy->mdio_read) 2643 return (EOPNOTSUPP); 2644 if (is_10G(sc)) { 2645 mmd = mid->phy_id >> 8; 2646 if (!mmd) 2647 mmd = MDIO_DEV_PCS; 2648 else if (mmd > MDIO_DEV_VEND2) 2649 return (EINVAL); 2650 2651 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2652 mid->reg_num, &val); 2653 } else 2654 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2655 mid->reg_num & 0x1f, &val); 2656 if (error == 0) 2657 mid->val_out = val; 2658 break; 2659 } 2660 case CHELSIO_SET_MIIREG: { 2661 struct cphy *phy = &pi->phy; 2662 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2663 2664 if (!phy->mdio_write) 2665 return (EOPNOTSUPP); 2666 if (is_10G(sc)) { 2667 mmd = mid->phy_id >> 8; 2668 if (!mmd) 2669 mmd = MDIO_DEV_PCS; 2670 else if (mmd > MDIO_DEV_VEND2) 2671 return (EINVAL); 2672 2673 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2674 mmd, mid->reg_num, mid->val_in); 2675 } else 2676 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2677 mid->reg_num & 0x1f, 2678 mid->val_in); 2679 break; 2680 } 2681 case CHELSIO_SETREG: { 2682 struct ch_reg *edata = (struct ch_reg *)data; 2683 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2684 return (EFAULT); 2685 t3_write_reg(sc, edata->addr, edata->val); 2686 break; 2687 } 2688 case CHELSIO_GETREG: { 2689 struct ch_reg *edata = (struct ch_reg *)data; 2690 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2691 return (EFAULT); 2692 edata->val = t3_read_reg(sc, edata->addr); 2693 break; 2694 } 2695 case CHELSIO_GET_SGE_CONTEXT: { 2696 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2697 mtx_lock_spin(&sc->sge.reg_lock); 2698 switch (ecntxt->cntxt_type) { 2699 case CNTXT_TYPE_EGRESS: 2700 error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2701 ecntxt->data); 2702 break; 2703 case CNTXT_TYPE_FL: 2704 error = -t3_sge_read_fl(sc, ecntxt->cntxt_id, 2705 ecntxt->data); 2706 break; 2707 case CNTXT_TYPE_RSP: 2708 error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2709 ecntxt->data); 2710 break; 2711 case CNTXT_TYPE_CQ: 2712 error = -t3_sge_read_cq(sc, ecntxt->cntxt_id, 2713 ecntxt->data); 2714 break; 2715 default: 2716 error = EINVAL; 2717 break; 2718 } 2719 mtx_unlock_spin(&sc->sge.reg_lock); 2720 break; 2721 } 2722 case CHELSIO_GET_SGE_DESC: { 2723 struct ch_desc *edesc = (struct ch_desc *)data; 2724 int ret; 2725 if (edesc->queue_num >= SGE_QSETS * 6) 2726 return (EINVAL); 2727 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2728 edesc->queue_num % 6, edesc->idx, edesc->data); 2729 if (ret < 0) 2730 return (EINVAL); 2731 edesc->size = ret; 2732 break; 2733 } 2734 case CHELSIO_GET_QSET_PARAMS: { 2735 struct qset_params *q; 2736 struct ch_qset_params *t = (struct ch_qset_params *)data; 2737 int q1 = pi->first_qset; 2738 int nqsets = pi->nqsets; 2739 int i; 2740 2741 if (t->qset_idx >= nqsets) 2742 return EINVAL; 2743 2744 i = q1 + t->qset_idx; 2745 q = &sc->params.sge.qset[i]; 2746 t->rspq_size = q->rspq_size; 2747 t->txq_size[0] = q->txq_size[0]; 2748 t->txq_size[1] = q->txq_size[1]; 2749 t->txq_size[2] = q->txq_size[2]; 2750 t->fl_size[0] = q->fl_size; 2751 t->fl_size[1] = q->jumbo_size; 2752 t->polling = q->polling; 2753 t->lro = q->lro; 2754 t->intr_lat = q->coalesce_usecs; 2755 t->cong_thres = q->cong_thres; 2756 t->qnum = i; 2757 2758 if (sc->flags & USING_MSIX) 2759 t->vector = rman_get_start(sc->msix_irq_res[i]); 2760 else 2761 t->vector = rman_get_start(sc->irq_res); 2762 2763 break; 2764 } 2765 case CHELSIO_GET_QSET_NUM: { 2766 struct ch_reg *edata = (struct ch_reg *)data; 2767 edata->val = pi->nqsets; 2768 break; 2769 } 2770 case CHELSIO_LOAD_FW: { 2771 uint8_t *fw_data; 2772 uint32_t vers; 2773 struct ch_mem_range *t = (struct ch_mem_range *)data; 2774 2775 /* 2776 * You're allowed to load a firmware only before FULL_INIT_DONE 2777 * 2778 * FW_UPTODATE is also set so the rest of the initialization 2779 * will not overwrite what was loaded here. This gives you the 2780 * flexibility to load any firmware (and maybe shoot yourself in 2781 * the foot). 2782 */ 2783 2784 ADAPTER_LOCK(sc); 2785 if (sc->open_device_map || sc->flags & FULL_INIT_DONE) { 2786 ADAPTER_UNLOCK(sc); 2787 return (EBUSY); 2788 } 2789 2790 fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2791 if (!fw_data) 2792 error = ENOMEM; 2793 else 2794 error = copyin(t->buf, fw_data, t->len); 2795 2796 if (!error) 2797 error = -t3_load_fw(sc, fw_data, t->len); 2798 2799 if (t3_get_fw_version(sc, &vers) == 0) { 2800 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), 2801 "%d.%d.%d", G_FW_VERSION_MAJOR(vers), 2802 G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); 2803 } 2804 2805 if (!error) 2806 sc->flags |= FW_UPTODATE; 2807 2808 free(fw_data, M_DEVBUF); 2809 ADAPTER_UNLOCK(sc); 2810 break; 2811 } 2812 case CHELSIO_LOAD_BOOT: { 2813 uint8_t *boot_data; 2814 struct ch_mem_range *t = (struct ch_mem_range *)data; 2815 2816 boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2817 if (!boot_data) 2818 return ENOMEM; 2819 2820 error = copyin(t->buf, boot_data, t->len); 2821 if (!error) 2822 error = -t3_load_boot(sc, boot_data, t->len); 2823 2824 free(boot_data, M_DEVBUF); 2825 break; 2826 } 2827 case CHELSIO_GET_PM: { 2828 struct ch_pm *m = (struct ch_pm *)data; 2829 struct tp_params *p = &sc->params.tp; 2830 2831 if (!is_offload(sc)) 2832 return (EOPNOTSUPP); 2833 2834 m->tx_pg_sz = p->tx_pg_size; 2835 m->tx_num_pg = p->tx_num_pgs; 2836 m->rx_pg_sz = p->rx_pg_size; 2837 m->rx_num_pg = p->rx_num_pgs; 2838 m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; 2839 2840 break; 2841 } 2842 case CHELSIO_SET_PM: { 2843 struct ch_pm *m = (struct ch_pm *)data; 2844 struct tp_params *p = &sc->params.tp; 2845 2846 if (!is_offload(sc)) 2847 return (EOPNOTSUPP); 2848 if (sc->flags & FULL_INIT_DONE) 2849 return (EBUSY); 2850 2851 if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) || 2852 !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1))) 2853 return (EINVAL); /* not power of 2 */ 2854 if (!(m->rx_pg_sz & 0x14000)) 2855 return (EINVAL); /* not 16KB or 64KB */ 2856 if (!(m->tx_pg_sz & 0x1554000)) 2857 return (EINVAL); 2858 if (m->tx_num_pg == -1) 2859 m->tx_num_pg = p->tx_num_pgs; 2860 if (m->rx_num_pg == -1) 2861 m->rx_num_pg = p->rx_num_pgs; 2862 if (m->tx_num_pg % 24 || m->rx_num_pg % 24) 2863 return (EINVAL); 2864 if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size || 2865 m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size) 2866 return (EINVAL); 2867 2868 p->rx_pg_size = m->rx_pg_sz; 2869 p->tx_pg_size = m->tx_pg_sz; 2870 p->rx_num_pgs = m->rx_num_pg; 2871 p->tx_num_pgs = m->tx_num_pg; 2872 break; 2873 } 2874 case CHELSIO_SETMTUTAB: { 2875 struct ch_mtus *m = (struct ch_mtus *)data; 2876 int i; 2877 2878 if (!is_offload(sc)) 2879 return (EOPNOTSUPP); 2880 if (offload_running(sc)) 2881 return (EBUSY); 2882 if (m->nmtus != NMTUS) 2883 return (EINVAL); 2884 if (m->mtus[0] < 81) /* accommodate SACK */ 2885 return (EINVAL); 2886 2887 /* 2888 * MTUs must be in ascending order 2889 */ 2890 for (i = 1; i < NMTUS; ++i) 2891 if (m->mtus[i] < m->mtus[i - 1]) 2892 return (EINVAL); 2893 2894 memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus)); 2895 break; 2896 } 2897 case CHELSIO_GETMTUTAB: { 2898 struct ch_mtus *m = (struct ch_mtus *)data; 2899 2900 if (!is_offload(sc)) 2901 return (EOPNOTSUPP); 2902 2903 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2904 m->nmtus = NMTUS; 2905 break; 2906 } 2907 case CHELSIO_GET_MEM: { 2908 struct ch_mem_range *t = (struct ch_mem_range *)data; 2909 struct mc7 *mem; 2910 uint8_t *useraddr; 2911 u64 buf[32]; 2912 2913 /* 2914 * Use these to avoid modifying len/addr in the the return 2915 * struct 2916 */ 2917 uint32_t len = t->len, addr = t->addr; 2918 2919 if (!is_offload(sc)) 2920 return (EOPNOTSUPP); 2921 if (!(sc->flags & FULL_INIT_DONE)) 2922 return (EIO); /* need the memory controllers */ 2923 if ((addr & 0x7) || (len & 0x7)) 2924 return (EINVAL); 2925 if (t->mem_id == MEM_CM) 2926 mem = &sc->cm; 2927 else if (t->mem_id == MEM_PMRX) 2928 mem = &sc->pmrx; 2929 else if (t->mem_id == MEM_PMTX) 2930 mem = &sc->pmtx; 2931 else 2932 return (EINVAL); 2933 2934 /* 2935 * Version scheme: 2936 * bits 0..9: chip version 2937 * bits 10..15: chip revision 2938 */ 2939 t->version = 3 | (sc->params.rev << 10); 2940 2941 /* 2942 * Read 256 bytes at a time as len can be large and we don't 2943 * want to use huge intermediate buffers. 2944 */ 2945 useraddr = (uint8_t *)t->buf; 2946 while (len) { 2947 unsigned int chunk = min(len, sizeof(buf)); 2948 2949 error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf); 2950 if (error) 2951 return (-error); 2952 if (copyout(buf, useraddr, chunk)) 2953 return (EFAULT); 2954 useraddr += chunk; 2955 addr += chunk; 2956 len -= chunk; 2957 } 2958 break; 2959 } 2960 case CHELSIO_READ_TCAM_WORD: { 2961 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2962 2963 if (!is_offload(sc)) 2964 return (EOPNOTSUPP); 2965 if (!(sc->flags & FULL_INIT_DONE)) 2966 return (EIO); /* need MC5 */ 2967 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2968 break; 2969 } 2970 case CHELSIO_SET_TRACE_FILTER: { 2971 struct ch_trace *t = (struct ch_trace *)data; 2972 const struct trace_params *tp; 2973 2974 tp = (const struct trace_params *)&t->sip; 2975 if (t->config_tx) 2976 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2977 t->trace_tx); 2978 if (t->config_rx) 2979 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2980 t->trace_rx); 2981 break; 2982 } 2983 case CHELSIO_SET_PKTSCHED: { 2984 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2985 if (sc->open_device_map == 0) 2986 return (EAGAIN); 2987 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2988 p->binding); 2989 break; 2990 } 2991 case CHELSIO_IFCONF_GETREGS: { 2992 struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data; 2993 int reglen = cxgb_get_regs_len(); 2994 uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT); 2995 if (buf == NULL) { 2996 return (ENOMEM); 2997 } 2998 if (regs->len > reglen) 2999 regs->len = reglen; 3000 else if (regs->len < reglen) 3001 error = ENOBUFS; 3002 3003 if (!error) { 3004 cxgb_get_regs(sc, regs, buf); 3005 error = copyout(buf, regs->data, reglen); 3006 } 3007 free(buf, M_DEVBUF); 3008 3009 break; 3010 } 3011 case CHELSIO_SET_HW_SCHED: { 3012 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 3013 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 3014 3015 if ((sc->flags & FULL_INIT_DONE) == 0) 3016 return (EAGAIN); /* need TP to be initialized */ 3017 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 3018 !in_range(t->channel, 0, 1) || 3019 !in_range(t->kbps, 0, 10000000) || 3020 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 3021 !in_range(t->flow_ipg, 0, 3022 dack_ticks_to_usec(sc, 0x7ff))) 3023 return (EINVAL); 3024 3025 if (t->kbps >= 0) { 3026 error = t3_config_sched(sc, t->kbps, t->sched); 3027 if (error < 0) 3028 return (-error); 3029 } 3030 if (t->class_ipg >= 0) 3031 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 3032 if (t->flow_ipg >= 0) { 3033 t->flow_ipg *= 1000; /* us -> ns */ 3034 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 3035 } 3036 if (t->mode >= 0) { 3037 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 3038 3039 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 3040 bit, t->mode ? bit : 0); 3041 } 3042 if (t->channel >= 0) 3043 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 3044 1 << t->sched, t->channel << t->sched); 3045 break; 3046 } 3047 case CHELSIO_GET_EEPROM: { 3048 int i; 3049 struct ch_eeprom *e = (struct ch_eeprom *)data; 3050 uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT); 3051 3052 if (buf == NULL) { 3053 return (ENOMEM); 3054 } 3055 e->magic = EEPROM_MAGIC; 3056 for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4) 3057 error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]); 3058 3059 if (!error) 3060 error = copyout(buf + e->offset, e->data, e->len); 3061 3062 free(buf, M_DEVBUF); 3063 break; 3064 } 3065 case CHELSIO_CLEAR_STATS: { 3066 if (!(sc->flags & FULL_INIT_DONE)) 3067 return EAGAIN; 3068 3069 PORT_LOCK(pi); 3070 t3_mac_update_stats(&pi->mac); 3071 memset(&pi->mac.stats, 0, sizeof(pi->mac.stats)); 3072 PORT_UNLOCK(pi); 3073 break; 3074 } 3075 case CHELSIO_GET_UP_LA: { 3076 struct ch_up_la *la = (struct ch_up_la *)data; 3077 uint8_t *buf = malloc(LA_BUFSIZE, M_DEVBUF, M_NOWAIT); 3078 if (buf == NULL) { 3079 return (ENOMEM); 3080 } 3081 if (la->bufsize < LA_BUFSIZE) 3082 error = ENOBUFS; 3083 3084 if (!error) 3085 error = -t3_get_up_la(sc, &la->stopped, &la->idx, 3086 &la->bufsize, buf); 3087 if (!error) 3088 error = copyout(buf, la->data, la->bufsize); 3089 3090 free(buf, M_DEVBUF); 3091 break; 3092 } 3093 case CHELSIO_GET_UP_IOQS: { 3094 struct ch_up_ioqs *ioqs = (struct ch_up_ioqs *)data; 3095 uint8_t *buf = malloc(IOQS_BUFSIZE, M_DEVBUF, M_NOWAIT); 3096 uint32_t *v; 3097 3098 if (buf == NULL) { 3099 return (ENOMEM); 3100 } 3101 if (ioqs->bufsize < IOQS_BUFSIZE) 3102 error = ENOBUFS; 3103 3104 if (!error) 3105 error = -t3_get_up_ioqs(sc, &ioqs->bufsize, buf); 3106 3107 if (!error) { 3108 v = (uint32_t *)buf; 3109 3110 ioqs->bufsize -= 4 * sizeof(uint32_t); 3111 ioqs->ioq_rx_enable = *v++; 3112 ioqs->ioq_tx_enable = *v++; 3113 ioqs->ioq_rx_status = *v++; 3114 ioqs->ioq_tx_status = *v++; 3115 3116 error = copyout(v, ioqs->data, ioqs->bufsize); 3117 } 3118 3119 free(buf, M_DEVBUF); 3120 break; 3121 } 3122 default: 3123 return (EOPNOTSUPP); 3124 break; 3125 } 3126 3127 return (error); 3128} 3129 3130static __inline void 3131reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 3132 unsigned int end) 3133{ 3134 uint32_t *p = (uint32_t *)(buf + start); 3135 3136 for ( ; start <= end; start += sizeof(uint32_t)) 3137 *p++ = t3_read_reg(ap, start); 3138} 3139 3140#define T3_REGMAP_SIZE (3 * 1024) 3141static int 3142cxgb_get_regs_len(void) 3143{ 3144 return T3_REGMAP_SIZE; 3145} 3146 3147static void 3148cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf) 3149{ 3150 3151 /* 3152 * Version scheme: 3153 * bits 0..9: chip version 3154 * bits 10..15: chip revision 3155 * bit 31: set for PCIe cards 3156 */ 3157 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 3158 3159 /* 3160 * We skip the MAC statistics registers because they are clear-on-read. 3161 * Also reading multi-register stats would need to synchronize with the 3162 * periodic mac stats accumulation. Hard to justify the complexity. 3163 */ 3164 memset(buf, 0, cxgb_get_regs_len()); 3165 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 3166 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 3167 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 3168 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 3169 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 3170 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 3171 XGM_REG(A_XGM_SERDES_STAT3, 1)); 3172 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 3173 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 3174} 3175 3176 3177MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 3178