cxgb_main.c revision 196840
1/************************************************************************** 2 3Copyright (c) 2007-2009, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28***************************************************************************/ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_main.c 196840 2009-09-04 21:00:45Z jhb $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/module.h> 38#include <sys/pciio.h> 39#include <sys/conf.h> 40#include <machine/bus.h> 41#include <machine/resource.h> 42#include <sys/bus_dma.h> 43#include <sys/ktr.h> 44#include <sys/rman.h> 45#include <sys/ioccom.h> 46#include <sys/mbuf.h> 47#include <sys/linker.h> 48#include <sys/firmware.h> 49#include <sys/socket.h> 50#include <sys/sockio.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <sys/syslog.h> 54#include <sys/queue.h> 55#include <sys/taskqueue.h> 56#include <sys/proc.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64#include <net/if_types.h> 65#include <net/if_vlan_var.h> 66 67#include <netinet/in_systm.h> 68#include <netinet/in.h> 69#include <netinet/if_ether.h> 70#include <netinet/ip.h> 71#include <netinet/ip.h> 72#include <netinet/tcp.h> 73#include <netinet/udp.h> 74 75#include <dev/pci/pcireg.h> 76#include <dev/pci/pcivar.h> 77#include <dev/pci/pci_private.h> 78 79#include <cxgb_include.h> 80 81#ifdef PRIV_SUPPORTED 82#include <sys/priv.h> 83#endif 84 85static int cxgb_setup_interrupts(adapter_t *); 86static void cxgb_teardown_interrupts(adapter_t *); 87static int cxgb_begin_op(struct port_info *, const char *); 88static int cxgb_begin_detach(struct port_info *); 89static int cxgb_end_op(struct port_info *); 90static void cxgb_init(void *); 91static int cxgb_init_synchronized(struct port_info *); 92static int cxgb_uninit_synchronized(struct port_info *); 93static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 94static int cxgb_media_change(struct ifnet *); 95static int cxgb_ifm_type(int); 96static void cxgb_build_medialist(struct port_info *); 97static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 98static int setup_sge_qsets(adapter_t *); 99static void cxgb_async_intr(void *); 100static void cxgb_ext_intr_handler(void *, int); 101static void cxgb_tick_handler(void *, int); 102static void cxgb_tick(void *); 103static void setup_rss(adapter_t *sc); 104 105/* Attachment glue for the PCI controller end of the device. Each port of 106 * the device is attached separately, as defined later. 107 */ 108static int cxgb_controller_probe(device_t); 109static int cxgb_controller_attach(device_t); 110static int cxgb_controller_detach(device_t); 111static void cxgb_free(struct adapter *); 112static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 113 unsigned int end); 114static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf); 115static int cxgb_get_regs_len(void); 116static int offload_open(struct port_info *pi); 117static void touch_bars(device_t dev); 118static int offload_close(struct t3cdev *tdev); 119int t3_detect_link_fault(adapter_t *adapter, int port_id); 120 121static device_method_t cxgb_controller_methods[] = { 122 DEVMETHOD(device_probe, cxgb_controller_probe), 123 DEVMETHOD(device_attach, cxgb_controller_attach), 124 DEVMETHOD(device_detach, cxgb_controller_detach), 125 126 /* bus interface */ 127 DEVMETHOD(bus_print_child, bus_generic_print_child), 128 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 129 130 { 0, 0 } 131}; 132 133static driver_t cxgb_controller_driver = { 134 "cxgbc", 135 cxgb_controller_methods, 136 sizeof(struct adapter) 137}; 138 139static devclass_t cxgb_controller_devclass; 140DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 141 142/* 143 * Attachment glue for the ports. Attachment is done directly to the 144 * controller device. 145 */ 146static int cxgb_port_probe(device_t); 147static int cxgb_port_attach(device_t); 148static int cxgb_port_detach(device_t); 149 150static device_method_t cxgb_port_methods[] = { 151 DEVMETHOD(device_probe, cxgb_port_probe), 152 DEVMETHOD(device_attach, cxgb_port_attach), 153 DEVMETHOD(device_detach, cxgb_port_detach), 154 { 0, 0 } 155}; 156 157static driver_t cxgb_port_driver = { 158 "cxgb", 159 cxgb_port_methods, 160 0 161}; 162 163static d_ioctl_t cxgb_extension_ioctl; 164static d_open_t cxgb_extension_open; 165static d_close_t cxgb_extension_close; 166 167static struct cdevsw cxgb_cdevsw = { 168 .d_version = D_VERSION, 169 .d_flags = 0, 170 .d_open = cxgb_extension_open, 171 .d_close = cxgb_extension_close, 172 .d_ioctl = cxgb_extension_ioctl, 173 .d_name = "cxgb", 174}; 175 176static devclass_t cxgb_port_devclass; 177DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 178 179/* 180 * The driver uses the best interrupt scheme available on a platform in the 181 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 182 * of these schemes the driver may consider as follows: 183 * 184 * msi = 2: choose from among all three options 185 * msi = 1 : only consider MSI and pin interrupts 186 * msi = 0: force pin interrupts 187 */ 188static int msi_allowed = 2; 189 190TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 191SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 192SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 193 "MSI-X, MSI, INTx selector"); 194 195/* 196 * The driver enables offload as a default. 197 * To disable it, use ofld_disable = 1. 198 */ 199static int ofld_disable = 0; 200TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 201SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 202 "disable ULP offload"); 203 204/* 205 * The driver uses an auto-queue algorithm by default. 206 * To disable it and force a single queue-set per port, use multiq = 0 207 */ 208static int multiq = 1; 209TUNABLE_INT("hw.cxgb.multiq", &multiq); 210SYSCTL_UINT(_hw_cxgb, OID_AUTO, multiq, CTLFLAG_RDTUN, &multiq, 0, 211 "use min(ncpus/ports, 8) queue-sets per port"); 212 213/* 214 * By default the driver will not update the firmware unless 215 * it was compiled against a newer version 216 * 217 */ 218static int force_fw_update = 0; 219TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 220SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 221 "update firmware even if up to date"); 222 223int cxgb_use_16k_clusters = 1; 224TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 225SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 226 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 227 228/* 229 * Tune the size of the output queue. 230 */ 231int cxgb_snd_queue_len = IFQ_MAXLEN; 232TUNABLE_INT("hw.cxgb.snd_queue_len", &cxgb_snd_queue_len); 233SYSCTL_UINT(_hw_cxgb, OID_AUTO, snd_queue_len, CTLFLAG_RDTUN, 234 &cxgb_snd_queue_len, 0, "send queue size "); 235 236 237enum { 238 MAX_TXQ_ENTRIES = 16384, 239 MAX_CTRL_TXQ_ENTRIES = 1024, 240 MAX_RSPQ_ENTRIES = 16384, 241 MAX_RX_BUFFERS = 16384, 242 MAX_RX_JUMBO_BUFFERS = 16384, 243 MIN_TXQ_ENTRIES = 4, 244 MIN_CTRL_TXQ_ENTRIES = 4, 245 MIN_RSPQ_ENTRIES = 32, 246 MIN_FL_ENTRIES = 32, 247 MIN_FL_JUMBO_ENTRIES = 32 248}; 249 250struct filter_info { 251 u32 sip; 252 u32 sip_mask; 253 u32 dip; 254 u16 sport; 255 u16 dport; 256 u32 vlan:12; 257 u32 vlan_prio:3; 258 u32 mac_hit:1; 259 u32 mac_idx:4; 260 u32 mac_vld:1; 261 u32 pkt_type:2; 262 u32 report_filter_id:1; 263 u32 pass:1; 264 u32 rss:1; 265 u32 qset:3; 266 u32 locked:1; 267 u32 valid:1; 268}; 269 270enum { FILTER_NO_VLAN_PRI = 7 }; 271 272#define EEPROM_MAGIC 0x38E2F10C 273 274#define PORT_MASK ((1 << MAX_NPORTS) - 1) 275 276/* Table for probing the cards. The desc field isn't actually used */ 277struct cxgb_ident { 278 uint16_t vendor; 279 uint16_t device; 280 int index; 281 char *desc; 282} cxgb_identifiers[] = { 283 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 284 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 285 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 286 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 287 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 288 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 289 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 290 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 291 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 292 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 293 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 294 {PCI_VENDOR_ID_CHELSIO, 0x0035, 6, "N310E"}, 295 {0, 0, 0, NULL} 296}; 297 298static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 299 300 301static __inline char 302t3rev2char(struct adapter *adapter) 303{ 304 char rev = 'z'; 305 306 switch(adapter->params.rev) { 307 case T3_REV_A: 308 rev = 'a'; 309 break; 310 case T3_REV_B: 311 case T3_REV_B2: 312 rev = 'b'; 313 break; 314 case T3_REV_C: 315 rev = 'c'; 316 break; 317 } 318 return rev; 319} 320 321static struct cxgb_ident * 322cxgb_get_ident(device_t dev) 323{ 324 struct cxgb_ident *id; 325 326 for (id = cxgb_identifiers; id->desc != NULL; id++) { 327 if ((id->vendor == pci_get_vendor(dev)) && 328 (id->device == pci_get_device(dev))) { 329 return (id); 330 } 331 } 332 return (NULL); 333} 334 335static const struct adapter_info * 336cxgb_get_adapter_info(device_t dev) 337{ 338 struct cxgb_ident *id; 339 const struct adapter_info *ai; 340 341 id = cxgb_get_ident(dev); 342 if (id == NULL) 343 return (NULL); 344 345 ai = t3_get_adapter_info(id->index); 346 347 return (ai); 348} 349 350static int 351cxgb_controller_probe(device_t dev) 352{ 353 const struct adapter_info *ai; 354 char *ports, buf[80]; 355 int nports; 356 struct adapter *sc = device_get_softc(dev); 357 358 ai = cxgb_get_adapter_info(dev); 359 if (ai == NULL) 360 return (ENXIO); 361 362 nports = ai->nports0 + ai->nports1; 363 if (nports == 1) 364 ports = "port"; 365 else 366 ports = "ports"; 367 368 snprintf(buf, sizeof(buf), "%s %sNIC, rev: %d nports: %d %s", 369 ai->desc, is_offload(sc) ? "R" : "", 370 sc->params.rev, nports, ports); 371 device_set_desc_copy(dev, buf); 372 return (BUS_PROBE_DEFAULT); 373} 374 375#define FW_FNAME "cxgb_t3fw" 376#define TPEEPROM_NAME "cxgb_t3%c_tp_eeprom" 377#define TPSRAM_NAME "cxgb_t3%c_protocol_sram" 378 379static int 380upgrade_fw(adapter_t *sc) 381{ 382#ifdef FIRMWARE_LATEST 383 const struct firmware *fw; 384#else 385 struct firmware *fw; 386#endif 387 int status; 388 389 if ((fw = firmware_get(FW_FNAME)) == NULL) { 390 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 391 return (ENOENT); 392 } else 393 device_printf(sc->dev, "updating firmware on card\n"); 394 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 395 396 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 397 398 firmware_put(fw, FIRMWARE_UNLOAD); 399 400 return (status); 401} 402 403/* 404 * The cxgb_controller_attach function is responsible for the initial 405 * bringup of the device. Its responsibilities include: 406 * 407 * 1. Determine if the device supports MSI or MSI-X. 408 * 2. Allocate bus resources so that we can access the Base Address Register 409 * 3. Create and initialize mutexes for the controller and its control 410 * logic such as SGE and MDIO. 411 * 4. Call hardware specific setup routine for the adapter as a whole. 412 * 5. Allocate the BAR for doing MSI-X. 413 * 6. Setup the line interrupt iff MSI-X is not supported. 414 * 7. Create the driver's taskq. 415 * 8. Start one task queue service thread. 416 * 9. Check if the firmware and SRAM are up-to-date. They will be 417 * auto-updated later (before FULL_INIT_DONE), if required. 418 * 10. Create a child device for each MAC (port) 419 * 11. Initialize T3 private state. 420 * 12. Trigger the LED 421 * 13. Setup offload iff supported. 422 * 14. Reset/restart the tick callout. 423 * 15. Attach sysctls 424 * 425 * NOTE: Any modification or deviation from this list MUST be reflected in 426 * the above comment. Failure to do so will result in problems on various 427 * error conditions including link flapping. 428 */ 429static int 430cxgb_controller_attach(device_t dev) 431{ 432 device_t child; 433 const struct adapter_info *ai; 434 struct adapter *sc; 435 int i, error = 0; 436 uint32_t vers; 437 int port_qsets = 1; 438#ifdef MSI_SUPPORTED 439 int msi_needed, reg; 440#endif 441 char buf[80]; 442 443 sc = device_get_softc(dev); 444 sc->dev = dev; 445 sc->msi_count = 0; 446 ai = cxgb_get_adapter_info(dev); 447 448 /* 449 * XXX not really related but a recent addition 450 */ 451#ifdef MSI_SUPPORTED 452 /* find the PCIe link width and set max read request to 4KB*/ 453 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 454 uint16_t lnk, pectl; 455 lnk = pci_read_config(dev, reg + 0x12, 2); 456 sc->link_width = (lnk >> 4) & 0x3f; 457 458 pectl = pci_read_config(dev, reg + 0x8, 2); 459 pectl = (pectl & ~0x7000) | (5 << 12); 460 pci_write_config(dev, reg + 0x8, pectl, 2); 461 } 462 463 if (sc->link_width != 0 && sc->link_width <= 4 && 464 (ai->nports0 + ai->nports1) <= 2) { 465 device_printf(sc->dev, 466 "PCIe x%d Link, expect reduced performance\n", 467 sc->link_width); 468 } 469#endif 470 touch_bars(dev); 471 pci_enable_busmaster(dev); 472 /* 473 * Allocate the registers and make them available to the driver. 474 * The registers that we care about for NIC mode are in BAR 0 475 */ 476 sc->regs_rid = PCIR_BAR(0); 477 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 478 &sc->regs_rid, RF_ACTIVE)) == NULL) { 479 device_printf(dev, "Cannot allocate BAR region 0\n"); 480 return (ENXIO); 481 } 482 sc->udbs_rid = PCIR_BAR(2); 483 sc->udbs_res = NULL; 484 if (is_offload(sc) && 485 ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 486 &sc->udbs_rid, RF_ACTIVE)) == NULL)) { 487 device_printf(dev, "Cannot allocate BAR region 1\n"); 488 error = ENXIO; 489 goto out; 490 } 491 492 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 493 device_get_unit(dev)); 494 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 495 496 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 497 device_get_unit(dev)); 498 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 499 device_get_unit(dev)); 500 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 501 device_get_unit(dev)); 502 503 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 504 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 505 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 506 507 sc->bt = rman_get_bustag(sc->regs_res); 508 sc->bh = rman_get_bushandle(sc->regs_res); 509 sc->mmio_len = rman_get_size(sc->regs_res); 510 511 if (t3_prep_adapter(sc, ai, 1) < 0) { 512 printf("prep adapter failed\n"); 513 error = ENODEV; 514 goto out; 515 } 516 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 517 * enough messages for the queue sets. If that fails, try falling 518 * back to MSI. If that fails, then try falling back to the legacy 519 * interrupt pin model. 520 */ 521#ifdef MSI_SUPPORTED 522 523 sc->msix_regs_rid = 0x20; 524 if ((msi_allowed >= 2) && 525 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 526 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 527 528 if (multiq) 529 port_qsets = min(SGE_QSETS/sc->params.nports, mp_ncpus); 530 msi_needed = sc->msi_count = sc->params.nports * port_qsets + 1; 531 532 if (pci_msix_count(dev) == 0 || 533 (error = pci_alloc_msix(dev, &sc->msi_count)) != 0 || 534 sc->msi_count != msi_needed) { 535 device_printf(dev, "alloc msix failed - " 536 "msi_count=%d, msi_needed=%d, err=%d; " 537 "will try MSI\n", sc->msi_count, 538 msi_needed, error); 539 sc->msi_count = 0; 540 port_qsets = 1; 541 pci_release_msi(dev); 542 bus_release_resource(dev, SYS_RES_MEMORY, 543 sc->msix_regs_rid, sc->msix_regs_res); 544 sc->msix_regs_res = NULL; 545 } else { 546 sc->flags |= USING_MSIX; 547 sc->cxgb_intr = cxgb_async_intr; 548 device_printf(dev, 549 "using MSI-X interrupts (%u vectors)\n", 550 sc->msi_count); 551 } 552 } 553 554 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 555 sc->msi_count = 1; 556 if ((error = pci_alloc_msi(dev, &sc->msi_count)) != 0) { 557 device_printf(dev, "alloc msi failed - " 558 "err=%d; will try INTx\n", error); 559 sc->msi_count = 0; 560 port_qsets = 1; 561 pci_release_msi(dev); 562 } else { 563 sc->flags |= USING_MSI; 564 sc->cxgb_intr = t3_intr_msi; 565 device_printf(dev, "using MSI interrupts\n"); 566 } 567 } 568#endif 569 if (sc->msi_count == 0) { 570 device_printf(dev, "using line interrupts\n"); 571 sc->cxgb_intr = t3b_intr; 572 } 573 574 /* Create a private taskqueue thread for handling driver events */ 575#ifdef TASKQUEUE_CURRENT 576 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 577 taskqueue_thread_enqueue, &sc->tq); 578#else 579 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 580 taskqueue_thread_enqueue, &sc->tq); 581#endif 582 if (sc->tq == NULL) { 583 device_printf(dev, "failed to allocate controller task queue\n"); 584 goto out; 585 } 586 587 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 588 device_get_nameunit(dev)); 589 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 590 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 591 592 593 /* Create a periodic callout for checking adapter status */ 594 callout_init(&sc->cxgb_tick_ch, TRUE); 595 596 if (t3_check_fw_version(sc) < 0 || force_fw_update) { 597 /* 598 * Warn user that a firmware update will be attempted in init. 599 */ 600 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 601 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 602 sc->flags &= ~FW_UPTODATE; 603 } else { 604 sc->flags |= FW_UPTODATE; 605 } 606 607 if (t3_check_tpsram_version(sc) < 0) { 608 /* 609 * Warn user that a firmware update will be attempted in init. 610 */ 611 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 612 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 613 sc->flags &= ~TPS_UPTODATE; 614 } else { 615 sc->flags |= TPS_UPTODATE; 616 } 617 618 /* 619 * Create a child device for each MAC. The ethernet attachment 620 * will be done in these children. 621 */ 622 for (i = 0; i < (sc)->params.nports; i++) { 623 struct port_info *pi; 624 625 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 626 device_printf(dev, "failed to add child port\n"); 627 error = EINVAL; 628 goto out; 629 } 630 pi = &sc->port[i]; 631 pi->adapter = sc; 632 pi->nqsets = port_qsets; 633 pi->first_qset = i*port_qsets; 634 pi->port_id = i; 635 pi->tx_chan = i >= ai->nports0; 636 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 637 sc->rxpkt_map[pi->txpkt_intf] = i; 638 sc->port[i].tx_chan = i >= ai->nports0; 639 sc->portdev[i] = child; 640 device_set_softc(child, pi); 641 } 642 if ((error = bus_generic_attach(dev)) != 0) 643 goto out; 644 645 /* initialize sge private state */ 646 t3_sge_init_adapter(sc); 647 648 t3_led_ready(sc); 649 650 cxgb_offload_init(); 651 if (is_offload(sc)) { 652 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 653 cxgb_adapter_ofld(sc); 654 } 655 error = t3_get_fw_version(sc, &vers); 656 if (error) 657 goto out; 658 659 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 660 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 661 G_FW_VERSION_MICRO(vers)); 662 663 snprintf(buf, sizeof(buf), "%s\t E/C: %s S/N: %s", 664 ai->desc, 665 sc->params.vpd.ec, sc->params.vpd.sn); 666 device_set_desc_copy(dev, buf); 667 668 snprintf(&sc->port_types[0], sizeof(sc->port_types), "%x%x%x%x", 669 sc->params.vpd.port_type[0], sc->params.vpd.port_type[1], 670 sc->params.vpd.port_type[2], sc->params.vpd.port_type[3]); 671 672 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 673 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 674 t3_add_attach_sysctls(sc); 675out: 676 if (error) 677 cxgb_free(sc); 678 679 return (error); 680} 681 682/* 683 * The cxgb_controller_detach routine is called with the device is 684 * unloaded from the system. 685 */ 686 687static int 688cxgb_controller_detach(device_t dev) 689{ 690 struct adapter *sc; 691 692 sc = device_get_softc(dev); 693 694 cxgb_free(sc); 695 696 return (0); 697} 698 699/* 700 * The cxgb_free() is called by the cxgb_controller_detach() routine 701 * to tear down the structures that were built up in 702 * cxgb_controller_attach(), and should be the final piece of work 703 * done when fully unloading the driver. 704 * 705 * 706 * 1. Shutting down the threads started by the cxgb_controller_attach() 707 * routine. 708 * 2. Stopping the lower level device and all callouts (cxgb_down_locked()). 709 * 3. Detaching all of the port devices created during the 710 * cxgb_controller_attach() routine. 711 * 4. Removing the device children created via cxgb_controller_attach(). 712 * 5. Releasing PCI resources associated with the device. 713 * 6. Turning off the offload support, iff it was turned on. 714 * 7. Destroying the mutexes created in cxgb_controller_attach(). 715 * 716 */ 717static void 718cxgb_free(struct adapter *sc) 719{ 720 int i; 721 722 ADAPTER_LOCK(sc); 723 sc->flags |= CXGB_SHUTDOWN; 724 ADAPTER_UNLOCK(sc); 725 726 /* 727 * Make sure all child devices are gone. 728 */ 729 bus_generic_detach(sc->dev); 730 for (i = 0; i < (sc)->params.nports; i++) { 731 if (sc->portdev[i] && 732 device_delete_child(sc->dev, sc->portdev[i]) != 0) 733 device_printf(sc->dev, "failed to delete child port\n"); 734 } 735 736 /* 737 * At this point, it is as if cxgb_port_detach has run on all ports, and 738 * cxgb_down has run on the adapter. All interrupts have been silenced, 739 * all open devices have been closed. 740 */ 741 KASSERT(sc->open_device_map == 0, ("%s: device(s) still open (%x)", 742 __func__, sc->open_device_map)); 743 for (i = 0; i < sc->params.nports; i++) { 744 KASSERT(sc->port[i].ifp == NULL, ("%s: port %i undead!", 745 __func__, i)); 746 } 747 748 /* 749 * Finish off the adapter's callouts. 750 */ 751 callout_drain(&sc->cxgb_tick_ch); 752 callout_drain(&sc->sge_timer_ch); 753 754 /* 755 * Release resources grabbed under FULL_INIT_DONE by cxgb_up. The 756 * sysctls are cleaned up by the kernel linker. 757 */ 758 if (sc->flags & FULL_INIT_DONE) { 759 t3_free_sge_resources(sc); 760 sc->flags &= ~FULL_INIT_DONE; 761 } 762 763 /* 764 * Release all interrupt resources. 765 */ 766 cxgb_teardown_interrupts(sc); 767#ifdef MSI_SUPPORTED 768 if (sc->flags & (USING_MSI | USING_MSIX)) { 769 device_printf(sc->dev, "releasing msi message(s)\n"); 770 pci_release_msi(sc->dev); 771 } else { 772 device_printf(sc->dev, "no msi message to release\n"); 773 } 774 775 if (sc->msix_regs_res != NULL) { 776 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 777 sc->msix_regs_res); 778 } 779#endif 780 781 /* 782 * Free the adapter's taskqueue. 783 */ 784 if (sc->tq != NULL) { 785 taskqueue_free(sc->tq); 786 sc->tq = NULL; 787 } 788 789 if (is_offload(sc)) { 790 clrbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 791 cxgb_adapter_unofld(sc); 792 } 793 794#ifdef notyet 795 if (sc->flags & CXGB_OFLD_INIT) 796 cxgb_offload_deactivate(sc); 797#endif 798 free(sc->filters, M_DEVBUF); 799 t3_sge_free(sc); 800 801 cxgb_offload_exit(); 802 803 if (sc->udbs_res != NULL) 804 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 805 sc->udbs_res); 806 807 if (sc->regs_res != NULL) 808 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 809 sc->regs_res); 810 811 MTX_DESTROY(&sc->mdio_lock); 812 MTX_DESTROY(&sc->sge.reg_lock); 813 MTX_DESTROY(&sc->elmer_lock); 814 ADAPTER_LOCK_DEINIT(sc); 815} 816 817/** 818 * setup_sge_qsets - configure SGE Tx/Rx/response queues 819 * @sc: the controller softc 820 * 821 * Determines how many sets of SGE queues to use and initializes them. 822 * We support multiple queue sets per port if we have MSI-X, otherwise 823 * just one queue set per port. 824 */ 825static int 826setup_sge_qsets(adapter_t *sc) 827{ 828 int i, j, err, irq_idx = 0, qset_idx = 0; 829 u_int ntxq = SGE_TXQ_PER_SET; 830 831 if ((err = t3_sge_alloc(sc)) != 0) { 832 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 833 return (err); 834 } 835 836 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 837 irq_idx = -1; 838 839 for (i = 0; i < (sc)->params.nports; i++) { 840 struct port_info *pi = &sc->port[i]; 841 842 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 843 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 844 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 845 &sc->params.sge.qset[qset_idx], ntxq, pi); 846 if (err) { 847 t3_free_sge_resources(sc); 848 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 849 err); 850 return (err); 851 } 852 } 853 } 854 855 return (0); 856} 857 858static void 859cxgb_teardown_interrupts(adapter_t *sc) 860{ 861 int i; 862 863 for (i = 0; i < SGE_QSETS; i++) { 864 if (sc->msix_intr_tag[i] == NULL) { 865 866 /* Should have been setup fully or not at all */ 867 KASSERT(sc->msix_irq_res[i] == NULL && 868 sc->msix_irq_rid[i] == 0, 869 ("%s: half-done interrupt (%d).", __func__, i)); 870 871 continue; 872 } 873 874 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 875 sc->msix_intr_tag[i]); 876 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->msix_irq_rid[i], 877 sc->msix_irq_res[i]); 878 879 sc->msix_irq_res[i] = sc->msix_intr_tag[i] = NULL; 880 sc->msix_irq_rid[i] = 0; 881 } 882 883 if (sc->intr_tag) { 884 KASSERT(sc->irq_res != NULL, 885 ("%s: half-done interrupt.", __func__)); 886 887 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 888 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 889 sc->irq_res); 890 891 sc->irq_res = sc->intr_tag = NULL; 892 sc->irq_rid = 0; 893 } 894} 895 896static int 897cxgb_setup_interrupts(adapter_t *sc) 898{ 899 struct resource *res; 900 void *tag; 901 int i, rid, err, intr_flag = sc->flags & (USING_MSI | USING_MSIX); 902 903 sc->irq_rid = intr_flag ? 1 : 0; 904 sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irq_rid, 905 RF_SHAREABLE | RF_ACTIVE); 906 if (sc->irq_res == NULL) { 907 device_printf(sc->dev, "Cannot allocate interrupt (%x, %u)\n", 908 intr_flag, sc->irq_rid); 909 err = EINVAL; 910 sc->irq_rid = 0; 911 } else { 912 err = bus_setup_intr(sc->dev, sc->irq_res, 913 INTR_MPSAFE | INTR_TYPE_NET, 914#ifdef INTR_FILTERS 915 NULL, 916#endif 917 sc->cxgb_intr, sc, &sc->intr_tag); 918 919 if (err) { 920 device_printf(sc->dev, 921 "Cannot set up interrupt (%x, %u, %d)\n", 922 intr_flag, sc->irq_rid, err); 923 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 924 sc->irq_res); 925 sc->irq_res = sc->intr_tag = NULL; 926 sc->irq_rid = 0; 927 } 928 } 929 930 /* That's all for INTx or MSI */ 931 if (!(intr_flag & USING_MSIX) || err) 932 return (err); 933 934 for (i = 0; i < sc->msi_count - 1; i++) { 935 rid = i + 2; 936 res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, 937 RF_SHAREABLE | RF_ACTIVE); 938 if (res == NULL) { 939 device_printf(sc->dev, "Cannot allocate interrupt " 940 "for message %d\n", rid); 941 err = EINVAL; 942 break; 943 } 944 945 err = bus_setup_intr(sc->dev, res, INTR_MPSAFE | INTR_TYPE_NET, 946#ifdef INTR_FILTERS 947 NULL, 948#endif 949 t3_intr_msix, &sc->sge.qs[i], &tag); 950 if (err) { 951 device_printf(sc->dev, "Cannot set up interrupt " 952 "for message %d (%d)\n", rid, err); 953 bus_release_resource(sc->dev, SYS_RES_IRQ, rid, res); 954 break; 955 } 956 957 sc->msix_irq_rid[i] = rid; 958 sc->msix_irq_res[i] = res; 959 sc->msix_intr_tag[i] = tag; 960 } 961 962 if (err) 963 cxgb_teardown_interrupts(sc); 964 965 return (err); 966} 967 968 969static int 970cxgb_port_probe(device_t dev) 971{ 972 struct port_info *p; 973 char buf[80]; 974 const char *desc; 975 976 p = device_get_softc(dev); 977 desc = p->phy.desc; 978 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 979 device_set_desc_copy(dev, buf); 980 return (0); 981} 982 983 984static int 985cxgb_makedev(struct port_info *pi) 986{ 987 988 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 989 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 990 991 if (pi->port_cdev == NULL) 992 return (ENOMEM); 993 994 pi->port_cdev->si_drv1 = (void *)pi; 995 996 return (0); 997} 998 999#ifndef LRO_SUPPORTED 1000#ifdef IFCAP_LRO 1001#undef IFCAP_LRO 1002#endif 1003#define IFCAP_LRO 0x0 1004#endif 1005 1006#ifdef TSO_SUPPORTED 1007#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO) 1008/* Don't enable TSO6 yet */ 1009#define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_LRO) 1010#else 1011#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 1012/* Don't enable TSO6 yet */ 1013#define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 1014#define IFCAP_TSO4 0x0 1015#define IFCAP_TSO6 0x0 1016#define CSUM_TSO 0x0 1017#endif 1018 1019 1020static int 1021cxgb_port_attach(device_t dev) 1022{ 1023 struct port_info *p; 1024 struct ifnet *ifp; 1025 int err; 1026 struct adapter *sc; 1027 1028 1029 p = device_get_softc(dev); 1030 sc = p->adapter; 1031 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 1032 device_get_unit(device_get_parent(dev)), p->port_id); 1033 PORT_LOCK_INIT(p, p->lockbuf); 1034 1035 /* Allocate an ifnet object and set it up */ 1036 ifp = p->ifp = if_alloc(IFT_ETHER); 1037 if (ifp == NULL) { 1038 device_printf(dev, "Cannot allocate ifnet\n"); 1039 return (ENOMEM); 1040 } 1041 1042 /* 1043 * Note that there is currently no watchdog timer. 1044 */ 1045 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1046 ifp->if_init = cxgb_init; 1047 ifp->if_softc = p; 1048 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1049 ifp->if_ioctl = cxgb_ioctl; 1050 ifp->if_start = cxgb_start; 1051 1052 1053 ifp->if_timer = 0; /* Disable ifnet watchdog */ 1054 ifp->if_watchdog = NULL; 1055 1056 ifp->if_snd.ifq_drv_maxlen = cxgb_snd_queue_len; 1057 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1058 IFQ_SET_READY(&ifp->if_snd); 1059 1060 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 1061 ifp->if_capabilities |= CXGB_CAP; 1062 ifp->if_capenable |= CXGB_CAP_ENABLE; 1063 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 1064 /* 1065 * disable TSO on 4-port - it isn't supported by the firmware yet 1066 */ 1067 if (p->adapter->params.nports > 2) { 1068 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 1069 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 1070 ifp->if_hwassist &= ~CSUM_TSO; 1071 } 1072 1073 ether_ifattach(ifp, p->hw_addr); 1074 ifp->if_transmit = cxgb_transmit; 1075 ifp->if_qflush = cxgb_qflush; 1076 1077 /* 1078 * Only default to jumbo frames on 10GigE 1079 */ 1080 if (p->adapter->params.nports <= 2) 1081 ifp->if_mtu = ETHERMTU_JUMBO; 1082 if ((err = cxgb_makedev(p)) != 0) { 1083 printf("makedev failed %d\n", err); 1084 return (err); 1085 } 1086 1087 /* Create a list of media supported by this port */ 1088 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 1089 cxgb_media_status); 1090 cxgb_build_medialist(p); 1091 1092 t3_sge_init_port(p); 1093 1094 return (err); 1095} 1096 1097/* 1098 * cxgb_port_detach() is called via the device_detach methods when 1099 * cxgb_free() calls the bus_generic_detach. It is responsible for 1100 * removing the device from the view of the kernel, i.e. from all 1101 * interfaces lists etc. This routine is only called when the driver is 1102 * being unloaded, not when the link goes down. 1103 */ 1104static int 1105cxgb_port_detach(device_t dev) 1106{ 1107 struct port_info *p; 1108 struct adapter *sc; 1109 int i; 1110 1111 p = device_get_softc(dev); 1112 sc = p->adapter; 1113 1114 cxgb_begin_detach(p); 1115 1116 if (p->port_cdev != NULL) 1117 destroy_dev(p->port_cdev); 1118 1119 cxgb_uninit_synchronized(p); 1120 ether_ifdetach(p->ifp); 1121 1122 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { 1123 struct sge_qset *qs = &sc->sge.qs[i]; 1124 struct sge_txq *txq = &qs->txq[TXQ_ETH]; 1125 1126 callout_drain(&txq->txq_watchdog); 1127 callout_drain(&txq->txq_timer); 1128 } 1129 1130 PORT_LOCK_DEINIT(p); 1131 if_free(p->ifp); 1132 p->ifp = NULL; 1133 1134 cxgb_end_op(p); 1135 return (0); 1136} 1137 1138void 1139t3_fatal_err(struct adapter *sc) 1140{ 1141 u_int fw_status[4]; 1142 1143 if (sc->flags & FULL_INIT_DONE) { 1144 t3_sge_stop(sc); 1145 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1146 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1147 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1148 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1149 t3_intr_disable(sc); 1150 } 1151 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1152 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1153 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1154 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1155} 1156 1157int 1158t3_os_find_pci_capability(adapter_t *sc, int cap) 1159{ 1160 device_t dev; 1161 struct pci_devinfo *dinfo; 1162 pcicfgregs *cfg; 1163 uint32_t status; 1164 uint8_t ptr; 1165 1166 dev = sc->dev; 1167 dinfo = device_get_ivars(dev); 1168 cfg = &dinfo->cfg; 1169 1170 status = pci_read_config(dev, PCIR_STATUS, 2); 1171 if (!(status & PCIM_STATUS_CAPPRESENT)) 1172 return (0); 1173 1174 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1175 case 0: 1176 case 1: 1177 ptr = PCIR_CAP_PTR; 1178 break; 1179 case 2: 1180 ptr = PCIR_CAP_PTR_2; 1181 break; 1182 default: 1183 return (0); 1184 break; 1185 } 1186 ptr = pci_read_config(dev, ptr, 1); 1187 1188 while (ptr != 0) { 1189 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1190 return (ptr); 1191 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1192 } 1193 1194 return (0); 1195} 1196 1197int 1198t3_os_pci_save_state(struct adapter *sc) 1199{ 1200 device_t dev; 1201 struct pci_devinfo *dinfo; 1202 1203 dev = sc->dev; 1204 dinfo = device_get_ivars(dev); 1205 1206 pci_cfg_save(dev, dinfo, 0); 1207 return (0); 1208} 1209 1210int 1211t3_os_pci_restore_state(struct adapter *sc) 1212{ 1213 device_t dev; 1214 struct pci_devinfo *dinfo; 1215 1216 dev = sc->dev; 1217 dinfo = device_get_ivars(dev); 1218 1219 pci_cfg_restore(dev, dinfo); 1220 return (0); 1221} 1222 1223/** 1224 * t3_os_link_changed - handle link status changes 1225 * @adapter: the adapter associated with the link change 1226 * @port_id: the port index whose limk status has changed 1227 * @link_status: the new status of the link 1228 * @speed: the new speed setting 1229 * @duplex: the new duplex setting 1230 * @fc: the new flow-control setting 1231 * 1232 * This is the OS-dependent handler for link status changes. The OS 1233 * neutral handler takes care of most of the processing for these events, 1234 * then calls this handler for any OS-specific processing. 1235 */ 1236void 1237t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1238 int duplex, int fc) 1239{ 1240 struct port_info *pi = &adapter->port[port_id]; 1241 struct ifnet *ifp = pi->ifp; 1242 1243 /* no race with detach, so ifp should always be good */ 1244 KASSERT(ifp, ("%s: if detached.", __func__)); 1245 1246 if (link_status) { 1247 ifp->if_baudrate = IF_Mbps(speed); 1248 if_link_state_change(ifp, LINK_STATE_UP); 1249 } else 1250 if_link_state_change(ifp, LINK_STATE_DOWN); 1251} 1252 1253/** 1254 * t3_os_phymod_changed - handle PHY module changes 1255 * @phy: the PHY reporting the module change 1256 * @mod_type: new module type 1257 * 1258 * This is the OS-dependent handler for PHY module changes. It is 1259 * invoked when a PHY module is removed or inserted for any OS-specific 1260 * processing. 1261 */ 1262void t3_os_phymod_changed(struct adapter *adap, int port_id) 1263{ 1264 static const char *mod_str[] = { 1265 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown" 1266 }; 1267 struct port_info *pi = &adap->port[port_id]; 1268 int mod = pi->phy.modtype; 1269 1270 if (mod != pi->media.ifm_cur->ifm_data) 1271 cxgb_build_medialist(pi); 1272 1273 if (mod == phy_modtype_none) 1274 if_printf(pi->ifp, "PHY module unplugged\n"); 1275 else { 1276 KASSERT(mod < ARRAY_SIZE(mod_str), 1277 ("invalid PHY module type %d", mod)); 1278 if_printf(pi->ifp, "%s PHY module inserted\n", mod_str[mod]); 1279 } 1280} 1281 1282/* 1283 * Interrupt-context handler for external (PHY) interrupts. 1284 */ 1285void 1286t3_os_ext_intr_handler(adapter_t *sc) 1287{ 1288 if (cxgb_debug) 1289 printf("t3_os_ext_intr_handler\n"); 1290 /* 1291 * Schedule a task to handle external interrupts as they may be slow 1292 * and we use a mutex to protect MDIO registers. We disable PHY 1293 * interrupts in the meantime and let the task reenable them when 1294 * it's done. 1295 */ 1296 if (sc->slow_intr_mask) { 1297 ADAPTER_LOCK(sc); 1298 sc->slow_intr_mask &= ~F_T3DBG; 1299 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1300 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1301 ADAPTER_UNLOCK(sc); 1302 } 1303} 1304 1305void 1306t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1307{ 1308 1309 /* 1310 * The ifnet might not be allocated before this gets called, 1311 * as this is called early on in attach by t3_prep_adapter 1312 * save the address off in the port structure 1313 */ 1314 if (cxgb_debug) 1315 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1316 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1317} 1318 1319/* 1320 * Programs the XGMAC based on the settings in the ifnet. These settings 1321 * include MTU, MAC address, mcast addresses, etc. 1322 */ 1323static void 1324cxgb_update_mac_settings(struct port_info *p) 1325{ 1326 struct ifnet *ifp = p->ifp; 1327 struct t3_rx_mode rm; 1328 struct cmac *mac = &p->mac; 1329 int mtu, hwtagging; 1330 1331 PORT_LOCK_ASSERT_OWNED(p); 1332 1333 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN); 1334 1335 mtu = ifp->if_mtu; 1336 if (ifp->if_capenable & IFCAP_VLAN_MTU) 1337 mtu += ETHER_VLAN_ENCAP_LEN; 1338 1339 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0; 1340 1341 t3_mac_set_mtu(mac, mtu); 1342 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging); 1343 t3_mac_set_address(mac, 0, p->hw_addr); 1344 t3_init_rx_mode(&rm, p); 1345 t3_mac_set_rx_mode(mac, &rm); 1346} 1347 1348 1349static int 1350await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1351 unsigned long n) 1352{ 1353 int attempts = 5; 1354 1355 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1356 if (!--attempts) 1357 return (ETIMEDOUT); 1358 t3_os_sleep(10); 1359 } 1360 return 0; 1361} 1362 1363static int 1364init_tp_parity(struct adapter *adap) 1365{ 1366 int i; 1367 struct mbuf *m; 1368 struct cpl_set_tcb_field *greq; 1369 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1370 1371 t3_tp_set_offload_mode(adap, 1); 1372 1373 for (i = 0; i < 16; i++) { 1374 struct cpl_smt_write_req *req; 1375 1376 m = m_gethdr(M_WAITOK, MT_DATA); 1377 req = mtod(m, struct cpl_smt_write_req *); 1378 m->m_len = m->m_pkthdr.len = sizeof(*req); 1379 memset(req, 0, sizeof(*req)); 1380 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1381 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1382 req->iff = i; 1383 t3_mgmt_tx(adap, m); 1384 } 1385 1386 for (i = 0; i < 2048; i++) { 1387 struct cpl_l2t_write_req *req; 1388 1389 m = m_gethdr(M_WAITOK, MT_DATA); 1390 req = mtod(m, struct cpl_l2t_write_req *); 1391 m->m_len = m->m_pkthdr.len = sizeof(*req); 1392 memset(req, 0, sizeof(*req)); 1393 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1394 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1395 req->params = htonl(V_L2T_W_IDX(i)); 1396 t3_mgmt_tx(adap, m); 1397 } 1398 1399 for (i = 0; i < 2048; i++) { 1400 struct cpl_rte_write_req *req; 1401 1402 m = m_gethdr(M_WAITOK, MT_DATA); 1403 req = mtod(m, struct cpl_rte_write_req *); 1404 m->m_len = m->m_pkthdr.len = sizeof(*req); 1405 memset(req, 0, sizeof(*req)); 1406 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1407 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1408 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1409 t3_mgmt_tx(adap, m); 1410 } 1411 1412 m = m_gethdr(M_WAITOK, MT_DATA); 1413 greq = mtod(m, struct cpl_set_tcb_field *); 1414 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1415 memset(greq, 0, sizeof(*greq)); 1416 greq->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1417 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1418 greq->mask = htobe64(1); 1419 t3_mgmt_tx(adap, m); 1420 1421 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1422 t3_tp_set_offload_mode(adap, 0); 1423 return (i); 1424} 1425 1426/** 1427 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1428 * @adap: the adapter 1429 * 1430 * Sets up RSS to distribute packets to multiple receive queues. We 1431 * configure the RSS CPU lookup table to distribute to the number of HW 1432 * receive queues, and the response queue lookup table to narrow that 1433 * down to the response queues actually configured for each port. 1434 * We always configure the RSS mapping for two ports since the mapping 1435 * table has plenty of entries. 1436 */ 1437static void 1438setup_rss(adapter_t *adap) 1439{ 1440 int i; 1441 u_int nq[2]; 1442 uint8_t cpus[SGE_QSETS + 1]; 1443 uint16_t rspq_map[RSS_TABLE_SIZE]; 1444 1445 for (i = 0; i < SGE_QSETS; ++i) 1446 cpus[i] = i; 1447 cpus[SGE_QSETS] = 0xff; 1448 1449 nq[0] = nq[1] = 0; 1450 for_each_port(adap, i) { 1451 const struct port_info *pi = adap2pinfo(adap, i); 1452 1453 nq[pi->tx_chan] += pi->nqsets; 1454 } 1455 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1456 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1457 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1458 } 1459 1460 /* Calculate the reverse RSS map table */ 1461 for (i = 0; i < SGE_QSETS; ++i) 1462 adap->rrss_map[i] = 0xff; 1463 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1464 if (adap->rrss_map[rspq_map[i]] == 0xff) 1465 adap->rrss_map[rspq_map[i]] = i; 1466 1467 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1468 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1469 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1470 cpus, rspq_map); 1471 1472} 1473 1474/* 1475 * Sends an mbuf to an offload queue driver 1476 * after dealing with any active network taps. 1477 */ 1478static inline int 1479offload_tx(struct t3cdev *tdev, struct mbuf *m) 1480{ 1481 int ret; 1482 1483 ret = t3_offload_tx(tdev, m); 1484 return (ret); 1485} 1486 1487static int 1488write_smt_entry(struct adapter *adapter, int idx) 1489{ 1490 struct port_info *pi = &adapter->port[idx]; 1491 struct cpl_smt_write_req *req; 1492 struct mbuf *m; 1493 1494 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1495 return (ENOMEM); 1496 1497 req = mtod(m, struct cpl_smt_write_req *); 1498 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1499 1500 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1501 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1502 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1503 req->iff = idx; 1504 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1505 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1506 1507 m_set_priority(m, 1); 1508 1509 offload_tx(&adapter->tdev, m); 1510 1511 return (0); 1512} 1513 1514static int 1515init_smt(struct adapter *adapter) 1516{ 1517 int i; 1518 1519 for_each_port(adapter, i) 1520 write_smt_entry(adapter, i); 1521 return 0; 1522} 1523 1524static void 1525init_port_mtus(adapter_t *adapter) 1526{ 1527 unsigned int mtus = ETHERMTU | (ETHERMTU << 16); 1528 1529 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1530} 1531 1532static void 1533send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1534 int hi, int port) 1535{ 1536 struct mbuf *m; 1537 struct mngt_pktsched_wr *req; 1538 1539 m = m_gethdr(M_DONTWAIT, MT_DATA); 1540 if (m) { 1541 req = mtod(m, struct mngt_pktsched_wr *); 1542 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1543 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1544 req->sched = sched; 1545 req->idx = qidx; 1546 req->min = lo; 1547 req->max = hi; 1548 req->binding = port; 1549 m->m_len = m->m_pkthdr.len = sizeof(*req); 1550 t3_mgmt_tx(adap, m); 1551 } 1552} 1553 1554static void 1555bind_qsets(adapter_t *sc) 1556{ 1557 int i, j; 1558 1559 for (i = 0; i < (sc)->params.nports; ++i) { 1560 const struct port_info *pi = adap2pinfo(sc, i); 1561 1562 for (j = 0; j < pi->nqsets; ++j) { 1563 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1564 -1, pi->tx_chan); 1565 1566 } 1567 } 1568} 1569 1570static void 1571update_tpeeprom(struct adapter *adap) 1572{ 1573#ifdef FIRMWARE_LATEST 1574 const struct firmware *tpeeprom; 1575#else 1576 struct firmware *tpeeprom; 1577#endif 1578 1579 uint32_t version; 1580 unsigned int major, minor; 1581 int ret, len; 1582 char rev, name[32]; 1583 1584 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1585 1586 major = G_TP_VERSION_MAJOR(version); 1587 minor = G_TP_VERSION_MINOR(version); 1588 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1589 return; 1590 1591 rev = t3rev2char(adap); 1592 snprintf(name, sizeof(name), TPEEPROM_NAME, rev); 1593 1594 tpeeprom = firmware_get(name); 1595 if (tpeeprom == NULL) { 1596 device_printf(adap->dev, 1597 "could not load TP EEPROM: unable to load %s\n", 1598 name); 1599 return; 1600 } 1601 1602 len = tpeeprom->datasize - 4; 1603 1604 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1605 if (ret) 1606 goto release_tpeeprom; 1607 1608 if (len != TP_SRAM_LEN) { 1609 device_printf(adap->dev, 1610 "%s length is wrong len=%d expected=%d\n", name, 1611 len, TP_SRAM_LEN); 1612 return; 1613 } 1614 1615 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1616 TP_SRAM_OFFSET); 1617 1618 if (!ret) { 1619 device_printf(adap->dev, 1620 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1621 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1622 } else 1623 device_printf(adap->dev, 1624 "Protocol SRAM image update in EEPROM failed\n"); 1625 1626release_tpeeprom: 1627 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1628 1629 return; 1630} 1631 1632static int 1633update_tpsram(struct adapter *adap) 1634{ 1635#ifdef FIRMWARE_LATEST 1636 const struct firmware *tpsram; 1637#else 1638 struct firmware *tpsram; 1639#endif 1640 int ret; 1641 char rev, name[32]; 1642 1643 rev = t3rev2char(adap); 1644 snprintf(name, sizeof(name), TPSRAM_NAME, rev); 1645 1646 update_tpeeprom(adap); 1647 1648 tpsram = firmware_get(name); 1649 if (tpsram == NULL){ 1650 device_printf(adap->dev, "could not load TP SRAM\n"); 1651 return (EINVAL); 1652 } else 1653 device_printf(adap->dev, "updating TP SRAM\n"); 1654 1655 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1656 if (ret) 1657 goto release_tpsram; 1658 1659 ret = t3_set_proto_sram(adap, tpsram->data); 1660 if (ret) 1661 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1662 1663release_tpsram: 1664 firmware_put(tpsram, FIRMWARE_UNLOAD); 1665 1666 return ret; 1667} 1668 1669/** 1670 * cxgb_up - enable the adapter 1671 * @adap: adapter being enabled 1672 * 1673 * Called when the first port is enabled, this function performs the 1674 * actions necessary to make an adapter operational, such as completing 1675 * the initialization of HW modules, and enabling interrupts. 1676 */ 1677static int 1678cxgb_up(struct adapter *sc) 1679{ 1680 int err = 0; 1681 1682 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1683 KASSERT(sc->open_device_map == 0, ("%s: device(s) already open (%x)", 1684 __func__, sc->open_device_map)); 1685 1686 if ((sc->flags & FULL_INIT_DONE) == 0) { 1687 1688 if ((sc->flags & FW_UPTODATE) == 0) 1689 if ((err = upgrade_fw(sc))) 1690 goto out; 1691 1692 if ((sc->flags & TPS_UPTODATE) == 0) 1693 if ((err = update_tpsram(sc))) 1694 goto out; 1695 1696 err = t3_init_hw(sc, 0); 1697 if (err) 1698 goto out; 1699 1700 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1701 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1702 1703 err = setup_sge_qsets(sc); 1704 if (err) 1705 goto out; 1706 1707 setup_rss(sc); 1708 1709 t3_intr_clear(sc); 1710 err = cxgb_setup_interrupts(sc); 1711 if (err) 1712 goto out; 1713 1714 t3_add_configured_sysctls(sc); 1715 sc->flags |= FULL_INIT_DONE; 1716 } 1717 1718 t3_intr_clear(sc); 1719 t3_sge_start(sc); 1720 t3_intr_enable(sc); 1721 1722 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1723 is_offload(sc) && init_tp_parity(sc) == 0) 1724 sc->flags |= TP_PARITY_INIT; 1725 1726 if (sc->flags & TP_PARITY_INIT) { 1727 t3_write_reg(sc, A_TP_INT_CAUSE, F_CMCACHEPERR | F_ARPLUTPERR); 1728 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1729 } 1730 1731 if (!(sc->flags & QUEUES_BOUND)) { 1732 bind_qsets(sc); 1733 sc->flags |= QUEUES_BOUND; 1734 } 1735 1736 t3_sge_reset_adapter(sc); 1737out: 1738 return (err); 1739} 1740 1741/* 1742 * Called when the last open device is closed. Does NOT undo all of cxgb_up's 1743 * work. Specifically, the resources grabbed under FULL_INIT_DONE are released 1744 * during controller_detach, not here. 1745 */ 1746static void 1747cxgb_down(struct adapter *sc) 1748{ 1749 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1750 1751 t3_sge_stop(sc); 1752 t3_intr_disable(sc); 1753} 1754 1755static int 1756offload_open(struct port_info *pi) 1757{ 1758 struct adapter *sc = pi->adapter; 1759 struct t3cdev *tdev = &sc->tdev; 1760 1761 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1762 1763 setbit(&sc->open_device_map, OFFLOAD_DEVMAP_BIT); 1764 1765 t3_tp_set_offload_mode(sc, 1); 1766 tdev->lldev = pi->ifp; 1767 init_port_mtus(sc); 1768 t3_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd, 1769 sc->params.rev == 0 ? sc->port[0].ifp->if_mtu : 0xffff); 1770 init_smt(sc); 1771 cxgb_add_clients(tdev); 1772 1773 return (0); 1774} 1775 1776static int 1777offload_close(struct t3cdev *tdev) 1778{ 1779 struct adapter *adapter = tdev2adap(tdev); 1780 1781 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1782 return (0); 1783 1784 /* Call back all registered clients */ 1785 cxgb_remove_clients(tdev); 1786 1787 tdev->lldev = NULL; 1788 cxgb_set_dummy_ops(tdev); 1789 t3_tp_set_offload_mode(adapter, 0); 1790 1791 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1792 1793 return (0); 1794} 1795 1796/* 1797 * Begin a synchronized operation. If this call succeeds, it is guaranteed that 1798 * no one will remove the port or its ifp from underneath the caller. Caller is 1799 * also granted exclusive access to open_device_map. 1800 * 1801 * operation here means init, uninit, detach, and ioctl service. 1802 * 1803 * May fail. 1804 * EINTR (ctrl-c pressed during ifconfig for example). 1805 * ENXIO (port is about to detach - due to kldunload for example). 1806 */ 1807int 1808cxgb_begin_op(struct port_info *p, const char *wmsg) 1809{ 1810 int rc = 0; 1811 struct adapter *sc = p->adapter; 1812 1813 ADAPTER_LOCK(sc); 1814 1815 while (!IS_DOOMED(p) && IS_BUSY(sc)) { 1816 if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, wmsg, 0)) { 1817 rc = EINTR; 1818 goto done; 1819 } 1820 } 1821 1822 if (IS_DOOMED(p)) 1823 rc = ENXIO; 1824 else if (!IS_BUSY(sc)) 1825 SET_BUSY(sc); 1826 else { 1827 KASSERT(0, ("%s: port %d, p->flags = %x , sc->flags = %x", 1828 __func__, p->port_id, p->flags, sc->flags)); 1829 rc = EDOOFUS; 1830 } 1831 1832done: 1833 ADAPTER_UNLOCK(sc); 1834 return (rc); 1835} 1836 1837/* 1838 * End a synchronized operation. Read comment block above cxgb_begin_op. 1839 */ 1840int 1841cxgb_end_op(struct port_info *p) 1842{ 1843 struct adapter *sc = p->adapter; 1844 1845 ADAPTER_LOCK(sc); 1846 KASSERT(IS_BUSY(sc), ("%s: not busy.", __func__)); 1847 CLR_BUSY(sc); 1848 wakeup_one(&sc->flags); 1849 ADAPTER_UNLOCK(sc); 1850 1851 return (0); 1852} 1853 1854/* 1855 * Prepare for port detachment. Detach is a special kind of synchronized 1856 * operation. Also read comment before cxgb_begin_op. 1857 */ 1858static int 1859cxgb_begin_detach(struct port_info *p) 1860{ 1861 struct adapter *sc = p->adapter; 1862 1863 /* 1864 * Inform those waiting for this port that it is going to be destroyed 1865 * and they should not continue further. (They'll return with ENXIO). 1866 */ 1867 ADAPTER_LOCK(sc); 1868 SET_DOOMED(p); 1869 wakeup(&sc->flags); 1870 ADAPTER_UNLOCK(sc); 1871 1872 /* 1873 * Wait for in-progress operations. 1874 */ 1875 ADAPTER_LOCK(sc); 1876 while (IS_BUSY(sc)) { 1877 mtx_sleep(&sc->flags, &sc->lock, 0, "cxgbdtch", 0); 1878 } 1879 SET_BUSY(sc); 1880 ADAPTER_UNLOCK(sc); 1881 1882 return (0); 1883} 1884 1885/* 1886 * if_init for cxgb ports. 1887 */ 1888static void 1889cxgb_init(void *arg) 1890{ 1891 struct port_info *p = arg; 1892 1893 if (cxgb_begin_op(p, "cxgbinit")) 1894 return; 1895 1896 cxgb_init_synchronized(p); 1897 cxgb_end_op(p); 1898} 1899 1900static int 1901cxgb_init_synchronized(struct port_info *p) 1902{ 1903 struct adapter *sc = p->adapter; 1904 struct ifnet *ifp = p->ifp; 1905 struct cmac *mac = &p->mac; 1906 int i, rc; 1907 1908 if (sc->open_device_map == 0) { 1909 if ((rc = cxgb_up(sc)) != 0) 1910 return (rc); 1911 1912 if (is_offload(sc) && !ofld_disable && offload_open(p)) 1913 log(LOG_WARNING, 1914 "Could not initialize offload capabilities\n"); 1915 } 1916 1917 PORT_LOCK(p); 1918 t3_port_intr_enable(sc, p->port_id); 1919 if (!mac->multiport) 1920 t3_mac_reset(mac); 1921 cxgb_update_mac_settings(p); 1922 t3_link_start(&p->phy, mac, &p->link_config); 1923 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1924 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1925 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1926 PORT_UNLOCK(p); 1927 1928 t3_link_changed(sc, p->port_id); 1929 1930 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { 1931 struct sge_qset *qs = &sc->sge.qs[i]; 1932 struct sge_txq *txq = &qs->txq[TXQ_ETH]; 1933 1934 callout_reset_on(&txq->txq_watchdog, hz, cxgb_tx_watchdog, qs, 1935 txq->txq_watchdog.c_cpu); 1936 } 1937 1938 /* all ok */ 1939 setbit(&sc->open_device_map, p->port_id); 1940 1941 return (0); 1942} 1943 1944/* 1945 * Called on "ifconfig down", and from port_detach 1946 */ 1947static int 1948cxgb_uninit_synchronized(struct port_info *pi) 1949{ 1950 struct adapter *sc = pi->adapter; 1951 struct ifnet *ifp = pi->ifp; 1952 1953 /* 1954 * Clear this port's bit from the open device map, and then drain all 1955 * the tasks that can access/manipulate this port's port_info or ifp. 1956 * We disable this port's interrupts here and so the the slow/ext 1957 * interrupt tasks won't be enqueued. The tick task will continue to 1958 * be enqueued every second but the runs after this drain will not see 1959 * this port in the open device map. 1960 * 1961 * A well behaved task must take open_device_map into account and ignore 1962 * ports that are not open. 1963 */ 1964 clrbit(&sc->open_device_map, pi->port_id); 1965 t3_port_intr_disable(sc, pi->port_id); 1966 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1967 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1968 taskqueue_drain(sc->tq, &sc->tick_task); 1969 1970 PORT_LOCK(pi); 1971 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1972 1973 /* disable pause frames */ 1974 t3_set_reg_field(sc, A_XGM_TX_CFG + pi->mac.offset, F_TXPAUSEEN, 0); 1975 1976 /* Reset RX FIFO HWM */ 1977 t3_set_reg_field(sc, A_XGM_RXFIFO_CFG + pi->mac.offset, 1978 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); 1979 1980 DELAY(100); 1981 1982 /* Wait for TXFIFO empty */ 1983 t3_wait_op_done(sc, A_XGM_TXFIFO_CFG + pi->mac.offset, 1984 F_TXFIFO_EMPTY, 1, 20, 5); 1985 1986 DELAY(100); 1987 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1988 1989 1990 pi->phy.ops->power_down(&pi->phy, 1); 1991 1992 PORT_UNLOCK(pi); 1993 1994 pi->link_config.link_ok = 0; 1995 t3_os_link_changed(sc, pi->port_id, 0, 0, 0, 0); 1996 1997 if ((sc->open_device_map & PORT_MASK) == 0) 1998 offload_close(&sc->tdev); 1999 2000 if (sc->open_device_map == 0) 2001 cxgb_down(pi->adapter); 2002 2003 return (0); 2004} 2005 2006#ifdef LRO_SUPPORTED 2007/* 2008 * Mark lro enabled or disabled in all qsets for this port 2009 */ 2010static int 2011cxgb_set_lro(struct port_info *p, int enabled) 2012{ 2013 int i; 2014 struct adapter *adp = p->adapter; 2015 struct sge_qset *q; 2016 2017 PORT_LOCK_ASSERT_OWNED(p); 2018 for (i = 0; i < p->nqsets; i++) { 2019 q = &adp->sge.qs[p->first_qset + i]; 2020 q->lro.enabled = (enabled != 0); 2021 } 2022 return (0); 2023} 2024#endif 2025 2026static int 2027cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 2028{ 2029 struct port_info *p = ifp->if_softc; 2030 struct ifreq *ifr = (struct ifreq *)data; 2031 int flags, error = 0, mtu, handle_unsynchronized = 0; 2032 uint32_t mask; 2033 2034 if ((error = cxgb_begin_op(p, "cxgbioct")) != 0) 2035 return (error); 2036 2037 /* 2038 * Only commands that should be handled within begin-op/end-op are 2039 * serviced in this switch statement. See handle_unsynchronized. 2040 */ 2041 switch (command) { 2042 case SIOCSIFMTU: 2043 mtu = ifr->ifr_mtu; 2044 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) { 2045 error = EINVAL; 2046 } else { 2047 ifp->if_mtu = mtu; 2048 PORT_LOCK(p); 2049 cxgb_update_mac_settings(p); 2050 PORT_UNLOCK(p); 2051 } 2052 2053 break; 2054 case SIOCSIFFLAGS: 2055 if (ifp->if_flags & IFF_UP) { 2056 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2057 flags = p->if_flags; 2058 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 2059 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) { 2060 PORT_LOCK(p); 2061 cxgb_update_mac_settings(p); 2062 PORT_UNLOCK(p); 2063 } 2064 } else 2065 error = cxgb_init_synchronized(p); 2066 p->if_flags = ifp->if_flags; 2067 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2068 error = cxgb_uninit_synchronized(p); 2069 2070 break; 2071 case SIOCADDMULTI: 2072 case SIOCDELMULTI: 2073 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2074 PORT_LOCK(p); 2075 cxgb_update_mac_settings(p); 2076 PORT_UNLOCK(p); 2077 } 2078 2079 break; 2080 case SIOCSIFCAP: 2081 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2082 if (mask & IFCAP_TXCSUM) { 2083 if (IFCAP_TXCSUM & ifp->if_capenable) { 2084 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 2085 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 2086 | CSUM_IP | CSUM_TSO); 2087 } else { 2088 ifp->if_capenable |= IFCAP_TXCSUM; 2089 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP 2090 | CSUM_IP); 2091 } 2092 } 2093 if (mask & IFCAP_RXCSUM) { 2094 ifp->if_capenable ^= IFCAP_RXCSUM; 2095 } 2096 if (mask & IFCAP_TSO4) { 2097 if (IFCAP_TSO4 & ifp->if_capenable) { 2098 ifp->if_capenable &= ~IFCAP_TSO4; 2099 ifp->if_hwassist &= ~CSUM_TSO; 2100 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 2101 ifp->if_capenable |= IFCAP_TSO4; 2102 ifp->if_hwassist |= CSUM_TSO; 2103 } else 2104 error = EINVAL; 2105 } 2106#ifdef LRO_SUPPORTED 2107 if (mask & IFCAP_LRO) { 2108 ifp->if_capenable ^= IFCAP_LRO; 2109 2110 /* Safe to do this even if cxgb_up not called yet */ 2111 cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO); 2112 } 2113#endif 2114 if (mask & IFCAP_VLAN_HWTAGGING) { 2115 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2116 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2117 PORT_LOCK(p); 2118 cxgb_update_mac_settings(p); 2119 PORT_UNLOCK(p); 2120 } 2121 } 2122 if (mask & IFCAP_VLAN_MTU) { 2123 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2124 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2125 PORT_LOCK(p); 2126 cxgb_update_mac_settings(p); 2127 PORT_UNLOCK(p); 2128 } 2129 } 2130 if (mask & IFCAP_VLAN_HWCSUM) { 2131 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2132 } 2133 2134#ifdef VLAN_CAPABILITIES 2135 VLAN_CAPABILITIES(ifp); 2136#endif 2137 break; 2138 default: 2139 handle_unsynchronized = 1; 2140 break; 2141 } 2142 2143 /* 2144 * We don't want to call anything outside the driver while inside a 2145 * begin-op/end-op block. If it calls us back (eg. ether_ioctl may 2146 * call cxgb_init) we may deadlock if the state is already marked busy. 2147 * 2148 * XXX: this probably opens a small race window with kldunload... 2149 */ 2150 cxgb_end_op(p); 2151 2152 /* The IS_DOOMED check is racy, we're clutching at straws here */ 2153 if (handle_unsynchronized && !IS_DOOMED(p)) { 2154 if (command == SIOCSIFMEDIA || command == SIOCGIFMEDIA) 2155 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 2156 else 2157 error = ether_ioctl(ifp, command, data); 2158 } 2159 2160 return (error); 2161} 2162 2163static int 2164cxgb_media_change(struct ifnet *ifp) 2165{ 2166 return (EOPNOTSUPP); 2167} 2168 2169/* 2170 * Translates phy->modtype to the correct Ethernet media subtype. 2171 */ 2172static int 2173cxgb_ifm_type(int mod) 2174{ 2175 switch (mod) { 2176 case phy_modtype_sr: 2177 return (IFM_10G_SR); 2178 case phy_modtype_lr: 2179 return (IFM_10G_LR); 2180 case phy_modtype_lrm: 2181 return (IFM_10G_LRM); 2182 case phy_modtype_twinax: 2183 return (IFM_10G_TWINAX); 2184 case phy_modtype_twinax_long: 2185 return (IFM_10G_TWINAX_LONG); 2186 case phy_modtype_none: 2187 return (IFM_NONE); 2188 case phy_modtype_unknown: 2189 return (IFM_UNKNOWN); 2190 } 2191 2192 KASSERT(0, ("%s: modtype %d unknown", __func__, mod)); 2193 return (IFM_UNKNOWN); 2194} 2195 2196/* 2197 * Rebuilds the ifmedia list for this port, and sets the current media. 2198 */ 2199static void 2200cxgb_build_medialist(struct port_info *p) 2201{ 2202 struct cphy *phy = &p->phy; 2203 struct ifmedia *media = &p->media; 2204 int mod = phy->modtype; 2205 int m = IFM_ETHER | IFM_FDX; 2206 2207 PORT_LOCK(p); 2208 2209 ifmedia_removeall(media); 2210 if (phy->caps & SUPPORTED_TP && phy->caps & SUPPORTED_Autoneg) { 2211 /* Copper (RJ45) */ 2212 2213 if (phy->caps & SUPPORTED_10000baseT_Full) 2214 ifmedia_add(media, m | IFM_10G_T, mod, NULL); 2215 2216 if (phy->caps & SUPPORTED_1000baseT_Full) 2217 ifmedia_add(media, m | IFM_1000_T, mod, NULL); 2218 2219 if (phy->caps & SUPPORTED_100baseT_Full) 2220 ifmedia_add(media, m | IFM_100_TX, mod, NULL); 2221 2222 if (phy->caps & SUPPORTED_10baseT_Full) 2223 ifmedia_add(media, m | IFM_10_T, mod, NULL); 2224 2225 ifmedia_add(media, IFM_ETHER | IFM_AUTO, mod, NULL); 2226 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 2227 2228 } else if (phy->caps & SUPPORTED_TP) { 2229 /* Copper (CX4) */ 2230 2231 KASSERT(phy->caps & SUPPORTED_10000baseT_Full, 2232 ("%s: unexpected cap 0x%x", __func__, phy->caps)); 2233 2234 ifmedia_add(media, m | IFM_10G_CX4, mod, NULL); 2235 ifmedia_set(media, m | IFM_10G_CX4); 2236 2237 } else if (phy->caps & SUPPORTED_FIBRE && 2238 phy->caps & SUPPORTED_10000baseT_Full) { 2239 /* 10G optical (but includes SFP+ twinax) */ 2240 2241 m |= cxgb_ifm_type(mod); 2242 if (IFM_SUBTYPE(m) == IFM_NONE) 2243 m &= ~IFM_FDX; 2244 2245 ifmedia_add(media, m, mod, NULL); 2246 ifmedia_set(media, m); 2247 2248 } else if (phy->caps & SUPPORTED_FIBRE && 2249 phy->caps & SUPPORTED_1000baseT_Full) { 2250 /* 1G optical */ 2251 2252 /* XXX: Lie and claim to be SX, could actually be any 1G-X */ 2253 ifmedia_add(media, m | IFM_1000_SX, mod, NULL); 2254 ifmedia_set(media, m | IFM_1000_SX); 2255 2256 } else { 2257 KASSERT(0, ("%s: don't know how to handle 0x%x.", __func__, 2258 phy->caps)); 2259 } 2260 2261 PORT_UNLOCK(p); 2262} 2263 2264static void 2265cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2266{ 2267 struct port_info *p = ifp->if_softc; 2268 struct ifmedia_entry *cur = p->media.ifm_cur; 2269 int speed = p->link_config.speed; 2270 2271 if (cur->ifm_data != p->phy.modtype) { 2272 cxgb_build_medialist(p); 2273 cur = p->media.ifm_cur; 2274 } 2275 2276 ifmr->ifm_status = IFM_AVALID; 2277 if (!p->link_config.link_ok) 2278 return; 2279 2280 ifmr->ifm_status |= IFM_ACTIVE; 2281 2282 /* 2283 * active and current will differ iff current media is autoselect. That 2284 * can happen only for copper RJ45. 2285 */ 2286 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2287 return; 2288 KASSERT(p->phy.caps & SUPPORTED_TP && p->phy.caps & SUPPORTED_Autoneg, 2289 ("%s: unexpected PHY caps 0x%x", __func__, p->phy.caps)); 2290 2291 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2292 if (speed == SPEED_10000) 2293 ifmr->ifm_active |= IFM_10G_T; 2294 else if (speed == SPEED_1000) 2295 ifmr->ifm_active |= IFM_1000_T; 2296 else if (speed == SPEED_100) 2297 ifmr->ifm_active |= IFM_100_TX; 2298 else if (speed == SPEED_10) 2299 ifmr->ifm_active |= IFM_10_T; 2300 else 2301 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 2302 speed)); 2303} 2304 2305static void 2306cxgb_async_intr(void *data) 2307{ 2308 adapter_t *sc = data; 2309 2310 if (cxgb_debug) 2311 device_printf(sc->dev, "cxgb_async_intr\n"); 2312 /* 2313 * May need to sleep - defer to taskqueue 2314 */ 2315 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2316} 2317 2318static void 2319cxgb_ext_intr_handler(void *arg, int count) 2320{ 2321 adapter_t *sc = (adapter_t *)arg; 2322 2323 if (cxgb_debug) 2324 printf("cxgb_ext_intr_handler\n"); 2325 2326 t3_phy_intr_handler(sc); 2327 2328 /* Now reenable external interrupts */ 2329 ADAPTER_LOCK(sc); 2330 if (sc->slow_intr_mask) { 2331 sc->slow_intr_mask |= F_T3DBG; 2332 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2333 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2334 } 2335 ADAPTER_UNLOCK(sc); 2336} 2337 2338static void 2339check_link_status(adapter_t *sc) 2340{ 2341 int i; 2342 2343 for (i = 0; i < (sc)->params.nports; ++i) { 2344 struct port_info *p = &sc->port[i]; 2345 2346 if (!isset(&sc->open_device_map, p->port_id)) 2347 continue; 2348 2349 if (p->link_fault || !(p->phy.caps & SUPPORTED_IRQ)) 2350 t3_link_changed(sc, i); 2351 } 2352} 2353 2354static void 2355check_t3b2_mac(struct adapter *sc) 2356{ 2357 int i; 2358 2359 if (sc->flags & CXGB_SHUTDOWN) 2360 return; 2361 2362 for_each_port(sc, i) { 2363 struct port_info *p = &sc->port[i]; 2364 int status; 2365#ifdef INVARIANTS 2366 struct ifnet *ifp = p->ifp; 2367#endif 2368 2369 if (!isset(&sc->open_device_map, p->port_id)) 2370 continue; 2371 2372 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, 2373 ("%s: state mismatch (drv_flags %x, device_map %x)", 2374 __func__, ifp->if_drv_flags, sc->open_device_map)); 2375 2376 PORT_LOCK(p); 2377 status = t3b2_mac_watchdog_task(&p->mac); 2378 if (status == 1) 2379 p->mac.stats.num_toggled++; 2380 else if (status == 2) { 2381 struct cmac *mac = &p->mac; 2382 2383 cxgb_update_mac_settings(p); 2384 t3_link_start(&p->phy, mac, &p->link_config); 2385 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2386 t3_port_intr_enable(sc, p->port_id); 2387 p->mac.stats.num_resets++; 2388 } 2389 PORT_UNLOCK(p); 2390 } 2391} 2392 2393static void 2394cxgb_tick(void *arg) 2395{ 2396 adapter_t *sc = (adapter_t *)arg; 2397 2398 if (sc->flags & CXGB_SHUTDOWN) 2399 return; 2400 2401 taskqueue_enqueue(sc->tq, &sc->tick_task); 2402 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 2403} 2404 2405static void 2406cxgb_tick_handler(void *arg, int count) 2407{ 2408 adapter_t *sc = (adapter_t *)arg; 2409 const struct adapter_params *p = &sc->params; 2410 int i; 2411 uint32_t cause, reset; 2412 2413 if (sc->flags & CXGB_SHUTDOWN || !(sc->flags & FULL_INIT_DONE)) 2414 return; 2415 2416 check_link_status(sc); 2417 sc->check_task_cnt++; 2418 2419 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2420 check_t3b2_mac(sc); 2421 2422 cause = t3_read_reg(sc, A_SG_INT_CAUSE); 2423 reset = 0; 2424 if (cause & F_FLEMPTY) { 2425 struct sge_qset *qs = &sc->sge.qs[0]; 2426 2427 i = 0; 2428 reset |= F_FLEMPTY; 2429 2430 cause = (t3_read_reg(sc, A_SG_RSPQ_FL_STATUS) >> 2431 S_FL0EMPTY) & 0xffff; 2432 while (cause) { 2433 qs->fl[i].empty += (cause & 1); 2434 if (i) 2435 qs++; 2436 i ^= 1; 2437 cause >>= 1; 2438 } 2439 } 2440 t3_write_reg(sc, A_SG_INT_CAUSE, reset); 2441 2442 for (i = 0; i < sc->params.nports; i++) { 2443 struct port_info *pi = &sc->port[i]; 2444 struct ifnet *ifp = pi->ifp; 2445 struct cmac *mac = &pi->mac; 2446 struct mac_stats *mstats = &mac->stats; 2447 2448 if (!isset(&sc->open_device_map, pi->port_id)) 2449 continue; 2450 2451 PORT_LOCK(pi); 2452 t3_mac_update_stats(mac); 2453 PORT_UNLOCK(pi); 2454 2455 ifp->if_opackets = 2456 mstats->tx_frames_64 + 2457 mstats->tx_frames_65_127 + 2458 mstats->tx_frames_128_255 + 2459 mstats->tx_frames_256_511 + 2460 mstats->tx_frames_512_1023 + 2461 mstats->tx_frames_1024_1518 + 2462 mstats->tx_frames_1519_max; 2463 2464 ifp->if_ipackets = 2465 mstats->rx_frames_64 + 2466 mstats->rx_frames_65_127 + 2467 mstats->rx_frames_128_255 + 2468 mstats->rx_frames_256_511 + 2469 mstats->rx_frames_512_1023 + 2470 mstats->rx_frames_1024_1518 + 2471 mstats->rx_frames_1519_max; 2472 2473 ifp->if_obytes = mstats->tx_octets; 2474 ifp->if_ibytes = mstats->rx_octets; 2475 ifp->if_omcasts = mstats->tx_mcast_frames; 2476 ifp->if_imcasts = mstats->rx_mcast_frames; 2477 2478 ifp->if_collisions = 2479 mstats->tx_total_collisions; 2480 2481 ifp->if_iqdrops = mstats->rx_cong_drops; 2482 2483 ifp->if_oerrors = 2484 mstats->tx_excess_collisions + 2485 mstats->tx_underrun + 2486 mstats->tx_len_errs + 2487 mstats->tx_mac_internal_errs + 2488 mstats->tx_excess_deferral + 2489 mstats->tx_fcs_errs; 2490 ifp->if_ierrors = 2491 mstats->rx_jabber + 2492 mstats->rx_data_errs + 2493 mstats->rx_sequence_errs + 2494 mstats->rx_runt + 2495 mstats->rx_too_long + 2496 mstats->rx_mac_internal_errs + 2497 mstats->rx_short + 2498 mstats->rx_fcs_errs; 2499 2500 if (mac->multiport) 2501 continue; 2502 2503 /* Count rx fifo overflows, once per second */ 2504 cause = t3_read_reg(sc, A_XGM_INT_CAUSE + mac->offset); 2505 reset = 0; 2506 if (cause & F_RXFIFO_OVERFLOW) { 2507 mac->stats.rx_fifo_ovfl++; 2508 reset |= F_RXFIFO_OVERFLOW; 2509 } 2510 t3_write_reg(sc, A_XGM_INT_CAUSE + mac->offset, reset); 2511 } 2512} 2513 2514static void 2515touch_bars(device_t dev) 2516{ 2517 /* 2518 * Don't enable yet 2519 */ 2520#if !defined(__LP64__) && 0 2521 u32 v; 2522 2523 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2524 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2525 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2526 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2527 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2528 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2529#endif 2530} 2531 2532static int 2533set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2534{ 2535 uint8_t *buf; 2536 int err = 0; 2537 u32 aligned_offset, aligned_len, *p; 2538 struct adapter *adapter = pi->adapter; 2539 2540 2541 aligned_offset = offset & ~3; 2542 aligned_len = (len + (offset & 3) + 3) & ~3; 2543 2544 if (aligned_offset != offset || aligned_len != len) { 2545 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2546 if (!buf) 2547 return (ENOMEM); 2548 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2549 if (!err && aligned_len > 4) 2550 err = t3_seeprom_read(adapter, 2551 aligned_offset + aligned_len - 4, 2552 (u32 *)&buf[aligned_len - 4]); 2553 if (err) 2554 goto out; 2555 memcpy(buf + (offset & 3), data, len); 2556 } else 2557 buf = (uint8_t *)(uintptr_t)data; 2558 2559 err = t3_seeprom_wp(adapter, 0); 2560 if (err) 2561 goto out; 2562 2563 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2564 err = t3_seeprom_write(adapter, aligned_offset, *p); 2565 aligned_offset += 4; 2566 } 2567 2568 if (!err) 2569 err = t3_seeprom_wp(adapter, 1); 2570out: 2571 if (buf != data) 2572 free(buf, M_DEVBUF); 2573 return err; 2574} 2575 2576 2577static int 2578in_range(int val, int lo, int hi) 2579{ 2580 return val < 0 || (val <= hi && val >= lo); 2581} 2582 2583static int 2584cxgb_extension_open(struct cdev *dev, int flags, int fmp, struct thread *td) 2585{ 2586 return (0); 2587} 2588 2589static int 2590cxgb_extension_close(struct cdev *dev, int flags, int fmt, struct thread *td) 2591{ 2592 return (0); 2593} 2594 2595static int 2596cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2597 int fflag, struct thread *td) 2598{ 2599 int mmd, error = 0; 2600 struct port_info *pi = dev->si_drv1; 2601 adapter_t *sc = pi->adapter; 2602 2603#ifdef PRIV_SUPPORTED 2604 if (priv_check(td, PRIV_DRIVER)) { 2605 if (cxgb_debug) 2606 printf("user does not have access to privileged ioctls\n"); 2607 return (EPERM); 2608 } 2609#else 2610 if (suser(td)) { 2611 if (cxgb_debug) 2612 printf("user does not have access to privileged ioctls\n"); 2613 return (EPERM); 2614 } 2615#endif 2616 2617 switch (cmd) { 2618 case CHELSIO_GET_MIIREG: { 2619 uint32_t val; 2620 struct cphy *phy = &pi->phy; 2621 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2622 2623 if (!phy->mdio_read) 2624 return (EOPNOTSUPP); 2625 if (is_10G(sc)) { 2626 mmd = mid->phy_id >> 8; 2627 if (!mmd) 2628 mmd = MDIO_DEV_PCS; 2629 else if (mmd > MDIO_DEV_VEND2) 2630 return (EINVAL); 2631 2632 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2633 mid->reg_num, &val); 2634 } else 2635 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2636 mid->reg_num & 0x1f, &val); 2637 if (error == 0) 2638 mid->val_out = val; 2639 break; 2640 } 2641 case CHELSIO_SET_MIIREG: { 2642 struct cphy *phy = &pi->phy; 2643 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2644 2645 if (!phy->mdio_write) 2646 return (EOPNOTSUPP); 2647 if (is_10G(sc)) { 2648 mmd = mid->phy_id >> 8; 2649 if (!mmd) 2650 mmd = MDIO_DEV_PCS; 2651 else if (mmd > MDIO_DEV_VEND2) 2652 return (EINVAL); 2653 2654 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2655 mmd, mid->reg_num, mid->val_in); 2656 } else 2657 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2658 mid->reg_num & 0x1f, 2659 mid->val_in); 2660 break; 2661 } 2662 case CHELSIO_SETREG: { 2663 struct ch_reg *edata = (struct ch_reg *)data; 2664 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2665 return (EFAULT); 2666 t3_write_reg(sc, edata->addr, edata->val); 2667 break; 2668 } 2669 case CHELSIO_GETREG: { 2670 struct ch_reg *edata = (struct ch_reg *)data; 2671 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2672 return (EFAULT); 2673 edata->val = t3_read_reg(sc, edata->addr); 2674 break; 2675 } 2676 case CHELSIO_GET_SGE_CONTEXT: { 2677 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2678 mtx_lock_spin(&sc->sge.reg_lock); 2679 switch (ecntxt->cntxt_type) { 2680 case CNTXT_TYPE_EGRESS: 2681 error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2682 ecntxt->data); 2683 break; 2684 case CNTXT_TYPE_FL: 2685 error = -t3_sge_read_fl(sc, ecntxt->cntxt_id, 2686 ecntxt->data); 2687 break; 2688 case CNTXT_TYPE_RSP: 2689 error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2690 ecntxt->data); 2691 break; 2692 case CNTXT_TYPE_CQ: 2693 error = -t3_sge_read_cq(sc, ecntxt->cntxt_id, 2694 ecntxt->data); 2695 break; 2696 default: 2697 error = EINVAL; 2698 break; 2699 } 2700 mtx_unlock_spin(&sc->sge.reg_lock); 2701 break; 2702 } 2703 case CHELSIO_GET_SGE_DESC: { 2704 struct ch_desc *edesc = (struct ch_desc *)data; 2705 int ret; 2706 if (edesc->queue_num >= SGE_QSETS * 6) 2707 return (EINVAL); 2708 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2709 edesc->queue_num % 6, edesc->idx, edesc->data); 2710 if (ret < 0) 2711 return (EINVAL); 2712 edesc->size = ret; 2713 break; 2714 } 2715 case CHELSIO_GET_QSET_PARAMS: { 2716 struct qset_params *q; 2717 struct ch_qset_params *t = (struct ch_qset_params *)data; 2718 int q1 = pi->first_qset; 2719 int nqsets = pi->nqsets; 2720 int i; 2721 2722 if (t->qset_idx >= nqsets) 2723 return EINVAL; 2724 2725 i = q1 + t->qset_idx; 2726 q = &sc->params.sge.qset[i]; 2727 t->rspq_size = q->rspq_size; 2728 t->txq_size[0] = q->txq_size[0]; 2729 t->txq_size[1] = q->txq_size[1]; 2730 t->txq_size[2] = q->txq_size[2]; 2731 t->fl_size[0] = q->fl_size; 2732 t->fl_size[1] = q->jumbo_size; 2733 t->polling = q->polling; 2734 t->lro = q->lro; 2735 t->intr_lat = q->coalesce_usecs; 2736 t->cong_thres = q->cong_thres; 2737 t->qnum = i; 2738 2739 if (sc->flags & USING_MSIX) 2740 t->vector = rman_get_start(sc->msix_irq_res[i]); 2741 else 2742 t->vector = rman_get_start(sc->irq_res); 2743 2744 break; 2745 } 2746 case CHELSIO_GET_QSET_NUM: { 2747 struct ch_reg *edata = (struct ch_reg *)data; 2748 edata->val = pi->nqsets; 2749 break; 2750 } 2751 case CHELSIO_LOAD_FW: { 2752 uint8_t *fw_data; 2753 uint32_t vers; 2754 struct ch_mem_range *t = (struct ch_mem_range *)data; 2755 2756 /* 2757 * You're allowed to load a firmware only before FULL_INIT_DONE 2758 * 2759 * FW_UPTODATE is also set so the rest of the initialization 2760 * will not overwrite what was loaded here. This gives you the 2761 * flexibility to load any firmware (and maybe shoot yourself in 2762 * the foot). 2763 */ 2764 2765 ADAPTER_LOCK(sc); 2766 if (sc->open_device_map || sc->flags & FULL_INIT_DONE) { 2767 ADAPTER_UNLOCK(sc); 2768 return (EBUSY); 2769 } 2770 2771 fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2772 if (!fw_data) 2773 error = ENOMEM; 2774 else 2775 error = copyin(t->buf, fw_data, t->len); 2776 2777 if (!error) 2778 error = -t3_load_fw(sc, fw_data, t->len); 2779 2780 if (t3_get_fw_version(sc, &vers) == 0) { 2781 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), 2782 "%d.%d.%d", G_FW_VERSION_MAJOR(vers), 2783 G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); 2784 } 2785 2786 if (!error) 2787 sc->flags |= FW_UPTODATE; 2788 2789 free(fw_data, M_DEVBUF); 2790 ADAPTER_UNLOCK(sc); 2791 break; 2792 } 2793 case CHELSIO_LOAD_BOOT: { 2794 uint8_t *boot_data; 2795 struct ch_mem_range *t = (struct ch_mem_range *)data; 2796 2797 boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2798 if (!boot_data) 2799 return ENOMEM; 2800 2801 error = copyin(t->buf, boot_data, t->len); 2802 if (!error) 2803 error = -t3_load_boot(sc, boot_data, t->len); 2804 2805 free(boot_data, M_DEVBUF); 2806 break; 2807 } 2808 case CHELSIO_GET_PM: { 2809 struct ch_pm *m = (struct ch_pm *)data; 2810 struct tp_params *p = &sc->params.tp; 2811 2812 if (!is_offload(sc)) 2813 return (EOPNOTSUPP); 2814 2815 m->tx_pg_sz = p->tx_pg_size; 2816 m->tx_num_pg = p->tx_num_pgs; 2817 m->rx_pg_sz = p->rx_pg_size; 2818 m->rx_num_pg = p->rx_num_pgs; 2819 m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; 2820 2821 break; 2822 } 2823 case CHELSIO_SET_PM: { 2824 struct ch_pm *m = (struct ch_pm *)data; 2825 struct tp_params *p = &sc->params.tp; 2826 2827 if (!is_offload(sc)) 2828 return (EOPNOTSUPP); 2829 if (sc->flags & FULL_INIT_DONE) 2830 return (EBUSY); 2831 2832 if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) || 2833 !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1))) 2834 return (EINVAL); /* not power of 2 */ 2835 if (!(m->rx_pg_sz & 0x14000)) 2836 return (EINVAL); /* not 16KB or 64KB */ 2837 if (!(m->tx_pg_sz & 0x1554000)) 2838 return (EINVAL); 2839 if (m->tx_num_pg == -1) 2840 m->tx_num_pg = p->tx_num_pgs; 2841 if (m->rx_num_pg == -1) 2842 m->rx_num_pg = p->rx_num_pgs; 2843 if (m->tx_num_pg % 24 || m->rx_num_pg % 24) 2844 return (EINVAL); 2845 if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size || 2846 m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size) 2847 return (EINVAL); 2848 2849 p->rx_pg_size = m->rx_pg_sz; 2850 p->tx_pg_size = m->tx_pg_sz; 2851 p->rx_num_pgs = m->rx_num_pg; 2852 p->tx_num_pgs = m->tx_num_pg; 2853 break; 2854 } 2855 case CHELSIO_SETMTUTAB: { 2856 struct ch_mtus *m = (struct ch_mtus *)data; 2857 int i; 2858 2859 if (!is_offload(sc)) 2860 return (EOPNOTSUPP); 2861 if (offload_running(sc)) 2862 return (EBUSY); 2863 if (m->nmtus != NMTUS) 2864 return (EINVAL); 2865 if (m->mtus[0] < 81) /* accommodate SACK */ 2866 return (EINVAL); 2867 2868 /* 2869 * MTUs must be in ascending order 2870 */ 2871 for (i = 1; i < NMTUS; ++i) 2872 if (m->mtus[i] < m->mtus[i - 1]) 2873 return (EINVAL); 2874 2875 memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus)); 2876 break; 2877 } 2878 case CHELSIO_GETMTUTAB: { 2879 struct ch_mtus *m = (struct ch_mtus *)data; 2880 2881 if (!is_offload(sc)) 2882 return (EOPNOTSUPP); 2883 2884 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2885 m->nmtus = NMTUS; 2886 break; 2887 } 2888 case CHELSIO_GET_MEM: { 2889 struct ch_mem_range *t = (struct ch_mem_range *)data; 2890 struct mc7 *mem; 2891 uint8_t *useraddr; 2892 u64 buf[32]; 2893 2894 /* 2895 * Use these to avoid modifying len/addr in the the return 2896 * struct 2897 */ 2898 uint32_t len = t->len, addr = t->addr; 2899 2900 if (!is_offload(sc)) 2901 return (EOPNOTSUPP); 2902 if (!(sc->flags & FULL_INIT_DONE)) 2903 return (EIO); /* need the memory controllers */ 2904 if ((addr & 0x7) || (len & 0x7)) 2905 return (EINVAL); 2906 if (t->mem_id == MEM_CM) 2907 mem = &sc->cm; 2908 else if (t->mem_id == MEM_PMRX) 2909 mem = &sc->pmrx; 2910 else if (t->mem_id == MEM_PMTX) 2911 mem = &sc->pmtx; 2912 else 2913 return (EINVAL); 2914 2915 /* 2916 * Version scheme: 2917 * bits 0..9: chip version 2918 * bits 10..15: chip revision 2919 */ 2920 t->version = 3 | (sc->params.rev << 10); 2921 2922 /* 2923 * Read 256 bytes at a time as len can be large and we don't 2924 * want to use huge intermediate buffers. 2925 */ 2926 useraddr = (uint8_t *)t->buf; 2927 while (len) { 2928 unsigned int chunk = min(len, sizeof(buf)); 2929 2930 error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf); 2931 if (error) 2932 return (-error); 2933 if (copyout(buf, useraddr, chunk)) 2934 return (EFAULT); 2935 useraddr += chunk; 2936 addr += chunk; 2937 len -= chunk; 2938 } 2939 break; 2940 } 2941 case CHELSIO_READ_TCAM_WORD: { 2942 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2943 2944 if (!is_offload(sc)) 2945 return (EOPNOTSUPP); 2946 if (!(sc->flags & FULL_INIT_DONE)) 2947 return (EIO); /* need MC5 */ 2948 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2949 break; 2950 } 2951 case CHELSIO_SET_TRACE_FILTER: { 2952 struct ch_trace *t = (struct ch_trace *)data; 2953 const struct trace_params *tp; 2954 2955 tp = (const struct trace_params *)&t->sip; 2956 if (t->config_tx) 2957 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2958 t->trace_tx); 2959 if (t->config_rx) 2960 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2961 t->trace_rx); 2962 break; 2963 } 2964 case CHELSIO_SET_PKTSCHED: { 2965 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2966 if (sc->open_device_map == 0) 2967 return (EAGAIN); 2968 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2969 p->binding); 2970 break; 2971 } 2972 case CHELSIO_IFCONF_GETREGS: { 2973 struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data; 2974 int reglen = cxgb_get_regs_len(); 2975 uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT); 2976 if (buf == NULL) { 2977 return (ENOMEM); 2978 } 2979 if (regs->len > reglen) 2980 regs->len = reglen; 2981 else if (regs->len < reglen) 2982 error = ENOBUFS; 2983 2984 if (!error) { 2985 cxgb_get_regs(sc, regs, buf); 2986 error = copyout(buf, regs->data, reglen); 2987 } 2988 free(buf, M_DEVBUF); 2989 2990 break; 2991 } 2992 case CHELSIO_SET_HW_SCHED: { 2993 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2994 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2995 2996 if ((sc->flags & FULL_INIT_DONE) == 0) 2997 return (EAGAIN); /* need TP to be initialized */ 2998 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2999 !in_range(t->channel, 0, 1) || 3000 !in_range(t->kbps, 0, 10000000) || 3001 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 3002 !in_range(t->flow_ipg, 0, 3003 dack_ticks_to_usec(sc, 0x7ff))) 3004 return (EINVAL); 3005 3006 if (t->kbps >= 0) { 3007 error = t3_config_sched(sc, t->kbps, t->sched); 3008 if (error < 0) 3009 return (-error); 3010 } 3011 if (t->class_ipg >= 0) 3012 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 3013 if (t->flow_ipg >= 0) { 3014 t->flow_ipg *= 1000; /* us -> ns */ 3015 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 3016 } 3017 if (t->mode >= 0) { 3018 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 3019 3020 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 3021 bit, t->mode ? bit : 0); 3022 } 3023 if (t->channel >= 0) 3024 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 3025 1 << t->sched, t->channel << t->sched); 3026 break; 3027 } 3028 case CHELSIO_GET_EEPROM: { 3029 int i; 3030 struct ch_eeprom *e = (struct ch_eeprom *)data; 3031 uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT); 3032 3033 if (buf == NULL) { 3034 return (ENOMEM); 3035 } 3036 e->magic = EEPROM_MAGIC; 3037 for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4) 3038 error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]); 3039 3040 if (!error) 3041 error = copyout(buf + e->offset, e->data, e->len); 3042 3043 free(buf, M_DEVBUF); 3044 break; 3045 } 3046 case CHELSIO_CLEAR_STATS: { 3047 if (!(sc->flags & FULL_INIT_DONE)) 3048 return EAGAIN; 3049 3050 PORT_LOCK(pi); 3051 t3_mac_update_stats(&pi->mac); 3052 memset(&pi->mac.stats, 0, sizeof(pi->mac.stats)); 3053 PORT_UNLOCK(pi); 3054 break; 3055 } 3056 case CHELSIO_GET_UP_LA: { 3057 struct ch_up_la *la = (struct ch_up_la *)data; 3058 uint8_t *buf = malloc(LA_BUFSIZE, M_DEVBUF, M_NOWAIT); 3059 if (buf == NULL) { 3060 return (ENOMEM); 3061 } 3062 if (la->bufsize < LA_BUFSIZE) 3063 error = ENOBUFS; 3064 3065 if (!error) 3066 error = -t3_get_up_la(sc, &la->stopped, &la->idx, 3067 &la->bufsize, buf); 3068 if (!error) 3069 error = copyout(buf, la->data, la->bufsize); 3070 3071 free(buf, M_DEVBUF); 3072 break; 3073 } 3074 case CHELSIO_GET_UP_IOQS: { 3075 struct ch_up_ioqs *ioqs = (struct ch_up_ioqs *)data; 3076 uint8_t *buf = malloc(IOQS_BUFSIZE, M_DEVBUF, M_NOWAIT); 3077 uint32_t *v; 3078 3079 if (buf == NULL) { 3080 return (ENOMEM); 3081 } 3082 if (ioqs->bufsize < IOQS_BUFSIZE) 3083 error = ENOBUFS; 3084 3085 if (!error) 3086 error = -t3_get_up_ioqs(sc, &ioqs->bufsize, buf); 3087 3088 if (!error) { 3089 v = (uint32_t *)buf; 3090 3091 ioqs->bufsize -= 4 * sizeof(uint32_t); 3092 ioqs->ioq_rx_enable = *v++; 3093 ioqs->ioq_tx_enable = *v++; 3094 ioqs->ioq_rx_status = *v++; 3095 ioqs->ioq_tx_status = *v++; 3096 3097 error = copyout(v, ioqs->data, ioqs->bufsize); 3098 } 3099 3100 free(buf, M_DEVBUF); 3101 break; 3102 } 3103 default: 3104 return (EOPNOTSUPP); 3105 break; 3106 } 3107 3108 return (error); 3109} 3110 3111static __inline void 3112reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 3113 unsigned int end) 3114{ 3115 uint32_t *p = (uint32_t *)(buf + start); 3116 3117 for ( ; start <= end; start += sizeof(uint32_t)) 3118 *p++ = t3_read_reg(ap, start); 3119} 3120 3121#define T3_REGMAP_SIZE (3 * 1024) 3122static int 3123cxgb_get_regs_len(void) 3124{ 3125 return T3_REGMAP_SIZE; 3126} 3127 3128static void 3129cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf) 3130{ 3131 3132 /* 3133 * Version scheme: 3134 * bits 0..9: chip version 3135 * bits 10..15: chip revision 3136 * bit 31: set for PCIe cards 3137 */ 3138 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 3139 3140 /* 3141 * We skip the MAC statistics registers because they are clear-on-read. 3142 * Also reading multi-register stats would need to synchronize with the 3143 * periodic mac stats accumulation. Hard to justify the complexity. 3144 */ 3145 memset(buf, 0, cxgb_get_regs_len()); 3146 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 3147 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 3148 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 3149 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 3150 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 3151 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 3152 XGM_REG(A_XGM_SERDES_STAT3, 1)); 3153 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 3154 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 3155} 3156 3157 3158MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 3159