cxgb_main.c revision 185655
1/************************************************************************** 2 3Copyright (c) 2007-2008, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28***************************************************************************/ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_main.c 185655 2008-12-05 21:40:11Z gnn $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/module.h> 38#include <sys/pciio.h> 39#include <sys/conf.h> 40#include <machine/bus.h> 41#include <machine/resource.h> 42#include <sys/bus_dma.h> 43#include <sys/ktr.h> 44#include <sys/rman.h> 45#include <sys/ioccom.h> 46#include <sys/mbuf.h> 47#include <sys/linker.h> 48#include <sys/firmware.h> 49#include <sys/socket.h> 50#include <sys/sockio.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <sys/syslog.h> 54#include <sys/queue.h> 55#include <sys/taskqueue.h> 56#include <sys/proc.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64#include <net/if_types.h> 65#include <net/if_vlan_var.h> 66 67#include <netinet/in_systm.h> 68#include <netinet/in.h> 69#include <netinet/if_ether.h> 70#include <netinet/ip.h> 71#include <netinet/ip.h> 72#include <netinet/tcp.h> 73#include <netinet/udp.h> 74 75#include <dev/pci/pcireg.h> 76#include <dev/pci/pcivar.h> 77#include <dev/pci/pci_private.h> 78 79#include <cxgb_include.h> 80 81#ifdef PRIV_SUPPORTED 82#include <sys/priv.h> 83#endif 84 85static int cxgb_setup_msix(adapter_t *, int); 86static void cxgb_teardown_msix(adapter_t *); 87static void cxgb_init(void *); 88static void cxgb_init_locked(struct port_info *); 89static void cxgb_stop_locked(struct port_info *); 90static void cxgb_set_rxmode(struct port_info *); 91static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 92static int cxgb_media_change(struct ifnet *); 93static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 94static int setup_sge_qsets(adapter_t *); 95static void cxgb_async_intr(void *); 96static void cxgb_ext_intr_handler(void *, int); 97static void cxgb_tick_handler(void *, int); 98static void cxgb_down_locked(struct adapter *sc); 99static void cxgb_tick(void *); 100static void setup_rss(adapter_t *sc); 101 102/* Attachment glue for the PCI controller end of the device. Each port of 103 * the device is attached separately, as defined later. 104 */ 105static int cxgb_controller_probe(device_t); 106static int cxgb_controller_attach(device_t); 107static int cxgb_controller_detach(device_t); 108static void cxgb_free(struct adapter *); 109static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 110 unsigned int end); 111static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf); 112static int cxgb_get_regs_len(void); 113static int offload_open(struct port_info *pi); 114static void touch_bars(device_t dev); 115static int offload_close(struct t3cdev *tdev); 116static void cxgb_link_start(struct port_info *p); 117 118static device_method_t cxgb_controller_methods[] = { 119 DEVMETHOD(device_probe, cxgb_controller_probe), 120 DEVMETHOD(device_attach, cxgb_controller_attach), 121 DEVMETHOD(device_detach, cxgb_controller_detach), 122 123 /* bus interface */ 124 DEVMETHOD(bus_print_child, bus_generic_print_child), 125 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 126 127 { 0, 0 } 128}; 129 130static driver_t cxgb_controller_driver = { 131 "cxgbc", 132 cxgb_controller_methods, 133 sizeof(struct adapter) 134}; 135 136static devclass_t cxgb_controller_devclass; 137DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 138 139/* 140 * Attachment glue for the ports. Attachment is done directly to the 141 * controller device. 142 */ 143static int cxgb_port_probe(device_t); 144static int cxgb_port_attach(device_t); 145static int cxgb_port_detach(device_t); 146 147static device_method_t cxgb_port_methods[] = { 148 DEVMETHOD(device_probe, cxgb_port_probe), 149 DEVMETHOD(device_attach, cxgb_port_attach), 150 DEVMETHOD(device_detach, cxgb_port_detach), 151 { 0, 0 } 152}; 153 154static driver_t cxgb_port_driver = { 155 "cxgb", 156 cxgb_port_methods, 157 0 158}; 159 160static d_ioctl_t cxgb_extension_ioctl; 161static d_open_t cxgb_extension_open; 162static d_close_t cxgb_extension_close; 163 164static struct cdevsw cxgb_cdevsw = { 165 .d_version = D_VERSION, 166 .d_flags = 0, 167 .d_open = cxgb_extension_open, 168 .d_close = cxgb_extension_close, 169 .d_ioctl = cxgb_extension_ioctl, 170 .d_name = "cxgb", 171}; 172 173static devclass_t cxgb_port_devclass; 174DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 175 176#define SGE_MSIX_COUNT (SGE_QSETS + 1) 177 178/* 179 * The driver uses the best interrupt scheme available on a platform in the 180 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 181 * of these schemes the driver may consider as follows: 182 * 183 * msi = 2: choose from among all three options 184 * msi = 1 : only consider MSI and pin interrupts 185 * msi = 0: force pin interrupts 186 */ 187static int msi_allowed = 2; 188 189TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 190SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 191SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 192 "MSI-X, MSI, INTx selector"); 193 194/* 195 * The driver enables offload as a default. 196 * To disable it, use ofld_disable = 1. 197 */ 198static int ofld_disable = 0; 199TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 200SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 201 "disable ULP offload"); 202 203/* 204 * The driver uses an auto-queue algorithm by default. 205 * To disable it and force a single queue-set per port, use multiq = 0 206 */ 207static int multiq = 1; 208TUNABLE_INT("hw.cxgb.multiq", &multiq); 209SYSCTL_UINT(_hw_cxgb, OID_AUTO, multiq, CTLFLAG_RDTUN, &multiq, 0, 210 "use min(ncpus/ports, 8) queue-sets per port"); 211 212/* 213 * By default the driver will not update the firmware unless 214 * it was compiled against a newer version 215 * 216 */ 217static int force_fw_update = 0; 218TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 219SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 220 "update firmware even if up to date"); 221 222int cxgb_use_16k_clusters = 1; 223TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 224SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 225 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 226 227enum { 228 MAX_TXQ_ENTRIES = 16384, 229 MAX_CTRL_TXQ_ENTRIES = 1024, 230 MAX_RSPQ_ENTRIES = 16384, 231 MAX_RX_BUFFERS = 16384, 232 MAX_RX_JUMBO_BUFFERS = 16384, 233 MIN_TXQ_ENTRIES = 4, 234 MIN_CTRL_TXQ_ENTRIES = 4, 235 MIN_RSPQ_ENTRIES = 32, 236 MIN_FL_ENTRIES = 32, 237 MIN_FL_JUMBO_ENTRIES = 32 238}; 239 240struct filter_info { 241 u32 sip; 242 u32 sip_mask; 243 u32 dip; 244 u16 sport; 245 u16 dport; 246 u32 vlan:12; 247 u32 vlan_prio:3; 248 u32 mac_hit:1; 249 u32 mac_idx:4; 250 u32 mac_vld:1; 251 u32 pkt_type:2; 252 u32 report_filter_id:1; 253 u32 pass:1; 254 u32 rss:1; 255 u32 qset:3; 256 u32 locked:1; 257 u32 valid:1; 258}; 259 260enum { FILTER_NO_VLAN_PRI = 7 }; 261 262#define EEPROM_MAGIC 0x38E2F10C 263 264#define PORT_MASK ((1 << MAX_NPORTS) - 1) 265 266/* Table for probing the cards. The desc field isn't actually used */ 267struct cxgb_ident { 268 uint16_t vendor; 269 uint16_t device; 270 int index; 271 char *desc; 272} cxgb_identifiers[] = { 273 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 274 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 275 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 276 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 277 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 278 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 279 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 280 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 281 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 282 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 283 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 284 {0, 0, 0, NULL} 285}; 286 287static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 288 289 290static __inline char 291t3rev2char(struct adapter *adapter) 292{ 293 char rev = 'z'; 294 295 switch(adapter->params.rev) { 296 case T3_REV_A: 297 rev = 'a'; 298 break; 299 case T3_REV_B: 300 case T3_REV_B2: 301 rev = 'b'; 302 break; 303 case T3_REV_C: 304 rev = 'c'; 305 break; 306 } 307 return rev; 308} 309 310static struct cxgb_ident * 311cxgb_get_ident(device_t dev) 312{ 313 struct cxgb_ident *id; 314 315 for (id = cxgb_identifiers; id->desc != NULL; id++) { 316 if ((id->vendor == pci_get_vendor(dev)) && 317 (id->device == pci_get_device(dev))) { 318 return (id); 319 } 320 } 321 return (NULL); 322} 323 324static const struct adapter_info * 325cxgb_get_adapter_info(device_t dev) 326{ 327 struct cxgb_ident *id; 328 const struct adapter_info *ai; 329 330 id = cxgb_get_ident(dev); 331 if (id == NULL) 332 return (NULL); 333 334 ai = t3_get_adapter_info(id->index); 335 336 return (ai); 337} 338 339static int 340cxgb_controller_probe(device_t dev) 341{ 342 const struct adapter_info *ai; 343 char *ports, buf[80]; 344 int nports; 345 struct adapter *sc = device_get_softc(dev); 346 347 ai = cxgb_get_adapter_info(dev); 348 if (ai == NULL) 349 return (ENXIO); 350 351 nports = ai->nports0 + ai->nports1; 352 if (nports == 1) 353 ports = "port"; 354 else 355 ports = "ports"; 356 357 snprintf(buf, sizeof(buf), "%s %sNIC, rev: %d nports: %d %s", 358 ai->desc, is_offload(sc) ? "R" : "", 359 sc->params.rev, nports, ports); 360 device_set_desc_copy(dev, buf); 361 return (BUS_PROBE_DEFAULT); 362} 363 364#define FW_FNAME "cxgb_t3fw" 365#define TPEEPROM_NAME "t3b_tp_eeprom" 366#define TPSRAM_NAME "t3b_protocol_sram" 367 368static int 369upgrade_fw(adapter_t *sc) 370{ 371#ifdef FIRMWARE_LATEST 372 const struct firmware *fw; 373#else 374 struct firmware *fw; 375#endif 376 int status; 377 378 if ((fw = firmware_get(FW_FNAME)) == NULL) { 379 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 380 return (ENOENT); 381 } else 382 device_printf(sc->dev, "updating firmware on card\n"); 383 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 384 385 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 386 387 firmware_put(fw, FIRMWARE_UNLOAD); 388 389 return (status); 390} 391 392static int 393cxgb_controller_attach(device_t dev) 394{ 395 device_t child; 396 const struct adapter_info *ai; 397 struct adapter *sc; 398 int i, error = 0; 399 uint32_t vers; 400 int port_qsets = 1; 401#ifdef MSI_SUPPORTED 402 int msi_needed, reg; 403#endif 404 int must_load = 0; 405 char buf[80]; 406 407 sc = device_get_softc(dev); 408 sc->dev = dev; 409 sc->msi_count = 0; 410 ai = cxgb_get_adapter_info(dev); 411 412 /* 413 * XXX not really related but a recent addition 414 */ 415#ifdef MSI_SUPPORTED 416 /* find the PCIe link width and set max read request to 4KB*/ 417 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 418 uint16_t lnk, pectl; 419 lnk = pci_read_config(dev, reg + 0x12, 2); 420 sc->link_width = (lnk >> 4) & 0x3f; 421 422 pectl = pci_read_config(dev, reg + 0x8, 2); 423 pectl = (pectl & ~0x7000) | (5 << 12); 424 pci_write_config(dev, reg + 0x8, pectl, 2); 425 } 426 427 if (sc->link_width != 0 && sc->link_width <= 4 && 428 (ai->nports0 + ai->nports1) <= 2) { 429 device_printf(sc->dev, 430 "PCIe x%d Link, expect reduced performance\n", 431 sc->link_width); 432 } 433#endif 434 touch_bars(dev); 435 pci_enable_busmaster(dev); 436 /* 437 * Allocate the registers and make them available to the driver. 438 * The registers that we care about for NIC mode are in BAR 0 439 */ 440 sc->regs_rid = PCIR_BAR(0); 441 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 442 &sc->regs_rid, RF_ACTIVE)) == NULL) { 443 device_printf(dev, "Cannot allocate BAR region 0\n"); 444 return (ENXIO); 445 } 446 sc->udbs_rid = PCIR_BAR(2); 447 if ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 448 &sc->udbs_rid, RF_ACTIVE)) == NULL) { 449 device_printf(dev, "Cannot allocate BAR region 1\n"); 450 error = ENXIO; 451 goto out; 452 } 453 454 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 455 device_get_unit(dev)); 456 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 457 458 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 459 device_get_unit(dev)); 460 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 461 device_get_unit(dev)); 462 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 463 device_get_unit(dev)); 464 465 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 466 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 467 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 468 469 sc->bt = rman_get_bustag(sc->regs_res); 470 sc->bh = rman_get_bushandle(sc->regs_res); 471 sc->mmio_len = rman_get_size(sc->regs_res); 472 473 if (t3_prep_adapter(sc, ai, 1) < 0) { 474 printf("prep adapter failed\n"); 475 error = ENODEV; 476 goto out; 477 } 478 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 479 * enough messages for the queue sets. If that fails, try falling 480 * back to MSI. If that fails, then try falling back to the legacy 481 * interrupt pin model. 482 */ 483#ifdef MSI_SUPPORTED 484 485 sc->msix_regs_rid = 0x20; 486 if ((msi_allowed >= 2) && 487 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 488 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 489 490 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 491 492 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 493 (sc->msi_count != msi_needed)) { 494 device_printf(dev, "msix allocation failed - msi_count = %d" 495 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 496 msi_needed, error); 497 sc->msi_count = 0; 498 pci_release_msi(dev); 499 bus_release_resource(dev, SYS_RES_MEMORY, 500 sc->msix_regs_rid, sc->msix_regs_res); 501 sc->msix_regs_res = NULL; 502 } else { 503 sc->flags |= USING_MSIX; 504 sc->cxgb_intr = t3_intr_msix; 505 } 506 } 507 508 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 509 sc->msi_count = 1; 510 if (pci_alloc_msi(dev, &sc->msi_count)) { 511 device_printf(dev, "alloc msi failed - will try INTx\n"); 512 sc->msi_count = 0; 513 pci_release_msi(dev); 514 } else { 515 sc->flags |= USING_MSI; 516 sc->irq_rid = 1; 517 sc->cxgb_intr = t3_intr_msi; 518 } 519 } 520#endif 521 if (sc->msi_count == 0) { 522 device_printf(dev, "using line interrupts\n"); 523 sc->irq_rid = 0; 524 sc->cxgb_intr = t3b_intr; 525 } 526 527 if ((sc->flags & USING_MSIX) && multiq) 528 port_qsets = min((SGE_QSETS/(sc)->params.nports), mp_ncpus); 529 530 /* Create a private taskqueue thread for handling driver events */ 531#ifdef TASKQUEUE_CURRENT 532 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 533 taskqueue_thread_enqueue, &sc->tq); 534#else 535 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 536 taskqueue_thread_enqueue, &sc->tq); 537#endif 538 if (sc->tq == NULL) { 539 device_printf(dev, "failed to allocate controller task queue\n"); 540 goto out; 541 } 542 543 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 544 device_get_nameunit(dev)); 545 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 546 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 547 548 549 /* Create a periodic callout for checking adapter status */ 550 callout_init(&sc->cxgb_tick_ch, TRUE); 551 552 if ((t3_check_fw_version(sc, &must_load) != 0 && must_load) || force_fw_update) { 553 /* 554 * Warn user that a firmware update will be attempted in init. 555 */ 556 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 557 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 558 sc->flags &= ~FW_UPTODATE; 559 } else { 560 sc->flags |= FW_UPTODATE; 561 } 562 563 if (t3_check_tpsram_version(sc, &must_load) != 0 && must_load) { 564 /* 565 * Warn user that a firmware update will be attempted in init. 566 */ 567 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 568 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 569 sc->flags &= ~TPS_UPTODATE; 570 } else { 571 sc->flags |= TPS_UPTODATE; 572 } 573 574 /* 575 * Create a child device for each MAC. The ethernet attachment 576 * will be done in these children. 577 */ 578 for (i = 0; i < (sc)->params.nports; i++) { 579 struct port_info *pi; 580 581 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 582 device_printf(dev, "failed to add child port\n"); 583 error = EINVAL; 584 goto out; 585 } 586 pi = &sc->port[i]; 587 pi->adapter = sc; 588 pi->nqsets = port_qsets; 589 pi->first_qset = i*port_qsets; 590 pi->port_id = i; 591 pi->tx_chan = i >= ai->nports0; 592 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 593 sc->rxpkt_map[pi->txpkt_intf] = i; 594 sc->port[i].tx_chan = i >= ai->nports0; 595 sc->portdev[i] = child; 596 device_set_softc(child, pi); 597 } 598 if ((error = bus_generic_attach(dev)) != 0) 599 goto out; 600 601 /* initialize sge private state */ 602 t3_sge_init_adapter(sc); 603 604 t3_led_ready(sc); 605 606 cxgb_offload_init(); 607 if (is_offload(sc)) { 608 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 609 cxgb_adapter_ofld(sc); 610 } 611 error = t3_get_fw_version(sc, &vers); 612 if (error) 613 goto out; 614 615 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 616 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 617 G_FW_VERSION_MICRO(vers)); 618 619 snprintf(buf, sizeof(buf), "%s\t E/C: %s S/N: %s", 620 ai->desc, 621 sc->params.vpd.ec, sc->params.vpd.sn); 622 device_set_desc_copy(dev, buf); 623 624 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 625 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 626 t3_add_attach_sysctls(sc); 627out: 628 if (error) 629 cxgb_free(sc); 630 631 return (error); 632} 633 634static int 635cxgb_controller_detach(device_t dev) 636{ 637 struct adapter *sc; 638 639 sc = device_get_softc(dev); 640 641 cxgb_free(sc); 642 643 return (0); 644} 645 646static void 647cxgb_free(struct adapter *sc) 648{ 649 int i; 650 651 ADAPTER_LOCK(sc); 652 sc->flags |= CXGB_SHUTDOWN; 653 ADAPTER_UNLOCK(sc); 654 cxgb_pcpu_shutdown_threads(sc); 655 ADAPTER_LOCK(sc); 656 657/* 658 * drops the lock 659 */ 660 cxgb_down_locked(sc); 661 662#ifdef MSI_SUPPORTED 663 if (sc->flags & (USING_MSI | USING_MSIX)) { 664 device_printf(sc->dev, "releasing msi message(s)\n"); 665 pci_release_msi(sc->dev); 666 } else { 667 device_printf(sc->dev, "no msi message to release\n"); 668 } 669#endif 670 if (sc->msix_regs_res != NULL) { 671 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 672 sc->msix_regs_res); 673 } 674 675 t3_sge_deinit_sw(sc); 676 /* 677 * Wait for last callout 678 */ 679 680 DELAY(hz*100); 681 682 for (i = 0; i < (sc)->params.nports; ++i) { 683 if (sc->portdev[i] != NULL) 684 device_delete_child(sc->dev, sc->portdev[i]); 685 } 686 687 bus_generic_detach(sc->dev); 688 if (sc->tq != NULL) { 689 taskqueue_free(sc->tq); 690 sc->tq = NULL; 691 } 692 693 if (is_offload(sc)) { 694 cxgb_adapter_unofld(sc); 695 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 696 offload_close(&sc->tdev); 697 else 698 printf("cxgb_free: DEVMAP_BIT not set\n"); 699 } else 700 printf("not offloading set\n"); 701#ifdef notyet 702 if (sc->flags & CXGB_OFLD_INIT) 703 cxgb_offload_deactivate(sc); 704#endif 705 free(sc->filters, M_DEVBUF); 706 t3_sge_free(sc); 707 708 cxgb_offload_exit(); 709 710 if (sc->udbs_res != NULL) 711 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 712 sc->udbs_res); 713 714 if (sc->regs_res != NULL) 715 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 716 sc->regs_res); 717 718 MTX_DESTROY(&sc->mdio_lock); 719 MTX_DESTROY(&sc->sge.reg_lock); 720 MTX_DESTROY(&sc->elmer_lock); 721 ADAPTER_LOCK_DEINIT(sc); 722} 723 724/** 725 * setup_sge_qsets - configure SGE Tx/Rx/response queues 726 * @sc: the controller softc 727 * 728 * Determines how many sets of SGE queues to use and initializes them. 729 * We support multiple queue sets per port if we have MSI-X, otherwise 730 * just one queue set per port. 731 */ 732static int 733setup_sge_qsets(adapter_t *sc) 734{ 735 int i, j, err, irq_idx = 0, qset_idx = 0; 736 u_int ntxq = SGE_TXQ_PER_SET; 737 738 if ((err = t3_sge_alloc(sc)) != 0) { 739 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 740 return (err); 741 } 742 743 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 744 irq_idx = -1; 745 746 for (i = 0; i < (sc)->params.nports; i++) { 747 struct port_info *pi = &sc->port[i]; 748 749 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 750 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 751 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 752 &sc->params.sge.qset[qset_idx], ntxq, pi); 753 if (err) { 754 t3_free_sge_resources(sc); 755 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 756 err); 757 return (err); 758 } 759 } 760 } 761 762 return (0); 763} 764 765static void 766cxgb_teardown_msix(adapter_t *sc) 767{ 768 int i, nqsets; 769 770 for (nqsets = i = 0; i < (sc)->params.nports; i++) 771 nqsets += sc->port[i].nqsets; 772 773 for (i = 0; i < nqsets; i++) { 774 if (sc->msix_intr_tag[i] != NULL) { 775 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 776 sc->msix_intr_tag[i]); 777 sc->msix_intr_tag[i] = NULL; 778 } 779 if (sc->msix_irq_res[i] != NULL) { 780 bus_release_resource(sc->dev, SYS_RES_IRQ, 781 sc->msix_irq_rid[i], sc->msix_irq_res[i]); 782 sc->msix_irq_res[i] = NULL; 783 } 784 } 785} 786 787static int 788cxgb_setup_msix(adapter_t *sc, int msix_count) 789{ 790 int i, j, k, nqsets, rid; 791 792 /* The first message indicates link changes and error conditions */ 793 sc->irq_rid = 1; 794 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 795 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 796 device_printf(sc->dev, "Cannot allocate msix interrupt\n"); 797 return (EINVAL); 798 } 799 800 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 801#ifdef INTR_FILTERS 802 NULL, 803#endif 804 cxgb_async_intr, sc, &sc->intr_tag)) { 805 device_printf(sc->dev, "Cannot set up interrupt\n"); 806 return (EINVAL); 807 } 808 for (i = k = 0; i < (sc)->params.nports; i++) { 809 nqsets = sc->port[i].nqsets; 810 for (j = 0; j < nqsets; j++, k++) { 811 struct sge_qset *qs = &sc->sge.qs[k]; 812 813 rid = k + 2; 814 if (cxgb_debug) 815 printf("rid=%d ", rid); 816 if ((sc->msix_irq_res[k] = bus_alloc_resource_any( 817 sc->dev, SYS_RES_IRQ, &rid, 818 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 819 device_printf(sc->dev, "Cannot allocate " 820 "interrupt for message %d\n", rid); 821 return (EINVAL); 822 } 823 sc->msix_irq_rid[k] = rid; 824 if (bus_setup_intr(sc->dev, sc->msix_irq_res[k], 825 INTR_MPSAFE|INTR_TYPE_NET, 826#ifdef INTR_FILTERS 827 NULL, 828#endif 829 t3_intr_msix, qs, &sc->msix_intr_tag[k])) { 830 device_printf(sc->dev, "Cannot set up " 831 "interrupt for message %d\n", rid); 832 return (EINVAL); 833 834 } 835#if 0 836#ifdef IFNET_MULTIQUEUE 837 if (multiq) { 838 int vector = rman_get_start(sc->msix_irq_res[k]); 839 if (bootverbose) 840 device_printf(sc->dev, "binding vector=%d to cpu=%d\n", vector, k % mp_ncpus); 841 intr_bind(vector, k % mp_ncpus); 842 } 843#endif 844#endif 845 } 846 } 847 848 return (0); 849} 850 851static int 852cxgb_port_probe(device_t dev) 853{ 854 struct port_info *p; 855 char buf[80]; 856 const char *desc; 857 858 p = device_get_softc(dev); 859 desc = p->phy.desc; 860 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 861 device_set_desc_copy(dev, buf); 862 return (0); 863} 864 865 866static int 867cxgb_makedev(struct port_info *pi) 868{ 869 870 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 871 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 872 873 if (pi->port_cdev == NULL) 874 return (ENOMEM); 875 876 pi->port_cdev->si_drv1 = (void *)pi; 877 878 return (0); 879} 880 881#ifndef LRO_SUPPORTED 882#ifdef IFCAP_LRO 883#undef IFCAP_LRO 884#endif 885#define IFCAP_LRO 0x0 886#endif 887 888#ifdef TSO_SUPPORTED 889#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO) 890/* Don't enable TSO6 yet */ 891#define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_LRO) 892#else 893#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 894/* Don't enable TSO6 yet */ 895#define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 896#define IFCAP_TSO4 0x0 897#define IFCAP_TSO6 0x0 898#define CSUM_TSO 0x0 899#endif 900 901 902static int 903cxgb_port_attach(device_t dev) 904{ 905 struct port_info *p; 906 struct ifnet *ifp; 907 int err, media_flags; 908 struct adapter *sc; 909 910 911 p = device_get_softc(dev); 912 sc = p->adapter; 913 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 914 device_get_unit(device_get_parent(dev)), p->port_id); 915 PORT_LOCK_INIT(p, p->lockbuf); 916 917 /* Allocate an ifnet object and set it up */ 918 ifp = p->ifp = if_alloc(IFT_ETHER); 919 if (ifp == NULL) { 920 device_printf(dev, "Cannot allocate ifnet\n"); 921 return (ENOMEM); 922 } 923 924 /* 925 * Note that there is currently no watchdog timer. 926 */ 927 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 928 ifp->if_init = cxgb_init; 929 ifp->if_softc = p; 930 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 931 ifp->if_ioctl = cxgb_ioctl; 932 ifp->if_start = cxgb_start; 933 934 935 ifp->if_timer = 0; /* Disable ifnet watchdog */ 936 ifp->if_watchdog = NULL; 937 938 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 939 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 940 IFQ_SET_READY(&ifp->if_snd); 941 942 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 943 ifp->if_capabilities |= CXGB_CAP; 944 ifp->if_capenable |= CXGB_CAP_ENABLE; 945 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 946 /* 947 * disable TSO on 4-port - it isn't supported by the firmware yet 948 */ 949 if (p->adapter->params.nports > 2) { 950 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 951 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 952 ifp->if_hwassist &= ~CSUM_TSO; 953 } 954 955 ether_ifattach(ifp, p->hw_addr); 956#ifdef IFNET_MULTIQUEUE 957 ifp->if_transmit = cxgb_pcpu_transmit; 958#endif 959 /* 960 * Only default to jumbo frames on 10GigE 961 */ 962 if (p->adapter->params.nports <= 2) 963 ifp->if_mtu = ETHERMTU_JUMBO; 964 if ((err = cxgb_makedev(p)) != 0) { 965 printf("makedev failed %d\n", err); 966 return (err); 967 } 968 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 969 cxgb_media_status); 970 971 if (!strcmp(p->phy.desc, "10GBASE-CX4")) { 972 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 973 } else if (!strcmp(p->phy.desc, "10GBASE-SR")) { 974 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 975 } else if (!strcmp(p->phy.desc, "10GBASE-R")) { 976 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 977 } else if (!strcmp(p->phy.desc, "10/100/1000BASE-T")) { 978 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 979 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 980 0, NULL); 981 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 982 0, NULL); 983 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 984 0, NULL); 985 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 986 0, NULL); 987 media_flags = 0; 988 } else if (!strcmp(p->phy.desc, "1000BASE-X")) { 989 /* 990 * XXX: This is not very accurate. Fix when common code 991 * returns more specific value - eg 1000BASE-SX, LX, etc. 992 */ 993 media_flags = IFM_ETHER | IFM_1000_SX | IFM_FDX; 994 } else { 995 printf("unsupported media type %s\n", p->phy.desc); 996 return (ENXIO); 997 } 998 if (media_flags) { 999 ifmedia_add(&p->media, media_flags, 0, NULL); 1000 ifmedia_set(&p->media, media_flags); 1001 } else { 1002 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1003 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 1004 } 1005 1006 /* Get the latest mac address, User can use a LAA */ 1007 bcopy(IF_LLADDR(p->ifp), p->hw_addr, ETHER_ADDR_LEN); 1008 t3_sge_init_port(p); 1009#if defined(LINK_ATTACH) 1010 cxgb_link_start(p); 1011 t3_link_changed(sc, p->port_id); 1012#endif 1013 return (0); 1014} 1015 1016static int 1017cxgb_port_detach(device_t dev) 1018{ 1019 struct port_info *p; 1020 1021 p = device_get_softc(dev); 1022 1023 PORT_LOCK(p); 1024 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 1025 cxgb_stop_locked(p); 1026 PORT_UNLOCK(p); 1027 1028 ether_ifdetach(p->ifp); 1029 printf("waiting for callout to stop ..."); 1030 DELAY(1000000); 1031 printf("done\n"); 1032 /* 1033 * the lock may be acquired in ifdetach 1034 */ 1035 PORT_LOCK_DEINIT(p); 1036 if_free(p->ifp); 1037 1038 if (p->port_cdev != NULL) 1039 destroy_dev(p->port_cdev); 1040 1041 return (0); 1042} 1043 1044void 1045t3_fatal_err(struct adapter *sc) 1046{ 1047 u_int fw_status[4]; 1048 1049 if (sc->flags & FULL_INIT_DONE) { 1050 t3_sge_stop(sc); 1051 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1052 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1053 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1054 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1055 t3_intr_disable(sc); 1056 } 1057 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1058 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1059 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1060 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1061} 1062 1063int 1064t3_os_find_pci_capability(adapter_t *sc, int cap) 1065{ 1066 device_t dev; 1067 struct pci_devinfo *dinfo; 1068 pcicfgregs *cfg; 1069 uint32_t status; 1070 uint8_t ptr; 1071 1072 dev = sc->dev; 1073 dinfo = device_get_ivars(dev); 1074 cfg = &dinfo->cfg; 1075 1076 status = pci_read_config(dev, PCIR_STATUS, 2); 1077 if (!(status & PCIM_STATUS_CAPPRESENT)) 1078 return (0); 1079 1080 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1081 case 0: 1082 case 1: 1083 ptr = PCIR_CAP_PTR; 1084 break; 1085 case 2: 1086 ptr = PCIR_CAP_PTR_2; 1087 break; 1088 default: 1089 return (0); 1090 break; 1091 } 1092 ptr = pci_read_config(dev, ptr, 1); 1093 1094 while (ptr != 0) { 1095 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1096 return (ptr); 1097 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1098 } 1099 1100 return (0); 1101} 1102 1103int 1104t3_os_pci_save_state(struct adapter *sc) 1105{ 1106 device_t dev; 1107 struct pci_devinfo *dinfo; 1108 1109 dev = sc->dev; 1110 dinfo = device_get_ivars(dev); 1111 1112 pci_cfg_save(dev, dinfo, 0); 1113 return (0); 1114} 1115 1116int 1117t3_os_pci_restore_state(struct adapter *sc) 1118{ 1119 device_t dev; 1120 struct pci_devinfo *dinfo; 1121 1122 dev = sc->dev; 1123 dinfo = device_get_ivars(dev); 1124 1125 pci_cfg_restore(dev, dinfo); 1126 return (0); 1127} 1128 1129/** 1130 * t3_os_link_changed - handle link status changes 1131 * @adapter: the adapter associated with the link change 1132 * @port_id: the port index whose limk status has changed 1133 * @link_status: the new status of the link 1134 * @speed: the new speed setting 1135 * @duplex: the new duplex setting 1136 * @fc: the new flow-control setting 1137 * 1138 * This is the OS-dependent handler for link status changes. The OS 1139 * neutral handler takes care of most of the processing for these events, 1140 * then calls this handler for any OS-specific processing. 1141 */ 1142void 1143t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1144 int duplex, int fc) 1145{ 1146 struct port_info *pi = &adapter->port[port_id]; 1147 struct cmac *mac = &adapter->port[port_id].mac; 1148 1149 if (link_status) { 1150 DELAY(10); 1151 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1152 /* Clear errors created by MAC enable */ 1153 t3_set_reg_field(adapter, 1154 A_XGM_STAT_CTRL + pi->mac.offset, 1155 F_CLRSTATS, 1); 1156 if_link_state_change(pi->ifp, LINK_STATE_UP); 1157 1158 } else { 1159 pi->phy.ops->power_down(&pi->phy, 1); 1160 t3_mac_disable(mac, MAC_DIRECTION_RX); 1161 t3_link_start(&pi->phy, mac, &pi->link_config); 1162 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1163 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 1164 } 1165} 1166 1167/** 1168 * t3_os_phymod_changed - handle PHY module changes 1169 * @phy: the PHY reporting the module change 1170 * @mod_type: new module type 1171 * 1172 * This is the OS-dependent handler for PHY module changes. It is 1173 * invoked when a PHY module is removed or inserted for any OS-specific 1174 * processing. 1175 */ 1176void t3_os_phymod_changed(struct adapter *adap, int port_id) 1177{ 1178 static const char *mod_str[] = { 1179 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown" 1180 }; 1181 1182 struct port_info *pi = &adap->port[port_id]; 1183 1184 if (pi->phy.modtype == phy_modtype_none) 1185 device_printf(adap->dev, "PHY module unplugged\n"); 1186 else { 1187 KASSERT(pi->phy.modtype < ARRAY_SIZE(mod_str), 1188 ("invalid PHY module type %d", pi->phy.modtype)); 1189 device_printf(adap->dev, "%s PHY module inserted\n", 1190 mod_str[pi->phy.modtype]); 1191 } 1192} 1193 1194/* 1195 * Interrupt-context handler for external (PHY) interrupts. 1196 */ 1197void 1198t3_os_ext_intr_handler(adapter_t *sc) 1199{ 1200 if (cxgb_debug) 1201 printf("t3_os_ext_intr_handler\n"); 1202 /* 1203 * Schedule a task to handle external interrupts as they may be slow 1204 * and we use a mutex to protect MDIO registers. We disable PHY 1205 * interrupts in the meantime and let the task reenable them when 1206 * it's done. 1207 */ 1208 ADAPTER_LOCK(sc); 1209 if (sc->slow_intr_mask) { 1210 sc->slow_intr_mask &= ~F_T3DBG; 1211 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1212 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1213 } 1214 ADAPTER_UNLOCK(sc); 1215} 1216 1217void 1218t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1219{ 1220 1221 /* 1222 * The ifnet might not be allocated before this gets called, 1223 * as this is called early on in attach by t3_prep_adapter 1224 * save the address off in the port structure 1225 */ 1226 if (cxgb_debug) 1227 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1228 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1229} 1230 1231/** 1232 * link_start - enable a port 1233 * @p: the port to enable 1234 * 1235 * Performs the MAC and PHY actions needed to enable a port. 1236 */ 1237static void 1238cxgb_link_start(struct port_info *p) 1239{ 1240 struct ifnet *ifp; 1241 struct t3_rx_mode rm; 1242 struct cmac *mac = &p->mac; 1243 int mtu, hwtagging; 1244 1245 ifp = p->ifp; 1246 1247 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN); 1248 1249 mtu = ifp->if_mtu; 1250 if (ifp->if_capenable & IFCAP_VLAN_MTU) 1251 mtu += ETHER_VLAN_ENCAP_LEN; 1252 1253 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0; 1254 1255 t3_init_rx_mode(&rm, p); 1256 if (!mac->multiport) 1257 t3_mac_reset(mac); 1258 t3_mac_set_mtu(mac, mtu); 1259 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging); 1260 t3_mac_set_address(mac, 0, p->hw_addr); 1261 t3_mac_set_rx_mode(mac, &rm); 1262 t3_link_start(&p->phy, mac, &p->link_config); 1263 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1264} 1265 1266 1267static int 1268await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1269 unsigned long n) 1270{ 1271 int attempts = 5; 1272 1273 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1274 if (!--attempts) 1275 return (ETIMEDOUT); 1276 t3_os_sleep(10); 1277 } 1278 return 0; 1279} 1280 1281static int 1282init_tp_parity(struct adapter *adap) 1283{ 1284 int i; 1285 struct mbuf *m; 1286 struct cpl_set_tcb_field *greq; 1287 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1288 1289 t3_tp_set_offload_mode(adap, 1); 1290 1291 for (i = 0; i < 16; i++) { 1292 struct cpl_smt_write_req *req; 1293 1294 m = m_gethdr(M_WAITOK, MT_DATA); 1295 req = mtod(m, struct cpl_smt_write_req *); 1296 m->m_len = m->m_pkthdr.len = sizeof(*req); 1297 memset(req, 0, sizeof(*req)); 1298 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1299 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1300 req->iff = i; 1301 t3_mgmt_tx(adap, m); 1302 } 1303 1304 for (i = 0; i < 2048; i++) { 1305 struct cpl_l2t_write_req *req; 1306 1307 m = m_gethdr(M_WAITOK, MT_DATA); 1308 req = mtod(m, struct cpl_l2t_write_req *); 1309 m->m_len = m->m_pkthdr.len = sizeof(*req); 1310 memset(req, 0, sizeof(*req)); 1311 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1312 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1313 req->params = htonl(V_L2T_W_IDX(i)); 1314 t3_mgmt_tx(adap, m); 1315 } 1316 1317 for (i = 0; i < 2048; i++) { 1318 struct cpl_rte_write_req *req; 1319 1320 m = m_gethdr(M_WAITOK, MT_DATA); 1321 req = mtod(m, struct cpl_rte_write_req *); 1322 m->m_len = m->m_pkthdr.len = sizeof(*req); 1323 memset(req, 0, sizeof(*req)); 1324 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1325 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1326 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1327 t3_mgmt_tx(adap, m); 1328 } 1329 1330 m = m_gethdr(M_WAITOK, MT_DATA); 1331 greq = mtod(m, struct cpl_set_tcb_field *); 1332 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1333 memset(greq, 0, sizeof(*greq)); 1334 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1335 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1336 greq->mask = htobe64(1); 1337 t3_mgmt_tx(adap, m); 1338 1339 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1340 t3_tp_set_offload_mode(adap, 0); 1341 return (i); 1342} 1343 1344/** 1345 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1346 * @adap: the adapter 1347 * 1348 * Sets up RSS to distribute packets to multiple receive queues. We 1349 * configure the RSS CPU lookup table to distribute to the number of HW 1350 * receive queues, and the response queue lookup table to narrow that 1351 * down to the response queues actually configured for each port. 1352 * We always configure the RSS mapping for two ports since the mapping 1353 * table has plenty of entries. 1354 */ 1355static void 1356setup_rss(adapter_t *adap) 1357{ 1358 int i; 1359 u_int nq[2]; 1360 uint8_t cpus[SGE_QSETS + 1]; 1361 uint16_t rspq_map[RSS_TABLE_SIZE]; 1362 1363 for (i = 0; i < SGE_QSETS; ++i) 1364 cpus[i] = i; 1365 cpus[SGE_QSETS] = 0xff; 1366 1367 nq[0] = nq[1] = 0; 1368 for_each_port(adap, i) { 1369 const struct port_info *pi = adap2pinfo(adap, i); 1370 1371 nq[pi->tx_chan] += pi->nqsets; 1372 } 1373 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1374 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1375 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1376 } 1377 /* Calculate the reverse RSS map table */ 1378 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1379 if (adap->rrss_map[rspq_map[i]] == 0xff) 1380 adap->rrss_map[rspq_map[i]] = i; 1381 1382 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1383 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1384 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1385 cpus, rspq_map); 1386 1387} 1388 1389/* 1390 * Sends an mbuf to an offload queue driver 1391 * after dealing with any active network taps. 1392 */ 1393static inline int 1394offload_tx(struct t3cdev *tdev, struct mbuf *m) 1395{ 1396 int ret; 1397 1398 ret = t3_offload_tx(tdev, m); 1399 return (ret); 1400} 1401 1402static int 1403write_smt_entry(struct adapter *adapter, int idx) 1404{ 1405 struct port_info *pi = &adapter->port[idx]; 1406 struct cpl_smt_write_req *req; 1407 struct mbuf *m; 1408 1409 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1410 return (ENOMEM); 1411 1412 req = mtod(m, struct cpl_smt_write_req *); 1413 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1414 1415 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1416 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1417 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1418 req->iff = idx; 1419 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1420 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1421 1422 m_set_priority(m, 1); 1423 1424 offload_tx(&adapter->tdev, m); 1425 1426 return (0); 1427} 1428 1429static int 1430init_smt(struct adapter *adapter) 1431{ 1432 int i; 1433 1434 for_each_port(adapter, i) 1435 write_smt_entry(adapter, i); 1436 return 0; 1437} 1438 1439static void 1440init_port_mtus(adapter_t *adapter) 1441{ 1442 unsigned int mtus = adapter->port[0].ifp->if_mtu; 1443 1444 if (adapter->port[1].ifp) 1445 mtus |= adapter->port[1].ifp->if_mtu << 16; 1446 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1447} 1448 1449static void 1450send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1451 int hi, int port) 1452{ 1453 struct mbuf *m; 1454 struct mngt_pktsched_wr *req; 1455 1456 m = m_gethdr(M_DONTWAIT, MT_DATA); 1457 if (m) { 1458 req = mtod(m, struct mngt_pktsched_wr *); 1459 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1460 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1461 req->sched = sched; 1462 req->idx = qidx; 1463 req->min = lo; 1464 req->max = hi; 1465 req->binding = port; 1466 m->m_len = m->m_pkthdr.len = sizeof(*req); 1467 t3_mgmt_tx(adap, m); 1468 } 1469} 1470 1471static void 1472bind_qsets(adapter_t *sc) 1473{ 1474 int i, j; 1475 1476 cxgb_pcpu_startup_threads(sc); 1477 for (i = 0; i < (sc)->params.nports; ++i) { 1478 const struct port_info *pi = adap2pinfo(sc, i); 1479 1480 for (j = 0; j < pi->nqsets; ++j) { 1481 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1482 -1, pi->tx_chan); 1483 1484 } 1485 } 1486} 1487 1488static void 1489update_tpeeprom(struct adapter *adap) 1490{ 1491#ifdef FIRMWARE_LATEST 1492 const struct firmware *tpeeprom; 1493#else 1494 struct firmware *tpeeprom; 1495#endif 1496 1497 uint32_t version; 1498 unsigned int major, minor; 1499 int ret, len; 1500 char rev; 1501 1502 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1503 1504 major = G_TP_VERSION_MAJOR(version); 1505 minor = G_TP_VERSION_MINOR(version); 1506 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1507 return; 1508 1509 rev = t3rev2char(adap); 1510 1511 tpeeprom = firmware_get(TPEEPROM_NAME); 1512 if (tpeeprom == NULL) { 1513 device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n", 1514 TPEEPROM_NAME); 1515 return; 1516 } 1517 1518 len = tpeeprom->datasize - 4; 1519 1520 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1521 if (ret) 1522 goto release_tpeeprom; 1523 1524 if (len != TP_SRAM_LEN) { 1525 device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", TPEEPROM_NAME, len, TP_SRAM_LEN); 1526 return; 1527 } 1528 1529 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1530 TP_SRAM_OFFSET); 1531 1532 if (!ret) { 1533 device_printf(adap->dev, 1534 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1535 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1536 } else 1537 device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n"); 1538 1539release_tpeeprom: 1540 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1541 1542 return; 1543} 1544 1545static int 1546update_tpsram(struct adapter *adap) 1547{ 1548#ifdef FIRMWARE_LATEST 1549 const struct firmware *tpsram; 1550#else 1551 struct firmware *tpsram; 1552#endif 1553 int ret; 1554 char rev; 1555 1556 rev = t3rev2char(adap); 1557 if (!rev) 1558 return 0; 1559 1560 update_tpeeprom(adap); 1561 1562 tpsram = firmware_get(TPSRAM_NAME); 1563 if (tpsram == NULL){ 1564 device_printf(adap->dev, "could not load TP SRAM\n"); 1565 return (EINVAL); 1566 } else 1567 device_printf(adap->dev, "updating TP SRAM\n"); 1568 1569 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1570 if (ret) 1571 goto release_tpsram; 1572 1573 ret = t3_set_proto_sram(adap, tpsram->data); 1574 if (ret) 1575 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1576 1577release_tpsram: 1578 firmware_put(tpsram, FIRMWARE_UNLOAD); 1579 1580 return ret; 1581} 1582 1583/** 1584 * cxgb_up - enable the adapter 1585 * @adap: adapter being enabled 1586 * 1587 * Called when the first port is enabled, this function performs the 1588 * actions necessary to make an adapter operational, such as completing 1589 * the initialization of HW modules, and enabling interrupts. 1590 * 1591 */ 1592static int 1593cxgb_up(struct adapter *sc) 1594{ 1595 int err = 0; 1596 1597 if ((sc->flags & FULL_INIT_DONE) == 0) { 1598 1599 if ((sc->flags & FW_UPTODATE) == 0) 1600 if ((err = upgrade_fw(sc))) 1601 goto out; 1602 if ((sc->flags & TPS_UPTODATE) == 0) 1603 if ((err = update_tpsram(sc))) 1604 goto out; 1605 err = t3_init_hw(sc, 0); 1606 if (err) 1607 goto out; 1608 1609 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1610 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1611 1612 err = setup_sge_qsets(sc); 1613 if (err) 1614 goto out; 1615 1616 setup_rss(sc); 1617 t3_add_configured_sysctls(sc); 1618 sc->flags |= FULL_INIT_DONE; 1619 } 1620 1621 t3_intr_clear(sc); 1622 1623 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1624 if ((sc->flags & USING_MSIX) == 0) { 1625 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1626 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 1627 device_printf(sc->dev, "Cannot allocate interrupt rid=%d\n", 1628 sc->irq_rid); 1629 err = EINVAL; 1630 goto out; 1631 } 1632 device_printf(sc->dev, "allocated irq_res=%p\n", sc->irq_res); 1633 1634 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 1635#ifdef INTR_FILTERS 1636 NULL, 1637#endif 1638 sc->cxgb_intr, sc, &sc->intr_tag)) { 1639 device_printf(sc->dev, "Cannot set up interrupt\n"); 1640 err = EINVAL; 1641 goto irq_err; 1642 } 1643 } else { 1644 cxgb_setup_msix(sc, sc->msi_count); 1645 } 1646 1647 t3_sge_start(sc); 1648 t3_intr_enable(sc); 1649 1650 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1651 is_offload(sc) && init_tp_parity(sc) == 0) 1652 sc->flags |= TP_PARITY_INIT; 1653 1654 if (sc->flags & TP_PARITY_INIT) { 1655 t3_write_reg(sc, A_TP_INT_CAUSE, 1656 F_CMCACHEPERR | F_ARPLUTPERR); 1657 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1658 } 1659 1660 1661 if (!(sc->flags & QUEUES_BOUND)) { 1662 bind_qsets(sc); 1663 sc->flags |= QUEUES_BOUND; 1664 } 1665out: 1666 return (err); 1667irq_err: 1668 CH_ERR(sc, "request_irq failed, err %d\n", err); 1669 goto out; 1670} 1671 1672 1673/* 1674 * Release resources when all the ports and offloading have been stopped. 1675 */ 1676static void 1677cxgb_down_locked(struct adapter *sc) 1678{ 1679 1680 t3_sge_stop(sc); 1681 t3_intr_disable(sc); 1682 1683 if (sc->intr_tag != NULL) { 1684 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 1685 sc->intr_tag = NULL; 1686 } 1687 if (sc->irq_res != NULL) { 1688 device_printf(sc->dev, "de-allocating interrupt irq_rid=%d irq_res=%p\n", 1689 sc->irq_rid, sc->irq_res); 1690 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 1691 sc->irq_res); 1692 sc->irq_res = NULL; 1693 } 1694 1695 if (sc->flags & USING_MSIX) 1696 cxgb_teardown_msix(sc); 1697 1698 callout_stop(&sc->cxgb_tick_ch); 1699 callout_stop(&sc->sge_timer_ch); 1700 callout_drain(&sc->cxgb_tick_ch); 1701 callout_drain(&sc->sge_timer_ch); 1702 1703 if (sc->tq != NULL) { 1704 printf("draining slow intr\n"); 1705 1706 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1707 printf("draining ext intr\n"); 1708 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1709 printf("draining tick task\n"); 1710 taskqueue_drain(sc->tq, &sc->tick_task); 1711 } 1712 ADAPTER_UNLOCK(sc); 1713} 1714 1715static int 1716offload_open(struct port_info *pi) 1717{ 1718 struct adapter *adapter = pi->adapter; 1719 struct t3cdev *tdev = &adapter->tdev; 1720 1721 int adap_up = adapter->open_device_map & PORT_MASK; 1722 int err = 0; 1723 1724 if (atomic_cmpset_int(&adapter->open_device_map, 1725 (adapter->open_device_map & ~(1<<OFFLOAD_DEVMAP_BIT)), 1726 (adapter->open_device_map | (1<<OFFLOAD_DEVMAP_BIT))) == 0) 1727 return (0); 1728 1729 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1730 printf("offload_open: DEVMAP_BIT did not get set 0x%x\n", 1731 adapter->open_device_map); 1732 ADAPTER_LOCK(pi->adapter); 1733 if (!adap_up) 1734 err = cxgb_up(adapter); 1735 ADAPTER_UNLOCK(pi->adapter); 1736 if (err) 1737 return (err); 1738 1739 t3_tp_set_offload_mode(adapter, 1); 1740 tdev->lldev = pi->ifp; 1741 1742 init_port_mtus(adapter); 1743 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, 1744 adapter->params.b_wnd, 1745 adapter->params.rev == 0 ? 1746 adapter->port[0].ifp->if_mtu : 0xffff); 1747 init_smt(adapter); 1748 /* Call back all registered clients */ 1749 cxgb_add_clients(tdev); 1750 1751 /* restore them in case the offload module has changed them */ 1752 if (err) { 1753 t3_tp_set_offload_mode(adapter, 0); 1754 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1755 cxgb_set_dummy_ops(tdev); 1756 } 1757 return (err); 1758} 1759 1760static int 1761offload_close(struct t3cdev *tdev) 1762{ 1763 struct adapter *adapter = tdev2adap(tdev); 1764 1765 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1766 return (0); 1767 1768 /* Call back all registered clients */ 1769 cxgb_remove_clients(tdev); 1770 1771 tdev->lldev = NULL; 1772 cxgb_set_dummy_ops(tdev); 1773 t3_tp_set_offload_mode(adapter, 0); 1774 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1775 1776 ADAPTER_LOCK(adapter); 1777 if (!adapter->open_device_map) 1778 cxgb_down_locked(adapter); 1779 else 1780 ADAPTER_UNLOCK(adapter); 1781 return (0); 1782} 1783 1784 1785static void 1786cxgb_init(void *arg) 1787{ 1788 struct port_info *p = arg; 1789 1790 PORT_LOCK(p); 1791 cxgb_init_locked(p); 1792 PORT_UNLOCK(p); 1793} 1794 1795static void 1796cxgb_init_locked(struct port_info *p) 1797{ 1798 struct ifnet *ifp; 1799 adapter_t *sc = p->adapter; 1800 int err; 1801 1802 PORT_LOCK_ASSERT_OWNED(p); 1803 ifp = p->ifp; 1804 1805 ADAPTER_LOCK(p->adapter); 1806 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1807 ADAPTER_UNLOCK(p->adapter); 1808 cxgb_stop_locked(p); 1809 return; 1810 } 1811 if (p->adapter->open_device_map == 0) { 1812 t3_intr_clear(sc); 1813 } 1814 setbit(&p->adapter->open_device_map, p->port_id); 1815 ADAPTER_UNLOCK(p->adapter); 1816 1817 if (is_offload(sc) && !ofld_disable) { 1818 err = offload_open(p); 1819 if (err) 1820 log(LOG_WARNING, 1821 "Could not initialize offload capabilities\n"); 1822 } 1823#if !defined(LINK_ATTACH) 1824 cxgb_link_start(p); 1825 t3_link_changed(sc, p->port_id); 1826#endif 1827 ifp->if_baudrate = p->link_config.speed * 1000000; 1828 1829 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id); 1830 t3_port_intr_enable(sc, p->port_id); 1831 1832 t3_sge_reset_adapter(sc); 1833 1834 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1835 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1836} 1837 1838static void 1839cxgb_set_rxmode(struct port_info *p) 1840{ 1841 struct t3_rx_mode rm; 1842 struct cmac *mac = &p->mac; 1843 1844 t3_init_rx_mode(&rm, p); 1845 mtx_lock(&p->adapter->mdio_lock); 1846 t3_mac_set_rx_mode(mac, &rm); 1847 mtx_unlock(&p->adapter->mdio_lock); 1848} 1849 1850static void 1851cxgb_stop_locked(struct port_info *pi) 1852{ 1853 struct ifnet *ifp; 1854 1855 PORT_LOCK_ASSERT_OWNED(pi); 1856 ADAPTER_LOCK_ASSERT_NOTOWNED(pi->adapter); 1857 1858 ifp = pi->ifp; 1859 t3_port_intr_disable(pi->adapter, pi->port_id); 1860 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1861 1862 /* disable pause frames */ 1863 t3_set_reg_field(pi->adapter, A_XGM_TX_CFG + pi->mac.offset, 1864 F_TXPAUSEEN, 0); 1865 1866 /* Reset RX FIFO HWM */ 1867 t3_set_reg_field(pi->adapter, A_XGM_RXFIFO_CFG + pi->mac.offset, 1868 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); 1869 1870 1871 ADAPTER_LOCK(pi->adapter); 1872 clrbit(&pi->adapter->open_device_map, pi->port_id); 1873 1874 if (pi->adapter->open_device_map == 0) { 1875 cxgb_down_locked(pi->adapter); 1876 } else 1877 ADAPTER_UNLOCK(pi->adapter); 1878 1879#if !defined(LINK_ATTACH) 1880 DELAY(100); 1881 1882 /* Wait for TXFIFO empty */ 1883 t3_wait_op_done(pi->adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 1884 F_TXFIFO_EMPTY, 1, 20, 5); 1885 1886 DELAY(100); 1887 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1888 1889 pi->phy.ops->power_down(&pi->phy, 1); 1890#endif 1891 1892} 1893 1894static int 1895cxgb_set_mtu(struct port_info *p, int mtu) 1896{ 1897 struct ifnet *ifp = p->ifp; 1898 int error = 0; 1899 1900 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) 1901 error = EINVAL; 1902 else if (ifp->if_mtu != mtu) { 1903 PORT_LOCK(p); 1904 ifp->if_mtu = mtu; 1905 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1906 cxgb_stop_locked(p); 1907 cxgb_init_locked(p); 1908 } 1909 PORT_UNLOCK(p); 1910 } 1911 return (error); 1912} 1913 1914#ifdef LRO_SUPPORTED 1915/* 1916 * Mark lro enabled or disabled in all qsets for this port 1917 */ 1918static int 1919cxgb_set_lro(struct port_info *p, int enabled) 1920{ 1921 int i; 1922 struct adapter *adp = p->adapter; 1923 struct sge_qset *q; 1924 1925 PORT_LOCK_ASSERT_OWNED(p); 1926 for (i = 0; i < p->nqsets; i++) { 1927 q = &adp->sge.qs[p->first_qset + i]; 1928 q->lro.enabled = (enabled != 0); 1929 } 1930 return (0); 1931} 1932#endif 1933 1934static int 1935cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 1936{ 1937 struct port_info *p = ifp->if_softc; 1938#ifdef INET 1939 struct ifaddr *ifa = (struct ifaddr *)data; 1940#endif 1941 struct ifreq *ifr = (struct ifreq *)data; 1942 int flags, error = 0, reinit = 0; 1943 uint32_t mask; 1944 1945 /* 1946 * XXX need to check that we aren't in the middle of an unload 1947 */ 1948 switch (command) { 1949 case SIOCSIFMTU: 1950 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1951 break; 1952 case SIOCSIFADDR: 1953#ifdef INET 1954 if (ifa->ifa_addr->sa_family == AF_INET) { 1955 ifp->if_flags |= IFF_UP; 1956 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1957 PORT_LOCK(p); 1958 cxgb_init_locked(p); 1959 PORT_UNLOCK(p); 1960 } 1961 arp_ifinit(ifp, ifa); 1962 } else 1963#endif 1964 error = ether_ioctl(ifp, command, data); 1965 break; 1966 case SIOCSIFFLAGS: 1967 PORT_LOCK(p); 1968 if (ifp->if_flags & IFF_UP) { 1969 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1970 flags = p->if_flags; 1971 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1972 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1973 cxgb_set_rxmode(p); 1974 } else 1975 cxgb_init_locked(p); 1976 p->if_flags = ifp->if_flags; 1977 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1978 cxgb_stop_locked(p); 1979 1980 PORT_UNLOCK(p); 1981 break; 1982 case SIOCADDMULTI: 1983 case SIOCDELMULTI: 1984 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1985 cxgb_set_rxmode(p); 1986 } 1987 break; 1988 case SIOCSIFMEDIA: 1989 case SIOCGIFMEDIA: 1990 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 1991 break; 1992 case SIOCSIFCAP: 1993 PORT_LOCK(p); 1994 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1995 if (mask & IFCAP_TXCSUM) { 1996 if (IFCAP_TXCSUM & ifp->if_capenable) { 1997 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 1998 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 1999 | CSUM_IP | CSUM_TSO); 2000 } else { 2001 ifp->if_capenable |= IFCAP_TXCSUM; 2002 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP 2003 | CSUM_IP); 2004 } 2005 } 2006 if (mask & IFCAP_RXCSUM) { 2007 ifp->if_capenable ^= IFCAP_RXCSUM; 2008 } 2009 if (mask & IFCAP_TSO4) { 2010 if (IFCAP_TSO4 & ifp->if_capenable) { 2011 ifp->if_capenable &= ~IFCAP_TSO4; 2012 ifp->if_hwassist &= ~CSUM_TSO; 2013 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 2014 ifp->if_capenable |= IFCAP_TSO4; 2015 ifp->if_hwassist |= CSUM_TSO; 2016 } else { 2017 if (cxgb_debug) 2018 printf("cxgb requires tx checksum offload" 2019 " be enabled to use TSO\n"); 2020 error = EINVAL; 2021 } 2022 } 2023#ifdef LRO_SUPPORTED 2024 if (mask & IFCAP_LRO) { 2025 ifp->if_capenable ^= IFCAP_LRO; 2026 2027 /* Safe to do this even if cxgb_up not called yet */ 2028 cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO); 2029 } 2030#endif 2031 if (mask & IFCAP_VLAN_HWTAGGING) { 2032 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2033 reinit = ifp->if_drv_flags & IFF_DRV_RUNNING; 2034 } 2035 if (mask & IFCAP_VLAN_MTU) { 2036 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2037 reinit = ifp->if_drv_flags & IFF_DRV_RUNNING; 2038 } 2039 if (mask & IFCAP_VLAN_HWCSUM) { 2040 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2041 } 2042 if (reinit) { 2043 cxgb_stop_locked(p); 2044 cxgb_init_locked(p); 2045 } 2046 PORT_UNLOCK(p); 2047 2048#ifdef VLAN_CAPABILITIES 2049 VLAN_CAPABILITIES(ifp); 2050#endif 2051 break; 2052 default: 2053 error = ether_ioctl(ifp, command, data); 2054 break; 2055 } 2056 return (error); 2057} 2058 2059static int 2060cxgb_media_change(struct ifnet *ifp) 2061{ 2062 if_printf(ifp, "media change not supported\n"); 2063 return (ENXIO); 2064} 2065 2066static void 2067cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2068{ 2069 struct port_info *p = ifp->if_softc; 2070 2071 ifmr->ifm_status = IFM_AVALID; 2072 ifmr->ifm_active = IFM_ETHER; 2073 2074 if (!p->link_config.link_ok) 2075 return; 2076 2077 ifmr->ifm_status |= IFM_ACTIVE; 2078 2079 switch (p->link_config.speed) { 2080 case 10: 2081 ifmr->ifm_active |= IFM_10_T; 2082 break; 2083 case 100: 2084 ifmr->ifm_active |= IFM_100_TX; 2085 break; 2086 case 1000: 2087 ifmr->ifm_active |= IFM_1000_T; 2088 break; 2089 } 2090 2091 if (p->link_config.duplex) 2092 ifmr->ifm_active |= IFM_FDX; 2093 else 2094 ifmr->ifm_active |= IFM_HDX; 2095} 2096 2097static void 2098cxgb_async_intr(void *data) 2099{ 2100 adapter_t *sc = data; 2101 2102 if (cxgb_debug) 2103 device_printf(sc->dev, "cxgb_async_intr\n"); 2104 /* 2105 * May need to sleep - defer to taskqueue 2106 */ 2107 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2108} 2109 2110static void 2111cxgb_ext_intr_handler(void *arg, int count) 2112{ 2113 adapter_t *sc = (adapter_t *)arg; 2114 2115 if (cxgb_debug) 2116 printf("cxgb_ext_intr_handler\n"); 2117 2118 t3_phy_intr_handler(sc); 2119 2120 /* Now reenable external interrupts */ 2121 ADAPTER_LOCK(sc); 2122 if (sc->slow_intr_mask) { 2123 sc->slow_intr_mask |= F_T3DBG; 2124 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2125 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2126 } 2127 ADAPTER_UNLOCK(sc); 2128} 2129 2130static void 2131check_link_status(adapter_t *sc) 2132{ 2133 int i; 2134 2135 for (i = 0; i < (sc)->params.nports; ++i) { 2136 struct port_info *p = &sc->port[i]; 2137 2138 if (!(p->phy.caps & SUPPORTED_IRQ)) 2139 t3_link_changed(sc, i); 2140 p->ifp->if_baudrate = p->link_config.speed * 1000000; 2141 } 2142} 2143 2144static void 2145check_t3b2_mac(struct adapter *adapter) 2146{ 2147 int i; 2148 2149 if(adapter->flags & CXGB_SHUTDOWN) 2150 return; 2151 2152 for_each_port(adapter, i) { 2153 struct port_info *p = &adapter->port[i]; 2154 struct ifnet *ifp = p->ifp; 2155 int status; 2156 2157 if(adapter->flags & CXGB_SHUTDOWN) 2158 return; 2159 2160 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2161 continue; 2162 2163 status = 0; 2164 PORT_LOCK(p); 2165 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 2166 status = t3b2_mac_watchdog_task(&p->mac); 2167 if (status == 1) 2168 p->mac.stats.num_toggled++; 2169 else if (status == 2) { 2170 struct cmac *mac = &p->mac; 2171 int mtu = ifp->if_mtu; 2172 2173 if (ifp->if_capenable & IFCAP_VLAN_MTU) 2174 mtu += ETHER_VLAN_ENCAP_LEN; 2175 t3_mac_set_mtu(mac, mtu); 2176 t3_mac_set_address(mac, 0, p->hw_addr); 2177 cxgb_set_rxmode(p); 2178 t3_link_start(&p->phy, mac, &p->link_config); 2179 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2180 t3_port_intr_enable(adapter, p->port_id); 2181 p->mac.stats.num_resets++; 2182 } 2183 PORT_UNLOCK(p); 2184 } 2185} 2186 2187static void 2188cxgb_tick(void *arg) 2189{ 2190 adapter_t *sc = (adapter_t *)arg; 2191 2192 if(sc->flags & CXGB_SHUTDOWN) 2193 return; 2194 2195 taskqueue_enqueue(sc->tq, &sc->tick_task); 2196 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 2197} 2198 2199static void 2200cxgb_tick_handler(void *arg, int count) 2201{ 2202 adapter_t *sc = (adapter_t *)arg; 2203 const struct adapter_params *p = &sc->params; 2204 int i; 2205 2206 if(sc->flags & CXGB_SHUTDOWN) 2207 return; 2208 2209 ADAPTER_LOCK(sc); 2210 if (p->linkpoll_period) 2211 check_link_status(sc); 2212 2213 2214 sc->check_task_cnt++; 2215 2216 /* 2217 * adapter lock can currently only be acquired after the 2218 * port lock 2219 */ 2220 ADAPTER_UNLOCK(sc); 2221 2222 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2223 check_t3b2_mac(sc); 2224 2225 for (i = 0; i < sc->params.nports; i++) { 2226 struct port_info *pi = &sc->port[i]; 2227 struct ifnet *ifp = pi->ifp; 2228 struct mac_stats *mstats = &pi->mac.stats; 2229 PORT_LOCK(pi); 2230 t3_mac_update_stats(&pi->mac); 2231 PORT_UNLOCK(pi); 2232 2233 2234 ifp->if_opackets = 2235 mstats->tx_frames_64 + 2236 mstats->tx_frames_65_127 + 2237 mstats->tx_frames_128_255 + 2238 mstats->tx_frames_256_511 + 2239 mstats->tx_frames_512_1023 + 2240 mstats->tx_frames_1024_1518 + 2241 mstats->tx_frames_1519_max; 2242 2243 ifp->if_ipackets = 2244 mstats->rx_frames_64 + 2245 mstats->rx_frames_65_127 + 2246 mstats->rx_frames_128_255 + 2247 mstats->rx_frames_256_511 + 2248 mstats->rx_frames_512_1023 + 2249 mstats->rx_frames_1024_1518 + 2250 mstats->rx_frames_1519_max; 2251 2252 ifp->if_obytes = mstats->tx_octets; 2253 ifp->if_ibytes = mstats->rx_octets; 2254 ifp->if_omcasts = mstats->tx_mcast_frames; 2255 ifp->if_imcasts = mstats->rx_mcast_frames; 2256 2257 ifp->if_collisions = 2258 mstats->tx_total_collisions; 2259 2260 ifp->if_iqdrops = mstats->rx_cong_drops; 2261 2262 ifp->if_oerrors = 2263 mstats->tx_excess_collisions + 2264 mstats->tx_underrun + 2265 mstats->tx_len_errs + 2266 mstats->tx_mac_internal_errs + 2267 mstats->tx_excess_deferral + 2268 mstats->tx_fcs_errs; 2269 ifp->if_ierrors = 2270 mstats->rx_jabber + 2271 mstats->rx_data_errs + 2272 mstats->rx_sequence_errs + 2273 mstats->rx_runt + 2274 mstats->rx_too_long + 2275 mstats->rx_mac_internal_errs + 2276 mstats->rx_short + 2277 mstats->rx_fcs_errs; 2278 } 2279} 2280 2281static void 2282touch_bars(device_t dev) 2283{ 2284 /* 2285 * Don't enable yet 2286 */ 2287#if !defined(__LP64__) && 0 2288 u32 v; 2289 2290 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2291 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2292 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2293 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2294 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2295 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2296#endif 2297} 2298 2299static int 2300set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2301{ 2302 uint8_t *buf; 2303 int err = 0; 2304 u32 aligned_offset, aligned_len, *p; 2305 struct adapter *adapter = pi->adapter; 2306 2307 2308 aligned_offset = offset & ~3; 2309 aligned_len = (len + (offset & 3) + 3) & ~3; 2310 2311 if (aligned_offset != offset || aligned_len != len) { 2312 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2313 if (!buf) 2314 return (ENOMEM); 2315 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2316 if (!err && aligned_len > 4) 2317 err = t3_seeprom_read(adapter, 2318 aligned_offset + aligned_len - 4, 2319 (u32 *)&buf[aligned_len - 4]); 2320 if (err) 2321 goto out; 2322 memcpy(buf + (offset & 3), data, len); 2323 } else 2324 buf = (uint8_t *)(uintptr_t)data; 2325 2326 err = t3_seeprom_wp(adapter, 0); 2327 if (err) 2328 goto out; 2329 2330 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2331 err = t3_seeprom_write(adapter, aligned_offset, *p); 2332 aligned_offset += 4; 2333 } 2334 2335 if (!err) 2336 err = t3_seeprom_wp(adapter, 1); 2337out: 2338 if (buf != data) 2339 free(buf, M_DEVBUF); 2340 return err; 2341} 2342 2343 2344static int 2345in_range(int val, int lo, int hi) 2346{ 2347 return val < 0 || (val <= hi && val >= lo); 2348} 2349 2350static int 2351cxgb_extension_open(struct cdev *dev, int flags, int fmp, d_thread_t *td) 2352{ 2353 return (0); 2354} 2355 2356static int 2357cxgb_extension_close(struct cdev *dev, int flags, int fmt, d_thread_t *td) 2358{ 2359 return (0); 2360} 2361 2362static int 2363cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2364 int fflag, struct thread *td) 2365{ 2366 int mmd, error = 0; 2367 struct port_info *pi = dev->si_drv1; 2368 adapter_t *sc = pi->adapter; 2369 2370#ifdef PRIV_SUPPORTED 2371 if (priv_check(td, PRIV_DRIVER)) { 2372 if (cxgb_debug) 2373 printf("user does not have access to privileged ioctls\n"); 2374 return (EPERM); 2375 } 2376#else 2377 if (suser(td)) { 2378 if (cxgb_debug) 2379 printf("user does not have access to privileged ioctls\n"); 2380 return (EPERM); 2381 } 2382#endif 2383 2384 switch (cmd) { 2385 case CHELSIO_GET_MIIREG: { 2386 uint32_t val; 2387 struct cphy *phy = &pi->phy; 2388 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2389 2390 if (!phy->mdio_read) 2391 return (EOPNOTSUPP); 2392 if (is_10G(sc)) { 2393 mmd = mid->phy_id >> 8; 2394 if (!mmd) 2395 mmd = MDIO_DEV_PCS; 2396 else if (mmd > MDIO_DEV_XGXS) 2397 return (EINVAL); 2398 2399 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2400 mid->reg_num, &val); 2401 } else 2402 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2403 mid->reg_num & 0x1f, &val); 2404 if (error == 0) 2405 mid->val_out = val; 2406 break; 2407 } 2408 case CHELSIO_SET_MIIREG: { 2409 struct cphy *phy = &pi->phy; 2410 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2411 2412 if (!phy->mdio_write) 2413 return (EOPNOTSUPP); 2414 if (is_10G(sc)) { 2415 mmd = mid->phy_id >> 8; 2416 if (!mmd) 2417 mmd = MDIO_DEV_PCS; 2418 else if (mmd > MDIO_DEV_XGXS) 2419 return (EINVAL); 2420 2421 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2422 mmd, mid->reg_num, mid->val_in); 2423 } else 2424 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2425 mid->reg_num & 0x1f, 2426 mid->val_in); 2427 break; 2428 } 2429 case CHELSIO_SETREG: { 2430 struct ch_reg *edata = (struct ch_reg *)data; 2431 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2432 return (EFAULT); 2433 t3_write_reg(sc, edata->addr, edata->val); 2434 break; 2435 } 2436 case CHELSIO_GETREG: { 2437 struct ch_reg *edata = (struct ch_reg *)data; 2438 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2439 return (EFAULT); 2440 edata->val = t3_read_reg(sc, edata->addr); 2441 break; 2442 } 2443 case CHELSIO_GET_SGE_CONTEXT: { 2444 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2445 mtx_lock_spin(&sc->sge.reg_lock); 2446 switch (ecntxt->cntxt_type) { 2447 case CNTXT_TYPE_EGRESS: 2448 error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2449 ecntxt->data); 2450 break; 2451 case CNTXT_TYPE_FL: 2452 error = -t3_sge_read_fl(sc, ecntxt->cntxt_id, 2453 ecntxt->data); 2454 break; 2455 case CNTXT_TYPE_RSP: 2456 error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2457 ecntxt->data); 2458 break; 2459 case CNTXT_TYPE_CQ: 2460 error = -t3_sge_read_cq(sc, ecntxt->cntxt_id, 2461 ecntxt->data); 2462 break; 2463 default: 2464 error = EINVAL; 2465 break; 2466 } 2467 mtx_unlock_spin(&sc->sge.reg_lock); 2468 break; 2469 } 2470 case CHELSIO_GET_SGE_DESC: { 2471 struct ch_desc *edesc = (struct ch_desc *)data; 2472 int ret; 2473 if (edesc->queue_num >= SGE_QSETS * 6) 2474 return (EINVAL); 2475 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2476 edesc->queue_num % 6, edesc->idx, edesc->data); 2477 if (ret < 0) 2478 return (EINVAL); 2479 edesc->size = ret; 2480 break; 2481 } 2482 case CHELSIO_GET_QSET_PARAMS: { 2483 struct qset_params *q; 2484 struct ch_qset_params *t = (struct ch_qset_params *)data; 2485 int q1 = pi->first_qset; 2486 int nqsets = pi->nqsets; 2487 int i; 2488 2489 if (t->qset_idx >= nqsets) 2490 return EINVAL; 2491 2492 i = q1 + t->qset_idx; 2493 q = &sc->params.sge.qset[i]; 2494 t->rspq_size = q->rspq_size; 2495 t->txq_size[0] = q->txq_size[0]; 2496 t->txq_size[1] = q->txq_size[1]; 2497 t->txq_size[2] = q->txq_size[2]; 2498 t->fl_size[0] = q->fl_size; 2499 t->fl_size[1] = q->jumbo_size; 2500 t->polling = q->polling; 2501 t->lro = q->lro; 2502 t->intr_lat = q->coalesce_usecs; 2503 t->cong_thres = q->cong_thres; 2504 t->qnum = i; 2505 2506 if (sc->flags & USING_MSIX) 2507 t->vector = rman_get_start(sc->msix_irq_res[i]); 2508 else 2509 t->vector = rman_get_start(sc->irq_res); 2510 2511 break; 2512 } 2513 case CHELSIO_GET_QSET_NUM: { 2514 struct ch_reg *edata = (struct ch_reg *)data; 2515 edata->val = pi->nqsets; 2516 break; 2517 } 2518 case CHELSIO_LOAD_FW: { 2519 uint8_t *fw_data; 2520 uint32_t vers; 2521 struct ch_mem_range *t = (struct ch_mem_range *)data; 2522 2523 /* 2524 * You're allowed to load a firmware only before FULL_INIT_DONE 2525 * 2526 * FW_UPTODATE is also set so the rest of the initialization 2527 * will not overwrite what was loaded here. This gives you the 2528 * flexibility to load any firmware (and maybe shoot yourself in 2529 * the foot). 2530 */ 2531 2532 ADAPTER_LOCK(sc); 2533 if (sc->open_device_map || sc->flags & FULL_INIT_DONE) { 2534 ADAPTER_UNLOCK(sc); 2535 return (EBUSY); 2536 } 2537 2538 fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2539 if (!fw_data) 2540 error = ENOMEM; 2541 else 2542 error = copyin(t->buf, fw_data, t->len); 2543 2544 if (!error) 2545 error = -t3_load_fw(sc, fw_data, t->len); 2546 2547 if (t3_get_fw_version(sc, &vers) == 0) { 2548 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), 2549 "%d.%d.%d", G_FW_VERSION_MAJOR(vers), 2550 G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); 2551 } 2552 2553 if (!error) 2554 sc->flags |= FW_UPTODATE; 2555 2556 free(fw_data, M_DEVBUF); 2557 ADAPTER_UNLOCK(sc); 2558 break; 2559 } 2560 case CHELSIO_LOAD_BOOT: { 2561 uint8_t *boot_data; 2562 struct ch_mem_range *t = (struct ch_mem_range *)data; 2563 2564 boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2565 if (!boot_data) 2566 return ENOMEM; 2567 2568 error = copyin(t->buf, boot_data, t->len); 2569 if (!error) 2570 error = -t3_load_boot(sc, boot_data, t->len); 2571 2572 free(boot_data, M_DEVBUF); 2573 break; 2574 } 2575 case CHELSIO_GET_PM: { 2576 struct ch_pm *m = (struct ch_pm *)data; 2577 struct tp_params *p = &sc->params.tp; 2578 2579 if (!is_offload(sc)) 2580 return (EOPNOTSUPP); 2581 2582 m->tx_pg_sz = p->tx_pg_size; 2583 m->tx_num_pg = p->tx_num_pgs; 2584 m->rx_pg_sz = p->rx_pg_size; 2585 m->rx_num_pg = p->rx_num_pgs; 2586 m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; 2587 2588 break; 2589 } 2590 case CHELSIO_SET_PM: { 2591 struct ch_pm *m = (struct ch_pm *)data; 2592 struct tp_params *p = &sc->params.tp; 2593 2594 if (!is_offload(sc)) 2595 return (EOPNOTSUPP); 2596 if (sc->flags & FULL_INIT_DONE) 2597 return (EBUSY); 2598 2599 if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) || 2600 !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1))) 2601 return (EINVAL); /* not power of 2 */ 2602 if (!(m->rx_pg_sz & 0x14000)) 2603 return (EINVAL); /* not 16KB or 64KB */ 2604 if (!(m->tx_pg_sz & 0x1554000)) 2605 return (EINVAL); 2606 if (m->tx_num_pg == -1) 2607 m->tx_num_pg = p->tx_num_pgs; 2608 if (m->rx_num_pg == -1) 2609 m->rx_num_pg = p->rx_num_pgs; 2610 if (m->tx_num_pg % 24 || m->rx_num_pg % 24) 2611 return (EINVAL); 2612 if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size || 2613 m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size) 2614 return (EINVAL); 2615 2616 p->rx_pg_size = m->rx_pg_sz; 2617 p->tx_pg_size = m->tx_pg_sz; 2618 p->rx_num_pgs = m->rx_num_pg; 2619 p->tx_num_pgs = m->tx_num_pg; 2620 break; 2621 } 2622 case CHELSIO_SETMTUTAB: { 2623 struct ch_mtus *m = (struct ch_mtus *)data; 2624 int i; 2625 2626 if (!is_offload(sc)) 2627 return (EOPNOTSUPP); 2628 if (offload_running(sc)) 2629 return (EBUSY); 2630 if (m->nmtus != NMTUS) 2631 return (EINVAL); 2632 if (m->mtus[0] < 81) /* accommodate SACK */ 2633 return (EINVAL); 2634 2635 /* 2636 * MTUs must be in ascending order 2637 */ 2638 for (i = 1; i < NMTUS; ++i) 2639 if (m->mtus[i] < m->mtus[i - 1]) 2640 return (EINVAL); 2641 2642 memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus)); 2643 break; 2644 } 2645 case CHELSIO_GETMTUTAB: { 2646 struct ch_mtus *m = (struct ch_mtus *)data; 2647 2648 if (!is_offload(sc)) 2649 return (EOPNOTSUPP); 2650 2651 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2652 m->nmtus = NMTUS; 2653 break; 2654 } 2655 case CHELSIO_GET_MEM: { 2656 struct ch_mem_range *t = (struct ch_mem_range *)data; 2657 struct mc7 *mem; 2658 uint8_t *useraddr; 2659 u64 buf[32]; 2660 2661 /* 2662 * Use these to avoid modifying len/addr in the the return 2663 * struct 2664 */ 2665 uint32_t len = t->len, addr = t->addr; 2666 2667 if (!is_offload(sc)) 2668 return (EOPNOTSUPP); 2669 if (!(sc->flags & FULL_INIT_DONE)) 2670 return (EIO); /* need the memory controllers */ 2671 if ((addr & 0x7) || (len & 0x7)) 2672 return (EINVAL); 2673 if (t->mem_id == MEM_CM) 2674 mem = &sc->cm; 2675 else if (t->mem_id == MEM_PMRX) 2676 mem = &sc->pmrx; 2677 else if (t->mem_id == MEM_PMTX) 2678 mem = &sc->pmtx; 2679 else 2680 return (EINVAL); 2681 2682 /* 2683 * Version scheme: 2684 * bits 0..9: chip version 2685 * bits 10..15: chip revision 2686 */ 2687 t->version = 3 | (sc->params.rev << 10); 2688 2689 /* 2690 * Read 256 bytes at a time as len can be large and we don't 2691 * want to use huge intermediate buffers. 2692 */ 2693 useraddr = (uint8_t *)t->buf; 2694 while (len) { 2695 unsigned int chunk = min(len, sizeof(buf)); 2696 2697 error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf); 2698 if (error) 2699 return (-error); 2700 if (copyout(buf, useraddr, chunk)) 2701 return (EFAULT); 2702 useraddr += chunk; 2703 addr += chunk; 2704 len -= chunk; 2705 } 2706 break; 2707 } 2708 case CHELSIO_READ_TCAM_WORD: { 2709 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2710 2711 if (!is_offload(sc)) 2712 return (EOPNOTSUPP); 2713 if (!(sc->flags & FULL_INIT_DONE)) 2714 return (EIO); /* need MC5 */ 2715 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2716 break; 2717 } 2718 case CHELSIO_SET_TRACE_FILTER: { 2719 struct ch_trace *t = (struct ch_trace *)data; 2720 const struct trace_params *tp; 2721 2722 tp = (const struct trace_params *)&t->sip; 2723 if (t->config_tx) 2724 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2725 t->trace_tx); 2726 if (t->config_rx) 2727 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2728 t->trace_rx); 2729 break; 2730 } 2731 case CHELSIO_SET_PKTSCHED: { 2732 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2733 if (sc->open_device_map == 0) 2734 return (EAGAIN); 2735 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2736 p->binding); 2737 break; 2738 } 2739 case CHELSIO_IFCONF_GETREGS: { 2740 struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data; 2741 int reglen = cxgb_get_regs_len(); 2742 uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT); 2743 if (buf == NULL) { 2744 return (ENOMEM); 2745 } 2746 if (regs->len > reglen) 2747 regs->len = reglen; 2748 else if (regs->len < reglen) 2749 error = E2BIG; 2750 2751 if (!error) { 2752 cxgb_get_regs(sc, regs, buf); 2753 error = copyout(buf, regs->data, reglen); 2754 } 2755 free(buf, M_DEVBUF); 2756 2757 break; 2758 } 2759 case CHELSIO_SET_HW_SCHED: { 2760 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2761 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2762 2763 if ((sc->flags & FULL_INIT_DONE) == 0) 2764 return (EAGAIN); /* need TP to be initialized */ 2765 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2766 !in_range(t->channel, 0, 1) || 2767 !in_range(t->kbps, 0, 10000000) || 2768 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 2769 !in_range(t->flow_ipg, 0, 2770 dack_ticks_to_usec(sc, 0x7ff))) 2771 return (EINVAL); 2772 2773 if (t->kbps >= 0) { 2774 error = t3_config_sched(sc, t->kbps, t->sched); 2775 if (error < 0) 2776 return (-error); 2777 } 2778 if (t->class_ipg >= 0) 2779 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 2780 if (t->flow_ipg >= 0) { 2781 t->flow_ipg *= 1000; /* us -> ns */ 2782 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 2783 } 2784 if (t->mode >= 0) { 2785 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 2786 2787 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2788 bit, t->mode ? bit : 0); 2789 } 2790 if (t->channel >= 0) 2791 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2792 1 << t->sched, t->channel << t->sched); 2793 break; 2794 } 2795 case CHELSIO_GET_EEPROM: { 2796 int i; 2797 struct ch_eeprom *e = (struct ch_eeprom *)data; 2798 uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT); 2799 2800 if (buf == NULL) { 2801 return (ENOMEM); 2802 } 2803 e->magic = EEPROM_MAGIC; 2804 for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4) 2805 error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]); 2806 2807 if (!error) 2808 error = copyout(buf + e->offset, e->data, e->len); 2809 2810 free(buf, M_DEVBUF); 2811 break; 2812 } 2813 case CHELSIO_CLEAR_STATS: { 2814 if (!(sc->flags & FULL_INIT_DONE)) 2815 return EAGAIN; 2816 2817 PORT_LOCK(pi); 2818 t3_mac_update_stats(&pi->mac); 2819 memset(&pi->mac.stats, 0, sizeof(pi->mac.stats)); 2820 PORT_UNLOCK(pi); 2821 break; 2822 } 2823 default: 2824 return (EOPNOTSUPP); 2825 break; 2826 } 2827 2828 return (error); 2829} 2830 2831static __inline void 2832reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 2833 unsigned int end) 2834{ 2835 uint32_t *p = (uint32_t *)(buf + start); 2836 2837 for ( ; start <= end; start += sizeof(uint32_t)) 2838 *p++ = t3_read_reg(ap, start); 2839} 2840 2841#define T3_REGMAP_SIZE (3 * 1024) 2842static int 2843cxgb_get_regs_len(void) 2844{ 2845 return T3_REGMAP_SIZE; 2846} 2847 2848static void 2849cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf) 2850{ 2851 2852 /* 2853 * Version scheme: 2854 * bits 0..9: chip version 2855 * bits 10..15: chip revision 2856 * bit 31: set for PCIe cards 2857 */ 2858 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 2859 2860 /* 2861 * We skip the MAC statistics registers because they are clear-on-read. 2862 * Also reading multi-register stats would need to synchronize with the 2863 * periodic mac stats accumulation. Hard to justify the complexity. 2864 */ 2865 memset(buf, 0, cxgb_get_regs_len()); 2866 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 2867 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 2868 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 2869 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 2870 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 2871 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 2872 XGM_REG(A_XGM_SERDES_STAT3, 1)); 2873 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 2874 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 2875} 2876 2877 2878MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 2879