cxgb_main.c revision 182679
1/************************************************************************** 2 3Copyright (c) 2007-2008, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28***************************************************************************/ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_main.c 182679 2008-09-02 07:47:14Z kmacy $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/module.h> 38#include <sys/pciio.h> 39#include <sys/conf.h> 40#include <machine/bus.h> 41#include <machine/resource.h> 42#include <sys/bus_dma.h> 43#include <sys/ktr.h> 44#include <sys/rman.h> 45#include <sys/ioccom.h> 46#include <sys/mbuf.h> 47#include <sys/linker.h> 48#include <sys/firmware.h> 49#include <sys/socket.h> 50#include <sys/sockio.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <sys/syslog.h> 54#include <sys/queue.h> 55#include <sys/taskqueue.h> 56#include <sys/proc.h> 57 58#include <net/bpf.h> 59#include <net/ethernet.h> 60#include <net/if.h> 61#include <net/if_arp.h> 62#include <net/if_dl.h> 63#include <net/if_media.h> 64#include <net/if_types.h> 65#include <net/if_vlan_var.h> 66 67#include <netinet/in_systm.h> 68#include <netinet/in.h> 69#include <netinet/if_ether.h> 70#include <netinet/ip.h> 71#include <netinet/ip.h> 72#include <netinet/tcp.h> 73#include <netinet/udp.h> 74 75#include <dev/pci/pcireg.h> 76#include <dev/pci/pcivar.h> 77#include <dev/pci/pci_private.h> 78 79#ifdef CONFIG_DEFINED 80#include <cxgb_include.h> 81#else 82#include <dev/cxgb/cxgb_include.h> 83#endif 84 85#ifdef PRIV_SUPPORTED 86#include <sys/priv.h> 87#endif 88 89#ifdef IFNET_MULTIQUEUE 90#include <machine/intr_machdep.h> 91#endif 92 93static int cxgb_setup_msix(adapter_t *, int); 94static void cxgb_teardown_msix(adapter_t *); 95static void cxgb_init(void *); 96static void cxgb_init_locked(struct port_info *); 97static void cxgb_stop_locked(struct port_info *); 98static void cxgb_set_rxmode(struct port_info *); 99static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 100static int cxgb_media_change(struct ifnet *); 101static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 102static int setup_sge_qsets(adapter_t *); 103static void cxgb_async_intr(void *); 104static void cxgb_ext_intr_handler(void *, int); 105static void cxgb_tick_handler(void *, int); 106static void cxgb_down_locked(struct adapter *sc); 107static void cxgb_tick(void *); 108static void setup_rss(adapter_t *sc); 109 110/* Attachment glue for the PCI controller end of the device. Each port of 111 * the device is attached separately, as defined later. 112 */ 113static int cxgb_controller_probe(device_t); 114static int cxgb_controller_attach(device_t); 115static int cxgb_controller_detach(device_t); 116static void cxgb_free(struct adapter *); 117static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 118 unsigned int end); 119static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf); 120static int cxgb_get_regs_len(void); 121static int offload_open(struct port_info *pi); 122static void touch_bars(device_t dev); 123static int offload_close(struct t3cdev *tdev); 124static void cxgb_link_start(struct port_info *p); 125 126static device_method_t cxgb_controller_methods[] = { 127 DEVMETHOD(device_probe, cxgb_controller_probe), 128 DEVMETHOD(device_attach, cxgb_controller_attach), 129 DEVMETHOD(device_detach, cxgb_controller_detach), 130 131 /* bus interface */ 132 DEVMETHOD(bus_print_child, bus_generic_print_child), 133 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 134 135 { 0, 0 } 136}; 137 138static driver_t cxgb_controller_driver = { 139 "cxgbc", 140 cxgb_controller_methods, 141 sizeof(struct adapter) 142}; 143 144static devclass_t cxgb_controller_devclass; 145DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 146 147/* 148 * Attachment glue for the ports. Attachment is done directly to the 149 * controller device. 150 */ 151static int cxgb_port_probe(device_t); 152static int cxgb_port_attach(device_t); 153static int cxgb_port_detach(device_t); 154 155static device_method_t cxgb_port_methods[] = { 156 DEVMETHOD(device_probe, cxgb_port_probe), 157 DEVMETHOD(device_attach, cxgb_port_attach), 158 DEVMETHOD(device_detach, cxgb_port_detach), 159 { 0, 0 } 160}; 161 162static driver_t cxgb_port_driver = { 163 "cxgb", 164 cxgb_port_methods, 165 0 166}; 167 168static d_ioctl_t cxgb_extension_ioctl; 169static d_open_t cxgb_extension_open; 170static d_close_t cxgb_extension_close; 171 172static struct cdevsw cxgb_cdevsw = { 173 .d_version = D_VERSION, 174 .d_flags = 0, 175 .d_open = cxgb_extension_open, 176 .d_close = cxgb_extension_close, 177 .d_ioctl = cxgb_extension_ioctl, 178 .d_name = "cxgb", 179}; 180 181static devclass_t cxgb_port_devclass; 182DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 183 184#define SGE_MSIX_COUNT (SGE_QSETS + 1) 185 186/* 187 * The driver uses the best interrupt scheme available on a platform in the 188 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 189 * of these schemes the driver may consider as follows: 190 * 191 * msi = 2: choose from among all three options 192 * msi = 1 : only consider MSI and pin interrupts 193 * msi = 0: force pin interrupts 194 */ 195static int msi_allowed = 2; 196 197TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 198SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 199SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 200 "MSI-X, MSI, INTx selector"); 201 202/* 203 * The driver enables offload as a default. 204 * To disable it, use ofld_disable = 1. 205 */ 206static int ofld_disable = 0; 207TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 208SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 209 "disable ULP offload"); 210 211/* 212 * The driver uses an auto-queue algorithm by default. 213 * To disable it and force a single queue-set per port, use singleq = 1. 214 */ 215static int singleq = 0; 216TUNABLE_INT("hw.cxgb.singleq", &singleq); 217SYSCTL_UINT(_hw_cxgb, OID_AUTO, singleq, CTLFLAG_RDTUN, &singleq, 0, 218 "use a single queue-set per port"); 219 220 221/* 222 * The driver uses an auto-queue algorithm by default. 223 * To disable it and force a single queue-set per port, use singleq = 1. 224 */ 225static int force_fw_update = 0; 226TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 227SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 228 "update firmware even if up to date"); 229 230int cxgb_use_16k_clusters = 0; 231TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 232SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 233 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 234 235enum { 236 MAX_TXQ_ENTRIES = 16384, 237 MAX_CTRL_TXQ_ENTRIES = 1024, 238 MAX_RSPQ_ENTRIES = 16384, 239 MAX_RX_BUFFERS = 16384, 240 MAX_RX_JUMBO_BUFFERS = 16384, 241 MIN_TXQ_ENTRIES = 4, 242 MIN_CTRL_TXQ_ENTRIES = 4, 243 MIN_RSPQ_ENTRIES = 32, 244 MIN_FL_ENTRIES = 32, 245 MIN_FL_JUMBO_ENTRIES = 32 246}; 247 248struct filter_info { 249 u32 sip; 250 u32 sip_mask; 251 u32 dip; 252 u16 sport; 253 u16 dport; 254 u32 vlan:12; 255 u32 vlan_prio:3; 256 u32 mac_hit:1; 257 u32 mac_idx:4; 258 u32 mac_vld:1; 259 u32 pkt_type:2; 260 u32 report_filter_id:1; 261 u32 pass:1; 262 u32 rss:1; 263 u32 qset:3; 264 u32 locked:1; 265 u32 valid:1; 266}; 267 268enum { FILTER_NO_VLAN_PRI = 7 }; 269 270#define EEPROM_MAGIC 0x38E2F10C 271 272#define PORT_MASK ((1 << MAX_NPORTS) - 1) 273 274/* Table for probing the cards. The desc field isn't actually used */ 275struct cxgb_ident { 276 uint16_t vendor; 277 uint16_t device; 278 int index; 279 char *desc; 280} cxgb_identifiers[] = { 281 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 282 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 283 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 284 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 285 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 286 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 287 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 288 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 289 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 290 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 291 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 292 {0, 0, 0, NULL} 293}; 294 295static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 296 297 298void 299cxgb_log_tcb(struct adapter *sc, unsigned int tid) 300{ 301 char buf[TCB_SIZE]; 302 uint64_t *tcb = (uint64_t *)buf; 303 int i, error; 304 struct mc7 *mem = &sc->cm; 305 306 error = t3_mc7_bd_read(mem, tid*TCB_SIZE/8, TCB_SIZE/8, tcb); 307 if (error) 308 printf("cxgb_tcb_log failed\n"); 309 310 CTR1(KTR_CXGB, "TCB tid=%u", tid); 311 for (i = 0; i < TCB_SIZE / 32; i++) { 312 CTR5(KTR_CXGB, "%1d: %08x %08x %08x %08x", 313 i, (uint32_t)tcb[1], (uint32_t)(tcb[1] >> 32), 314 (uint32_t)tcb[0], (uint32_t)(tcb[0] >> 32)); 315 tcb += 2; 316 CTR4(KTR_CXGB, " %08x %08x %08x %08x", 317 (uint32_t)tcb[1], (uint32_t)(tcb[1] >> 32), 318 (uint32_t)tcb[0], (uint32_t)(tcb[0] >> 32)); 319 tcb += 2; 320 } 321} 322 323static __inline char 324t3rev2char(struct adapter *adapter) 325{ 326 char rev = 'z'; 327 328 switch(adapter->params.rev) { 329 case T3_REV_A: 330 rev = 'a'; 331 break; 332 case T3_REV_B: 333 case T3_REV_B2: 334 rev = 'b'; 335 break; 336 case T3_REV_C: 337 rev = 'c'; 338 break; 339 } 340 return rev; 341} 342 343static struct cxgb_ident * 344cxgb_get_ident(device_t dev) 345{ 346 struct cxgb_ident *id; 347 348 for (id = cxgb_identifiers; id->desc != NULL; id++) { 349 if ((id->vendor == pci_get_vendor(dev)) && 350 (id->device == pci_get_device(dev))) { 351 return (id); 352 } 353 } 354 return (NULL); 355} 356 357static const struct adapter_info * 358cxgb_get_adapter_info(device_t dev) 359{ 360 struct cxgb_ident *id; 361 const struct adapter_info *ai; 362 363 id = cxgb_get_ident(dev); 364 if (id == NULL) 365 return (NULL); 366 367 ai = t3_get_adapter_info(id->index); 368 369 return (ai); 370} 371 372static int 373cxgb_controller_probe(device_t dev) 374{ 375 const struct adapter_info *ai; 376 char *ports, buf[80]; 377 int nports; 378 379 ai = cxgb_get_adapter_info(dev); 380 if (ai == NULL) 381 return (ENXIO); 382 383 nports = ai->nports0 + ai->nports1; 384 if (nports == 1) 385 ports = "port"; 386 else 387 ports = "ports"; 388 389 snprintf(buf, sizeof(buf), "%s RNIC, %d %s", ai->desc, nports, ports); 390 device_set_desc_copy(dev, buf); 391 return (BUS_PROBE_DEFAULT); 392} 393 394#define FW_FNAME "cxgb_t3fw" 395#define TPEEPROM_NAME "t3b_tp_eeprom" 396#define TPSRAM_NAME "t3b_protocol_sram" 397 398static int 399upgrade_fw(adapter_t *sc) 400{ 401#ifdef FIRMWARE_LATEST 402 const struct firmware *fw; 403#else 404 struct firmware *fw; 405#endif 406 int status; 407 408 if ((fw = firmware_get(FW_FNAME)) == NULL) { 409 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 410 return (ENOENT); 411 } else 412 device_printf(sc->dev, "updating firmware on card\n"); 413 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 414 415 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status); 416 417 firmware_put(fw, FIRMWARE_UNLOAD); 418 419 return (status); 420} 421 422static int 423cxgb_controller_attach(device_t dev) 424{ 425 device_t child; 426 const struct adapter_info *ai; 427 struct adapter *sc; 428 int i, error = 0; 429 uint32_t vers; 430 int port_qsets = 1; 431#ifdef MSI_SUPPORTED 432 int msi_needed, reg; 433#endif 434 int must_load = 0; 435 sc = device_get_softc(dev); 436 sc->dev = dev; 437 sc->msi_count = 0; 438 ai = cxgb_get_adapter_info(dev); 439 440 /* 441 * XXX not really related but a recent addition 442 */ 443#ifdef MSI_SUPPORTED 444 /* find the PCIe link width and set max read request to 4KB*/ 445 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 446 uint16_t lnk, pectl; 447 lnk = pci_read_config(dev, reg + 0x12, 2); 448 sc->link_width = (lnk >> 4) & 0x3f; 449 450 pectl = pci_read_config(dev, reg + 0x8, 2); 451 pectl = (pectl & ~0x7000) | (5 << 12); 452 pci_write_config(dev, reg + 0x8, pectl, 2); 453 } 454 455 if (sc->link_width != 0 && sc->link_width <= 4 && 456 (ai->nports0 + ai->nports1) <= 2) { 457 device_printf(sc->dev, 458 "PCIe x%d Link, expect reduced performance\n", 459 sc->link_width); 460 } 461#endif 462 touch_bars(dev); 463 pci_enable_busmaster(dev); 464 /* 465 * Allocate the registers and make them available to the driver. 466 * The registers that we care about for NIC mode are in BAR 0 467 */ 468 sc->regs_rid = PCIR_BAR(0); 469 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 470 &sc->regs_rid, RF_ACTIVE)) == NULL) { 471 device_printf(dev, "Cannot allocate BAR region 0\n"); 472 return (ENXIO); 473 } 474 sc->udbs_rid = PCIR_BAR(2); 475 if ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 476 &sc->udbs_rid, RF_ACTIVE)) == NULL) { 477 device_printf(dev, "Cannot allocate BAR region 1\n"); 478 error = ENXIO; 479 goto out; 480 } 481 482 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 483 device_get_unit(dev)); 484 ADAPTER_LOCK_INIT(sc, sc->lockbuf); 485 486 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 487 device_get_unit(dev)); 488 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 489 device_get_unit(dev)); 490 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 491 device_get_unit(dev)); 492 493 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 494 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 495 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 496 497 sc->bt = rman_get_bustag(sc->regs_res); 498 sc->bh = rman_get_bushandle(sc->regs_res); 499 sc->mmio_len = rman_get_size(sc->regs_res); 500 501 if (t3_prep_adapter(sc, ai, 1) < 0) { 502 printf("prep adapter failed\n"); 503 error = ENODEV; 504 goto out; 505 } 506 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 507 * enough messages for the queue sets. If that fails, try falling 508 * back to MSI. If that fails, then try falling back to the legacy 509 * interrupt pin model. 510 */ 511#ifdef MSI_SUPPORTED 512 513 sc->msix_regs_rid = 0x20; 514 if ((msi_allowed >= 2) && 515 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 516 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 517 518 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 519 520 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 521 (sc->msi_count != msi_needed)) { 522 device_printf(dev, "msix allocation failed - msi_count = %d" 523 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 524 msi_needed, error); 525 sc->msi_count = 0; 526 pci_release_msi(dev); 527 bus_release_resource(dev, SYS_RES_MEMORY, 528 sc->msix_regs_rid, sc->msix_regs_res); 529 sc->msix_regs_res = NULL; 530 } else { 531 sc->flags |= USING_MSIX; 532 sc->cxgb_intr = t3_intr_msix; 533 } 534 } 535 536 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 537 sc->msi_count = 1; 538 if (pci_alloc_msi(dev, &sc->msi_count)) { 539 device_printf(dev, "alloc msi failed - will try INTx\n"); 540 sc->msi_count = 0; 541 pci_release_msi(dev); 542 } else { 543 sc->flags |= USING_MSI; 544 sc->irq_rid = 1; 545 sc->cxgb_intr = t3_intr_msi; 546 } 547 } 548#endif 549 if (sc->msi_count == 0) { 550 device_printf(dev, "using line interrupts\n"); 551 sc->irq_rid = 0; 552 sc->cxgb_intr = t3b_intr; 553 } 554 555 if ((sc->flags & USING_MSIX) && !singleq) 556 port_qsets = min((SGE_QSETS/(sc)->params.nports), mp_ncpus); 557 558 /* Create a private taskqueue thread for handling driver events */ 559#ifdef TASKQUEUE_CURRENT 560 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 561 taskqueue_thread_enqueue, &sc->tq); 562#else 563 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, 564 taskqueue_thread_enqueue, &sc->tq); 565#endif 566 if (sc->tq == NULL) { 567 device_printf(dev, "failed to allocate controller task queue\n"); 568 goto out; 569 } 570 571 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 572 device_get_nameunit(dev)); 573 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 574 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 575 576 577 /* Create a periodic callout for checking adapter status */ 578 callout_init(&sc->cxgb_tick_ch, TRUE); 579 580 if ((t3_check_fw_version(sc, &must_load) != 0 && must_load) || force_fw_update) { 581 /* 582 * Warn user that a firmware update will be attempted in init. 583 */ 584 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 585 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 586 sc->flags &= ~FW_UPTODATE; 587 } else { 588 sc->flags |= FW_UPTODATE; 589 } 590 591 if (t3_check_tpsram_version(sc, &must_load) != 0 && must_load) { 592 /* 593 * Warn user that a firmware update will be attempted in init. 594 */ 595 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 596 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 597 sc->flags &= ~TPS_UPTODATE; 598 } else { 599 sc->flags |= TPS_UPTODATE; 600 } 601 602 /* 603 * Create a child device for each MAC. The ethernet attachment 604 * will be done in these children. 605 */ 606 for (i = 0; i < (sc)->params.nports; i++) { 607 struct port_info *pi; 608 609 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 610 device_printf(dev, "failed to add child port\n"); 611 error = EINVAL; 612 goto out; 613 } 614 pi = &sc->port[i]; 615 pi->adapter = sc; 616 pi->nqsets = port_qsets; 617 pi->first_qset = i*port_qsets; 618 pi->port_id = i; 619 pi->tx_chan = i >= ai->nports0; 620 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 621 sc->rxpkt_map[pi->txpkt_intf] = i; 622 sc->port[i].tx_chan = i >= ai->nports0; 623 sc->portdev[i] = child; 624 device_set_softc(child, pi); 625 } 626 if ((error = bus_generic_attach(dev)) != 0) 627 goto out; 628 629 /* initialize sge private state */ 630 t3_sge_init_adapter(sc); 631 632 t3_led_ready(sc); 633 634 cxgb_offload_init(); 635 if (is_offload(sc)) { 636 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 637 cxgb_adapter_ofld(sc); 638 } 639 error = t3_get_fw_version(sc, &vers); 640 if (error) 641 goto out; 642 643 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 644 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 645 G_FW_VERSION_MICRO(vers)); 646 647 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 648 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 649 t3_add_attach_sysctls(sc); 650out: 651 if (error) 652 cxgb_free(sc); 653 654 return (error); 655} 656 657static int 658cxgb_controller_detach(device_t dev) 659{ 660 struct adapter *sc; 661 662 sc = device_get_softc(dev); 663 664 cxgb_free(sc); 665 666 return (0); 667} 668 669static void 670cxgb_free(struct adapter *sc) 671{ 672 int i; 673 674 ADAPTER_LOCK(sc); 675 sc->flags |= CXGB_SHUTDOWN; 676 ADAPTER_UNLOCK(sc); 677 cxgb_pcpu_shutdown_threads(sc); 678 ADAPTER_LOCK(sc); 679 680/* 681 * drops the lock 682 */ 683 cxgb_down_locked(sc); 684 685#ifdef MSI_SUPPORTED 686 if (sc->flags & (USING_MSI | USING_MSIX)) { 687 device_printf(sc->dev, "releasing msi message(s)\n"); 688 pci_release_msi(sc->dev); 689 } else { 690 device_printf(sc->dev, "no msi message to release\n"); 691 } 692#endif 693 if (sc->msix_regs_res != NULL) { 694 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 695 sc->msix_regs_res); 696 } 697 698 t3_sge_deinit_sw(sc); 699 /* 700 * Wait for last callout 701 */ 702 703 DELAY(hz*100); 704 705 for (i = 0; i < (sc)->params.nports; ++i) { 706 if (sc->portdev[i] != NULL) 707 device_delete_child(sc->dev, sc->portdev[i]); 708 } 709 710 bus_generic_detach(sc->dev); 711 if (sc->tq != NULL) { 712 taskqueue_free(sc->tq); 713 sc->tq = NULL; 714 } 715 716 if (is_offload(sc)) { 717 cxgb_adapter_unofld(sc); 718 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 719 offload_close(&sc->tdev); 720 else 721 printf("cxgb_free: DEVMAP_BIT not set\n"); 722 } else 723 printf("not offloading set\n"); 724#ifdef notyet 725 if (sc->flags & CXGB_OFLD_INIT) 726 cxgb_offload_deactivate(sc); 727#endif 728 free(sc->filters, M_DEVBUF); 729 t3_sge_free(sc); 730 731 cxgb_offload_exit(); 732 733 if (sc->udbs_res != NULL) 734 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 735 sc->udbs_res); 736 737 if (sc->regs_res != NULL) 738 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 739 sc->regs_res); 740 741 MTX_DESTROY(&sc->mdio_lock); 742 MTX_DESTROY(&sc->sge.reg_lock); 743 MTX_DESTROY(&sc->elmer_lock); 744 ADAPTER_LOCK_DEINIT(sc); 745} 746 747/** 748 * setup_sge_qsets - configure SGE Tx/Rx/response queues 749 * @sc: the controller softc 750 * 751 * Determines how many sets of SGE queues to use and initializes them. 752 * We support multiple queue sets per port if we have MSI-X, otherwise 753 * just one queue set per port. 754 */ 755static int 756setup_sge_qsets(adapter_t *sc) 757{ 758 int i, j, err, irq_idx = 0, qset_idx = 0; 759 u_int ntxq = SGE_TXQ_PER_SET; 760 761 if ((err = t3_sge_alloc(sc)) != 0) { 762 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 763 return (err); 764 } 765 766 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 767 irq_idx = -1; 768 769 for (i = 0; i < (sc)->params.nports; i++) { 770 struct port_info *pi = &sc->port[i]; 771 772 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 773 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 774 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 775 &sc->params.sge.qset[qset_idx], ntxq, pi); 776 if (err) { 777 t3_free_sge_resources(sc); 778 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 779 err); 780 return (err); 781 } 782 } 783 } 784 785 return (0); 786} 787 788static void 789cxgb_teardown_msix(adapter_t *sc) 790{ 791 int i, nqsets; 792 793 for (nqsets = i = 0; i < (sc)->params.nports; i++) 794 nqsets += sc->port[i].nqsets; 795 796 for (i = 0; i < nqsets; i++) { 797 if (sc->msix_intr_tag[i] != NULL) { 798 bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 799 sc->msix_intr_tag[i]); 800 sc->msix_intr_tag[i] = NULL; 801 } 802 if (sc->msix_irq_res[i] != NULL) { 803 bus_release_resource(sc->dev, SYS_RES_IRQ, 804 sc->msix_irq_rid[i], sc->msix_irq_res[i]); 805 sc->msix_irq_res[i] = NULL; 806 } 807 } 808} 809 810static int 811cxgb_setup_msix(adapter_t *sc, int msix_count) 812{ 813 int i, j, k, nqsets, rid; 814 815 /* The first message indicates link changes and error conditions */ 816 sc->irq_rid = 1; 817 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 818 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 819 device_printf(sc->dev, "Cannot allocate msix interrupt\n"); 820 return (EINVAL); 821 } 822 823 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 824#ifdef INTR_FILTERS 825 NULL, 826#endif 827 cxgb_async_intr, sc, &sc->intr_tag)) { 828 device_printf(sc->dev, "Cannot set up interrupt\n"); 829 return (EINVAL); 830 } 831 for (i = k = 0; i < (sc)->params.nports; i++) { 832 nqsets = sc->port[i].nqsets; 833 for (j = 0; j < nqsets; j++, k++) { 834 struct sge_qset *qs = &sc->sge.qs[k]; 835 836 rid = k + 2; 837 if (cxgb_debug) 838 printf("rid=%d ", rid); 839 if ((sc->msix_irq_res[k] = bus_alloc_resource_any( 840 sc->dev, SYS_RES_IRQ, &rid, 841 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 842 device_printf(sc->dev, "Cannot allocate " 843 "interrupt for message %d\n", rid); 844 return (EINVAL); 845 } 846 sc->msix_irq_rid[k] = rid; 847 if (bus_setup_intr(sc->dev, sc->msix_irq_res[k], 848 INTR_MPSAFE|INTR_TYPE_NET, 849#ifdef INTR_FILTERS 850 NULL, 851#endif 852 t3_intr_msix, qs, &sc->msix_intr_tag[k])) { 853 device_printf(sc->dev, "Cannot set up " 854 "interrupt for message %d\n", rid); 855 return (EINVAL); 856 } 857#ifdef IFNET_MULTIQUEUE 858 if (singleq == 0) { 859 int vector = rman_get_start(sc->msix_irq_res[k]); 860 if (bootverbose) 861 device_printf(sc->dev, "binding vector=%d to cpu=%d\n", vector, k % mp_ncpus); 862 intr_bind(vector, k % mp_ncpus); 863 } 864#endif 865 } 866 } 867 868 return (0); 869} 870 871static int 872cxgb_port_probe(device_t dev) 873{ 874 struct port_info *p; 875 char buf[80]; 876 const char *desc; 877 878 p = device_get_softc(dev); 879 desc = p->phy.desc; 880 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 881 device_set_desc_copy(dev, buf); 882 return (0); 883} 884 885 886static int 887cxgb_makedev(struct port_info *pi) 888{ 889 890 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 891 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 892 893 if (pi->port_cdev == NULL) 894 return (ENOMEM); 895 896 pi->port_cdev->si_drv1 = (void *)pi; 897 898 return (0); 899} 900 901 902#ifdef TSO_SUPPORTED 903#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO) 904/* Don't enable TSO6 yet */ 905#define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_LRO) 906#else 907#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 908/* Don't enable TSO6 yet */ 909#define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) 910#define IFCAP_TSO4 0x0 911#define IFCAP_TSO6 0x0 912#define CSUM_TSO 0x0 913#endif 914 915 916static int 917cxgb_port_attach(device_t dev) 918{ 919 struct port_info *p; 920 struct ifnet *ifp; 921 int err, media_flags; 922 struct adapter *sc; 923 924 925 p = device_get_softc(dev); 926 sc = p->adapter; 927 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 928 device_get_unit(device_get_parent(dev)), p->port_id); 929 PORT_LOCK_INIT(p, p->lockbuf); 930 931 /* Allocate an ifnet object and set it up */ 932 ifp = p->ifp = if_alloc(IFT_ETHER); 933 if (ifp == NULL) { 934 device_printf(dev, "Cannot allocate ifnet\n"); 935 return (ENOMEM); 936 } 937 938 /* 939 * Note that there is currently no watchdog timer. 940 */ 941 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 942 ifp->if_init = cxgb_init; 943 ifp->if_softc = p; 944 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 945 ifp->if_ioctl = cxgb_ioctl; 946 ifp->if_start = cxgb_start; 947 948#if 0 949#ifdef IFNET_MULTIQUEUE 950 ifp->if_flags |= IFF_MULTIQ; 951 ifp->if_mq_start = cxgb_pcpu_start; 952#endif 953#endif 954 ifp->if_timer = 0; /* Disable ifnet watchdog */ 955 ifp->if_watchdog = NULL; 956 957 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 958 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 959 IFQ_SET_READY(&ifp->if_snd); 960 961 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; 962 ifp->if_capabilities |= CXGB_CAP; 963 ifp->if_capenable |= CXGB_CAP_ENABLE; 964 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); 965 /* 966 * disable TSO on 4-port - it isn't supported by the firmware yet 967 */ 968 if (p->adapter->params.nports > 2) { 969 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 970 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 971 ifp->if_hwassist &= ~CSUM_TSO; 972 } 973 974 ether_ifattach(ifp, p->hw_addr); 975 /* 976 * Only default to jumbo frames on 10GigE 977 */ 978 if (p->adapter->params.nports <= 2) 979 ifp->if_mtu = ETHERMTU_JUMBO; 980 if ((err = cxgb_makedev(p)) != 0) { 981 printf("makedev failed %d\n", err); 982 return (err); 983 } 984 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 985 cxgb_media_status); 986 987 if (!strcmp(p->phy.desc, "10GBASE-CX4")) { 988 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 989 } else if (!strcmp(p->phy.desc, "10GBASE-SR")) { 990 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 991 } else if (!strcmp(p->phy.desc, "10GBASE-R")) { 992 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 993 } else if (!strcmp(p->phy.desc, "10/100/1000BASE-T")) { 994 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 995 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 996 0, NULL); 997 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 998 0, NULL); 999 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1000 0, NULL); 1001 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1002 0, NULL); 1003 media_flags = 0; 1004 } else { 1005 printf("unsupported media type %s\n", p->phy.desc); 1006 return (ENXIO); 1007 } 1008 if (media_flags) { 1009 ifmedia_add(&p->media, media_flags, 0, NULL); 1010 ifmedia_set(&p->media, media_flags); 1011 } else { 1012 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1013 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 1014 } 1015 1016 1017 snprintf(p->taskqbuf, TASKQ_NAME_LEN, "cxgb_port_taskq%d", p->port_id); 1018#ifdef TASKQUEUE_CURRENT 1019 /* Create a port for handling TX without starvation */ 1020 p->tq = taskqueue_create(p->taskqbuf, M_NOWAIT, 1021 taskqueue_thread_enqueue, &p->tq); 1022#else 1023 /* Create a port for handling TX without starvation */ 1024 p->tq = taskqueue_create_fast(p->taskqbuf, M_NOWAIT, 1025 taskqueue_thread_enqueue, &p->tq); 1026#endif 1027 /* Get the latest mac address, User can use a LAA */ 1028 bcopy(IF_LLADDR(p->ifp), p->hw_addr, ETHER_ADDR_LEN); 1029 t3_sge_init_port(p); 1030#if defined(LINK_ATTACH) 1031 cxgb_link_start(p); 1032 t3_link_changed(sc, p->port_id); 1033#endif 1034 return (0); 1035} 1036 1037static int 1038cxgb_port_detach(device_t dev) 1039{ 1040 struct port_info *p; 1041 1042 p = device_get_softc(dev); 1043 1044 PORT_LOCK(p); 1045 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 1046 cxgb_stop_locked(p); 1047 PORT_UNLOCK(p); 1048 1049 if (p->tq != NULL) { 1050 taskqueue_drain(p->tq, &p->start_task); 1051 taskqueue_free(p->tq); 1052 p->tq = NULL; 1053 } 1054 1055 ether_ifdetach(p->ifp); 1056 printf("waiting for callout to stop ..."); 1057 DELAY(1000000); 1058 printf("done\n"); 1059 /* 1060 * the lock may be acquired in ifdetach 1061 */ 1062 PORT_LOCK_DEINIT(p); 1063 if_free(p->ifp); 1064 1065 if (p->port_cdev != NULL) 1066 destroy_dev(p->port_cdev); 1067 1068 return (0); 1069} 1070 1071void 1072t3_fatal_err(struct adapter *sc) 1073{ 1074 u_int fw_status[4]; 1075 1076 if (sc->flags & FULL_INIT_DONE) { 1077 t3_sge_stop(sc); 1078 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1079 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1080 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1081 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1082 t3_intr_disable(sc); 1083 } 1084 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1085 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1086 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1087 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1088} 1089 1090int 1091t3_os_find_pci_capability(adapter_t *sc, int cap) 1092{ 1093 device_t dev; 1094 struct pci_devinfo *dinfo; 1095 pcicfgregs *cfg; 1096 uint32_t status; 1097 uint8_t ptr; 1098 1099 dev = sc->dev; 1100 dinfo = device_get_ivars(dev); 1101 cfg = &dinfo->cfg; 1102 1103 status = pci_read_config(dev, PCIR_STATUS, 2); 1104 if (!(status & PCIM_STATUS_CAPPRESENT)) 1105 return (0); 1106 1107 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1108 case 0: 1109 case 1: 1110 ptr = PCIR_CAP_PTR; 1111 break; 1112 case 2: 1113 ptr = PCIR_CAP_PTR_2; 1114 break; 1115 default: 1116 return (0); 1117 break; 1118 } 1119 ptr = pci_read_config(dev, ptr, 1); 1120 1121 while (ptr != 0) { 1122 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1123 return (ptr); 1124 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1125 } 1126 1127 return (0); 1128} 1129 1130int 1131t3_os_pci_save_state(struct adapter *sc) 1132{ 1133 device_t dev; 1134 struct pci_devinfo *dinfo; 1135 1136 dev = sc->dev; 1137 dinfo = device_get_ivars(dev); 1138 1139 pci_cfg_save(dev, dinfo, 0); 1140 return (0); 1141} 1142 1143int 1144t3_os_pci_restore_state(struct adapter *sc) 1145{ 1146 device_t dev; 1147 struct pci_devinfo *dinfo; 1148 1149 dev = sc->dev; 1150 dinfo = device_get_ivars(dev); 1151 1152 pci_cfg_restore(dev, dinfo); 1153 return (0); 1154} 1155 1156/** 1157 * t3_os_link_changed - handle link status changes 1158 * @adapter: the adapter associated with the link change 1159 * @port_id: the port index whose limk status has changed 1160 * @link_status: the new status of the link 1161 * @speed: the new speed setting 1162 * @duplex: the new duplex setting 1163 * @fc: the new flow-control setting 1164 * 1165 * This is the OS-dependent handler for link status changes. The OS 1166 * neutral handler takes care of most of the processing for these events, 1167 * then calls this handler for any OS-specific processing. 1168 */ 1169void 1170t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1171 int duplex, int fc) 1172{ 1173 struct port_info *pi = &adapter->port[port_id]; 1174 struct cmac *mac = &adapter->port[port_id].mac; 1175 1176 if (link_status) { 1177 DELAY(10); 1178 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1179 /* Clear errors created by MAC enable */ 1180 t3_set_reg_field(adapter, 1181 A_XGM_STAT_CTRL + pi->mac.offset, 1182 F_CLRSTATS, 1); 1183 if_link_state_change(pi->ifp, LINK_STATE_UP); 1184 1185 } else { 1186 pi->phy.ops->power_down(&pi->phy, 1); 1187 t3_mac_disable(mac, MAC_DIRECTION_RX); 1188 t3_link_start(&pi->phy, mac, &pi->link_config); 1189 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1190 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 1191 } 1192} 1193 1194/** 1195 * t3_os_phymod_changed - handle PHY module changes 1196 * @phy: the PHY reporting the module change 1197 * @mod_type: new module type 1198 * 1199 * This is the OS-dependent handler for PHY module changes. It is 1200 * invoked when a PHY module is removed or inserted for any OS-specific 1201 * processing. 1202 */ 1203void t3_os_phymod_changed(struct adapter *adap, int port_id) 1204{ 1205 static const char *mod_str[] = { 1206 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown" 1207 }; 1208 1209 struct port_info *pi = &adap->port[port_id]; 1210 1211 if (pi->phy.modtype == phy_modtype_none) 1212 device_printf(adap->dev, "PHY module unplugged\n"); 1213 else { 1214 KASSERT(pi->phy.modtype < ARRAY_SIZE(mod_str), 1215 ("invalid PHY module type %d", pi->phy.modtype)); 1216 device_printf(adap->dev, "%s PHY module inserted\n", 1217 mod_str[pi->phy.modtype]); 1218 } 1219} 1220 1221/* 1222 * Interrupt-context handler for external (PHY) interrupts. 1223 */ 1224void 1225t3_os_ext_intr_handler(adapter_t *sc) 1226{ 1227 if (cxgb_debug) 1228 printf("t3_os_ext_intr_handler\n"); 1229 /* 1230 * Schedule a task to handle external interrupts as they may be slow 1231 * and we use a mutex to protect MDIO registers. We disable PHY 1232 * interrupts in the meantime and let the task reenable them when 1233 * it's done. 1234 */ 1235 ADAPTER_LOCK(sc); 1236 if (sc->slow_intr_mask) { 1237 sc->slow_intr_mask &= ~F_T3DBG; 1238 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1239 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1240 } 1241 ADAPTER_UNLOCK(sc); 1242} 1243 1244void 1245t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1246{ 1247 1248 /* 1249 * The ifnet might not be allocated before this gets called, 1250 * as this is called early on in attach by t3_prep_adapter 1251 * save the address off in the port structure 1252 */ 1253 if (cxgb_debug) 1254 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1255 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1256} 1257 1258/** 1259 * link_start - enable a port 1260 * @p: the port to enable 1261 * 1262 * Performs the MAC and PHY actions needed to enable a port. 1263 */ 1264static void 1265cxgb_link_start(struct port_info *p) 1266{ 1267 struct ifnet *ifp; 1268 struct t3_rx_mode rm; 1269 struct cmac *mac = &p->mac; 1270 int mtu, hwtagging; 1271 1272 ifp = p->ifp; 1273 1274 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN); 1275 1276 mtu = ifp->if_mtu; 1277 if (ifp->if_capenable & IFCAP_VLAN_MTU) 1278 mtu += ETHER_VLAN_ENCAP_LEN; 1279 1280 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0; 1281 1282 t3_init_rx_mode(&rm, p); 1283 if (!mac->multiport) 1284 t3_mac_reset(mac); 1285 t3_mac_set_mtu(mac, mtu); 1286 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging); 1287 t3_mac_set_address(mac, 0, p->hw_addr); 1288 t3_mac_set_rx_mode(mac, &rm); 1289 t3_link_start(&p->phy, mac, &p->link_config); 1290 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1291} 1292 1293 1294static int 1295await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1296 unsigned long n) 1297{ 1298 int attempts = 5; 1299 1300 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1301 if (!--attempts) 1302 return (ETIMEDOUT); 1303 t3_os_sleep(10); 1304 } 1305 return 0; 1306} 1307 1308static int 1309init_tp_parity(struct adapter *adap) 1310{ 1311 int i; 1312 struct mbuf *m; 1313 struct cpl_set_tcb_field *greq; 1314 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1315 1316 t3_tp_set_offload_mode(adap, 1); 1317 1318 for (i = 0; i < 16; i++) { 1319 struct cpl_smt_write_req *req; 1320 1321 m = m_gethdr(M_WAITOK, MT_DATA); 1322 req = mtod(m, struct cpl_smt_write_req *); 1323 m->m_len = m->m_pkthdr.len = sizeof(*req); 1324 memset(req, 0, sizeof(*req)); 1325 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1326 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1327 req->iff = i; 1328 t3_mgmt_tx(adap, m); 1329 } 1330 1331 for (i = 0; i < 2048; i++) { 1332 struct cpl_l2t_write_req *req; 1333 1334 m = m_gethdr(M_WAITOK, MT_DATA); 1335 req = mtod(m, struct cpl_l2t_write_req *); 1336 m->m_len = m->m_pkthdr.len = sizeof(*req); 1337 memset(req, 0, sizeof(*req)); 1338 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1339 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1340 req->params = htonl(V_L2T_W_IDX(i)); 1341 t3_mgmt_tx(adap, m); 1342 } 1343 1344 for (i = 0; i < 2048; i++) { 1345 struct cpl_rte_write_req *req; 1346 1347 m = m_gethdr(M_WAITOK, MT_DATA); 1348 req = mtod(m, struct cpl_rte_write_req *); 1349 m->m_len = m->m_pkthdr.len = sizeof(*req); 1350 memset(req, 0, sizeof(*req)); 1351 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1352 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1353 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1354 t3_mgmt_tx(adap, m); 1355 } 1356 1357 m = m_gethdr(M_WAITOK, MT_DATA); 1358 greq = mtod(m, struct cpl_set_tcb_field *); 1359 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1360 memset(greq, 0, sizeof(*greq)); 1361 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1362 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1363 greq->mask = htobe64(1); 1364 t3_mgmt_tx(adap, m); 1365 1366 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1367 t3_tp_set_offload_mode(adap, 0); 1368 return (i); 1369} 1370 1371/** 1372 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1373 * @adap: the adapter 1374 * 1375 * Sets up RSS to distribute packets to multiple receive queues. We 1376 * configure the RSS CPU lookup table to distribute to the number of HW 1377 * receive queues, and the response queue lookup table to narrow that 1378 * down to the response queues actually configured for each port. 1379 * We always configure the RSS mapping for two ports since the mapping 1380 * table has plenty of entries. 1381 */ 1382static void 1383setup_rss(adapter_t *adap) 1384{ 1385 int i; 1386 u_int nq[2]; 1387 uint8_t cpus[SGE_QSETS + 1]; 1388 uint16_t rspq_map[RSS_TABLE_SIZE]; 1389 1390 for (i = 0; i < SGE_QSETS; ++i) 1391 cpus[i] = i; 1392 cpus[SGE_QSETS] = 0xff; 1393 1394 nq[0] = nq[1] = 0; 1395 for_each_port(adap, i) { 1396 const struct port_info *pi = adap2pinfo(adap, i); 1397 1398 nq[pi->tx_chan] += pi->nqsets; 1399 } 1400 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1401 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1402 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1403 } 1404 /* Calculate the reverse RSS map table */ 1405 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1406 if (adap->rrss_map[rspq_map[i]] == 0xff) 1407 adap->rrss_map[rspq_map[i]] = i; 1408 1409 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1410 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1411 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1412 cpus, rspq_map); 1413 1414} 1415 1416/* 1417 * Sends an mbuf to an offload queue driver 1418 * after dealing with any active network taps. 1419 */ 1420static inline int 1421offload_tx(struct t3cdev *tdev, struct mbuf *m) 1422{ 1423 int ret; 1424 1425 ret = t3_offload_tx(tdev, m); 1426 return (ret); 1427} 1428 1429static int 1430write_smt_entry(struct adapter *adapter, int idx) 1431{ 1432 struct port_info *pi = &adapter->port[idx]; 1433 struct cpl_smt_write_req *req; 1434 struct mbuf *m; 1435 1436 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1437 return (ENOMEM); 1438 1439 req = mtod(m, struct cpl_smt_write_req *); 1440 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1441 1442 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1443 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1444 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1445 req->iff = idx; 1446 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1447 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1448 1449 m_set_priority(m, 1); 1450 1451 offload_tx(&adapter->tdev, m); 1452 1453 return (0); 1454} 1455 1456static int 1457init_smt(struct adapter *adapter) 1458{ 1459 int i; 1460 1461 for_each_port(adapter, i) 1462 write_smt_entry(adapter, i); 1463 return 0; 1464} 1465 1466static void 1467init_port_mtus(adapter_t *adapter) 1468{ 1469 unsigned int mtus = adapter->port[0].ifp->if_mtu; 1470 1471 if (adapter->port[1].ifp) 1472 mtus |= adapter->port[1].ifp->if_mtu << 16; 1473 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1474} 1475 1476static void 1477send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1478 int hi, int port) 1479{ 1480 struct mbuf *m; 1481 struct mngt_pktsched_wr *req; 1482 1483 m = m_gethdr(M_DONTWAIT, MT_DATA); 1484 if (m) { 1485 req = mtod(m, struct mngt_pktsched_wr *); 1486 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1487 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1488 req->sched = sched; 1489 req->idx = qidx; 1490 req->min = lo; 1491 req->max = hi; 1492 req->binding = port; 1493 m->m_len = m->m_pkthdr.len = sizeof(*req); 1494 t3_mgmt_tx(adap, m); 1495 } 1496} 1497 1498static void 1499bind_qsets(adapter_t *sc) 1500{ 1501 int i, j; 1502 1503 cxgb_pcpu_startup_threads(sc); 1504 for (i = 0; i < (sc)->params.nports; ++i) { 1505 const struct port_info *pi = adap2pinfo(sc, i); 1506 1507 for (j = 0; j < pi->nqsets; ++j) { 1508 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1509 -1, pi->tx_chan); 1510 1511 } 1512 } 1513} 1514 1515static void 1516update_tpeeprom(struct adapter *adap) 1517{ 1518#ifdef FIRMWARE_LATEST 1519 const struct firmware *tpeeprom; 1520#else 1521 struct firmware *tpeeprom; 1522#endif 1523 1524 uint32_t version; 1525 unsigned int major, minor; 1526 int ret, len; 1527 char rev; 1528 1529 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1530 1531 major = G_TP_VERSION_MAJOR(version); 1532 minor = G_TP_VERSION_MINOR(version); 1533 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1534 return; 1535 1536 rev = t3rev2char(adap); 1537 1538 tpeeprom = firmware_get(TPEEPROM_NAME); 1539 if (tpeeprom == NULL) { 1540 device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n", 1541 TPEEPROM_NAME); 1542 return; 1543 } 1544 1545 len = tpeeprom->datasize - 4; 1546 1547 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1548 if (ret) 1549 goto release_tpeeprom; 1550 1551 if (len != TP_SRAM_LEN) { 1552 device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", TPEEPROM_NAME, len, TP_SRAM_LEN); 1553 return; 1554 } 1555 1556 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1557 TP_SRAM_OFFSET); 1558 1559 if (!ret) { 1560 device_printf(adap->dev, 1561 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1562 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1563 } else 1564 device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n"); 1565 1566release_tpeeprom: 1567 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1568 1569 return; 1570} 1571 1572static int 1573update_tpsram(struct adapter *adap) 1574{ 1575#ifdef FIRMWARE_LATEST 1576 const struct firmware *tpsram; 1577#else 1578 struct firmware *tpsram; 1579#endif 1580 int ret; 1581 char rev; 1582 1583 rev = t3rev2char(adap); 1584 if (!rev) 1585 return 0; 1586 1587 update_tpeeprom(adap); 1588 1589 tpsram = firmware_get(TPSRAM_NAME); 1590 if (tpsram == NULL){ 1591 device_printf(adap->dev, "could not load TP SRAM\n"); 1592 return (EINVAL); 1593 } else 1594 device_printf(adap->dev, "updating TP SRAM\n"); 1595 1596 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1597 if (ret) 1598 goto release_tpsram; 1599 1600 ret = t3_set_proto_sram(adap, tpsram->data); 1601 if (ret) 1602 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1603 1604release_tpsram: 1605 firmware_put(tpsram, FIRMWARE_UNLOAD); 1606 1607 return ret; 1608} 1609 1610/** 1611 * cxgb_up - enable the adapter 1612 * @adap: adapter being enabled 1613 * 1614 * Called when the first port is enabled, this function performs the 1615 * actions necessary to make an adapter operational, such as completing 1616 * the initialization of HW modules, and enabling interrupts. 1617 * 1618 */ 1619static int 1620cxgb_up(struct adapter *sc) 1621{ 1622 int err = 0; 1623 1624 if ((sc->flags & FULL_INIT_DONE) == 0) { 1625 1626 if ((sc->flags & FW_UPTODATE) == 0) 1627 if ((err = upgrade_fw(sc))) 1628 goto out; 1629 if ((sc->flags & TPS_UPTODATE) == 0) 1630 if ((err = update_tpsram(sc))) 1631 goto out; 1632 err = t3_init_hw(sc, 0); 1633 if (err) 1634 goto out; 1635 1636 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1637 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1638 1639 err = setup_sge_qsets(sc); 1640 if (err) 1641 goto out; 1642 1643 setup_rss(sc); 1644 t3_add_configured_sysctls(sc); 1645 sc->flags |= FULL_INIT_DONE; 1646 } 1647 1648 t3_intr_clear(sc); 1649 1650 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1651 if ((sc->flags & USING_MSIX) == 0) { 1652 if ((sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1653 &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 1654 device_printf(sc->dev, "Cannot allocate interrupt rid=%d\n", 1655 sc->irq_rid); 1656 err = EINVAL; 1657 goto out; 1658 } 1659 device_printf(sc->dev, "allocated irq_res=%p\n", sc->irq_res); 1660 1661 if (bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE|INTR_TYPE_NET, 1662#ifdef INTR_FILTERS 1663 NULL, 1664#endif 1665 sc->cxgb_intr, sc, &sc->intr_tag)) { 1666 device_printf(sc->dev, "Cannot set up interrupt\n"); 1667 err = EINVAL; 1668 goto irq_err; 1669 } 1670 } else { 1671 cxgb_setup_msix(sc, sc->msi_count); 1672 } 1673 1674 t3_sge_start(sc); 1675 t3_intr_enable(sc); 1676 1677 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1678 is_offload(sc) && init_tp_parity(sc) == 0) 1679 sc->flags |= TP_PARITY_INIT; 1680 1681 if (sc->flags & TP_PARITY_INIT) { 1682 t3_write_reg(sc, A_TP_INT_CAUSE, 1683 F_CMCACHEPERR | F_ARPLUTPERR); 1684 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1685 } 1686 1687 1688 if (!(sc->flags & QUEUES_BOUND)) { 1689 bind_qsets(sc); 1690 sc->flags |= QUEUES_BOUND; 1691 } 1692out: 1693 return (err); 1694irq_err: 1695 CH_ERR(sc, "request_irq failed, err %d\n", err); 1696 goto out; 1697} 1698 1699 1700/* 1701 * Release resources when all the ports and offloading have been stopped. 1702 */ 1703static void 1704cxgb_down_locked(struct adapter *sc) 1705{ 1706 1707 t3_sge_stop(sc); 1708 t3_intr_disable(sc); 1709 1710 if (sc->intr_tag != NULL) { 1711 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 1712 sc->intr_tag = NULL; 1713 } 1714 if (sc->irq_res != NULL) { 1715 device_printf(sc->dev, "de-allocating interrupt irq_rid=%d irq_res=%p\n", 1716 sc->irq_rid, sc->irq_res); 1717 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 1718 sc->irq_res); 1719 sc->irq_res = NULL; 1720 } 1721 1722 if (sc->flags & USING_MSIX) 1723 cxgb_teardown_msix(sc); 1724 1725 callout_stop(&sc->cxgb_tick_ch); 1726 callout_stop(&sc->sge_timer_ch); 1727 callout_drain(&sc->cxgb_tick_ch); 1728 callout_drain(&sc->sge_timer_ch); 1729 1730 if (sc->tq != NULL) { 1731 printf("draining slow intr\n"); 1732 1733 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1734 printf("draining ext intr\n"); 1735 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1736 printf("draining tick task\n"); 1737 taskqueue_drain(sc->tq, &sc->tick_task); 1738 } 1739 ADAPTER_UNLOCK(sc); 1740} 1741 1742static int 1743offload_open(struct port_info *pi) 1744{ 1745 struct adapter *adapter = pi->adapter; 1746 struct t3cdev *tdev = &adapter->tdev; 1747#ifdef notyet 1748 T3CDEV(pi->ifp); 1749#endif 1750 int adap_up = adapter->open_device_map & PORT_MASK; 1751 int err = 0; 1752 1753 CTR1(KTR_CXGB, "device_map=0x%x", adapter->open_device_map); 1754 if (atomic_cmpset_int(&adapter->open_device_map, 1755 (adapter->open_device_map & ~(1<<OFFLOAD_DEVMAP_BIT)), 1756 (adapter->open_device_map | (1<<OFFLOAD_DEVMAP_BIT))) == 0) 1757 return (0); 1758 1759 1760 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1761 printf("offload_open: DEVMAP_BIT did not get set 0x%x\n", adapter->open_device_map); 1762 ADAPTER_LOCK(pi->adapter); 1763 if (!adap_up) 1764 err = cxgb_up(adapter); 1765 ADAPTER_UNLOCK(pi->adapter); 1766 if (err) 1767 return (err); 1768 1769 t3_tp_set_offload_mode(adapter, 1); 1770 tdev->lldev = pi->ifp; 1771 1772 init_port_mtus(adapter); 1773 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd, 1774 adapter->params.b_wnd, 1775 adapter->params.rev == 0 ? 1776 adapter->port[0].ifp->if_mtu : 0xffff); 1777 init_smt(adapter); 1778 1779 /* Call back all registered clients */ 1780 cxgb_add_clients(tdev); 1781 1782 1783 /* restore them in case the offload module has changed them */ 1784 if (err) { 1785 t3_tp_set_offload_mode(adapter, 0); 1786 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1787 cxgb_set_dummy_ops(tdev); 1788 } 1789 return (err); 1790} 1791 1792static int 1793offload_close(struct t3cdev *tdev) 1794{ 1795 struct adapter *adapter = tdev2adap(tdev); 1796 1797 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1798 return (0); 1799 1800 /* Call back all registered clients */ 1801 cxgb_remove_clients(tdev); 1802 1803 tdev->lldev = NULL; 1804 cxgb_set_dummy_ops(tdev); 1805 t3_tp_set_offload_mode(adapter, 0); 1806 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1807 1808 ADAPTER_LOCK(adapter); 1809 if (!adapter->open_device_map) 1810 cxgb_down_locked(adapter); 1811 else 1812 ADAPTER_UNLOCK(adapter); 1813 return (0); 1814} 1815 1816 1817static void 1818cxgb_init(void *arg) 1819{ 1820 struct port_info *p = arg; 1821 1822 PORT_LOCK(p); 1823 cxgb_init_locked(p); 1824 PORT_UNLOCK(p); 1825} 1826 1827static void 1828cxgb_init_locked(struct port_info *p) 1829{ 1830 struct ifnet *ifp; 1831 adapter_t *sc = p->adapter; 1832 int err; 1833 1834 PORT_LOCK_ASSERT_OWNED(p); 1835 ifp = p->ifp; 1836 1837 ADAPTER_LOCK(p->adapter); 1838 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1839 ADAPTER_UNLOCK(p->adapter); 1840 cxgb_stop_locked(p); 1841 return; 1842 } 1843 if (p->adapter->open_device_map == 0) { 1844 t3_intr_clear(sc); 1845 } 1846 setbit(&p->adapter->open_device_map, p->port_id); 1847 ADAPTER_UNLOCK(p->adapter); 1848 1849 if (is_offload(sc) && !ofld_disable) { 1850 err = offload_open(p); 1851 if (err) 1852 log(LOG_WARNING, 1853 "Could not initialize offload capabilities\n"); 1854 } 1855#if !defined(LINK_ATTACH) 1856 cxgb_link_start(p); 1857 t3_link_changed(sc, p->port_id); 1858#endif 1859 ifp->if_baudrate = p->link_config.speed * 1000000; 1860 1861 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id); 1862 t3_port_intr_enable(sc, p->port_id); 1863 1864 t3_sge_reset_adapter(sc); 1865 1866 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1867 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1868} 1869 1870static void 1871cxgb_set_rxmode(struct port_info *p) 1872{ 1873 struct t3_rx_mode rm; 1874 struct cmac *mac = &p->mac; 1875 1876 t3_init_rx_mode(&rm, p); 1877 mtx_lock(&p->adapter->mdio_lock); 1878 t3_mac_set_rx_mode(mac, &rm); 1879 mtx_unlock(&p->adapter->mdio_lock); 1880} 1881 1882static void 1883cxgb_stop_locked(struct port_info *pi) 1884{ 1885 struct ifnet *ifp; 1886 1887 PORT_LOCK_ASSERT_OWNED(pi); 1888 ADAPTER_LOCK_ASSERT_NOTOWNED(pi->adapter); 1889 1890 ifp = pi->ifp; 1891 t3_port_intr_disable(pi->adapter, pi->port_id); 1892 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1893 1894 /* disable pause frames */ 1895 t3_set_reg_field(pi->adapter, A_XGM_TX_CFG + pi->mac.offset, 1896 F_TXPAUSEEN, 0); 1897 1898 /* Reset RX FIFO HWM */ 1899 t3_set_reg_field(pi->adapter, A_XGM_RXFIFO_CFG + pi->mac.offset, 1900 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); 1901 1902 1903 ADAPTER_LOCK(pi->adapter); 1904 clrbit(&pi->adapter->open_device_map, pi->port_id); 1905 1906 if (pi->adapter->open_device_map == 0) { 1907 cxgb_down_locked(pi->adapter); 1908 } else 1909 ADAPTER_UNLOCK(pi->adapter); 1910 1911#if !defined(LINK_ATTACH) 1912 DELAY(100); 1913 1914 /* Wait for TXFIFO empty */ 1915 t3_wait_op_done(pi->adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 1916 F_TXFIFO_EMPTY, 1, 20, 5); 1917 1918 DELAY(100); 1919 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1920 1921 pi->phy.ops->power_down(&pi->phy, 1); 1922#endif 1923 1924} 1925 1926static int 1927cxgb_set_mtu(struct port_info *p, int mtu) 1928{ 1929 struct ifnet *ifp = p->ifp; 1930 int error = 0; 1931 1932 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) 1933 error = EINVAL; 1934 else if (ifp->if_mtu != mtu) { 1935 PORT_LOCK(p); 1936 ifp->if_mtu = mtu; 1937 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1938 cxgb_stop_locked(p); 1939 cxgb_init_locked(p); 1940 } 1941 PORT_UNLOCK(p); 1942 } 1943 return (error); 1944} 1945 1946/* 1947 * Mark lro enabled or disabled in all qsets for this port 1948 */ 1949static int 1950cxgb_set_lro(struct port_info *p, int enabled) 1951{ 1952 int i; 1953 struct adapter *adp = p->adapter; 1954 struct sge_qset *q; 1955 1956 PORT_LOCK_ASSERT_OWNED(p); 1957 for (i = 0; i < p->nqsets; i++) { 1958 q = &adp->sge.qs[p->first_qset + i]; 1959 q->lro.enabled = (enabled != 0); 1960 } 1961 return (0); 1962} 1963 1964static int 1965cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 1966{ 1967 struct port_info *p = ifp->if_softc; 1968 struct ifaddr *ifa = (struct ifaddr *)data; 1969 struct ifreq *ifr = (struct ifreq *)data; 1970 int flags, error = 0, reinit = 0; 1971 uint32_t mask; 1972 1973 /* 1974 * XXX need to check that we aren't in the middle of an unload 1975 */ 1976 switch (command) { 1977 case SIOCSIFMTU: 1978 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1979 break; 1980 case SIOCSIFADDR: 1981 if (ifa->ifa_addr->sa_family == AF_INET) { 1982 ifp->if_flags |= IFF_UP; 1983 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1984 PORT_LOCK(p); 1985 cxgb_init_locked(p); 1986 PORT_UNLOCK(p); 1987 } 1988 arp_ifinit(ifp, ifa); 1989 } else 1990 error = ether_ioctl(ifp, command, data); 1991 break; 1992 case SIOCSIFFLAGS: 1993 PORT_LOCK(p); 1994 if (ifp->if_flags & IFF_UP) { 1995 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1996 flags = p->if_flags; 1997 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1998 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1999 cxgb_set_rxmode(p); 2000 } else 2001 cxgb_init_locked(p); 2002 p->if_flags = ifp->if_flags; 2003 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2004 cxgb_stop_locked(p); 2005 2006 PORT_UNLOCK(p); 2007 break; 2008 case SIOCADDMULTI: 2009 case SIOCDELMULTI: 2010 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2011 cxgb_set_rxmode(p); 2012 } 2013 break; 2014 case SIOCSIFMEDIA: 2015 case SIOCGIFMEDIA: 2016 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 2017 break; 2018 case SIOCSIFCAP: 2019 PORT_LOCK(p); 2020 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2021 if (mask & IFCAP_TXCSUM) { 2022 if (IFCAP_TXCSUM & ifp->if_capenable) { 2023 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); 2024 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP 2025 | CSUM_IP | CSUM_TSO); 2026 } else { 2027 ifp->if_capenable |= IFCAP_TXCSUM; 2028 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP 2029 | CSUM_IP); 2030 } 2031 } 2032 if (mask & IFCAP_RXCSUM) { 2033 ifp->if_capenable ^= IFCAP_RXCSUM; 2034 } 2035 if (mask & IFCAP_TSO4) { 2036 if (IFCAP_TSO4 & ifp->if_capenable) { 2037 ifp->if_capenable &= ~IFCAP_TSO4; 2038 ifp->if_hwassist &= ~CSUM_TSO; 2039 } else if (IFCAP_TXCSUM & ifp->if_capenable) { 2040 ifp->if_capenable |= IFCAP_TSO4; 2041 ifp->if_hwassist |= CSUM_TSO; 2042 } else { 2043 if (cxgb_debug) 2044 printf("cxgb requires tx checksum offload" 2045 " be enabled to use TSO\n"); 2046 error = EINVAL; 2047 } 2048 } 2049 if (mask & IFCAP_LRO) { 2050 ifp->if_capenable ^= IFCAP_LRO; 2051 2052 /* Safe to do this even if cxgb_up not called yet */ 2053 cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO); 2054 } 2055 if (mask & IFCAP_VLAN_HWTAGGING) { 2056 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2057 reinit = ifp->if_drv_flags & IFF_DRV_RUNNING; 2058 } 2059 if (mask & IFCAP_VLAN_MTU) { 2060 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2061 reinit = ifp->if_drv_flags & IFF_DRV_RUNNING; 2062 } 2063 if (mask & IFCAP_VLAN_HWCSUM) { 2064 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2065 } 2066 if (reinit) { 2067 cxgb_stop_locked(p); 2068 cxgb_init_locked(p); 2069 } 2070 PORT_UNLOCK(p); 2071 2072#ifdef VLAN_CAPABILITIES 2073 VLAN_CAPABILITIES(ifp); 2074#endif 2075 break; 2076 default: 2077 error = ether_ioctl(ifp, command, data); 2078 break; 2079 } 2080 return (error); 2081} 2082 2083static int 2084cxgb_media_change(struct ifnet *ifp) 2085{ 2086 if_printf(ifp, "media change not supported\n"); 2087 return (ENXIO); 2088} 2089 2090static void 2091cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2092{ 2093 struct port_info *p = ifp->if_softc; 2094 2095 ifmr->ifm_status = IFM_AVALID; 2096 ifmr->ifm_active = IFM_ETHER; 2097 2098 if (!p->link_config.link_ok) 2099 return; 2100 2101 ifmr->ifm_status |= IFM_ACTIVE; 2102 2103 switch (p->link_config.speed) { 2104 case 10: 2105 ifmr->ifm_active |= IFM_10_T; 2106 break; 2107 case 100: 2108 ifmr->ifm_active |= IFM_100_TX; 2109 break; 2110 case 1000: 2111 ifmr->ifm_active |= IFM_1000_T; 2112 break; 2113 } 2114 2115 if (p->link_config.duplex) 2116 ifmr->ifm_active |= IFM_FDX; 2117 else 2118 ifmr->ifm_active |= IFM_HDX; 2119} 2120 2121static void 2122cxgb_async_intr(void *data) 2123{ 2124 adapter_t *sc = data; 2125 2126 if (cxgb_debug) 2127 device_printf(sc->dev, "cxgb_async_intr\n"); 2128 /* 2129 * May need to sleep - defer to taskqueue 2130 */ 2131 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2132} 2133 2134static void 2135cxgb_ext_intr_handler(void *arg, int count) 2136{ 2137 adapter_t *sc = (adapter_t *)arg; 2138 2139 if (cxgb_debug) 2140 printf("cxgb_ext_intr_handler\n"); 2141 2142 t3_phy_intr_handler(sc); 2143 2144 /* Now reenable external interrupts */ 2145 ADAPTER_LOCK(sc); 2146 if (sc->slow_intr_mask) { 2147 sc->slow_intr_mask |= F_T3DBG; 2148 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2149 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2150 } 2151 ADAPTER_UNLOCK(sc); 2152} 2153 2154static void 2155check_link_status(adapter_t *sc) 2156{ 2157 int i; 2158 2159 for (i = 0; i < (sc)->params.nports; ++i) { 2160 struct port_info *p = &sc->port[i]; 2161 2162 if (!(p->phy.caps & SUPPORTED_IRQ)) 2163 t3_link_changed(sc, i); 2164 p->ifp->if_baudrate = p->link_config.speed * 1000000; 2165 } 2166} 2167 2168static void 2169check_t3b2_mac(struct adapter *adapter) 2170{ 2171 int i; 2172 2173 if(adapter->flags & CXGB_SHUTDOWN) 2174 return; 2175 2176 for_each_port(adapter, i) { 2177 struct port_info *p = &adapter->port[i]; 2178 struct ifnet *ifp = p->ifp; 2179 int status; 2180 2181 if(adapter->flags & CXGB_SHUTDOWN) 2182 return; 2183 2184 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2185 continue; 2186 2187 status = 0; 2188 PORT_LOCK(p); 2189 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 2190 status = t3b2_mac_watchdog_task(&p->mac); 2191 if (status == 1) 2192 p->mac.stats.num_toggled++; 2193 else if (status == 2) { 2194 struct cmac *mac = &p->mac; 2195 int mtu = ifp->if_mtu; 2196 2197 if (ifp->if_capenable & IFCAP_VLAN_MTU) 2198 mtu += ETHER_VLAN_ENCAP_LEN; 2199 t3_mac_set_mtu(mac, mtu); 2200 t3_mac_set_address(mac, 0, p->hw_addr); 2201 cxgb_set_rxmode(p); 2202 t3_link_start(&p->phy, mac, &p->link_config); 2203 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2204 t3_port_intr_enable(adapter, p->port_id); 2205 p->mac.stats.num_resets++; 2206 } 2207 PORT_UNLOCK(p); 2208 } 2209} 2210 2211static void 2212cxgb_tick(void *arg) 2213{ 2214 adapter_t *sc = (adapter_t *)arg; 2215 2216 if(sc->flags & CXGB_SHUTDOWN) 2217 return; 2218 2219 taskqueue_enqueue(sc->tq, &sc->tick_task); 2220 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 2221} 2222 2223static void 2224cxgb_tick_handler(void *arg, int count) 2225{ 2226 adapter_t *sc = (adapter_t *)arg; 2227 const struct adapter_params *p = &sc->params; 2228 int i; 2229 2230 if(sc->flags & CXGB_SHUTDOWN) 2231 return; 2232 2233 ADAPTER_LOCK(sc); 2234 if (p->linkpoll_period) 2235 check_link_status(sc); 2236 2237 sc->check_task_cnt++; 2238 2239 /* 2240 * adapter lock can currently only be acquired after the 2241 * port lock 2242 */ 2243 ADAPTER_UNLOCK(sc); 2244 2245 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2246 check_t3b2_mac(sc); 2247 2248 /* Update MAC stats if it's time to do so */ 2249 if (!p->linkpoll_period || 2250 (sc->check_task_cnt * p->linkpoll_period) / 10 >= 2251 p->stats_update_period) { 2252 for_each_port(sc, i) { 2253 struct port_info *port = &sc->port[i]; 2254 PORT_LOCK(port); 2255 t3_mac_update_stats(&port->mac); 2256 PORT_UNLOCK(port); 2257 } 2258 sc->check_task_cnt = 0; 2259 } 2260} 2261 2262static void 2263touch_bars(device_t dev) 2264{ 2265 /* 2266 * Don't enable yet 2267 */ 2268#if !defined(__LP64__) && 0 2269 u32 v; 2270 2271 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2272 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2273 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2274 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2275 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2276 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2277#endif 2278} 2279 2280static int 2281set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2282{ 2283 uint8_t *buf; 2284 int err = 0; 2285 u32 aligned_offset, aligned_len, *p; 2286 struct adapter *adapter = pi->adapter; 2287 2288 2289 aligned_offset = offset & ~3; 2290 aligned_len = (len + (offset & 3) + 3) & ~3; 2291 2292 if (aligned_offset != offset || aligned_len != len) { 2293 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2294 if (!buf) 2295 return (ENOMEM); 2296 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2297 if (!err && aligned_len > 4) 2298 err = t3_seeprom_read(adapter, 2299 aligned_offset + aligned_len - 4, 2300 (u32 *)&buf[aligned_len - 4]); 2301 if (err) 2302 goto out; 2303 memcpy(buf + (offset & 3), data, len); 2304 } else 2305 buf = (uint8_t *)(uintptr_t)data; 2306 2307 err = t3_seeprom_wp(adapter, 0); 2308 if (err) 2309 goto out; 2310 2311 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2312 err = t3_seeprom_write(adapter, aligned_offset, *p); 2313 aligned_offset += 4; 2314 } 2315 2316 if (!err) 2317 err = t3_seeprom_wp(adapter, 1); 2318out: 2319 if (buf != data) 2320 free(buf, M_DEVBUF); 2321 return err; 2322} 2323 2324 2325static int 2326in_range(int val, int lo, int hi) 2327{ 2328 return val < 0 || (val <= hi && val >= lo); 2329} 2330 2331static int 2332cxgb_extension_open(struct cdev *dev, int flags, int fmp, d_thread_t *td) 2333{ 2334 return (0); 2335} 2336 2337static int 2338cxgb_extension_close(struct cdev *dev, int flags, int fmt, d_thread_t *td) 2339{ 2340 return (0); 2341} 2342 2343static int 2344cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2345 int fflag, struct thread *td) 2346{ 2347 int mmd, error = 0; 2348 struct port_info *pi = dev->si_drv1; 2349 adapter_t *sc = pi->adapter; 2350 2351#ifdef PRIV_SUPPORTED 2352 if (priv_check(td, PRIV_DRIVER)) { 2353 if (cxgb_debug) 2354 printf("user does not have access to privileged ioctls\n"); 2355 return (EPERM); 2356 } 2357#else 2358 if (suser(td)) { 2359 if (cxgb_debug) 2360 printf("user does not have access to privileged ioctls\n"); 2361 return (EPERM); 2362 } 2363#endif 2364 2365 switch (cmd) { 2366 case CHELSIO_GET_MIIREG: { 2367 uint32_t val; 2368 struct cphy *phy = &pi->phy; 2369 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2370 2371 if (!phy->mdio_read) 2372 return (EOPNOTSUPP); 2373 if (is_10G(sc)) { 2374 mmd = mid->phy_id >> 8; 2375 if (!mmd) 2376 mmd = MDIO_DEV_PCS; 2377 else if (mmd > MDIO_DEV_XGXS) 2378 return (EINVAL); 2379 2380 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2381 mid->reg_num, &val); 2382 } else 2383 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2384 mid->reg_num & 0x1f, &val); 2385 if (error == 0) 2386 mid->val_out = val; 2387 break; 2388 } 2389 case CHELSIO_SET_MIIREG: { 2390 struct cphy *phy = &pi->phy; 2391 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2392 2393 if (!phy->mdio_write) 2394 return (EOPNOTSUPP); 2395 if (is_10G(sc)) { 2396 mmd = mid->phy_id >> 8; 2397 if (!mmd) 2398 mmd = MDIO_DEV_PCS; 2399 else if (mmd > MDIO_DEV_XGXS) 2400 return (EINVAL); 2401 2402 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2403 mmd, mid->reg_num, mid->val_in); 2404 } else 2405 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2406 mid->reg_num & 0x1f, 2407 mid->val_in); 2408 break; 2409 } 2410 case CHELSIO_SETREG: { 2411 struct ch_reg *edata = (struct ch_reg *)data; 2412 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2413 return (EFAULT); 2414 t3_write_reg(sc, edata->addr, edata->val); 2415 break; 2416 } 2417 case CHELSIO_GETREG: { 2418 struct ch_reg *edata = (struct ch_reg *)data; 2419 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2420 return (EFAULT); 2421 edata->val = t3_read_reg(sc, edata->addr); 2422 break; 2423 } 2424 case CHELSIO_GET_SGE_CONTEXT: { 2425 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2426 mtx_lock_spin(&sc->sge.reg_lock); 2427 switch (ecntxt->cntxt_type) { 2428 case CNTXT_TYPE_EGRESS: 2429 error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2430 ecntxt->data); 2431 break; 2432 case CNTXT_TYPE_FL: 2433 error = -t3_sge_read_fl(sc, ecntxt->cntxt_id, 2434 ecntxt->data); 2435 break; 2436 case CNTXT_TYPE_RSP: 2437 error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2438 ecntxt->data); 2439 break; 2440 case CNTXT_TYPE_CQ: 2441 error = -t3_sge_read_cq(sc, ecntxt->cntxt_id, 2442 ecntxt->data); 2443 break; 2444 default: 2445 error = EINVAL; 2446 break; 2447 } 2448 mtx_unlock_spin(&sc->sge.reg_lock); 2449 break; 2450 } 2451 case CHELSIO_GET_SGE_DESC: { 2452 struct ch_desc *edesc = (struct ch_desc *)data; 2453 int ret; 2454 if (edesc->queue_num >= SGE_QSETS * 6) 2455 return (EINVAL); 2456 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2457 edesc->queue_num % 6, edesc->idx, edesc->data); 2458 if (ret < 0) 2459 return (EINVAL); 2460 edesc->size = ret; 2461 break; 2462 } 2463 case CHELSIO_GET_QSET_PARAMS: { 2464 struct qset_params *q; 2465 struct ch_qset_params *t = (struct ch_qset_params *)data; 2466 int q1 = pi->first_qset; 2467 int nqsets = pi->nqsets; 2468 int i; 2469 2470 if (t->qset_idx >= nqsets) 2471 return EINVAL; 2472 2473 i = q1 + t->qset_idx; 2474 q = &sc->params.sge.qset[i]; 2475 t->rspq_size = q->rspq_size; 2476 t->txq_size[0] = q->txq_size[0]; 2477 t->txq_size[1] = q->txq_size[1]; 2478 t->txq_size[2] = q->txq_size[2]; 2479 t->fl_size[0] = q->fl_size; 2480 t->fl_size[1] = q->jumbo_size; 2481 t->polling = q->polling; 2482 t->lro = q->lro; 2483 t->intr_lat = q->coalesce_usecs; 2484 t->cong_thres = q->cong_thres; 2485 t->qnum = i; 2486 2487 if (sc->flags & USING_MSIX) 2488 t->vector = rman_get_start(sc->msix_irq_res[i]); 2489 else 2490 t->vector = rman_get_start(sc->irq_res); 2491 2492 break; 2493 } 2494 case CHELSIO_GET_QSET_NUM: { 2495 struct ch_reg *edata = (struct ch_reg *)data; 2496 edata->val = pi->nqsets; 2497 break; 2498 } 2499 case CHELSIO_LOAD_FW: { 2500 uint8_t *fw_data; 2501 uint32_t vers; 2502 struct ch_mem_range *t = (struct ch_mem_range *)data; 2503 2504 /* 2505 * You're allowed to load a firmware only before FULL_INIT_DONE 2506 * 2507 * FW_UPTODATE is also set so the rest of the initialization 2508 * will not overwrite what was loaded here. This gives you the 2509 * flexibility to load any firmware (and maybe shoot yourself in 2510 * the foot). 2511 */ 2512 2513 ADAPTER_LOCK(sc); 2514 if (sc->open_device_map || sc->flags & FULL_INIT_DONE) { 2515 ADAPTER_UNLOCK(sc); 2516 return (EBUSY); 2517 } 2518 2519 fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2520 if (!fw_data) 2521 error = ENOMEM; 2522 else 2523 error = copyin(t->buf, fw_data, t->len); 2524 2525 if (!error) 2526 error = -t3_load_fw(sc, fw_data, t->len); 2527 2528 if (t3_get_fw_version(sc, &vers) == 0) { 2529 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), 2530 "%d.%d.%d", G_FW_VERSION_MAJOR(vers), 2531 G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); 2532 } 2533 2534 if (!error) 2535 sc->flags |= FW_UPTODATE; 2536 2537 free(fw_data, M_DEVBUF); 2538 ADAPTER_UNLOCK(sc); 2539 break; 2540 } 2541 case CHELSIO_LOAD_BOOT: { 2542 uint8_t *boot_data; 2543 struct ch_mem_range *t = (struct ch_mem_range *)data; 2544 2545 boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2546 if (!boot_data) 2547 return ENOMEM; 2548 2549 error = copyin(t->buf, boot_data, t->len); 2550 if (!error) 2551 error = -t3_load_boot(sc, boot_data, t->len); 2552 2553 free(boot_data, M_DEVBUF); 2554 break; 2555 } 2556 case CHELSIO_GET_PM: { 2557 struct ch_pm *m = (struct ch_pm *)data; 2558 struct tp_params *p = &sc->params.tp; 2559 2560 if (!is_offload(sc)) 2561 return (EOPNOTSUPP); 2562 2563 m->tx_pg_sz = p->tx_pg_size; 2564 m->tx_num_pg = p->tx_num_pgs; 2565 m->rx_pg_sz = p->rx_pg_size; 2566 m->rx_num_pg = p->rx_num_pgs; 2567 m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; 2568 2569 break; 2570 } 2571 case CHELSIO_SET_PM: { 2572 struct ch_pm *m = (struct ch_pm *)data; 2573 struct tp_params *p = &sc->params.tp; 2574 2575 if (!is_offload(sc)) 2576 return (EOPNOTSUPP); 2577 if (sc->flags & FULL_INIT_DONE) 2578 return (EBUSY); 2579 2580 if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) || 2581 !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1))) 2582 return (EINVAL); /* not power of 2 */ 2583 if (!(m->rx_pg_sz & 0x14000)) 2584 return (EINVAL); /* not 16KB or 64KB */ 2585 if (!(m->tx_pg_sz & 0x1554000)) 2586 return (EINVAL); 2587 if (m->tx_num_pg == -1) 2588 m->tx_num_pg = p->tx_num_pgs; 2589 if (m->rx_num_pg == -1) 2590 m->rx_num_pg = p->rx_num_pgs; 2591 if (m->tx_num_pg % 24 || m->rx_num_pg % 24) 2592 return (EINVAL); 2593 if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size || 2594 m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size) 2595 return (EINVAL); 2596 2597 p->rx_pg_size = m->rx_pg_sz; 2598 p->tx_pg_size = m->tx_pg_sz; 2599 p->rx_num_pgs = m->rx_num_pg; 2600 p->tx_num_pgs = m->tx_num_pg; 2601 break; 2602 } 2603 case CHELSIO_SETMTUTAB: { 2604 struct ch_mtus *m = (struct ch_mtus *)data; 2605 int i; 2606 2607 if (!is_offload(sc)) 2608 return (EOPNOTSUPP); 2609 if (offload_running(sc)) 2610 return (EBUSY); 2611 if (m->nmtus != NMTUS) 2612 return (EINVAL); 2613 if (m->mtus[0] < 81) /* accommodate SACK */ 2614 return (EINVAL); 2615 2616 /* 2617 * MTUs must be in ascending order 2618 */ 2619 for (i = 1; i < NMTUS; ++i) 2620 if (m->mtus[i] < m->mtus[i - 1]) 2621 return (EINVAL); 2622 2623 memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus)); 2624 break; 2625 } 2626 case CHELSIO_GETMTUTAB: { 2627 struct ch_mtus *m = (struct ch_mtus *)data; 2628 2629 if (!is_offload(sc)) 2630 return (EOPNOTSUPP); 2631 2632 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2633 m->nmtus = NMTUS; 2634 break; 2635 } 2636 case CHELSIO_GET_MEM: { 2637 struct ch_mem_range *t = (struct ch_mem_range *)data; 2638 struct mc7 *mem; 2639 uint8_t *useraddr; 2640 u64 buf[32]; 2641 2642 /* 2643 * Use these to avoid modifying len/addr in the the return 2644 * struct 2645 */ 2646 uint32_t len = t->len, addr = t->addr; 2647 2648 if (!is_offload(sc)) 2649 return (EOPNOTSUPP); 2650 if (!(sc->flags & FULL_INIT_DONE)) 2651 return (EIO); /* need the memory controllers */ 2652 if ((addr & 0x7) || (len & 0x7)) 2653 return (EINVAL); 2654 if (t->mem_id == MEM_CM) 2655 mem = &sc->cm; 2656 else if (t->mem_id == MEM_PMRX) 2657 mem = &sc->pmrx; 2658 else if (t->mem_id == MEM_PMTX) 2659 mem = &sc->pmtx; 2660 else 2661 return (EINVAL); 2662 2663 /* 2664 * Version scheme: 2665 * bits 0..9: chip version 2666 * bits 10..15: chip revision 2667 */ 2668 t->version = 3 | (sc->params.rev << 10); 2669 2670 /* 2671 * Read 256 bytes at a time as len can be large and we don't 2672 * want to use huge intermediate buffers. 2673 */ 2674 useraddr = (uint8_t *)t->buf; 2675 while (len) { 2676 unsigned int chunk = min(len, sizeof(buf)); 2677 2678 error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf); 2679 if (error) 2680 return (-error); 2681 if (copyout(buf, useraddr, chunk)) 2682 return (EFAULT); 2683 useraddr += chunk; 2684 addr += chunk; 2685 len -= chunk; 2686 } 2687 break; 2688 } 2689 case CHELSIO_READ_TCAM_WORD: { 2690 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2691 2692 if (!is_offload(sc)) 2693 return (EOPNOTSUPP); 2694 if (!(sc->flags & FULL_INIT_DONE)) 2695 return (EIO); /* need MC5 */ 2696 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2697 break; 2698 } 2699 case CHELSIO_SET_TRACE_FILTER: { 2700 struct ch_trace *t = (struct ch_trace *)data; 2701 const struct trace_params *tp; 2702 2703 tp = (const struct trace_params *)&t->sip; 2704 if (t->config_tx) 2705 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2706 t->trace_tx); 2707 if (t->config_rx) 2708 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2709 t->trace_rx); 2710 break; 2711 } 2712 case CHELSIO_SET_PKTSCHED: { 2713 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2714 if (sc->open_device_map == 0) 2715 return (EAGAIN); 2716 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2717 p->binding); 2718 break; 2719 } 2720 case CHELSIO_IFCONF_GETREGS: { 2721 struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data; 2722 int reglen = cxgb_get_regs_len(); 2723 uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT); 2724 if (buf == NULL) { 2725 return (ENOMEM); 2726 } 2727 if (regs->len > reglen) 2728 regs->len = reglen; 2729 else if (regs->len < reglen) 2730 error = E2BIG; 2731 2732 if (!error) { 2733 cxgb_get_regs(sc, regs, buf); 2734 error = copyout(buf, regs->data, reglen); 2735 } 2736 free(buf, M_DEVBUF); 2737 2738 break; 2739 } 2740 case CHELSIO_SET_HW_SCHED: { 2741 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2742 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2743 2744 if ((sc->flags & FULL_INIT_DONE) == 0) 2745 return (EAGAIN); /* need TP to be initialized */ 2746 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2747 !in_range(t->channel, 0, 1) || 2748 !in_range(t->kbps, 0, 10000000) || 2749 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 2750 !in_range(t->flow_ipg, 0, 2751 dack_ticks_to_usec(sc, 0x7ff))) 2752 return (EINVAL); 2753 2754 if (t->kbps >= 0) { 2755 error = t3_config_sched(sc, t->kbps, t->sched); 2756 if (error < 0) 2757 return (-error); 2758 } 2759 if (t->class_ipg >= 0) 2760 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 2761 if (t->flow_ipg >= 0) { 2762 t->flow_ipg *= 1000; /* us -> ns */ 2763 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 2764 } 2765 if (t->mode >= 0) { 2766 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 2767 2768 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2769 bit, t->mode ? bit : 0); 2770 } 2771 if (t->channel >= 0) 2772 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 2773 1 << t->sched, t->channel << t->sched); 2774 break; 2775 } 2776 case CHELSIO_GET_EEPROM: { 2777 int i; 2778 struct ch_eeprom *e = (struct ch_eeprom *)data; 2779 uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT); 2780 2781 if (buf == NULL) { 2782 return (ENOMEM); 2783 } 2784 e->magic = EEPROM_MAGIC; 2785 for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4) 2786 error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]); 2787 2788 if (!error) 2789 error = copyout(buf + e->offset, e->data, e->len); 2790 2791 free(buf, M_DEVBUF); 2792 break; 2793 } 2794 case CHELSIO_CLEAR_STATS: { 2795 if (!(sc->flags & FULL_INIT_DONE)) 2796 return EAGAIN; 2797 2798 PORT_LOCK(pi); 2799 t3_mac_update_stats(&pi->mac); 2800 memset(&pi->mac.stats, 0, sizeof(pi->mac.stats)); 2801 PORT_UNLOCK(pi); 2802 break; 2803 } 2804 default: 2805 return (EOPNOTSUPP); 2806 break; 2807 } 2808 2809 return (error); 2810} 2811 2812static __inline void 2813reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 2814 unsigned int end) 2815{ 2816 uint32_t *p = (uint32_t *)(buf + start); 2817 2818 for ( ; start <= end; start += sizeof(uint32_t)) 2819 *p++ = t3_read_reg(ap, start); 2820} 2821 2822#define T3_REGMAP_SIZE (3 * 1024) 2823static int 2824cxgb_get_regs_len(void) 2825{ 2826 return T3_REGMAP_SIZE; 2827} 2828 2829static void 2830cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf) 2831{ 2832 2833 /* 2834 * Version scheme: 2835 * bits 0..9: chip version 2836 * bits 10..15: chip revision 2837 * bit 31: set for PCIe cards 2838 */ 2839 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 2840 2841 /* 2842 * We skip the MAC statistics registers because they are clear-on-read. 2843 * Also reading multi-register stats would need to synchronize with the 2844 * periodic mac stats accumulation. Hard to justify the complexity. 2845 */ 2846 memset(buf, 0, cxgb_get_regs_len()); 2847 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 2848 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 2849 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 2850 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 2851 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 2852 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 2853 XGM_REG(A_XGM_SERDES_STAT3, 1)); 2854 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 2855 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 2856} 2857 2858 2859MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 2860