cxgb_main.c revision 205946
1239278Sgonzo/************************************************************************** 2239278Sgonzo 3239278SgonzoCopyright (c) 2007-2009, Chelsio Inc. 4239278SgonzoAll rights reserved. 5239278Sgonzo 6239278SgonzoRedistribution and use in source and binary forms, with or without 7239278Sgonzomodification, are permitted provided that the following conditions are met: 8239278Sgonzo 9239278Sgonzo 1. Redistributions of source code must retain the above copyright notice, 10239278Sgonzo this list of conditions and the following disclaimer. 11239278Sgonzo 12239278Sgonzo 2. Neither the name of the Chelsio Corporation nor the names of its 13239278Sgonzo contributors may be used to endorse or promote products derived from 14239278Sgonzo this software without specific prior written permission. 15239278Sgonzo 16239278SgonzoTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17239278SgonzoAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18239278SgonzoIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19239278SgonzoARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20239278SgonzoLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21239278SgonzoCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22239278SgonzoSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23239278SgonzoINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24239278SgonzoCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25239278SgonzoARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26239278SgonzoPOSSIBILITY OF SUCH DAMAGE. 27239278Sgonzo 28239278Sgonzo***************************************************************************/ 29239278Sgonzo 30239278Sgonzo#include <sys/cdefs.h> 31239278Sgonzo__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_main.c 205946 2010-03-31 00:22:58Z np $"); 32239278Sgonzo 33239278Sgonzo#include <sys/param.h> 34239278Sgonzo#include <sys/systm.h> 35239278Sgonzo#include <sys/kernel.h> 36239278Sgonzo#include <sys/bus.h> 37239278Sgonzo#include <sys/module.h> 38239278Sgonzo#include <sys/pciio.h> 39239278Sgonzo#include <sys/conf.h> 40239278Sgonzo#include <machine/bus.h> 41239278Sgonzo#include <machine/resource.h> 42239278Sgonzo#include <sys/bus_dma.h> 43239278Sgonzo#include <sys/ktr.h> 44239278Sgonzo#include <sys/rman.h> 45239278Sgonzo#include <sys/ioccom.h> 46239278Sgonzo#include <sys/mbuf.h> 47239278Sgonzo#include <sys/linker.h> 48239278Sgonzo#include <sys/firmware.h> 49239278Sgonzo#include <sys/socket.h> 50239278Sgonzo#include <sys/sockio.h> 51239278Sgonzo#include <sys/smp.h> 52259342Sian#include <sys/sysctl.h> 53239278Sgonzo#include <sys/syslog.h> 54239278Sgonzo#include <sys/queue.h> 55239278Sgonzo#include <sys/taskqueue.h> 56239278Sgonzo#include <sys/proc.h> 57239278Sgonzo 58239278Sgonzo#include <net/bpf.h> 59239278Sgonzo#include <net/ethernet.h> 60239278Sgonzo#include <net/if.h> 61239278Sgonzo#include <net/if_arp.h> 62239278Sgonzo#include <net/if_dl.h> 63239278Sgonzo#include <net/if_media.h> 64239278Sgonzo#include <net/if_types.h> 65239278Sgonzo#include <net/if_vlan_var.h> 66239278Sgonzo 67239278Sgonzo#include <netinet/in_systm.h> 68239278Sgonzo#include <netinet/in.h> 69239278Sgonzo#include <netinet/if_ether.h> 70239278Sgonzo#include <netinet/ip.h> 71239278Sgonzo#include <netinet/ip.h> 72239278Sgonzo#include <netinet/tcp.h> 73239278Sgonzo#include <netinet/udp.h> 74239278Sgonzo 75239278Sgonzo#include <dev/pci/pcireg.h> 76239278Sgonzo#include <dev/pci/pcivar.h> 77239278Sgonzo#include <dev/pci/pci_private.h> 78239278Sgonzo 79239278Sgonzo#include <cxgb_include.h> 80239278Sgonzo 81239278Sgonzo#ifdef PRIV_SUPPORTED 82239278Sgonzo#include <sys/priv.h> 83239278Sgonzo#endif 84239278Sgonzo 85239278Sgonzostatic int cxgb_setup_interrupts(adapter_t *); 86239278Sgonzostatic void cxgb_teardown_interrupts(adapter_t *); 87239278Sgonzostatic void cxgb_init(void *); 88239278Sgonzostatic int cxgb_init_locked(struct port_info *); 89239278Sgonzostatic int cxgb_uninit_locked(struct port_info *); 90239278Sgonzostatic int cxgb_uninit_synchronized(struct port_info *); 91239278Sgonzostatic int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); 92239278Sgonzostatic int cxgb_media_change(struct ifnet *); 93239278Sgonzostatic int cxgb_ifm_type(int); 94239278Sgonzostatic void cxgb_build_medialist(struct port_info *); 95239278Sgonzostatic void cxgb_media_status(struct ifnet *, struct ifmediareq *); 96239278Sgonzostatic int setup_sge_qsets(adapter_t *); 97239278Sgonzostatic void cxgb_async_intr(void *); 98239278Sgonzostatic void cxgb_ext_intr_handler(void *, int); 99239278Sgonzostatic void cxgb_tick_handler(void *, int); 100239278Sgonzostatic void cxgb_tick(void *); 101239278Sgonzostatic void setup_rss(adapter_t *sc); 102239278Sgonzo 103239278Sgonzo/* Attachment glue for the PCI controller end of the device. Each port of 104239278Sgonzo * the device is attached separately, as defined later. 105239278Sgonzo */ 106239278Sgonzostatic int cxgb_controller_probe(device_t); 107239278Sgonzostatic int cxgb_controller_attach(device_t); 108239278Sgonzostatic int cxgb_controller_detach(device_t); 109239278Sgonzostatic void cxgb_free(struct adapter *); 110239278Sgonzostatic __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 111239278Sgonzo unsigned int end); 112239278Sgonzostatic void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf); 113239278Sgonzostatic int cxgb_get_regs_len(void); 114239278Sgonzostatic int offload_open(struct port_info *pi); 115239278Sgonzostatic void touch_bars(device_t dev); 116239278Sgonzostatic int offload_close(struct t3cdev *tdev); 117239278Sgonzostatic void cxgb_update_mac_settings(struct port_info *p); 118239278Sgonzo 119239278Sgonzostatic device_method_t cxgb_controller_methods[] = { 120239278Sgonzo DEVMETHOD(device_probe, cxgb_controller_probe), 121239278Sgonzo DEVMETHOD(device_attach, cxgb_controller_attach), 122239278Sgonzo DEVMETHOD(device_detach, cxgb_controller_detach), 123239278Sgonzo 124239278Sgonzo /* bus interface */ 125239278Sgonzo DEVMETHOD(bus_print_child, bus_generic_print_child), 126239278Sgonzo DEVMETHOD(bus_driver_added, bus_generic_driver_added), 127239278Sgonzo 128239278Sgonzo { 0, 0 } 129239278Sgonzo}; 130239278Sgonzo 131239278Sgonzostatic driver_t cxgb_controller_driver = { 132239278Sgonzo "cxgbc", 133239278Sgonzo cxgb_controller_methods, 134239278Sgonzo sizeof(struct adapter) 135239278Sgonzo}; 136239278Sgonzo 137239278Sgonzostatic devclass_t cxgb_controller_devclass; 138239278SgonzoDRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); 139239278Sgonzo 140239278Sgonzo/* 141239278Sgonzo * Attachment glue for the ports. Attachment is done directly to the 142239278Sgonzo * controller device. 143239278Sgonzo */ 144239278Sgonzostatic int cxgb_port_probe(device_t); 145239278Sgonzostatic int cxgb_port_attach(device_t); 146239278Sgonzostatic int cxgb_port_detach(device_t); 147239278Sgonzo 148239278Sgonzostatic device_method_t cxgb_port_methods[] = { 149239278Sgonzo DEVMETHOD(device_probe, cxgb_port_probe), 150239278Sgonzo DEVMETHOD(device_attach, cxgb_port_attach), 151239278Sgonzo DEVMETHOD(device_detach, cxgb_port_detach), 152239278Sgonzo { 0, 0 } 153239278Sgonzo}; 154239278Sgonzo 155239278Sgonzostatic driver_t cxgb_port_driver = { 156239278Sgonzo "cxgb", 157239278Sgonzo cxgb_port_methods, 158239278Sgonzo 0 159239278Sgonzo}; 160239278Sgonzo 161239278Sgonzostatic d_ioctl_t cxgb_extension_ioctl; 162239278Sgonzostatic d_open_t cxgb_extension_open; 163239278Sgonzostatic d_close_t cxgb_extension_close; 164239278Sgonzo 165239278Sgonzostatic struct cdevsw cxgb_cdevsw = { 166239278Sgonzo .d_version = D_VERSION, 167239278Sgonzo .d_flags = 0, 168239278Sgonzo .d_open = cxgb_extension_open, 169239278Sgonzo .d_close = cxgb_extension_close, 170239278Sgonzo .d_ioctl = cxgb_extension_ioctl, 171239278Sgonzo .d_name = "cxgb", 172239278Sgonzo}; 173239278Sgonzo 174239278Sgonzostatic devclass_t cxgb_port_devclass; 175239278SgonzoDRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); 176239278Sgonzo 177239278Sgonzo/* 178239278Sgonzo * The driver uses the best interrupt scheme available on a platform in the 179239278Sgonzo * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 180239278Sgonzo * of these schemes the driver may consider as follows: 181239278Sgonzo * 182239278Sgonzo * msi = 2: choose from among all three options 183239278Sgonzo * msi = 1 : only consider MSI and pin interrupts 184239278Sgonzo * msi = 0: force pin interrupts 185239278Sgonzo */ 186239278Sgonzostatic int msi_allowed = 2; 187239278Sgonzo 188239278SgonzoTUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); 189239278SgonzoSYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); 190239278SgonzoSYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, 191239278Sgonzo "MSI-X, MSI, INTx selector"); 192239278Sgonzo 193266152Sian/* 194266152Sian * The driver enables offload as a default. 195266152Sian * To disable it, use ofld_disable = 1. 196239278Sgonzo */ 197239278Sgonzostatic int ofld_disable = 0; 198239278SgonzoTUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); 199239278SgonzoSYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, 200239278Sgonzo "disable ULP offload"); 201239278Sgonzo 202239278Sgonzo/* 203239278Sgonzo * The driver uses an auto-queue algorithm by default. 204239278Sgonzo * To disable it and force a single queue-set per port, use multiq = 0 205239278Sgonzo */ 206239278Sgonzostatic int multiq = 1; 207239278SgonzoTUNABLE_INT("hw.cxgb.multiq", &multiq); 208239278SgonzoSYSCTL_UINT(_hw_cxgb, OID_AUTO, multiq, CTLFLAG_RDTUN, &multiq, 0, 209239278Sgonzo "use min(ncpus/ports, 8) queue-sets per port"); 210239278Sgonzo 211239278Sgonzo/* 212239278Sgonzo * By default the driver will not update the firmware unless 213239278Sgonzo * it was compiled against a newer version 214239278Sgonzo * 215239278Sgonzo */ 216239278Sgonzostatic int force_fw_update = 0; 217239278SgonzoTUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); 218239278SgonzoSYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, 219239278Sgonzo "update firmware even if up to date"); 220239278Sgonzo 221239278Sgonzoint cxgb_use_16k_clusters = 1; 222239278SgonzoTUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); 223239278SgonzoSYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, 224239278Sgonzo &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); 225239278Sgonzo 226239278Sgonzo/* 227239278Sgonzo * Tune the size of the output queue. 228239278Sgonzo */ 229239278Sgonzoint cxgb_snd_queue_len = IFQ_MAXLEN; 230239278SgonzoTUNABLE_INT("hw.cxgb.snd_queue_len", &cxgb_snd_queue_len); 231239278SgonzoSYSCTL_UINT(_hw_cxgb, OID_AUTO, snd_queue_len, CTLFLAG_RDTUN, 232239278Sgonzo &cxgb_snd_queue_len, 0, "send queue size "); 233239278Sgonzo 234239278Sgonzo 235239278Sgonzoenum { 236239278Sgonzo MAX_TXQ_ENTRIES = 16384, 237239278Sgonzo MAX_CTRL_TXQ_ENTRIES = 1024, 238239278Sgonzo MAX_RSPQ_ENTRIES = 16384, 239239278Sgonzo MAX_RX_BUFFERS = 16384, 240239278Sgonzo MAX_RX_JUMBO_BUFFERS = 16384, 241239278Sgonzo MIN_TXQ_ENTRIES = 4, 242239278Sgonzo MIN_CTRL_TXQ_ENTRIES = 4, 243239278Sgonzo MIN_RSPQ_ENTRIES = 32, 244239278Sgonzo MIN_FL_ENTRIES = 32, 245239278Sgonzo MIN_FL_JUMBO_ENTRIES = 32 246239278Sgonzo}; 247239278Sgonzo 248239278Sgonzostruct filter_info { 249239278Sgonzo u32 sip; 250239278Sgonzo u32 sip_mask; 251239278Sgonzo u32 dip; 252239278Sgonzo u16 sport; 253239278Sgonzo u16 dport; 254239278Sgonzo u32 vlan:12; 255239278Sgonzo u32 vlan_prio:3; 256239278Sgonzo u32 mac_hit:1; 257239278Sgonzo u32 mac_idx:4; 258239278Sgonzo u32 mac_vld:1; 259239278Sgonzo u32 pkt_type:2; 260239278Sgonzo u32 report_filter_id:1; 261239278Sgonzo u32 pass:1; 262239278Sgonzo u32 rss:1; 263239278Sgonzo u32 qset:3; 264239278Sgonzo u32 locked:1; 265239278Sgonzo u32 valid:1; 266239278Sgonzo}; 267239278Sgonzo 268239278Sgonzoenum { FILTER_NO_VLAN_PRI = 7 }; 269239278Sgonzo 270239278Sgonzo#define EEPROM_MAGIC 0x38E2F10C 271239278Sgonzo 272239278Sgonzo#define PORT_MASK ((1 << MAX_NPORTS) - 1) 273239278Sgonzo 274239278Sgonzo/* Table for probing the cards. The desc field isn't actually used */ 275239278Sgonzostruct cxgb_ident { 276239278Sgonzo uint16_t vendor; 277239278Sgonzo uint16_t device; 278239278Sgonzo int index; 279239278Sgonzo char *desc; 280239278Sgonzo} cxgb_identifiers[] = { 281239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 282239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 283239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 284239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 285239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 286239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 287239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 288239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 289239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 290239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 291239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 292239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0035, 6, "T3C10"}, 293239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0036, 3, "S320E-CR"}, 294239278Sgonzo {PCI_VENDOR_ID_CHELSIO, 0x0037, 7, "N320E-G2"}, 295239278Sgonzo {0, 0, 0, NULL} 296239278Sgonzo}; 297239278Sgonzo 298239278Sgonzostatic int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); 299239278Sgonzo 300239278Sgonzo 301239278Sgonzostatic __inline char 302239278Sgonzot3rev2char(struct adapter *adapter) 303239278Sgonzo{ 304239278Sgonzo char rev = 'z'; 305239278Sgonzo 306239278Sgonzo switch(adapter->params.rev) { 307239278Sgonzo case T3_REV_A: 308239278Sgonzo rev = 'a'; 309239278Sgonzo break; 310239278Sgonzo case T3_REV_B: 311239278Sgonzo case T3_REV_B2: 312239278Sgonzo rev = 'b'; 313239278Sgonzo break; 314239278Sgonzo case T3_REV_C: 315239278Sgonzo rev = 'c'; 316239278Sgonzo break; 317239278Sgonzo } 318239278Sgonzo return rev; 319239278Sgonzo} 320239278Sgonzo 321239278Sgonzostatic struct cxgb_ident * 322239278Sgonzocxgb_get_ident(device_t dev) 323239278Sgonzo{ 324239278Sgonzo struct cxgb_ident *id; 325239278Sgonzo 326239278Sgonzo for (id = cxgb_identifiers; id->desc != NULL; id++) { 327239278Sgonzo if ((id->vendor == pci_get_vendor(dev)) && 328239278Sgonzo (id->device == pci_get_device(dev))) { 329239278Sgonzo return (id); 330239278Sgonzo } 331239278Sgonzo } 332239278Sgonzo return (NULL); 333239278Sgonzo} 334239278Sgonzo 335239278Sgonzostatic const struct adapter_info * 336239278Sgonzocxgb_get_adapter_info(device_t dev) 337239278Sgonzo{ 338239278Sgonzo struct cxgb_ident *id; 339239278Sgonzo const struct adapter_info *ai; 340239278Sgonzo 341239278Sgonzo id = cxgb_get_ident(dev); 342239278Sgonzo if (id == NULL) 343239278Sgonzo return (NULL); 344239278Sgonzo 345239278Sgonzo ai = t3_get_adapter_info(id->index); 346239278Sgonzo 347239278Sgonzo return (ai); 348239278Sgonzo} 349239278Sgonzo 350239278Sgonzostatic int 351239278Sgonzocxgb_controller_probe(device_t dev) 352239278Sgonzo{ 353239278Sgonzo const struct adapter_info *ai; 354239278Sgonzo char *ports, buf[80]; 355239278Sgonzo int nports; 356239278Sgonzo 357239278Sgonzo ai = cxgb_get_adapter_info(dev); 358239278Sgonzo if (ai == NULL) 359239278Sgonzo return (ENXIO); 360239278Sgonzo 361239278Sgonzo nports = ai->nports0 + ai->nports1; 362239278Sgonzo if (nports == 1) 363239278Sgonzo ports = "port"; 364239278Sgonzo else 365239278Sgonzo ports = "ports"; 366239278Sgonzo 367239278Sgonzo snprintf(buf, sizeof(buf), "%s, %d %s", ai->desc, nports, ports); 368239278Sgonzo device_set_desc_copy(dev, buf); 369239278Sgonzo return (BUS_PROBE_DEFAULT); 370239278Sgonzo} 371239278Sgonzo 372239278Sgonzo#define FW_FNAME "cxgb_t3fw" 373239278Sgonzo#define TPEEPROM_NAME "cxgb_t3%c_tp_eeprom" 374239278Sgonzo#define TPSRAM_NAME "cxgb_t3%c_protocol_sram" 375239278Sgonzo 376239278Sgonzostatic int 377239278Sgonzoupgrade_fw(adapter_t *sc) 378239278Sgonzo{ 379239278Sgonzo const struct firmware *fw; 380239278Sgonzo int status; 381239278Sgonzo u32 vers; 382239278Sgonzo 383239278Sgonzo if ((fw = firmware_get(FW_FNAME)) == NULL) { 384239278Sgonzo device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); 385239278Sgonzo return (ENOENT); 386239278Sgonzo } else 387239278Sgonzo device_printf(sc->dev, "installing firmware on card\n"); 388239278Sgonzo status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); 389239278Sgonzo 390239278Sgonzo if (status != 0) { 391239278Sgonzo device_printf(sc->dev, "failed to install firmware: %d\n", 392239278Sgonzo status); 393239278Sgonzo } else { 394239278Sgonzo t3_get_fw_version(sc, &vers); 395239278Sgonzo snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 396239278Sgonzo G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 397239278Sgonzo G_FW_VERSION_MICRO(vers)); 398239278Sgonzo } 399239278Sgonzo 400239278Sgonzo firmware_put(fw, FIRMWARE_UNLOAD); 401239278Sgonzo 402239278Sgonzo return (status); 403239278Sgonzo} 404239278Sgonzo 405239278Sgonzo/* 406239278Sgonzo * The cxgb_controller_attach function is responsible for the initial 407239278Sgonzo * bringup of the device. Its responsibilities include: 408239278Sgonzo * 409239278Sgonzo * 1. Determine if the device supports MSI or MSI-X. 410239278Sgonzo * 2. Allocate bus resources so that we can access the Base Address Register 411239278Sgonzo * 3. Create and initialize mutexes for the controller and its control 412239278Sgonzo * logic such as SGE and MDIO. 413239278Sgonzo * 4. Call hardware specific setup routine for the adapter as a whole. 414239278Sgonzo * 5. Allocate the BAR for doing MSI-X. 415239278Sgonzo * 6. Setup the line interrupt iff MSI-X is not supported. 416239278Sgonzo * 7. Create the driver's taskq. 417239278Sgonzo * 8. Start one task queue service thread. 418239278Sgonzo * 9. Check if the firmware and SRAM are up-to-date. They will be 419239278Sgonzo * auto-updated later (before FULL_INIT_DONE), if required. 420239278Sgonzo * 10. Create a child device for each MAC (port) 421239278Sgonzo * 11. Initialize T3 private state. 422239278Sgonzo * 12. Trigger the LED 423239278Sgonzo * 13. Setup offload iff supported. 424239278Sgonzo * 14. Reset/restart the tick callout. 425239278Sgonzo * 15. Attach sysctls 426239278Sgonzo * 427239278Sgonzo * NOTE: Any modification or deviation from this list MUST be reflected in 428239278Sgonzo * the above comment. Failure to do so will result in problems on various 429239278Sgonzo * error conditions including link flapping. 430239278Sgonzo */ 431239278Sgonzostatic int 432239278Sgonzocxgb_controller_attach(device_t dev) 433239278Sgonzo{ 434239278Sgonzo device_t child; 435239278Sgonzo const struct adapter_info *ai; 436239278Sgonzo struct adapter *sc; 437239278Sgonzo int i, error = 0; 438239278Sgonzo uint32_t vers; 439239278Sgonzo int port_qsets = 1; 440239278Sgonzo int msi_needed, reg; 441239278Sgonzo char buf[80]; 442239278Sgonzo 443239278Sgonzo sc = device_get_softc(dev); 444239278Sgonzo sc->dev = dev; 445239278Sgonzo sc->msi_count = 0; 446239278Sgonzo ai = cxgb_get_adapter_info(dev); 447239278Sgonzo 448239278Sgonzo /* find the PCIe link width and set max read request to 4KB*/ 449239278Sgonzo if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 450239278Sgonzo uint16_t lnk, pectl; 451239278Sgonzo lnk = pci_read_config(dev, reg + 0x12, 2); 452239278Sgonzo sc->link_width = (lnk >> 4) & 0x3f; 453239278Sgonzo 454239278Sgonzo pectl = pci_read_config(dev, reg + 0x8, 2); 455239278Sgonzo pectl = (pectl & ~0x7000) | (5 << 12); 456239278Sgonzo pci_write_config(dev, reg + 0x8, pectl, 2); 457239278Sgonzo } 458239278Sgonzo 459239278Sgonzo if (sc->link_width != 0 && sc->link_width <= 4 && 460239278Sgonzo (ai->nports0 + ai->nports1) <= 2) { 461239278Sgonzo device_printf(sc->dev, 462239278Sgonzo "PCIe x%d Link, expect reduced performance\n", 463239278Sgonzo sc->link_width); 464239278Sgonzo } 465239278Sgonzo 466239278Sgonzo touch_bars(dev); 467239278Sgonzo pci_enable_busmaster(dev); 468239278Sgonzo /* 469239278Sgonzo * Allocate the registers and make them available to the driver. 470239278Sgonzo * The registers that we care about for NIC mode are in BAR 0 471239278Sgonzo */ 472239278Sgonzo sc->regs_rid = PCIR_BAR(0); 473239278Sgonzo if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 474239278Sgonzo &sc->regs_rid, RF_ACTIVE)) == NULL) { 475239278Sgonzo device_printf(dev, "Cannot allocate BAR region 0\n"); 476239278Sgonzo return (ENXIO); 477239278Sgonzo } 478239278Sgonzo sc->udbs_rid = PCIR_BAR(2); 479239278Sgonzo sc->udbs_res = NULL; 480239278Sgonzo if (is_offload(sc) && 481239278Sgonzo ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 482239278Sgonzo &sc->udbs_rid, RF_ACTIVE)) == NULL)) { 483239278Sgonzo device_printf(dev, "Cannot allocate BAR region 1\n"); 484239278Sgonzo error = ENXIO; 485239278Sgonzo goto out; 486239278Sgonzo } 487239278Sgonzo 488239278Sgonzo snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", 489239278Sgonzo device_get_unit(dev)); 490239278Sgonzo ADAPTER_LOCK_INIT(sc, sc->lockbuf); 491239278Sgonzo 492239278Sgonzo snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", 493239278Sgonzo device_get_unit(dev)); 494239278Sgonzo snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", 495239278Sgonzo device_get_unit(dev)); 496239278Sgonzo snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", 497239278Sgonzo device_get_unit(dev)); 498239278Sgonzo 499239278Sgonzo MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); 500239278Sgonzo MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 501239278Sgonzo MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 502239278Sgonzo 503239278Sgonzo sc->bt = rman_get_bustag(sc->regs_res); 504239278Sgonzo sc->bh = rman_get_bushandle(sc->regs_res); 505239278Sgonzo sc->mmio_len = rman_get_size(sc->regs_res); 506239278Sgonzo 507239278Sgonzo for (i = 0; i < MAX_NPORTS; i++) 508239278Sgonzo sc->port[i].adapter = sc; 509239278Sgonzo 510239278Sgonzo if (t3_prep_adapter(sc, ai, 1) < 0) { 511239278Sgonzo printf("prep adapter failed\n"); 512239278Sgonzo error = ENODEV; 513239278Sgonzo goto out; 514239278Sgonzo } 515239278Sgonzo /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 516239278Sgonzo * enough messages for the queue sets. If that fails, try falling 517239278Sgonzo * back to MSI. If that fails, then try falling back to the legacy 518239278Sgonzo * interrupt pin model. 519239278Sgonzo */ 520239278Sgonzo sc->msix_regs_rid = 0x20; 521239278Sgonzo if ((msi_allowed >= 2) && 522239278Sgonzo (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 523239278Sgonzo &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 524239278Sgonzo 525239278Sgonzo if (multiq) 526239278Sgonzo port_qsets = min(SGE_QSETS/sc->params.nports, mp_ncpus); 527239278Sgonzo msi_needed = sc->msi_count = sc->params.nports * port_qsets + 1; 528239278Sgonzo 529239278Sgonzo if (pci_msix_count(dev) == 0 || 530239278Sgonzo (error = pci_alloc_msix(dev, &sc->msi_count)) != 0 || 531239278Sgonzo sc->msi_count != msi_needed) { 532239278Sgonzo device_printf(dev, "alloc msix failed - " 533239278Sgonzo "msi_count=%d, msi_needed=%d, err=%d; " 534239278Sgonzo "will try MSI\n", sc->msi_count, 535239278Sgonzo msi_needed, error); 536239278Sgonzo sc->msi_count = 0; 537239278Sgonzo port_qsets = 1; 538239278Sgonzo pci_release_msi(dev); 539239278Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, 540239278Sgonzo sc->msix_regs_rid, sc->msix_regs_res); 541239278Sgonzo sc->msix_regs_res = NULL; 542239278Sgonzo } else { 543239278Sgonzo sc->flags |= USING_MSIX; 544239278Sgonzo sc->cxgb_intr = cxgb_async_intr; 545239278Sgonzo device_printf(dev, 546239278Sgonzo "using MSI-X interrupts (%u vectors)\n", 547239278Sgonzo sc->msi_count); 548239278Sgonzo } 549239278Sgonzo } 550239278Sgonzo 551239278Sgonzo if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 552239278Sgonzo sc->msi_count = 1; 553239278Sgonzo if ((error = pci_alloc_msi(dev, &sc->msi_count)) != 0) { 554239278Sgonzo device_printf(dev, "alloc msi failed - " 555239278Sgonzo "err=%d; will try INTx\n", error); 556239278Sgonzo sc->msi_count = 0; 557239278Sgonzo port_qsets = 1; 558239278Sgonzo pci_release_msi(dev); 559239278Sgonzo } else { 560239278Sgonzo sc->flags |= USING_MSI; 561239278Sgonzo sc->cxgb_intr = t3_intr_msi; 562239278Sgonzo device_printf(dev, "using MSI interrupts\n"); 563239278Sgonzo } 564239278Sgonzo } 565239278Sgonzo if (sc->msi_count == 0) { 566239278Sgonzo device_printf(dev, "using line interrupts\n"); 567239278Sgonzo sc->cxgb_intr = t3b_intr; 568239278Sgonzo } 569239278Sgonzo 570239278Sgonzo /* Create a private taskqueue thread for handling driver events */ 571239278Sgonzo sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, 572239278Sgonzo taskqueue_thread_enqueue, &sc->tq); 573239278Sgonzo if (sc->tq == NULL) { 574239278Sgonzo device_printf(dev, "failed to allocate controller task queue\n"); 575239278Sgonzo goto out; 576239278Sgonzo } 577239278Sgonzo 578239278Sgonzo taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 579239278Sgonzo device_get_nameunit(dev)); 580239278Sgonzo TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc); 581239278Sgonzo TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); 582239278Sgonzo 583239278Sgonzo 584239278Sgonzo /* Create a periodic callout for checking adapter status */ 585239278Sgonzo callout_init(&sc->cxgb_tick_ch, TRUE); 586239278Sgonzo 587239278Sgonzo if (t3_check_fw_version(sc) < 0 || force_fw_update) { 588239278Sgonzo /* 589239278Sgonzo * Warn user that a firmware update will be attempted in init. 590239278Sgonzo */ 591239278Sgonzo device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 592239278Sgonzo FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 593239278Sgonzo sc->flags &= ~FW_UPTODATE; 594239278Sgonzo } else { 595239278Sgonzo sc->flags |= FW_UPTODATE; 596239278Sgonzo } 597239278Sgonzo 598239278Sgonzo if (t3_check_tpsram_version(sc) < 0) { 599239278Sgonzo /* 600239278Sgonzo * Warn user that a firmware update will be attempted in init. 601239278Sgonzo */ 602239278Sgonzo device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 603239278Sgonzo t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 604239278Sgonzo sc->flags &= ~TPS_UPTODATE; 605239278Sgonzo } else { 606239278Sgonzo sc->flags |= TPS_UPTODATE; 607239278Sgonzo } 608239278Sgonzo 609239278Sgonzo /* 610239278Sgonzo * Create a child device for each MAC. The ethernet attachment 611239278Sgonzo * will be done in these children. 612239278Sgonzo */ 613239278Sgonzo for (i = 0; i < (sc)->params.nports; i++) { 614239278Sgonzo struct port_info *pi; 615239278Sgonzo 616239278Sgonzo if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { 617239278Sgonzo device_printf(dev, "failed to add child port\n"); 618239278Sgonzo error = EINVAL; 619239278Sgonzo goto out; 620239278Sgonzo } 621239278Sgonzo pi = &sc->port[i]; 622239278Sgonzo pi->adapter = sc; 623239278Sgonzo pi->nqsets = port_qsets; 624239278Sgonzo pi->first_qset = i*port_qsets; 625239278Sgonzo pi->port_id = i; 626239278Sgonzo pi->tx_chan = i >= ai->nports0; 627239278Sgonzo pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 628239278Sgonzo sc->rxpkt_map[pi->txpkt_intf] = i; 629239278Sgonzo sc->port[i].tx_chan = i >= ai->nports0; 630239278Sgonzo sc->portdev[i] = child; 631239278Sgonzo device_set_softc(child, pi); 632239278Sgonzo } 633239278Sgonzo if ((error = bus_generic_attach(dev)) != 0) 634239278Sgonzo goto out; 635239278Sgonzo 636239278Sgonzo /* initialize sge private state */ 637239278Sgonzo t3_sge_init_adapter(sc); 638239278Sgonzo 639239278Sgonzo t3_led_ready(sc); 640239278Sgonzo 641239278Sgonzo cxgb_offload_init(); 642239278Sgonzo if (is_offload(sc)) { 643239278Sgonzo setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 644239278Sgonzo cxgb_adapter_ofld(sc); 645239278Sgonzo } 646239278Sgonzo error = t3_get_fw_version(sc, &vers); 647239278Sgonzo if (error) 648239278Sgonzo goto out; 649239278Sgonzo 650239278Sgonzo snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 651239278Sgonzo G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 652239278Sgonzo G_FW_VERSION_MICRO(vers)); 653239278Sgonzo 654239278Sgonzo snprintf(buf, sizeof(buf), "%s %sNIC\t E/C: %s S/N: %s", 655239278Sgonzo ai->desc, is_offload(sc) ? "R" : "", 656239278Sgonzo sc->params.vpd.ec, sc->params.vpd.sn); 657239278Sgonzo device_set_desc_copy(dev, buf); 658239278Sgonzo 659239278Sgonzo snprintf(&sc->port_types[0], sizeof(sc->port_types), "%x%x%x%x", 660239278Sgonzo sc->params.vpd.port_type[0], sc->params.vpd.port_type[1], 661239278Sgonzo sc->params.vpd.port_type[2], sc->params.vpd.port_type[3]); 662239278Sgonzo 663239278Sgonzo device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); 664239278Sgonzo callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 665239278Sgonzo t3_add_attach_sysctls(sc); 666239278Sgonzoout: 667239278Sgonzo if (error) 668239278Sgonzo cxgb_free(sc); 669239278Sgonzo 670239278Sgonzo return (error); 671239278Sgonzo} 672239278Sgonzo 673239278Sgonzo/* 674239278Sgonzo * The cxgb_controller_detach routine is called with the device is 675239278Sgonzo * unloaded from the system. 676239278Sgonzo */ 677239278Sgonzo 678239278Sgonzostatic int 679239278Sgonzocxgb_controller_detach(device_t dev) 680239278Sgonzo{ 681239278Sgonzo struct adapter *sc; 682239278Sgonzo 683239278Sgonzo sc = device_get_softc(dev); 684239278Sgonzo 685239278Sgonzo cxgb_free(sc); 686239278Sgonzo 687239278Sgonzo return (0); 688239278Sgonzo} 689239278Sgonzo 690239278Sgonzo/* 691239278Sgonzo * The cxgb_free() is called by the cxgb_controller_detach() routine 692239278Sgonzo * to tear down the structures that were built up in 693239278Sgonzo * cxgb_controller_attach(), and should be the final piece of work 694239278Sgonzo * done when fully unloading the driver. 695239278Sgonzo * 696239278Sgonzo * 697239278Sgonzo * 1. Shutting down the threads started by the cxgb_controller_attach() 698239278Sgonzo * routine. 699239278Sgonzo * 2. Stopping the lower level device and all callouts (cxgb_down_locked()). 700239278Sgonzo * 3. Detaching all of the port devices created during the 701239278Sgonzo * cxgb_controller_attach() routine. 702239278Sgonzo * 4. Removing the device children created via cxgb_controller_attach(). 703239278Sgonzo * 5. Releasing PCI resources associated with the device. 704239278Sgonzo * 6. Turning off the offload support, iff it was turned on. 705239278Sgonzo * 7. Destroying the mutexes created in cxgb_controller_attach(). 706239278Sgonzo * 707239278Sgonzo */ 708239278Sgonzostatic void 709239278Sgonzocxgb_free(struct adapter *sc) 710239278Sgonzo{ 711239278Sgonzo int i; 712239278Sgonzo 713239278Sgonzo ADAPTER_LOCK(sc); 714239278Sgonzo sc->flags |= CXGB_SHUTDOWN; 715239278Sgonzo ADAPTER_UNLOCK(sc); 716239278Sgonzo 717239278Sgonzo /* 718239278Sgonzo * Make sure all child devices are gone. 719239278Sgonzo */ 720239278Sgonzo bus_generic_detach(sc->dev); 721239278Sgonzo for (i = 0; i < (sc)->params.nports; i++) { 722239278Sgonzo if (sc->portdev[i] && 723239278Sgonzo device_delete_child(sc->dev, sc->portdev[i]) != 0) 724239278Sgonzo device_printf(sc->dev, "failed to delete child port\n"); 725239278Sgonzo } 726239278Sgonzo 727239278Sgonzo /* 728239278Sgonzo * At this point, it is as if cxgb_port_detach has run on all ports, and 729239278Sgonzo * cxgb_down has run on the adapter. All interrupts have been silenced, 730239278Sgonzo * all open devices have been closed. 731239278Sgonzo */ 732239278Sgonzo KASSERT(sc->open_device_map == 0, ("%s: device(s) still open (%x)", 733239278Sgonzo __func__, sc->open_device_map)); 734239278Sgonzo for (i = 0; i < sc->params.nports; i++) { 735239278Sgonzo KASSERT(sc->port[i].ifp == NULL, ("%s: port %i undead!", 736239278Sgonzo __func__, i)); 737239278Sgonzo } 738239278Sgonzo 739239278Sgonzo /* 740239278Sgonzo * Finish off the adapter's callouts. 741239278Sgonzo */ 742239278Sgonzo callout_drain(&sc->cxgb_tick_ch); 743239278Sgonzo callout_drain(&sc->sge_timer_ch); 744239278Sgonzo 745239278Sgonzo /* 746239278Sgonzo * Release resources grabbed under FULL_INIT_DONE by cxgb_up. The 747239278Sgonzo * sysctls are cleaned up by the kernel linker. 748239278Sgonzo */ 749239278Sgonzo if (sc->flags & FULL_INIT_DONE) { 750239278Sgonzo t3_free_sge_resources(sc); 751239278Sgonzo sc->flags &= ~FULL_INIT_DONE; 752239278Sgonzo } 753239278Sgonzo 754239278Sgonzo /* 755239278Sgonzo * Release all interrupt resources. 756239278Sgonzo */ 757239278Sgonzo cxgb_teardown_interrupts(sc); 758239278Sgonzo if (sc->flags & (USING_MSI | USING_MSIX)) { 759239278Sgonzo device_printf(sc->dev, "releasing msi message(s)\n"); 760239278Sgonzo pci_release_msi(sc->dev); 761239278Sgonzo } else { 762239278Sgonzo device_printf(sc->dev, "no msi message to release\n"); 763239278Sgonzo } 764239278Sgonzo 765239278Sgonzo if (sc->msix_regs_res != NULL) { 766239278Sgonzo bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 767239278Sgonzo sc->msix_regs_res); 768239278Sgonzo } 769239278Sgonzo 770239278Sgonzo /* 771239278Sgonzo * Free the adapter's taskqueue. 772239278Sgonzo */ 773239278Sgonzo if (sc->tq != NULL) { 774239278Sgonzo taskqueue_free(sc->tq); 775239278Sgonzo sc->tq = NULL; 776239278Sgonzo } 777239278Sgonzo 778239278Sgonzo if (is_offload(sc)) { 779239278Sgonzo clrbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); 780239278Sgonzo cxgb_adapter_unofld(sc); 781239278Sgonzo } 782239278Sgonzo 783239278Sgonzo#ifdef notyet 784239278Sgonzo if (sc->flags & CXGB_OFLD_INIT) 785239278Sgonzo cxgb_offload_deactivate(sc); 786239278Sgonzo#endif 787239278Sgonzo free(sc->filters, M_DEVBUF); 788239278Sgonzo t3_sge_free(sc); 789239278Sgonzo 790239278Sgonzo cxgb_offload_exit(); 791239278Sgonzo 792239278Sgonzo if (sc->udbs_res != NULL) 793239278Sgonzo bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, 794239278Sgonzo sc->udbs_res); 795239278Sgonzo 796239278Sgonzo if (sc->regs_res != NULL) 797239278Sgonzo bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, 798239278Sgonzo sc->regs_res); 799239278Sgonzo 800239278Sgonzo MTX_DESTROY(&sc->mdio_lock); 801239278Sgonzo MTX_DESTROY(&sc->sge.reg_lock); 802239278Sgonzo MTX_DESTROY(&sc->elmer_lock); 803239278Sgonzo ADAPTER_LOCK_DEINIT(sc); 804239278Sgonzo} 805239278Sgonzo 806239278Sgonzo/** 807239278Sgonzo * setup_sge_qsets - configure SGE Tx/Rx/response queues 808239278Sgonzo * @sc: the controller softc 809239278Sgonzo * 810239278Sgonzo * Determines how many sets of SGE queues to use and initializes them. 811239278Sgonzo * We support multiple queue sets per port if we have MSI-X, otherwise 812239278Sgonzo * just one queue set per port. 813239278Sgonzo */ 814239278Sgonzostatic int 815239278Sgonzosetup_sge_qsets(adapter_t *sc) 816239278Sgonzo{ 817239278Sgonzo int i, j, err, irq_idx = 0, qset_idx = 0; 818239278Sgonzo u_int ntxq = SGE_TXQ_PER_SET; 819239278Sgonzo 820239278Sgonzo if ((err = t3_sge_alloc(sc)) != 0) { 821239278Sgonzo device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 822239278Sgonzo return (err); 823239278Sgonzo } 824239278Sgonzo 825239278Sgonzo if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 826239278Sgonzo irq_idx = -1; 827239278Sgonzo 828239278Sgonzo for (i = 0; i < (sc)->params.nports; i++) { 829239278Sgonzo struct port_info *pi = &sc->port[i]; 830239278Sgonzo 831239278Sgonzo for (j = 0; j < pi->nqsets; j++, qset_idx++) { 832239278Sgonzo err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 833239278Sgonzo (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 834239278Sgonzo &sc->params.sge.qset[qset_idx], ntxq, pi); 835239278Sgonzo if (err) { 836239278Sgonzo t3_free_sge_resources(sc); 837239278Sgonzo device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 838239278Sgonzo err); 839239278Sgonzo return (err); 840239278Sgonzo } 841239278Sgonzo } 842239278Sgonzo } 843239278Sgonzo 844239278Sgonzo return (0); 845239278Sgonzo} 846239278Sgonzo 847239278Sgonzostatic void 848239278Sgonzocxgb_teardown_interrupts(adapter_t *sc) 849239278Sgonzo{ 850239278Sgonzo int i; 851239278Sgonzo 852239278Sgonzo for (i = 0; i < SGE_QSETS; i++) { 853239278Sgonzo if (sc->msix_intr_tag[i] == NULL) { 854239278Sgonzo 855239278Sgonzo /* Should have been setup fully or not at all */ 856239278Sgonzo KASSERT(sc->msix_irq_res[i] == NULL && 857239278Sgonzo sc->msix_irq_rid[i] == 0, 858239278Sgonzo ("%s: half-done interrupt (%d).", __func__, i)); 859239278Sgonzo 860239278Sgonzo continue; 861239278Sgonzo } 862239278Sgonzo 863239278Sgonzo bus_teardown_intr(sc->dev, sc->msix_irq_res[i], 864239278Sgonzo sc->msix_intr_tag[i]); 865239278Sgonzo bus_release_resource(sc->dev, SYS_RES_IRQ, sc->msix_irq_rid[i], 866239278Sgonzo sc->msix_irq_res[i]); 867239278Sgonzo 868239278Sgonzo sc->msix_irq_res[i] = sc->msix_intr_tag[i] = NULL; 869239278Sgonzo sc->msix_irq_rid[i] = 0; 870239278Sgonzo } 871239278Sgonzo 872239278Sgonzo if (sc->intr_tag) { 873239278Sgonzo KASSERT(sc->irq_res != NULL, 874239278Sgonzo ("%s: half-done interrupt.", __func__)); 875239278Sgonzo 876239278Sgonzo bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); 877239278Sgonzo bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 878239278Sgonzo sc->irq_res); 879239278Sgonzo 880239278Sgonzo sc->irq_res = sc->intr_tag = NULL; 881239278Sgonzo sc->irq_rid = 0; 882239278Sgonzo } 883239278Sgonzo} 884239278Sgonzo 885239278Sgonzostatic int 886239278Sgonzocxgb_setup_interrupts(adapter_t *sc) 887239278Sgonzo{ 888239278Sgonzo struct resource *res; 889239278Sgonzo void *tag; 890239278Sgonzo int i, rid, err, intr_flag = sc->flags & (USING_MSI | USING_MSIX); 891239278Sgonzo 892239278Sgonzo sc->irq_rid = intr_flag ? 1 : 0; 893239278Sgonzo sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irq_rid, 894239278Sgonzo RF_SHAREABLE | RF_ACTIVE); 895239278Sgonzo if (sc->irq_res == NULL) { 896239278Sgonzo device_printf(sc->dev, "Cannot allocate interrupt (%x, %u)\n", 897239278Sgonzo intr_flag, sc->irq_rid); 898239278Sgonzo err = EINVAL; 899239278Sgonzo sc->irq_rid = 0; 900239278Sgonzo } else { 901239278Sgonzo err = bus_setup_intr(sc->dev, sc->irq_res, 902239278Sgonzo INTR_MPSAFE | INTR_TYPE_NET, NULL, 903239278Sgonzo sc->cxgb_intr, sc, &sc->intr_tag); 904239278Sgonzo 905239278Sgonzo if (err) { 906239278Sgonzo device_printf(sc->dev, 907239278Sgonzo "Cannot set up interrupt (%x, %u, %d)\n", 908239278Sgonzo intr_flag, sc->irq_rid, err); 909239278Sgonzo bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, 910239278Sgonzo sc->irq_res); 911239278Sgonzo sc->irq_res = sc->intr_tag = NULL; 912239278Sgonzo sc->irq_rid = 0; 913239278Sgonzo } 914239278Sgonzo } 915239278Sgonzo 916239278Sgonzo /* That's all for INTx or MSI */ 917239278Sgonzo if (!(intr_flag & USING_MSIX) || err) 918239278Sgonzo return (err); 919239278Sgonzo 920239278Sgonzo for (i = 0; i < sc->msi_count - 1; i++) { 921239278Sgonzo rid = i + 2; 922239278Sgonzo res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, 923239278Sgonzo RF_SHAREABLE | RF_ACTIVE); 924239278Sgonzo if (res == NULL) { 925239278Sgonzo device_printf(sc->dev, "Cannot allocate interrupt " 926239278Sgonzo "for message %d\n", rid); 927239278Sgonzo err = EINVAL; 928239278Sgonzo break; 929239278Sgonzo } 930239278Sgonzo 931239278Sgonzo err = bus_setup_intr(sc->dev, res, INTR_MPSAFE | INTR_TYPE_NET, 932239278Sgonzo NULL, t3_intr_msix, &sc->sge.qs[i], &tag); 933239278Sgonzo if (err) { 934239278Sgonzo device_printf(sc->dev, "Cannot set up interrupt " 935239278Sgonzo "for message %d (%d)\n", rid, err); 936239278Sgonzo bus_release_resource(sc->dev, SYS_RES_IRQ, rid, res); 937239278Sgonzo break; 938239278Sgonzo } 939239278Sgonzo 940239278Sgonzo sc->msix_irq_rid[i] = rid; 941239278Sgonzo sc->msix_irq_res[i] = res; 942239278Sgonzo sc->msix_intr_tag[i] = tag; 943239278Sgonzo } 944239278Sgonzo 945239278Sgonzo if (err) 946239278Sgonzo cxgb_teardown_interrupts(sc); 947239278Sgonzo 948239278Sgonzo return (err); 949239278Sgonzo} 950239278Sgonzo 951239278Sgonzo 952239278Sgonzostatic int 953239278Sgonzocxgb_port_probe(device_t dev) 954239278Sgonzo{ 955239278Sgonzo struct port_info *p; 956239278Sgonzo char buf[80]; 957239278Sgonzo const char *desc; 958239278Sgonzo 959239278Sgonzo p = device_get_softc(dev); 960239278Sgonzo desc = p->phy.desc; 961239278Sgonzo snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); 962239278Sgonzo device_set_desc_copy(dev, buf); 963239278Sgonzo return (0); 964239278Sgonzo} 965239278Sgonzo 966239278Sgonzo 967239278Sgonzostatic int 968239278Sgonzocxgb_makedev(struct port_info *pi) 969239278Sgonzo{ 970239278Sgonzo 971239278Sgonzo pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, 972239278Sgonzo UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp)); 973239278Sgonzo 974239278Sgonzo if (pi->port_cdev == NULL) 975239278Sgonzo return (ENOMEM); 976239278Sgonzo 977239278Sgonzo pi->port_cdev->si_drv1 = (void *)pi; 978239278Sgonzo 979239278Sgonzo return (0); 980239278Sgonzo} 981239278Sgonzo 982239278Sgonzo#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 983239278Sgonzo IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 984239278Sgonzo IFCAP_VLAN_HWTSO) 985239278Sgonzo#define CXGB_CAP_ENABLE (CXGB_CAP & ~IFCAP_TSO6) 986239278Sgonzo 987239278Sgonzostatic int 988239278Sgonzocxgb_port_attach(device_t dev) 989239278Sgonzo{ 990239278Sgonzo struct port_info *p; 991239278Sgonzo struct ifnet *ifp; 992239278Sgonzo int err; 993239278Sgonzo struct adapter *sc; 994239278Sgonzo 995239278Sgonzo p = device_get_softc(dev); 996239278Sgonzo sc = p->adapter; 997239278Sgonzo snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", 998239278Sgonzo device_get_unit(device_get_parent(dev)), p->port_id); 999239278Sgonzo PORT_LOCK_INIT(p, p->lockbuf); 1000239278Sgonzo 1001239278Sgonzo /* Allocate an ifnet object and set it up */ 1002239278Sgonzo ifp = p->ifp = if_alloc(IFT_ETHER); 1003239278Sgonzo if (ifp == NULL) { 1004239278Sgonzo device_printf(dev, "Cannot allocate ifnet\n"); 1005239278Sgonzo return (ENOMEM); 1006239278Sgonzo } 1007239278Sgonzo 1008239278Sgonzo if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1009239278Sgonzo ifp->if_init = cxgb_init; 1010239278Sgonzo ifp->if_softc = p; 1011239278Sgonzo ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1012239278Sgonzo ifp->if_ioctl = cxgb_ioctl; 1013239278Sgonzo ifp->if_start = cxgb_start; 1014239278Sgonzo 1015239278Sgonzo ifp->if_snd.ifq_drv_maxlen = cxgb_snd_queue_len; 1016239278Sgonzo IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1017239278Sgonzo IFQ_SET_READY(&ifp->if_snd); 1018239278Sgonzo 1019239278Sgonzo ifp->if_capabilities = CXGB_CAP; 1020239278Sgonzo ifp->if_capenable = CXGB_CAP_ENABLE; 1021239278Sgonzo ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO; 1022239278Sgonzo 1023239278Sgonzo /* 1024239278Sgonzo * Disable TSO on 4-port - it isn't supported by the firmware. 1025239278Sgonzo */ 1026239278Sgonzo if (sc->params.nports > 2) { 1027239278Sgonzo ifp->if_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO); 1028239278Sgonzo ifp->if_capenable &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO); 1029239278Sgonzo ifp->if_hwassist &= ~CSUM_TSO; 1030239278Sgonzo } 1031239278Sgonzo 1032239278Sgonzo ether_ifattach(ifp, p->hw_addr); 1033239278Sgonzo ifp->if_transmit = cxgb_transmit; 1034239278Sgonzo ifp->if_qflush = cxgb_qflush; 1035239278Sgonzo 1036239278Sgonzo#ifdef DEFAULT_JUMBO 1037239278Sgonzo if (sc->params.nports <= 2) 1038239278Sgonzo ifp->if_mtu = ETHERMTU_JUMBO; 1039239278Sgonzo#endif 1040239278Sgonzo if ((err = cxgb_makedev(p)) != 0) { 1041239278Sgonzo printf("makedev failed %d\n", err); 1042239278Sgonzo return (err); 1043239278Sgonzo } 1044239278Sgonzo 1045239278Sgonzo /* Create a list of media supported by this port */ 1046239278Sgonzo ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 1047239278Sgonzo cxgb_media_status); 1048239278Sgonzo cxgb_build_medialist(p); 1049239278Sgonzo 1050239278Sgonzo t3_sge_init_port(p); 1051239278Sgonzo 1052239278Sgonzo return (err); 1053239278Sgonzo} 1054239278Sgonzo 1055239278Sgonzo/* 1056239278Sgonzo * cxgb_port_detach() is called via the device_detach methods when 1057239278Sgonzo * cxgb_free() calls the bus_generic_detach. It is responsible for 1058239278Sgonzo * removing the device from the view of the kernel, i.e. from all 1059239278Sgonzo * interfaces lists etc. This routine is only called when the driver is 1060239278Sgonzo * being unloaded, not when the link goes down. 1061239278Sgonzo */ 1062239278Sgonzostatic int 1063239278Sgonzocxgb_port_detach(device_t dev) 1064239278Sgonzo{ 1065239278Sgonzo struct port_info *p; 1066239278Sgonzo struct adapter *sc; 1067239278Sgonzo int i; 1068239278Sgonzo 1069239278Sgonzo p = device_get_softc(dev); 1070239278Sgonzo sc = p->adapter; 1071239278Sgonzo 1072239278Sgonzo /* Tell cxgb_ioctl and if_init that the port is going away */ 1073239278Sgonzo ADAPTER_LOCK(sc); 1074239278Sgonzo SET_DOOMED(p); 1075239278Sgonzo wakeup(&sc->flags); 1076239278Sgonzo while (IS_BUSY(sc)) 1077239278Sgonzo mtx_sleep(&sc->flags, &sc->lock, 0, "cxgbdtch", 0); 1078239278Sgonzo SET_BUSY(sc); 1079239278Sgonzo ADAPTER_UNLOCK(sc); 1080239278Sgonzo 1081239278Sgonzo if (p->port_cdev != NULL) 1082239278Sgonzo destroy_dev(p->port_cdev); 1083239278Sgonzo 1084239278Sgonzo cxgb_uninit_synchronized(p); 1085239278Sgonzo ether_ifdetach(p->ifp); 1086239278Sgonzo 1087239278Sgonzo for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { 1088239278Sgonzo struct sge_qset *qs = &sc->sge.qs[i]; 1089239278Sgonzo struct sge_txq *txq = &qs->txq[TXQ_ETH]; 1090239278Sgonzo 1091239278Sgonzo callout_drain(&txq->txq_watchdog); 1092239278Sgonzo callout_drain(&txq->txq_timer); 1093239278Sgonzo } 1094239278Sgonzo 1095239278Sgonzo PORT_LOCK_DEINIT(p); 1096239278Sgonzo if_free(p->ifp); 1097239278Sgonzo p->ifp = NULL; 1098239278Sgonzo 1099239278Sgonzo ADAPTER_LOCK(sc); 1100239278Sgonzo CLR_BUSY(sc); 1101239278Sgonzo wakeup_one(&sc->flags); 1102239278Sgonzo ADAPTER_UNLOCK(sc); 1103239278Sgonzo return (0); 1104239278Sgonzo} 1105239278Sgonzo 1106239278Sgonzovoid 1107239278Sgonzot3_fatal_err(struct adapter *sc) 1108239278Sgonzo{ 1109239278Sgonzo u_int fw_status[4]; 1110239278Sgonzo 1111239278Sgonzo if (sc->flags & FULL_INIT_DONE) { 1112239278Sgonzo t3_sge_stop(sc); 1113239278Sgonzo t3_write_reg(sc, A_XGM_TX_CTRL, 0); 1114239278Sgonzo t3_write_reg(sc, A_XGM_RX_CTRL, 0); 1115239278Sgonzo t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 1116239278Sgonzo t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 1117239278Sgonzo t3_intr_disable(sc); 1118239278Sgonzo } 1119239278Sgonzo device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 1120239278Sgonzo if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 1121239278Sgonzo device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 1122239278Sgonzo fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 1123239278Sgonzo} 1124239278Sgonzo 1125239278Sgonzoint 1126243882Sglebiust3_os_find_pci_capability(adapter_t *sc, int cap) 1127239278Sgonzo{ 1128239278Sgonzo device_t dev; 1129239278Sgonzo struct pci_devinfo *dinfo; 1130239278Sgonzo pcicfgregs *cfg; 1131239278Sgonzo uint32_t status; 1132239278Sgonzo uint8_t ptr; 1133239278Sgonzo 1134239278Sgonzo dev = sc->dev; 1135239278Sgonzo dinfo = device_get_ivars(dev); 1136239278Sgonzo cfg = &dinfo->cfg; 1137239278Sgonzo 1138239278Sgonzo status = pci_read_config(dev, PCIR_STATUS, 2); 1139239278Sgonzo if (!(status & PCIM_STATUS_CAPPRESENT)) 1140239278Sgonzo return (0); 1141239278Sgonzo 1142239278Sgonzo switch (cfg->hdrtype & PCIM_HDRTYPE) { 1143239278Sgonzo case 0: 1144239278Sgonzo case 1: 1145239278Sgonzo ptr = PCIR_CAP_PTR; 1146239278Sgonzo break; 1147239278Sgonzo case 2: 1148239278Sgonzo ptr = PCIR_CAP_PTR_2; 1149239278Sgonzo break; 1150239278Sgonzo default: 1151239278Sgonzo return (0); 1152239278Sgonzo break; 1153239278Sgonzo } 1154239278Sgonzo ptr = pci_read_config(dev, ptr, 1); 1155239278Sgonzo 1156239278Sgonzo while (ptr != 0) { 1157239278Sgonzo if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 1158239278Sgonzo return (ptr); 1159239278Sgonzo ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 1160239278Sgonzo } 1161239278Sgonzo 1162239278Sgonzo return (0); 1163239278Sgonzo} 1164239278Sgonzo 1165239278Sgonzoint 1166239278Sgonzot3_os_pci_save_state(struct adapter *sc) 1167239278Sgonzo{ 1168239278Sgonzo device_t dev; 1169239278Sgonzo struct pci_devinfo *dinfo; 1170239278Sgonzo 1171239278Sgonzo dev = sc->dev; 1172239278Sgonzo dinfo = device_get_ivars(dev); 1173239278Sgonzo 1174239278Sgonzo pci_cfg_save(dev, dinfo, 0); 1175239278Sgonzo return (0); 1176239278Sgonzo} 1177239278Sgonzo 1178239278Sgonzoint 1179239278Sgonzot3_os_pci_restore_state(struct adapter *sc) 1180239278Sgonzo{ 1181239278Sgonzo device_t dev; 1182239278Sgonzo struct pci_devinfo *dinfo; 1183239278Sgonzo 1184239278Sgonzo dev = sc->dev; 1185239278Sgonzo dinfo = device_get_ivars(dev); 1186239278Sgonzo 1187239278Sgonzo pci_cfg_restore(dev, dinfo); 1188239278Sgonzo return (0); 1189239278Sgonzo} 1190239278Sgonzo 1191239278Sgonzo/** 1192239278Sgonzo * t3_os_link_changed - handle link status changes 1193239278Sgonzo * @sc: the adapter associated with the link change 1194239278Sgonzo * @port_id: the port index whose link status has changed 1195239278Sgonzo * @link_status: the new status of the link 1196239278Sgonzo * @speed: the new speed setting 1197239278Sgonzo * @duplex: the new duplex setting 1198239278Sgonzo * @fc: the new flow-control setting 1199239278Sgonzo * 1200239278Sgonzo * This is the OS-dependent handler for link status changes. The OS 1201239278Sgonzo * neutral handler takes care of most of the processing for these events, 1202239278Sgonzo * then calls this handler for any OS-specific processing. 1203239278Sgonzo */ 1204239278Sgonzovoid 1205239278Sgonzot3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 1206239278Sgonzo int duplex, int fc, int mac_was_reset) 1207239278Sgonzo{ 1208239278Sgonzo struct port_info *pi = &adapter->port[port_id]; 1209239278Sgonzo struct ifnet *ifp = pi->ifp; 1210239278Sgonzo 1211239278Sgonzo /* no race with detach, so ifp should always be good */ 1212239278Sgonzo KASSERT(ifp, ("%s: if detached.", __func__)); 1213239278Sgonzo 1214239278Sgonzo /* Reapply mac settings if they were lost due to a reset */ 1215239278Sgonzo if (mac_was_reset) { 1216239278Sgonzo PORT_LOCK(pi); 1217239278Sgonzo cxgb_update_mac_settings(pi); 1218239278Sgonzo PORT_UNLOCK(pi); 1219239278Sgonzo } 1220239278Sgonzo 1221239278Sgonzo if (link_status) { 1222239278Sgonzo ifp->if_baudrate = IF_Mbps(speed); 1223239278Sgonzo if_link_state_change(ifp, LINK_STATE_UP); 1224239278Sgonzo } else 1225239278Sgonzo if_link_state_change(ifp, LINK_STATE_DOWN); 1226239278Sgonzo} 1227239278Sgonzo 1228239278Sgonzo/** 1229239278Sgonzo * t3_os_phymod_changed - handle PHY module changes 1230239278Sgonzo * @phy: the PHY reporting the module change 1231239278Sgonzo * @mod_type: new module type 1232239278Sgonzo * 1233 * This is the OS-dependent handler for PHY module changes. It is 1234 * invoked when a PHY module is removed or inserted for any OS-specific 1235 * processing. 1236 */ 1237void t3_os_phymod_changed(struct adapter *adap, int port_id) 1238{ 1239 static const char *mod_str[] = { 1240 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX-L", "unknown" 1241 }; 1242 struct port_info *pi = &adap->port[port_id]; 1243 int mod = pi->phy.modtype; 1244 1245 if (mod != pi->media.ifm_cur->ifm_data) 1246 cxgb_build_medialist(pi); 1247 1248 if (mod == phy_modtype_none) 1249 if_printf(pi->ifp, "PHY module unplugged\n"); 1250 else { 1251 KASSERT(mod < ARRAY_SIZE(mod_str), 1252 ("invalid PHY module type %d", mod)); 1253 if_printf(pi->ifp, "%s PHY module inserted\n", mod_str[mod]); 1254 } 1255} 1256 1257/* 1258 * Interrupt-context handler for external (PHY) interrupts. 1259 */ 1260void 1261t3_os_ext_intr_handler(adapter_t *sc) 1262{ 1263 if (cxgb_debug) 1264 printf("t3_os_ext_intr_handler\n"); 1265 /* 1266 * Schedule a task to handle external interrupts as they may be slow 1267 * and we use a mutex to protect MDIO registers. We disable PHY 1268 * interrupts in the meantime and let the task reenable them when 1269 * it's done. 1270 */ 1271 if (sc->slow_intr_mask) { 1272 ADAPTER_LOCK(sc); 1273 sc->slow_intr_mask &= ~F_T3DBG; 1274 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1275 taskqueue_enqueue(sc->tq, &sc->ext_intr_task); 1276 ADAPTER_UNLOCK(sc); 1277 } 1278} 1279 1280void 1281t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 1282{ 1283 1284 /* 1285 * The ifnet might not be allocated before this gets called, 1286 * as this is called early on in attach by t3_prep_adapter 1287 * save the address off in the port structure 1288 */ 1289 if (cxgb_debug) 1290 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); 1291 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); 1292} 1293 1294/* 1295 * Programs the XGMAC based on the settings in the ifnet. These settings 1296 * include MTU, MAC address, mcast addresses, etc. 1297 */ 1298static void 1299cxgb_update_mac_settings(struct port_info *p) 1300{ 1301 struct ifnet *ifp = p->ifp; 1302 struct t3_rx_mode rm; 1303 struct cmac *mac = &p->mac; 1304 int mtu, hwtagging; 1305 1306 PORT_LOCK_ASSERT_OWNED(p); 1307 1308 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN); 1309 1310 mtu = ifp->if_mtu; 1311 if (ifp->if_capenable & IFCAP_VLAN_MTU) 1312 mtu += ETHER_VLAN_ENCAP_LEN; 1313 1314 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0; 1315 1316 t3_mac_set_mtu(mac, mtu); 1317 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging); 1318 t3_mac_set_address(mac, 0, p->hw_addr); 1319 t3_init_rx_mode(&rm, p); 1320 t3_mac_set_rx_mode(mac, &rm); 1321} 1322 1323 1324static int 1325await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, 1326 unsigned long n) 1327{ 1328 int attempts = 5; 1329 1330 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { 1331 if (!--attempts) 1332 return (ETIMEDOUT); 1333 t3_os_sleep(10); 1334 } 1335 return 0; 1336} 1337 1338static int 1339init_tp_parity(struct adapter *adap) 1340{ 1341 int i; 1342 struct mbuf *m; 1343 struct cpl_set_tcb_field *greq; 1344 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; 1345 1346 t3_tp_set_offload_mode(adap, 1); 1347 1348 for (i = 0; i < 16; i++) { 1349 struct cpl_smt_write_req *req; 1350 1351 m = m_gethdr(M_WAITOK, MT_DATA); 1352 req = mtod(m, struct cpl_smt_write_req *); 1353 m->m_len = m->m_pkthdr.len = sizeof(*req); 1354 memset(req, 0, sizeof(*req)); 1355 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1356 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); 1357 req->iff = i; 1358 t3_mgmt_tx(adap, m); 1359 } 1360 1361 for (i = 0; i < 2048; i++) { 1362 struct cpl_l2t_write_req *req; 1363 1364 m = m_gethdr(M_WAITOK, MT_DATA); 1365 req = mtod(m, struct cpl_l2t_write_req *); 1366 m->m_len = m->m_pkthdr.len = sizeof(*req); 1367 memset(req, 0, sizeof(*req)); 1368 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1369 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); 1370 req->params = htonl(V_L2T_W_IDX(i)); 1371 t3_mgmt_tx(adap, m); 1372 } 1373 1374 for (i = 0; i < 2048; i++) { 1375 struct cpl_rte_write_req *req; 1376 1377 m = m_gethdr(M_WAITOK, MT_DATA); 1378 req = mtod(m, struct cpl_rte_write_req *); 1379 m->m_len = m->m_pkthdr.len = sizeof(*req); 1380 memset(req, 0, sizeof(*req)); 1381 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1382 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); 1383 req->l2t_idx = htonl(V_L2T_W_IDX(i)); 1384 t3_mgmt_tx(adap, m); 1385 } 1386 1387 m = m_gethdr(M_WAITOK, MT_DATA); 1388 greq = mtod(m, struct cpl_set_tcb_field *); 1389 m->m_len = m->m_pkthdr.len = sizeof(*greq); 1390 memset(greq, 0, sizeof(*greq)); 1391 greq->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1392 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); 1393 greq->mask = htobe64(1); 1394 t3_mgmt_tx(adap, m); 1395 1396 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); 1397 t3_tp_set_offload_mode(adap, 0); 1398 return (i); 1399} 1400 1401/** 1402 * setup_rss - configure Receive Side Steering (per-queue connection demux) 1403 * @adap: the adapter 1404 * 1405 * Sets up RSS to distribute packets to multiple receive queues. We 1406 * configure the RSS CPU lookup table to distribute to the number of HW 1407 * receive queues, and the response queue lookup table to narrow that 1408 * down to the response queues actually configured for each port. 1409 * We always configure the RSS mapping for two ports since the mapping 1410 * table has plenty of entries. 1411 */ 1412static void 1413setup_rss(adapter_t *adap) 1414{ 1415 int i; 1416 u_int nq[2]; 1417 uint8_t cpus[SGE_QSETS + 1]; 1418 uint16_t rspq_map[RSS_TABLE_SIZE]; 1419 1420 for (i = 0; i < SGE_QSETS; ++i) 1421 cpus[i] = i; 1422 cpus[SGE_QSETS] = 0xff; 1423 1424 nq[0] = nq[1] = 0; 1425 for_each_port(adap, i) { 1426 const struct port_info *pi = adap2pinfo(adap, i); 1427 1428 nq[pi->tx_chan] += pi->nqsets; 1429 } 1430 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1431 rspq_map[i] = nq[0] ? i % nq[0] : 0; 1432 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; 1433 } 1434 1435 /* Calculate the reverse RSS map table */ 1436 for (i = 0; i < SGE_QSETS; ++i) 1437 adap->rrss_map[i] = 0xff; 1438 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1439 if (adap->rrss_map[rspq_map[i]] == 0xff) 1440 adap->rrss_map[rspq_map[i]] = i; 1441 1442 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1443 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1444 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, 1445 cpus, rspq_map); 1446 1447} 1448 1449/* 1450 * Sends an mbuf to an offload queue driver 1451 * after dealing with any active network taps. 1452 */ 1453static inline int 1454offload_tx(struct t3cdev *tdev, struct mbuf *m) 1455{ 1456 int ret; 1457 1458 ret = t3_offload_tx(tdev, m); 1459 return (ret); 1460} 1461 1462static int 1463write_smt_entry(struct adapter *adapter, int idx) 1464{ 1465 struct port_info *pi = &adapter->port[idx]; 1466 struct cpl_smt_write_req *req; 1467 struct mbuf *m; 1468 1469 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) 1470 return (ENOMEM); 1471 1472 req = mtod(m, struct cpl_smt_write_req *); 1473 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); 1474 1475 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 1476 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); 1477 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ 1478 req->iff = idx; 1479 memset(req->src_mac1, 0, sizeof(req->src_mac1)); 1480 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); 1481 1482 m_set_priority(m, 1); 1483 1484 offload_tx(&adapter->tdev, m); 1485 1486 return (0); 1487} 1488 1489static int 1490init_smt(struct adapter *adapter) 1491{ 1492 int i; 1493 1494 for_each_port(adapter, i) 1495 write_smt_entry(adapter, i); 1496 return 0; 1497} 1498 1499static void 1500init_port_mtus(adapter_t *adapter) 1501{ 1502 unsigned int mtus = ETHERMTU | (ETHERMTU << 16); 1503 1504 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); 1505} 1506 1507static void 1508send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1509 int hi, int port) 1510{ 1511 struct mbuf *m; 1512 struct mngt_pktsched_wr *req; 1513 1514 m = m_gethdr(M_DONTWAIT, MT_DATA); 1515 if (m) { 1516 req = mtod(m, struct mngt_pktsched_wr *); 1517 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1518 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1519 req->sched = sched; 1520 req->idx = qidx; 1521 req->min = lo; 1522 req->max = hi; 1523 req->binding = port; 1524 m->m_len = m->m_pkthdr.len = sizeof(*req); 1525 t3_mgmt_tx(adap, m); 1526 } 1527} 1528 1529static void 1530bind_qsets(adapter_t *sc) 1531{ 1532 int i, j; 1533 1534 for (i = 0; i < (sc)->params.nports; ++i) { 1535 const struct port_info *pi = adap2pinfo(sc, i); 1536 1537 for (j = 0; j < pi->nqsets; ++j) { 1538 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1539 -1, pi->tx_chan); 1540 1541 } 1542 } 1543} 1544 1545static void 1546update_tpeeprom(struct adapter *adap) 1547{ 1548 const struct firmware *tpeeprom; 1549 1550 uint32_t version; 1551 unsigned int major, minor; 1552 int ret, len; 1553 char rev, name[32]; 1554 1555 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); 1556 1557 major = G_TP_VERSION_MAJOR(version); 1558 minor = G_TP_VERSION_MINOR(version); 1559 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) 1560 return; 1561 1562 rev = t3rev2char(adap); 1563 snprintf(name, sizeof(name), TPEEPROM_NAME, rev); 1564 1565 tpeeprom = firmware_get(name); 1566 if (tpeeprom == NULL) { 1567 device_printf(adap->dev, 1568 "could not load TP EEPROM: unable to load %s\n", 1569 name); 1570 return; 1571 } 1572 1573 len = tpeeprom->datasize - 4; 1574 1575 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); 1576 if (ret) 1577 goto release_tpeeprom; 1578 1579 if (len != TP_SRAM_LEN) { 1580 device_printf(adap->dev, 1581 "%s length is wrong len=%d expected=%d\n", name, 1582 len, TP_SRAM_LEN); 1583 return; 1584 } 1585 1586 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, 1587 TP_SRAM_OFFSET); 1588 1589 if (!ret) { 1590 device_printf(adap->dev, 1591 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", 1592 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 1593 } else 1594 device_printf(adap->dev, 1595 "Protocol SRAM image update in EEPROM failed\n"); 1596 1597release_tpeeprom: 1598 firmware_put(tpeeprom, FIRMWARE_UNLOAD); 1599 1600 return; 1601} 1602 1603static int 1604update_tpsram(struct adapter *adap) 1605{ 1606 const struct firmware *tpsram; 1607 int ret; 1608 char rev, name[32]; 1609 1610 rev = t3rev2char(adap); 1611 snprintf(name, sizeof(name), TPSRAM_NAME, rev); 1612 1613 update_tpeeprom(adap); 1614 1615 tpsram = firmware_get(name); 1616 if (tpsram == NULL){ 1617 device_printf(adap->dev, "could not load TP SRAM\n"); 1618 return (EINVAL); 1619 } else 1620 device_printf(adap->dev, "updating TP SRAM\n"); 1621 1622 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); 1623 if (ret) 1624 goto release_tpsram; 1625 1626 ret = t3_set_proto_sram(adap, tpsram->data); 1627 if (ret) 1628 device_printf(adap->dev, "loading protocol SRAM failed\n"); 1629 1630release_tpsram: 1631 firmware_put(tpsram, FIRMWARE_UNLOAD); 1632 1633 return ret; 1634} 1635 1636/** 1637 * cxgb_up - enable the adapter 1638 * @adap: adapter being enabled 1639 * 1640 * Called when the first port is enabled, this function performs the 1641 * actions necessary to make an adapter operational, such as completing 1642 * the initialization of HW modules, and enabling interrupts. 1643 */ 1644static int 1645cxgb_up(struct adapter *sc) 1646{ 1647 int err = 0; 1648 1649 KASSERT(sc->open_device_map == 0, ("%s: device(s) already open (%x)", 1650 __func__, sc->open_device_map)); 1651 1652 if ((sc->flags & FULL_INIT_DONE) == 0) { 1653 1654 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1655 1656 if ((sc->flags & FW_UPTODATE) == 0) 1657 if ((err = upgrade_fw(sc))) 1658 goto out; 1659 1660 if ((sc->flags & TPS_UPTODATE) == 0) 1661 if ((err = update_tpsram(sc))) 1662 goto out; 1663 1664 err = t3_init_hw(sc, 0); 1665 if (err) 1666 goto out; 1667 1668 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); 1669 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1670 1671 err = setup_sge_qsets(sc); 1672 if (err) 1673 goto out; 1674 1675 setup_rss(sc); 1676 1677 t3_intr_clear(sc); 1678 err = cxgb_setup_interrupts(sc); 1679 if (err) 1680 goto out; 1681 1682 t3_add_configured_sysctls(sc); 1683 sc->flags |= FULL_INIT_DONE; 1684 } 1685 1686 t3_intr_clear(sc); 1687 t3_sge_start(sc); 1688 t3_intr_enable(sc); 1689 1690 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && 1691 is_offload(sc) && init_tp_parity(sc) == 0) 1692 sc->flags |= TP_PARITY_INIT; 1693 1694 if (sc->flags & TP_PARITY_INIT) { 1695 t3_write_reg(sc, A_TP_INT_CAUSE, F_CMCACHEPERR | F_ARPLUTPERR); 1696 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); 1697 } 1698 1699 if (!(sc->flags & QUEUES_BOUND)) { 1700 bind_qsets(sc); 1701 sc->flags |= QUEUES_BOUND; 1702 } 1703 1704 t3_sge_reset_adapter(sc); 1705out: 1706 return (err); 1707} 1708 1709/* 1710 * Called when the last open device is closed. Does NOT undo all of cxgb_up's 1711 * work. Specifically, the resources grabbed under FULL_INIT_DONE are released 1712 * during controller_detach, not here. 1713 */ 1714static void 1715cxgb_down(struct adapter *sc) 1716{ 1717 t3_sge_stop(sc); 1718 t3_intr_disable(sc); 1719} 1720 1721static int 1722offload_open(struct port_info *pi) 1723{ 1724 struct adapter *sc = pi->adapter; 1725 struct t3cdev *tdev = &sc->tdev; 1726 1727 setbit(&sc->open_device_map, OFFLOAD_DEVMAP_BIT); 1728 1729 t3_tp_set_offload_mode(sc, 1); 1730 tdev->lldev = pi->ifp; 1731 init_port_mtus(sc); 1732 t3_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd, 1733 sc->params.rev == 0 ? sc->port[0].ifp->if_mtu : 0xffff); 1734 init_smt(sc); 1735 cxgb_add_clients(tdev); 1736 1737 return (0); 1738} 1739 1740static int 1741offload_close(struct t3cdev *tdev) 1742{ 1743 struct adapter *adapter = tdev2adap(tdev); 1744 1745 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) 1746 return (0); 1747 1748 /* Call back all registered clients */ 1749 cxgb_remove_clients(tdev); 1750 1751 tdev->lldev = NULL; 1752 cxgb_set_dummy_ops(tdev); 1753 t3_tp_set_offload_mode(adapter, 0); 1754 1755 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); 1756 1757 return (0); 1758} 1759 1760/* 1761 * if_init for cxgb ports. 1762 */ 1763static void 1764cxgb_init(void *arg) 1765{ 1766 struct port_info *p = arg; 1767 struct adapter *sc = p->adapter; 1768 1769 ADAPTER_LOCK(sc); 1770 cxgb_init_locked(p); /* releases adapter lock */ 1771 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1772} 1773 1774static int 1775cxgb_init_locked(struct port_info *p) 1776{ 1777 struct adapter *sc = p->adapter; 1778 struct ifnet *ifp = p->ifp; 1779 struct cmac *mac = &p->mac; 1780 int i, rc = 0, may_sleep = 0; 1781 1782 ADAPTER_LOCK_ASSERT_OWNED(sc); 1783 1784 while (!IS_DOOMED(p) && IS_BUSY(sc)) { 1785 if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, "cxgbinit", 0)) { 1786 rc = EINTR; 1787 goto done; 1788 } 1789 } 1790 if (IS_DOOMED(p)) { 1791 rc = ENXIO; 1792 goto done; 1793 } 1794 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 1795 1796 /* 1797 * The code that runs during one-time adapter initialization can sleep 1798 * so it's important not to hold any locks across it. 1799 */ 1800 may_sleep = sc->flags & FULL_INIT_DONE ? 0 : 1; 1801 1802 if (may_sleep) { 1803 SET_BUSY(sc); 1804 ADAPTER_UNLOCK(sc); 1805 } 1806 1807 if (sc->open_device_map == 0) { 1808 if ((rc = cxgb_up(sc)) != 0) 1809 goto done; 1810 1811 if (is_offload(sc) && !ofld_disable && offload_open(p)) 1812 log(LOG_WARNING, 1813 "Could not initialize offload capabilities\n"); 1814 } 1815 1816 PORT_LOCK(p); 1817 if (isset(&sc->open_device_map, p->port_id) && 1818 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1819 PORT_UNLOCK(p); 1820 goto done; 1821 } 1822 t3_port_intr_enable(sc, p->port_id); 1823 if (!mac->multiport) 1824 t3_mac_init(mac); 1825 cxgb_update_mac_settings(p); 1826 t3_link_start(&p->phy, mac, &p->link_config); 1827 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1828 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1829 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1830 PORT_UNLOCK(p); 1831 1832 t3_link_changed(sc, p->port_id); 1833 1834 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) { 1835 struct sge_qset *qs = &sc->sge.qs[i]; 1836 struct sge_txq *txq = &qs->txq[TXQ_ETH]; 1837 1838 callout_reset_on(&txq->txq_watchdog, hz, cxgb_tx_watchdog, qs, 1839 txq->txq_watchdog.c_cpu); 1840 } 1841 1842 /* all ok */ 1843 setbit(&sc->open_device_map, p->port_id); 1844 1845done: 1846 if (may_sleep) { 1847 ADAPTER_LOCK(sc); 1848 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 1849 CLR_BUSY(sc); 1850 wakeup_one(&sc->flags); 1851 } 1852 ADAPTER_UNLOCK(sc); 1853 return (rc); 1854} 1855 1856static int 1857cxgb_uninit_locked(struct port_info *p) 1858{ 1859 struct adapter *sc = p->adapter; 1860 int rc; 1861 1862 ADAPTER_LOCK_ASSERT_OWNED(sc); 1863 1864 while (!IS_DOOMED(p) && IS_BUSY(sc)) { 1865 if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, "cxgbunin", 0)) { 1866 rc = EINTR; 1867 goto done; 1868 } 1869 } 1870 if (IS_DOOMED(p)) { 1871 rc = ENXIO; 1872 goto done; 1873 } 1874 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 1875 SET_BUSY(sc); 1876 ADAPTER_UNLOCK(sc); 1877 1878 rc = cxgb_uninit_synchronized(p); 1879 1880 ADAPTER_LOCK(sc); 1881 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 1882 CLR_BUSY(sc); 1883 wakeup_one(&sc->flags); 1884done: 1885 ADAPTER_UNLOCK(sc); 1886 return (rc); 1887} 1888 1889/* 1890 * Called on "ifconfig down", and from port_detach 1891 */ 1892static int 1893cxgb_uninit_synchronized(struct port_info *pi) 1894{ 1895 struct adapter *sc = pi->adapter; 1896 struct ifnet *ifp = pi->ifp; 1897 1898 /* 1899 * taskqueue_drain may cause a deadlock if the adapter lock is held. 1900 */ 1901 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1902 1903 /* 1904 * Clear this port's bit from the open device map, and then drain all 1905 * the tasks that can access/manipulate this port's port_info or ifp. 1906 * We disable this port's interrupts here and so the the slow/ext 1907 * interrupt tasks won't be enqueued. The tick task will continue to 1908 * be enqueued every second but the runs after this drain will not see 1909 * this port in the open device map. 1910 * 1911 * A well behaved task must take open_device_map into account and ignore 1912 * ports that are not open. 1913 */ 1914 clrbit(&sc->open_device_map, pi->port_id); 1915 t3_port_intr_disable(sc, pi->port_id); 1916 taskqueue_drain(sc->tq, &sc->slow_intr_task); 1917 taskqueue_drain(sc->tq, &sc->ext_intr_task); 1918 taskqueue_drain(sc->tq, &sc->tick_task); 1919 1920 PORT_LOCK(pi); 1921 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1922 1923 /* disable pause frames */ 1924 t3_set_reg_field(sc, A_XGM_TX_CFG + pi->mac.offset, F_TXPAUSEEN, 0); 1925 1926 /* Reset RX FIFO HWM */ 1927 t3_set_reg_field(sc, A_XGM_RXFIFO_CFG + pi->mac.offset, 1928 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); 1929 1930 DELAY(100 * 1000); 1931 1932 /* Wait for TXFIFO empty */ 1933 t3_wait_op_done(sc, A_XGM_TXFIFO_CFG + pi->mac.offset, 1934 F_TXFIFO_EMPTY, 1, 20, 5); 1935 1936 DELAY(100 * 1000); 1937 t3_mac_disable(&pi->mac, MAC_DIRECTION_RX); 1938 1939 1940 pi->phy.ops->power_down(&pi->phy, 1); 1941 1942 PORT_UNLOCK(pi); 1943 1944 pi->link_config.link_ok = 0; 1945 t3_os_link_changed(sc, pi->port_id, 0, 0, 0, 0, 0); 1946 1947 if ((sc->open_device_map & PORT_MASK) == 0) 1948 offload_close(&sc->tdev); 1949 1950 if (sc->open_device_map == 0) 1951 cxgb_down(pi->adapter); 1952 1953 return (0); 1954} 1955 1956/* 1957 * Mark lro enabled or disabled in all qsets for this port 1958 */ 1959static int 1960cxgb_set_lro(struct port_info *p, int enabled) 1961{ 1962 int i; 1963 struct adapter *adp = p->adapter; 1964 struct sge_qset *q; 1965 1966 PORT_LOCK_ASSERT_OWNED(p); 1967 for (i = 0; i < p->nqsets; i++) { 1968 q = &adp->sge.qs[p->first_qset + i]; 1969 q->lro.enabled = (enabled != 0); 1970 } 1971 return (0); 1972} 1973 1974static int 1975cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) 1976{ 1977 struct port_info *p = ifp->if_softc; 1978 struct adapter *sc = p->adapter; 1979 struct ifreq *ifr = (struct ifreq *)data; 1980 int flags, error = 0, mtu; 1981 uint32_t mask; 1982 1983 switch (command) { 1984 case SIOCSIFMTU: 1985 ADAPTER_LOCK(sc); 1986 error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 1987 if (error) { 1988fail: 1989 ADAPTER_UNLOCK(sc); 1990 return (error); 1991 } 1992 1993 mtu = ifr->ifr_mtu; 1994 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) { 1995 error = EINVAL; 1996 } else { 1997 ifp->if_mtu = mtu; 1998 PORT_LOCK(p); 1999 cxgb_update_mac_settings(p); 2000 PORT_UNLOCK(p); 2001 } 2002 ADAPTER_UNLOCK(sc); 2003 break; 2004 case SIOCSIFFLAGS: 2005 ADAPTER_LOCK(sc); 2006 if (IS_DOOMED(p)) { 2007 error = ENXIO; 2008 goto fail; 2009 } 2010 if (ifp->if_flags & IFF_UP) { 2011 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2012 flags = p->if_flags; 2013 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 2014 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) { 2015 if (IS_BUSY(sc)) { 2016 error = EBUSY; 2017 goto fail; 2018 } 2019 PORT_LOCK(p); 2020 cxgb_update_mac_settings(p); 2021 PORT_UNLOCK(p); 2022 } 2023 ADAPTER_UNLOCK(sc); 2024 } else 2025 error = cxgb_init_locked(p); 2026 p->if_flags = ifp->if_flags; 2027 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2028 error = cxgb_uninit_locked(p); 2029 else 2030 ADAPTER_UNLOCK(sc); 2031 2032 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 2033 break; 2034 case SIOCADDMULTI: 2035 case SIOCDELMULTI: 2036 ADAPTER_LOCK(sc); 2037 error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2038 if (error) 2039 goto fail; 2040 2041 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2042 PORT_LOCK(p); 2043 cxgb_update_mac_settings(p); 2044 PORT_UNLOCK(p); 2045 } 2046 ADAPTER_UNLOCK(sc); 2047 2048 break; 2049 case SIOCSIFCAP: 2050 ADAPTER_LOCK(sc); 2051 error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2052 if (error) 2053 goto fail; 2054 2055 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2056 if (mask & IFCAP_TXCSUM) { 2057 ifp->if_capenable ^= IFCAP_TXCSUM; 2058 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2059 2060 if (IFCAP_TSO & ifp->if_capenable && 2061 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2062 ifp->if_capenable &= ~IFCAP_TSO; 2063 ifp->if_hwassist &= ~CSUM_TSO; 2064 if_printf(ifp, 2065 "tso disabled due to -txcsum.\n"); 2066 } 2067 } 2068 if (mask & IFCAP_RXCSUM) 2069 ifp->if_capenable ^= IFCAP_RXCSUM; 2070 if (mask & IFCAP_TSO4) { 2071 ifp->if_capenable ^= IFCAP_TSO4; 2072 2073 if (IFCAP_TSO & ifp->if_capenable) { 2074 if (IFCAP_TXCSUM & ifp->if_capenable) 2075 ifp->if_hwassist |= CSUM_TSO; 2076 else { 2077 ifp->if_capenable &= ~IFCAP_TSO; 2078 ifp->if_hwassist &= ~CSUM_TSO; 2079 if_printf(ifp, 2080 "enable txcsum first.\n"); 2081 error = EAGAIN; 2082 } 2083 } else 2084 ifp->if_hwassist &= ~CSUM_TSO; 2085 } 2086 if (mask & IFCAP_LRO) { 2087 ifp->if_capenable ^= IFCAP_LRO; 2088 2089 /* Safe to do this even if cxgb_up not called yet */ 2090 cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO); 2091 } 2092 if (mask & IFCAP_VLAN_HWTAGGING) { 2093 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2094 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2095 PORT_LOCK(p); 2096 cxgb_update_mac_settings(p); 2097 PORT_UNLOCK(p); 2098 } 2099 } 2100 if (mask & IFCAP_VLAN_MTU) { 2101 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2102 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2103 PORT_LOCK(p); 2104 cxgb_update_mac_settings(p); 2105 PORT_UNLOCK(p); 2106 } 2107 } 2108 if (mask & IFCAP_VLAN_HWTSO) 2109 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2110 if (mask & IFCAP_VLAN_HWCSUM) 2111 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2112 2113#ifdef VLAN_CAPABILITIES 2114 VLAN_CAPABILITIES(ifp); 2115#endif 2116 ADAPTER_UNLOCK(sc); 2117 break; 2118 case SIOCSIFMEDIA: 2119 case SIOCGIFMEDIA: 2120 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 2121 break; 2122 default: 2123 error = ether_ioctl(ifp, command, data); 2124 } 2125 2126 return (error); 2127} 2128 2129static int 2130cxgb_media_change(struct ifnet *ifp) 2131{ 2132 return (EOPNOTSUPP); 2133} 2134 2135/* 2136 * Translates phy->modtype to the correct Ethernet media subtype. 2137 */ 2138static int 2139cxgb_ifm_type(int mod) 2140{ 2141 switch (mod) { 2142 case phy_modtype_sr: 2143 return (IFM_10G_SR); 2144 case phy_modtype_lr: 2145 return (IFM_10G_LR); 2146 case phy_modtype_lrm: 2147 return (IFM_10G_LRM); 2148 case phy_modtype_twinax: 2149 return (IFM_10G_TWINAX); 2150 case phy_modtype_twinax_long: 2151 return (IFM_10G_TWINAX_LONG); 2152 case phy_modtype_none: 2153 return (IFM_NONE); 2154 case phy_modtype_unknown: 2155 return (IFM_UNKNOWN); 2156 } 2157 2158 KASSERT(0, ("%s: modtype %d unknown", __func__, mod)); 2159 return (IFM_UNKNOWN); 2160} 2161 2162/* 2163 * Rebuilds the ifmedia list for this port, and sets the current media. 2164 */ 2165static void 2166cxgb_build_medialist(struct port_info *p) 2167{ 2168 struct cphy *phy = &p->phy; 2169 struct ifmedia *media = &p->media; 2170 int mod = phy->modtype; 2171 int m = IFM_ETHER | IFM_FDX; 2172 2173 PORT_LOCK(p); 2174 2175 ifmedia_removeall(media); 2176 if (phy->caps & SUPPORTED_TP && phy->caps & SUPPORTED_Autoneg) { 2177 /* Copper (RJ45) */ 2178 2179 if (phy->caps & SUPPORTED_10000baseT_Full) 2180 ifmedia_add(media, m | IFM_10G_T, mod, NULL); 2181 2182 if (phy->caps & SUPPORTED_1000baseT_Full) 2183 ifmedia_add(media, m | IFM_1000_T, mod, NULL); 2184 2185 if (phy->caps & SUPPORTED_100baseT_Full) 2186 ifmedia_add(media, m | IFM_100_TX, mod, NULL); 2187 2188 if (phy->caps & SUPPORTED_10baseT_Full) 2189 ifmedia_add(media, m | IFM_10_T, mod, NULL); 2190 2191 ifmedia_add(media, IFM_ETHER | IFM_AUTO, mod, NULL); 2192 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 2193 2194 } else if (phy->caps & SUPPORTED_TP) { 2195 /* Copper (CX4) */ 2196 2197 KASSERT(phy->caps & SUPPORTED_10000baseT_Full, 2198 ("%s: unexpected cap 0x%x", __func__, phy->caps)); 2199 2200 ifmedia_add(media, m | IFM_10G_CX4, mod, NULL); 2201 ifmedia_set(media, m | IFM_10G_CX4); 2202 2203 } else if (phy->caps & SUPPORTED_FIBRE && 2204 phy->caps & SUPPORTED_10000baseT_Full) { 2205 /* 10G optical (but includes SFP+ twinax) */ 2206 2207 m |= cxgb_ifm_type(mod); 2208 if (IFM_SUBTYPE(m) == IFM_NONE) 2209 m &= ~IFM_FDX; 2210 2211 ifmedia_add(media, m, mod, NULL); 2212 ifmedia_set(media, m); 2213 2214 } else if (phy->caps & SUPPORTED_FIBRE && 2215 phy->caps & SUPPORTED_1000baseT_Full) { 2216 /* 1G optical */ 2217 2218 /* XXX: Lie and claim to be SX, could actually be any 1G-X */ 2219 ifmedia_add(media, m | IFM_1000_SX, mod, NULL); 2220 ifmedia_set(media, m | IFM_1000_SX); 2221 2222 } else { 2223 KASSERT(0, ("%s: don't know how to handle 0x%x.", __func__, 2224 phy->caps)); 2225 } 2226 2227 PORT_UNLOCK(p); 2228} 2229 2230static void 2231cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2232{ 2233 struct port_info *p = ifp->if_softc; 2234 struct ifmedia_entry *cur = p->media.ifm_cur; 2235 int speed = p->link_config.speed; 2236 2237 if (cur->ifm_data != p->phy.modtype) { 2238 cxgb_build_medialist(p); 2239 cur = p->media.ifm_cur; 2240 } 2241 2242 ifmr->ifm_status = IFM_AVALID; 2243 if (!p->link_config.link_ok) 2244 return; 2245 2246 ifmr->ifm_status |= IFM_ACTIVE; 2247 2248 /* 2249 * active and current will differ iff current media is autoselect. That 2250 * can happen only for copper RJ45. 2251 */ 2252 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2253 return; 2254 KASSERT(p->phy.caps & SUPPORTED_TP && p->phy.caps & SUPPORTED_Autoneg, 2255 ("%s: unexpected PHY caps 0x%x", __func__, p->phy.caps)); 2256 2257 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2258 if (speed == SPEED_10000) 2259 ifmr->ifm_active |= IFM_10G_T; 2260 else if (speed == SPEED_1000) 2261 ifmr->ifm_active |= IFM_1000_T; 2262 else if (speed == SPEED_100) 2263 ifmr->ifm_active |= IFM_100_TX; 2264 else if (speed == SPEED_10) 2265 ifmr->ifm_active |= IFM_10_T; 2266 else 2267 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 2268 speed)); 2269} 2270 2271static void 2272cxgb_async_intr(void *data) 2273{ 2274 adapter_t *sc = data; 2275 2276 if (cxgb_debug) 2277 device_printf(sc->dev, "cxgb_async_intr\n"); 2278 /* 2279 * May need to sleep - defer to taskqueue 2280 */ 2281 taskqueue_enqueue(sc->tq, &sc->slow_intr_task); 2282} 2283 2284static void 2285cxgb_ext_intr_handler(void *arg, int count) 2286{ 2287 adapter_t *sc = (adapter_t *)arg; 2288 2289 if (cxgb_debug) 2290 printf("cxgb_ext_intr_handler\n"); 2291 2292 t3_phy_intr_handler(sc); 2293 2294 /* Now reenable external interrupts */ 2295 ADAPTER_LOCK(sc); 2296 if (sc->slow_intr_mask) { 2297 sc->slow_intr_mask |= F_T3DBG; 2298 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 2299 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 2300 } 2301 ADAPTER_UNLOCK(sc); 2302} 2303 2304static inline int 2305link_poll_needed(struct port_info *p) 2306{ 2307 struct cphy *phy = &p->phy; 2308 2309 if (phy->caps & POLL_LINK_1ST_TIME) { 2310 p->phy.caps &= ~POLL_LINK_1ST_TIME; 2311 return (1); 2312 } 2313 2314 return (p->link_fault || !(phy->caps & SUPPORTED_LINK_IRQ)); 2315} 2316 2317static void 2318check_link_status(adapter_t *sc) 2319{ 2320 int i; 2321 2322 for (i = 0; i < (sc)->params.nports; ++i) { 2323 struct port_info *p = &sc->port[i]; 2324 2325 if (!isset(&sc->open_device_map, p->port_id)) 2326 continue; 2327 2328 if (link_poll_needed(p)) 2329 t3_link_changed(sc, i); 2330 } 2331} 2332 2333static void 2334check_t3b2_mac(struct adapter *sc) 2335{ 2336 int i; 2337 2338 if (sc->flags & CXGB_SHUTDOWN) 2339 return; 2340 2341 for_each_port(sc, i) { 2342 struct port_info *p = &sc->port[i]; 2343 int status; 2344#ifdef INVARIANTS 2345 struct ifnet *ifp = p->ifp; 2346#endif 2347 2348 if (!isset(&sc->open_device_map, p->port_id) || p->link_fault || 2349 !p->link_config.link_ok) 2350 continue; 2351 2352 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, 2353 ("%s: state mismatch (drv_flags %x, device_map %x)", 2354 __func__, ifp->if_drv_flags, sc->open_device_map)); 2355 2356 PORT_LOCK(p); 2357 status = t3b2_mac_watchdog_task(&p->mac); 2358 if (status == 1) 2359 p->mac.stats.num_toggled++; 2360 else if (status == 2) { 2361 struct cmac *mac = &p->mac; 2362 2363 cxgb_update_mac_settings(p); 2364 t3_link_start(&p->phy, mac, &p->link_config); 2365 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 2366 t3_port_intr_enable(sc, p->port_id); 2367 p->mac.stats.num_resets++; 2368 } 2369 PORT_UNLOCK(p); 2370 } 2371} 2372 2373static void 2374cxgb_tick(void *arg) 2375{ 2376 adapter_t *sc = (adapter_t *)arg; 2377 2378 if (sc->flags & CXGB_SHUTDOWN) 2379 return; 2380 2381 taskqueue_enqueue(sc->tq, &sc->tick_task); 2382 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc); 2383} 2384 2385static void 2386cxgb_tick_handler(void *arg, int count) 2387{ 2388 adapter_t *sc = (adapter_t *)arg; 2389 const struct adapter_params *p = &sc->params; 2390 int i; 2391 uint32_t cause, reset; 2392 2393 if (sc->flags & CXGB_SHUTDOWN || !(sc->flags & FULL_INIT_DONE)) 2394 return; 2395 2396 check_link_status(sc); 2397 2398 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) 2399 check_t3b2_mac(sc); 2400 2401 cause = t3_read_reg(sc, A_SG_INT_CAUSE); 2402 reset = 0; 2403 if (cause & F_FLEMPTY) { 2404 struct sge_qset *qs = &sc->sge.qs[0]; 2405 2406 i = 0; 2407 reset |= F_FLEMPTY; 2408 2409 cause = (t3_read_reg(sc, A_SG_RSPQ_FL_STATUS) >> 2410 S_FL0EMPTY) & 0xffff; 2411 while (cause) { 2412 qs->fl[i].empty += (cause & 1); 2413 if (i) 2414 qs++; 2415 i ^= 1; 2416 cause >>= 1; 2417 } 2418 } 2419 t3_write_reg(sc, A_SG_INT_CAUSE, reset); 2420 2421 for (i = 0; i < sc->params.nports; i++) { 2422 struct port_info *pi = &sc->port[i]; 2423 struct ifnet *ifp = pi->ifp; 2424 struct cmac *mac = &pi->mac; 2425 struct mac_stats *mstats = &mac->stats; 2426 2427 if (!isset(&sc->open_device_map, pi->port_id)) 2428 continue; 2429 2430 PORT_LOCK(pi); 2431 t3_mac_update_stats(mac); 2432 PORT_UNLOCK(pi); 2433 2434 ifp->if_opackets = 2435 mstats->tx_frames_64 + 2436 mstats->tx_frames_65_127 + 2437 mstats->tx_frames_128_255 + 2438 mstats->tx_frames_256_511 + 2439 mstats->tx_frames_512_1023 + 2440 mstats->tx_frames_1024_1518 + 2441 mstats->tx_frames_1519_max; 2442 2443 ifp->if_ipackets = 2444 mstats->rx_frames_64 + 2445 mstats->rx_frames_65_127 + 2446 mstats->rx_frames_128_255 + 2447 mstats->rx_frames_256_511 + 2448 mstats->rx_frames_512_1023 + 2449 mstats->rx_frames_1024_1518 + 2450 mstats->rx_frames_1519_max; 2451 2452 ifp->if_obytes = mstats->tx_octets; 2453 ifp->if_ibytes = mstats->rx_octets; 2454 ifp->if_omcasts = mstats->tx_mcast_frames; 2455 ifp->if_imcasts = mstats->rx_mcast_frames; 2456 2457 ifp->if_collisions = 2458 mstats->tx_total_collisions; 2459 2460 ifp->if_iqdrops = mstats->rx_cong_drops; 2461 2462 ifp->if_oerrors = 2463 mstats->tx_excess_collisions + 2464 mstats->tx_underrun + 2465 mstats->tx_len_errs + 2466 mstats->tx_mac_internal_errs + 2467 mstats->tx_excess_deferral + 2468 mstats->tx_fcs_errs; 2469 ifp->if_ierrors = 2470 mstats->rx_jabber + 2471 mstats->rx_data_errs + 2472 mstats->rx_sequence_errs + 2473 mstats->rx_runt + 2474 mstats->rx_too_long + 2475 mstats->rx_mac_internal_errs + 2476 mstats->rx_short + 2477 mstats->rx_fcs_errs; 2478 2479 if (mac->multiport) 2480 continue; 2481 2482 /* Count rx fifo overflows, once per second */ 2483 cause = t3_read_reg(sc, A_XGM_INT_CAUSE + mac->offset); 2484 reset = 0; 2485 if (cause & F_RXFIFO_OVERFLOW) { 2486 mac->stats.rx_fifo_ovfl++; 2487 reset |= F_RXFIFO_OVERFLOW; 2488 } 2489 t3_write_reg(sc, A_XGM_INT_CAUSE + mac->offset, reset); 2490 } 2491} 2492 2493static void 2494touch_bars(device_t dev) 2495{ 2496 /* 2497 * Don't enable yet 2498 */ 2499#if !defined(__LP64__) && 0 2500 u32 v; 2501 2502 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 2503 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 2504 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 2505 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 2506 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 2507 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 2508#endif 2509} 2510 2511static int 2512set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) 2513{ 2514 uint8_t *buf; 2515 int err = 0; 2516 u32 aligned_offset, aligned_len, *p; 2517 struct adapter *adapter = pi->adapter; 2518 2519 2520 aligned_offset = offset & ~3; 2521 aligned_len = (len + (offset & 3) + 3) & ~3; 2522 2523 if (aligned_offset != offset || aligned_len != len) { 2524 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); 2525 if (!buf) 2526 return (ENOMEM); 2527 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); 2528 if (!err && aligned_len > 4) 2529 err = t3_seeprom_read(adapter, 2530 aligned_offset + aligned_len - 4, 2531 (u32 *)&buf[aligned_len - 4]); 2532 if (err) 2533 goto out; 2534 memcpy(buf + (offset & 3), data, len); 2535 } else 2536 buf = (uint8_t *)(uintptr_t)data; 2537 2538 err = t3_seeprom_wp(adapter, 0); 2539 if (err) 2540 goto out; 2541 2542 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 2543 err = t3_seeprom_write(adapter, aligned_offset, *p); 2544 aligned_offset += 4; 2545 } 2546 2547 if (!err) 2548 err = t3_seeprom_wp(adapter, 1); 2549out: 2550 if (buf != data) 2551 free(buf, M_DEVBUF); 2552 return err; 2553} 2554 2555 2556static int 2557in_range(int val, int lo, int hi) 2558{ 2559 return val < 0 || (val <= hi && val >= lo); 2560} 2561 2562static int 2563cxgb_extension_open(struct cdev *dev, int flags, int fmp, struct thread *td) 2564{ 2565 return (0); 2566} 2567 2568static int 2569cxgb_extension_close(struct cdev *dev, int flags, int fmt, struct thread *td) 2570{ 2571 return (0); 2572} 2573 2574static int 2575cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, 2576 int fflag, struct thread *td) 2577{ 2578 int mmd, error = 0; 2579 struct port_info *pi = dev->si_drv1; 2580 adapter_t *sc = pi->adapter; 2581 2582#ifdef PRIV_SUPPORTED 2583 if (priv_check(td, PRIV_DRIVER)) { 2584 if (cxgb_debug) 2585 printf("user does not have access to privileged ioctls\n"); 2586 return (EPERM); 2587 } 2588#else 2589 if (suser(td)) { 2590 if (cxgb_debug) 2591 printf("user does not have access to privileged ioctls\n"); 2592 return (EPERM); 2593 } 2594#endif 2595 2596 switch (cmd) { 2597 case CHELSIO_GET_MIIREG: { 2598 uint32_t val; 2599 struct cphy *phy = &pi->phy; 2600 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2601 2602 if (!phy->mdio_read) 2603 return (EOPNOTSUPP); 2604 if (is_10G(sc)) { 2605 mmd = mid->phy_id >> 8; 2606 if (!mmd) 2607 mmd = MDIO_DEV_PCS; 2608 else if (mmd > MDIO_DEV_VEND2) 2609 return (EINVAL); 2610 2611 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, 2612 mid->reg_num, &val); 2613 } else 2614 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, 2615 mid->reg_num & 0x1f, &val); 2616 if (error == 0) 2617 mid->val_out = val; 2618 break; 2619 } 2620 case CHELSIO_SET_MIIREG: { 2621 struct cphy *phy = &pi->phy; 2622 struct ch_mii_data *mid = (struct ch_mii_data *)data; 2623 2624 if (!phy->mdio_write) 2625 return (EOPNOTSUPP); 2626 if (is_10G(sc)) { 2627 mmd = mid->phy_id >> 8; 2628 if (!mmd) 2629 mmd = MDIO_DEV_PCS; 2630 else if (mmd > MDIO_DEV_VEND2) 2631 return (EINVAL); 2632 2633 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 2634 mmd, mid->reg_num, mid->val_in); 2635 } else 2636 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, 2637 mid->reg_num & 0x1f, 2638 mid->val_in); 2639 break; 2640 } 2641 case CHELSIO_SETREG: { 2642 struct ch_reg *edata = (struct ch_reg *)data; 2643 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2644 return (EFAULT); 2645 t3_write_reg(sc, edata->addr, edata->val); 2646 break; 2647 } 2648 case CHELSIO_GETREG: { 2649 struct ch_reg *edata = (struct ch_reg *)data; 2650 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2651 return (EFAULT); 2652 edata->val = t3_read_reg(sc, edata->addr); 2653 break; 2654 } 2655 case CHELSIO_GET_SGE_CONTEXT: { 2656 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; 2657 mtx_lock_spin(&sc->sge.reg_lock); 2658 switch (ecntxt->cntxt_type) { 2659 case CNTXT_TYPE_EGRESS: 2660 error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, 2661 ecntxt->data); 2662 break; 2663 case CNTXT_TYPE_FL: 2664 error = -t3_sge_read_fl(sc, ecntxt->cntxt_id, 2665 ecntxt->data); 2666 break; 2667 case CNTXT_TYPE_RSP: 2668 error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id, 2669 ecntxt->data); 2670 break; 2671 case CNTXT_TYPE_CQ: 2672 error = -t3_sge_read_cq(sc, ecntxt->cntxt_id, 2673 ecntxt->data); 2674 break; 2675 default: 2676 error = EINVAL; 2677 break; 2678 } 2679 mtx_unlock_spin(&sc->sge.reg_lock); 2680 break; 2681 } 2682 case CHELSIO_GET_SGE_DESC: { 2683 struct ch_desc *edesc = (struct ch_desc *)data; 2684 int ret; 2685 if (edesc->queue_num >= SGE_QSETS * 6) 2686 return (EINVAL); 2687 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], 2688 edesc->queue_num % 6, edesc->idx, edesc->data); 2689 if (ret < 0) 2690 return (EINVAL); 2691 edesc->size = ret; 2692 break; 2693 } 2694 case CHELSIO_GET_QSET_PARAMS: { 2695 struct qset_params *q; 2696 struct ch_qset_params *t = (struct ch_qset_params *)data; 2697 int q1 = pi->first_qset; 2698 int nqsets = pi->nqsets; 2699 int i; 2700 2701 if (t->qset_idx >= nqsets) 2702 return EINVAL; 2703 2704 i = q1 + t->qset_idx; 2705 q = &sc->params.sge.qset[i]; 2706 t->rspq_size = q->rspq_size; 2707 t->txq_size[0] = q->txq_size[0]; 2708 t->txq_size[1] = q->txq_size[1]; 2709 t->txq_size[2] = q->txq_size[2]; 2710 t->fl_size[0] = q->fl_size; 2711 t->fl_size[1] = q->jumbo_size; 2712 t->polling = q->polling; 2713 t->lro = q->lro; 2714 t->intr_lat = q->coalesce_usecs; 2715 t->cong_thres = q->cong_thres; 2716 t->qnum = i; 2717 2718 if ((sc->flags & FULL_INIT_DONE) == 0) 2719 t->vector = 0; 2720 else if (sc->flags & USING_MSIX) 2721 t->vector = rman_get_start(sc->msix_irq_res[i]); 2722 else 2723 t->vector = rman_get_start(sc->irq_res); 2724 2725 break; 2726 } 2727 case CHELSIO_GET_QSET_NUM: { 2728 struct ch_reg *edata = (struct ch_reg *)data; 2729 edata->val = pi->nqsets; 2730 break; 2731 } 2732 case CHELSIO_LOAD_FW: { 2733 uint8_t *fw_data; 2734 uint32_t vers; 2735 struct ch_mem_range *t = (struct ch_mem_range *)data; 2736 2737 /* 2738 * You're allowed to load a firmware only before FULL_INIT_DONE 2739 * 2740 * FW_UPTODATE is also set so the rest of the initialization 2741 * will not overwrite what was loaded here. This gives you the 2742 * flexibility to load any firmware (and maybe shoot yourself in 2743 * the foot). 2744 */ 2745 2746 ADAPTER_LOCK(sc); 2747 if (sc->open_device_map || sc->flags & FULL_INIT_DONE) { 2748 ADAPTER_UNLOCK(sc); 2749 return (EBUSY); 2750 } 2751 2752 fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2753 if (!fw_data) 2754 error = ENOMEM; 2755 else 2756 error = copyin(t->buf, fw_data, t->len); 2757 2758 if (!error) 2759 error = -t3_load_fw(sc, fw_data, t->len); 2760 2761 if (t3_get_fw_version(sc, &vers) == 0) { 2762 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), 2763 "%d.%d.%d", G_FW_VERSION_MAJOR(vers), 2764 G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); 2765 } 2766 2767 if (!error) 2768 sc->flags |= FW_UPTODATE; 2769 2770 free(fw_data, M_DEVBUF); 2771 ADAPTER_UNLOCK(sc); 2772 break; 2773 } 2774 case CHELSIO_LOAD_BOOT: { 2775 uint8_t *boot_data; 2776 struct ch_mem_range *t = (struct ch_mem_range *)data; 2777 2778 boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT); 2779 if (!boot_data) 2780 return ENOMEM; 2781 2782 error = copyin(t->buf, boot_data, t->len); 2783 if (!error) 2784 error = -t3_load_boot(sc, boot_data, t->len); 2785 2786 free(boot_data, M_DEVBUF); 2787 break; 2788 } 2789 case CHELSIO_GET_PM: { 2790 struct ch_pm *m = (struct ch_pm *)data; 2791 struct tp_params *p = &sc->params.tp; 2792 2793 if (!is_offload(sc)) 2794 return (EOPNOTSUPP); 2795 2796 m->tx_pg_sz = p->tx_pg_size; 2797 m->tx_num_pg = p->tx_num_pgs; 2798 m->rx_pg_sz = p->rx_pg_size; 2799 m->rx_num_pg = p->rx_num_pgs; 2800 m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; 2801 2802 break; 2803 } 2804 case CHELSIO_SET_PM: { 2805 struct ch_pm *m = (struct ch_pm *)data; 2806 struct tp_params *p = &sc->params.tp; 2807 2808 if (!is_offload(sc)) 2809 return (EOPNOTSUPP); 2810 if (sc->flags & FULL_INIT_DONE) 2811 return (EBUSY); 2812 2813 if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) || 2814 !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1))) 2815 return (EINVAL); /* not power of 2 */ 2816 if (!(m->rx_pg_sz & 0x14000)) 2817 return (EINVAL); /* not 16KB or 64KB */ 2818 if (!(m->tx_pg_sz & 0x1554000)) 2819 return (EINVAL); 2820 if (m->tx_num_pg == -1) 2821 m->tx_num_pg = p->tx_num_pgs; 2822 if (m->rx_num_pg == -1) 2823 m->rx_num_pg = p->rx_num_pgs; 2824 if (m->tx_num_pg % 24 || m->rx_num_pg % 24) 2825 return (EINVAL); 2826 if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size || 2827 m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size) 2828 return (EINVAL); 2829 2830 p->rx_pg_size = m->rx_pg_sz; 2831 p->tx_pg_size = m->tx_pg_sz; 2832 p->rx_num_pgs = m->rx_num_pg; 2833 p->tx_num_pgs = m->tx_num_pg; 2834 break; 2835 } 2836 case CHELSIO_SETMTUTAB: { 2837 struct ch_mtus *m = (struct ch_mtus *)data; 2838 int i; 2839 2840 if (!is_offload(sc)) 2841 return (EOPNOTSUPP); 2842 if (offload_running(sc)) 2843 return (EBUSY); 2844 if (m->nmtus != NMTUS) 2845 return (EINVAL); 2846 if (m->mtus[0] < 81) /* accommodate SACK */ 2847 return (EINVAL); 2848 2849 /* 2850 * MTUs must be in ascending order 2851 */ 2852 for (i = 1; i < NMTUS; ++i) 2853 if (m->mtus[i] < m->mtus[i - 1]) 2854 return (EINVAL); 2855 2856 memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus)); 2857 break; 2858 } 2859 case CHELSIO_GETMTUTAB: { 2860 struct ch_mtus *m = (struct ch_mtus *)data; 2861 2862 if (!is_offload(sc)) 2863 return (EOPNOTSUPP); 2864 2865 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); 2866 m->nmtus = NMTUS; 2867 break; 2868 } 2869 case CHELSIO_GET_MEM: { 2870 struct ch_mem_range *t = (struct ch_mem_range *)data; 2871 struct mc7 *mem; 2872 uint8_t *useraddr; 2873 u64 buf[32]; 2874 2875 /* 2876 * Use these to avoid modifying len/addr in the the return 2877 * struct 2878 */ 2879 uint32_t len = t->len, addr = t->addr; 2880 2881 if (!is_offload(sc)) 2882 return (EOPNOTSUPP); 2883 if (!(sc->flags & FULL_INIT_DONE)) 2884 return (EIO); /* need the memory controllers */ 2885 if ((addr & 0x7) || (len & 0x7)) 2886 return (EINVAL); 2887 if (t->mem_id == MEM_CM) 2888 mem = &sc->cm; 2889 else if (t->mem_id == MEM_PMRX) 2890 mem = &sc->pmrx; 2891 else if (t->mem_id == MEM_PMTX) 2892 mem = &sc->pmtx; 2893 else 2894 return (EINVAL); 2895 2896 /* 2897 * Version scheme: 2898 * bits 0..9: chip version 2899 * bits 10..15: chip revision 2900 */ 2901 t->version = 3 | (sc->params.rev << 10); 2902 2903 /* 2904 * Read 256 bytes at a time as len can be large and we don't 2905 * want to use huge intermediate buffers. 2906 */ 2907 useraddr = (uint8_t *)t->buf; 2908 while (len) { 2909 unsigned int chunk = min(len, sizeof(buf)); 2910 2911 error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf); 2912 if (error) 2913 return (-error); 2914 if (copyout(buf, useraddr, chunk)) 2915 return (EFAULT); 2916 useraddr += chunk; 2917 addr += chunk; 2918 len -= chunk; 2919 } 2920 break; 2921 } 2922 case CHELSIO_READ_TCAM_WORD: { 2923 struct ch_tcam_word *t = (struct ch_tcam_word *)data; 2924 2925 if (!is_offload(sc)) 2926 return (EOPNOTSUPP); 2927 if (!(sc->flags & FULL_INIT_DONE)) 2928 return (EIO); /* need MC5 */ 2929 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); 2930 break; 2931 } 2932 case CHELSIO_SET_TRACE_FILTER: { 2933 struct ch_trace *t = (struct ch_trace *)data; 2934 const struct trace_params *tp; 2935 2936 tp = (const struct trace_params *)&t->sip; 2937 if (t->config_tx) 2938 t3_config_trace_filter(sc, tp, 0, t->invert_match, 2939 t->trace_tx); 2940 if (t->config_rx) 2941 t3_config_trace_filter(sc, tp, 1, t->invert_match, 2942 t->trace_rx); 2943 break; 2944 } 2945 case CHELSIO_SET_PKTSCHED: { 2946 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; 2947 if (sc->open_device_map == 0) 2948 return (EAGAIN); 2949 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, 2950 p->binding); 2951 break; 2952 } 2953 case CHELSIO_IFCONF_GETREGS: { 2954 struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data; 2955 int reglen = cxgb_get_regs_len(); 2956 uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT); 2957 if (buf == NULL) { 2958 return (ENOMEM); 2959 } 2960 if (regs->len > reglen) 2961 regs->len = reglen; 2962 else if (regs->len < reglen) 2963 error = ENOBUFS; 2964 2965 if (!error) { 2966 cxgb_get_regs(sc, regs, buf); 2967 error = copyout(buf, regs->data, reglen); 2968 } 2969 free(buf, M_DEVBUF); 2970 2971 break; 2972 } 2973 case CHELSIO_SET_HW_SCHED: { 2974 struct ch_hw_sched *t = (struct ch_hw_sched *)data; 2975 unsigned int ticks_per_usec = core_ticks_per_usec(sc); 2976 2977 if ((sc->flags & FULL_INIT_DONE) == 0) 2978 return (EAGAIN); /* need TP to be initialized */ 2979 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || 2980 !in_range(t->channel, 0, 1) || 2981 !in_range(t->kbps, 0, 10000000) || 2982 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || 2983 !in_range(t->flow_ipg, 0, 2984 dack_ticks_to_usec(sc, 0x7ff))) 2985 return (EINVAL); 2986 2987 if (t->kbps >= 0) { 2988 error = t3_config_sched(sc, t->kbps, t->sched); 2989 if (error < 0) 2990 return (-error); 2991 } 2992 if (t->class_ipg >= 0) 2993 t3_set_sched_ipg(sc, t->sched, t->class_ipg); 2994 if (t->flow_ipg >= 0) { 2995 t->flow_ipg *= 1000; /* us -> ns */ 2996 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); 2997 } 2998 if (t->mode >= 0) { 2999 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); 3000 3001 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 3002 bit, t->mode ? bit : 0); 3003 } 3004 if (t->channel >= 0) 3005 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 3006 1 << t->sched, t->channel << t->sched); 3007 break; 3008 } 3009 case CHELSIO_GET_EEPROM: { 3010 int i; 3011 struct ch_eeprom *e = (struct ch_eeprom *)data; 3012 uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT); 3013 3014 if (buf == NULL) { 3015 return (ENOMEM); 3016 } 3017 e->magic = EEPROM_MAGIC; 3018 for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4) 3019 error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]); 3020 3021 if (!error) 3022 error = copyout(buf + e->offset, e->data, e->len); 3023 3024 free(buf, M_DEVBUF); 3025 break; 3026 } 3027 case CHELSIO_CLEAR_STATS: { 3028 if (!(sc->flags & FULL_INIT_DONE)) 3029 return EAGAIN; 3030 3031 PORT_LOCK(pi); 3032 t3_mac_update_stats(&pi->mac); 3033 memset(&pi->mac.stats, 0, sizeof(pi->mac.stats)); 3034 PORT_UNLOCK(pi); 3035 break; 3036 } 3037 case CHELSIO_GET_UP_LA: { 3038 struct ch_up_la *la = (struct ch_up_la *)data; 3039 uint8_t *buf = malloc(LA_BUFSIZE, M_DEVBUF, M_NOWAIT); 3040 if (buf == NULL) { 3041 return (ENOMEM); 3042 } 3043 if (la->bufsize < LA_BUFSIZE) 3044 error = ENOBUFS; 3045 3046 if (!error) 3047 error = -t3_get_up_la(sc, &la->stopped, &la->idx, 3048 &la->bufsize, buf); 3049 if (!error) 3050 error = copyout(buf, la->data, la->bufsize); 3051 3052 free(buf, M_DEVBUF); 3053 break; 3054 } 3055 case CHELSIO_GET_UP_IOQS: { 3056 struct ch_up_ioqs *ioqs = (struct ch_up_ioqs *)data; 3057 uint8_t *buf = malloc(IOQS_BUFSIZE, M_DEVBUF, M_NOWAIT); 3058 uint32_t *v; 3059 3060 if (buf == NULL) { 3061 return (ENOMEM); 3062 } 3063 if (ioqs->bufsize < IOQS_BUFSIZE) 3064 error = ENOBUFS; 3065 3066 if (!error) 3067 error = -t3_get_up_ioqs(sc, &ioqs->bufsize, buf); 3068 3069 if (!error) { 3070 v = (uint32_t *)buf; 3071 3072 ioqs->bufsize -= 4 * sizeof(uint32_t); 3073 ioqs->ioq_rx_enable = *v++; 3074 ioqs->ioq_tx_enable = *v++; 3075 ioqs->ioq_rx_status = *v++; 3076 ioqs->ioq_tx_status = *v++; 3077 3078 error = copyout(v, ioqs->data, ioqs->bufsize); 3079 } 3080 3081 free(buf, M_DEVBUF); 3082 break; 3083 } 3084 default: 3085 return (EOPNOTSUPP); 3086 break; 3087 } 3088 3089 return (error); 3090} 3091 3092static __inline void 3093reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 3094 unsigned int end) 3095{ 3096 uint32_t *p = (uint32_t *)(buf + start); 3097 3098 for ( ; start <= end; start += sizeof(uint32_t)) 3099 *p++ = t3_read_reg(ap, start); 3100} 3101 3102#define T3_REGMAP_SIZE (3 * 1024) 3103static int 3104cxgb_get_regs_len(void) 3105{ 3106 return T3_REGMAP_SIZE; 3107} 3108 3109static void 3110cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf) 3111{ 3112 3113 /* 3114 * Version scheme: 3115 * bits 0..9: chip version 3116 * bits 10..15: chip revision 3117 * bit 31: set for PCIe cards 3118 */ 3119 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); 3120 3121 /* 3122 * We skip the MAC statistics registers because they are clear-on-read. 3123 * Also reading multi-register stats would need to synchronize with the 3124 * periodic mac stats accumulation. Hard to justify the complexity. 3125 */ 3126 memset(buf, 0, cxgb_get_regs_len()); 3127 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); 3128 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); 3129 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); 3130 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); 3131 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); 3132 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, 3133 XGM_REG(A_XGM_SERDES_STAT3, 1)); 3134 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), 3135 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); 3136} 3137 3138 3139MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1); 3140