cxgb_t3_cpl.h revision 176472
1/************************************************************************** 2 3Copyright (c) 2007, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28$FreeBSD: head/sys/dev/cxgb/common/cxgb_t3_cpl.h 176472 2008-02-23 01:06:17Z kmacy $ 29 30***************************************************************************/ 31#ifndef T3_CPL_H 32#define T3_CPL_H 33 34enum CPL_opcode { 35 CPL_PASS_OPEN_REQ = 0x1, 36 CPL_PASS_ACCEPT_RPL = 0x2, 37 CPL_ACT_OPEN_REQ = 0x3, 38 CPL_SET_TCB = 0x4, 39 CPL_SET_TCB_FIELD = 0x5, 40 CPL_GET_TCB = 0x6, 41 CPL_PCMD = 0x7, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TX_PKT_LSO = 0x16, 57 CPL_PCMD_READ = 0x17, 58 CPL_BARRIER = 0x18, 59 CPL_TID_RELEASE = 0x1A, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PCMD_READ_RPL = 0x24, 66 CPL_PCMD_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_DDP_COMPLETE = 0x29, 71 CPL_RX_PHYS_ADDR = 0x2A, 72 CPL_RX_PKT = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_SET_TCB_RPL = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_ABORT_REQ_RSS = 0x30, 79 CPL_ABORT_RPL_RSS = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 89 CPL_ACT_OPEN_RPL = 0x40, 90 CPL_PASS_OPEN_RPL = 0x41, 91 CPL_RX_DATA_DDP = 0x42, 92 CPL_SMT_READ_RPL = 0x43, 93 94 CPL_ACT_ESTABLISH = 0x50, 95 CPL_PASS_ESTABLISH = 0x51, 96 97 CPL_PASS_ACCEPT_REQ = 0x70, 98 99 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ 100 101 CPL_TX_DMA_ACK = 0xA0, 102 CPL_RDMA_READ_REQ = 0xA1, 103 CPL_RDMA_TERMINATE = 0xA2, 104 CPL_TRACE_PKT = 0xA3, 105 CPL_RDMA_EC_STATUS = 0xA5, 106 107 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 108}; 109 110enum CPL_error { 111 CPL_ERR_NONE = 0, 112 CPL_ERR_TCAM_PARITY = 1, 113 CPL_ERR_TCAM_FULL = 3, 114 CPL_ERR_CONN_RESET = 20, 115 CPL_ERR_CONN_EXIST = 22, 116 CPL_ERR_ARP_MISS = 23, 117 CPL_ERR_BAD_SYN = 24, 118 CPL_ERR_CONN_TIMEDOUT = 30, 119 CPL_ERR_XMIT_TIMEDOUT = 31, 120 CPL_ERR_PERSIST_TIMEDOUT = 32, 121 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 122 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 123 CPL_ERR_RTX_NEG_ADVICE = 35, 124 CPL_ERR_PERSIST_NEG_ADVICE = 36, 125 CPL_ERR_ABORT_FAILED = 42, 126 CPL_ERR_GENERAL = 99 127}; 128 129enum { 130 CPL_CONN_POLICY_AUTO = 0, 131 CPL_CONN_POLICY_ASK = 1, 132 CPL_CONN_POLICY_FILTER = 2, 133 CPL_CONN_POLICY_DENY = 3 134}; 135 136enum { 137 ULP_MODE_NONE = 0, 138 ULP_MODE_TCP_DDP = 1, 139 ULP_MODE_ISCSI = 2, 140 ULP_MODE_RDMA = 4, 141 ULP_MODE_TCPDDP = 5 142}; 143 144enum { 145 ULP_CRC_HEADER = 1 << 0, 146 ULP_CRC_DATA = 1 << 1 147}; 148 149enum { 150 CPL_PASS_OPEN_ACCEPT, 151 CPL_PASS_OPEN_REJECT 152}; 153 154enum { 155 CPL_ABORT_SEND_RST = 0, 156 CPL_ABORT_NO_RST, 157 CPL_ABORT_POST_CLOSE_REQ = 2 158}; 159 160enum { /* TX_PKT_LSO ethernet types */ 161 CPL_ETH_II, 162 CPL_ETH_II_VLAN, 163 CPL_ETH_802_3, 164 CPL_ETH_802_3_VLAN 165}; 166 167enum { /* TCP congestion control algorithms */ 168 CONG_ALG_RENO, 169 CONG_ALG_TAHOE, 170 CONG_ALG_NEWRENO, 171 CONG_ALG_HIGHSPEED 172}; 173 174enum { /* RSS hash type */ 175 RSS_HASH_NONE = 0, 176 RSS_HASH_2_TUPLE = 1, 177 RSS_HASH_4_TUPLE = 2, 178 RSS_HASH_TCPV6 = 3 179}; 180 181union opcode_tid { 182 __be32 opcode_tid; 183 __u8 opcode; 184}; 185 186#define S_OPCODE 24 187#define V_OPCODE(x) ((x) << S_OPCODE) 188#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 189#define G_TID(x) ((x) & 0xFFFFFF) 190 191#define S_HASHTYPE 22 192#define M_HASHTYPE 0x3 193#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 194 195#define S_QNUM 0 196#define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF) 197 198/* tid is assumed to be 24-bits */ 199#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 200 201#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 202 203/* extract the TID from a CPL command */ 204#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 205 206struct tcp_options { 207 __be16 mss; 208 __u8 wsf; 209#if defined(__LITTLE_ENDIAN_BITFIELD) 210 __u8 :5; 211 __u8 ecn:1; 212 __u8 sack:1; 213 __u8 tstamp:1; 214#else 215 __u8 tstamp:1; 216 __u8 sack:1; 217 __u8 ecn:1; 218 __u8 :5; 219#endif 220}; 221 222struct rss_header { 223 __u8 opcode; 224#if defined(__LITTLE_ENDIAN_BITFIELD) 225 __u8 cpu_idx:6; 226 __u8 hash_type:2; 227#else 228 __u8 hash_type:2; 229 __u8 cpu_idx:6; 230#endif 231 __be16 cq_idx; 232 __be32 rss_hash_val; 233}; 234 235#ifndef CHELSIO_FW 236struct work_request_hdr { 237 __be32 wr_hi; 238 __be32 wr_lo; 239}; 240 241/* wr_hi fields */ 242#define S_WR_SGE_CREDITS 0 243#define M_WR_SGE_CREDITS 0xFF 244#define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) 245#define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) 246 247#define S_WR_SGLSFLT 8 248#define M_WR_SGLSFLT 0xFF 249#define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) 250#define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) 251 252#define S_WR_BCNTLFLT 16 253#define M_WR_BCNTLFLT 0xF 254#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) 255#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) 256 257/* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before 258 * and after the BYPASS WR if the ATOMIC bit is set. 259 */ 260#define S_WR_ATOMIC 16 261#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) 262#define F_WR_ATOMIC V_WR_ATOMIC(1U) 263 264/* Applicable to BYPASS WRs only: the uP will flush buffered non abort 265 * related WRs. 266 */ 267#define S_WR_FLUSH 17 268#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) 269#define F_WR_FLUSH V_WR_FLUSH(1U) 270 271#define S_WR_DATATYPE 20 272#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) 273#define F_WR_DATATYPE V_WR_DATATYPE(1U) 274 275#define S_WR_COMPL 21 276#define V_WR_COMPL(x) ((x) << S_WR_COMPL) 277#define F_WR_COMPL V_WR_COMPL(1U) 278 279#define S_WR_EOP 22 280#define V_WR_EOP(x) ((x) << S_WR_EOP) 281#define F_WR_EOP V_WR_EOP(1U) 282 283#define S_WR_SOP 23 284#define V_WR_SOP(x) ((x) << S_WR_SOP) 285#define F_WR_SOP V_WR_SOP(1U) 286 287#define S_WR_OP 24 288#define M_WR_OP 0xFF 289#define V_WR_OP(x) ((x) << S_WR_OP) 290#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 291 292/* wr_lo fields */ 293#define S_WR_LEN 0 294#define M_WR_LEN 0xFF 295#define V_WR_LEN(x) ((x) << S_WR_LEN) 296#define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) 297 298#define S_WR_TID 8 299#define M_WR_TID 0xFFFFF 300#define V_WR_TID(x) ((x) << S_WR_TID) 301#define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) 302 303#define S_WR_CR_FLUSH 30 304#define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH) 305#define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U) 306 307#define S_WR_GEN 31 308#define V_WR_GEN(x) ((x) << S_WR_GEN) 309#define F_WR_GEN V_WR_GEN(1U) 310#define G_WR_GEN(x) ((x) >> S_WR_GEN) 311 312# define WR_HDR struct work_request_hdr wr 313# define RSS_HDR 314#else 315# define WR_HDR 316# define RSS_HDR struct rss_header rss_hdr; 317#endif 318 319/* option 0 lower-half fields */ 320#define S_CPL_STATUS 0 321#define M_CPL_STATUS 0xFF 322#define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) 323#define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) 324 325#define S_INJECT_TIMER 6 326#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 327#define F_INJECT_TIMER V_INJECT_TIMER(1U) 328 329#define S_NO_OFFLOAD 7 330#define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD) 331#define F_NO_OFFLOAD V_NO_OFFLOAD(1U) 332 333#define S_ULP_MODE 8 334#define M_ULP_MODE 0xF 335#define V_ULP_MODE(x) ((x) << S_ULP_MODE) 336#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 337 338#define S_RCV_BUFSIZ 12 339#define M_RCV_BUFSIZ 0x3FFF 340#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 341#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 342 343#define S_TOS 26 344#define M_TOS 0x3F 345#define V_TOS(x) ((x) << S_TOS) 346#define G_TOS(x) (((x) >> S_TOS) & M_TOS) 347 348/* option 0 upper-half fields */ 349#define S_DELACK 0 350#define V_DELACK(x) ((x) << S_DELACK) 351#define F_DELACK V_DELACK(1U) 352 353#define S_NO_CONG 1 354#define V_NO_CONG(x) ((x) << S_NO_CONG) 355#define F_NO_CONG V_NO_CONG(1U) 356 357#define S_SRC_MAC_SEL 2 358#define M_SRC_MAC_SEL 0x3 359#define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) 360#define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) 361 362#define S_L2T_IDX 4 363#define M_L2T_IDX 0x7FF 364#define V_L2T_IDX(x) ((x) << S_L2T_IDX) 365#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 366 367#define S_TX_CHANNEL 15 368#define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL) 369#define F_TX_CHANNEL V_TX_CHANNEL(1U) 370 371#define S_TCAM_BYPASS 16 372#define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS) 373#define F_TCAM_BYPASS V_TCAM_BYPASS(1U) 374 375#define S_NAGLE 17 376#define V_NAGLE(x) ((x) << S_NAGLE) 377#define F_NAGLE V_NAGLE(1U) 378 379#define S_WND_SCALE 18 380#define M_WND_SCALE 0xF 381#define V_WND_SCALE(x) ((x) << S_WND_SCALE) 382#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 383 384#define S_KEEP_ALIVE 22 385#define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE) 386#define F_KEEP_ALIVE V_KEEP_ALIVE(1U) 387 388#define S_MAX_RETRANS 23 389#define M_MAX_RETRANS 0xF 390#define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) 391#define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) 392 393#define S_MAX_RETRANS_OVERRIDE 27 394#define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE) 395#define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U) 396 397#define S_MSS_IDX 28 398#define M_MSS_IDX 0xF 399#define V_MSS_IDX(x) ((x) << S_MSS_IDX) 400#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 401 402/* option 1 fields */ 403#define S_RSS_ENABLE 0 404#define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE) 405#define F_RSS_ENABLE V_RSS_ENABLE(1U) 406 407#define S_RSS_MASK_LEN 1 408#define M_RSS_MASK_LEN 0x7 409#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) 410#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) 411 412#define S_CPU_IDX 4 413#define M_CPU_IDX 0x3F 414#define V_CPU_IDX(x) ((x) << S_CPU_IDX) 415#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) 416 417#define S_OPT1_VLAN 6 418#define M_OPT1_VLAN 0xFFF 419#define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN) 420#define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN) 421 422#define S_MAC_MATCH_VALID 18 423#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) 424#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) 425 426#define S_CONN_POLICY 19 427#define M_CONN_POLICY 0x3 428#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 429#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 430 431#define S_SYN_DEFENSE 21 432#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 433#define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 434 435#define S_VLAN_PRI 22 436#define M_VLAN_PRI 0x3 437#define V_VLAN_PRI(x) ((x) << S_VLAN_PRI) 438#define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) 439 440#define S_VLAN_PRI_VALID 24 441#define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID) 442#define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U) 443 444#define S_PKT_TYPE 25 445#define M_PKT_TYPE 0x3 446#define V_PKT_TYPE(x) ((x) << S_PKT_TYPE) 447#define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) 448 449#define S_MAC_MATCH 27 450#define M_MAC_MATCH 0x1F 451#define V_MAC_MATCH(x) ((x) << S_MAC_MATCH) 452#define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) 453 454/* option 2 fields */ 455#define S_CPU_INDEX 0 456#define M_CPU_INDEX 0x7F 457#define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) 458#define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) 459 460#define S_CPU_INDEX_VALID 7 461#define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID) 462#define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U) 463 464#define S_RX_COALESCE 8 465#define M_RX_COALESCE 0x3 466#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 467#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 468 469#define S_RX_COALESCE_VALID 10 470#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 471#define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 472 473#define S_CONG_CONTROL_FLAVOR 11 474#define M_CONG_CONTROL_FLAVOR 0x3 475#define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) 476#define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) 477 478#define S_PACING_FLAVOR 13 479#define M_PACING_FLAVOR 0x3 480#define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) 481#define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) 482 483#define S_FLAVORS_VALID 15 484#define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID) 485#define F_FLAVORS_VALID V_FLAVORS_VALID(1U) 486 487#define S_RX_FC_DISABLE 16 488#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 489#define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 490 491#define S_RX_FC_VALID 17 492#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 493#define F_RX_FC_VALID V_RX_FC_VALID(1U) 494 495struct cpl_pass_open_req { 496 WR_HDR; 497 union opcode_tid ot; 498 __be16 local_port; 499 __be16 peer_port; 500 __be32 local_ip; 501 __be32 peer_ip; 502 __be32 opt0h; 503 __be32 opt0l; 504 __be32 peer_netmask; 505 __be32 opt1; 506}; 507 508struct cpl_pass_open_rpl { 509 RSS_HDR 510 union opcode_tid ot; 511 __be16 local_port; 512 __be16 peer_port; 513 __be32 local_ip; 514 __be32 peer_ip; 515 __u8 resvd[7]; 516 __u8 status; 517}; 518 519struct cpl_pass_establish { 520 RSS_HDR 521 union opcode_tid ot; 522 __be16 local_port; 523 __be16 peer_port; 524 __be32 local_ip; 525 __be32 peer_ip; 526 __be32 tos_tid; 527 __be16 l2t_idx; 528 __be16 tcp_opt; 529 __be32 snd_isn; 530 __be32 rcv_isn; 531}; 532 533/* cpl_pass_establish.tos_tid fields */ 534#define S_PASS_OPEN_TID 0 535#define M_PASS_OPEN_TID 0xFFFFFF 536#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 537#define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 538 539#define S_PASS_OPEN_TOS 24 540#define M_PASS_OPEN_TOS 0xFF 541#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 542#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 543 544/* cpl_pass_establish.l2t_idx fields */ 545#define S_L2T_IDX16 5 546#define M_L2T_IDX16 0x7FF 547#define V_L2T_IDX16(x) ((x) << S_L2T_IDX16) 548#define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16) 549 550/* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */ 551#define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 552#define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 553#define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 554#define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 555#define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 556 557struct cpl_pass_accept_req { 558 RSS_HDR 559 union opcode_tid ot; 560 __be16 local_port; 561 __be16 peer_port; 562 __be32 local_ip; 563 __be32 peer_ip; 564 __be32 tos_tid; 565 struct tcp_options tcp_options; 566 __u8 dst_mac[6]; 567 __be16 vlan_tag; 568 __u8 src_mac[6]; 569#if defined(__LITTLE_ENDIAN_BITFIELD) 570 __u8 :3; 571 __u8 addr_idx:3; 572 __u8 port_idx:1; 573 __u8 exact_match:1; 574#else 575 __u8 exact_match:1; 576 __u8 port_idx:1; 577 __u8 addr_idx:3; 578 __u8 :3; 579#endif 580 __u8 rsvd; 581 __be32 rcv_isn; 582 __be32 rsvd2; 583}; 584 585struct cpl_pass_accept_rpl { 586 WR_HDR; 587 union opcode_tid ot; 588 __be32 opt2; 589 __be32 rsvd; 590 __be32 peer_ip; 591 __be32 opt0h; 592 __be32 opt0l_status; 593}; 594 595struct cpl_act_open_req { 596 WR_HDR; 597 union opcode_tid ot; 598 __be16 local_port; 599 __be16 peer_port; 600 __be32 local_ip; 601 __be32 peer_ip; 602 __be32 opt0h; 603 __be32 opt0l; 604 __be32 params; 605 __be32 opt2; 606}; 607 608/* cpl_act_open_req.params fields */ 609#define S_AOPEN_VLAN_PRI 9 610#define M_AOPEN_VLAN_PRI 0x3 611#define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 612#define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 613 614#define S_AOPEN_VLAN_PRI_VALID 11 615#define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 616#define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 617 618#define S_AOPEN_PKT_TYPE 12 619#define M_AOPEN_PKT_TYPE 0x3 620#define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 621#define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 622 623#define S_AOPEN_MAC_MATCH 14 624#define M_AOPEN_MAC_MATCH 0x1F 625#define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 626#define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 627 628#define S_AOPEN_MAC_MATCH_VALID 19 629#define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 630#define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 631 632#define S_AOPEN_IFF_VLAN 20 633#define M_AOPEN_IFF_VLAN 0xFFF 634#define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 635#define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 636 637struct cpl_act_open_rpl { 638 RSS_HDR 639 union opcode_tid ot; 640 __be16 local_port; 641 __be16 peer_port; 642 __be32 local_ip; 643 __be32 peer_ip; 644 __be32 atid; 645 __u8 rsvd[3]; 646 __u8 status; 647}; 648 649struct cpl_act_establish { 650 RSS_HDR 651 union opcode_tid ot; 652 __be16 local_port; 653 __be16 peer_port; 654 __be32 local_ip; 655 __be32 peer_ip; 656 __be32 tos_tid; 657 __be16 l2t_idx; 658 __be16 tcp_opt; 659 __be32 snd_isn; 660 __be32 rcv_isn; 661}; 662 663struct cpl_get_tcb { 664 WR_HDR; 665 union opcode_tid ot; 666 __be16 cpuno; 667 __be16 rsvd; 668}; 669 670struct cpl_get_tcb_rpl { 671 RSS_HDR 672 union opcode_tid ot; 673 __u8 rsvd; 674 __u8 status; 675 __be16 len; 676}; 677 678struct cpl_set_tcb { 679 WR_HDR; 680 union opcode_tid ot; 681 __u8 reply; 682 __u8 cpu_idx; 683 __be16 len; 684}; 685 686/* cpl_set_tcb.reply fields */ 687#define S_NO_REPLY 7 688#define V_NO_REPLY(x) ((x) << S_NO_REPLY) 689#define F_NO_REPLY V_NO_REPLY(1U) 690 691struct cpl_set_tcb_field { 692 WR_HDR; 693 union opcode_tid ot; 694 __u8 reply; 695 __u8 cpu_idx; 696 __be16 word; 697 __be64 mask; 698 __be64 val; 699}; 700 701struct cpl_set_tcb_rpl { 702 RSS_HDR 703 union opcode_tid ot; 704 __u8 rsvd[3]; 705 __u8 status; 706}; 707 708struct cpl_pcmd { 709 WR_HDR; 710 union opcode_tid ot; 711 __u8 rsvd[3]; 712#if defined(__LITTLE_ENDIAN_BITFIELD) 713 __u8 src:1; 714 __u8 bundle:1; 715 __u8 channel:1; 716 __u8 :5; 717#else 718 __u8 :5; 719 __u8 channel:1; 720 __u8 bundle:1; 721 __u8 src:1; 722#endif 723 __be32 pcmd_parm[2]; 724}; 725 726struct cpl_pcmd_reply { 727 RSS_HDR 728 union opcode_tid ot; 729 __u8 status; 730 __u8 rsvd; 731 __be16 len; 732}; 733 734struct cpl_close_con_req { 735 WR_HDR; 736 union opcode_tid ot; 737 __be32 rsvd; 738}; 739 740struct cpl_close_con_rpl { 741 RSS_HDR 742 union opcode_tid ot; 743 __u8 rsvd[3]; 744 __u8 status; 745 __be32 snd_nxt; 746 __be32 rcv_nxt; 747}; 748 749struct cpl_close_listserv_req { 750 WR_HDR; 751 union opcode_tid ot; 752 __u8 rsvd0; 753 __u8 cpu_idx; 754 __be16 rsvd1; 755}; 756 757struct cpl_close_listserv_rpl { 758 RSS_HDR 759 union opcode_tid ot; 760 __u8 rsvd[3]; 761 __u8 status; 762}; 763 764struct cpl_abort_req_rss { 765 RSS_HDR 766 union opcode_tid ot; 767 __be32 rsvd0; 768 __u8 rsvd1; 769 __u8 status; 770 __u8 rsvd2[6]; 771}; 772 773struct cpl_abort_req { 774 WR_HDR; 775 union opcode_tid ot; 776 __be32 rsvd0; 777 __u8 rsvd1; 778 __u8 cmd; 779 __u8 rsvd2[6]; 780}; 781 782struct cpl_abort_rpl_rss { 783 RSS_HDR 784 union opcode_tid ot; 785 __be32 rsvd0; 786 __u8 rsvd1; 787 __u8 status; 788 __u8 rsvd2[6]; 789}; 790 791struct cpl_abort_rpl { 792 WR_HDR; 793 union opcode_tid ot; 794 __be32 rsvd0; 795 __u8 rsvd1; 796 __u8 cmd; 797 __u8 rsvd2[6]; 798}; 799 800struct cpl_peer_close { 801 RSS_HDR 802 union opcode_tid ot; 803 __be32 rcv_nxt; 804}; 805 806struct tx_data_wr { 807 __be32 wr_hi; 808 __be32 wr_lo; 809 __be32 len; 810 __be32 flags; 811 __be32 sndseq; 812 __be32 param; 813}; 814 815/* tx_data_wr.flags fields */ 816#define S_TX_ACK_PAGES 21 817#define M_TX_ACK_PAGES 0x7 818#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 819#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 820 821/* tx_data_wr.param fields */ 822#define S_TX_PORT 0 823#define M_TX_PORT 0x7 824#define V_TX_PORT(x) ((x) << S_TX_PORT) 825#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 826 827#define S_TX_MSS 4 828#define M_TX_MSS 0xF 829#define V_TX_MSS(x) ((x) << S_TX_MSS) 830#define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 831 832#define S_TX_QOS 8 833#define M_TX_QOS 0xFF 834#define V_TX_QOS(x) ((x) << S_TX_QOS) 835#define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 836 837#define S_TX_SNDBUF 16 838#define M_TX_SNDBUF 0xFFFF 839#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 840#define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 841 842struct cpl_tx_data { 843 union opcode_tid ot; 844 __be32 len; 845 __be32 rsvd; 846 __be16 urg; 847 __be16 flags; 848}; 849 850/* cpl_tx_data.flags fields */ 851#define S_TX_ULP_SUBMODE 6 852#define M_TX_ULP_SUBMODE 0xF 853#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 854#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 855 856#define S_TX_ULP_MODE 10 857#define M_TX_ULP_MODE 0xF 858#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 859#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 860 861#define S_TX_SHOVE 14 862#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 863#define F_TX_SHOVE V_TX_SHOVE(1U) 864 865#define S_TX_MORE 15 866#define V_TX_MORE(x) ((x) << S_TX_MORE) 867#define F_TX_MORE V_TX_MORE(1U) 868 869/* additional tx_data_wr.flags fields */ 870#define S_TX_CPU_IDX 0 871#define M_TX_CPU_IDX 0x3F 872#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 873#define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 874 875#define S_TX_URG 16 876#define V_TX_URG(x) ((x) << S_TX_URG) 877#define F_TX_URG V_TX_URG(1U) 878 879#define S_TX_CLOSE 17 880#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 881#define F_TX_CLOSE V_TX_CLOSE(1U) 882 883#define S_TX_INIT 18 884#define V_TX_INIT(x) ((x) << S_TX_INIT) 885#define F_TX_INIT V_TX_INIT(1U) 886 887#define S_TX_IMM_ACK 19 888#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 889#define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 890 891#define S_TX_IMM_DMA 20 892#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 893#define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 894 895struct cpl_tx_data_ack { 896 RSS_HDR 897 union opcode_tid ot; 898 __be32 ack_seq; 899}; 900 901struct cpl_wr_ack { 902 RSS_HDR 903 union opcode_tid ot; 904 __be16 credits; 905 __be16 rsvd; 906 __be32 snd_nxt; 907 __be32 snd_una; 908}; 909 910struct cpl_rdma_ec_status { 911 RSS_HDR 912 union opcode_tid ot; 913 __u8 rsvd[3]; 914 __u8 status; 915}; 916 917struct mngt_pktsched_wr { 918 __be32 wr_hi; 919 __be32 wr_lo; 920 __u8 mngt_opcode; 921 __u8 rsvd[7]; 922 __u8 sched; 923 __u8 idx; 924 __u8 min; 925 __u8 max; 926 __u8 binding; 927 __u8 rsvd1[3]; 928}; 929 930struct cpl_iscsi_hdr { 931 RSS_HDR 932 union opcode_tid ot; 933 __be16 pdu_len_ddp; 934 __be16 len; 935 __be32 seq; 936 __be16 urg; 937 __u8 rsvd; 938 __u8 status; 939}; 940 941/* cpl_iscsi_hdr.pdu_len_ddp fields */ 942#define S_ISCSI_PDU_LEN 0 943#define M_ISCSI_PDU_LEN 0x7FFF 944#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 945#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 946 947#define S_ISCSI_DDP 15 948#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 949#define F_ISCSI_DDP V_ISCSI_DDP(1U) 950 951struct cpl_rx_data { 952 RSS_HDR 953 union opcode_tid ot; 954 __be16 rsvd; 955 __be16 len; 956 __be32 seq; 957 __be16 urg; 958#if defined(__LITTLE_ENDIAN_BITFIELD) 959 __u8 dack_mode:2; 960 __u8 psh:1; 961 __u8 heartbeat:1; 962 __u8 :4; 963#else 964 __u8 :4; 965 __u8 heartbeat:1; 966 __u8 psh:1; 967 __u8 dack_mode:2; 968#endif 969 __u8 status; 970}; 971 972struct cpl_rx_data_ack { 973 WR_HDR; 974 union opcode_tid ot; 975 __be32 credit_dack; 976}; 977 978/* cpl_rx_data_ack.ack_seq fields */ 979#define S_RX_CREDITS 0 980#define M_RX_CREDITS 0x7FFFFFF 981#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 982#define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 983 984#define S_RX_MODULATE 27 985#define V_RX_MODULATE(x) ((x) << S_RX_MODULATE) 986#define F_RX_MODULATE V_RX_MODULATE(1U) 987 988#define S_RX_FORCE_ACK 28 989#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 990#define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 991 992#define S_RX_DACK_MODE 29 993#define M_RX_DACK_MODE 0x3 994#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 995#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 996 997#define S_RX_DACK_CHANGE 31 998#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 999#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1000 1001struct cpl_rx_urg_notify { 1002 RSS_HDR 1003 union opcode_tid ot; 1004 __be32 seq; 1005}; 1006 1007struct cpl_rx_ddp_complete { 1008 RSS_HDR 1009 union opcode_tid ot; 1010 __be32 ddp_report; 1011}; 1012 1013struct cpl_rx_data_ddp { 1014 RSS_HDR 1015 union opcode_tid ot; 1016 __be16 urg; 1017 __be16 len; 1018 __be32 seq; 1019 union { 1020 __be32 nxt_seq; 1021 __be32 ddp_report; 1022 } u; 1023 __be32 ulp_crc; 1024 __be32 ddpvld_status; 1025}; 1026 1027/* cpl_rx_data_ddp.ddpvld_status fields */ 1028#define S_DDP_STATUS 0 1029#define M_DDP_STATUS 0xFF 1030#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) 1031#define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) 1032 1033#define S_DDP_VALID 15 1034#define M_DDP_VALID 0x1FFFF 1035#define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1036#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1037 1038#define S_DDP_PPOD_MISMATCH 15 1039#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1040#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1041 1042#define S_DDP_PDU 16 1043#define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1044#define F_DDP_PDU V_DDP_PDU(1U) 1045 1046#define S_DDP_LLIMIT_ERR 17 1047#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1048#define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1049 1050#define S_DDP_PPOD_PARITY_ERR 18 1051#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1052#define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1053 1054#define S_DDP_PADDING_ERR 19 1055#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1056#define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1057 1058#define S_DDP_HDRCRC_ERR 20 1059#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1060#define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1061 1062#define S_DDP_DATACRC_ERR 21 1063#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1064#define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1065 1066#define S_DDP_INVALID_TAG 22 1067#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1068#define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1069 1070#define S_DDP_ULIMIT_ERR 23 1071#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1072#define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1073 1074#define S_DDP_OFFSET_ERR 24 1075#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1076#define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1077 1078#define S_DDP_COLOR_ERR 25 1079#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1080#define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1081 1082#define S_DDP_TID_MISMATCH 26 1083#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1084#define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1085 1086#define S_DDP_INVALID_PPOD 27 1087#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1088#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1089 1090#define S_DDP_ULP_MODE 28 1091#define M_DDP_ULP_MODE 0xF 1092#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1093#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1094 1095/* cpl_rx_data_ddp.ddp_report fields */ 1096#define S_DDP_OFFSET 0 1097#define M_DDP_OFFSET 0x3FFFFF 1098#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1099#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1100 1101#define S_DDP_DACK_MODE 22 1102#define M_DDP_DACK_MODE 0x3 1103#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1104#define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1105 1106#define S_DDP_URG 24 1107#define V_DDP_URG(x) ((x) << S_DDP_URG) 1108#define F_DDP_URG V_DDP_URG(1U) 1109 1110#define S_DDP_PSH 25 1111#define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1112#define F_DDP_PSH V_DDP_PSH(1U) 1113 1114#define S_DDP_BUF_COMPLETE 26 1115#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1116#define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1117 1118#define S_DDP_BUF_TIMED_OUT 27 1119#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1120#define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1121 1122#define S_DDP_BUF_IDX 28 1123#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1124#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1125 1126struct cpl_tx_pkt { 1127 WR_HDR; 1128 __be32 cntrl; 1129 __be32 len; 1130}; 1131 1132struct cpl_tx_pkt_lso { 1133 WR_HDR; 1134 __be32 cntrl; 1135 __be32 len; 1136 1137 __be32 rsvd; 1138 __be32 lso_info; 1139}; 1140 1141struct cpl_tx_pkt_batch_entry { 1142 __be32 cntrl; 1143 __be32 len; 1144 __be64 addr; 1145}; 1146 1147struct cpl_tx_pkt_batch { 1148 WR_HDR; 1149 struct cpl_tx_pkt_batch_entry pkt_entry[7]; 1150}; 1151 1152 1153/* cpl_tx_pkt*.cntrl fields */ 1154#define S_TXPKT_VLAN 0 1155#define M_TXPKT_VLAN 0xFFFF 1156#define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN) 1157#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1158 1159#define S_TXPKT_INTF 16 1160#define M_TXPKT_INTF 0xF 1161#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1162#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1163 1164#define S_TXPKT_IPCSUM_DIS 20 1165#define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS) 1166#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U) 1167 1168#define S_TXPKT_L4CSUM_DIS 21 1169#define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS) 1170#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U) 1171 1172#define S_TXPKT_VLAN_VLD 22 1173#define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD) 1174#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U) 1175 1176#define S_TXPKT_LOOPBACK 23 1177#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1178#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1179 1180#define S_TXPKT_OPCODE 24 1181#define M_TXPKT_OPCODE 0xFF 1182#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1183#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1184 1185/* cpl_tx_pkt_lso.lso_info fields */ 1186#define S_LSO_MSS 0 1187#define M_LSO_MSS 0x3FFF 1188#define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1189#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1190 1191#define S_LSO_ETH_TYPE 14 1192#define M_LSO_ETH_TYPE 0x3 1193#define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE) 1194#define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) 1195 1196#define S_LSO_TCPHDR_WORDS 16 1197#define M_LSO_TCPHDR_WORDS 0xF 1198#define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS) 1199#define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) 1200 1201#define S_LSO_IPHDR_WORDS 20 1202#define M_LSO_IPHDR_WORDS 0xF 1203#define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS) 1204#define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) 1205 1206#define S_LSO_IPV6 24 1207#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1208#define F_LSO_IPV6 V_LSO_IPV6(1U) 1209 1210struct cpl_trace_pkt { 1211#ifdef CHELSIO_FW 1212 __u8 rss_opcode; 1213#if defined(__LITTLE_ENDIAN_BITFIELD) 1214 __u8 err:1; 1215 __u8 :7; 1216#else 1217 __u8 :7; 1218 __u8 err:1; 1219#endif 1220 __u8 rsvd0; 1221#if defined(__LITTLE_ENDIAN_BITFIELD) 1222 __u8 qid:4; 1223 __u8 :4; 1224#else 1225 __u8 :4; 1226 __u8 qid:4; 1227#endif 1228 __be32 tstamp; 1229#endif /* CHELSIO_FW */ 1230 1231 __u8 opcode; 1232#if defined(__LITTLE_ENDIAN_BITFIELD) 1233 __u8 iff:4; 1234 __u8 :4; 1235#else 1236 __u8 :4; 1237 __u8 iff:4; 1238#endif 1239 __u8 rsvd[4]; 1240 __be16 len; 1241}; 1242 1243struct cpl_rx_pkt { 1244 RSS_HDR 1245 __u8 opcode; 1246#if defined(__LITTLE_ENDIAN_BITFIELD) 1247 __u8 iff:4; 1248 __u8 csum_valid:1; 1249 __u8 ipmi_pkt:1; 1250 __u8 vlan_valid:1; 1251 __u8 fragment:1; 1252#else 1253 __u8 fragment:1; 1254 __u8 vlan_valid:1; 1255 __u8 ipmi_pkt:1; 1256 __u8 csum_valid:1; 1257 __u8 iff:4; 1258#endif 1259 __be16 csum; 1260 __be16 vlan; 1261 __be16 len; 1262}; 1263 1264struct cpl_l2t_write_req { 1265 WR_HDR; 1266 union opcode_tid ot; 1267 __be32 params; 1268 __u8 rsvd[2]; 1269 __u8 dst_mac[6]; 1270}; 1271 1272/* cpl_l2t_write_req.params fields */ 1273#define S_L2T_W_IDX 0 1274#define M_L2T_W_IDX 0x7FF 1275#define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX) 1276#define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX) 1277 1278#define S_L2T_W_VLAN 11 1279#define M_L2T_W_VLAN 0xFFF 1280#define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN) 1281#define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN) 1282 1283#define S_L2T_W_IFF 23 1284#define M_L2T_W_IFF 0xF 1285#define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF) 1286#define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF) 1287 1288#define S_L2T_W_PRIO 27 1289#define M_L2T_W_PRIO 0x7 1290#define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO) 1291#define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) 1292 1293struct cpl_l2t_write_rpl { 1294 RSS_HDR 1295 union opcode_tid ot; 1296 __u8 status; 1297 __u8 rsvd[3]; 1298}; 1299 1300struct cpl_l2t_read_req { 1301 WR_HDR; 1302 union opcode_tid ot; 1303 __be16 rsvd; 1304 __be16 l2t_idx; 1305}; 1306 1307struct cpl_l2t_read_rpl { 1308 RSS_HDR 1309 union opcode_tid ot; 1310 __be32 params; 1311 __u8 rsvd[2]; 1312 __u8 dst_mac[6]; 1313}; 1314 1315/* cpl_l2t_read_rpl.params fields */ 1316#define S_L2T_R_PRIO 0 1317#define M_L2T_R_PRIO 0x7 1318#define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO) 1319#define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO) 1320 1321#define S_L2T_R_VLAN 8 1322#define M_L2T_R_VLAN 0xFFF 1323#define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN) 1324#define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN) 1325 1326#define S_L2T_R_IFF 20 1327#define M_L2T_R_IFF 0xF 1328#define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF) 1329#define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF) 1330 1331#define S_L2T_STATUS 24 1332#define M_L2T_STATUS 0xFF 1333#define V_L2T_STATUS(x) ((x) << S_L2T_STATUS) 1334#define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS) 1335 1336struct cpl_smt_write_req { 1337 WR_HDR; 1338 union opcode_tid ot; 1339 __u8 rsvd0; 1340#if defined(__LITTLE_ENDIAN_BITFIELD) 1341 __u8 mtu_idx:4; 1342 __u8 iff:4; 1343#else 1344 __u8 iff:4; 1345 __u8 mtu_idx:4; 1346#endif 1347 __be16 rsvd2; 1348 __be16 rsvd3; 1349 __u8 src_mac1[6]; 1350 __be16 rsvd4; 1351 __u8 src_mac0[6]; 1352}; 1353 1354struct cpl_smt_write_rpl { 1355 RSS_HDR 1356 union opcode_tid ot; 1357 __u8 status; 1358 __u8 rsvd[3]; 1359}; 1360 1361struct cpl_smt_read_req { 1362 WR_HDR; 1363 union opcode_tid ot; 1364 __u8 rsvd0; 1365#if defined(__LITTLE_ENDIAN_BITFIELD) 1366 __u8 :4; 1367 __u8 iff:4; 1368#else 1369 __u8 iff:4; 1370 __u8 :4; 1371#endif 1372 __be16 rsvd2; 1373}; 1374 1375struct cpl_smt_read_rpl { 1376 RSS_HDR 1377 union opcode_tid ot; 1378 __u8 status; 1379#if defined(__LITTLE_ENDIAN_BITFIELD) 1380 __u8 mtu_idx:4; 1381 __u8 :4; 1382#else 1383 __u8 :4; 1384 __u8 mtu_idx:4; 1385#endif 1386 __be16 rsvd2; 1387 __be16 rsvd3; 1388 __u8 src_mac1[6]; 1389 __be16 rsvd4; 1390 __u8 src_mac0[6]; 1391}; 1392 1393struct cpl_rte_delete_req { 1394 WR_HDR; 1395 union opcode_tid ot; 1396 __be32 params; 1397}; 1398 1399/* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */ 1400#define S_RTE_REQ_LUT_IX 8 1401#define M_RTE_REQ_LUT_IX 0x7FF 1402#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1403#define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1404 1405#define S_RTE_REQ_LUT_BASE 19 1406#define M_RTE_REQ_LUT_BASE 0x7FF 1407#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1408#define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1409 1410#define S_RTE_READ_REQ_SELECT 31 1411#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1412#define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1413 1414struct cpl_rte_delete_rpl { 1415 RSS_HDR 1416 union opcode_tid ot; 1417 __u8 status; 1418 __u8 rsvd[3]; 1419}; 1420 1421struct cpl_rte_write_req { 1422 WR_HDR; 1423 union opcode_tid ot; 1424#if defined(__LITTLE_ENDIAN_BITFIELD) 1425 __u8 :6; 1426 __u8 write_tcam:1; 1427 __u8 write_l2t_lut:1; 1428#else 1429 __u8 write_l2t_lut:1; 1430 __u8 write_tcam:1; 1431 __u8 :6; 1432#endif 1433 __u8 rsvd[3]; 1434 __be32 lut_params; 1435 __be16 rsvd2; 1436 __be16 l2t_idx; 1437 __be32 netmask; 1438 __be32 faddr; 1439}; 1440 1441/* cpl_rte_write_req.lut_params fields */ 1442#define S_RTE_WRITE_REQ_LUT_IX 10 1443#define M_RTE_WRITE_REQ_LUT_IX 0x7FF 1444#define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) 1445#define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) 1446 1447#define S_RTE_WRITE_REQ_LUT_BASE 21 1448#define M_RTE_WRITE_REQ_LUT_BASE 0x7FF 1449#define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) 1450#define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) 1451 1452struct cpl_rte_write_rpl { 1453 RSS_HDR 1454 union opcode_tid ot; 1455 __u8 status; 1456 __u8 rsvd[3]; 1457}; 1458 1459struct cpl_rte_read_req { 1460 WR_HDR; 1461 union opcode_tid ot; 1462 __be32 params; 1463}; 1464 1465struct cpl_rte_read_rpl { 1466 RSS_HDR 1467 union opcode_tid ot; 1468 __u8 status; 1469 __u8 rsvd0; 1470 __be16 l2t_idx; 1471#if defined(__LITTLE_ENDIAN_BITFIELD) 1472 __u8 :7; 1473 __u8 select:1; 1474#else 1475 __u8 select:1; 1476 __u8 :7; 1477#endif 1478 __u8 rsvd2[3]; 1479 __be32 addr; 1480}; 1481 1482struct cpl_tid_release { 1483 WR_HDR; 1484 union opcode_tid ot; 1485 __be32 rsvd; 1486}; 1487 1488struct cpl_barrier { 1489 WR_HDR; 1490 __u8 opcode; 1491 __u8 rsvd[7]; 1492}; 1493 1494struct cpl_rdma_read_req { 1495 __u8 opcode; 1496 __u8 rsvd[15]; 1497}; 1498 1499struct cpl_rdma_terminate { 1500#ifdef CHELSIO_FW 1501 __u8 opcode; 1502 __u8 rsvd[2]; 1503#if defined(__LITTLE_ENDIAN_BITFIELD) 1504 __u8 rspq:3; 1505 __u8 :5; 1506#else 1507 __u8 :5; 1508 __u8 rspq:3; 1509#endif 1510 __be32 tid_len; 1511#endif 1512 __be32 msn; 1513 __be32 mo; 1514 __u8 data[0]; 1515}; 1516 1517/* cpl_rdma_terminate.tid_len fields */ 1518#define S_FLIT_CNT 0 1519#define M_FLIT_CNT 0xFF 1520#define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) 1521#define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) 1522 1523#define S_TERM_TID 8 1524#define M_TERM_TID 0xFFFFF 1525#define V_TERM_TID(x) ((x) << S_TERM_TID) 1526#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1527 1528/* ULP_TX opcodes */ 1529enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; 1530 1531#define S_ULPTX_CMD 28 1532#define M_ULPTX_CMD 0xF 1533#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 1534 1535#define S_ULPTX_NFLITS 0 1536#define M_ULPTX_NFLITS 0xFF 1537#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) 1538 1539struct ulp_mem_io { 1540 WR_HDR; 1541 __be32 cmd_lock_addr; 1542 __be32 len; 1543}; 1544 1545/* ulp_mem_io.cmd_lock_addr fields */ 1546#define S_ULP_MEMIO_ADDR 0 1547#define M_ULP_MEMIO_ADDR 0x7FFFFFF 1548#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 1549 1550#define S_ULP_MEMIO_LOCK 27 1551#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 1552#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 1553 1554/* ulp_mem_io.len fields */ 1555#define S_ULP_MEMIO_DATA_LEN 28 1556#define M_ULP_MEMIO_DATA_LEN 0xF 1557#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 1558 1559struct ulp_txpkt { 1560 __be32 cmd_dest; 1561 __be32 len; 1562}; 1563 1564/* ulp_txpkt.cmd_dest fields */ 1565#define S_ULP_TXPKT_DEST 24 1566#define M_ULP_TXPKT_DEST 0xF 1567#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 1568 1569#endif /* T3_CPL_H */ 1570