1139749Simp/*- 2126177Srik * AMD Am83C30 serial communication controller registers. 3126177Srik * 4126177Srik * Copyright (C) 1996 Cronyx Engineering. 5126177Srik * Author: Serge Vakulenko, <vak@cronyx.ru> 6126177Srik * 7126177Srik * This software is distributed with NO WARRANTIES, not even the implied 8126177Srik * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9126177Srik * 10126177Srik * Authors grant any other persons or organisations permission to use 11126177Srik * or modify this software as long as this message is kept with the software, 12126177Srik * all derivative works or modified versions. 13126177Srik * 14126177Srik * Cronyx Id: am8530.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $ 15126177Srik * $FreeBSD: releng/11.0/sys/dev/ctau/am8530.h 139749 2005-01-06 01:43:34Z imp $ 16126177Srik */ 17126177Srik 18126177Srik/* 19126177Srik * Read/write registers. 20126177Srik */ 21126177Srik#define AM_IVR 2 /* rw2 - interrupt vector register */ 22126177Srik#define AM_DAT 8 /* rw8 - data buffer register */ 23126177Srik#define AM_TCL 12 /* rw12 - time constant low */ 24126177Srik#define AM_TCH 13 /* rw13 - time constant high */ 25126177Srik#define AM_SICR 15 /* rw15 - status interrupt control reg */ 26126177Srik 27126177Srik/* 28126177Srik * Write only registers. 29126177Srik */ 30126177Srik#define AM_CR 0 /* w0 - command register */ 31126177Srik#define AM_IMR 1 /* w1 - interrupt mode register */ 32126177Srik#define AM_RCR 3 /* w3 - receive control register */ 33126177Srik#define AM_PMR 4 /* w4 - tx/rx parameters and modes reg */ 34126177Srik#define AM_TCR 5 /* w5 - transmit control register */ 35126177Srik#define AM_SAF 6 /* w6 - sync address field */ 36126177Srik#define AM_SFR 7 /* w7 - sync flag register */ 37126177Srik#define AM_MICR 9 /* w9 - master interrupt control reg */ 38126177Srik#define AM_MCR 10 /* w10 - misc control register */ 39126177Srik#define AM_CMR 11 /* w11 - clock mode register */ 40126177Srik#define AM_BCR 14 /* w14 - baud rate control register */ 41126177Srik 42126177Srik/* 43126177Srik * Read only registers. 44126177Srik */ 45126177Srik#define AM_SR 0 /* r0 - status register */ 46126177Srik#define AM_RSR 1 /* r1 - receive status register */ 47126177Srik#define AM_IPR 3 /* r3 - interrupt pending register */ 48126177Srik#define AM_MSR 10 /* r10 - misc status register */ 49126177Srik 50126177Srik/* 51126177Srik * Enhanced mode registers. 52126177Srik * In enhanced mode registers PMR(w4), TCR(w5) become readable. 53126177Srik */ 54126177Srik#define AM_FBCL 6 /* r6 - frame byte count low */ 55126177Srik#define AM_FBCH 7 /* r7 - frame byte count high */ 56126177Srik#define AM_RCR_R 9 /* r9 - read RCR(w3) */ 57126177Srik#define AM_MCR_R 11 /* r11 - read MCR(w10) */ 58126177Srik#define AM_SFR_R 14 /* r14 - read SFR(w7') */ 59126177Srik 60126177Srik#define AM_A 32 /* channel A offset */ 61126177Srik 62126177Srik/* 63126177Srik * Interrupt vector register 64126177Srik */ 65126177Srik#define IVR_A 0x08 /* channel A status */ 66126177Srik#define IVR_REASON 0x06 /* interrupt reason mask */ 67126177Srik#define IVR_TXRDY 0x00 /* transmit buffer empty */ 68126177Srik#define IVR_STATUS 0x02 /* external status interrupt */ 69126177Srik#define IVR_RX 0x04 /* receive character available */ 70126177Srik#define IVR_RXERR 0x06 /* special receive condition */ 71126177Srik 72126177Srik/* 73126177Srik * Interrupt mask register 74126177Srik */ 75126177Srik#define IMR_EXT 0x01 /* ext interrupt enable */ 76126177Srik#define IMR_TX 0x02 /* ext interrupt enable */ 77126177Srik#define IMR_PARITY 0x04 /* ext interrupt enable */ 78126177Srik 79126177Srik#define IMR_RX_FIRST 0x08 /* ext interrupt enable */ 80126177Srik#define IMR_RX_ALL 0x10 /* ext interrupt enable */ 81126177Srik#define IMR_RX_ERR 0x18 /* ext interrupt enable */ 82126177Srik 83126177Srik#define IMR_WD_RX 0x20 /* wait/request follows receiver fifo */ 84126177Srik#define IMR_WD_REQ 0x40 /* wait/request function as request */ 85126177Srik#define IMR_WD_ENABLE 0x80 /* wait/request pin enable */ 86126177Srik 87126177Srik/* 88126177Srik * Master interrupt control register 89126177Srik */ 90126177Srik#define MICR_VIS 0x01 /* vector includes status */ 91126177Srik#define MICR_NV 0x02 /* no interrupt vector */ 92126177Srik#define MICR_DLC 0x04 /* disable lower chain */ 93126177Srik#define MICR_MIE 0x08 /* master interrupt enable */ 94126177Srik#define MICR_HIGH 0x10 /* status high */ 95126177Srik#define MICR_NINTACK 0x20 /* interrupt masking without INTACK */ 96126177Srik 97126177Srik#define MICR_RESET_A 0x80 /* channel reset A */ 98126177Srik#define MICR_RESET_B 0x40 /* channel reset B */ 99126177Srik#define MICR_RESET_HW 0xc0 /* force hardware reset */ 100126177Srik 101126177Srik/* 102126177Srik * Receive status register 103126177Srik */ 104126177Srik#define RSR_FRME 0x10 /* framing error */ 105126177Srik#define RSR_RXOVRN 0x20 /* rx overrun error */ 106126177Srik 107126177Srik/* 108126177Srik * Command register 109126177Srik */ 110126177Srik#define CR_RST_EXTINT 0x10 /* reset external/status irq */ 111126177Srik#define CR_TX_ABORT 0x18 /* send abort (SDLC) */ 112126177Srik#define CR_RX_NXTINT 0x20 /* enable irq on next rx character */ 113126177Srik#define CR_RST_TXINT 0x28 /* reset tx irq pending */ 114126177Srik#define CR_RST_ERROR 0x30 /* error reset */ 115126177Srik#define CR_RST_HIUS 0x38 /* reset highest irq under service */ 116