if_bmreg.h revision 179645
1238438Sdteske/* 2238438Sdteske * Copyright 1991-1998 by Open Software Foundation, Inc. 3238438Sdteske * All Rights Reserved 4262904Sdteske * 5238438Sdteske * Permission to use, copy, modify, and distribute this software and 6238438Sdteske * its documentation for any purpose and without fee is hereby granted, 7238438Sdteske * provided that the above copyright notice appears in all copies and 8238438Sdteske * that both the copyright notice and this permission notice appear in 9238438Sdteske * supporting documentation. 10238438Sdteske * 11238438Sdteske * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 12238438Sdteske * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 13238438Sdteske * FOR A PARTICULAR PURPOSE. 14238438Sdteske * 15238438Sdteske * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 16238438Sdteske * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 17238438Sdteske * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 18238438Sdteske * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 19238438Sdteske * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20238438Sdteske */ 21238438Sdteske/* 22238438Sdteske * Copyright 2003 by Peter Grehan. All rights reserved. 23238438Sdteske * 24238438Sdteske * Redistribution and use in source and binary forms, with or without 25238438Sdteske * modification, are permitted provided that the following conditions 26238438Sdteske * are met: 27238438Sdteske * 1. Redistributions of source code must retain the above copyright 28238438Sdteske * notice, this list of conditions and the following disclaimer. 29238438Sdteske * 2. Redistributions in binary form must reproduce the above copyright 30238438Sdteske * notice, this list of conditions and the following disclaimer in the 31238438Sdteske * documentation and/or other materials provided with the distribution. 32240684Sdteske * 3. The name of the author may not be used to endorse or promote products 33240684Sdteske * derived from this software without specific prior written permission. 34244675Sdteske * 35240684Sdteske * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 36240684Sdteske * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 37262904Sdteske * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 38240684Sdteske * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 39238438Sdteske * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 40240684Sdteske * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 41238438Sdteske * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 42238438Sdteske * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 43259054Sdteske * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44259054Sdteske * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45238438Sdteske * SUCH DAMAGE. 46238438Sdteske * 47238438Sdteske * $FreeBSD: head/sys/dev/bm/if_bmreg.h 179645 2008-06-07 22:58:32Z marcel $ 48238438Sdteske */ 49238438Sdteske 50238438Sdteske/* 51238438Sdteske * BMAC resource indices 52238438Sdteske */ 53238438Sdteske 54250633Sdteske#define BM_MAIN_REGISTERS 0 55238438Sdteske#define BM_TXDMA_REGISTERS 1 56252178Sdteske#define BM_RXDMA_REGISTERS 2 57238438Sdteske 58238438Sdteske#define BM_MAIN_INTERRUPT 0 59238438Sdteske#define BM_TXDMA_INTERRUPT 1 60238438Sdteske#define BM_RXDMA_INTERRUPT 2 61238438Sdteske 62238438Sdteske/* 63238438Sdteske * BMAC/BMAC+ register offsets 64238438Sdteske */ 65238438Sdteske 66238438Sdteske#define BM_TX_IFC 0x0000 /* interface control */ 67238438Sdteske#define BM_TXFIFO_CSR 0x0100 /* TX FIFO control/status */ 68238438Sdteske#define BM_TX_THRESH 0x0110 /* TX threshold */ 69262904Sdteske#define BM_RXFIFO_CSR 0x0120 /* receive FIFO control/status */ 70238438Sdteske#define BM_MEMADD 0x0130 /* unused */ 71262904Sdteske#define BM_MEMDATA_HI 0x0140 /* unused */ 72262904Sdteske#define BM_MEMDATA_LO 0x0150 /* unused */ 73262904Sdteske#define BM_XCVR 0x0160 /* transceiver control register */ 74262904Sdteske#define BM_CHIPID 0x0170 /* chip ID */ 75262904Sdteske#define BM_MII_CSR 0x0180 /* MII control register */ 76262904Sdteske#define BM_SROM_CSR 0x0190 /* unused, OFW provides enet addr */ 77262904Sdteske#define BM_TX_PTR 0x01A0 /* unused */ 78262904Sdteske#define BM_RX_PTR 0x01B0 /* unused */ 79262904Sdteske#define BM_STATUS 0x01C0 /* status register */ 80238438Sdteske#define BM_INTR_DISABLE 0x0200 /* interrupt control register */ 81249751Sdteske#define BM_TX_RESET 0x0420 /* TX reset */ 82238438Sdteske#define BM_TX_CONFIG 0x0430 /* TX config */ 83251236Sdteske#define BM_IPG1 0x0440 /* inter-packet gap hi */ 84244550Sdteske#define BM_IPG2 0x0450 /* inter-packet gap lo */ 85249751Sdteske#define BM_TX_ALIMIT 0x0460 /* TX attempt limit */ 86238438Sdteske#define BM_TX_STIME 0x0470 /* TX slot time */ 87256181Sdteske#define BM_TX_PASIZE 0x0480 /* TX preamble size */ 88238438Sdteske#define BM_TX_PAPAT 0x0490 /* TX preamble pattern */ 89252019Sdteske#define BM_TX_SFD 0x04A0 /* TX start-frame delimiter */ 90252019Sdteske#define BM_JAMSIZE 0x04B0 /* collision jam size */ 91252019Sdteske#define BM_TX_MAXLEN 0x04C0 /* max TX packet length */ 92252019Sdteske#define BM_TX_MINLEN 0x04D0 /* min TX packet length */ 93262904Sdteske#define BM_TX_PEAKCNT 0x04E0 /* TX peak attempts count */ 94238438Sdteske#define BM_TX_DCNT 0x04F0 /* TX defer timer */ 95238438Sdteske#define BM_TX_NCCNT 0x0500 /* TX normal collision cnt */ 96238438Sdteske#define BM_TX_FCCNT 0x0510 /* TX first collision cnt */ 97238438Sdteske#define BM_TX_EXCNT 0x0520 /* TX excess collision cnt */ 98238438Sdteske#define BM_TX_LTCNT 0x0530 /* TX late collision cnt */ 99238438Sdteske#define BM_TX_RANDSEED 0x0540 /* TX random seed */ 100238438Sdteske#define BM_TXSM 0x0550 /* TX state machine */ 101#define BM_RX_RESET 0x0620 /* RX reset */ 102#define BM_RX_CONFIG 0x0630 /* RX config */ 103#define BM_RX_MAXLEN 0x0640 /* max RX packet length */ 104#define BM_RX_MINLEN 0x0650 /* min RX packet length */ 105#define BM_MACADDR2 0x0660 /* MAC address */ 106#define BM_MACADDR1 0x0670 107#define BM_MACADDR0 0x0680 108#define BM_RX_FRCNT 0x0690 /* RX frame count */ 109#define BM_RX_LECNT 0x06A0 /* RX too-long frame count */ 110#define BM_RX_AECNT 0x06B0 /* RX misaligned frame count */ 111#define BM_RX_FECNT 0x06C0 /* RX CRC error count */ 112#define BM_RXSM 0x06D0 /* RX state machine */ 113#define BM_RXCV 0x06E0 /* RX code violations */ 114#define BM_HASHTAB3 0x0700 /* Address hash table */ 115#define BM_HASHTAB2 0x0710 116#define BM_HASHTAB1 0x0720 117#define BM_HASHTAB0 0x0730 118#define BM_AFILTER2 0x0740 /* Address filter */ 119#define BM_AFILTER1 0x0750 120#define BM_AFILTER0 0x0760 121#define BM_AFILTER_MASK 0x0770 122 123/* 124 * MII control register bits 125 */ 126#define BM_MII_CLK 0x0001 /* MDIO clock */ 127#define BM_MII_DATAOUT 0x0002 /* MDIO data out */ 128#define BM_MII_OENABLE 0x0004 /* MDIO output enable */ 129#define BM_MII_DATAIN 0x0008 /* MDIO data in */ 130 131/* 132 * MII constants 133 */ 134#define BM_MII_STARTDELIM 0x01 135#define BM_MII_READOP 0x02 136#define BM_MII_WRITEOP 0x01 137#define BM_MII_TURNAROUND 0x02 138 139/* 140 * Various flags 141 */ 142 143#define BM_ENABLE 0x0001 144 145#define BM_CRC_ENABLE 0x0100 146#define BM_HASH_FILTER_ENABLE 0x0200 147#define BM_REJECT_OWN_PKTS 0x0800 148#define BM_PROMISC 0x0040 149 150#define BM_TX_FULLDPX 0x0200 151#define BM_TX_IGNORECOLL 0x0040 152 153#define BM_INTR_PKT_RX 0x0001 154#define BM_INTR_PKT_TX 0x0100 155#define BM_INTR_TX_UNDERRUN 0x0200 156 157#define BM_INTR_NORMAL ~(BM_INTR_PKT_TX | BM_INTR_TX_UNDERRUN) 158#define BM_INTR_NONE 0xffff 159 160/* 161 * register space access macros 162 */ 163#define CSR_WRITE_4(sc, reg, val) \ 164 bus_space_write_4(sc->sc_btag, sc->sc_bhandle, reg, val) 165#define CSR_WRITE_2(sc, reg, val) \ 166 bus_space_write_2(sc->sc_btag, sc->sc_bhandle, reg, val) 167#define CSR_WRITE_1(sc, reg, val) \ 168 bus_space_write_1(sc->sc_btag, sc->sc_bhandle, reg, val) 169 170#define CSR_READ_4(sc, reg) \ 171 bus_space_read_4(sc->sc_btag, sc->sc_bhandle, reg) 172#define CSR_READ_2(sc, reg) \ 173 bus_space_read_2(sc->sc_btag, sc->sc_bhandle, reg) 174#define CSR_READ_1(sc, reg) \ 175 bus_space_read_1(sc->sc_btag, sc->sc_bhandle, reg) 176 177