bhndb_pcireg.h revision 299241
1/*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2010 Broadcom Corporation 4 * 5 * Portions of this file were derived from the bcmdevs.h header contributed by 6 * Broadcom to Android's bcmdhd driver module, and the pcicfg.h header 7 * distributed with Broadcom's initial brcm80211 Linux driver release. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 16 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 18 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 19 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 * $FreeBSD: head/sys/dev/bhnd/bhndb/bhndb_pcireg.h 299241 2016-05-08 19:14:05Z adrian $ 22 */ 23 24#ifndef _BHND_BHNDB_PCIREG_H_ 25#define _BHND_BHNDB_PCIREG_H_ 26 27/* 28 * Common PCI/PCIE Bridge Configuration Registers. 29 * 30 * = MAJOR CORE REVISIONS = 31 * 32 * There have been four revisions to the BAR0/BAR1 memory mappings used 33 * in BHND PCI/PCIE bridge cores: 34 * 35 * == PCI_V0 == 36 * Applies to: 37 * - PCI (cid=0x804, revision <= 12) 38 * BAR size: 8KB 39 * Address Map: 40 * [offset+ size] type description 41 * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 42 * [0x1000+0x0800] fixed SPROM shadow 43 * [0x1800+0x0800] fixed pci core registers 44 * 45 * == PCI_V1 == 46 * Applies to: 47 * - PCI (cid=0x804, revision >= 13) 48 * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 49 * BAR size: 16KB 50 * Address Map: 51 * [offset+ size] type description 52 * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 53 * [0x1000+0x1000] fixed SPROM shadow 54 * [0x2000+0x1000] fixed pci/pcie core registers 55 * [0x3000+0x1000] fixed chipcommon core registers 56 * 57 * == PCI_V2 == 58 * Applies to: 59 * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 60 * BAR size: 16KB 61 * Address Map: 62 * [offset+ size] type description 63 * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 64 * [0x1000+0x1000] dynamic mapped backplane address space (window 1). 65 * [0x2000+0x1000] fixed pci/pcie core registers 66 * [0x3000+0x1000] fixed chipcommon core registers 67 * 68 * == PCI_V3 == 69 * Applies to: 70 * - PCIE Gen 2 (cid=0x83c) 71 * BAR size: 32KB? 72 * Address Map: 73 * [offset+ size] type description 74 * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 75 * [0x1000+0x1000] dynamic mapped backplane address space (window 1). 76 * [0x2000+0x1000] fixed pci/pcie core registers 77 * [0x3000+0x1000] fixed chipcommon core registers 78 * [???] 79 * 80 * = MINOR CORE REVISIONS = 81 * 82 * == PCI Cores Revision >= 3 == 83 * - Mapped GPIO CSRs into the PCI config space. Refer to 84 * BHND_PCI_GPIO_*. 85 * 86 * == PCI/PCIE Cores Revision >= 14 == 87 * - Mapped the clock CSR into the PCI config space. Refer to 88 * BHND_PCI_CLK_CTL_ST 89 * 90 * = Hardware Bugs = 91 * == BAR1 == 92 * 93 * The BHND PCI(e) cores hypothetically support an additional memory mapping 94 * of the backplane address space via BAR1, but this appears to be subject 95 * to a hardware bug in which BAR1 is initially configured with a 4 byte 96 * length. 97 * 98 * A work-around for this bug may be possible by writing to the PCI core's 99 * BAR1 config register (0x4e0), but this requires further research -- I've 100 * found three sources for information on the BAR1 PCI core configuration that 101 * may be relevant: 102 * - The QLogix NetXTreme 10GB PCIe NIC seems to use the same PCIE 103 * core IP block as is used in other BHND devices. The bxe(4) driver 104 * contains example initialization code and register constants 105 * that may apply (e.g. GRC_BAR2_CONFIG/PCI_CONFIG_2_BAR2_SIZE). 106 * - The publicly available Broadcom BCM440X data sheet (440X-PG02-R) 107 * appears to (partially) document a Broadcom PCI(e) core that has a 108 * seemingly compatible programming model. 109 * - The Android bcmdhd driver sources include a possible work-around 110 * implementation (writing to 0x4e0) in dhd_pcie.c 111 */ 112 113/* Common PCI/PCIE Config Registers */ 114#define BHNDB_PCI_SPROM_CONTROL 0x88 /* sprom property control */ 115#define BHNDB_PCI_BAR1_CONTROL 0x8c /* BAR1 region prefetch/burst control */ 116#define BHNDB_PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 117#define BHNDB_PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 118#define BHNDB_PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 119#define BHNDB_PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */ 120#define BHNDB_PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */ 121 122/* PCI (non-PCIe) GPIO/Clock Config Registers */ 123#define BHNDB_PCI_CLK_CTL 0xa8 /* clock control/status (pci >=rev14) */ 124#define BHNDB_PCI_GPIO_IN 0xb0 /* gpio input (pci >=rev3) */ 125#define BHNDB_PCI_GPIO_OUT 0xb4 /* gpio output (pci >=rev3) */ 126#define BHNDB_PCI_GPIO_OUTEN 0xb8 /* gpio output enable (pci >=rev3) */ 127 128/* Hardware revisions used to determine PCI revision */ 129#define BHNDB_PCI_V0_MAX_PCI_HWREV 12 130#define BHNDB_PCI_V1_MIN_PCI_HWREV 13 131#define BHNDB_PCI_V1_MAX_CHIPC_HWREV 31 132#define BHNDB_PCI_V2_MIN_CHIPC_HWREV 32 133 134/** 135 * Number of times to retry writing to a PCI window address register. 136 * 137 * On siba(4) devices, it's possible that writing a PCI window register may 138 * not succeed; it's necessary to immediately read the configuration register 139 * and retry if not set to the desired value. 140 */ 141#define BHNDB_PCI_BARCTRL_WRITE_RETRY 50 142 143/* PCI_V0 */ 144#define BHNDB_PCI_V0_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 145#define BHNDB_PCI_V0_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 146 147#define BHNDB_PCI_V0_BAR0_SIZE 0x2000 /* 8KB BAR0 */ 148#define BHNDB_PCI_V0_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 149#define BHNDB_PCI_V0_BAR0_WIN0_SIZE 0x1000 150#define BHNDB_PCI_V0_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */ 151#define BHNDB_PCI_V0_BAR0_SPROM_SIZE 0x0800 152#define BHNDB_PCI_V0_BAR0_PCIREG_OFFSET 0x1800 /* bar0 + 6K accesses pci core registers */ 153#define BHNDB_PCI_V0_BAR0_PCIREG_SIZE 0x0800 154 155/* PCI_V1 */ 156#define BHNDB_PCI_V1_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 157#define BHNDB_PCI_V1_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 158 159#define BHNDB_PCI_V1_BAR0_SIZE 0x4000 /* 16KB BAR0 */ 160#define BHNDB_PCI_V1_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 161#define BHNDB_PCI_V1_BAR0_WIN0_SIZE 0x1000 162#define BHNDB_PCI_V1_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */ 163#define BHNDB_PCI_V1_BAR0_SPROM_SIZE 0x1000 164#define BHNDB_PCI_V1_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 165#define BHNDB_PCI_V1_BAR0_PCIREG_SIZE 0x1000 166#define BHNDB_PCI_V1_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 167#define BHNDB_PCI_V1_BAR0_CCREGS_SIZE 0x1000 168 169/* PCI_V2 */ 170#define BHNDB_PCI_V2_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 171#define BHNDB_PCI_V2_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 172#define BHNDB_PCI_V2_BAR0_WIN1_CONTROL 0xAC /* backplane address space accessed by BAR0/WIN1 */ 173 174#define BHNDB_PCI_V2_BAR0_SIZE 0x4000 /* 16KB BAR0 */ 175#define BHNDB_PCI_V2_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 176#define BHNDB_PCI_V2_BAR0_WIN0_SIZE 0x1000 177#define BHNDB_PCI_V2_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */ 178#define BHNDB_PCI_V2_BAR0_WIN1_SIZE 0x1000 179#define BHNDB_PCI_V2_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 180#define BHNDB_PCI_V2_BAR0_PCIREG_SIZE 0x1000 181#define BHNDB_PCI_V2_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 182#define BHNDB_PCI_V2_BAR0_CCREGS_SIZE 0x1000 183 184/* PCI_V3 */ 185#define BHNDB_PCI_V3_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 186#define BHNDB_PCI_V3_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 187#define BHNDB_PCI_V3_BAR0_WIN1_CONTROL 0x70 /* backplane address space accessed by BAR0/WIN1 */ 188 189#define BHNDB_PCI_V3_BAR0_SIZE 0x8000 /* 32KB BAR0 (?) */ 190#define BHNDB_PCI_V3_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 191#define BHNDB_PCI_V3_BAR0_WIN0_SIZE 0x1000 192#define BHNDB_PCI_V3_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */ 193#define BHNDB_PCI_V3_BAR0_WIN1_SIZE 0x1000 194#define BHNDB_PCI_V3_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 195#define BHNDB_PCI_V3_BAR0_PCIREG_SIZE 0x1000 196#define BHNDB_PCI_V3_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 197#define BHNDB_PCI_V3_BAR0_CCREGS_SIZE 0x1000 198 199/* BHNDB_PCI_INT_STATUS */ 200#define BHNDB_PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 201 202/* BHNDB_PCI_INT_MASK */ 203#define BHNDB_PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 204#define BHNDB_PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 205#define BHNDB_PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 206 207/* BHNDB_PCI_SPROM_CONTROL */ 208#define BHNDB_PCI_SPROM_SZ_MASK 0x03 /**< sprom size mask */ 209#define BHNDB_PCI_SPROM_SZ_1KB 0x00 /**< 1KB sprom size */ 210#define BHNDB_PCI_SPROM_SZ_4KB 0x01 /**< 4KB sprom size */ 211#define BHNDB_PCI_SPROM_SZ_16KB 0x02 /**< 16KB sprom size */ 212#define BHNDB_PCI_SPROM_SZ_RESERVED 0x03 /**< unsupported sprom size */ 213#define BHNDB_PCI_SPROM_LOCKED 0x08 /**< sprom locked */ 214#define BHNDB_PCI_SPROM_BLANK 0x04 /**< sprom blank */ 215#define BHNDB_PCI_SPROM_WRITEEN 0x10 /**< sprom write enable */ 216#define BHNDB_PCI_SPROM_BOOTROM_WE 0x20 /**< external bootrom write enable */ 217#define BHNDB_PCI_SPROM_BACKPLANE_EN 0x40 /**< enable indirect backplane access (BHNDB_PCI_BACKPLANE_*) */ 218#define BHNDB_PCI_SPROM_OTPIN_USE 0x80 /**< device OTP in use */ 219 220 221/* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN */ 222#define BHNDB_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ 223#define BHNDB_PCI_GPIO_HWRAD_OFF 0x20 /* PCI config space GPIO 13 for hw radio disable */ 224#define BHNDB_PCI_GPIO_XTAL_ON 0x40 /* PCI config space GPIO 14 for Xtal power-up */ 225#define BHNDB_PCI_GPIO_PLL_OFF 0x80 /* PCI config space GPIO 15 for PLL power-down */ 226 227#endif /* _BHND_BHNDB_PCIREG_H_ */ 228