1296077Sadrian/*- 2296077Sadrian * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3296077Sadrian * Copyright (c) 2010 Broadcom Corporation 4296077Sadrian * 5296077Sadrian * Portions of this file were derived from the bcmdevs.h header contributed by 6296077Sadrian * Broadcom to Android's bcmdhd driver module, and the pcicfg.h header 7296077Sadrian * distributed with Broadcom's initial brcm80211 Linux driver release. 8296077Sadrian * 9296077Sadrian * Permission to use, copy, modify, and/or distribute this software for any 10296077Sadrian * purpose with or without fee is hereby granted, provided that the above 11296077Sadrian * copyright notice and this permission notice appear in all copies. 12296077Sadrian * 13296077Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14296077Sadrian * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15296077Sadrian * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 16296077Sadrian * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17296077Sadrian * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 18296077Sadrian * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 19296077Sadrian * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20296077Sadrian * 21296077Sadrian * $FreeBSD: releng/11.0/sys/dev/bhnd/bhndb/bhndb_pcireg.h 300015 2016-05-17 06:52:53Z adrian $ 22296077Sadrian */ 23296077Sadrian 24296077Sadrian#ifndef _BHND_BHNDB_PCIREG_H_ 25296077Sadrian#define _BHND_BHNDB_PCIREG_H_ 26296077Sadrian 27296077Sadrian/* 28296077Sadrian * Common PCI/PCIE Bridge Configuration Registers. 29296077Sadrian * 30296077Sadrian * = MAJOR CORE REVISIONS = 31296077Sadrian * 32300015Sadrian * There have been four revisions to the BAR0 memory mappings used 33296077Sadrian * in BHND PCI/PCIE bridge cores: 34296077Sadrian * 35296077Sadrian * == PCI_V0 == 36296077Sadrian * Applies to: 37296077Sadrian * - PCI (cid=0x804, revision <= 12) 38300015Sadrian * BAR0 size: 8KB 39296077Sadrian * Address Map: 40296077Sadrian * [offset+ size] type description 41296077Sadrian * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 42296077Sadrian * [0x1000+0x0800] fixed SPROM shadow 43296077Sadrian * [0x1800+0x0800] fixed pci core registers 44296077Sadrian * 45296077Sadrian * == PCI_V1 == 46296077Sadrian * Applies to: 47296077Sadrian * - PCI (cid=0x804, revision >= 13) 48296077Sadrian * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 49300015Sadrian * BAR0 size: 16KB 50296077Sadrian * Address Map: 51296077Sadrian * [offset+ size] type description 52296077Sadrian * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 53296077Sadrian * [0x1000+0x1000] fixed SPROM shadow 54296077Sadrian * [0x2000+0x1000] fixed pci/pcie core registers 55296077Sadrian * [0x3000+0x1000] fixed chipcommon core registers 56296077Sadrian * 57296077Sadrian * == PCI_V2 == 58296077Sadrian * Applies to: 59296077Sadrian * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 60300015Sadrian * BAR0 size: 16KB 61296077Sadrian * Address Map: 62296077Sadrian * [offset+ size] type description 63296077Sadrian * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 64296077Sadrian * [0x1000+0x1000] dynamic mapped backplane address space (window 1). 65296077Sadrian * [0x2000+0x1000] fixed pci/pcie core registers 66296077Sadrian * [0x3000+0x1000] fixed chipcommon core registers 67296077Sadrian * 68296077Sadrian * == PCI_V3 == 69296077Sadrian * Applies to: 70296077Sadrian * - PCIE Gen 2 (cid=0x83c) 71300015Sadrian * BAR0 size: 32KB 72296077Sadrian * Address Map: 73296077Sadrian * [offset+ size] type description 74296077Sadrian * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 75296077Sadrian * [0x1000+0x1000] dynamic mapped backplane address space (window 1). 76296077Sadrian * [0x2000+0x1000] fixed pci/pcie core registers 77296077Sadrian * [0x3000+0x1000] fixed chipcommon core registers 78296077Sadrian * [???] 79300015Sadrian * BAR1 size: varies 80300015Sadrian * Address Map: 81300015Sadrian * [offset+ size] type description 82300015Sadrian * [0x0000+0x????] fixed ARM tightly-coupled memory (TCM). 83300015Sadrian * While fullmac chipsets provided a fixed 84300015Sadrian * 4KB mapping, newer devices will vary. 85296077Sadrian * 86296077Sadrian * = MINOR CORE REVISIONS = 87296077Sadrian * 88296077Sadrian * == PCI Cores Revision >= 3 == 89296077Sadrian * - Mapped GPIO CSRs into the PCI config space. Refer to 90296077Sadrian * BHND_PCI_GPIO_*. 91296077Sadrian * 92296077Sadrian * == PCI/PCIE Cores Revision >= 14 == 93296077Sadrian * - Mapped the clock CSR into the PCI config space. Refer to 94296077Sadrian * BHND_PCI_CLK_CTL_ST 95296077Sadrian */ 96296077Sadrian 97296077Sadrian/* Common PCI/PCIE Config Registers */ 98296077Sadrian#define BHNDB_PCI_SPROM_CONTROL 0x88 /* sprom property control */ 99296077Sadrian#define BHNDB_PCI_BAR1_CONTROL 0x8c /* BAR1 region prefetch/burst control */ 100296077Sadrian#define BHNDB_PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 101296077Sadrian#define BHNDB_PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 102296077Sadrian#define BHNDB_PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 103296077Sadrian#define BHNDB_PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */ 104296077Sadrian#define BHNDB_PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */ 105296077Sadrian 106296077Sadrian/* PCI (non-PCIe) GPIO/Clock Config Registers */ 107296077Sadrian#define BHNDB_PCI_CLK_CTL 0xa8 /* clock control/status (pci >=rev14) */ 108296077Sadrian#define BHNDB_PCI_GPIO_IN 0xb0 /* gpio input (pci >=rev3) */ 109296077Sadrian#define BHNDB_PCI_GPIO_OUT 0xb4 /* gpio output (pci >=rev3) */ 110296077Sadrian#define BHNDB_PCI_GPIO_OUTEN 0xb8 /* gpio output enable (pci >=rev3) */ 111296077Sadrian 112296077Sadrian/* Hardware revisions used to determine PCI revision */ 113296077Sadrian#define BHNDB_PCI_V0_MAX_PCI_HWREV 12 114296077Sadrian#define BHNDB_PCI_V1_MIN_PCI_HWREV 13 115296077Sadrian#define BHNDB_PCI_V1_MAX_CHIPC_HWREV 31 116296077Sadrian#define BHNDB_PCI_V2_MIN_CHIPC_HWREV 32 117296077Sadrian 118296077Sadrian/** 119296077Sadrian * Number of times to retry writing to a PCI window address register. 120296077Sadrian * 121296077Sadrian * On siba(4) devices, it's possible that writing a PCI window register may 122296077Sadrian * not succeed; it's necessary to immediately read the configuration register 123296077Sadrian * and retry if not set to the desired value. 124296077Sadrian */ 125296077Sadrian#define BHNDB_PCI_BARCTRL_WRITE_RETRY 50 126296077Sadrian 127296077Sadrian/* PCI_V0 */ 128296077Sadrian#define BHNDB_PCI_V0_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 129296077Sadrian#define BHNDB_PCI_V0_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 130296077Sadrian 131296077Sadrian#define BHNDB_PCI_V0_BAR0_SIZE 0x2000 /* 8KB BAR0 */ 132296077Sadrian#define BHNDB_PCI_V0_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 133296077Sadrian#define BHNDB_PCI_V0_BAR0_WIN0_SIZE 0x1000 134296077Sadrian#define BHNDB_PCI_V0_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */ 135296077Sadrian#define BHNDB_PCI_V0_BAR0_SPROM_SIZE 0x0800 136296077Sadrian#define BHNDB_PCI_V0_BAR0_PCIREG_OFFSET 0x1800 /* bar0 + 6K accesses pci core registers */ 137296077Sadrian#define BHNDB_PCI_V0_BAR0_PCIREG_SIZE 0x0800 138296077Sadrian 139296077Sadrian/* PCI_V1 */ 140296077Sadrian#define BHNDB_PCI_V1_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 141296077Sadrian#define BHNDB_PCI_V1_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 142296077Sadrian 143296077Sadrian#define BHNDB_PCI_V1_BAR0_SIZE 0x4000 /* 16KB BAR0 */ 144296077Sadrian#define BHNDB_PCI_V1_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 145296077Sadrian#define BHNDB_PCI_V1_BAR0_WIN0_SIZE 0x1000 146296077Sadrian#define BHNDB_PCI_V1_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */ 147296077Sadrian#define BHNDB_PCI_V1_BAR0_SPROM_SIZE 0x1000 148296077Sadrian#define BHNDB_PCI_V1_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 149296077Sadrian#define BHNDB_PCI_V1_BAR0_PCIREG_SIZE 0x1000 150296077Sadrian#define BHNDB_PCI_V1_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 151296077Sadrian#define BHNDB_PCI_V1_BAR0_CCREGS_SIZE 0x1000 152296077Sadrian 153296077Sadrian/* PCI_V2 */ 154296077Sadrian#define BHNDB_PCI_V2_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 155296077Sadrian#define BHNDB_PCI_V2_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 156296077Sadrian#define BHNDB_PCI_V2_BAR0_WIN1_CONTROL 0xAC /* backplane address space accessed by BAR0/WIN1 */ 157296077Sadrian 158296077Sadrian#define BHNDB_PCI_V2_BAR0_SIZE 0x4000 /* 16KB BAR0 */ 159296077Sadrian#define BHNDB_PCI_V2_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 160296077Sadrian#define BHNDB_PCI_V2_BAR0_WIN0_SIZE 0x1000 161296077Sadrian#define BHNDB_PCI_V2_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */ 162296077Sadrian#define BHNDB_PCI_V2_BAR0_WIN1_SIZE 0x1000 163296077Sadrian#define BHNDB_PCI_V2_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 164296077Sadrian#define BHNDB_PCI_V2_BAR0_PCIREG_SIZE 0x1000 165296077Sadrian#define BHNDB_PCI_V2_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 166296077Sadrian#define BHNDB_PCI_V2_BAR0_CCREGS_SIZE 0x1000 167296077Sadrian 168300015Sadrian/* PCI_V3 (PCIe-G2) */ 169296077Sadrian#define BHNDB_PCI_V3_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 170296077Sadrian#define BHNDB_PCI_V3_BAR0_WIN1_CONTROL 0x70 /* backplane address space accessed by BAR0/WIN1 */ 171296077Sadrian 172300015Sadrian#define BHNDB_PCI_V3_BAR0_SIZE 0x8000 /* 32KB BAR0 */ 173296077Sadrian#define BHNDB_PCI_V3_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 174296077Sadrian#define BHNDB_PCI_V3_BAR0_WIN0_SIZE 0x1000 175296077Sadrian#define BHNDB_PCI_V3_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */ 176296077Sadrian#define BHNDB_PCI_V3_BAR0_WIN1_SIZE 0x1000 177296077Sadrian#define BHNDB_PCI_V3_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 178296077Sadrian#define BHNDB_PCI_V3_BAR0_PCIREG_SIZE 0x1000 179296077Sadrian#define BHNDB_PCI_V3_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 180296077Sadrian#define BHNDB_PCI_V3_BAR0_CCREGS_SIZE 0x1000 181296077Sadrian 182296077Sadrian/* BHNDB_PCI_INT_STATUS */ 183296077Sadrian#define BHNDB_PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 184296077Sadrian 185296077Sadrian/* BHNDB_PCI_INT_MASK */ 186296077Sadrian#define BHNDB_PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 187296077Sadrian#define BHNDB_PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 188296077Sadrian#define BHNDB_PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 189296077Sadrian 190296077Sadrian/* BHNDB_PCI_SPROM_CONTROL */ 191299241Sadrian#define BHNDB_PCI_SPROM_SZ_MASK 0x03 /**< sprom size mask */ 192299241Sadrian#define BHNDB_PCI_SPROM_SZ_1KB 0x00 /**< 1KB sprom size */ 193299241Sadrian#define BHNDB_PCI_SPROM_SZ_4KB 0x01 /**< 4KB sprom size */ 194299241Sadrian#define BHNDB_PCI_SPROM_SZ_16KB 0x02 /**< 16KB sprom size */ 195299241Sadrian#define BHNDB_PCI_SPROM_SZ_RESERVED 0x03 /**< unsupported sprom size */ 196299241Sadrian#define BHNDB_PCI_SPROM_LOCKED 0x08 /**< sprom locked */ 197299241Sadrian#define BHNDB_PCI_SPROM_BLANK 0x04 /**< sprom blank */ 198299241Sadrian#define BHNDB_PCI_SPROM_WRITEEN 0x10 /**< sprom write enable */ 199299241Sadrian#define BHNDB_PCI_SPROM_BOOTROM_WE 0x20 /**< external bootrom write enable */ 200299241Sadrian#define BHNDB_PCI_SPROM_BACKPLANE_EN 0x40 /**< enable indirect backplane access (BHNDB_PCI_BACKPLANE_*) */ 201299241Sadrian#define BHNDB_PCI_SPROM_OTPIN_USE 0x80 /**< device OTP in use */ 202296077Sadrian 203296077Sadrian 204296077Sadrian/* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN */ 205296077Sadrian#define BHNDB_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ 206296077Sadrian#define BHNDB_PCI_GPIO_HWRAD_OFF 0x20 /* PCI config space GPIO 13 for hw radio disable */ 207296077Sadrian#define BHNDB_PCI_GPIO_XTAL_ON 0x40 /* PCI config space GPIO 14 for Xtal power-up */ 208296077Sadrian#define BHNDB_PCI_GPIO_PLL_OFF 0x80 /* PCI config space GPIO 15 for PLL power-down */ 209296077Sadrian 210296077Sadrian#endif /* _BHND_BHNDB_PCIREG_H_ */ 211