bhndb_pci_hwdata.c revision 300628
1/*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c 300628 2016-05-24 21:20:17Z adrian $"); 32 33/* 34 * Resource specifications and register maps for Broadcom PCI/PCIe cores 35 * configured as PCI-BHND bridges. 36 */ 37 38#include <sys/param.h> 39#include <sys/bus.h> 40 41#include <machine/bus.h> 42#include <sys/rman.h> 43#include <machine/resource.h> 44 45#include <dev/pci/pcireg.h> 46#include <dev/pci/pcivar.h> 47 48#include "bhndbvar.h" 49#include "bhndb_pcireg.h" 50 51static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; 52static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; 53static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; 54static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; 55static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; 56 57/** 58 * Define a bhndb_hw match entry. 59 * 60 * @param _name The entry name. 61 * @param _vers The configuration version associated with this entry. 62 */ 63#define BHNDB_HW_MATCH(_name, _vers, ...) { \ 64 .name = _name, \ 65 .hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \ 66 .num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \ 67 sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \ 68 .cfg = &bhndb_pci_hwcfg_ ## _vers \ 69} 70 71#define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ } 72 73/** 74 * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based 75 * PCI devices; this configuration is adequate for enumerating a bridged 76 * siba(4) bus to determine the full hardware configuration. 77 * 78 * @par Compatibility 79 * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices. 80 * - Compatible with siba(4) bus enumeration. 81 * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped 82 * at the default enumeration address (0x18000000). 83 */ 84const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = { 85 .resource_specs = (const struct resource_spec[]) { 86 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 87 { -1, 0, 0 } 88 }, 89 90 .register_windows = (const struct bhndb_regwin[]) { 91 /* bar0+0x0000: configurable backplane window */ 92 { 93 .win_type = BHNDB_REGWIN_T_DYN, 94 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 95 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 96 .d.dyn = { 97 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 98 }, 99 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 100 }, 101 BHNDB_REGWIN_TABLE_END 102 }, 103}; 104 105 106/** 107 * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based 108 * PCI devices; this configuration is adequate for enumerating a bridged 109 * bcma(4) bus to determine the full hardware configuration. 110 * 111 * @par Compatibility 112 * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices. 113 * - Compatible with both siba(4) and bcma(4) bus enumeration. 114 */ 115const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = { 116 .resource_specs = (const struct resource_spec[]) { 117 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 118 { -1, 0, 0 } 119 }, 120 121 .register_windows = (const struct bhndb_regwin[]) { 122 /* bar0+0x0000: configurable backplane window */ 123 { 124 .win_type = BHNDB_REGWIN_T_DYN, 125 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 126 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 127 .d.dyn = { 128 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 129 }, 130 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 131 }, 132 133 /* bar0+0x3000: chipc core registers */ 134 { 135 .win_type = BHNDB_REGWIN_T_CORE, 136 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 137 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 138 .d.core = { 139 .class = BHND_DEVCLASS_CC, 140 .unit = 0, 141 .port = 0, 142 .region = 0, 143 .port_type = BHND_PORT_DEVICE 144 }, 145 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 146 }, 147 148 BHNDB_REGWIN_TABLE_END 149 }, 150}; 151 152/** 153 * Hardware configuration tables for Broadcom HND PCI NICs. 154 */ 155const struct bhndb_hw bhndb_pci_generic_hw_table[] = { 156 /* PCI/V0 WLAN */ 157 BHNDB_HW_MATCH("PCI/v0 WLAN", v0, 158 /* PCI Core */ 159 { 160 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 161 BHND_MATCH_CORE_ID (BHND_COREID_PCI), 162 BHND_MATCH_CORE_REV( 163 HWREV_LTE (BHNDB_PCI_V0_MAX_PCI_HWREV)), 164 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI), 165 BHND_MATCH_CORE_UNIT (0) 166 }, 167 168 /* 802.11 Core */ 169 { 170 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 171 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 172 BHND_MATCH_CORE_UNIT (0) 173 } 174 ), 175 176 /* PCI/V1 WLAN */ 177 BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci, 178 /* PCI Core */ 179 { 180 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 181 BHND_MATCH_CORE_ID (BHND_COREID_PCI), 182 BHND_MATCH_CORE_REV( 183 HWREV_GTE (BHNDB_PCI_V1_MIN_PCI_HWREV)), 184 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI), 185 BHND_MATCH_CORE_UNIT (0) 186 }, 187 188 /* 802.11 Core */ 189 { 190 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 191 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 192 BHND_MATCH_CORE_UNIT (0) 193 } 194 ), 195 196 /* PCIE/V1 WLAN */ 197 BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie, 198 /* PCIe Core */ 199 { 200 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 201 BHND_MATCH_CORE_ID (BHND_COREID_PCIE), 202 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 203 BHND_MATCH_CORE_UNIT (0) 204 }, 205 206 /* ChipCommon (revision <= 31) */ 207 { 208 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 209 BHND_MATCH_CORE_ID (BHND_COREID_CC), 210 BHND_MATCH_CORE_REV( 211 HWREV_LTE (BHNDB_PCI_V1_MAX_CHIPC_HWREV)), 212 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC), 213 BHND_MATCH_CORE_UNIT (0) 214 }, 215 216 /* 802.11 Core */ 217 { 218 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 219 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 220 BHND_MATCH_CORE_UNIT (0) 221 } 222 ), 223 224 /* PCIE/V2 WLAN */ 225 BHNDB_HW_MATCH("PCIe/v2 WLAN", v2, 226 /* PCIe Core */ 227 { 228 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 229 BHND_MATCH_CORE_ID (BHND_COREID_PCIE), 230 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 231 BHND_MATCH_CORE_UNIT (0) 232 }, 233 234 /* ChipCommon (revision >= 32) */ 235 { 236 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 237 BHND_MATCH_CORE_ID (BHND_COREID_CC), 238 BHND_MATCH_CORE_REV( 239 HWREV_GTE (BHNDB_PCI_V2_MIN_CHIPC_HWREV)), 240 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC), 241 BHND_MATCH_CORE_UNIT (0) 242 }, 243 244 /* 802.11 Core */ 245 { 246 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 247 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 248 BHND_MATCH_CORE_UNIT (0) 249 } 250 ), 251 252 253 /* PCIE/V3 WLAN */ 254 BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3, 255 /* PCIe Gen2 Core */ 256 { 257 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 258 BHND_MATCH_CORE_ID (BHND_COREID_PCIE2), 259 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 260 BHND_MATCH_CORE_UNIT (0) 261 }, 262 263 /* 802.11 Core */ 264 { 265 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 266 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 267 BHND_MATCH_CORE_UNIT (0) 268 } 269 ), 270 271 { NULL, NULL, 0, NULL } 272}; 273 274/** 275 * PCI_V0 hardware configuration. 276 * 277 * Applies to: 278 * - PCI (cid=0x804, revision <= 12) 279 */ 280static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = { 281 .resource_specs = (const struct resource_spec[]) { 282 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 283 { -1, 0, 0 } 284 }, 285 286 .register_windows = (const struct bhndb_regwin[]) { 287 /* bar0+0x0000: configurable backplane window */ 288 { 289 .win_type = BHNDB_REGWIN_T_DYN, 290 .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET, 291 .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE, 292 .d.dyn = { 293 .cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL 294 }, 295 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 296 }, 297 298 /* bar0+0x1000: sprom shadow */ 299 { 300 .win_type = BHNDB_REGWIN_T_SPROM, 301 .win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET, 302 .win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE, 303 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 304 }, 305 306 /* bar0+0x1800: pci core registers */ 307 { 308 .win_type = BHNDB_REGWIN_T_CORE, 309 .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET, 310 .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE, 311 .d.core = { 312 .class = BHND_DEVCLASS_PCI, 313 .unit = 0, 314 .port = 0, 315 .region = 0, 316 .port_type = BHND_PORT_DEVICE 317 }, 318 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 319 }, 320 BHNDB_REGWIN_TABLE_END 321 }, 322}; 323 324/** 325 * PCI_V1 (PCI-only) hardware configuration (PCI version) 326 * 327 * Applies to: 328 * - PCI (cid=0x804, revision >= 13) 329 */ 330static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = { 331 .resource_specs = (const struct resource_spec[]) { 332 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 333 { -1, 0, 0 } 334 }, 335 336 .register_windows = (const struct bhndb_regwin[]) { 337 /* bar0+0x0000: configurable backplane window */ 338 { 339 .win_type = BHNDB_REGWIN_T_DYN, 340 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 341 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 342 .d.dyn = { 343 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 344 }, 345 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 346 }, 347 348 /* bar0+0x1000: sprom shadow */ 349 { 350 .win_type = BHNDB_REGWIN_T_SPROM, 351 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 352 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 353 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 354 }, 355 356 /* bar0+0x2000: pci core registers */ 357 { 358 .win_type = BHNDB_REGWIN_T_CORE, 359 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 360 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 361 .d.core = { 362 .class = BHND_DEVCLASS_PCI, 363 .unit = 0, 364 .port = 0, 365 .region = 0, 366 .port_type = BHND_PORT_DEVICE 367 }, 368 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 369 }, 370 371 /* bar0+0x3000: chipc core registers */ 372 { 373 .win_type = BHNDB_REGWIN_T_CORE, 374 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 375 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 376 .d.core = { 377 .class = BHND_DEVCLASS_CC, 378 .unit = 0, 379 .port = 0, 380 .region = 0, 381 .port_type = BHND_PORT_DEVICE 382 }, 383 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 384 }, 385 386 BHNDB_REGWIN_TABLE_END 387 }, 388}; 389 390/** 391 * PCI_V1 hardware configuration (PCIE version). 392 * 393 * Applies to: 394 * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 395 */ 396static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = { 397 .resource_specs = (const struct resource_spec[]) { 398 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 399 { -1, 0, 0 } 400 }, 401 402 .register_windows = (const struct bhndb_regwin[]) { 403 /* bar0+0x0000: configurable backplane window */ 404 { 405 .win_type = BHNDB_REGWIN_T_DYN, 406 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 407 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 408 .d.dyn = { 409 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 410 }, 411 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 412 }, 413 414 /* bar0+0x1000: sprom shadow */ 415 { 416 .win_type = BHNDB_REGWIN_T_SPROM, 417 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 418 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 419 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 420 }, 421 422 /* bar0+0x2000: pci core registers */ 423 { 424 .win_type = BHNDB_REGWIN_T_CORE, 425 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 426 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 427 .d.core = { 428 .class = BHND_DEVCLASS_PCIE, 429 .unit = 0, 430 .port = 0, 431 .region = 0, 432 .port_type = BHND_PORT_DEVICE 433 }, 434 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 435 }, 436 437 /* bar0+0x3000: chipc core registers */ 438 { 439 .win_type = BHNDB_REGWIN_T_CORE, 440 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 441 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 442 .d.core = { 443 .class = BHND_DEVCLASS_CC, 444 .unit = 0, 445 .port = 0, 446 .region = 0, 447 .port_type = BHND_PORT_DEVICE 448 }, 449 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 450 }, 451 452 BHNDB_REGWIN_TABLE_END 453 }, 454}; 455 456/** 457 * PCI_V2 hardware configuration. 458 * 459 * Applies to: 460 * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 461 */ 462static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = { 463 .resource_specs = (const struct resource_spec[]) { 464 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 465 { -1, 0, 0 } 466 }, 467 468 .register_windows = (const struct bhndb_regwin[]) { 469 /* bar0+0x0000: configurable backplane window */ 470 { 471 .win_type = BHNDB_REGWIN_T_DYN, 472 .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET, 473 .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE, 474 .d.dyn = { 475 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL, 476 }, 477 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 478 }, 479 480 /* bar0+0x1000: configurable backplane window */ 481 { 482 .win_type = BHNDB_REGWIN_T_DYN, 483 .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET, 484 .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE, 485 .d.dyn = { 486 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL, 487 }, 488 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 489 }, 490 491 /* bar0+0x2000: pcie core registers */ 492 { 493 .win_type = BHNDB_REGWIN_T_CORE, 494 .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET, 495 .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE, 496 .d.core = { 497 .class = BHND_DEVCLASS_PCIE, 498 .unit = 0, 499 .port = 0, 500 .region = 0, 501 .port_type = BHND_PORT_DEVICE 502 }, 503 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 504 }, 505 506 /* bar0+0x3000: chipc core registers */ 507 { 508 .win_type = BHNDB_REGWIN_T_CORE, 509 .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET, 510 .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE, 511 .d.core = { 512 .class = BHND_DEVCLASS_CC, 513 .unit = 0, 514 .port = 0, 515 .region = 0, 516 .port_type = BHND_PORT_DEVICE 517 }, 518 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 519 }, 520 521 BHNDB_REGWIN_TABLE_END 522 }, 523}; 524 525/** 526 * PCI_V3 hardware configuration. 527 * 528 * Applies to: 529 * - PCIE2 (cid=0x83c) 530 */ 531static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = { 532 .resource_specs = (const struct resource_spec[]) { 533 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 534 { -1, 0, 0 } 535 }, 536 537 .register_windows = (const struct bhndb_regwin[]) { 538 /* bar0+0x0000: configurable backplane window */ 539 { 540 .win_type = BHNDB_REGWIN_T_DYN, 541 .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET, 542 .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE, 543 .d.dyn = { 544 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL, 545 }, 546 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 547 }, 548 549 /* bar0+0x1000: configurable backplane window */ 550 { 551 .win_type = BHNDB_REGWIN_T_DYN, 552 .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET, 553 .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE, 554 .d.dyn = { 555 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL, 556 }, 557 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 558 }, 559 560 /* bar0+0x2000: pcie core registers */ 561 { 562 .win_type = BHNDB_REGWIN_T_CORE, 563 .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET, 564 .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE, 565 .d.core = { 566 .class = BHND_DEVCLASS_PCIE, 567 .unit = 0, 568 .port = 0, 569 .region = 0, 570 .port_type = BHND_PORT_DEVICE 571 }, 572 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 573 }, 574 575 /* bar0+0x3000: chipc core registers */ 576 { 577 .win_type = BHNDB_REGWIN_T_CORE, 578 .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET, 579 .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE, 580 .d.core = { 581 .class = BHND_DEVCLASS_CC, 582 .unit = 0, 583 .port = 0, 584 .region = 0, 585 .port_type = BHND_PORT_DEVICE 586 }, 587 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 588 }, 589 590 BHNDB_REGWIN_TABLE_END 591 }, 592}; 593