bhndb_pci_hwdata.c revision 299135
1/*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c 299135 2016-05-05 19:56:18Z adrian $"); 32 33/* 34 * Resource specifications and register maps for Broadcom PCI/PCIe cores 35 * configured as PCI-BHND bridges. 36 */ 37 38#include <sys/param.h> 39#include <sys/bus.h> 40 41#include <machine/bus.h> 42#include <sys/rman.h> 43#include <machine/resource.h> 44 45#include <dev/pci/pcireg.h> 46#include <dev/pci/pcivar.h> 47 48#include "bhndbvar.h" 49#include "bhndb_pcireg.h" 50 51static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; 52static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; 53static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; 54static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; 55static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; 56 57/** 58 * Define a bhndb_hw match entry. 59 * 60 * @param _name The entry name. 61 * @param _vers The configuration version associated with this entry. 62 */ 63#define BHNDB_HW_MATCH(_name, _vers, ...) { \ 64 .name = _name, \ 65 .hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \ 66 .num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \ 67 sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \ 68 .cfg = &bhndb_pci_hwcfg_ ## _vers \ 69} 70 71#define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ } 72 73/** 74 * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based 75 * PCI devices; this configuration is adequate for enumerating a bridged 76 * siba(4) bus to determine the full hardware configuration. 77 * 78 * @par Compatibility 79 * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices. 80 * - Compatible with siba(4) bus enumeration. 81 * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped 82 * at the default enumeration address (0x18000000). 83 */ 84const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = { 85 .resource_specs = (const struct resource_spec[]) { 86 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 87 { -1, 0, 0 } 88 }, 89 90 .register_windows = (const struct bhndb_regwin[]) { 91 /* bar0+0x0000: configurable backplane window */ 92 { 93 .win_type = BHNDB_REGWIN_T_DYN, 94 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 95 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 96 .d.dyn = { 97 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 98 }, 99 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 100 }, 101 BHNDB_REGWIN_TABLE_END 102 }, 103}; 104 105 106/** 107 * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based 108 * PCI devices; this configuration is adequate for enumerating a bridged 109 * bcma(4) bus to determine the full hardware configuration. 110 * 111 * @par Compatibility 112 * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices. 113 * - Compatible with both siba(4) and bcma(4) bus enumeration. 114 */ 115const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = { 116 .resource_specs = (const struct resource_spec[]) { 117 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 118 { -1, 0, 0 } 119 }, 120 121 .register_windows = (const struct bhndb_regwin[]) { 122 /* bar0+0x0000: configurable backplane window */ 123 { 124 .win_type = BHNDB_REGWIN_T_DYN, 125 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 126 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 127 .d.dyn = { 128 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 129 }, 130 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 131 }, 132 133 /* bar0+0x3000: chipc core registers */ 134 { 135 .win_type = BHNDB_REGWIN_T_CORE, 136 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 137 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 138 .d.core = { 139 .class = BHND_DEVCLASS_CC, 140 .unit = 0, 141 .port = 0, 142 .region = 0, 143 .port_type = BHND_PORT_DEVICE 144 }, 145 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 146 }, 147 148 BHNDB_REGWIN_TABLE_END 149 }, 150}; 151 152/** 153 * Hardware configuration tables for Broadcom HND PCI NICs. 154 */ 155const struct bhndb_hw bhndb_pci_generic_hw_table[] = { 156 /* PCI/V0 WLAN */ 157 BHNDB_HW_MATCH("PCI/v0 WLAN", v0, 158 /* PCI Core */ 159 { 160 .vendor = BHND_MFGID_BCM, 161 .device = BHND_COREID_PCI, 162 .hwrev = { 163 .start = 0, 164 .end = BHNDB_PCI_V0_MAX_PCI_HWREV 165 }, 166 .class = BHND_DEVCLASS_PCI, 167 .unit = 0 168 }, 169 170 /* 802.11 Core */ 171 { 172 .vendor = BHND_MFGID_BCM, 173 .device = BHND_COREID_INVALID, 174 .hwrev = { 175 .start = 0, 176 .end = BHND_HWREV_INVALID 177 }, 178 .class = BHND_DEVCLASS_WLAN, 179 .unit = 0 180 } 181 ), 182 183 /* PCI/V1 WLAN */ 184 BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci, 185 /* PCI Core */ 186 { 187 .vendor = BHND_MFGID_BCM, 188 .device = BHND_COREID_PCI, 189 .hwrev = { 190 .start = BHNDB_PCI_V1_MIN_PCI_HWREV, 191 .end = BHND_HWREV_INVALID 192 }, 193 .class = BHND_DEVCLASS_PCI, 194 .unit = 0 195 }, 196 197 /* 802.11 Core */ 198 { 199 .vendor = BHND_MFGID_BCM, 200 .device = BHND_COREID_INVALID, 201 .hwrev = { 202 .start = 0, 203 .end = BHND_HWREV_INVALID 204 }, 205 .class = BHND_DEVCLASS_WLAN, 206 .unit = 0 207 } 208 ), 209 210 /* PCIE/V1 WLAN */ 211 BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie, 212 /* PCIe Core */ 213 { 214 .vendor = BHND_MFGID_BCM, 215 .device = BHND_COREID_PCIE, 216 .hwrev = { 217 .start = 0, 218 .end = BHND_HWREV_INVALID 219 }, 220 .class = BHND_DEVCLASS_PCIE, 221 .unit = 0 222 }, 223 224 /* ChipCommon (revision <= 31) */ 225 { 226 .vendor = BHND_MFGID_BCM, 227 .device = BHND_COREID_CC, 228 .hwrev = { 229 .start = 0, 230 .end = BHNDB_PCI_V1_MAX_CHIPC_HWREV 231 }, 232 .class = BHND_DEVCLASS_CC, 233 .unit = 0 234 }, 235 236 /* 802.11 Core */ 237 { 238 .vendor = BHND_MFGID_BCM, 239 .device = BHND_COREID_INVALID, 240 .hwrev = { 241 .start = 0, 242 .end = BHND_HWREV_INVALID 243 }, 244 .class = BHND_DEVCLASS_WLAN, 245 .unit = 0 246 } 247 ), 248 249 /* PCIE/V2 WLAN */ 250 BHNDB_HW_MATCH("PCIe/v2 WLAN", v2, 251 /* PCIe Core */ 252 { 253 .vendor = BHND_MFGID_BCM, 254 .device = BHND_COREID_PCIE, 255 .hwrev = { 0, BHND_HWREV_INVALID }, 256 .class = BHND_DEVCLASS_PCIE, 257 .unit = 0 258 }, 259 260 /* ChipCommon (revision >= 32) */ 261 { 262 .vendor = BHND_MFGID_BCM, 263 .device = BHND_COREID_CC, 264 .hwrev = { 265 .start = BHNDB_PCI_V2_MIN_CHIPC_HWREV, 266 .end = BHND_HWREV_INVALID 267 }, 268 .class = BHND_DEVCLASS_CC, 269 .unit = 0 270 }, 271 272 /* 802.11 Core */ 273 { 274 .vendor = BHND_MFGID_BCM, 275 .device = BHND_COREID_INVALID, 276 .hwrev = { 277 .start = 0, 278 .end = BHND_HWREV_INVALID 279 }, 280 .class = BHND_DEVCLASS_WLAN, 281 .unit = 0 282 } 283 ), 284 285 286 /* PCIE/V3 WLAN */ 287 BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3, 288 /* PCIe Gen2 Core */ 289 { 290 .vendor = BHND_MFGID_BCM, 291 .device = BHND_COREID_PCIE2, 292 .hwrev = { 293 .start = 0, 294 .end = BHND_HWREV_INVALID 295 }, 296 .class = BHND_DEVCLASS_PCIE, 297 .unit = 0 298 }, 299 300 /* 802.11 Core */ 301 { 302 .vendor = BHND_MFGID_BCM, 303 .device = BHND_COREID_INVALID, 304 .hwrev = { 305 .start = 0, 306 .end = BHND_HWREV_INVALID 307 }, 308 .class = BHND_DEVCLASS_WLAN, 309 .unit = 0 310 } 311 ), 312 313 { NULL, NULL, 0, NULL } 314}; 315 316/** 317 * PCI_V0 hardware configuration. 318 * 319 * Applies to: 320 * - PCI (cid=0x804, revision <= 12) 321 */ 322static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = { 323 .resource_specs = (const struct resource_spec[]) { 324 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 325 { -1, 0, 0 } 326 }, 327 328 .register_windows = (const struct bhndb_regwin[]) { 329 /* bar0+0x0000: configurable backplane window */ 330 { 331 .win_type = BHNDB_REGWIN_T_DYN, 332 .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET, 333 .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE, 334 .d.dyn = { 335 .cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL 336 }, 337 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 338 }, 339 340 /* bar0+0x1000: sprom shadow */ 341 { 342 .win_type = BHNDB_REGWIN_T_SPROM, 343 .win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET, 344 .win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE, 345 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 346 }, 347 348 /* bar0+0x1800: pci core registers */ 349 { 350 .win_type = BHNDB_REGWIN_T_CORE, 351 .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET, 352 .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE, 353 .d.core = { 354 .class = BHND_DEVCLASS_PCI, 355 .unit = 0, 356 .port = 0, 357 .region = 0, 358 .port_type = BHND_PORT_DEVICE 359 }, 360 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 361 }, 362 BHNDB_REGWIN_TABLE_END 363 }, 364}; 365 366/** 367 * PCI_V1 (PCI-only) hardware configuration (PCI version) 368 * 369 * Applies to: 370 * - PCI (cid=0x804, revision >= 13) 371 */ 372static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = { 373 .resource_specs = (const struct resource_spec[]) { 374 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 375 { -1, 0, 0 } 376 }, 377 378 .register_windows = (const struct bhndb_regwin[]) { 379 /* bar0+0x0000: configurable backplane window */ 380 { 381 .win_type = BHNDB_REGWIN_T_DYN, 382 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 383 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 384 .d.dyn = { 385 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 386 }, 387 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 388 }, 389 390 /* bar0+0x1000: sprom shadow */ 391 { 392 .win_type = BHNDB_REGWIN_T_SPROM, 393 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 394 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 395 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 396 }, 397 398 /* bar0+0x2000: pci core registers */ 399 { 400 .win_type = BHNDB_REGWIN_T_CORE, 401 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 402 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 403 .d.core = { 404 .class = BHND_DEVCLASS_PCI, 405 .unit = 0, 406 .port = 0, 407 .region = 0, 408 .port_type = BHND_PORT_DEVICE 409 }, 410 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 411 }, 412 413 /* bar0+0x3000: chipc core registers */ 414 { 415 .win_type = BHNDB_REGWIN_T_CORE, 416 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 417 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 418 .d.core = { 419 .class = BHND_DEVCLASS_CC, 420 .unit = 0, 421 .port = 0, 422 .region = 0, 423 .port_type = BHND_PORT_DEVICE 424 }, 425 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 426 }, 427 428 BHNDB_REGWIN_TABLE_END 429 }, 430}; 431 432/** 433 * PCI_V1 hardware configuration (PCIE version). 434 * 435 * Applies to: 436 * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 437 */ 438static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = { 439 .resource_specs = (const struct resource_spec[]) { 440 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 441 { -1, 0, 0 } 442 }, 443 444 .register_windows = (const struct bhndb_regwin[]) { 445 /* bar0+0x0000: configurable backplane window */ 446 { 447 .win_type = BHNDB_REGWIN_T_DYN, 448 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 449 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 450 .d.dyn = { 451 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 452 }, 453 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 454 }, 455 456 /* bar0+0x1000: sprom shadow */ 457 { 458 .win_type = BHNDB_REGWIN_T_SPROM, 459 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 460 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 461 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 462 }, 463 464 /* bar0+0x2000: pci core registers */ 465 { 466 .win_type = BHNDB_REGWIN_T_CORE, 467 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 468 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 469 .d.core = { 470 .class = BHND_DEVCLASS_PCIE, 471 .unit = 0, 472 .port = 0, 473 .region = 0, 474 .port_type = BHND_PORT_DEVICE 475 }, 476 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 477 }, 478 479 /* bar0+0x3000: chipc core registers */ 480 { 481 .win_type = BHNDB_REGWIN_T_CORE, 482 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 483 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 484 .d.core = { 485 .class = BHND_DEVCLASS_CC, 486 .unit = 0, 487 .port = 0, 488 .region = 0, 489 .port_type = BHND_PORT_DEVICE 490 }, 491 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 492 }, 493 494 BHNDB_REGWIN_TABLE_END 495 }, 496}; 497 498/** 499 * PCI_V2 hardware configuration. 500 * 501 * Applies to: 502 * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 503 */ 504static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = { 505 .resource_specs = (const struct resource_spec[]) { 506 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 507 { -1, 0, 0 } 508 }, 509 510 .register_windows = (const struct bhndb_regwin[]) { 511 /* bar0+0x0000: configurable backplane window */ 512 { 513 .win_type = BHNDB_REGWIN_T_DYN, 514 .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET, 515 .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE, 516 .d.dyn = { 517 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL, 518 }, 519 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 520 }, 521 522 /* bar0+0x1000: configurable backplane window */ 523 { 524 .win_type = BHNDB_REGWIN_T_DYN, 525 .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET, 526 .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE, 527 .d.dyn = { 528 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL, 529 }, 530 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 531 }, 532 533 /* bar0+0x2000: pcie core registers */ 534 { 535 .win_type = BHNDB_REGWIN_T_CORE, 536 .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET, 537 .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE, 538 .d.core = { 539 .class = BHND_DEVCLASS_PCIE, 540 .unit = 0, 541 .port = 0, 542 .region = 0, 543 .port_type = BHND_PORT_DEVICE 544 }, 545 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 546 }, 547 548 /* bar0+0x3000: chipc core registers */ 549 { 550 .win_type = BHNDB_REGWIN_T_CORE, 551 .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET, 552 .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE, 553 .d.core = { 554 .class = BHND_DEVCLASS_CC, 555 .unit = 0, 556 .port = 0, 557 .region = 0, 558 .port_type = BHND_PORT_DEVICE 559 }, 560 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 561 }, 562 563 BHNDB_REGWIN_TABLE_END 564 }, 565}; 566 567/** 568 * PCI_V3 hardware configuration. 569 * 570 * Applies to: 571 * - PCIE2 (cid=0x83c) 572 */ 573static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = { 574 .resource_specs = (const struct resource_spec[]) { 575 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 576 { -1, 0, 0 } 577 }, 578 579 .register_windows = (const struct bhndb_regwin[]) { 580 /* bar0+0x0000: configurable backplane window */ 581 { 582 .win_type = BHNDB_REGWIN_T_DYN, 583 .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET, 584 .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE, 585 .d.dyn = { 586 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL, 587 }, 588 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 589 }, 590 591 /* bar0+0x1000: configurable backplane window */ 592 { 593 .win_type = BHNDB_REGWIN_T_DYN, 594 .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET, 595 .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE, 596 .d.dyn = { 597 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL, 598 }, 599 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 600 }, 601 602 /* bar0+0x2000: pcie core registers */ 603 { 604 .win_type = BHNDB_REGWIN_T_CORE, 605 .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET, 606 .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE, 607 .d.core = { 608 .class = BHND_DEVCLASS_PCIE, 609 .unit = 0, 610 .port = 0, 611 .region = 0, 612 .port_type = BHND_PORT_DEVICE 613 }, 614 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 615 }, 616 617 /* bar0+0x3000: chipc core registers */ 618 { 619 .win_type = BHNDB_REGWIN_T_CORE, 620 .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET, 621 .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE, 622 .d.core = { 623 .class = BHND_DEVCLASS_CC, 624 .unit = 0, 625 .port = 0, 626 .region = 0, 627 .port_type = BHND_PORT_DEVICE 628 }, 629 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 630 }, 631 632 BHNDB_REGWIN_TABLE_END 633 }, 634}; 635