bhndb_pci_hwdata.c revision 296077
1296077Sadrian/*- 2296077Sadrian * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3296077Sadrian * All rights reserved. 4296077Sadrian * 5296077Sadrian * Redistribution and use in source and binary forms, with or without 6296077Sadrian * modification, are permitted provided that the following conditions 7296077Sadrian * are met: 8296077Sadrian * 1. Redistributions of source code must retain the above copyright 9296077Sadrian * notice, this list of conditions and the following disclaimer, 10296077Sadrian * without modification. 11296077Sadrian * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12296077Sadrian * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13296077Sadrian * redistribution must be conditioned upon including a substantially 14296077Sadrian * similar Disclaimer requirement for further binary redistribution. 15296077Sadrian * 16296077Sadrian * NO WARRANTY 17296077Sadrian * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18296077Sadrian * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19296077Sadrian * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20296077Sadrian * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21296077Sadrian * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22296077Sadrian * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23296077Sadrian * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24296077Sadrian * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25296077Sadrian * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26296077Sadrian * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27296077Sadrian * THE POSSIBILITY OF SUCH DAMAGES. 28296077Sadrian */ 29296077Sadrian 30296077Sadrian#include <sys/cdefs.h> 31296077Sadrian__FBSDID("$FreeBSD: head/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c 296077 2016-02-26 03:34:08Z adrian $"); 32296077Sadrian 33296077Sadrian/* 34296077Sadrian * Resource specifications and register maps for Broadcom PCI/PCIe cores 35296077Sadrian * configured as PCI-BHND bridges. 36296077Sadrian */ 37296077Sadrian 38296077Sadrian#include <sys/param.h> 39296077Sadrian#include <sys/bus.h> 40296077Sadrian 41296077Sadrian#include <machine/bus.h> 42296077Sadrian#include <sys/rman.h> 43296077Sadrian#include <machine/resource.h> 44296077Sadrian 45296077Sadrian#include <dev/pci/pcireg.h> 46296077Sadrian#include <dev/pci/pcivar.h> 47296077Sadrian 48296077Sadrian#include "bhndbvar.h" 49296077Sadrian#include "bhndb_pcireg.h" 50296077Sadrian 51296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; 52296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; 53296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; 54296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; 55296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; 56296077Sadrian 57296077Sadrian/** 58296077Sadrian * Define a bhndb_hw match entry. 59296077Sadrian * 60296077Sadrian * @param _name The entry name. 61296077Sadrian * @param _vers The configuration version associated with this entry. 62296077Sadrian */ 63296077Sadrian#define BHNDB_HW_MATCH(_name, _vers, ...) { \ 64296077Sadrian .name = _name, \ 65296077Sadrian .hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \ 66296077Sadrian .num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \ 67296077Sadrian sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \ 68296077Sadrian .cfg = &bhndb_pci_hwcfg_ ## _vers \ 69296077Sadrian} 70296077Sadrian 71296077Sadrian#define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ } 72296077Sadrian 73296077Sadrian/** 74296077Sadrian * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based 75296077Sadrian * PCI devices; this configuration is adequate for enumerating a bridged 76296077Sadrian * siba(4) bus to determine the full hardware configuration. 77296077Sadrian * 78296077Sadrian * @par Compatibility 79296077Sadrian * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices. 80296077Sadrian * - Compatible with siba(4) bus enumeration. 81296077Sadrian * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped 82296077Sadrian * at the default enumeration address (0x18000000). 83296077Sadrian */ 84296077Sadrianconst struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = { 85296077Sadrian .resource_specs = (const struct resource_spec[]) { 86296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 87296077Sadrian { -1, 0, 0 } 88296077Sadrian }, 89296077Sadrian 90296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 91296077Sadrian /* bar0+0x0000: configurable backplane window */ 92296077Sadrian { 93296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 94296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 95296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 96296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 97296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 98296077Sadrian }, 99296077Sadrian BHNDB_REGWIN_TABLE_END 100296077Sadrian }, 101296077Sadrian}; 102296077Sadrian 103296077Sadrian 104296077Sadrian/** 105296077Sadrian * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based 106296077Sadrian * PCI devices; this configuration is adequate for enumerating a bridged 107296077Sadrian * bcma(4) bus to determine the full hardware configuration. 108296077Sadrian * 109296077Sadrian * @par Compatibility 110296077Sadrian * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices. 111296077Sadrian * - Compatible with both siba(4) and bcma(4) bus enumeration. 112296077Sadrian */ 113296077Sadrianconst struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = { 114296077Sadrian .resource_specs = (const struct resource_spec[]) { 115296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 116296077Sadrian { -1, 0, 0 } 117296077Sadrian }, 118296077Sadrian 119296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 120296077Sadrian /* bar0+0x0000: configurable backplane window */ 121296077Sadrian { 122296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 123296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 124296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 125296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 126296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 127296077Sadrian }, 128296077Sadrian 129296077Sadrian /* bar0+0x3000: chipc core registers */ 130296077Sadrian { 131296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 132296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 133296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 134296077Sadrian .core = { 135296077Sadrian .class = BHND_DEVCLASS_CC, 136296077Sadrian .unit = 0, 137296077Sadrian .port = 0, 138296077Sadrian .region = 0, 139296077Sadrian .port_type = BHND_PORT_DEVICE 140296077Sadrian }, 141296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 142296077Sadrian }, 143296077Sadrian 144296077Sadrian BHNDB_REGWIN_TABLE_END 145296077Sadrian }, 146296077Sadrian}; 147296077Sadrian 148296077Sadrian/** 149296077Sadrian * Hardware configuration tables for Broadcom HND PCI NICs. 150296077Sadrian */ 151296077Sadrianconst struct bhndb_hw bhndb_pci_generic_hw_table[] = { 152296077Sadrian /* PCI/V0 WLAN */ 153296077Sadrian BHNDB_HW_MATCH("PCI/v0 WLAN", v0, 154296077Sadrian /* PCI Core */ 155296077Sadrian { 156296077Sadrian .vendor = BHND_MFGID_BCM, 157296077Sadrian .device = BHND_COREID_PCI, 158296077Sadrian .hwrev = { 159296077Sadrian .start = 0, 160296077Sadrian .end = BHNDB_PCI_V0_MAX_PCI_HWREV 161296077Sadrian }, 162296077Sadrian .class = BHND_DEVCLASS_PCI, 163296077Sadrian .unit = 0 164296077Sadrian }, 165296077Sadrian 166296077Sadrian /* 802.11 Core */ 167296077Sadrian { 168296077Sadrian .vendor = BHND_MFGID_BCM, 169296077Sadrian .device = BHND_COREID_INVALID, 170296077Sadrian .hwrev = { 171296077Sadrian .start = 0, 172296077Sadrian .end = BHND_HWREV_INVALID 173296077Sadrian }, 174296077Sadrian .class = BHND_DEVCLASS_WLAN, 175296077Sadrian .unit = 0 176296077Sadrian } 177296077Sadrian ), 178296077Sadrian 179296077Sadrian /* PCI/V1 WLAN */ 180296077Sadrian BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci, 181296077Sadrian /* PCI Core */ 182296077Sadrian { 183296077Sadrian .vendor = BHND_MFGID_BCM, 184296077Sadrian .device = BHND_COREID_PCI, 185296077Sadrian .hwrev = { 186296077Sadrian .start = BHNDB_PCI_V1_MIN_PCI_HWREV, 187296077Sadrian .end = BHND_HWREV_INVALID 188296077Sadrian }, 189296077Sadrian .class = BHND_DEVCLASS_PCI, 190296077Sadrian .unit = 0 191296077Sadrian }, 192296077Sadrian 193296077Sadrian /* 802.11 Core */ 194296077Sadrian { 195296077Sadrian .vendor = BHND_MFGID_BCM, 196296077Sadrian .device = BHND_COREID_INVALID, 197296077Sadrian .hwrev = { 198296077Sadrian .start = 0, 199296077Sadrian .end = BHND_HWREV_INVALID 200296077Sadrian }, 201296077Sadrian .class = BHND_DEVCLASS_WLAN, 202296077Sadrian .unit = 0 203296077Sadrian } 204296077Sadrian ), 205296077Sadrian 206296077Sadrian /* PCIE/V1 WLAN */ 207296077Sadrian BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie, 208296077Sadrian /* PCIe Core */ 209296077Sadrian { 210296077Sadrian .vendor = BHND_MFGID_BCM, 211296077Sadrian .device = BHND_COREID_PCIE, 212296077Sadrian .hwrev = { 213296077Sadrian .start = 0, 214296077Sadrian .end = BHND_HWREV_INVALID 215296077Sadrian }, 216296077Sadrian .class = BHND_DEVCLASS_PCIE, 217296077Sadrian .unit = 0 218296077Sadrian }, 219296077Sadrian 220296077Sadrian /* ChipCommon (revision <= 31) */ 221296077Sadrian { 222296077Sadrian .vendor = BHND_MFGID_BCM, 223296077Sadrian .device = BHND_COREID_CC, 224296077Sadrian .hwrev = { 225296077Sadrian .start = 0, 226296077Sadrian .end = BHNDB_PCI_V1_MAX_CHIPC_HWREV 227296077Sadrian }, 228296077Sadrian .class = BHND_DEVCLASS_CC, 229296077Sadrian .unit = 0 230296077Sadrian }, 231296077Sadrian 232296077Sadrian /* 802.11 Core */ 233296077Sadrian { 234296077Sadrian .vendor = BHND_MFGID_BCM, 235296077Sadrian .device = BHND_COREID_INVALID, 236296077Sadrian .hwrev = { 237296077Sadrian .start = 0, 238296077Sadrian .end = BHND_HWREV_INVALID 239296077Sadrian }, 240296077Sadrian .class = BHND_DEVCLASS_WLAN, 241296077Sadrian .unit = 0 242296077Sadrian } 243296077Sadrian ), 244296077Sadrian 245296077Sadrian /* PCIE/V2 WLAN */ 246296077Sadrian BHNDB_HW_MATCH("PCIe/v2 WLAN", v2, 247296077Sadrian /* PCIe Core */ 248296077Sadrian { 249296077Sadrian .vendor = BHND_MFGID_BCM, 250296077Sadrian .device = BHND_COREID_PCIE, 251296077Sadrian .hwrev = { 0, BHND_HWREV_INVALID }, 252296077Sadrian .class = BHND_DEVCLASS_PCIE, 253296077Sadrian .unit = 0 254296077Sadrian }, 255296077Sadrian 256296077Sadrian /* ChipCommon (revision >= 32) */ 257296077Sadrian { 258296077Sadrian .vendor = BHND_MFGID_BCM, 259296077Sadrian .device = BHND_COREID_CC, 260296077Sadrian .hwrev = { 261296077Sadrian .start = BHNDB_PCI_V2_MIN_CHIPC_HWREV, 262296077Sadrian .end = BHND_HWREV_INVALID 263296077Sadrian }, 264296077Sadrian .class = BHND_DEVCLASS_CC, 265296077Sadrian .unit = 0 266296077Sadrian }, 267296077Sadrian 268296077Sadrian /* 802.11 Core */ 269296077Sadrian { 270296077Sadrian .vendor = BHND_MFGID_BCM, 271296077Sadrian .device = BHND_COREID_INVALID, 272296077Sadrian .hwrev = { 273296077Sadrian .start = 0, 274296077Sadrian .end = BHND_HWREV_INVALID 275296077Sadrian }, 276296077Sadrian .class = BHND_DEVCLASS_WLAN, 277296077Sadrian .unit = 0 278296077Sadrian } 279296077Sadrian ), 280296077Sadrian 281296077Sadrian 282296077Sadrian /* PCIE/V3 WLAN */ 283296077Sadrian BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3, 284296077Sadrian /* PCIe Gen2 Core */ 285296077Sadrian { 286296077Sadrian .vendor = BHND_MFGID_BCM, 287296077Sadrian .device = BHND_COREID_PCIE2, 288296077Sadrian .hwrev = { 289296077Sadrian .start = 0, 290296077Sadrian .end = BHND_HWREV_INVALID 291296077Sadrian }, 292296077Sadrian .class = BHND_DEVCLASS_PCIE, 293296077Sadrian .unit = 0 294296077Sadrian }, 295296077Sadrian 296296077Sadrian /* 802.11 Core */ 297296077Sadrian { 298296077Sadrian .vendor = BHND_MFGID_BCM, 299296077Sadrian .device = BHND_COREID_INVALID, 300296077Sadrian .hwrev = { 301296077Sadrian .start = 0, 302296077Sadrian .end = BHND_HWREV_INVALID 303296077Sadrian }, 304296077Sadrian .class = BHND_DEVCLASS_WLAN, 305296077Sadrian .unit = 0 306296077Sadrian } 307296077Sadrian ), 308296077Sadrian 309296077Sadrian { NULL, NULL, 0, NULL } 310296077Sadrian}; 311296077Sadrian 312296077Sadrian/** 313296077Sadrian * PCI_V0 hardware configuration. 314296077Sadrian * 315296077Sadrian * Applies to: 316296077Sadrian * - PCI (cid=0x804, revision <= 12) 317296077Sadrian */ 318296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = { 319296077Sadrian .resource_specs = (const struct resource_spec[]) { 320296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 321296077Sadrian { -1, 0, 0 } 322296077Sadrian }, 323296077Sadrian 324296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 325296077Sadrian /* bar0+0x0000: configurable backplane window */ 326296077Sadrian { 327296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 328296077Sadrian .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET, 329296077Sadrian .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE, 330296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL, 331296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 332296077Sadrian }, 333296077Sadrian 334296077Sadrian /* bar0+0x1000: sprom shadow */ 335296077Sadrian { 336296077Sadrian .win_type = BHNDB_REGWIN_T_SPROM, 337296077Sadrian .win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET, 338296077Sadrian .win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE, 339296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 340296077Sadrian }, 341296077Sadrian 342296077Sadrian /* bar0+0x1800: pci core registers */ 343296077Sadrian { 344296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 345296077Sadrian .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET, 346296077Sadrian .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE, 347296077Sadrian .core = { 348296077Sadrian .class = BHND_DEVCLASS_PCI, 349296077Sadrian .unit = 0, 350296077Sadrian .port = 0, 351296077Sadrian .region = 0, 352296077Sadrian .port_type = BHND_PORT_DEVICE 353296077Sadrian }, 354296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 355296077Sadrian }, 356296077Sadrian BHNDB_REGWIN_TABLE_END 357296077Sadrian }, 358296077Sadrian}; 359296077Sadrian 360296077Sadrian/** 361296077Sadrian * PCI_V1 (PCI-only) hardware configuration (PCI version) 362296077Sadrian * 363296077Sadrian * Applies to: 364296077Sadrian * - PCI (cid=0x804, revision >= 13) 365296077Sadrian */ 366296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = { 367296077Sadrian .resource_specs = (const struct resource_spec[]) { 368296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 369296077Sadrian { -1, 0, 0 } 370296077Sadrian }, 371296077Sadrian 372296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 373296077Sadrian /* bar0+0x0000: configurable backplane window */ 374296077Sadrian { 375296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 376296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 377296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 378296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 379296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 380296077Sadrian }, 381296077Sadrian 382296077Sadrian /* bar0+0x1000: sprom shadow */ 383296077Sadrian { 384296077Sadrian .win_type = BHNDB_REGWIN_T_SPROM, 385296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 386296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 387296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 388296077Sadrian }, 389296077Sadrian 390296077Sadrian /* bar0+0x2000: pci core registers */ 391296077Sadrian { 392296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 393296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 394296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 395296077Sadrian .core = { 396296077Sadrian .class = BHND_DEVCLASS_PCI, 397296077Sadrian .unit = 0, 398296077Sadrian .port = 0, 399296077Sadrian .region = 0, 400296077Sadrian .port_type = BHND_PORT_DEVICE 401296077Sadrian }, 402296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 403296077Sadrian }, 404296077Sadrian 405296077Sadrian /* bar0+0x3000: chipc core registers */ 406296077Sadrian { 407296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 408296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 409296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 410296077Sadrian .core = { 411296077Sadrian .class = BHND_DEVCLASS_CC, 412296077Sadrian .unit = 0, 413296077Sadrian .port = 0, 414296077Sadrian .region = 0, 415296077Sadrian .port_type = BHND_PORT_DEVICE 416296077Sadrian }, 417296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 418296077Sadrian }, 419296077Sadrian 420296077Sadrian BHNDB_REGWIN_TABLE_END 421296077Sadrian }, 422296077Sadrian}; 423296077Sadrian 424296077Sadrian/** 425296077Sadrian * PCI_V1 hardware configuration (PCIE version). 426296077Sadrian * 427296077Sadrian * Applies to: 428296077Sadrian * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 429296077Sadrian */ 430296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = { 431296077Sadrian .resource_specs = (const struct resource_spec[]) { 432296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 433296077Sadrian { -1, 0, 0 } 434296077Sadrian }, 435296077Sadrian 436296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 437296077Sadrian /* bar0+0x0000: configurable backplane window */ 438296077Sadrian { 439296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 440296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 441296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 442296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 443296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 444296077Sadrian }, 445296077Sadrian 446296077Sadrian /* bar0+0x1000: sprom shadow */ 447296077Sadrian { 448296077Sadrian .win_type = BHNDB_REGWIN_T_SPROM, 449296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 450296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 451296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 452296077Sadrian }, 453296077Sadrian 454296077Sadrian /* bar0+0x2000: pci core registers */ 455296077Sadrian { 456296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 457296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 458296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 459296077Sadrian .core = { 460296077Sadrian .class = BHND_DEVCLASS_PCIE, 461296077Sadrian .unit = 0, 462296077Sadrian .port = 0, 463296077Sadrian .region = 0, 464296077Sadrian .port_type = BHND_PORT_DEVICE 465296077Sadrian }, 466296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 467296077Sadrian }, 468296077Sadrian 469296077Sadrian /* bar0+0x3000: chipc core registers */ 470296077Sadrian { 471296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 472296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 473296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 474296077Sadrian .core = { 475296077Sadrian .class = BHND_DEVCLASS_CC, 476296077Sadrian .unit = 0, 477296077Sadrian .port = 0, 478296077Sadrian .region = 0, 479296077Sadrian .port_type = BHND_PORT_DEVICE 480296077Sadrian }, 481296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 482296077Sadrian }, 483296077Sadrian 484296077Sadrian BHNDB_REGWIN_TABLE_END 485296077Sadrian }, 486296077Sadrian}; 487296077Sadrian 488296077Sadrian/** 489296077Sadrian * PCI_V2 hardware configuration. 490296077Sadrian * 491296077Sadrian * Applies to: 492296077Sadrian * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 493296077Sadrian */ 494296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = { 495296077Sadrian .resource_specs = (const struct resource_spec[]) { 496296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 497296077Sadrian { -1, 0, 0 } 498296077Sadrian }, 499296077Sadrian 500296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 501296077Sadrian /* bar0+0x0000: configurable backplane window */ 502296077Sadrian { 503296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 504296077Sadrian .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET, 505296077Sadrian .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE, 506296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL, 507296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 508296077Sadrian }, 509296077Sadrian 510296077Sadrian /* bar0+0x1000: configurable backplane window */ 511296077Sadrian { 512296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 513296077Sadrian .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET, 514296077Sadrian .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE, 515296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL, 516296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 517296077Sadrian }, 518296077Sadrian 519296077Sadrian /* bar0+0x2000: pcie core registers */ 520296077Sadrian { 521296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 522296077Sadrian .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET, 523296077Sadrian .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE, 524296077Sadrian .core = { 525296077Sadrian .class = BHND_DEVCLASS_PCIE, 526296077Sadrian .unit = 0, 527296077Sadrian .port = 0, 528296077Sadrian .region = 0, 529296077Sadrian .port_type = BHND_PORT_DEVICE 530296077Sadrian }, 531296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 532296077Sadrian }, 533296077Sadrian 534296077Sadrian /* bar0+0x3000: chipc core registers */ 535296077Sadrian { 536296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 537296077Sadrian .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET, 538296077Sadrian .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE, 539296077Sadrian .core = { 540296077Sadrian .class = BHND_DEVCLASS_CC, 541296077Sadrian .unit = 0, 542296077Sadrian .port = 0, 543296077Sadrian .region = 0, 544296077Sadrian .port_type = BHND_PORT_DEVICE 545296077Sadrian }, 546296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 547296077Sadrian }, 548296077Sadrian 549296077Sadrian BHNDB_REGWIN_TABLE_END 550296077Sadrian }, 551296077Sadrian}; 552296077Sadrian 553296077Sadrian/** 554296077Sadrian * PCI_V3 hardware configuration. 555296077Sadrian * 556296077Sadrian * Applies to: 557296077Sadrian * - PCIE2 (cid=0x83c) 558296077Sadrian */ 559296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = { 560296077Sadrian .resource_specs = (const struct resource_spec[]) { 561296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 562296077Sadrian { -1, 0, 0 } 563296077Sadrian }, 564296077Sadrian 565296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 566296077Sadrian /* bar0+0x0000: configurable backplane window */ 567296077Sadrian { 568296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 569296077Sadrian .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET, 570296077Sadrian .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE, 571296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL, 572296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 573296077Sadrian }, 574296077Sadrian 575296077Sadrian /* bar0+0x1000: configurable backplane window */ 576296077Sadrian { 577296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 578296077Sadrian .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET, 579296077Sadrian .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE, 580296077Sadrian .dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL, 581296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 582296077Sadrian }, 583296077Sadrian 584296077Sadrian /* bar0+0x2000: pcie core registers */ 585296077Sadrian { 586296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 587296077Sadrian .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET, 588296077Sadrian .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE, 589296077Sadrian .core = { 590296077Sadrian .class = BHND_DEVCLASS_PCIE, 591296077Sadrian .unit = 0, 592296077Sadrian .port = 0, 593296077Sadrian .region = 0, 594296077Sadrian .port_type = BHND_PORT_DEVICE 595296077Sadrian }, 596296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 597296077Sadrian }, 598296077Sadrian 599296077Sadrian /* bar0+0x3000: chipc core registers */ 600296077Sadrian { 601296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 602296077Sadrian .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET, 603296077Sadrian .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE, 604296077Sadrian .core = { 605296077Sadrian .class = BHND_DEVCLASS_CC, 606296077Sadrian .unit = 0, 607296077Sadrian .port = 0, 608296077Sadrian .region = 0, 609296077Sadrian .port_type = BHND_PORT_DEVICE 610296077Sadrian }, 611296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 612296077Sadrian }, 613296077Sadrian 614296077Sadrian BHNDB_REGWIN_TABLE_END 615296077Sadrian }, 616296077Sadrian}; 617