1296077Sadrian/*- 2296077Sadrian * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3296077Sadrian * All rights reserved. 4296077Sadrian * 5296077Sadrian * Redistribution and use in source and binary forms, with or without 6296077Sadrian * modification, are permitted provided that the following conditions 7296077Sadrian * are met: 8296077Sadrian * 1. Redistributions of source code must retain the above copyright 9296077Sadrian * notice, this list of conditions and the following disclaimer, 10296077Sadrian * without modification. 11296077Sadrian * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12296077Sadrian * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13296077Sadrian * redistribution must be conditioned upon including a substantially 14296077Sadrian * similar Disclaimer requirement for further binary redistribution. 15296077Sadrian * 16296077Sadrian * NO WARRANTY 17296077Sadrian * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18296077Sadrian * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19296077Sadrian * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20296077Sadrian * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21296077Sadrian * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22296077Sadrian * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23296077Sadrian * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24296077Sadrian * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25296077Sadrian * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26296077Sadrian * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27296077Sadrian * THE POSSIBILITY OF SUCH DAMAGES. 28296077Sadrian */ 29296077Sadrian 30296077Sadrian#include <sys/cdefs.h> 31296077Sadrian__FBSDID("$FreeBSD: releng/11.0/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c 300628 2016-05-24 21:20:17Z adrian $"); 32296077Sadrian 33296077Sadrian/* 34296077Sadrian * Resource specifications and register maps for Broadcom PCI/PCIe cores 35296077Sadrian * configured as PCI-BHND bridges. 36296077Sadrian */ 37296077Sadrian 38296077Sadrian#include <sys/param.h> 39296077Sadrian#include <sys/bus.h> 40296077Sadrian 41296077Sadrian#include <machine/bus.h> 42296077Sadrian#include <sys/rman.h> 43296077Sadrian#include <machine/resource.h> 44296077Sadrian 45296077Sadrian#include <dev/pci/pcireg.h> 46296077Sadrian#include <dev/pci/pcivar.h> 47296077Sadrian 48296077Sadrian#include "bhndbvar.h" 49296077Sadrian#include "bhndb_pcireg.h" 50296077Sadrian 51296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; 52296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; 53296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; 54296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; 55296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; 56296077Sadrian 57296077Sadrian/** 58296077Sadrian * Define a bhndb_hw match entry. 59296077Sadrian * 60296077Sadrian * @param _name The entry name. 61296077Sadrian * @param _vers The configuration version associated with this entry. 62296077Sadrian */ 63296077Sadrian#define BHNDB_HW_MATCH(_name, _vers, ...) { \ 64296077Sadrian .name = _name, \ 65296077Sadrian .hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \ 66296077Sadrian .num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \ 67296077Sadrian sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \ 68296077Sadrian .cfg = &bhndb_pci_hwcfg_ ## _vers \ 69296077Sadrian} 70296077Sadrian 71296077Sadrian#define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ } 72296077Sadrian 73296077Sadrian/** 74296077Sadrian * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based 75296077Sadrian * PCI devices; this configuration is adequate for enumerating a bridged 76296077Sadrian * siba(4) bus to determine the full hardware configuration. 77296077Sadrian * 78296077Sadrian * @par Compatibility 79296077Sadrian * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices. 80296077Sadrian * - Compatible with siba(4) bus enumeration. 81296077Sadrian * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped 82296077Sadrian * at the default enumeration address (0x18000000). 83296077Sadrian */ 84296077Sadrianconst struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = { 85296077Sadrian .resource_specs = (const struct resource_spec[]) { 86296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 87296077Sadrian { -1, 0, 0 } 88296077Sadrian }, 89296077Sadrian 90296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 91296077Sadrian /* bar0+0x0000: configurable backplane window */ 92296077Sadrian { 93296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 94296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 95296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 96299135Sadrian .d.dyn = { 97299135Sadrian .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 98299135Sadrian }, 99296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 100296077Sadrian }, 101296077Sadrian BHNDB_REGWIN_TABLE_END 102296077Sadrian }, 103296077Sadrian}; 104296077Sadrian 105296077Sadrian 106296077Sadrian/** 107296077Sadrian * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based 108296077Sadrian * PCI devices; this configuration is adequate for enumerating a bridged 109296077Sadrian * bcma(4) bus to determine the full hardware configuration. 110296077Sadrian * 111296077Sadrian * @par Compatibility 112296077Sadrian * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices. 113296077Sadrian * - Compatible with both siba(4) and bcma(4) bus enumeration. 114296077Sadrian */ 115296077Sadrianconst struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = { 116296077Sadrian .resource_specs = (const struct resource_spec[]) { 117296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 118296077Sadrian { -1, 0, 0 } 119296077Sadrian }, 120296077Sadrian 121296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 122296077Sadrian /* bar0+0x0000: configurable backplane window */ 123296077Sadrian { 124296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 125296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 126296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 127299135Sadrian .d.dyn = { 128299135Sadrian .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 129299135Sadrian }, 130296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 131296077Sadrian }, 132296077Sadrian 133296077Sadrian /* bar0+0x3000: chipc core registers */ 134296077Sadrian { 135296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 136296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 137296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 138299135Sadrian .d.core = { 139296077Sadrian .class = BHND_DEVCLASS_CC, 140296077Sadrian .unit = 0, 141296077Sadrian .port = 0, 142296077Sadrian .region = 0, 143296077Sadrian .port_type = BHND_PORT_DEVICE 144296077Sadrian }, 145296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 146296077Sadrian }, 147296077Sadrian 148296077Sadrian BHNDB_REGWIN_TABLE_END 149296077Sadrian }, 150296077Sadrian}; 151296077Sadrian 152296077Sadrian/** 153296077Sadrian * Hardware configuration tables for Broadcom HND PCI NICs. 154296077Sadrian */ 155296077Sadrianconst struct bhndb_hw bhndb_pci_generic_hw_table[] = { 156296077Sadrian /* PCI/V0 WLAN */ 157296077Sadrian BHNDB_HW_MATCH("PCI/v0 WLAN", v0, 158296077Sadrian /* PCI Core */ 159296077Sadrian { 160300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 161300628Sadrian BHND_MATCH_CORE_ID (BHND_COREID_PCI), 162300628Sadrian BHND_MATCH_CORE_REV( 163300628Sadrian HWREV_LTE (BHNDB_PCI_V0_MAX_PCI_HWREV)), 164300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI), 165300628Sadrian BHND_MATCH_CORE_UNIT (0) 166296077Sadrian }, 167296077Sadrian 168296077Sadrian /* 802.11 Core */ 169296077Sadrian { 170300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 171300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 172300628Sadrian BHND_MATCH_CORE_UNIT (0) 173296077Sadrian } 174296077Sadrian ), 175296077Sadrian 176296077Sadrian /* PCI/V1 WLAN */ 177296077Sadrian BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci, 178296077Sadrian /* PCI Core */ 179296077Sadrian { 180300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 181300628Sadrian BHND_MATCH_CORE_ID (BHND_COREID_PCI), 182300628Sadrian BHND_MATCH_CORE_REV( 183300628Sadrian HWREV_GTE (BHNDB_PCI_V1_MIN_PCI_HWREV)), 184300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI), 185300628Sadrian BHND_MATCH_CORE_UNIT (0) 186296077Sadrian }, 187296077Sadrian 188296077Sadrian /* 802.11 Core */ 189296077Sadrian { 190300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 191300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 192300628Sadrian BHND_MATCH_CORE_UNIT (0) 193296077Sadrian } 194296077Sadrian ), 195296077Sadrian 196296077Sadrian /* PCIE/V1 WLAN */ 197296077Sadrian BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie, 198296077Sadrian /* PCIe Core */ 199296077Sadrian { 200300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 201300628Sadrian BHND_MATCH_CORE_ID (BHND_COREID_PCIE), 202300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 203300628Sadrian BHND_MATCH_CORE_UNIT (0) 204296077Sadrian }, 205296077Sadrian 206296077Sadrian /* ChipCommon (revision <= 31) */ 207296077Sadrian { 208300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 209300628Sadrian BHND_MATCH_CORE_ID (BHND_COREID_CC), 210300628Sadrian BHND_MATCH_CORE_REV( 211300628Sadrian HWREV_LTE (BHNDB_PCI_V1_MAX_CHIPC_HWREV)), 212300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC), 213300628Sadrian BHND_MATCH_CORE_UNIT (0) 214296077Sadrian }, 215296077Sadrian 216296077Sadrian /* 802.11 Core */ 217296077Sadrian { 218300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 219300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 220300628Sadrian BHND_MATCH_CORE_UNIT (0) 221296077Sadrian } 222296077Sadrian ), 223296077Sadrian 224296077Sadrian /* PCIE/V2 WLAN */ 225296077Sadrian BHNDB_HW_MATCH("PCIe/v2 WLAN", v2, 226296077Sadrian /* PCIe Core */ 227296077Sadrian { 228300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 229300628Sadrian BHND_MATCH_CORE_ID (BHND_COREID_PCIE), 230300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 231300628Sadrian BHND_MATCH_CORE_UNIT (0) 232296077Sadrian }, 233296077Sadrian 234296077Sadrian /* ChipCommon (revision >= 32) */ 235296077Sadrian { 236300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 237300628Sadrian BHND_MATCH_CORE_ID (BHND_COREID_CC), 238300628Sadrian BHND_MATCH_CORE_REV( 239300628Sadrian HWREV_GTE (BHNDB_PCI_V2_MIN_CHIPC_HWREV)), 240300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC), 241300628Sadrian BHND_MATCH_CORE_UNIT (0) 242296077Sadrian }, 243296077Sadrian 244296077Sadrian /* 802.11 Core */ 245296077Sadrian { 246300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 247300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 248300628Sadrian BHND_MATCH_CORE_UNIT (0) 249296077Sadrian } 250296077Sadrian ), 251296077Sadrian 252296077Sadrian 253296077Sadrian /* PCIE/V3 WLAN */ 254296077Sadrian BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3, 255296077Sadrian /* PCIe Gen2 Core */ 256296077Sadrian { 257300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 258300628Sadrian BHND_MATCH_CORE_ID (BHND_COREID_PCIE2), 259300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 260300628Sadrian BHND_MATCH_CORE_UNIT (0) 261296077Sadrian }, 262296077Sadrian 263296077Sadrian /* 802.11 Core */ 264296077Sadrian { 265300628Sadrian BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 266300628Sadrian BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 267300628Sadrian BHND_MATCH_CORE_UNIT (0) 268296077Sadrian } 269296077Sadrian ), 270296077Sadrian 271296077Sadrian { NULL, NULL, 0, NULL } 272296077Sadrian}; 273296077Sadrian 274296077Sadrian/** 275296077Sadrian * PCI_V0 hardware configuration. 276296077Sadrian * 277296077Sadrian * Applies to: 278296077Sadrian * - PCI (cid=0x804, revision <= 12) 279296077Sadrian */ 280296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = { 281296077Sadrian .resource_specs = (const struct resource_spec[]) { 282296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 283296077Sadrian { -1, 0, 0 } 284296077Sadrian }, 285296077Sadrian 286296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 287296077Sadrian /* bar0+0x0000: configurable backplane window */ 288296077Sadrian { 289296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 290296077Sadrian .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET, 291296077Sadrian .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE, 292299135Sadrian .d.dyn = { 293299135Sadrian .cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL 294299135Sadrian }, 295296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 296296077Sadrian }, 297296077Sadrian 298296077Sadrian /* bar0+0x1000: sprom shadow */ 299296077Sadrian { 300296077Sadrian .win_type = BHNDB_REGWIN_T_SPROM, 301296077Sadrian .win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET, 302296077Sadrian .win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE, 303296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 304296077Sadrian }, 305296077Sadrian 306296077Sadrian /* bar0+0x1800: pci core registers */ 307296077Sadrian { 308296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 309296077Sadrian .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET, 310296077Sadrian .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE, 311299135Sadrian .d.core = { 312296077Sadrian .class = BHND_DEVCLASS_PCI, 313296077Sadrian .unit = 0, 314296077Sadrian .port = 0, 315296077Sadrian .region = 0, 316296077Sadrian .port_type = BHND_PORT_DEVICE 317296077Sadrian }, 318296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 319296077Sadrian }, 320296077Sadrian BHNDB_REGWIN_TABLE_END 321296077Sadrian }, 322296077Sadrian}; 323296077Sadrian 324296077Sadrian/** 325296077Sadrian * PCI_V1 (PCI-only) hardware configuration (PCI version) 326296077Sadrian * 327296077Sadrian * Applies to: 328296077Sadrian * - PCI (cid=0x804, revision >= 13) 329296077Sadrian */ 330296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = { 331296077Sadrian .resource_specs = (const struct resource_spec[]) { 332296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 333296077Sadrian { -1, 0, 0 } 334296077Sadrian }, 335296077Sadrian 336296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 337296077Sadrian /* bar0+0x0000: configurable backplane window */ 338296077Sadrian { 339296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 340296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 341296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 342299135Sadrian .d.dyn = { 343299135Sadrian .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 344299135Sadrian }, 345296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 346296077Sadrian }, 347296077Sadrian 348296077Sadrian /* bar0+0x1000: sprom shadow */ 349296077Sadrian { 350296077Sadrian .win_type = BHNDB_REGWIN_T_SPROM, 351296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 352296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 353296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 354296077Sadrian }, 355296077Sadrian 356296077Sadrian /* bar0+0x2000: pci core registers */ 357296077Sadrian { 358296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 359296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 360296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 361299135Sadrian .d.core = { 362296077Sadrian .class = BHND_DEVCLASS_PCI, 363296077Sadrian .unit = 0, 364296077Sadrian .port = 0, 365296077Sadrian .region = 0, 366296077Sadrian .port_type = BHND_PORT_DEVICE 367296077Sadrian }, 368296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 369296077Sadrian }, 370296077Sadrian 371296077Sadrian /* bar0+0x3000: chipc core registers */ 372296077Sadrian { 373296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 374296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 375296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 376299135Sadrian .d.core = { 377296077Sadrian .class = BHND_DEVCLASS_CC, 378296077Sadrian .unit = 0, 379296077Sadrian .port = 0, 380296077Sadrian .region = 0, 381296077Sadrian .port_type = BHND_PORT_DEVICE 382296077Sadrian }, 383296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 384296077Sadrian }, 385296077Sadrian 386296077Sadrian BHNDB_REGWIN_TABLE_END 387296077Sadrian }, 388296077Sadrian}; 389296077Sadrian 390296077Sadrian/** 391296077Sadrian * PCI_V1 hardware configuration (PCIE version). 392296077Sadrian * 393296077Sadrian * Applies to: 394296077Sadrian * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 395296077Sadrian */ 396296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = { 397296077Sadrian .resource_specs = (const struct resource_spec[]) { 398296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 399296077Sadrian { -1, 0, 0 } 400296077Sadrian }, 401296077Sadrian 402296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 403296077Sadrian /* bar0+0x0000: configurable backplane window */ 404296077Sadrian { 405296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 406296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 407296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 408299135Sadrian .d.dyn = { 409299135Sadrian .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 410299135Sadrian }, 411296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 412296077Sadrian }, 413296077Sadrian 414296077Sadrian /* bar0+0x1000: sprom shadow */ 415296077Sadrian { 416296077Sadrian .win_type = BHNDB_REGWIN_T_SPROM, 417296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 418296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 419296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 420296077Sadrian }, 421296077Sadrian 422296077Sadrian /* bar0+0x2000: pci core registers */ 423296077Sadrian { 424296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 425296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 426296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 427299135Sadrian .d.core = { 428296077Sadrian .class = BHND_DEVCLASS_PCIE, 429296077Sadrian .unit = 0, 430296077Sadrian .port = 0, 431296077Sadrian .region = 0, 432296077Sadrian .port_type = BHND_PORT_DEVICE 433296077Sadrian }, 434296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 435296077Sadrian }, 436296077Sadrian 437296077Sadrian /* bar0+0x3000: chipc core registers */ 438296077Sadrian { 439296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 440296077Sadrian .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 441296077Sadrian .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 442299135Sadrian .d.core = { 443296077Sadrian .class = BHND_DEVCLASS_CC, 444296077Sadrian .unit = 0, 445296077Sadrian .port = 0, 446296077Sadrian .region = 0, 447296077Sadrian .port_type = BHND_PORT_DEVICE 448296077Sadrian }, 449296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 450296077Sadrian }, 451296077Sadrian 452296077Sadrian BHNDB_REGWIN_TABLE_END 453296077Sadrian }, 454296077Sadrian}; 455296077Sadrian 456296077Sadrian/** 457296077Sadrian * PCI_V2 hardware configuration. 458296077Sadrian * 459296077Sadrian * Applies to: 460296077Sadrian * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 461296077Sadrian */ 462296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = { 463296077Sadrian .resource_specs = (const struct resource_spec[]) { 464296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 465296077Sadrian { -1, 0, 0 } 466296077Sadrian }, 467296077Sadrian 468296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 469296077Sadrian /* bar0+0x0000: configurable backplane window */ 470296077Sadrian { 471296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 472296077Sadrian .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET, 473296077Sadrian .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE, 474299135Sadrian .d.dyn = { 475299135Sadrian .cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL, 476299135Sadrian }, 477296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 478296077Sadrian }, 479296077Sadrian 480296077Sadrian /* bar0+0x1000: configurable backplane window */ 481296077Sadrian { 482296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 483296077Sadrian .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET, 484296077Sadrian .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE, 485299135Sadrian .d.dyn = { 486299135Sadrian .cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL, 487299135Sadrian }, 488296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 489296077Sadrian }, 490296077Sadrian 491296077Sadrian /* bar0+0x2000: pcie core registers */ 492296077Sadrian { 493296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 494296077Sadrian .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET, 495296077Sadrian .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE, 496299135Sadrian .d.core = { 497296077Sadrian .class = BHND_DEVCLASS_PCIE, 498296077Sadrian .unit = 0, 499296077Sadrian .port = 0, 500296077Sadrian .region = 0, 501296077Sadrian .port_type = BHND_PORT_DEVICE 502296077Sadrian }, 503296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 504296077Sadrian }, 505296077Sadrian 506296077Sadrian /* bar0+0x3000: chipc core registers */ 507296077Sadrian { 508296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 509296077Sadrian .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET, 510296077Sadrian .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE, 511299135Sadrian .d.core = { 512296077Sadrian .class = BHND_DEVCLASS_CC, 513296077Sadrian .unit = 0, 514296077Sadrian .port = 0, 515296077Sadrian .region = 0, 516296077Sadrian .port_type = BHND_PORT_DEVICE 517296077Sadrian }, 518296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 519296077Sadrian }, 520296077Sadrian 521296077Sadrian BHNDB_REGWIN_TABLE_END 522296077Sadrian }, 523296077Sadrian}; 524296077Sadrian 525296077Sadrian/** 526296077Sadrian * PCI_V3 hardware configuration. 527296077Sadrian * 528296077Sadrian * Applies to: 529296077Sadrian * - PCIE2 (cid=0x83c) 530296077Sadrian */ 531296077Sadrianstatic const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = { 532296077Sadrian .resource_specs = (const struct resource_spec[]) { 533296077Sadrian { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 534296077Sadrian { -1, 0, 0 } 535296077Sadrian }, 536296077Sadrian 537296077Sadrian .register_windows = (const struct bhndb_regwin[]) { 538296077Sadrian /* bar0+0x0000: configurable backplane window */ 539296077Sadrian { 540296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 541296077Sadrian .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET, 542296077Sadrian .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE, 543299135Sadrian .d.dyn = { 544299135Sadrian .cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL, 545299135Sadrian }, 546296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 547296077Sadrian }, 548296077Sadrian 549296077Sadrian /* bar0+0x1000: configurable backplane window */ 550296077Sadrian { 551296077Sadrian .win_type = BHNDB_REGWIN_T_DYN, 552296077Sadrian .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET, 553296077Sadrian .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE, 554299135Sadrian .d.dyn = { 555299135Sadrian .cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL, 556299135Sadrian }, 557296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 558296077Sadrian }, 559296077Sadrian 560296077Sadrian /* bar0+0x2000: pcie core registers */ 561296077Sadrian { 562296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 563296077Sadrian .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET, 564296077Sadrian .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE, 565299135Sadrian .d.core = { 566296077Sadrian .class = BHND_DEVCLASS_PCIE, 567296077Sadrian .unit = 0, 568296077Sadrian .port = 0, 569296077Sadrian .region = 0, 570296077Sadrian .port_type = BHND_PORT_DEVICE 571296077Sadrian }, 572296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 573296077Sadrian }, 574296077Sadrian 575296077Sadrian /* bar0+0x3000: chipc core registers */ 576296077Sadrian { 577296077Sadrian .win_type = BHNDB_REGWIN_T_CORE, 578296077Sadrian .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET, 579296077Sadrian .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE, 580299135Sadrian .d.core = { 581296077Sadrian .class = BHND_DEVCLASS_CC, 582296077Sadrian .unit = 0, 583296077Sadrian .port = 0, 584296077Sadrian .region = 0, 585296077Sadrian .port_type = BHND_PORT_DEVICE 586296077Sadrian }, 587296077Sadrian .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 588296077Sadrian }, 589296077Sadrian 590296077Sadrian BHNDB_REGWIN_TABLE_END 591296077Sadrian }, 592296077Sadrian}; 593