if_bgereg.h revision 84059
184059Swpaul/* 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 84059 2001-09-27 23:55:28Z wpaul $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 6484059Swpaul#define BGE_PAGE_ZERO 0x00000000 6584059Swpaul#define BGE_PAGE_ZERO_END 0x000000FF 6684059Swpaul#define BGE_SEND_RING_RCB 0x00000100 6784059Swpaul#define BGE_SEND_RING_RCB_END 0x000001FF 6884059Swpaul#define BGE_RX_RETURN_RING_RCB 0x00000200 6984059Swpaul#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 7084059Swpaul#define BGE_STATS_BLOCK 0x00000300 7184059Swpaul#define BGE_STATS_BLOCK_END 0x00000AFF 7284059Swpaul#define BGE_STATUS_BLOCK 0x00000B00 7384059Swpaul#define BGE_STATUS_BLOCK_END 0x00000B4F 7484059Swpaul#define BGE_SOFTWARE_GENCOMM 0x00000B50 7584059Swpaul#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 7684059Swpaul#define BGE_UNMAPPED 0x00001000 7784059Swpaul#define BGE_UNMAPPED_END 0x00001FFF 7884059Swpaul#define BGE_DMA_DESCRIPTORS 0x00002000 7984059Swpaul#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 8084059Swpaul#define BGE_SEND_RING_1_TO_4 0x00004000 8184059Swpaul#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8284059Swpaul 8384059Swpaul/* Mappings for internal memory configuration */ 8484059Swpaul#define BGE_STD_RX_RINGS 0x00006000 8584059Swpaul#define BGE_STD_RX_RINGS_END 0x00006FFF 8684059Swpaul#define BGE_JUMBO_RX_RINGS 0x00007000 8784059Swpaul#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 8884059Swpaul#define BGE_BUFFPOOL_1 0x00008000 8984059Swpaul#define BGE_BUFFPOOL_1_END 0x0000FFFF 9084059Swpaul#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 9184059Swpaul#define BGE_BUFFPOOL_2_END 0x00017FFF 9284059Swpaul#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 9384059Swpaul#define BGE_BUFFPOOL_3_END 0x0001FFFF 9484059Swpaul 9584059Swpaul/* Mappings for external SSRAM configurations */ 9684059Swpaul#define BGE_SEND_RING_5_TO_6 0x00006000 9784059Swpaul#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 9884059Swpaul#define BGE_SEND_RING_7_TO_8 0x00007000 9984059Swpaul#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 10084059Swpaul#define BGE_SEND_RING_9_TO_16 0x00008000 10184059Swpaul#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 10284059Swpaul#define BGE_EXT_STD_RX_RINGS 0x0000C000 10384059Swpaul#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 10484059Swpaul#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 10584059Swpaul#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 10684059Swpaul#define BGE_MINI_RX_RINGS 0x0000E000 10784059Swpaul#define BGE_MINI_RX_RINGS_END 0x0000FFFF 10884059Swpaul#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 10984059Swpaul#define BGE_AVAIL_REGION1_END 0x00017FFF 11084059Swpaul#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 11184059Swpaul#define BGE_AVAIL_REGION2_END 0x0001FFFF 11284059Swpaul#define BGE_EXT_SSRAM 0x00020000 11384059Swpaul#define BGE_EXT_SSRAM_END 0x000FFFFF 11484059Swpaul 11584059Swpaul 11684059Swpaul/* 11784059Swpaul * BCM570x register offsets. These are memory mapped registers 11884059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 11984059Swpaul * Each register must be accessed using 32 bit operations. 12084059Swpaul * 12184059Swpaul * All registers are accessed through a 32K shared memory block. 12284059Swpaul * The first group of registers are actually copies of the PCI 12384059Swpaul * configuration space registers. 12484059Swpaul */ 12584059Swpaul 12684059Swpaul/* 12784059Swpaul * PCI registers defined in the PCI 2.2 spec. 12884059Swpaul */ 12984059Swpaul#define BGE_PCI_VID 0x00 13084059Swpaul#define BGE_PCI_DID 0x02 13184059Swpaul#define BGE_PCI_CMD 0x04 13284059Swpaul#define BGE_PCI_STS 0x06 13384059Swpaul#define BGE_PCI_REV 0x08 13484059Swpaul#define BGE_PCI_CLASS 0x09 13584059Swpaul#define BGE_PCI_CACHESZ 0x0C 13684059Swpaul#define BGE_PCI_LATTIMER 0x0D 13784059Swpaul#define BGE_PCI_HDRTYPE 0x0E 13884059Swpaul#define BGE_PCI_BIST 0x0F 13984059Swpaul#define BGE_PCI_BAR0 0x10 14084059Swpaul#define BGE_PCI_BAR1 0x14 14184059Swpaul#define BGE_PCI_SUBSYS 0x2C 14284059Swpaul#define BGE_PCI_SUBVID 0x2E 14384059Swpaul#define BGE_PCI_ROMBASE 0x30 14484059Swpaul#define BGE_PCI_CAPPTR 0x34 14584059Swpaul#define BGE_PCI_INTLINE 0x3C 14684059Swpaul#define BGE_PCI_INTPIN 0x3D 14784059Swpaul#define BGE_PCI_MINGNT 0x3E 14884059Swpaul#define BGE_PCI_MAXLAT 0x3F 14984059Swpaul#define BGE_PCI_PCIXCAP 0x40 15084059Swpaul#define BGE_PCI_NEXTPTR_PM 0x41 15184059Swpaul#define BGE_PCI_PCIX_CMD 0x42 15284059Swpaul#define BGE_PCI_PCIX_STS 0x44 15384059Swpaul#define BGE_PCI_PWRMGMT_CAPID 0x48 15484059Swpaul#define BGE_PCI_NEXTPTR_VPD 0x49 15584059Swpaul#define BGE_PCI_PWRMGMT_CAPS 0x4A 15684059Swpaul#define BGE_PCI_PWRMGMT_CMD 0x4C 15784059Swpaul#define BGE_PCI_PWRMGMT_STS 0x4D 15884059Swpaul#define BGE_PCI_PWRMGMT_DATA 0x4F 15984059Swpaul#define BGE_PCI_VPD_CAPID 0x50 16084059Swpaul#define BGE_PCI_NEXTPTR_MSI 0x51 16184059Swpaul#define BGE_PCI_VPD_ADDR 0x52 16284059Swpaul#define BGE_PCI_VPD_DATA 0x54 16384059Swpaul#define BGE_PCI_MSI_CAPID 0x58 16484059Swpaul#define BGE_PCI_NEXTPTR_NONE 0x59 16584059Swpaul#define BGE_PCI_MSI_CTL 0x5A 16684059Swpaul#define BGE_PCI_MSI_ADDR_HI 0x5C 16784059Swpaul#define BGE_PCI_MSI_ADDR_LO 0x60 16884059Swpaul#define BGE_PCI_MSI_DATA 0x64 16984059Swpaul 17084059Swpaul/* 17184059Swpaul * PCI registers specific to the BCM570x family. 17284059Swpaul */ 17384059Swpaul#define BGE_PCI_MISC_CTL 0x68 17484059Swpaul#define BGE_PCI_DMA_RW_CTL 0x6C 17584059Swpaul#define BGE_PCI_PCISTATE 0x70 17684059Swpaul#define BGE_PCI_CLKCTL 0x74 17784059Swpaul#define BGE_PCI_REG_BASEADDR 0x78 17884059Swpaul#define BGE_PCI_MEMWIN_BASEADDR 0x7C 17984059Swpaul#define BGE_PCI_REG_DATA 0x80 18084059Swpaul#define BGE_PCI_MEMWIN_DATA 0x84 18184059Swpaul#define BGE_PCI_MODECTL 0x88 18284059Swpaul#define BGE_PCI_MISC_CFG 0x8C 18384059Swpaul#define BGE_PCI_MISC_LOCALCTL 0x90 18484059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 18584059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 18684059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 18784059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 18884059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 18984059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 19084059Swpaul#define BGE_PCI_ISR_MBX_HI 0xB0 19184059Swpaul#define BGE_PCI_ISR_MBX_LO 0xB4 19284059Swpaul 19384059Swpaul/* PCI Misc. Host control register */ 19484059Swpaul#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 19584059Swpaul#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 19684059Swpaul#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 19784059Swpaul#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 19884059Swpaul#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 19984059Swpaul#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 20084059Swpaul#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 20184059Swpaul#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 20284059Swpaul#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 20384059Swpaul 20484059Swpaul#define BGE_BIGENDIAN_INIT \ 20584059Swpaul (BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 20684059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 20784059Swpaul BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR) 20884059Swpaul 20984059Swpaul#define BGE_LITTLEENDIAN_INIT \ 21084059Swpaul (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 21184059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 21284059Swpaul 21384059Swpaul#define BGE_ASICREV_TIGON_I 0x40000000 21484059Swpaul#define BGE_ASICREV_TIGON_II 0x60000000 21584059Swpaul#define BGE_ASICREV_BCM5700_B0 0x71000000 21684059Swpaul#define BGE_ASICREV_BCM5700_B1 0x71020000 21784059Swpaul#define BGE_ASICREV_BCM5700_B2 0x71030000 21884059Swpaul#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 21984059Swpaul#define BGE_ASICREV_BCM5700_C0 0x72000000 22084059Swpaul 22184059Swpaul/* PCI DMA Read/Write Control register */ 22284059Swpaul#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 22384059Swpaul#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 22484059Swpaul#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 22584059Swpaul#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 22684059Swpaul#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 22784059Swpaul#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 22884059Swpaul#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 22984059Swpaul#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 23084059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 23184059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 23284059Swpaul 23384059Swpaul#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 23484059Swpaul#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 23584059Swpaul#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 23684059Swpaul#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 23784059Swpaul#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 23884059Swpaul#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 23984059Swpaul#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 24084059Swpaul#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 24184059Swpaul 24284059Swpaul#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 24384059Swpaul#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 24484059Swpaul#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 24584059Swpaul#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 24684059Swpaul#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 24784059Swpaul#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 24884059Swpaul#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 24984059Swpaul#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 25084059Swpaul 25184059Swpaul/* 25284059Swpaul * PCI state register -- note, this register is read only 25384059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 25484059Swpaul * register is set. 25584059Swpaul */ 25684059Swpaul#define BGE_PCISTATE_FORCE_RESET 0x00000001 25784059Swpaul#define BGE_PCISTATE_INTR_STATE 0x00000002 25884059Swpaul#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 25984059Swpaul#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 26084059Swpaul#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 26184059Swpaul#define BGE_PCISTATE_WANT_EXPROM 0x00000020 26284059Swpaul#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 26384059Swpaul#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 26484059Swpaul#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 26584059Swpaul 26684059Swpaul/* 26784059Swpaul * PCI Clock Control register -- note, this register is read only 26884059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 26984059Swpaul * register is set. 27084059Swpaul */ 27184059Swpaul#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 27284059Swpaul#define BGE_PCICLOCKCTL_M66EN 0x00000080 27384059Swpaul#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 27484059Swpaul#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 27584059Swpaul#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 27684059Swpaul#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 27784059Swpaul#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 27884059Swpaul#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 27984059Swpaul#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 28084059Swpaul#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 28184059Swpaul 28284059Swpaul 28384059Swpaul#ifndef PCIM_CMD_MWIEN 28484059Swpaul#define PCIM_CMD_MWIEN 0x0010 28584059Swpaul#endif 28684059Swpaul 28784059Swpaul/* 28884059Swpaul * High priority mailbox registers 28984059Swpaul * Each mailbox is 64-bits wide, though we only use the 29084059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 29184059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 29284059Swpaul * has been updated. 29384059Swpaul */ 29484059Swpaul#define BGE_MBX_IRQ0_HI 0x0200 29584059Swpaul#define BGE_MBX_IRQ0_LO 0x0204 29684059Swpaul#define BGE_MBX_IRQ1_HI 0x0208 29784059Swpaul#define BGE_MBX_IRQ1_LO 0x020C 29884059Swpaul#define BGE_MBX_IRQ2_HI 0x0210 29984059Swpaul#define BGE_MBX_IRQ2_LO 0x0214 30084059Swpaul#define BGE_MBX_IRQ3_HI 0x0218 30184059Swpaul#define BGE_MBX_IRQ3_LO 0x021C 30284059Swpaul#define BGE_MBX_GEN0_HI 0x0220 30384059Swpaul#define BGE_MBX_GEN0_LO 0x0224 30484059Swpaul#define BGE_MBX_GEN1_HI 0x0228 30584059Swpaul#define BGE_MBX_GEN1_LO 0x022C 30684059Swpaul#define BGE_MBX_GEN2_HI 0x0230 30784059Swpaul#define BGE_MBX_GEN2_LO 0x0234 30884059Swpaul#define BGE_MBX_GEN3_HI 0x0228 30984059Swpaul#define BGE_MBX_GEN3_LO 0x022C 31084059Swpaul#define BGE_MBX_GEN4_HI 0x0240 31184059Swpaul#define BGE_MBX_GEN4_LO 0x0244 31284059Swpaul#define BGE_MBX_GEN5_HI 0x0248 31384059Swpaul#define BGE_MBX_GEN5_LO 0x024C 31484059Swpaul#define BGE_MBX_GEN6_HI 0x0250 31584059Swpaul#define BGE_MBX_GEN6_LO 0x0254 31684059Swpaul#define BGE_MBX_GEN7_HI 0x0258 31784059Swpaul#define BGE_MBX_GEN7_LO 0x025C 31884059Swpaul#define BGE_MBX_RELOAD_STATS_HI 0x0260 31984059Swpaul#define BGE_MBX_RELOAD_STATS_LO 0x0264 32084059Swpaul#define BGE_MBX_RX_STD_PROD_HI 0x0268 32184059Swpaul#define BGE_MBX_RX_STD_PROD_LO 0x026C 32284059Swpaul#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 32384059Swpaul#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 32484059Swpaul#define BGE_MBX_RX_MINI_PROD_HI 0x0278 32584059Swpaul#define BGE_MBX_RX_MINI_PROD_LO 0x027C 32684059Swpaul#define BGE_MBX_RX_CONS0_HI 0x0280 32784059Swpaul#define BGE_MBX_RX_CONS0_LO 0x0284 32884059Swpaul#define BGE_MBX_RX_CONS1_HI 0x0288 32984059Swpaul#define BGE_MBX_RX_CONS1_LO 0x028C 33084059Swpaul#define BGE_MBX_RX_CONS2_HI 0x0290 33184059Swpaul#define BGE_MBX_RX_CONS2_LO 0x0294 33284059Swpaul#define BGE_MBX_RX_CONS3_HI 0x0298 33384059Swpaul#define BGE_MBX_RX_CONS3_LO 0x029C 33484059Swpaul#define BGE_MBX_RX_CONS4_HI 0x02A0 33584059Swpaul#define BGE_MBX_RX_CONS4_LO 0x02A4 33684059Swpaul#define BGE_MBX_RX_CONS5_HI 0x02A8 33784059Swpaul#define BGE_MBX_RX_CONS5_LO 0x02AC 33884059Swpaul#define BGE_MBX_RX_CONS6_HI 0x02B0 33984059Swpaul#define BGE_MBX_RX_CONS6_LO 0x02B4 34084059Swpaul#define BGE_MBX_RX_CONS7_HI 0x02B8 34184059Swpaul#define BGE_MBX_RX_CONS7_LO 0x02BC 34284059Swpaul#define BGE_MBX_RX_CONS8_HI 0x02C0 34384059Swpaul#define BGE_MBX_RX_CONS8_LO 0x02C4 34484059Swpaul#define BGE_MBX_RX_CONS9_HI 0x02C8 34584059Swpaul#define BGE_MBX_RX_CONS9_LO 0x02CC 34684059Swpaul#define BGE_MBX_RX_CONS10_HI 0x02D0 34784059Swpaul#define BGE_MBX_RX_CONS10_LO 0x02D4 34884059Swpaul#define BGE_MBX_RX_CONS11_HI 0x02D8 34984059Swpaul#define BGE_MBX_RX_CONS11_LO 0x02DC 35084059Swpaul#define BGE_MBX_RX_CONS12_HI 0x02E0 35184059Swpaul#define BGE_MBX_RX_CONS12_LO 0x02E4 35284059Swpaul#define BGE_MBX_RX_CONS13_HI 0x02E8 35384059Swpaul#define BGE_MBX_RX_CONS13_LO 0x02EC 35484059Swpaul#define BGE_MBX_RX_CONS14_HI 0x02F0 35584059Swpaul#define BGE_MBX_RX_CONS14_LO 0x02F4 35684059Swpaul#define BGE_MBX_RX_CONS15_HI 0x02F8 35784059Swpaul#define BGE_MBX_RX_CONS15_LO 0x02FC 35884059Swpaul#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 35984059Swpaul#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 36084059Swpaul#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 36184059Swpaul#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 36284059Swpaul#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 36384059Swpaul#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 36484059Swpaul#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 36584059Swpaul#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 36684059Swpaul#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 36784059Swpaul#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 36884059Swpaul#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 36984059Swpaul#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 37084059Swpaul#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 37184059Swpaul#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 37284059Swpaul#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 37384059Swpaul#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 37484059Swpaul#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 37584059Swpaul#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 37684059Swpaul#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 37784059Swpaul#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 37884059Swpaul#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 37984059Swpaul#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 38084059Swpaul#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 38184059Swpaul#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 38284059Swpaul#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 38384059Swpaul#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 38484059Swpaul#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 38584059Swpaul#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 38684059Swpaul#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 38784059Swpaul#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 38884059Swpaul#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 38984059Swpaul#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 39084059Swpaul#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 39184059Swpaul#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 39284059Swpaul#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 39384059Swpaul#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 39484059Swpaul#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 39584059Swpaul#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 39684059Swpaul#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 39784059Swpaul#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 39884059Swpaul#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 39984059Swpaul#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 40084059Swpaul#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 40184059Swpaul#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 40284059Swpaul#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 40384059Swpaul#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 40484059Swpaul#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 40584059Swpaul#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 40684059Swpaul#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 40784059Swpaul#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 40884059Swpaul#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 40984059Swpaul#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 41084059Swpaul#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 41184059Swpaul#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 41284059Swpaul#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 41384059Swpaul#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 41484059Swpaul#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 41584059Swpaul#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 41684059Swpaul#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 41784059Swpaul#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 41884059Swpaul#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 41984059Swpaul#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 42084059Swpaul#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 42184059Swpaul#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 42284059Swpaul 42384059Swpaul#define BGE_TX_RINGS_MAX 4 42484059Swpaul#define BGE_TX_RINGS_EXTSSRAM_MAX 16 42584059Swpaul#define BGE_RX_RINGS_MAX 16 42684059Swpaul 42784059Swpaul/* Ethernet MAC control registers */ 42884059Swpaul#define BGE_MAC_MODE 0x0400 42984059Swpaul#define BGE_MAC_STS 0x0404 43084059Swpaul#define BGE_MAC_EVT_ENB 0x0408 43184059Swpaul#define BGE_MAC_LED_CTL 0x040C 43284059Swpaul#define BGE_MAC_ADDR1_LO 0x0410 43384059Swpaul#define BGE_MAC_ADDR1_HI 0x0414 43484059Swpaul#define BGE_MAC_ADDR2_LO 0x0418 43584059Swpaul#define BGE_MAC_ADDR2_HI 0x041C 43684059Swpaul#define BGE_MAC_ADDR3_LO 0x0420 43784059Swpaul#define BGE_MAC_ADDR3_HI 0x0424 43884059Swpaul#define BGE_MAC_ADDR4_LO 0x0428 43984059Swpaul#define BGE_MAC_ADDR4_HI 0x042C 44084059Swpaul#define BGE_WOL_PATPTR 0x0430 44184059Swpaul#define BGE_WOL_PATCFG 0x0434 44284059Swpaul#define BGE_TX_RANDOM_BACKOFF 0x0438 44384059Swpaul#define BGE_RX_MTU 0x043C 44484059Swpaul#define BGE_GBIT_PCS_TEST 0x0440 44584059Swpaul#define BGE_TX_TBI_AUTONEG 0x0444 44684059Swpaul#define BGE_RX_TBI_AUTONEG 0x0448 44784059Swpaul#define BGE_MI_COMM 0x044C 44884059Swpaul#define BGE_MI_STS 0x0450 44984059Swpaul#define BGE_MI_MODE 0x0454 45084059Swpaul#define BGE_AUTOPOLL_STS 0x0458 45184059Swpaul#define BGE_TX_MODE 0x045C 45284059Swpaul#define BGE_TX_STS 0x0460 45384059Swpaul#define BGE_TX_LENGTHS 0x0464 45484059Swpaul#define BGE_RX_MODE 0x0468 45584059Swpaul#define BGE_RX_STS 0x046C 45684059Swpaul#define BGE_MAR0 0x0470 45784059Swpaul#define BGE_MAR1 0x0474 45884059Swpaul#define BGE_MAR2 0x0478 45984059Swpaul#define BGE_MAR3 0x047C 46084059Swpaul#define BGE_RX_BD_RULES_CTL0 0x0480 46184059Swpaul#define BGE_RX_BD_RULES_MASKVAL0 0x0484 46284059Swpaul#define BGE_RX_BD_RULES_CTL1 0x0488 46384059Swpaul#define BGE_RX_BD_RULES_MASKVAL1 0x048C 46484059Swpaul#define BGE_RX_BD_RULES_CTL2 0x0490 46584059Swpaul#define BGE_RX_BD_RULES_MASKVAL2 0x0494 46684059Swpaul#define BGE_RX_BD_RULES_CTL3 0x0498 46784059Swpaul#define BGE_RX_BD_RULES_MASKVAL3 0x049C 46884059Swpaul#define BGE_RX_BD_RULES_CTL4 0x04A0 46984059Swpaul#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 47084059Swpaul#define BGE_RX_BD_RULES_CTL5 0x04A8 47184059Swpaul#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 47284059Swpaul#define BGE_RX_BD_RULES_CTL6 0x04B0 47384059Swpaul#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 47484059Swpaul#define BGE_RX_BD_RULES_CTL7 0x04B8 47584059Swpaul#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 47684059Swpaul#define BGE_RX_BD_RULES_CTL8 0x04C0 47784059Swpaul#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 47884059Swpaul#define BGE_RX_BD_RULES_CTL9 0x04C8 47984059Swpaul#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 48084059Swpaul#define BGE_RX_BD_RULES_CTL10 0x04D0 48184059Swpaul#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 48284059Swpaul#define BGE_RX_BD_RULES_CTL11 0x04D8 48384059Swpaul#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 48484059Swpaul#define BGE_RX_BD_RULES_CTL12 0x04E0 48584059Swpaul#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 48684059Swpaul#define BGE_RX_BD_RULES_CTL13 0x04E8 48784059Swpaul#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 48884059Swpaul#define BGE_RX_BD_RULES_CTL14 0x04F0 48984059Swpaul#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 49084059Swpaul#define BGE_RX_BD_RULES_CTL15 0x04F8 49184059Swpaul#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 49284059Swpaul#define BGE_RX_RULES_CFG 0x0500 49384059Swpaul#define BGE_RX_STATS 0x0800 49484059Swpaul#define BGE_TX_STATS 0x0880 49584059Swpaul 49684059Swpaul/* Ethernet MAC Mode register */ 49784059Swpaul#define BGE_MACMODE_RESET 0x00000001 49884059Swpaul#define BGE_MACMODE_HALF_DUPLEX 0x00000002 49984059Swpaul#define BGE_MACMODE_PORTMODE 0x0000000C 50084059Swpaul#define BGE_MACMODE_LOOPBACK 0x00000010 50184059Swpaul#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 50284059Swpaul#define BGE_MACMODE_TX_BURST_ENB 0x00000100 50384059Swpaul#define BGE_MACMODE_MAX_DEFER 0x00000200 50484059Swpaul#define BGE_MACMODE_LINK_POLARITY 0x00000400 50584059Swpaul#define BGE_MACMODE_RX_STATS_ENB 0x00000800 50684059Swpaul#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 50784059Swpaul#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 50884059Swpaul#define BGE_MACMODE_TX_STATS_ENB 0x00004000 50984059Swpaul#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 51084059Swpaul#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 51184059Swpaul#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 51284059Swpaul#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 51384059Swpaul#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 51484059Swpaul#define BGE_MACMODE_MIP_ENB 0x00100000 51584059Swpaul#define BGE_MACMODE_TXDMA_ENB 0x00200000 51684059Swpaul#define BGE_MACMODE_RXDMA_ENB 0x00400000 51784059Swpaul#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 51884059Swpaul 51984059Swpaul#define BGE_PORTMODE_NONE 0x00000000 52084059Swpaul#define BGE_PORTMODE_MII 0x00000004 52184059Swpaul#define BGE_PORTMODE_GMII 0x00000008 52284059Swpaul#define BGE_PORTMODE_TBI 0x0000000C 52384059Swpaul 52484059Swpaul/* MAC Status register */ 52584059Swpaul#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 52684059Swpaul#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 52784059Swpaul#define BGE_MACSTAT_RX_CFG 0x00000004 52884059Swpaul#define BGE_MACSTAT_CFG_CHANGED 0x00000008 52984059Swpaul#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 53084059Swpaul#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 53184059Swpaul#define BGE_MACSTAT_LINK_CHANGED 0x00001000 53284059Swpaul#define BGE_MACSTAT_MI_COMPLETE 0x00400000 53384059Swpaul#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 53484059Swpaul#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 53584059Swpaul#define BGE_MACSTAT_ODI_ERROR 0x02000000 53684059Swpaul#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 53784059Swpaul#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 53884059Swpaul 53984059Swpaul/* MAC Event Enable Register */ 54084059Swpaul#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 54184059Swpaul#define BGE_EVTENB_LINK_CHANGED 0x00001000 54284059Swpaul#define BGE_EVTENB_MI_COMPLETE 0x00400000 54384059Swpaul#define BGE_EVTENB_MI_INTERRUPT 0x00800000 54484059Swpaul#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 54584059Swpaul#define BGE_EVTENB_ODI_ERROR 0x02000000 54684059Swpaul#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 54784059Swpaul#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 54884059Swpaul 54984059Swpaul/* LED Control Register */ 55084059Swpaul#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 55184059Swpaul#define BGE_LEDCTL_1000MBPS_LED 0x00000002 55284059Swpaul#define BGE_LEDCTL_100MBPS_LED 0x00000004 55384059Swpaul#define BGE_LEDCTL_10MBPS_LED 0x00000008 55484059Swpaul#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 55584059Swpaul#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 55684059Swpaul#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 55784059Swpaul#define BGE_LEDCTL_1000MBPS_STS 0x00000080 55884059Swpaul#define BGE_LEDCTL_100MBPS_STS 0x00000100 55984059Swpaul#define BGE_LEDCTL_10MBPS_STS 0x00000200 56084059Swpaul#define BGE_LEDCTL_TRADLED_STS 0x00000400 56184059Swpaul#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 56284059Swpaul#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 56384059Swpaul 56484059Swpaul/* TX backoff seed register */ 56584059Swpaul#define BGE_TX_BACKOFF_SEED_MASK 0x3F 56684059Swpaul 56784059Swpaul/* Autopoll status register */ 56884059Swpaul#define BGE_AUTOPOLLSTS_ERROR 0x00000001 56984059Swpaul 57084059Swpaul/* Transmit MAC mode register */ 57184059Swpaul#define BGE_TXMODE_RESET 0x00000001 57284059Swpaul#define BGE_TXMODE_ENABLE 0x00000002 57384059Swpaul#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 57484059Swpaul#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 57584059Swpaul#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 57684059Swpaul 57784059Swpaul/* Transmit MAC status register */ 57884059Swpaul#define BGE_TXSTAT_RX_XOFFED 0x00000001 57984059Swpaul#define BGE_TXSTAT_SENT_XOFF 0x00000002 58084059Swpaul#define BGE_TXSTAT_SENT_XON 0x00000004 58184059Swpaul#define BGE_TXSTAT_LINK_UP 0x00000008 58284059Swpaul#define BGE_TXSTAT_ODI_UFLOW 0x00000010 58384059Swpaul#define BGE_TXSTAT_ODI_OFLOW 0x00000020 58484059Swpaul 58584059Swpaul/* Transmit MAC lengths register */ 58684059Swpaul#define BGE_TXLEN_SLOTTIME 0x000000FF 58784059Swpaul#define BGE_TXLEN_IPG 0x00000F00 58884059Swpaul#define BGE_TXLEN_CRS 0x00003000 58984059Swpaul 59084059Swpaul/* Receive MAC mode register */ 59184059Swpaul#define BGE_RXMODE_RESET 0x00000001 59284059Swpaul#define BGE_RXMODE_ENABLE 0x00000002 59384059Swpaul#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 59484059Swpaul#define BGE_RXMODE_RX_GIANTS 0x00000020 59584059Swpaul#define BGE_RXMODE_RX_RUNTS 0x00000040 59684059Swpaul#define BGE_RXMODE_8022_LENCHECK 0x00000080 59784059Swpaul#define BGE_RXMODE_RX_PROMISC 0x00000100 59884059Swpaul#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 59984059Swpaul#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 60084059Swpaul 60184059Swpaul/* Receive MAC status register */ 60284059Swpaul#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 60384059Swpaul#define BGE_RXSTAT_RCVD_XOFF 0x00000002 60484059Swpaul#define BGE_RXSTAT_RCVD_XON 0x00000004 60584059Swpaul 60684059Swpaul/* Receive Rules Control register */ 60784059Swpaul#define BGE_RXRULECTL_OFFSET 0x000000FF 60884059Swpaul#define BGE_RXRULECTL_CLASS 0x00001F00 60984059Swpaul#define BGE_RXRULECTL_HDRTYPE 0x0000E000 61084059Swpaul#define BGE_RXRULECTL_COMPARE_OP 0x00030000 61184059Swpaul#define BGE_RXRULECTL_MAP 0x01000000 61284059Swpaul#define BGE_RXRULECTL_DISCARD 0x02000000 61384059Swpaul#define BGE_RXRULECTL_MASK 0x04000000 61484059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 61584059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 61684059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 61784059Swpaul#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 61884059Swpaul 61984059Swpaul/* Receive Rules Mask register */ 62084059Swpaul#define BGE_RXRULEMASK_VALUE 0x0000FFFF 62184059Swpaul#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 62284059Swpaul 62384059Swpaul/* MI communication register */ 62484059Swpaul#define BGE_MICOMM_DATA 0x0000FFFF 62584059Swpaul#define BGE_MICOMM_REG 0x001F0000 62684059Swpaul#define BGE_MICOMM_PHY 0x03E00000 62784059Swpaul#define BGE_MICOMM_CMD 0x0C000000 62884059Swpaul#define BGE_MICOMM_READFAIL 0x10000000 62984059Swpaul#define BGE_MICOMM_BUSY 0x20000000 63084059Swpaul 63184059Swpaul#define BGE_MIREG(x) ((x & 0x1F) << 16) 63284059Swpaul#define BGE_MIPHY(x) ((x & 0x1F) << 21) 63384059Swpaul#define BGE_MICMD_WRITE 0x04000000 63484059Swpaul#define BGE_MICMD_READ 0x08000000 63584059Swpaul 63684059Swpaul/* MI status register */ 63784059Swpaul#define BGE_MISTS_LINK 0x00000001 63884059Swpaul#define BGE_MISTS_10MBPS 0x00000002 63984059Swpaul 64084059Swpaul#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 64184059Swpaul#define BGE_MIMODE_AUTOPOLL 0x00000010 64284059Swpaul#define BGE_MIMODE_CLKCNT 0x001F0000 64384059Swpaul 64484059Swpaul 64584059Swpaul/* 64684059Swpaul * Send data initiator control registers. 64784059Swpaul */ 64884059Swpaul#define BGE_SDI_MODE 0x0C00 64984059Swpaul#define BGE_SDI_STATUS 0x0C04 65084059Swpaul#define BGE_SDI_STATS_CTL 0x0C08 65184059Swpaul#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 65284059Swpaul#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 65384059Swpaul#define BGE_LOCSTATS_COS0 0x0C80 65484059Swpaul#define BGE_LOCSTATS_COS1 0x0C84 65584059Swpaul#define BGE_LOCSTATS_COS2 0x0C88 65684059Swpaul#define BGE_LOCSTATS_COS3 0x0C8C 65784059Swpaul#define BGE_LOCSTATS_COS4 0x0C90 65884059Swpaul#define BGE_LOCSTATS_COS5 0x0C84 65984059Swpaul#define BGE_LOCSTATS_COS6 0x0C98 66084059Swpaul#define BGE_LOCSTATS_COS7 0x0C9C 66184059Swpaul#define BGE_LOCSTATS_COS8 0x0CA0 66284059Swpaul#define BGE_LOCSTATS_COS9 0x0CA4 66384059Swpaul#define BGE_LOCSTATS_COS10 0x0CA8 66484059Swpaul#define BGE_LOCSTATS_COS11 0x0CAC 66584059Swpaul#define BGE_LOCSTATS_COS12 0x0CB0 66684059Swpaul#define BGE_LOCSTATS_COS13 0x0CB4 66784059Swpaul#define BGE_LOCSTATS_COS14 0x0CB8 66884059Swpaul#define BGE_LOCSTATS_COS15 0x0CBC 66984059Swpaul#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 67084059Swpaul#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 67184059Swpaul#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 67284059Swpaul#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 67384059Swpaul#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 67484059Swpaul#define BGE_LOCSTATS_IRQS 0x0CD4 67584059Swpaul#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 67684059Swpaul#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 67784059Swpaul 67884059Swpaul/* Send Data Initiator mode register */ 67984059Swpaul#define BGE_SDIMODE_RESET 0x00000001 68084059Swpaul#define BGE_SDIMODE_ENABLE 0x00000002 68184059Swpaul#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 68284059Swpaul 68384059Swpaul/* Send Data Initiator stats register */ 68484059Swpaul#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 68584059Swpaul 68684059Swpaul/* Send Data Initiator stats control register */ 68784059Swpaul#define BGE_SDISTATSCTL_ENABLE 0x00000001 68884059Swpaul#define BGE_SDISTATSCTL_FASTER 0x00000002 68984059Swpaul#define BGE_SDISTATSCTL_CLEAR 0x00000004 69084059Swpaul#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 69184059Swpaul#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 69284059Swpaul 69384059Swpaul/* 69484059Swpaul * Send Data Completion Control registers 69584059Swpaul */ 69684059Swpaul#define BGE_SDC_MODE 0x1000 69784059Swpaul#define BGE_SDC_STATUS 0x1004 69884059Swpaul 69984059Swpaul/* Send Data completion mode register */ 70084059Swpaul#define BGE_SDCMODE_RESET 0x00000001 70184059Swpaul#define BGE_SDCMODE_ENABLE 0x00000002 70284059Swpaul#define BGE_SDCMODE_ATTN 0x00000004 70384059Swpaul 70484059Swpaul/* Send Data completion status register */ 70584059Swpaul#define BGE_SDCSTAT_ATTN 0x00000004 70684059Swpaul 70784059Swpaul/* 70884059Swpaul * Send BD Ring Selector Control registers 70984059Swpaul */ 71084059Swpaul#define BGE_SRS_MODE 0x1400 71184059Swpaul#define BGE_SRS_STATUS 0x1404 71284059Swpaul#define BGE_SRS_HWDIAG 0x1408 71384059Swpaul#define BGE_SRS_LOC_NIC_CONS0 0x1440 71484059Swpaul#define BGE_SRS_LOC_NIC_CONS1 0x1444 71584059Swpaul#define BGE_SRS_LOC_NIC_CONS2 0x1448 71684059Swpaul#define BGE_SRS_LOC_NIC_CONS3 0x144C 71784059Swpaul#define BGE_SRS_LOC_NIC_CONS4 0x1450 71884059Swpaul#define BGE_SRS_LOC_NIC_CONS5 0x1454 71984059Swpaul#define BGE_SRS_LOC_NIC_CONS6 0x1458 72084059Swpaul#define BGE_SRS_LOC_NIC_CONS7 0x145C 72184059Swpaul#define BGE_SRS_LOC_NIC_CONS8 0x1460 72284059Swpaul#define BGE_SRS_LOC_NIC_CONS9 0x1464 72384059Swpaul#define BGE_SRS_LOC_NIC_CONS10 0x1468 72484059Swpaul#define BGE_SRS_LOC_NIC_CONS11 0x146C 72584059Swpaul#define BGE_SRS_LOC_NIC_CONS12 0x1470 72684059Swpaul#define BGE_SRS_LOC_NIC_CONS13 0x1474 72784059Swpaul#define BGE_SRS_LOC_NIC_CONS14 0x1478 72884059Swpaul#define BGE_SRS_LOC_NIC_CONS15 0x147C 72984059Swpaul 73084059Swpaul/* Send BD Ring Selector Mode register */ 73184059Swpaul#define BGE_SRSMODE_RESET 0x00000001 73284059Swpaul#define BGE_SRSMODE_ENABLE 0x00000002 73384059Swpaul#define BGE_SRSMODE_ATTN 0x00000004 73484059Swpaul 73584059Swpaul/* Send BD Ring Selector Status register */ 73684059Swpaul#define BGE_SRSSTAT_ERROR 0x00000004 73784059Swpaul 73884059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 73984059Swpaul#define BGE_SRSHWDIAG_STATE 0x0000000F 74084059Swpaul#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 74184059Swpaul#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 74284059Swpaul#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 74384059Swpaul 74484059Swpaul/* 74584059Swpaul * Send BD Initiator Selector Control registers 74684059Swpaul */ 74784059Swpaul#define BGE_SBDI_MODE 0x1800 74884059Swpaul#define BGE_SBDI_STATUS 0x1804 74984059Swpaul#define BGE_SBDI_LOC_NIC_PROD0 0x1808 75084059Swpaul#define BGE_SBDI_LOC_NIC_PROD1 0x180C 75184059Swpaul#define BGE_SBDI_LOC_NIC_PROD2 0x1810 75284059Swpaul#define BGE_SBDI_LOC_NIC_PROD3 0x1814 75384059Swpaul#define BGE_SBDI_LOC_NIC_PROD4 0x1818 75484059Swpaul#define BGE_SBDI_LOC_NIC_PROD5 0x181C 75584059Swpaul#define BGE_SBDI_LOC_NIC_PROD6 0x1820 75684059Swpaul#define BGE_SBDI_LOC_NIC_PROD7 0x1824 75784059Swpaul#define BGE_SBDI_LOC_NIC_PROD8 0x1828 75884059Swpaul#define BGE_SBDI_LOC_NIC_PROD9 0x182C 75984059Swpaul#define BGE_SBDI_LOC_NIC_PROD10 0x1830 76084059Swpaul#define BGE_SBDI_LOC_NIC_PROD11 0x1834 76184059Swpaul#define BGE_SBDI_LOC_NIC_PROD12 0x1838 76284059Swpaul#define BGE_SBDI_LOC_NIC_PROD13 0x183C 76384059Swpaul#define BGE_SBDI_LOC_NIC_PROD14 0x1840 76484059Swpaul#define BGE_SBDI_LOC_NIC_PROD15 0x1844 76584059Swpaul 76684059Swpaul/* Send BD Initiator Mode register */ 76784059Swpaul#define BGE_SBDIMODE_RESET 0x00000001 76884059Swpaul#define BGE_SBDIMODE_ENABLE 0x00000002 76984059Swpaul#define BGE_SBDIMODE_ATTN 0x00000004 77084059Swpaul 77184059Swpaul/* Send BD Initiator Status register */ 77284059Swpaul#define BGE_SBDISTAT_ERROR 0x00000004 77384059Swpaul 77484059Swpaul/* 77584059Swpaul * Send BD Completion Control registers 77684059Swpaul */ 77784059Swpaul#define BGE_SBDC_MODE 0x1C00 77884059Swpaul#define BGE_SBDC_STATUS 0x1C04 77984059Swpaul 78084059Swpaul/* Send BD Completion Control Mode register */ 78184059Swpaul#define BGE_SBDCMODE_RESET 0x00000001 78284059Swpaul#define BGE_SBDCMODE_ENABLE 0x00000002 78384059Swpaul#define BGE_SBDCMODE_ATTN 0x00000004 78484059Swpaul 78584059Swpaul/* Send BD Completion Control Status register */ 78684059Swpaul#define BGE_SBDCSTAT_ATTN 0x00000004 78784059Swpaul 78884059Swpaul/* 78984059Swpaul * Receive List Placement Control registers 79084059Swpaul */ 79184059Swpaul#define BGE_RXLP_MODE 0x2000 79284059Swpaul#define BGE_RXLP_STATUS 0x2004 79384059Swpaul#define BGE_RXLP_SEL_LIST_LOCK 0x2008 79484059Swpaul#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 79584059Swpaul#define BGE_RXLP_CFG 0x2010 79684059Swpaul#define BGE_RXLP_STATS_CTL 0x2014 79784059Swpaul#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 79884059Swpaul#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 79984059Swpaul#define BGE_RXLP_HEAD0 0x2100 80084059Swpaul#define BGE_RXLP_TAIL0 0x2104 80184059Swpaul#define BGE_RXLP_COUNT0 0x2108 80284059Swpaul#define BGE_RXLP_HEAD1 0x2110 80384059Swpaul#define BGE_RXLP_TAIL1 0x2114 80484059Swpaul#define BGE_RXLP_COUNT1 0x2118 80584059Swpaul#define BGE_RXLP_HEAD2 0x2120 80684059Swpaul#define BGE_RXLP_TAIL2 0x2124 80784059Swpaul#define BGE_RXLP_COUNT2 0x2128 80884059Swpaul#define BGE_RXLP_HEAD3 0x2130 80984059Swpaul#define BGE_RXLP_TAIL3 0x2134 81084059Swpaul#define BGE_RXLP_COUNT3 0x2138 81184059Swpaul#define BGE_RXLP_HEAD4 0x2140 81284059Swpaul#define BGE_RXLP_TAIL4 0x2144 81384059Swpaul#define BGE_RXLP_COUNT4 0x2148 81484059Swpaul#define BGE_RXLP_HEAD5 0x2150 81584059Swpaul#define BGE_RXLP_TAIL5 0x2154 81684059Swpaul#define BGE_RXLP_COUNT5 0x2158 81784059Swpaul#define BGE_RXLP_HEAD6 0x2160 81884059Swpaul#define BGE_RXLP_TAIL6 0x2164 81984059Swpaul#define BGE_RXLP_COUNT6 0x2168 82084059Swpaul#define BGE_RXLP_HEAD7 0x2170 82184059Swpaul#define BGE_RXLP_TAIL7 0x2174 82284059Swpaul#define BGE_RXLP_COUNT7 0x2178 82384059Swpaul#define BGE_RXLP_HEAD8 0x2180 82484059Swpaul#define BGE_RXLP_TAIL8 0x2184 82584059Swpaul#define BGE_RXLP_COUNT8 0x2188 82684059Swpaul#define BGE_RXLP_HEAD9 0x2190 82784059Swpaul#define BGE_RXLP_TAIL9 0x2194 82884059Swpaul#define BGE_RXLP_COUNT9 0x2198 82984059Swpaul#define BGE_RXLP_HEAD10 0x21A0 83084059Swpaul#define BGE_RXLP_TAIL10 0x21A4 83184059Swpaul#define BGE_RXLP_COUNT10 0x21A8 83284059Swpaul#define BGE_RXLP_HEAD11 0x21B0 83384059Swpaul#define BGE_RXLP_TAIL11 0x21B4 83484059Swpaul#define BGE_RXLP_COUNT11 0x21B8 83584059Swpaul#define BGE_RXLP_HEAD12 0x21C0 83684059Swpaul#define BGE_RXLP_TAIL12 0x21C4 83784059Swpaul#define BGE_RXLP_COUNT12 0x21C8 83884059Swpaul#define BGE_RXLP_HEAD13 0x21D0 83984059Swpaul#define BGE_RXLP_TAIL13 0x21D4 84084059Swpaul#define BGE_RXLP_COUNT13 0x21D8 84184059Swpaul#define BGE_RXLP_HEAD14 0x21E0 84284059Swpaul#define BGE_RXLP_TAIL14 0x21E4 84384059Swpaul#define BGE_RXLP_COUNT14 0x21E8 84484059Swpaul#define BGE_RXLP_HEAD15 0x21F0 84584059Swpaul#define BGE_RXLP_TAIL15 0x21F4 84684059Swpaul#define BGE_RXLP_COUNT15 0x21F8 84784059Swpaul#define BGE_RXLP_LOCSTAT_COS0 0x2200 84884059Swpaul#define BGE_RXLP_LOCSTAT_COS1 0x2204 84984059Swpaul#define BGE_RXLP_LOCSTAT_COS2 0x2208 85084059Swpaul#define BGE_RXLP_LOCSTAT_COS3 0x220C 85184059Swpaul#define BGE_RXLP_LOCSTAT_COS4 0x2210 85284059Swpaul#define BGE_RXLP_LOCSTAT_COS5 0x2214 85384059Swpaul#define BGE_RXLP_LOCSTAT_COS6 0x2218 85484059Swpaul#define BGE_RXLP_LOCSTAT_COS7 0x221C 85584059Swpaul#define BGE_RXLP_LOCSTAT_COS8 0x2220 85684059Swpaul#define BGE_RXLP_LOCSTAT_COS9 0x2224 85784059Swpaul#define BGE_RXLP_LOCSTAT_COS10 0x2228 85884059Swpaul#define BGE_RXLP_LOCSTAT_COS11 0x222C 85984059Swpaul#define BGE_RXLP_LOCSTAT_COS12 0x2230 86084059Swpaul#define BGE_RXLP_LOCSTAT_COS13 0x2234 86184059Swpaul#define BGE_RXLP_LOCSTAT_COS14 0x2238 86284059Swpaul#define BGE_RXLP_LOCSTAT_COS15 0x223C 86384059Swpaul#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 86484059Swpaul#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 86584059Swpaul#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 86684059Swpaul#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 86784059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 86884059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 86984059Swpaul#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 87084059Swpaul 87184059Swpaul 87284059Swpaul/* Receive List Placement mode register */ 87384059Swpaul#define BGE_RXLPMODE_RESET 0x00000001 87484059Swpaul#define BGE_RXLPMODE_ENABLE 0x00000002 87584059Swpaul#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 87684059Swpaul#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 87784059Swpaul#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 87884059Swpaul 87984059Swpaul/* Receive List Placement Status register */ 88084059Swpaul#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 88184059Swpaul#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 88284059Swpaul#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 88384059Swpaul 88484059Swpaul/* 88584059Swpaul * Receive Data and Receive BD Initiator Control Registers 88684059Swpaul */ 88784059Swpaul#define BGE_RDBDI_MODE 0x2400 88884059Swpaul#define BGE_RDBDI_STATUS 0x2404 88984059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 89084059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 89184059Swpaul#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 89284059Swpaul#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 89384059Swpaul#define BGE_RX_STD_RCB_HADDR_HI 0x2450 89484059Swpaul#define BGE_RX_STD_RCB_HADDR_LO 0x2454 89584059Swpaul#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 89684059Swpaul#define BGE_RX_STD_RCB_NICADDR 0x245C 89784059Swpaul#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 89884059Swpaul#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 89984059Swpaul#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 90084059Swpaul#define BGE_RX_MINI_RCB_NICADDR 0x246C 90184059Swpaul#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 90284059Swpaul#define BGE_RDBDI_STD_RX_CONS 0x2474 90384059Swpaul#define BGE_RDBDI_MINI_RX_CONS 0x2478 90484059Swpaul#define BGE_RDBDI_RETURN_PROD0 0x2480 90584059Swpaul#define BGE_RDBDI_RETURN_PROD1 0x2484 90684059Swpaul#define BGE_RDBDI_RETURN_PROD2 0x2488 90784059Swpaul#define BGE_RDBDI_RETURN_PROD3 0x248C 90884059Swpaul#define BGE_RDBDI_RETURN_PROD4 0x2490 90984059Swpaul#define BGE_RDBDI_RETURN_PROD5 0x2494 91084059Swpaul#define BGE_RDBDI_RETURN_PROD6 0x2498 91184059Swpaul#define BGE_RDBDI_RETURN_PROD7 0x249C 91284059Swpaul#define BGE_RDBDI_RETURN_PROD8 0x24A0 91384059Swpaul#define BGE_RDBDI_RETURN_PROD9 0x24A4 91484059Swpaul#define BGE_RDBDI_RETURN_PROD10 0x24A8 91584059Swpaul#define BGE_RDBDI_RETURN_PROD11 0x24AC 91684059Swpaul#define BGE_RDBDI_RETURN_PROD12 0x24B0 91784059Swpaul#define BGE_RDBDI_RETURN_PROD13 0x24B4 91884059Swpaul#define BGE_RDBDI_RETURN_PROD14 0x24B8 91984059Swpaul#define BGE_RDBDI_RETURN_PROD15 0x24BC 92084059Swpaul#define BGE_RDBDI_HWDIAG 0x24C0 92184059Swpaul 92284059Swpaul 92384059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 92484059Swpaul#define BGE_RDBDIMODE_RESET 0x00000001 92584059Swpaul#define BGE_RDBDIMODE_ENABLE 0x00000002 92684059Swpaul#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 92784059Swpaul#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 92884059Swpaul#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 92984059Swpaul 93084059Swpaul/* Receive Data and Receive BD Initiator Status register */ 93184059Swpaul#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 93284059Swpaul#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 93384059Swpaul#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 93484059Swpaul 93584059Swpaul 93684059Swpaul/* 93784059Swpaul * Receive Data Completion Control registers 93884059Swpaul */ 93984059Swpaul#define BGE_RDC_MODE 0x2800 94084059Swpaul 94184059Swpaul/* Receive Data Completion Mode register */ 94284059Swpaul#define BGE_RDCMODE_RESET 0x00000001 94384059Swpaul#define BGE_RDCMODE_ENABLE 0x00000002 94484059Swpaul#define BGE_RDCMODE_ATTN 0x00000004 94584059Swpaul 94684059Swpaul/* 94784059Swpaul * Receive BD Initiator Control registers 94884059Swpaul */ 94984059Swpaul#define BGE_RBDI_MODE 0x2C00 95084059Swpaul#define BGE_RBDI_STATUS 0x2C04 95184059Swpaul#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 95284059Swpaul#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 95384059Swpaul#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 95484059Swpaul#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 95584059Swpaul#define BGE_RBDI_STD_REPL_THRESH 0x2C18 95684059Swpaul#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 95784059Swpaul 95884059Swpaul/* Receive BD Initiator Mode register */ 95984059Swpaul#define BGE_RBDIMODE_RESET 0x00000001 96084059Swpaul#define BGE_RBDIMODE_ENABLE 0x00000002 96184059Swpaul#define BGE_RBDIMODE_ATTN 0x00000004 96284059Swpaul 96384059Swpaul/* Receive BD Initiator Status register */ 96484059Swpaul#define BGE_RBDISTAT_ATTN 0x00000004 96584059Swpaul 96684059Swpaul/* 96784059Swpaul * Receive BD Completion Control registers 96884059Swpaul */ 96984059Swpaul#define BGE_RBDC_MODE 0x3000 97084059Swpaul#define BGE_RBDC_STATUS 0x3004 97184059Swpaul#define BGE_RBDC_JUMBO_BD_PROD 0x3008 97284059Swpaul#define BGE_RBDC_STD_BD_PROD 0x300C 97384059Swpaul#define BGE_RBDC_MINI_BD_PROD 0x3010 97484059Swpaul 97584059Swpaul/* Receive BD completion mode register */ 97684059Swpaul#define BGE_RBDCMODE_RESET 0x00000001 97784059Swpaul#define BGE_RBDCMODE_ENABLE 0x00000002 97884059Swpaul#define BGE_RBDCMODE_ATTN 0x00000004 97984059Swpaul 98084059Swpaul/* Receive BD completion status register */ 98184059Swpaul#define BGE_RBDCSTAT_ERROR 0x00000004 98284059Swpaul 98384059Swpaul/* 98484059Swpaul * Receive List Selector Control registers 98584059Swpaul */ 98684059Swpaul#define BGE_RXLS_MODE 0x3400 98784059Swpaul#define BGE_RXLS_STATUS 0x3404 98884059Swpaul 98984059Swpaul/* Receive List Selector Mode register */ 99084059Swpaul#define BGE_RXLSMODE_RESET 0x00000001 99184059Swpaul#define BGE_RXLSMODE_ENABLE 0x00000002 99284059Swpaul#define BGE_RXLSMODE_ATTN 0x00000004 99384059Swpaul 99484059Swpaul/* Receive List Selector Status register */ 99584059Swpaul#define BGE_RXLSSTAT_ERROR 0x00000004 99684059Swpaul 99784059Swpaul/* 99884059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 99984059Swpaul */ 100084059Swpaul#define BGE_MBCF_MODE 0x3800 100184059Swpaul#define BGE_MBCF_STATUS 0x3804 100284059Swpaul 100384059Swpaul/* Mbuf Cluster Free mode register */ 100484059Swpaul#define BGE_MBCFMODE_RESET 0x00000001 100584059Swpaul#define BGE_MBCFMODE_ENABLE 0x00000002 100684059Swpaul#define BGE_MBCFMODE_ATTN 0x00000004 100784059Swpaul 100884059Swpaul/* Mbuf Cluster Free status register */ 100984059Swpaul#define BGE_MBCFSTAT_ERROR 0x00000004 101084059Swpaul 101184059Swpaul/* 101284059Swpaul * Host Coalescing Control registers 101384059Swpaul */ 101484059Swpaul#define BGE_HCC_MODE 0x3C00 101584059Swpaul#define BGE_HCC_STATUS 0x3C04 101684059Swpaul#define BGE_HCC_RX_COAL_TICKS 0x3C08 101784059Swpaul#define BGE_HCC_TX_COAL_TICKS 0x3C0C 101884059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 101984059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 102084059Swpaul#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 102184059Swpaul#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 102284059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 102384059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 102484059Swpaul#define BGE_HCC_STATS_TICKS 0x3C28 102584059Swpaul#define BGE_HCC_STATS_ADDR_HI 0x3C30 102684059Swpaul#define BGE_HCC_STATS_ADDR_LO 0x3C34 102784059Swpaul#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 102884059Swpaul#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 102984059Swpaul#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 103084059Swpaul#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 103184059Swpaul#define BGE_FLOW_ATTN 0x3C48 103284059Swpaul#define BGE_HCC_JUMBO_BD_CONS 0x3C50 103384059Swpaul#define BGE_HCC_STD_BD_CONS 0x3C54 103484059Swpaul#define BGE_HCC_MINI_BD_CONS 0x3C58 103584059Swpaul#define BGE_HCC_RX_RETURN_PROD0 0x3C80 103684059Swpaul#define BGE_HCC_RX_RETURN_PROD1 0x3C84 103784059Swpaul#define BGE_HCC_RX_RETURN_PROD2 0x3C88 103884059Swpaul#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 103984059Swpaul#define BGE_HCC_RX_RETURN_PROD4 0x3C90 104084059Swpaul#define BGE_HCC_RX_RETURN_PROD5 0x3C94 104184059Swpaul#define BGE_HCC_RX_RETURN_PROD6 0x3C98 104284059Swpaul#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 104384059Swpaul#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 104484059Swpaul#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 104584059Swpaul#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 104684059Swpaul#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 104784059Swpaul#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 104884059Swpaul#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 104984059Swpaul#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 105084059Swpaul#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 105184059Swpaul#define BGE_HCC_TX_BD_CONS0 0x3CC0 105284059Swpaul#define BGE_HCC_TX_BD_CONS1 0x3CC4 105384059Swpaul#define BGE_HCC_TX_BD_CONS2 0x3CC8 105484059Swpaul#define BGE_HCC_TX_BD_CONS3 0x3CCC 105584059Swpaul#define BGE_HCC_TX_BD_CONS4 0x3CD0 105684059Swpaul#define BGE_HCC_TX_BD_CONS5 0x3CD4 105784059Swpaul#define BGE_HCC_TX_BD_CONS6 0x3CD8 105884059Swpaul#define BGE_HCC_TX_BD_CONS7 0x3CDC 105984059Swpaul#define BGE_HCC_TX_BD_CONS8 0x3CE0 106084059Swpaul#define BGE_HCC_TX_BD_CONS9 0x3CE4 106184059Swpaul#define BGE_HCC_TX_BD_CONS10 0x3CE8 106284059Swpaul#define BGE_HCC_TX_BD_CONS11 0x3CEC 106384059Swpaul#define BGE_HCC_TX_BD_CONS12 0x3CF0 106484059Swpaul#define BGE_HCC_TX_BD_CONS13 0x3CF4 106584059Swpaul#define BGE_HCC_TX_BD_CONS14 0x3CF8 106684059Swpaul#define BGE_HCC_TX_BD_CONS15 0x3CFC 106784059Swpaul 106884059Swpaul 106984059Swpaul/* Host coalescing mode register */ 107084059Swpaul#define BGE_HCCMODE_RESET 0x00000001 107184059Swpaul#define BGE_HCCMODE_ENABLE 0x00000002 107284059Swpaul#define BGE_HCCMODE_ATTN 0x00000004 107384059Swpaul#define BGE_HCCMODE_COAL_NOW 0x00000008 107484059Swpaul#define BGE_HCCMODE_MSI_BITS 0x0x000070 107584059Swpaul#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 107684059Swpaul 107784059Swpaul#define BGE_STATBLKSZ_FULL 0x00000000 107884059Swpaul#define BGE_STATBLKSZ_64BYTE 0x00000080 107984059Swpaul#define BGE_STATBLKSZ_32BYTE 0x00000100 108084059Swpaul 108184059Swpaul/* Host coalescing status register */ 108284059Swpaul#define BGE_HCCSTAT_ERROR 0x00000004 108384059Swpaul 108484059Swpaul/* Flow attention register */ 108584059Swpaul#define BGE_FLOWATTN_MB_LOWAT 0x00000040 108684059Swpaul#define BGE_FLOWATTN_MEMARB 0x00000080 108784059Swpaul#define BGE_FLOWATTN_HOSTCOAL 0x00008000 108884059Swpaul#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 108984059Swpaul#define BGE_FLOWATTN_RCB_INVAL 0x00020000 109084059Swpaul#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 109184059Swpaul#define BGE_FLOWATTN_RDBDI 0x00080000 109284059Swpaul#define BGE_FLOWATTN_RXLS 0x00100000 109384059Swpaul#define BGE_FLOWATTN_RXLP 0x00200000 109484059Swpaul#define BGE_FLOWATTN_RBDC 0x00400000 109584059Swpaul#define BGE_FLOWATTN_RBDI 0x00800000 109684059Swpaul#define BGE_FLOWATTN_SDC 0x08000000 109784059Swpaul#define BGE_FLOWATTN_SDI 0x10000000 109884059Swpaul#define BGE_FLOWATTN_SRS 0x20000000 109984059Swpaul#define BGE_FLOWATTN_SBDC 0x40000000 110084059Swpaul#define BGE_FLOWATTN_SBDI 0x80000000 110184059Swpaul 110284059Swpaul/* 110384059Swpaul * Memory arbiter registers 110484059Swpaul */ 110584059Swpaul#define BGE_MARB_MODE 0x4000 110684059Swpaul#define BGE_MARB_STATUS 0x4004 110784059Swpaul#define BGE_MARB_TRAPADDR_HI 0x4008 110884059Swpaul#define BGE_MARB_TRAPADDR_LO 0x400C 110984059Swpaul 111084059Swpaul/* Memory arbiter mode register */ 111184059Swpaul#define BGE_MARBMODE_RESET 0x00000001 111284059Swpaul#define BGE_MARBMODE_ENABLE 0x00000002 111384059Swpaul#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 111484059Swpaul#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 111584059Swpaul#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 111684059Swpaul#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 111784059Swpaul#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 111884059Swpaul#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 111984059Swpaul#define BGE_MARBMODE_PCI_TRAP 0x00000100 112084059Swpaul#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 112184059Swpaul#define BGE_MARBMODE_RXQ_TRAP 0x00000400 112284059Swpaul#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 112384059Swpaul#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 112484059Swpaul#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 112584059Swpaul#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 112684059Swpaul#define BGE_MARBMODE_MBUF_TRAP 0x00008000 112784059Swpaul#define BGE_MARBMODE_TXDI_TRAP 0x00010000 112884059Swpaul#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 112984059Swpaul#define BGE_MARBMODE_TXBD_TRAP 0x00040000 113084059Swpaul#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 113184059Swpaul#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 113284059Swpaul#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 113384059Swpaul#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 113484059Swpaul#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 113584059Swpaul#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 113684059Swpaul#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 113784059Swpaul 113884059Swpaul/* Memory arbiter status register */ 113984059Swpaul#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 114084059Swpaul#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 114184059Swpaul#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 114284059Swpaul#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 114384059Swpaul#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 114484059Swpaul#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 114584059Swpaul#define BGE_MARBSTAT_PCI_TRAP 0x00000100 114684059Swpaul#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 114784059Swpaul#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 114884059Swpaul#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 114984059Swpaul#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 115084059Swpaul#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 115184059Swpaul#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 115284059Swpaul#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 115384059Swpaul#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 115484059Swpaul#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 115584059Swpaul#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 115684059Swpaul#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 115784059Swpaul#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 115884059Swpaul#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 115984059Swpaul#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 116084059Swpaul#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 116184059Swpaul#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 116284059Swpaul#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 116384059Swpaul 116484059Swpaul/* 116584059Swpaul * Buffer manager control registers 116684059Swpaul */ 116784059Swpaul#define BGE_BMAN_MODE 0x4400 116884059Swpaul#define BGE_BMAN_STATUS 0x4404 116984059Swpaul#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 117084059Swpaul#define BGE_BMAN_MBUFPOOL_LEN 0x440C 117184059Swpaul#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 117284059Swpaul#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 117384059Swpaul#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 117484059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 117584059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 117684059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 117784059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 117884059Swpaul#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 117984059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 118084059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 118184059Swpaul#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 118284059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 118384059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 118484059Swpaul#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 118584059Swpaul#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 118684059Swpaul#define BGE_BMAN_HWDIAG_1 0x444C 118784059Swpaul#define BGE_BMAN_HWDIAG_2 0x4450 118884059Swpaul#define BGE_BMAN_HWDIAG_3 0x4454 118984059Swpaul 119084059Swpaul/* Buffer manager mode register */ 119184059Swpaul#define BGE_BMANMODE_RESET 0x00000001 119284059Swpaul#define BGE_BMANMODE_ENABLE 0x00000002 119384059Swpaul#define BGE_BMANMODE_ATTN 0x00000004 119484059Swpaul#define BGE_BMANMODE_TESTMODE 0x00000008 119584059Swpaul#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 119684059Swpaul 119784059Swpaul/* Buffer manager status register */ 119884059Swpaul#define BGE_BMANSTAT_ERRO 0x00000004 119984059Swpaul#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 120084059Swpaul 120184059Swpaul 120284059Swpaul/* 120384059Swpaul * Read DMA Control registers 120484059Swpaul */ 120584059Swpaul#define BGE_RDMA_MODE 0x4800 120684059Swpaul#define BGE_RDMA_STATUS 0x4804 120784059Swpaul 120884059Swpaul/* Read DMA mode register */ 120984059Swpaul#define BGE_RDMAMODE_RESET 0x00000001 121084059Swpaul#define BGE_RDMAMODE_ENABLE 0x00000002 121184059Swpaul#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 121284059Swpaul#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 121384059Swpaul#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 121484059Swpaul#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 121584059Swpaul#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 121684059Swpaul#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 121784059Swpaul#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 121884059Swpaul#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 121984059Swpaul#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 122084059Swpaul 122184059Swpaul/* Read DMA status register */ 122284059Swpaul#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 122384059Swpaul#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 122484059Swpaul#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 122584059Swpaul#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 122684059Swpaul#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 122784059Swpaul#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 122884059Swpaul#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 122984059Swpaul#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 123084059Swpaul 123184059Swpaul/* 123284059Swpaul * Write DMA control registers 123384059Swpaul */ 123484059Swpaul#define BGE_WDMA_MODE 0x4C00 123584059Swpaul#define BGE_WDMA_STATUS 0x4C04 123684059Swpaul 123784059Swpaul/* Write DMA mode register */ 123884059Swpaul#define BGE_WDMAMODE_RESET 0x00000001 123984059Swpaul#define BGE_WDMAMODE_ENABLE 0x00000002 124084059Swpaul#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 124184059Swpaul#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 124284059Swpaul#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 124384059Swpaul#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 124484059Swpaul#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 124584059Swpaul#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 124684059Swpaul#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 124784059Swpaul#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 124884059Swpaul#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 124984059Swpaul 125084059Swpaul/* Write DMA status register */ 125184059Swpaul#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 125284059Swpaul#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 125384059Swpaul#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 125484059Swpaul#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 125584059Swpaul#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 125684059Swpaul#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 125784059Swpaul#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 125884059Swpaul#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 125984059Swpaul 126084059Swpaul 126184059Swpaul/* 126284059Swpaul * RX CPU registers 126384059Swpaul */ 126484059Swpaul#define BGE_RXCPU_MODE 0x5000 126584059Swpaul#define BGE_RXCPU_STATUS 0x5004 126684059Swpaul#define BGE_RXCPU_PC 0x501C 126784059Swpaul 126884059Swpaul/* RX CPU mode register */ 126984059Swpaul#define BGE_RXCPUMODE_RESET 0x00000001 127084059Swpaul#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 127184059Swpaul#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 127284059Swpaul#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 127384059Swpaul#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 127484059Swpaul#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 127584059Swpaul#define BGE_RXCPUMODE_ROMFAIL 0x00000040 127684059Swpaul#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 127784059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 127884059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 127984059Swpaul#define BGE_RXCPUMODE_HALTCPU 0x00000400 128084059Swpaul#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 128184059Swpaul#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 128284059Swpaul#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 128384059Swpaul 128484059Swpaul/* RX CPU status register */ 128584059Swpaul#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 128684059Swpaul#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 128784059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 128884059Swpaul#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 128984059Swpaul#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 129084059Swpaul#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 129184059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 129284059Swpaul#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 129384059Swpaul#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 129484059Swpaul#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 129584059Swpaul#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 129684059Swpaul#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 129784059Swpaul#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 129884059Swpaul#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 129984059Swpaul#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 130084059Swpaul#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 130184059Swpaul#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 130284059Swpaul 130384059Swpaul 130484059Swpaul/* 130584059Swpaul * TX CPU registers 130684059Swpaul */ 130784059Swpaul#define BGE_TXCPU_MODE 0x5400 130884059Swpaul#define BGE_TXCPU_STATUS 0x5404 130984059Swpaul#define BGE_TXCPU_PC 0x541C 131084059Swpaul 131184059Swpaul/* TX CPU mode register */ 131284059Swpaul#define BGE_TXCPUMODE_RESET 0x00000001 131384059Swpaul#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 131484059Swpaul#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 131584059Swpaul#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 131684059Swpaul#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 131784059Swpaul#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 131884059Swpaul#define BGE_TXCPUMODE_ROMFAIL 0x00000040 131984059Swpaul#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 132084059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 132184059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 132284059Swpaul#define BGE_TXCPUMODE_HALTCPU 0x00000400 132384059Swpaul#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 132484059Swpaul#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 132584059Swpaul 132684059Swpaul/* TX CPU status register */ 132784059Swpaul#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 132884059Swpaul#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 132984059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 133084059Swpaul#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 133184059Swpaul#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 133284059Swpaul#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 133384059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 133484059Swpaul#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 133584059Swpaul#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 133684059Swpaul#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 133784059Swpaul#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 133884059Swpaul#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 133984059Swpaul#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 134084059Swpaul#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 134184059Swpaul#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 134284059Swpaul#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 134384059Swpaul#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 134484059Swpaul 134584059Swpaul 134684059Swpaul/* 134784059Swpaul * Low priority mailbox registers 134884059Swpaul */ 134984059Swpaul#define BGE_LPMBX_IRQ0_HI 0x5800 135084059Swpaul#define BGE_LPMBX_IRQ0_LO 0x5804 135184059Swpaul#define BGE_LPMBX_IRQ1_HI 0x5808 135284059Swpaul#define BGE_LPMBX_IRQ1_LO 0x580C 135384059Swpaul#define BGE_LPMBX_IRQ2_HI 0x5810 135484059Swpaul#define BGE_LPMBX_IRQ2_LO 0x5814 135584059Swpaul#define BGE_LPMBX_IRQ3_HI 0x5818 135684059Swpaul#define BGE_LPMBX_IRQ3_LO 0x581C 135784059Swpaul#define BGE_LPMBX_GEN0_HI 0x5820 135884059Swpaul#define BGE_LPMBX_GEN0_LO 0x5824 135984059Swpaul#define BGE_LPMBX_GEN1_HI 0x5828 136084059Swpaul#define BGE_LPMBX_GEN1_LO 0x582C 136184059Swpaul#define BGE_LPMBX_GEN2_HI 0x5830 136284059Swpaul#define BGE_LPMBX_GEN2_LO 0x5834 136384059Swpaul#define BGE_LPMBX_GEN3_HI 0x5828 136484059Swpaul#define BGE_LPMBX_GEN3_LO 0x582C 136584059Swpaul#define BGE_LPMBX_GEN4_HI 0x5840 136684059Swpaul#define BGE_LPMBX_GEN4_LO 0x5844 136784059Swpaul#define BGE_LPMBX_GEN5_HI 0x5848 136884059Swpaul#define BGE_LPMBX_GEN5_LO 0x584C 136984059Swpaul#define BGE_LPMBX_GEN6_HI 0x5850 137084059Swpaul#define BGE_LPMBX_GEN6_LO 0x5854 137184059Swpaul#define BGE_LPMBX_GEN7_HI 0x5858 137284059Swpaul#define BGE_LPMBX_GEN7_LO 0x585C 137384059Swpaul#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 137484059Swpaul#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 137584059Swpaul#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 137684059Swpaul#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 137784059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 137884059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 137984059Swpaul#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 138084059Swpaul#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 138184059Swpaul#define BGE_LPMBX_RX_CONS0_HI 0x5880 138284059Swpaul#define BGE_LPMBX_RX_CONS0_LO 0x5884 138384059Swpaul#define BGE_LPMBX_RX_CONS1_HI 0x5888 138484059Swpaul#define BGE_LPMBX_RX_CONS1_LO 0x588C 138584059Swpaul#define BGE_LPMBX_RX_CONS2_HI 0x5890 138684059Swpaul#define BGE_LPMBX_RX_CONS2_LO 0x5894 138784059Swpaul#define BGE_LPMBX_RX_CONS3_HI 0x5898 138884059Swpaul#define BGE_LPMBX_RX_CONS3_LO 0x589C 138984059Swpaul#define BGE_LPMBX_RX_CONS4_HI 0x58A0 139084059Swpaul#define BGE_LPMBX_RX_CONS4_LO 0x58A4 139184059Swpaul#define BGE_LPMBX_RX_CONS5_HI 0x58A8 139284059Swpaul#define BGE_LPMBX_RX_CONS5_LO 0x58AC 139384059Swpaul#define BGE_LPMBX_RX_CONS6_HI 0x58B0 139484059Swpaul#define BGE_LPMBX_RX_CONS6_LO 0x58B4 139584059Swpaul#define BGE_LPMBX_RX_CONS7_HI 0x58B8 139684059Swpaul#define BGE_LPMBX_RX_CONS7_LO 0x58BC 139784059Swpaul#define BGE_LPMBX_RX_CONS8_HI 0x58C0 139884059Swpaul#define BGE_LPMBX_RX_CONS8_LO 0x58C4 139984059Swpaul#define BGE_LPMBX_RX_CONS9_HI 0x58C8 140084059Swpaul#define BGE_LPMBX_RX_CONS9_LO 0x58CC 140184059Swpaul#define BGE_LPMBX_RX_CONS10_HI 0x58D0 140284059Swpaul#define BGE_LPMBX_RX_CONS10_LO 0x58D4 140384059Swpaul#define BGE_LPMBX_RX_CONS11_HI 0x58D8 140484059Swpaul#define BGE_LPMBX_RX_CONS11_LO 0x58DC 140584059Swpaul#define BGE_LPMBX_RX_CONS12_HI 0x58E0 140684059Swpaul#define BGE_LPMBX_RX_CONS12_LO 0x58E4 140784059Swpaul#define BGE_LPMBX_RX_CONS13_HI 0x58E8 140884059Swpaul#define BGE_LPMBX_RX_CONS13_LO 0x58EC 140984059Swpaul#define BGE_LPMBX_RX_CONS14_HI 0x58F0 141084059Swpaul#define BGE_LPMBX_RX_CONS14_LO 0x58F4 141184059Swpaul#define BGE_LPMBX_RX_CONS15_HI 0x58F8 141284059Swpaul#define BGE_LPMBX_RX_CONS15_LO 0x58FC 141384059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 141484059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 141584059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 141684059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 141784059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 141884059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 141984059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 142084059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 142184059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 142284059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 142384059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 142484059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 142584059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 142684059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 142784059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 142884059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 142984059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 143084059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 143184059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 143284059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 143384059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 143484059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 143584059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 143684059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 143784059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 143884059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 143984059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 144084059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 144184059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 144284059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 144384059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 144484059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 144584059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 144684059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 144784059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 144884059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 144984059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 145084059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 145184059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 145284059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 145384059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 145484059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 145584059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 145684059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 145784059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 145884059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 145984059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 146084059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 146184059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 146284059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 146384059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 146484059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 146584059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 146684059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 146784059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 146884059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 146984059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 147084059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 147184059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 147284059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 147384059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 147484059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 147584059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 147684059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 147784059Swpaul 147884059Swpaul/* 147984059Swpaul * Flow throw Queue reset register 148084059Swpaul */ 148184059Swpaul#define BGE_FTQ_RESET 0x5C00 148284059Swpaul 148384059Swpaul#define BGE_FTQRESET_DMAREAD 0x00000002 148484059Swpaul#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 148584059Swpaul#define BGE_FTQRESET_DMADONE 0x00000010 148684059Swpaul#define BGE_FTQRESET_SBDC 0x00000020 148784059Swpaul#define BGE_FTQRESET_SDI 0x00000040 148884059Swpaul#define BGE_FTQRESET_WDMA 0x00000080 148984059Swpaul#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 149084059Swpaul#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 149184059Swpaul#define BGE_FTQRESET_SDC 0x00000400 149284059Swpaul#define BGE_FTQRESET_HCC 0x00000800 149384059Swpaul#define BGE_FTQRESET_TXFIFO 0x00001000 149484059Swpaul#define BGE_FTQRESET_MBC 0x00002000 149584059Swpaul#define BGE_FTQRESET_RBDC 0x00004000 149684059Swpaul#define BGE_FTQRESET_RXLP 0x00008000 149784059Swpaul#define BGE_FTQRESET_RDBDI 0x00010000 149884059Swpaul#define BGE_FTQRESET_RDC 0x00020000 149984059Swpaul#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 150084059Swpaul 150184059Swpaul/* 150284059Swpaul * Message Signaled Interrupt registers 150384059Swpaul */ 150484059Swpaul#define BGE_MSI_MODE 0x6000 150584059Swpaul#define BGE_MSI_STATUS 0x6004 150684059Swpaul#define BGE_MSI_FIFOACCESS 0x6008 150784059Swpaul 150884059Swpaul/* MSI mode register */ 150984059Swpaul#define BGE_MSIMODE_RESET 0x00000001 151084059Swpaul#define BGE_MSIMODE_ENABLE 0x00000002 151184059Swpaul#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 151284059Swpaul#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 151384059Swpaul#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 151484059Swpaul#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 151584059Swpaul#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 151684059Swpaul 151784059Swpaul/* MSI status register */ 151884059Swpaul#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 151984059Swpaul#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 152084059Swpaul#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 152184059Swpaul#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 152284059Swpaul#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 152384059Swpaul 152484059Swpaul 152584059Swpaul/* 152684059Swpaul * DMA Completion registers 152784059Swpaul */ 152884059Swpaul#define BGE_DMAC_MODE 0x6400 152984059Swpaul 153084059Swpaul/* DMA Completion mode register */ 153184059Swpaul#define BGE_DMACMODE_RESET 0x00000001 153284059Swpaul#define BGE_DMACMODE_ENABLE 0x00000002 153384059Swpaul 153484059Swpaul 153584059Swpaul/* 153684059Swpaul * General control registers. 153784059Swpaul */ 153884059Swpaul#define BGE_MODE_CTL 0x6800 153984059Swpaul#define BGE_MISC_CFG 0x6804 154084059Swpaul#define BGE_MISC_LOCAL_CTL 0x6808 154184059Swpaul#define BGE_EE_ADDR 0x6838 154284059Swpaul#define BGE_EE_DATA 0x683C 154384059Swpaul#define BGE_EE_CTL 0x6840 154484059Swpaul#define BGE_MDI_CTL 0x6844 154584059Swpaul#define BGE_EE_DELAY 0x6848 154684059Swpaul 154784059Swpaul/* Mode control register */ 154884059Swpaul#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 154984059Swpaul#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 155084059Swpaul#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 155184059Swpaul#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 155284059Swpaul#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 155384059Swpaul#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 155484059Swpaul#define BGE_MODECTL_NO_RX_CRC 0x00000400 155584059Swpaul#define BGE_MODECTL_RX_BADFRAMES 0x00000800 155684059Swpaul#define BGE_MODECTL_NO_TX_INTR 0x00002000 155784059Swpaul#define BGE_MODECTL_NO_RX_INTR 0x00004000 155884059Swpaul#define BGE_MODECTL_FORCE_PCI32 0x00008000 155984059Swpaul#define BGE_MODECTL_STACKUP 0x00010000 156084059Swpaul#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 156184059Swpaul#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 156284059Swpaul#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 156384059Swpaul#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 156484059Swpaul#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 156584059Swpaul#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 156684059Swpaul#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 156784059Swpaul#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 156884059Swpaul#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 156984059Swpaul#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 157084059Swpaul 157184059Swpaul/* Misc. config register */ 157284059Swpaul#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 157384059Swpaul#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 157484059Swpaul 157584059Swpaul#define BGE_32BITTIME_66MHZ (0x41 << 1) 157684059Swpaul 157784059Swpaul/* Misc. Local Control */ 157884059Swpaul#define BGE_MLC_INTR_STATE 0x00000001 157984059Swpaul#define BGE_MLC_INTR_CLR 0x00000002 158084059Swpaul#define BGE_MLC_INTR_SET 0x00000004 158184059Swpaul#define BGE_MLC_INTR_ONATTN 0x00000008 158284059Swpaul#define BGE_MLC_MISCIO_IN0 0x00000100 158384059Swpaul#define BGE_MLC_MISCIO_IN1 0x00000200 158484059Swpaul#define BGE_MLC_MISCIO_IN2 0x00000400 158584059Swpaul#define BGE_MLC_MISCIO_OUTEN0 0x00000800 158684059Swpaul#define BGE_MLC_MISCIO_OUTEN1 0x00001000 158784059Swpaul#define BGE_MLC_MISCIO_OUTEN2 0x00002000 158884059Swpaul#define BGE_MLC_MISCIO_OUT0 0x00004000 158984059Swpaul#define BGE_MLC_MISCIO_OUT1 0x00008000 159084059Swpaul#define BGE_MLC_MISCIO_OUT2 0x00010000 159184059Swpaul#define BGE_MLC_EXTRAM_ENB 0x00020000 159284059Swpaul#define BGE_MLC_SRAM_SIZE 0x001C0000 159384059Swpaul#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 159484059Swpaul#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 159584059Swpaul#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 159684059Swpaul#define BGE_MLC_AUTO_EEPROM 0x01000000 159784059Swpaul 159884059Swpaul#define BGE_SSRAMSIZE_256KB 0x00000000 159984059Swpaul#define BGE_SSRAMSIZE_512KB 0x00040000 160084059Swpaul#define BGE_SSRAMSIZE_1MB 0x00080000 160184059Swpaul#define BGE_SSRAMSIZE_2MB 0x000C0000 160284059Swpaul#define BGE_SSRAMSIZE_4MB 0x00100000 160384059Swpaul#define BGE_SSRAMSIZE_8MB 0x00140000 160484059Swpaul#define BGE_SSRAMSIZE_16M 0x00180000 160584059Swpaul 160684059Swpaul/* EEPROM address register */ 160784059Swpaul#define BGE_EEADDR_ADDRESS 0x0000FFFC 160884059Swpaul#define BGE_EEADDR_HALFCLK 0x01FF0000 160984059Swpaul#define BGE_EEADDR_START 0x02000000 161084059Swpaul#define BGE_EEADDR_DEVID 0x1C000000 161184059Swpaul#define BGE_EEADDR_RESET 0x20000000 161284059Swpaul#define BGE_EEADDR_DONE 0x40000000 161384059Swpaul#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 161484059Swpaul 161584059Swpaul#define BGE_EEDEVID(x) ((x & 7) << 26) 161684059Swpaul#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 161784059Swpaul#define BGE_HALFCLK_384SCL 0x60 161884059Swpaul#define BGE_EE_READCMD \ 161984059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 162084059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 162184059Swpaul#define BGE_EE_WRCMD \ 162284059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 162384059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 162484059Swpaul 162584059Swpaul/* EEPROM Control register */ 162684059Swpaul#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 162784059Swpaul#define BGE_EECTL_CLKOUT 0x00000002 162884059Swpaul#define BGE_EECTL_CLKIN 0x00000004 162984059Swpaul#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 163084059Swpaul#define BGE_EECTL_DATAOUT 0x00000010 163184059Swpaul#define BGE_EECTL_DATAIN 0x00000020 163284059Swpaul 163384059Swpaul/* MDI (MII/GMII) access register */ 163484059Swpaul#define BGE_MDI_DATA 0x00000001 163584059Swpaul#define BGE_MDI_DIR 0x00000002 163684059Swpaul#define BGE_MDI_SEL 0x00000004 163784059Swpaul#define BGE_MDI_CLK 0x00000008 163884059Swpaul 163984059Swpaul#define BGE_MEMWIN_START 0x00008000 164084059Swpaul#define BGE_MEMWIN_END 0x0000FFFF 164184059Swpaul 164284059Swpaul 164384059Swpaul#define BGE_MEMWIN_READ(sc, x, val) \ 164484059Swpaul do { \ 164584059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 164684059Swpaul (0xFFFF0000 & x), 4); \ 164784059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 164884059Swpaul } while(0) 164984059Swpaul 165084059Swpaul#define BGE_MEMWIN_WRITE(sc, x, val) \ 165184059Swpaul do { \ 165284059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 165384059Swpaul (0xFFFF0000 & x), 4); \ 165484059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 165584059Swpaul } while(0) 165684059Swpaul 165784059Swpaul/* 165884059Swpaul * This magic number is used to prevent PXE restart when we 165984059Swpaul * issue a software reset. We write this magic number to the 166084059Swpaul * firmware mailbox at 0xB50 in order to prevent the PXE boot 166184059Swpaul * code from running. 166284059Swpaul */ 166384059Swpaul#define BGE_MAGIC_NUMBER 0x4B657654 166484059Swpaul 166584059Swpaultypedef struct { 166684059Swpaul u_int32_t bge_addr_hi; 166784059Swpaul u_int32_t bge_addr_lo; 166884059Swpaul} bge_hostaddr; 166984059Swpaul#define BGE_HOSTADDR(x) x.bge_addr_lo 167084059Swpaul 167184059Swpaul/* Ring control block structure */ 167284059Swpaulstruct bge_rcb { 167384059Swpaul bge_hostaddr bge_hostaddr; 167484059Swpaul u_int16_t bge_flags; 167584059Swpaul u_int16_t bge_max_len; 167684059Swpaul u_int32_t bge_nicaddr; 167784059Swpaul}; 167884059Swpaul 167984059Swpaulstruct bge_rcb_opaque { 168084059Swpaul u_int32_t bge_reg0; 168184059Swpaul u_int32_t bge_reg1; 168284059Swpaul u_int32_t bge_reg2; 168384059Swpaul u_int32_t bge_reg3; 168484059Swpaul}; 168584059Swpaul 168684059Swpaul#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 168784059Swpaul#define BGE_RCB_FLAG_RING_DISABLED 0x0002 168884059Swpaul 168984059Swpaulstruct bge_tx_bd { 169084059Swpaul bge_hostaddr bge_addr; 169184059Swpaul u_int16_t bge_flags; 169284059Swpaul u_int16_t bge_len; 169384059Swpaul u_int16_t bge_vlan_tag; 169484059Swpaul u_int16_t bge_rsvd; 169584059Swpaul}; 169684059Swpaul 169784059Swpaul#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 169884059Swpaul#define BGE_TXBDFLAG_IP_CSUM 0x0002 169984059Swpaul#define BGE_TXBDFLAG_END 0x0004 170084059Swpaul#define BGE_TXBDFLAG_IP_FRAG 0x0008 170184059Swpaul#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 170284059Swpaul#define BGE_TXBDFLAG_VLAN_TAG 0x0040 170384059Swpaul#define BGE_TXBDFLAG_COAL_NOW 0x0080 170484059Swpaul#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 170584059Swpaul#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 170684059Swpaul#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 170784059Swpaul#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 170884059Swpaul#define BGE_TXBDFLAG_NO_CRC 0x8000 170984059Swpaul 171084059Swpaul#define BGE_NIC_TXRING_ADDR(ringno, size) \ 171184059Swpaul BGE_SEND_RING_1_TO_4 + \ 171284059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 171384059Swpaul 171484059Swpaulstruct bge_rx_bd { 171584059Swpaul bge_hostaddr bge_addr; 171684059Swpaul u_int16_t bge_len; 171784059Swpaul u_int16_t bge_idx; 171884059Swpaul u_int16_t bge_flags; 171984059Swpaul u_int16_t bge_type; 172084059Swpaul u_int16_t bge_tcp_udp_csum; 172184059Swpaul u_int16_t bge_ip_csum; 172284059Swpaul u_int16_t bge_vlan_tag; 172384059Swpaul u_int16_t bge_error_flag; 172484059Swpaul u_int32_t bge_rsvd; 172584059Swpaul u_int32_t bge_opaque; 172684059Swpaul}; 172784059Swpaul 172884059Swpaul#define BGE_RXBDFLAG_END 0x0004 172984059Swpaul#define BGE_RXBDFLAG_JUMBO_RING 0x0020 173084059Swpaul#define BGE_RXBDFLAG_VLAN_TAG 0x0040 173184059Swpaul#define BGE_RXBDFLAG_ERROR 0x0400 173284059Swpaul#define BGE_RXBDFLAG_MINI_RING 0x0800 173384059Swpaul#define BGE_RXBDFLAG_IP_CSUM 0x1000 173484059Swpaul#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 173584059Swpaul#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 173684059Swpaul 173784059Swpaul#define BGE_RXERRFLAG_BAD_CRC 0x0001 173884059Swpaul#define BGE_RXERRFLAG_COLL_DETECT 0x0002 173984059Swpaul#define BGE_RXERRFLAG_LINK_LOST 0x0004 174084059Swpaul#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 174184059Swpaul#define BGE_RXERRFLAG_MAC_ABORT 0x0010 174284059Swpaul#define BGE_RXERRFLAG_RUNT 0x0020 174384059Swpaul#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 174484059Swpaul#define BGE_RXERRFLAG_GIANT 0x0080 174584059Swpaul 174684059Swpaulstruct bge_sts_idx { 174784059Swpaul u_int16_t bge_rx_prod_idx; 174884059Swpaul u_int16_t bge_tx_cons_idx; 174984059Swpaul}; 175084059Swpaul 175184059Swpaulstruct bge_status_block { 175284059Swpaul u_int32_t bge_status; 175384059Swpaul u_int32_t bge_rsvd0; 175484059Swpaul u_int16_t bge_rx_jumbo_cons_idx; 175584059Swpaul u_int16_t bge_rx_std_cons_idx; 175684059Swpaul u_int16_t bge_rx_mini_cons_idx; 175784059Swpaul u_int16_t bge_rsvd1; 175884059Swpaul struct bge_sts_idx bge_idx[16]; 175984059Swpaul}; 176084059Swpaul 176184059Swpaul#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 176284059Swpaul#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 176384059Swpaul 176484059Swpaul#define BGE_STATFLAG_UPDATED 0x00000001 176584059Swpaul#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 176684059Swpaul#define BGE_STATFLAG_ERROR 0x00000004 176784059Swpaul 176884059Swpaul 176984059Swpaul/* 177084059Swpaul * Broadcom Vendor ID 177184059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 177284059Swpaul * even though they're now manufactured by Broadcom) 177384059Swpaul */ 177484059Swpaul#define BCOM_VENDORID 0x14E4 177584059Swpaul#define BCOM_DEVICEID_BCM5700 0x1644 177684059Swpaul#define BCOM_DEVICEID_BCM5701 0x1645 177784059Swpaul 177884059Swpaul/* 177984059Swpaul * Alteon AceNIC PCI vendor/device ID. 178084059Swpaul */ 178184059Swpaul#define ALT_VENDORID 0x12AE 178284059Swpaul#define ALT_DEVICEID_ACENIC 0x0001 178384059Swpaul#define ALT_DEVICEID_ACENIC_COPPER 0x0002 178484059Swpaul#define ALT_DEVICEID_BCM5700 0x0003 178584059Swpaul#define ALT_DEVICEID_BCM5701 0x0004 178684059Swpaul 178784059Swpaul/* 178884059Swpaul * 3Com 3c985 PCI vendor/device ID. 178984059Swpaul */ 179084059Swpaul#define TC_VENDORID 0x10B7 179184059Swpaul#define TC_DEVICEID_3C985 0x0001 179284059Swpaul#define TC_DEVICEID_3C996 0x0003 179384059Swpaul 179484059Swpaul/* 179584059Swpaul * SysKonnect PCI vendor ID 179684059Swpaul */ 179784059Swpaul#define SK_VENDORID 0x1148 179884059Swpaul#define SK_DEVICEID_ALTIMA 0x4400 179984059Swpaul#define SK_SUBSYSID_9D21 0x4421 180084059Swpaul#define SK_SUBSYSID_9D41 0x4441 180184059Swpaul 180284059Swpaul/* 180384059Swpaul * Offset of MAC address inside EEPROM. 180484059Swpaul */ 180584059Swpaul#define BGE_EE_MAC_OFFSET 0x7C 180684059Swpaul#define BGE_EE_HWCFG_OFFSET 0xC8 180784059Swpaul 180884059Swpaul#define BGE_PCI_READ_CMD 0x06000000 180984059Swpaul#define BGE_PCI_WRITE_CMD 0x70000000 181084059Swpaul 181184059Swpaul#define BGE_TICKS_PER_SEC 1000000 181284059Swpaul 181384059Swpaul/* 181484059Swpaul * Ring size constants. 181584059Swpaul */ 181684059Swpaul#define BGE_EVENT_RING_CNT 256 181784059Swpaul#define BGE_CMD_RING_CNT 64 181884059Swpaul#define BGE_STD_RX_RING_CNT 512 181984059Swpaul#define BGE_JUMBO_RX_RING_CNT 256 182084059Swpaul#define BGE_MINI_RX_RING_CNT 1024 182184059Swpaul#define BGE_RETURN_RING_CNT 1024 182284059Swpaul 182384059Swpaul/* 182484059Swpaul * Possible TX ring sizes. 182584059Swpaul */ 182684059Swpaul#define BGE_TX_RING_CNT_128 128 182784059Swpaul#define BGE_TX_RING_BASE_128 0x3800 182884059Swpaul 182984059Swpaul#define BGE_TX_RING_CNT_256 256 183084059Swpaul#define BGE_TX_RING_BASE_256 0x3000 183184059Swpaul 183284059Swpaul#define BGE_TX_RING_CNT_512 512 183384059Swpaul#define BGE_TX_RING_BASE_512 0x2000 183484059Swpaul 183584059Swpaul#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 183684059Swpaul#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 183784059Swpaul 183884059Swpaul/* 183984059Swpaul * Tigon III statistics counters. 184084059Swpaul */ 184184059Swpaulstruct bge_stats { 184284059Swpaul u_int8_t Reserved0[256]; 184384059Swpaul 184484059Swpaul /* Statistics maintained by Receive MAC. */ 184584059Swpaul bge_hostaddr ifHCInOctets; 184684059Swpaul bge_hostaddr Reserved1; 184784059Swpaul bge_hostaddr etherStatsFragments; 184884059Swpaul bge_hostaddr ifHCInUcastPkts; 184984059Swpaul bge_hostaddr ifHCInMulticastPkts; 185084059Swpaul bge_hostaddr ifHCInBroadcastPkts; 185184059Swpaul bge_hostaddr dot3StatsFCSErrors; 185284059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 185384059Swpaul bge_hostaddr xonPauseFramesReceived; 185484059Swpaul bge_hostaddr xoffPauseFramesReceived; 185584059Swpaul bge_hostaddr macControlFramesReceived; 185684059Swpaul bge_hostaddr xoffStateEntered; 185784059Swpaul bge_hostaddr dot3StatsFramesTooLong; 185884059Swpaul bge_hostaddr etherStatsJabbers; 185984059Swpaul bge_hostaddr etherStatsUndersizePkts; 186084059Swpaul bge_hostaddr inRangeLengthError; 186184059Swpaul bge_hostaddr outRangeLengthError; 186284059Swpaul bge_hostaddr etherStatsPkts64Octets; 186384059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 186484059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 186584059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 186684059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 186784059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 186884059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 186984059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 187084059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 187184059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 187284059Swpaul 187384059Swpaul bge_hostaddr Unused1[37]; 187484059Swpaul 187584059Swpaul /* Statistics maintained by Transmit MAC. */ 187684059Swpaul bge_hostaddr ifHCOutOctets; 187784059Swpaul bge_hostaddr Reserved2; 187884059Swpaul bge_hostaddr etherStatsCollisions; 187984059Swpaul bge_hostaddr outXonSent; 188084059Swpaul bge_hostaddr outXoffSent; 188184059Swpaul bge_hostaddr flowControlDone; 188284059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 188384059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 188484059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 188584059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 188684059Swpaul bge_hostaddr Reserved3; 188784059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 188884059Swpaul bge_hostaddr dot3StatsLateCollisions; 188984059Swpaul bge_hostaddr dot3Collided2Times; 189084059Swpaul bge_hostaddr dot3Collided3Times; 189184059Swpaul bge_hostaddr dot3Collided4Times; 189284059Swpaul bge_hostaddr dot3Collided5Times; 189384059Swpaul bge_hostaddr dot3Collided6Times; 189484059Swpaul bge_hostaddr dot3Collided7Times; 189584059Swpaul bge_hostaddr dot3Collided8Times; 189684059Swpaul bge_hostaddr dot3Collided9Times; 189784059Swpaul bge_hostaddr dot3Collided10Times; 189884059Swpaul bge_hostaddr dot3Collided11Times; 189984059Swpaul bge_hostaddr dot3Collided12Times; 190084059Swpaul bge_hostaddr dot3Collided13Times; 190184059Swpaul bge_hostaddr dot3Collided14Times; 190284059Swpaul bge_hostaddr dot3Collided15Times; 190384059Swpaul bge_hostaddr ifHCOutUcastPkts; 190484059Swpaul bge_hostaddr ifHCOutMulticastPkts; 190584059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 190684059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 190784059Swpaul bge_hostaddr ifOutDiscards; 190884059Swpaul bge_hostaddr ifOutErrors; 190984059Swpaul 191084059Swpaul bge_hostaddr Unused2[31]; 191184059Swpaul 191284059Swpaul /* Statistics maintained by Receive List Placement. */ 191384059Swpaul bge_hostaddr COSIfHCInPkts[16]; 191484059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 191584059Swpaul bge_hostaddr nicDmaWriteQueueFull; 191684059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 191784059Swpaul bge_hostaddr nicNoMoreRxBDs; 191884059Swpaul bge_hostaddr ifInDiscards; 191984059Swpaul bge_hostaddr ifInErrors; 192084059Swpaul bge_hostaddr nicRecvThresholdHit; 192184059Swpaul 192284059Swpaul bge_hostaddr Unused3[9]; 192384059Swpaul 192484059Swpaul /* Statistics maintained by Send Data Initiator. */ 192584059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 192684059Swpaul bge_hostaddr nicDmaReadQueueFull; 192784059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 192884059Swpaul bge_hostaddr nicSendDataCompQueueFull; 192984059Swpaul 193084059Swpaul /* Statistics maintained by Host Coalescing. */ 193184059Swpaul bge_hostaddr nicRingSetSendProdIndex; 193284059Swpaul bge_hostaddr nicRingStatusUpdate; 193384059Swpaul bge_hostaddr nicInterrupts; 193484059Swpaul bge_hostaddr nicAvoidedInterrupts; 193584059Swpaul bge_hostaddr nicSendThresholdHit; 193684059Swpaul 193784059Swpaul u_int8_t Reserved4[320]; 193884059Swpaul}; 193984059Swpaul 194084059Swpaul/* 194184059Swpaul * Tigon general information block. This resides in host memory 194284059Swpaul * and contains the status counters, ring control blocks and 194384059Swpaul * producer pointers. 194484059Swpaul */ 194584059Swpaul 194684059Swpaulstruct bge_gib { 194784059Swpaul struct bge_stats bge_stats; 194884059Swpaul struct bge_rcb bge_tx_rcb[16]; 194984059Swpaul struct bge_rcb bge_std_rx_rcb; 195084059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 195184059Swpaul struct bge_rcb bge_mini_rx_rcb; 195284059Swpaul struct bge_rcb bge_return_rcb; 195384059Swpaul}; 195484059Swpaul 195584059Swpaul/* 195684059Swpaul * NOTE! On the Alpha, we have an alignment constraint. 195784059Swpaul * The first thing in the packet is a 14-byte Ethernet header. 195884059Swpaul * This means that the packet is misaligned. To compensate, 195984059Swpaul * we actually offset the data 2 bytes into the cluster. This 196084059Swpaul * alignes the packet after the Ethernet header at a 32-bit 196184059Swpaul * boundary. 196284059Swpaul */ 196384059Swpaul 196484059Swpaul#define ETHER_ALIGN 2 196584059Swpaul 196684059Swpaul#define BGE_FRAMELEN 1518 196784059Swpaul#define BGE_MAX_FRAMELEN 1536 196884059Swpaul#define BGE_JUMBO_FRAMELEN 9018 196984059Swpaul#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 197084059Swpaul#define BGE_PAGE_SIZE PAGE_SIZE 197184059Swpaul#define BGE_MIN_FRAMELEN 60 197284059Swpaul 197384059Swpaul/* 197484059Swpaul * Other utility macros. 197584059Swpaul */ 197684059Swpaul#define BGE_INC(x, y) (x) = (x + 1) % y 197784059Swpaul 197884059Swpaul/* 197984059Swpaul * Vital product data and structures. 198084059Swpaul */ 198184059Swpaul#define BGE_VPD_FLAG 0x8000 198284059Swpaul 198384059Swpaul/* VPD structures */ 198484059Swpaulstruct vpd_res { 198584059Swpaul u_int8_t vr_id; 198684059Swpaul u_int8_t vr_len; 198784059Swpaul u_int8_t vr_pad; 198884059Swpaul}; 198984059Swpaul 199084059Swpaulstruct vpd_key { 199184059Swpaul char vk_key[2]; 199284059Swpaul u_int8_t vk_len; 199384059Swpaul}; 199484059Swpaul 199584059Swpaul#define VPD_RES_ID 0x82 /* ID string */ 199684059Swpaul#define VPD_RES_READ 0x90 /* start of read only area */ 199784059Swpaul#define VPD_RES_WRITE 0x81 /* start of read/write area */ 199884059Swpaul#define VPD_RES_END 0x78 /* end tag */ 199984059Swpaul 200084059Swpaul 200184059Swpaul/* 200284059Swpaul * Register access macros. The Tigon always uses memory mapped register 200384059Swpaul * accesses and all registers must be accessed with 32 bit operations. 200484059Swpaul */ 200584059Swpaul 200684059Swpaul#define CSR_WRITE_4(sc, reg, val) \ 200784059Swpaul bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 200884059Swpaul 200984059Swpaul#define CSR_READ_4(sc, reg) \ 201084059Swpaul bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 201184059Swpaul 201284059Swpaul#define BGE_SETBIT(sc, reg, x) \ 201384059Swpaul CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 201484059Swpaul#define BGE_CLRBIT(sc, reg, x) \ 201584059Swpaul CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 201684059Swpaul 201784059Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 201884059Swpaul pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s) 201984059Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 202084059Swpaul pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s) 202184059Swpaul 202284059Swpaul/* 202384059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 202484059Swpaul * values are tuneable. They control the actual amount of buffers 202584059Swpaul * allocated for the standard, mini and jumbo receive rings. 202684059Swpaul */ 202784059Swpaul 202884059Swpaul#define BGE_SSLOTS 256 202984059Swpaul#define BGE_MSLOTS 256 203084059Swpaul#define BGE_JSLOTS 384 203184059Swpaul 203284059Swpaul#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 203384059Swpaul#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 203484059Swpaul (BGE_JRAWLEN % sizeof(u_int64_t)))) 203584059Swpaul#define BGE_JPAGESZ PAGE_SIZE 203684059Swpaul#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 203784059Swpaul#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 203884059Swpaul 203984059Swpaul/* 204084059Swpaul * Ring structures. Most of these reside in host memory and we tell 204184059Swpaul * the NIC where they are via the ring control blocks. The exceptions 204284059Swpaul * are the tx and command rings, which live in NIC memory and which 204384059Swpaul * we access via the shared memory window. 204484059Swpaul */ 204584059Swpaulstruct bge_ring_data { 204684059Swpaul struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 204784059Swpaul struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 204884059Swpaul struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 204984059Swpaul struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 205084059Swpaul struct bge_status_block bge_status_block; 205184059Swpaul struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 205284059Swpaul struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 205384059Swpaul struct bge_gib bge_info; 205484059Swpaul}; 205584059Swpaul 205684059Swpaul/* 205784059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 205884059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 205984059Swpaul * not the other way around. 206084059Swpaul */ 206184059Swpaulstruct bge_chain_data { 206284059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 206384059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 206484059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 206584059Swpaul struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 206684059Swpaul /* Stick the jumbo mem management stuff here too. */ 206784059Swpaul caddr_t bge_jslots[BGE_JSLOTS]; 206884059Swpaul void *bge_jumbo_buf; 206984059Swpaul}; 207084059Swpaul 207184059Swpaulstruct bge_type { 207284059Swpaul u_int16_t bge_vid; 207384059Swpaul u_int16_t bge_did; 207484059Swpaul char *bge_name; 207584059Swpaul}; 207684059Swpaul 207784059Swpaul#define BGE_HWREV_TIGON 0x01 207884059Swpaul#define BGE_HWREV_TIGON_II 0x02 207984059Swpaul#define BGE_TIMEOUT 1000 208084059Swpaul#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 208184059Swpaul 208284059Swpaulstruct bge_jpool_entry { 208384059Swpaul int slot; 208484059Swpaul SLIST_ENTRY(bge_jpool_entry) jpool_entries; 208584059Swpaul}; 208684059Swpaul 208784059Swpaulstruct bge_bcom_hack { 208884059Swpaul int reg; 208984059Swpaul int val; 209084059Swpaul}; 209184059Swpaul 209284059Swpaulstruct bge_softc { 209384059Swpaul struct arpcom arpcom; /* interface info */ 209484059Swpaul device_t bge_dev; 209584059Swpaul device_t bge_miibus; 209684059Swpaul bus_space_handle_t bge_bhandle; 209784059Swpaul vm_offset_t bge_vhandle; 209884059Swpaul bus_space_tag_t bge_btag; 209984059Swpaul void *bge_intrhand; 210084059Swpaul struct resource *bge_irq; 210184059Swpaul struct resource *bge_res; 210284059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 210384059Swpaul u_int8_t bge_unit; /* interface number */ 210484059Swpaul u_int8_t bge_extram; /* has external SSRAM */ 210584059Swpaul u_int8_t bge_tbi; 210684059Swpaul struct bge_ring_data *bge_rdata; /* rings */ 210784059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 210884059Swpaul u_int16_t bge_tx_saved_considx; 210984059Swpaul u_int16_t bge_rx_saved_considx; 211084059Swpaul u_int16_t bge_ev_saved_considx; 211184059Swpaul u_int16_t bge_std; /* current std ring head */ 211284059Swpaul u_int16_t bge_jumbo; /* current jumo ring head */ 211384059Swpaul SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 211484059Swpaul SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 211584059Swpaul u_int32_t bge_stat_ticks; 211684059Swpaul u_int32_t bge_rx_coal_ticks; 211784059Swpaul u_int32_t bge_tx_coal_ticks; 211884059Swpaul u_int32_t bge_rx_max_coal_bds; 211984059Swpaul u_int32_t bge_tx_max_coal_bds; 212084059Swpaul u_int32_t bge_tx_buf_ratio; 212184059Swpaul int bge_if_flags; 212284059Swpaul int bge_txcnt; 212384059Swpaul int bge_link; 212484059Swpaul struct callout_handle bge_stat_ch; 212584059Swpaul char *bge_vpd_prodname; 212684059Swpaul char *bge_vpd_readonly; 212784059Swpaul}; 212884059Swpaul 212984059Swpaul#ifdef __alpha__ 213084059Swpaul#undef vtophys 213184059Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 213284059Swpaul#endif 2133