if_bgereg.h revision 230337
1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 230337 2012-01-19 20:21:59Z yongari $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 64166676Sjkim#define BGE_PAGE_ZERO 0x00000000 65166676Sjkim#define BGE_PAGE_ZERO_END 0x000000FF 66166676Sjkim#define BGE_SEND_RING_RCB 0x00000100 67166676Sjkim#define BGE_SEND_RING_RCB_END 0x000001FF 68166676Sjkim#define BGE_RX_RETURN_RING_RCB 0x00000200 69166676Sjkim#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70166676Sjkim#define BGE_STATS_BLOCK 0x00000300 71166676Sjkim#define BGE_STATS_BLOCK_END 0x00000AFF 72166676Sjkim#define BGE_STATUS_BLOCK 0x00000B00 73166676Sjkim#define BGE_STATUS_BLOCK_END 0x00000B4F 74226814Syongari#define BGE_SRAM_FW_MB 0x00000B50 75226814Syongari#define BGE_SRAM_DATA_SIG 0x00000B54 76226814Syongari#define BGE_SRAM_DATA_CFG 0x00000B58 77226814Syongari#define BGE_SRAM_FW_CMD_MB 0x00000B78 78226814Syongari#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 79226814Syongari#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 80226821Syongari#define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 81226815Syongari#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 82226815Syongari#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 83166676Sjkim#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 84166676Sjkim#define BGE_UNMAPPED 0x00001000 85166676Sjkim#define BGE_UNMAPPED_END 0x00001FFF 86166676Sjkim#define BGE_DMA_DESCRIPTORS 0x00002000 87166676Sjkim#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 88214428Syongari#define BGE_SEND_RING_5717 0x00004000 89166676Sjkim#define BGE_SEND_RING_1_TO_4 0x00004000 90166676Sjkim#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 9184059Swpaul 92166676Sjkim/* Firmware interface */ 93226814Syongari#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 94166676Sjkim 95226864Syongari#define BGE_FW_CMD_DRV_ALIVE 0x00000001 96226864Syongari#define BGE_FW_CMD_PAUSE 0x00000002 97226864Syongari#define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 98226864Syongari#define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 99226864Syongari#define BGE_FW_CMD_LINK_UPDATE 0x0000000C 100226864Syongari#define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 101226864Syongari#define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 102226864Syongari 103226867Syongari#define BGE_FW_HB_TIMEOUT_SEC 3 104226867Syongari 105226821Syongari#define BGE_FW_DRV_STATE_START 0x00000001 106226821Syongari#define BGE_FW_DRV_STATE_START_DONE 0x80000001 107226821Syongari#define BGE_FW_DRV_STATE_UNLOAD 0x00000002 108226821Syongari#define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 109226821Syongari#define BGE_FW_DRV_STATE_WOL 0x00000003 110226821Syongari#define BGE_FW_DRV_STATE_SUSPEND 0x00000004 111226821Syongari 11284059Swpaul/* Mappings for internal memory configuration */ 113166676Sjkim#define BGE_STD_RX_RINGS 0x00006000 114166676Sjkim#define BGE_STD_RX_RINGS_END 0x00006FFF 115166676Sjkim#define BGE_JUMBO_RX_RINGS 0x00007000 116166676Sjkim#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 117166676Sjkim#define BGE_BUFFPOOL_1 0x00008000 118166676Sjkim#define BGE_BUFFPOOL_1_END 0x0000FFFF 119166676Sjkim#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 120166676Sjkim#define BGE_BUFFPOOL_2_END 0x00017FFF 121166676Sjkim#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 122166676Sjkim#define BGE_BUFFPOOL_3_END 0x0001FFFF 123214428Syongari#define BGE_STD_RX_RINGS_5717 0x00040000 124214428Syongari#define BGE_JUMBO_RX_RINGS_5717 0x00044400 12584059Swpaul 12684059Swpaul/* Mappings for external SSRAM configurations */ 127166676Sjkim#define BGE_SEND_RING_5_TO_6 0x00006000 128166676Sjkim#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 129166676Sjkim#define BGE_SEND_RING_7_TO_8 0x00007000 130166676Sjkim#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 131166676Sjkim#define BGE_SEND_RING_9_TO_16 0x00008000 132166676Sjkim#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 133166676Sjkim#define BGE_EXT_STD_RX_RINGS 0x0000C000 134166676Sjkim#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 135166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 136166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 137166676Sjkim#define BGE_MINI_RX_RINGS 0x0000E000 138166676Sjkim#define BGE_MINI_RX_RINGS_END 0x0000FFFF 139166676Sjkim#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 140166676Sjkim#define BGE_AVAIL_REGION1_END 0x00017FFF 141166676Sjkim#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 142166676Sjkim#define BGE_AVAIL_REGION2_END 0x0001FFFF 143166676Sjkim#define BGE_EXT_SSRAM 0x00020000 144166676Sjkim#define BGE_EXT_SSRAM_END 0x000FFFFF 14584059Swpaul 14684059Swpaul 14784059Swpaul/* 14884059Swpaul * BCM570x register offsets. These are memory mapped registers 14984059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 15084059Swpaul * Each register must be accessed using 32 bit operations. 15184059Swpaul * 15284059Swpaul * All registers are accessed through a 32K shared memory block. 15384059Swpaul * The first group of registers are actually copies of the PCI 15484059Swpaul * configuration space registers. 15584059Swpaul */ 15684059Swpaul 15784059Swpaul/* 15884059Swpaul * PCI registers defined in the PCI 2.2 spec. 15984059Swpaul */ 160166676Sjkim#define BGE_PCI_VID 0x00 161166676Sjkim#define BGE_PCI_DID 0x02 162166676Sjkim#define BGE_PCI_CMD 0x04 163166676Sjkim#define BGE_PCI_STS 0x06 164166676Sjkim#define BGE_PCI_REV 0x08 165166676Sjkim#define BGE_PCI_CLASS 0x09 166166676Sjkim#define BGE_PCI_CACHESZ 0x0C 167166676Sjkim#define BGE_PCI_LATTIMER 0x0D 168166676Sjkim#define BGE_PCI_HDRTYPE 0x0E 169166676Sjkim#define BGE_PCI_BIST 0x0F 170166676Sjkim#define BGE_PCI_BAR0 0x10 171166676Sjkim#define BGE_PCI_BAR1 0x14 172166676Sjkim#define BGE_PCI_SUBSYS 0x2C 173166676Sjkim#define BGE_PCI_SUBVID 0x2E 174166676Sjkim#define BGE_PCI_ROMBASE 0x30 175166676Sjkim#define BGE_PCI_CAPPTR 0x34 176166676Sjkim#define BGE_PCI_INTLINE 0x3C 177166676Sjkim#define BGE_PCI_INTPIN 0x3D 178166676Sjkim#define BGE_PCI_MINGNT 0x3E 179166676Sjkim#define BGE_PCI_MAXLAT 0x3F 180166676Sjkim#define BGE_PCI_PCIXCAP 0x40 181166676Sjkim#define BGE_PCI_NEXTPTR_PM 0x41 182166676Sjkim#define BGE_PCI_PCIX_CMD 0x42 183166676Sjkim#define BGE_PCI_PCIX_STS 0x44 184166676Sjkim#define BGE_PCI_PWRMGMT_CAPID 0x48 185166676Sjkim#define BGE_PCI_NEXTPTR_VPD 0x49 186166676Sjkim#define BGE_PCI_PWRMGMT_CAPS 0x4A 187166676Sjkim#define BGE_PCI_PWRMGMT_CMD 0x4C 188166676Sjkim#define BGE_PCI_PWRMGMT_STS 0x4D 189166676Sjkim#define BGE_PCI_PWRMGMT_DATA 0x4F 190166676Sjkim#define BGE_PCI_VPD_CAPID 0x50 191166676Sjkim#define BGE_PCI_NEXTPTR_MSI 0x51 192166676Sjkim#define BGE_PCI_VPD_ADDR 0x52 193166676Sjkim#define BGE_PCI_VPD_DATA 0x54 194166676Sjkim#define BGE_PCI_MSI_CAPID 0x58 195166676Sjkim#define BGE_PCI_NEXTPTR_NONE 0x59 196166676Sjkim#define BGE_PCI_MSI_CTL 0x5A 197166676Sjkim#define BGE_PCI_MSI_ADDR_HI 0x5C 198166676Sjkim#define BGE_PCI_MSI_ADDR_LO 0x60 199166676Sjkim#define BGE_PCI_MSI_DATA 0x64 20084059Swpaul 201190194Smarius/* 202190194Smarius * PCI Express definitions 203190194Smarius * According to 204190194Smarius * PCI Express base specification, REV. 1.0a 205190194Smarius */ 206190194Smarius 207190194Smarius/* PCI Express device control, 16bits */ 208190194Smarius#define BGE_PCIE_DEVCTL 0x08 209190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 210190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 211190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 212190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 213190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 214190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 215190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 216190194Smarius 217135772Sps/* PCI MSI. ??? */ 218166676Sjkim#define BGE_PCIE_CAPID_REG 0xD0 219166676Sjkim#define BGE_PCIE_CAPID 0x10 220135772Sps 22184059Swpaul/* 22284059Swpaul * PCI registers specific to the BCM570x family. 22384059Swpaul */ 224166676Sjkim#define BGE_PCI_MISC_CTL 0x68 225166676Sjkim#define BGE_PCI_DMA_RW_CTL 0x6C 226166676Sjkim#define BGE_PCI_PCISTATE 0x70 227166676Sjkim#define BGE_PCI_CLKCTL 0x74 228166676Sjkim#define BGE_PCI_REG_BASEADDR 0x78 229166676Sjkim#define BGE_PCI_MEMWIN_BASEADDR 0x7C 230166676Sjkim#define BGE_PCI_REG_DATA 0x80 231166676Sjkim#define BGE_PCI_MEMWIN_DATA 0x84 232166676Sjkim#define BGE_PCI_MODECTL 0x88 233166676Sjkim#define BGE_PCI_MISC_CFG 0x8C 234166676Sjkim#define BGE_PCI_MISC_LOCALCTL 0x90 235166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 236166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 237166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 238166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 239166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 240166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 241166676Sjkim#define BGE_PCI_ISR_MBX_HI 0xB0 242166676Sjkim#define BGE_PCI_ISR_MBX_LO 0xB4 243197832Sstas#define BGE_PCI_PRODID_ASICREV 0xBC 244214428Syongari#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 245221445Syongari#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 24684059Swpaul 24784059Swpaul/* PCI Misc. Host control register */ 248166676Sjkim#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 249166676Sjkim#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 250166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 251166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 252166676Sjkim#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 253166676Sjkim#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 254166676Sjkim#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 255166676Sjkim#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 256214428Syongari#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 257166676Sjkim#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 258197832Sstas#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 25984059Swpaul 260166676Sjkim#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 26184059Swpaul 262166676Sjkim#define BGE_INIT \ 263153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 264153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 26584059Swpaul 266197832Sstas#define BGE_CHIPID_TIGON_I 0x4000 267197832Sstas#define BGE_CHIPID_TIGON_II 0x6000 268197832Sstas#define BGE_CHIPID_BCM5700_A0 0x7000 269197832Sstas#define BGE_CHIPID_BCM5700_A1 0x7001 270197832Sstas#define BGE_CHIPID_BCM5700_B0 0x7100 271197832Sstas#define BGE_CHIPID_BCM5700_B1 0x7101 272197832Sstas#define BGE_CHIPID_BCM5700_B2 0x7102 273197832Sstas#define BGE_CHIPID_BCM5700_B3 0x7103 274197832Sstas#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 275197832Sstas#define BGE_CHIPID_BCM5700_C0 0x7200 276197832Sstas#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 277197832Sstas#define BGE_CHIPID_BCM5701_B0 0x0100 278197832Sstas#define BGE_CHIPID_BCM5701_B2 0x0102 279197832Sstas#define BGE_CHIPID_BCM5701_B5 0x0105 280197832Sstas#define BGE_CHIPID_BCM5703_A0 0x1000 281197832Sstas#define BGE_CHIPID_BCM5703_A1 0x1001 282197832Sstas#define BGE_CHIPID_BCM5703_A2 0x1002 283197832Sstas#define BGE_CHIPID_BCM5703_A3 0x1003 284197832Sstas#define BGE_CHIPID_BCM5703_B0 0x1100 285197832Sstas#define BGE_CHIPID_BCM5704_A0 0x2000 286197832Sstas#define BGE_CHIPID_BCM5704_A1 0x2001 287197832Sstas#define BGE_CHIPID_BCM5704_A2 0x2002 288197832Sstas#define BGE_CHIPID_BCM5704_A3 0x2003 289197832Sstas#define BGE_CHIPID_BCM5704_B0 0x2100 290197832Sstas#define BGE_CHIPID_BCM5705_A0 0x3000 291197832Sstas#define BGE_CHIPID_BCM5705_A1 0x3001 292197832Sstas#define BGE_CHIPID_BCM5705_A2 0x3002 293197832Sstas#define BGE_CHIPID_BCM5705_A3 0x3003 294197832Sstas#define BGE_CHIPID_BCM5750_A0 0x4000 295197832Sstas#define BGE_CHIPID_BCM5750_A1 0x4001 296197832Sstas#define BGE_CHIPID_BCM5750_A3 0x4000 297197832Sstas#define BGE_CHIPID_BCM5750_B0 0x4100 298197832Sstas#define BGE_CHIPID_BCM5750_B1 0x4101 299197832Sstas#define BGE_CHIPID_BCM5750_C0 0x4200 300197832Sstas#define BGE_CHIPID_BCM5750_C1 0x4201 301197832Sstas#define BGE_CHIPID_BCM5750_C2 0x4202 302197832Sstas#define BGE_CHIPID_BCM5714_A0 0x5000 303197832Sstas#define BGE_CHIPID_BCM5752_A0 0x6000 304197832Sstas#define BGE_CHIPID_BCM5752_A1 0x6001 305197832Sstas#define BGE_CHIPID_BCM5752_A2 0x6002 306197832Sstas#define BGE_CHIPID_BCM5714_B0 0x8000 307197832Sstas#define BGE_CHIPID_BCM5714_B3 0x8003 308197832Sstas#define BGE_CHIPID_BCM5715_A0 0x9000 309197832Sstas#define BGE_CHIPID_BCM5715_A1 0x9001 310197832Sstas#define BGE_CHIPID_BCM5715_A3 0x9003 311197832Sstas#define BGE_CHIPID_BCM5755_A0 0xa000 312197832Sstas#define BGE_CHIPID_BCM5755_A1 0xa001 313197832Sstas#define BGE_CHIPID_BCM5755_A2 0xa002 314197832Sstas#define BGE_CHIPID_BCM5722_A0 0xa200 315197832Sstas#define BGE_CHIPID_BCM5754_A0 0xb000 316197832Sstas#define BGE_CHIPID_BCM5754_A1 0xb001 317197832Sstas#define BGE_CHIPID_BCM5754_A2 0xb002 318197832Sstas#define BGE_CHIPID_BCM5761_A0 0x5761000 319197832Sstas#define BGE_CHIPID_BCM5761_A1 0x5761100 320197832Sstas#define BGE_CHIPID_BCM5784_A0 0x5784000 321197832Sstas#define BGE_CHIPID_BCM5784_A1 0x5784100 322197832Sstas#define BGE_CHIPID_BCM5787_A0 0xb000 323197832Sstas#define BGE_CHIPID_BCM5787_A1 0xb001 324197832Sstas#define BGE_CHIPID_BCM5787_A2 0xb002 325214251Syongari#define BGE_CHIPID_BCM5906_A0 0xc000 326197832Sstas#define BGE_CHIPID_BCM5906_A1 0xc001 327197832Sstas#define BGE_CHIPID_BCM5906_A2 0xc002 328197832Sstas#define BGE_CHIPID_BCM57780_A0 0x57780000 329197832Sstas#define BGE_CHIPID_BCM57780_A1 0x57780001 330214428Syongari#define BGE_CHIPID_BCM5717_A0 0x05717000 331214428Syongari#define BGE_CHIPID_BCM5717_B0 0x05717100 332221818Syongari#define BGE_CHIPID_BCM5719_A0 0x05719000 333226871Syongari#define BGE_CHIPID_BCM5720_A0 0x05720000 334221445Syongari#define BGE_CHIPID_BCM57765_A0 0x57785000 335221445Syongari#define BGE_CHIPID_BCM57765_B0 0x57785100 33684059Swpaul 33793751Swpaul/* shorthand one */ 338197832Sstas#define BGE_ASICREV(x) ((x) >> 12) 339166676Sjkim#define BGE_ASICREV_BCM5701 0x00 340166676Sjkim#define BGE_ASICREV_BCM5703 0x01 341166676Sjkim#define BGE_ASICREV_BCM5704 0x02 342166676Sjkim#define BGE_ASICREV_BCM5705 0x03 343166676Sjkim#define BGE_ASICREV_BCM5750 0x04 344166676Sjkim#define BGE_ASICREV_BCM5714_A0 0x05 345166676Sjkim#define BGE_ASICREV_BCM5752 0x06 346166676Sjkim#define BGE_ASICREV_BCM5700 0x07 347166676Sjkim#define BGE_ASICREV_BCM5780 0x08 348166676Sjkim#define BGE_ASICREV_BCM5714 0x09 349166676Sjkim#define BGE_ASICREV_BCM5755 0x0a 350166676Sjkim#define BGE_ASICREV_BCM5754 0x0b 351166676Sjkim#define BGE_ASICREV_BCM5787 0x0b 352178667Sjhb#define BGE_ASICREV_BCM5906 0x0c 353197832Sstas/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 354197832Sstas#define BGE_ASICREV_USE_PRODID_REG 0x0f 355197832Sstas/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 356214428Syongari#define BGE_ASICREV_BCM5717 0x5717 357221818Syongari#define BGE_ASICREV_BCM5719 0x5719 358226871Syongari#define BGE_ASICREV_BCM5720 0x5720 359197832Sstas#define BGE_ASICREV_BCM5761 0x5761 360197832Sstas#define BGE_ASICREV_BCM5784 0x5784 361197832Sstas#define BGE_ASICREV_BCM5785 0x5785 362221445Syongari#define BGE_ASICREV_BCM57765 0x57785 363197832Sstas#define BGE_ASICREV_BCM57780 0x57780 36493751Swpaul 365114813Sps/* chip revisions */ 366197832Sstas#define BGE_CHIPREV(x) ((x) >> 8) 367166676Sjkim#define BGE_CHIPREV_5700_AX 0x70 368166676Sjkim#define BGE_CHIPREV_5700_BX 0x71 369166676Sjkim#define BGE_CHIPREV_5700_CX 0x72 370166676Sjkim#define BGE_CHIPREV_5701_AX 0x00 371166676Sjkim#define BGE_CHIPREV_5703_AX 0x10 372166676Sjkim#define BGE_CHIPREV_5704_AX 0x20 373166676Sjkim#define BGE_CHIPREV_5704_BX 0x21 374166676Sjkim#define BGE_CHIPREV_5750_AX 0x40 375166676Sjkim#define BGE_CHIPREV_5750_BX 0x41 376197832Sstas/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 377214428Syongari#define BGE_CHIPREV_5717_AX 0x57170 378214428Syongari#define BGE_CHIPREV_5717_BX 0x57171 379197832Sstas#define BGE_CHIPREV_5761_AX 0x57611 380197832Sstas#define BGE_CHIPREV_5784_AX 0x57841 381114813Sps 38284059Swpaul/* PCI DMA Read/Write Control register */ 383166676Sjkim#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 384214428Syongari#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 385166676Sjkim#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 386166676Sjkim#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 387169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 388169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 389169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 390166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 391166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 392166676Sjkim#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 393166676Sjkim#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 394166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 395166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 39684059Swpaul 397166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 398166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 399166676Sjkim#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 400166676Sjkim#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 40184059Swpaul 402221818Syongari#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 403221445Syongari#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 404221445Syongari 405166676Sjkim#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 406166676Sjkim#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 407166676Sjkim#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 408166676Sjkim#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 409166676Sjkim#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 410166676Sjkim#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 411166676Sjkim#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 412166676Sjkim#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 41384059Swpaul 414166676Sjkim#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 415166676Sjkim#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 416166676Sjkim#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 417166676Sjkim#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 418166676Sjkim#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 419166676Sjkim#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 420166676Sjkim#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 421166676Sjkim#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 422166676Sjkim 42384059Swpaul/* 42484059Swpaul * PCI state register -- note, this register is read only 42584059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 42684059Swpaul * register is set. 42784059Swpaul */ 428166676Sjkim#define BGE_PCISTATE_FORCE_RESET 0x00000001 429166676Sjkim#define BGE_PCISTATE_INTR_STATE 0x00000002 430166676Sjkim#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 431166676Sjkim#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 432166676Sjkim#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 433166676Sjkim#define BGE_PCISTATE_WANT_EXPROM 0x00000020 434166676Sjkim#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 435166676Sjkim#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 436166676Sjkim#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 43784059Swpaul 43884059Swpaul/* 43984059Swpaul * PCI Clock Control register -- note, this register is read only 44084059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 44184059Swpaul * register is set. 44284059Swpaul */ 443166676Sjkim#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 444166676Sjkim#define BGE_PCICLOCKCTL_M66EN 0x00000080 445166676Sjkim#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 446166676Sjkim#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 447166676Sjkim#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 448166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 449166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 450166676Sjkim#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 451166676Sjkim#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 452166676Sjkim#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 45384059Swpaul 45484059Swpaul 45584059Swpaul#ifndef PCIM_CMD_MWIEN 456166676Sjkim#define PCIM_CMD_MWIEN 0x0010 45784059Swpaul#endif 458190319Smarius#ifndef PCIM_CMD_INTxDIS 459190319Smarius#define PCIM_CMD_INTxDIS 0x0400 460190319Smarius#endif 46184059Swpaul 46284059Swpaul/* 46384059Swpaul * High priority mailbox registers 46484059Swpaul * Each mailbox is 64-bits wide, though we only use the 46584059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 46684059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 46784059Swpaul * has been updated. 46884059Swpaul */ 469166676Sjkim#define BGE_MBX_IRQ0_HI 0x0200 470166676Sjkim#define BGE_MBX_IRQ0_LO 0x0204 471166676Sjkim#define BGE_MBX_IRQ1_HI 0x0208 472166676Sjkim#define BGE_MBX_IRQ1_LO 0x020C 473166676Sjkim#define BGE_MBX_IRQ2_HI 0x0210 474166676Sjkim#define BGE_MBX_IRQ2_LO 0x0214 475166676Sjkim#define BGE_MBX_IRQ3_HI 0x0218 476166676Sjkim#define BGE_MBX_IRQ3_LO 0x021C 477166676Sjkim#define BGE_MBX_GEN0_HI 0x0220 478166676Sjkim#define BGE_MBX_GEN0_LO 0x0224 479166676Sjkim#define BGE_MBX_GEN1_HI 0x0228 480166676Sjkim#define BGE_MBX_GEN1_LO 0x022C 481166676Sjkim#define BGE_MBX_GEN2_HI 0x0230 482166676Sjkim#define BGE_MBX_GEN2_LO 0x0234 483166676Sjkim#define BGE_MBX_GEN3_HI 0x0228 484166676Sjkim#define BGE_MBX_GEN3_LO 0x022C 485166676Sjkim#define BGE_MBX_GEN4_HI 0x0240 486166676Sjkim#define BGE_MBX_GEN4_LO 0x0244 487166676Sjkim#define BGE_MBX_GEN5_HI 0x0248 488166676Sjkim#define BGE_MBX_GEN5_LO 0x024C 489166676Sjkim#define BGE_MBX_GEN6_HI 0x0250 490166676Sjkim#define BGE_MBX_GEN6_LO 0x0254 491166676Sjkim#define BGE_MBX_GEN7_HI 0x0258 492166676Sjkim#define BGE_MBX_GEN7_LO 0x025C 493166676Sjkim#define BGE_MBX_RELOAD_STATS_HI 0x0260 494166676Sjkim#define BGE_MBX_RELOAD_STATS_LO 0x0264 495166676Sjkim#define BGE_MBX_RX_STD_PROD_HI 0x0268 496166676Sjkim#define BGE_MBX_RX_STD_PROD_LO 0x026C 497166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 498166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 499166676Sjkim#define BGE_MBX_RX_MINI_PROD_HI 0x0278 500166676Sjkim#define BGE_MBX_RX_MINI_PROD_LO 0x027C 501166676Sjkim#define BGE_MBX_RX_CONS0_HI 0x0280 502166676Sjkim#define BGE_MBX_RX_CONS0_LO 0x0284 503166676Sjkim#define BGE_MBX_RX_CONS1_HI 0x0288 504166676Sjkim#define BGE_MBX_RX_CONS1_LO 0x028C 505166676Sjkim#define BGE_MBX_RX_CONS2_HI 0x0290 506166676Sjkim#define BGE_MBX_RX_CONS2_LO 0x0294 507166676Sjkim#define BGE_MBX_RX_CONS3_HI 0x0298 508166676Sjkim#define BGE_MBX_RX_CONS3_LO 0x029C 509166676Sjkim#define BGE_MBX_RX_CONS4_HI 0x02A0 510166676Sjkim#define BGE_MBX_RX_CONS4_LO 0x02A4 511166676Sjkim#define BGE_MBX_RX_CONS5_HI 0x02A8 512166676Sjkim#define BGE_MBX_RX_CONS5_LO 0x02AC 513166676Sjkim#define BGE_MBX_RX_CONS6_HI 0x02B0 514166676Sjkim#define BGE_MBX_RX_CONS6_LO 0x02B4 515166676Sjkim#define BGE_MBX_RX_CONS7_HI 0x02B8 516166676Sjkim#define BGE_MBX_RX_CONS7_LO 0x02BC 517166676Sjkim#define BGE_MBX_RX_CONS8_HI 0x02C0 518166676Sjkim#define BGE_MBX_RX_CONS8_LO 0x02C4 519166676Sjkim#define BGE_MBX_RX_CONS9_HI 0x02C8 520166676Sjkim#define BGE_MBX_RX_CONS9_LO 0x02CC 521166676Sjkim#define BGE_MBX_RX_CONS10_HI 0x02D0 522166676Sjkim#define BGE_MBX_RX_CONS10_LO 0x02D4 523166676Sjkim#define BGE_MBX_RX_CONS11_HI 0x02D8 524166676Sjkim#define BGE_MBX_RX_CONS11_LO 0x02DC 525166676Sjkim#define BGE_MBX_RX_CONS12_HI 0x02E0 526166676Sjkim#define BGE_MBX_RX_CONS12_LO 0x02E4 527166676Sjkim#define BGE_MBX_RX_CONS13_HI 0x02E8 528166676Sjkim#define BGE_MBX_RX_CONS13_LO 0x02EC 529166676Sjkim#define BGE_MBX_RX_CONS14_HI 0x02F0 530166676Sjkim#define BGE_MBX_RX_CONS14_LO 0x02F4 531166676Sjkim#define BGE_MBX_RX_CONS15_HI 0x02F8 532166676Sjkim#define BGE_MBX_RX_CONS15_LO 0x02FC 533166676Sjkim#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 534166676Sjkim#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 535166676Sjkim#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 536166676Sjkim#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 537166676Sjkim#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 538166676Sjkim#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 539166676Sjkim#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 540166676Sjkim#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 541166676Sjkim#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 542166676Sjkim#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 543166676Sjkim#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 544166676Sjkim#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 545166676Sjkim#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 546166676Sjkim#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 547166676Sjkim#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 548166676Sjkim#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 549166676Sjkim#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 550166676Sjkim#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 551166676Sjkim#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 552166676Sjkim#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 553166676Sjkim#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 554166676Sjkim#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 555166676Sjkim#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 556166676Sjkim#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 557166676Sjkim#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 558166676Sjkim#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 559166676Sjkim#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 560166676Sjkim#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 561166676Sjkim#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 562166676Sjkim#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 563166676Sjkim#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 564166676Sjkim#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 565166676Sjkim#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 566166676Sjkim#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 567166676Sjkim#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 568166676Sjkim#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 569166676Sjkim#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 570166676Sjkim#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 571166676Sjkim#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 572166676Sjkim#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 573166676Sjkim#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 574166676Sjkim#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 575166676Sjkim#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 576166676Sjkim#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 577166676Sjkim#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 578166676Sjkim#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 579166676Sjkim#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 580166676Sjkim#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 581166676Sjkim#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 582166676Sjkim#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 583166676Sjkim#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 584166676Sjkim#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 585166676Sjkim#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 586166676Sjkim#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 587166676Sjkim#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 588166676Sjkim#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 589166676Sjkim#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 590166676Sjkim#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 591166676Sjkim#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 592166676Sjkim#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 593166676Sjkim#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 594166676Sjkim#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 595166676Sjkim#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 596166676Sjkim#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 59784059Swpaul 598166676Sjkim#define BGE_TX_RINGS_MAX 4 599166676Sjkim#define BGE_TX_RINGS_EXTSSRAM_MAX 16 600166676Sjkim#define BGE_RX_RINGS_MAX 16 601214428Syongari#define BGE_RX_RINGS_MAX_5717 17 60284059Swpaul 60384059Swpaul/* Ethernet MAC control registers */ 604166676Sjkim#define BGE_MAC_MODE 0x0400 605166676Sjkim#define BGE_MAC_STS 0x0404 606166676Sjkim#define BGE_MAC_EVT_ENB 0x0408 607166676Sjkim#define BGE_MAC_LED_CTL 0x040C 608166676Sjkim#define BGE_MAC_ADDR1_LO 0x0410 609166676Sjkim#define BGE_MAC_ADDR1_HI 0x0414 610166676Sjkim#define BGE_MAC_ADDR2_LO 0x0418 611166676Sjkim#define BGE_MAC_ADDR2_HI 0x041C 612166676Sjkim#define BGE_MAC_ADDR3_LO 0x0420 613166676Sjkim#define BGE_MAC_ADDR3_HI 0x0424 614166676Sjkim#define BGE_MAC_ADDR4_LO 0x0428 615166676Sjkim#define BGE_MAC_ADDR4_HI 0x042C 616166676Sjkim#define BGE_WOL_PATPTR 0x0430 617166676Sjkim#define BGE_WOL_PATCFG 0x0434 618166676Sjkim#define BGE_TX_RANDOM_BACKOFF 0x0438 619166676Sjkim#define BGE_RX_MTU 0x043C 620166676Sjkim#define BGE_GBIT_PCS_TEST 0x0440 621166676Sjkim#define BGE_TX_TBI_AUTONEG 0x0444 622166676Sjkim#define BGE_RX_TBI_AUTONEG 0x0448 623166676Sjkim#define BGE_MI_COMM 0x044C 624166676Sjkim#define BGE_MI_STS 0x0450 625166676Sjkim#define BGE_MI_MODE 0x0454 626166676Sjkim#define BGE_AUTOPOLL_STS 0x0458 627166676Sjkim#define BGE_TX_MODE 0x045C 628166676Sjkim#define BGE_TX_STS 0x0460 629166676Sjkim#define BGE_TX_LENGTHS 0x0464 630166676Sjkim#define BGE_RX_MODE 0x0468 631166676Sjkim#define BGE_RX_STS 0x046C 632166676Sjkim#define BGE_MAR0 0x0470 633166676Sjkim#define BGE_MAR1 0x0474 634166676Sjkim#define BGE_MAR2 0x0478 635166676Sjkim#define BGE_MAR3 0x047C 636166676Sjkim#define BGE_RX_BD_RULES_CTL0 0x0480 637166676Sjkim#define BGE_RX_BD_RULES_MASKVAL0 0x0484 638166676Sjkim#define BGE_RX_BD_RULES_CTL1 0x0488 639166676Sjkim#define BGE_RX_BD_RULES_MASKVAL1 0x048C 640166676Sjkim#define BGE_RX_BD_RULES_CTL2 0x0490 641166676Sjkim#define BGE_RX_BD_RULES_MASKVAL2 0x0494 642166676Sjkim#define BGE_RX_BD_RULES_CTL3 0x0498 643166676Sjkim#define BGE_RX_BD_RULES_MASKVAL3 0x049C 644166676Sjkim#define BGE_RX_BD_RULES_CTL4 0x04A0 645166676Sjkim#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 646166676Sjkim#define BGE_RX_BD_RULES_CTL5 0x04A8 647166676Sjkim#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 648166676Sjkim#define BGE_RX_BD_RULES_CTL6 0x04B0 649166676Sjkim#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 650166676Sjkim#define BGE_RX_BD_RULES_CTL7 0x04B8 651166676Sjkim#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 652166676Sjkim#define BGE_RX_BD_RULES_CTL8 0x04C0 653166676Sjkim#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 654166676Sjkim#define BGE_RX_BD_RULES_CTL9 0x04C8 655166676Sjkim#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 656166676Sjkim#define BGE_RX_BD_RULES_CTL10 0x04D0 657166676Sjkim#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 658166676Sjkim#define BGE_RX_BD_RULES_CTL11 0x04D8 659166676Sjkim#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 660166676Sjkim#define BGE_RX_BD_RULES_CTL12 0x04E0 661166676Sjkim#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 662166676Sjkim#define BGE_RX_BD_RULES_CTL13 0x04E8 663166676Sjkim#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 664166676Sjkim#define BGE_RX_BD_RULES_CTL14 0x04F0 665166676Sjkim#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 666166676Sjkim#define BGE_RX_BD_RULES_CTL15 0x04F8 667166676Sjkim#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 668166676Sjkim#define BGE_RX_RULES_CFG 0x0500 669213255Syongari#define BGE_MAX_RX_FRAME_LOWAT 0x0504 670166676Sjkim#define BGE_SERDES_CFG 0x0590 671166676Sjkim#define BGE_SERDES_STS 0x0594 672166676Sjkim#define BGE_SGDIG_CFG 0x05B0 673166676Sjkim#define BGE_SGDIG_STS 0x05B4 674213283Syongari#define BGE_TX_MAC_STATS_OCTETS 0x0800 675213283Syongari#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 676213283Syongari#define BGE_TX_MAC_STATS_COLLS 0x0808 677213283Syongari#define BGE_TX_MAC_STATS_XON_SENT 0x080C 678213283Syongari#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 679213283Syongari#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 680213283Syongari#define BGE_TX_MAC_STATS_ERRORS 0x0818 681213283Syongari#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 682213283Syongari#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 683213283Syongari#define BGE_TX_MAC_STATS_DEFERRED 0x0824 684213283Syongari#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 685213283Syongari#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 686213283Syongari#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 687213283Syongari#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 688213283Syongari#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 689213283Syongari#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 690213283Syongari#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 691213283Syongari#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 692213283Syongari#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 693213283Syongari#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 694213283Syongari#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 695213283Syongari#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 696213283Syongari#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 697213283Syongari#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 698213283Syongari#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 699213283Syongari#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 700213283Syongari#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 701213283Syongari#define BGE_TX_MAC_STATS_UCAST 0x086C 702213283Syongari#define BGE_TX_MAC_STATS_MCAST 0x0870 703213283Syongari#define BGE_TX_MAC_STATS_BCAST 0x0874 704213283Syongari#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 705213283Syongari#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 706213283Syongari#define BGE_RX_MAC_STATS_OCTESTS 0x0880 707213283Syongari#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 708213283Syongari#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 709213283Syongari#define BGE_RX_MAC_STATS_UCAST 0x088C 710213283Syongari#define BGE_RX_MAC_STATS_MCAST 0x0890 711213283Syongari#define BGE_RX_MAC_STATS_BCAST 0x0894 712213283Syongari#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 713213283Syongari#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 714213283Syongari#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 715213283Syongari#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 716213283Syongari#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 717213283Syongari#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 718213283Syongari#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 719213283Syongari#define BGE_RX_MAC_STATS_JABBERS 0x08B4 720213283Syongari#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 72184059Swpaul 72284059Swpaul/* Ethernet MAC Mode register */ 723166676Sjkim#define BGE_MACMODE_RESET 0x00000001 724166676Sjkim#define BGE_MACMODE_HALF_DUPLEX 0x00000002 725166676Sjkim#define BGE_MACMODE_PORTMODE 0x0000000C 726166676Sjkim#define BGE_MACMODE_LOOPBACK 0x00000010 727166676Sjkim#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 728166676Sjkim#define BGE_MACMODE_TX_BURST_ENB 0x00000100 729166676Sjkim#define BGE_MACMODE_MAX_DEFER 0x00000200 730166676Sjkim#define BGE_MACMODE_LINK_POLARITY 0x00000400 731166676Sjkim#define BGE_MACMODE_RX_STATS_ENB 0x00000800 732166676Sjkim#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 733166676Sjkim#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 734166676Sjkim#define BGE_MACMODE_TX_STATS_ENB 0x00004000 735166676Sjkim#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 736166676Sjkim#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 737166676Sjkim#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 738166676Sjkim#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 739166676Sjkim#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 740166676Sjkim#define BGE_MACMODE_MIP_ENB 0x00100000 741166676Sjkim#define BGE_MACMODE_TXDMA_ENB 0x00200000 742166676Sjkim#define BGE_MACMODE_RXDMA_ENB 0x00400000 743166676Sjkim#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 74484059Swpaul 745166676Sjkim#define BGE_PORTMODE_NONE 0x00000000 746166676Sjkim#define BGE_PORTMODE_MII 0x00000004 747166676Sjkim#define BGE_PORTMODE_GMII 0x00000008 748166676Sjkim#define BGE_PORTMODE_TBI 0x0000000C 74984059Swpaul 75084059Swpaul/* MAC Status register */ 751166676Sjkim#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 752166676Sjkim#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 753166676Sjkim#define BGE_MACSTAT_RX_CFG 0x00000004 754166676Sjkim#define BGE_MACSTAT_CFG_CHANGED 0x00000008 755166676Sjkim#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 756166676Sjkim#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 757166676Sjkim#define BGE_MACSTAT_LINK_CHANGED 0x00001000 758166676Sjkim#define BGE_MACSTAT_MI_COMPLETE 0x00400000 759166676Sjkim#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 760166676Sjkim#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 761166676Sjkim#define BGE_MACSTAT_ODI_ERROR 0x02000000 762166676Sjkim#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 763166676Sjkim#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 76484059Swpaul 76584059Swpaul/* MAC Event Enable Register */ 766166676Sjkim#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 767166676Sjkim#define BGE_EVTENB_LINK_CHANGED 0x00001000 768166676Sjkim#define BGE_EVTENB_MI_COMPLETE 0x00400000 769166676Sjkim#define BGE_EVTENB_MI_INTERRUPT 0x00800000 770166676Sjkim#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 771166676Sjkim#define BGE_EVTENB_ODI_ERROR 0x02000000 772166676Sjkim#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 773166676Sjkim#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 77484059Swpaul 77584059Swpaul/* LED Control Register */ 776166676Sjkim#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 777166676Sjkim#define BGE_LEDCTL_1000MBPS_LED 0x00000002 778166676Sjkim#define BGE_LEDCTL_100MBPS_LED 0x00000004 779166676Sjkim#define BGE_LEDCTL_10MBPS_LED 0x00000008 780166676Sjkim#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 781166676Sjkim#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 782166676Sjkim#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 783166676Sjkim#define BGE_LEDCTL_1000MBPS_STS 0x00000080 784166676Sjkim#define BGE_LEDCTL_100MBPS_STS 0x00000100 785166676Sjkim#define BGE_LEDCTL_10MBPS_STS 0x00000200 786166676Sjkim#define BGE_LEDCTL_TRADLED_STS 0x00000400 787166676Sjkim#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 788166676Sjkim#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 78984059Swpaul 79084059Swpaul/* TX backoff seed register */ 791166676Sjkim#define BGE_TX_BACKOFF_SEED_MASK 0x3F 79284059Swpaul 79384059Swpaul/* Autopoll status register */ 794166676Sjkim#define BGE_AUTOPOLLSTS_ERROR 0x00000001 79584059Swpaul 79684059Swpaul/* Transmit MAC mode register */ 797166676Sjkim#define BGE_TXMODE_RESET 0x00000001 798166676Sjkim#define BGE_TXMODE_ENABLE 0x00000002 799166676Sjkim#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 800166676Sjkim#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 801166676Sjkim#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 802214216Syongari#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 803226871Syongari#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 804226871Syongari#define BGE_TXMODE_CNT_DN_MODE 0x00800000 80584059Swpaul 80684059Swpaul/* Transmit MAC status register */ 807166676Sjkim#define BGE_TXSTAT_RX_XOFFED 0x00000001 808166676Sjkim#define BGE_TXSTAT_SENT_XOFF 0x00000002 809166676Sjkim#define BGE_TXSTAT_SENT_XON 0x00000004 810166676Sjkim#define BGE_TXSTAT_LINK_UP 0x00000008 811166676Sjkim#define BGE_TXSTAT_ODI_UFLOW 0x00000010 812166676Sjkim#define BGE_TXSTAT_ODI_OFLOW 0x00000020 81384059Swpaul 81484059Swpaul/* Transmit MAC lengths register */ 815166676Sjkim#define BGE_TXLEN_SLOTTIME 0x000000FF 816166676Sjkim#define BGE_TXLEN_IPG 0x00000F00 817166676Sjkim#define BGE_TXLEN_CRS 0x00003000 818226871Syongari#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 819226871Syongari#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 82084059Swpaul 82184059Swpaul/* Receive MAC mode register */ 822166676Sjkim#define BGE_RXMODE_RESET 0x00000001 823166676Sjkim#define BGE_RXMODE_ENABLE 0x00000002 824166676Sjkim#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 825166676Sjkim#define BGE_RXMODE_RX_GIANTS 0x00000020 826166676Sjkim#define BGE_RXMODE_RX_RUNTS 0x00000040 827166676Sjkim#define BGE_RXMODE_8022_LENCHECK 0x00000080 828166676Sjkim#define BGE_RXMODE_RX_PROMISC 0x00000100 829166676Sjkim#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 830166676Sjkim#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 83184059Swpaul 83284059Swpaul/* Receive MAC status register */ 833166676Sjkim#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 834166676Sjkim#define BGE_RXSTAT_RCVD_XOFF 0x00000002 835166676Sjkim#define BGE_RXSTAT_RCVD_XON 0x00000004 83684059Swpaul 83784059Swpaul/* Receive Rules Control register */ 838166676Sjkim#define BGE_RXRULECTL_OFFSET 0x000000FF 839166676Sjkim#define BGE_RXRULECTL_CLASS 0x00001F00 840166676Sjkim#define BGE_RXRULECTL_HDRTYPE 0x0000E000 841166676Sjkim#define BGE_RXRULECTL_COMPARE_OP 0x00030000 842166676Sjkim#define BGE_RXRULECTL_MAP 0x01000000 843166676Sjkim#define BGE_RXRULECTL_DISCARD 0x02000000 844166676Sjkim#define BGE_RXRULECTL_MASK 0x04000000 845166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 846166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 847166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 848166676Sjkim#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 84984059Swpaul 85084059Swpaul/* Receive Rules Mask register */ 851166676Sjkim#define BGE_RXRULEMASK_VALUE 0x0000FFFF 852166676Sjkim#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 85384059Swpaul 854130273Swpaul/* SERDES configuration register */ 855166676Sjkim#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 856166676Sjkim#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 857166676Sjkim#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 858166676Sjkim#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 859166676Sjkim#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 860166676Sjkim#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 861166676Sjkim#define BGE_SERDESCFG_TXMODE 0x00001000 862166676Sjkim#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 863166676Sjkim#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 864166676Sjkim#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 865166676Sjkim#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 866166676Sjkim#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 867166676Sjkim#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 868166676Sjkim#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 869166676Sjkim#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 870166676Sjkim#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 871130273Swpaul 872130273Swpaul/* SERDES status register */ 873166676Sjkim#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 874166676Sjkim#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 875130273Swpaul 876130273Swpaul/* SGDIG config (not documented) */ 877166676Sjkim#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 878166676Sjkim#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 879166676Sjkim#define BGE_SGDIGCFG_SEND 0x40000000 880166676Sjkim#define BGE_SGDIGCFG_AUTO 0x80000000 881130273Swpaul 882130273Swpaul/* SGDIG status (not documented) */ 883214428Syongari#define BGE_SGDIGSTS_DONE 0x00000002 884214428Syongari#define BGE_SGDIGSTS_IS_SERDES 0x00000100 885166676Sjkim#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 886166676Sjkim#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 887130273Swpaul 888130273Swpaul 88984059Swpaul/* MI communication register */ 890166676Sjkim#define BGE_MICOMM_DATA 0x0000FFFF 891166676Sjkim#define BGE_MICOMM_REG 0x001F0000 892166676Sjkim#define BGE_MICOMM_PHY 0x03E00000 893166676Sjkim#define BGE_MICOMM_CMD 0x0C000000 894166676Sjkim#define BGE_MICOMM_READFAIL 0x10000000 895166676Sjkim#define BGE_MICOMM_BUSY 0x20000000 89684059Swpaul 897166676Sjkim#define BGE_MIREG(x) ((x & 0x1F) << 16) 898166676Sjkim#define BGE_MIPHY(x) ((x & 0x1F) << 21) 899166676Sjkim#define BGE_MICMD_WRITE 0x04000000 900166676Sjkim#define BGE_MICMD_READ 0x08000000 90184059Swpaul 90284059Swpaul/* MI status register */ 903166676Sjkim#define BGE_MISTS_LINK 0x00000001 904166676Sjkim#define BGE_MISTS_10MBPS 0x00000002 90584059Swpaul 906213485Syongari#define BGE_MIMODE_CLK_10MHZ 0x00000001 907166676Sjkim#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 908166676Sjkim#define BGE_MIMODE_AUTOPOLL 0x00000010 909166676Sjkim#define BGE_MIMODE_CLKCNT 0x001F0000 910213485Syongari#define BGE_MIMODE_500KHZ_CONST 0x00008000 911213485Syongari#define BGE_MIMODE_BASE 0x000C0000 91284059Swpaul 91384059Swpaul 91484059Swpaul/* 91584059Swpaul * Send data initiator control registers. 91684059Swpaul */ 917166676Sjkim#define BGE_SDI_MODE 0x0C00 918166676Sjkim#define BGE_SDI_STATUS 0x0C04 919166676Sjkim#define BGE_SDI_STATS_CTL 0x0C08 920166676Sjkim#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 921166676Sjkim#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 922214219Syongari#define BGE_ISO_PKT_TX 0x0C20 923166676Sjkim#define BGE_LOCSTATS_COS0 0x0C80 924166676Sjkim#define BGE_LOCSTATS_COS1 0x0C84 925166676Sjkim#define BGE_LOCSTATS_COS2 0x0C88 926166676Sjkim#define BGE_LOCSTATS_COS3 0x0C8C 927166676Sjkim#define BGE_LOCSTATS_COS4 0x0C90 928166676Sjkim#define BGE_LOCSTATS_COS5 0x0C84 929166676Sjkim#define BGE_LOCSTATS_COS6 0x0C98 930166676Sjkim#define BGE_LOCSTATS_COS7 0x0C9C 931166676Sjkim#define BGE_LOCSTATS_COS8 0x0CA0 932166676Sjkim#define BGE_LOCSTATS_COS9 0x0CA4 933166676Sjkim#define BGE_LOCSTATS_COS10 0x0CA8 934166676Sjkim#define BGE_LOCSTATS_COS11 0x0CAC 935166676Sjkim#define BGE_LOCSTATS_COS12 0x0CB0 936166676Sjkim#define BGE_LOCSTATS_COS13 0x0CB4 937166676Sjkim#define BGE_LOCSTATS_COS14 0x0CB8 938166676Sjkim#define BGE_LOCSTATS_COS15 0x0CBC 939166676Sjkim#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 940166676Sjkim#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 941166676Sjkim#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 942166676Sjkim#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 943166676Sjkim#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 944166676Sjkim#define BGE_LOCSTATS_IRQS 0x0CD4 945166676Sjkim#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 946166676Sjkim#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 94784059Swpaul 94884059Swpaul/* Send Data Initiator mode register */ 949166676Sjkim#define BGE_SDIMODE_RESET 0x00000001 950166676Sjkim#define BGE_SDIMODE_ENABLE 0x00000002 951166676Sjkim#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 952214428Syongari#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 95384059Swpaul 95484059Swpaul/* Send Data Initiator stats register */ 955166676Sjkim#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 95684059Swpaul 95784059Swpaul/* Send Data Initiator stats control register */ 958166676Sjkim#define BGE_SDISTATSCTL_ENABLE 0x00000001 959166676Sjkim#define BGE_SDISTATSCTL_FASTER 0x00000002 960166676Sjkim#define BGE_SDISTATSCTL_CLEAR 0x00000004 961166676Sjkim#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 962166676Sjkim#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 96384059Swpaul 96484059Swpaul/* 96584059Swpaul * Send Data Completion Control registers 96684059Swpaul */ 967166676Sjkim#define BGE_SDC_MODE 0x1000 968166676Sjkim#define BGE_SDC_STATUS 0x1004 96984059Swpaul 97084059Swpaul/* Send Data completion mode register */ 971166676Sjkim#define BGE_SDCMODE_RESET 0x00000001 972166676Sjkim#define BGE_SDCMODE_ENABLE 0x00000002 973166676Sjkim#define BGE_SDCMODE_ATTN 0x00000004 974197832Sstas#define BGE_SDCMODE_CDELAY 0x00000010 97584059Swpaul 97684059Swpaul/* Send Data completion status register */ 977166676Sjkim#define BGE_SDCSTAT_ATTN 0x00000004 97884059Swpaul 97984059Swpaul/* 98084059Swpaul * Send BD Ring Selector Control registers 98184059Swpaul */ 982166676Sjkim#define BGE_SRS_MODE 0x1400 983166676Sjkim#define BGE_SRS_STATUS 0x1404 984166676Sjkim#define BGE_SRS_HWDIAG 0x1408 985166676Sjkim#define BGE_SRS_LOC_NIC_CONS0 0x1440 986166676Sjkim#define BGE_SRS_LOC_NIC_CONS1 0x1444 987166676Sjkim#define BGE_SRS_LOC_NIC_CONS2 0x1448 988166676Sjkim#define BGE_SRS_LOC_NIC_CONS3 0x144C 989166676Sjkim#define BGE_SRS_LOC_NIC_CONS4 0x1450 990166676Sjkim#define BGE_SRS_LOC_NIC_CONS5 0x1454 991166676Sjkim#define BGE_SRS_LOC_NIC_CONS6 0x1458 992166676Sjkim#define BGE_SRS_LOC_NIC_CONS7 0x145C 993166676Sjkim#define BGE_SRS_LOC_NIC_CONS8 0x1460 994166676Sjkim#define BGE_SRS_LOC_NIC_CONS9 0x1464 995166676Sjkim#define BGE_SRS_LOC_NIC_CONS10 0x1468 996166676Sjkim#define BGE_SRS_LOC_NIC_CONS11 0x146C 997166676Sjkim#define BGE_SRS_LOC_NIC_CONS12 0x1470 998166676Sjkim#define BGE_SRS_LOC_NIC_CONS13 0x1474 999166676Sjkim#define BGE_SRS_LOC_NIC_CONS14 0x1478 1000166676Sjkim#define BGE_SRS_LOC_NIC_CONS15 0x147C 100184059Swpaul 100284059Swpaul/* Send BD Ring Selector Mode register */ 1003166676Sjkim#define BGE_SRSMODE_RESET 0x00000001 1004166676Sjkim#define BGE_SRSMODE_ENABLE 0x00000002 1005166676Sjkim#define BGE_SRSMODE_ATTN 0x00000004 100684059Swpaul 100784059Swpaul/* Send BD Ring Selector Status register */ 1008166676Sjkim#define BGE_SRSSTAT_ERROR 0x00000004 100984059Swpaul 101084059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 1011166676Sjkim#define BGE_SRSHWDIAG_STATE 0x0000000F 1012166676Sjkim#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1013166676Sjkim#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1014166676Sjkim#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 101584059Swpaul 101684059Swpaul/* 101784059Swpaul * Send BD Initiator Selector Control registers 101884059Swpaul */ 1019166676Sjkim#define BGE_SBDI_MODE 0x1800 1020166676Sjkim#define BGE_SBDI_STATUS 0x1804 1021166676Sjkim#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1022166676Sjkim#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1023166676Sjkim#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1024166676Sjkim#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1025166676Sjkim#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1026166676Sjkim#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1027166676Sjkim#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1028166676Sjkim#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1029166676Sjkim#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1030166676Sjkim#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1031166676Sjkim#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1032166676Sjkim#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1033166676Sjkim#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1034166676Sjkim#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1035166676Sjkim#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1036166676Sjkim#define BGE_SBDI_LOC_NIC_PROD15 0x1844 103784059Swpaul 103884059Swpaul/* Send BD Initiator Mode register */ 1039166676Sjkim#define BGE_SBDIMODE_RESET 0x00000001 1040166676Sjkim#define BGE_SBDIMODE_ENABLE 0x00000002 1041166676Sjkim#define BGE_SBDIMODE_ATTN 0x00000004 104284059Swpaul 104384059Swpaul/* Send BD Initiator Status register */ 1044166676Sjkim#define BGE_SBDISTAT_ERROR 0x00000004 104584059Swpaul 104684059Swpaul/* 104784059Swpaul * Send BD Completion Control registers 104884059Swpaul */ 1049166676Sjkim#define BGE_SBDC_MODE 0x1C00 1050166676Sjkim#define BGE_SBDC_STATUS 0x1C04 105184059Swpaul 105284059Swpaul/* Send BD Completion Control Mode register */ 1053166676Sjkim#define BGE_SBDCMODE_RESET 0x00000001 1054166676Sjkim#define BGE_SBDCMODE_ENABLE 0x00000002 1055166676Sjkim#define BGE_SBDCMODE_ATTN 0x00000004 105684059Swpaul 105784059Swpaul/* Send BD Completion Control Status register */ 1058166676Sjkim#define BGE_SBDCSTAT_ATTN 0x00000004 105984059Swpaul 106084059Swpaul/* 106184059Swpaul * Receive List Placement Control registers 106284059Swpaul */ 1063166676Sjkim#define BGE_RXLP_MODE 0x2000 1064166676Sjkim#define BGE_RXLP_STATUS 0x2004 1065166676Sjkim#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1066166676Sjkim#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1067166676Sjkim#define BGE_RXLP_CFG 0x2010 1068166676Sjkim#define BGE_RXLP_STATS_CTL 0x2014 1069166676Sjkim#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1070166676Sjkim#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1071166676Sjkim#define BGE_RXLP_HEAD0 0x2100 1072166676Sjkim#define BGE_RXLP_TAIL0 0x2104 1073166676Sjkim#define BGE_RXLP_COUNT0 0x2108 1074166676Sjkim#define BGE_RXLP_HEAD1 0x2110 1075166676Sjkim#define BGE_RXLP_TAIL1 0x2114 1076166676Sjkim#define BGE_RXLP_COUNT1 0x2118 1077166676Sjkim#define BGE_RXLP_HEAD2 0x2120 1078166676Sjkim#define BGE_RXLP_TAIL2 0x2124 1079166676Sjkim#define BGE_RXLP_COUNT2 0x2128 1080166676Sjkim#define BGE_RXLP_HEAD3 0x2130 1081166676Sjkim#define BGE_RXLP_TAIL3 0x2134 1082166676Sjkim#define BGE_RXLP_COUNT3 0x2138 1083166676Sjkim#define BGE_RXLP_HEAD4 0x2140 1084166676Sjkim#define BGE_RXLP_TAIL4 0x2144 1085166676Sjkim#define BGE_RXLP_COUNT4 0x2148 1086166676Sjkim#define BGE_RXLP_HEAD5 0x2150 1087166676Sjkim#define BGE_RXLP_TAIL5 0x2154 1088166676Sjkim#define BGE_RXLP_COUNT5 0x2158 1089166676Sjkim#define BGE_RXLP_HEAD6 0x2160 1090166676Sjkim#define BGE_RXLP_TAIL6 0x2164 1091166676Sjkim#define BGE_RXLP_COUNT6 0x2168 1092166676Sjkim#define BGE_RXLP_HEAD7 0x2170 1093166676Sjkim#define BGE_RXLP_TAIL7 0x2174 1094166676Sjkim#define BGE_RXLP_COUNT7 0x2178 1095166676Sjkim#define BGE_RXLP_HEAD8 0x2180 1096166676Sjkim#define BGE_RXLP_TAIL8 0x2184 1097166676Sjkim#define BGE_RXLP_COUNT8 0x2188 1098166676Sjkim#define BGE_RXLP_HEAD9 0x2190 1099166676Sjkim#define BGE_RXLP_TAIL9 0x2194 1100166676Sjkim#define BGE_RXLP_COUNT9 0x2198 1101166676Sjkim#define BGE_RXLP_HEAD10 0x21A0 1102166676Sjkim#define BGE_RXLP_TAIL10 0x21A4 1103166676Sjkim#define BGE_RXLP_COUNT10 0x21A8 1104166676Sjkim#define BGE_RXLP_HEAD11 0x21B0 1105166676Sjkim#define BGE_RXLP_TAIL11 0x21B4 1106166676Sjkim#define BGE_RXLP_COUNT11 0x21B8 1107166676Sjkim#define BGE_RXLP_HEAD12 0x21C0 1108166676Sjkim#define BGE_RXLP_TAIL12 0x21C4 1109166676Sjkim#define BGE_RXLP_COUNT12 0x21C8 1110166676Sjkim#define BGE_RXLP_HEAD13 0x21D0 1111166676Sjkim#define BGE_RXLP_TAIL13 0x21D4 1112166676Sjkim#define BGE_RXLP_COUNT13 0x21D8 1113166676Sjkim#define BGE_RXLP_HEAD14 0x21E0 1114166676Sjkim#define BGE_RXLP_TAIL14 0x21E4 1115166676Sjkim#define BGE_RXLP_COUNT14 0x21E8 1116166676Sjkim#define BGE_RXLP_HEAD15 0x21F0 1117166676Sjkim#define BGE_RXLP_TAIL15 0x21F4 1118166676Sjkim#define BGE_RXLP_COUNT15 0x21F8 1119166676Sjkim#define BGE_RXLP_LOCSTAT_COS0 0x2200 1120166676Sjkim#define BGE_RXLP_LOCSTAT_COS1 0x2204 1121166676Sjkim#define BGE_RXLP_LOCSTAT_COS2 0x2208 1122166676Sjkim#define BGE_RXLP_LOCSTAT_COS3 0x220C 1123166676Sjkim#define BGE_RXLP_LOCSTAT_COS4 0x2210 1124166676Sjkim#define BGE_RXLP_LOCSTAT_COS5 0x2214 1125166676Sjkim#define BGE_RXLP_LOCSTAT_COS6 0x2218 1126166676Sjkim#define BGE_RXLP_LOCSTAT_COS7 0x221C 1127166676Sjkim#define BGE_RXLP_LOCSTAT_COS8 0x2220 1128166676Sjkim#define BGE_RXLP_LOCSTAT_COS9 0x2224 1129166676Sjkim#define BGE_RXLP_LOCSTAT_COS10 0x2228 1130166676Sjkim#define BGE_RXLP_LOCSTAT_COS11 0x222C 1131166676Sjkim#define BGE_RXLP_LOCSTAT_COS12 0x2230 1132166676Sjkim#define BGE_RXLP_LOCSTAT_COS13 0x2234 1133166676Sjkim#define BGE_RXLP_LOCSTAT_COS14 0x2238 1134166676Sjkim#define BGE_RXLP_LOCSTAT_COS15 0x223C 1135166676Sjkim#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1136166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1137166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1138166676Sjkim#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1139166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1140166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1141166676Sjkim#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 114284059Swpaul 114384059Swpaul 114484059Swpaul/* Receive List Placement mode register */ 1145166676Sjkim#define BGE_RXLPMODE_RESET 0x00000001 1146166676Sjkim#define BGE_RXLPMODE_ENABLE 0x00000002 1147166676Sjkim#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1148166676Sjkim#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1149166676Sjkim#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 115084059Swpaul 115184059Swpaul/* Receive List Placement Status register */ 1152166676Sjkim#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1153166676Sjkim#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1154166676Sjkim#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 115584059Swpaul 115684059Swpaul/* 115784059Swpaul * Receive Data and Receive BD Initiator Control Registers 115884059Swpaul */ 1159166676Sjkim#define BGE_RDBDI_MODE 0x2400 1160166676Sjkim#define BGE_RDBDI_STATUS 0x2404 1161166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1162166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1163166676Sjkim#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1164166676Sjkim#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1165166676Sjkim#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1166166676Sjkim#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1167166676Sjkim#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1168166676Sjkim#define BGE_RX_STD_RCB_NICADDR 0x245C 1169166676Sjkim#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1170166676Sjkim#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1171166676Sjkim#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1172166676Sjkim#define BGE_RX_MINI_RCB_NICADDR 0x246C 1173166676Sjkim#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1174166676Sjkim#define BGE_RDBDI_STD_RX_CONS 0x2474 1175166676Sjkim#define BGE_RDBDI_MINI_RX_CONS 0x2478 1176166676Sjkim#define BGE_RDBDI_RETURN_PROD0 0x2480 1177166676Sjkim#define BGE_RDBDI_RETURN_PROD1 0x2484 1178166676Sjkim#define BGE_RDBDI_RETURN_PROD2 0x2488 1179166676Sjkim#define BGE_RDBDI_RETURN_PROD3 0x248C 1180166676Sjkim#define BGE_RDBDI_RETURN_PROD4 0x2490 1181166676Sjkim#define BGE_RDBDI_RETURN_PROD5 0x2494 1182166676Sjkim#define BGE_RDBDI_RETURN_PROD6 0x2498 1183166676Sjkim#define BGE_RDBDI_RETURN_PROD7 0x249C 1184166676Sjkim#define BGE_RDBDI_RETURN_PROD8 0x24A0 1185166676Sjkim#define BGE_RDBDI_RETURN_PROD9 0x24A4 1186166676Sjkim#define BGE_RDBDI_RETURN_PROD10 0x24A8 1187166676Sjkim#define BGE_RDBDI_RETURN_PROD11 0x24AC 1188166676Sjkim#define BGE_RDBDI_RETURN_PROD12 0x24B0 1189166676Sjkim#define BGE_RDBDI_RETURN_PROD13 0x24B4 1190166676Sjkim#define BGE_RDBDI_RETURN_PROD14 0x24B8 1191166676Sjkim#define BGE_RDBDI_RETURN_PROD15 0x24BC 1192166676Sjkim#define BGE_RDBDI_HWDIAG 0x24C0 119384059Swpaul 119484059Swpaul 119584059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 1196166676Sjkim#define BGE_RDBDIMODE_RESET 0x00000001 1197166676Sjkim#define BGE_RDBDIMODE_ENABLE 0x00000002 1198166676Sjkim#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1199166676Sjkim#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1200166676Sjkim#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 120184059Swpaul 120284059Swpaul/* Receive Data and Receive BD Initiator Status register */ 1203166676Sjkim#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1204166676Sjkim#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1205166676Sjkim#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 120684059Swpaul 120784059Swpaul 120884059Swpaul/* 120984059Swpaul * Receive Data Completion Control registers 121084059Swpaul */ 1211166676Sjkim#define BGE_RDC_MODE 0x2800 121284059Swpaul 121384059Swpaul/* Receive Data Completion Mode register */ 1214166676Sjkim#define BGE_RDCMODE_RESET 0x00000001 1215166676Sjkim#define BGE_RDCMODE_ENABLE 0x00000002 1216166676Sjkim#define BGE_RDCMODE_ATTN 0x00000004 121784059Swpaul 121884059Swpaul/* 121984059Swpaul * Receive BD Initiator Control registers 122084059Swpaul */ 1221166676Sjkim#define BGE_RBDI_MODE 0x2C00 1222166676Sjkim#define BGE_RBDI_STATUS 0x2C04 1223166676Sjkim#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1224166676Sjkim#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1225166676Sjkim#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1226166676Sjkim#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1227166676Sjkim#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1228166676Sjkim#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 122984059Swpaul 1230214428Syongari#define BGE_STD_REPLENISH_LWM 0x2D00 1231214428Syongari#define BGE_JMB_REPLENISH_LWM 0x2D04 1232214428Syongari 123384059Swpaul/* Receive BD Initiator Mode register */ 1234166676Sjkim#define BGE_RBDIMODE_RESET 0x00000001 1235166676Sjkim#define BGE_RBDIMODE_ENABLE 0x00000002 1236166676Sjkim#define BGE_RBDIMODE_ATTN 0x00000004 123784059Swpaul 123884059Swpaul/* Receive BD Initiator Status register */ 1239166676Sjkim#define BGE_RBDISTAT_ATTN 0x00000004 124084059Swpaul 124184059Swpaul/* 124284059Swpaul * Receive BD Completion Control registers 124384059Swpaul */ 1244166676Sjkim#define BGE_RBDC_MODE 0x3000 1245166676Sjkim#define BGE_RBDC_STATUS 0x3004 1246166676Sjkim#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1247166676Sjkim#define BGE_RBDC_STD_BD_PROD 0x300C 1248166676Sjkim#define BGE_RBDC_MINI_BD_PROD 0x3010 124984059Swpaul 125084059Swpaul/* Receive BD completion mode register */ 1251166676Sjkim#define BGE_RBDCMODE_RESET 0x00000001 1252166676Sjkim#define BGE_RBDCMODE_ENABLE 0x00000002 1253166676Sjkim#define BGE_RBDCMODE_ATTN 0x00000004 125484059Swpaul 125584059Swpaul/* Receive BD completion status register */ 1256166676Sjkim#define BGE_RBDCSTAT_ERROR 0x00000004 125784059Swpaul 125884059Swpaul/* 125984059Swpaul * Receive List Selector Control registers 126084059Swpaul */ 1261166676Sjkim#define BGE_RXLS_MODE 0x3400 1262166676Sjkim#define BGE_RXLS_STATUS 0x3404 126384059Swpaul 126484059Swpaul/* Receive List Selector Mode register */ 1265166676Sjkim#define BGE_RXLSMODE_RESET 0x00000001 1266166676Sjkim#define BGE_RXLSMODE_ENABLE 0x00000002 1267166676Sjkim#define BGE_RXLSMODE_ATTN 0x00000004 126884059Swpaul 126984059Swpaul/* Receive List Selector Status register */ 1270166676Sjkim#define BGE_RXLSSTAT_ERROR 0x00000004 127184059Swpaul 1272213485Syongari#define BGE_CPMU_CTRL 0x3600 1273213485Syongari#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1274213485Syongari#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1275213485Syongari#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1276213485Syongari#define BGE_CPMU_HST_ACC 0x361C 1277226871Syongari#define BGE_CPMU_CLCK_ORIDE 0x3624 1278213485Syongari#define BGE_CPMU_CLCK_STAT 0x3630 1279213485Syongari#define BGE_CPMU_MUTEX_REQ 0x365C 1280213485Syongari#define BGE_CPMU_MUTEX_GNT 0x3660 1281213485Syongari#define BGE_CPMU_PHY_STRAP 0x3664 1282213485Syongari 1283213485Syongari/* Central Power Management Unit (CPMU) register */ 1284213485Syongari#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1285213485Syongari#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1286213485Syongari#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1287213485Syongari#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1288213485Syongari 1289213485Syongari/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1290213485Syongari#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1291213485Syongari#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1292213485Syongari 1293213485Syongari/* Link Speed 1000MB Power Mode Clock Policy register */ 1294213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1295213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1296213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1297213485Syongari 1298213485Syongari/* Link Aware Power Mode Clock Policy register */ 1299213485Syongari#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1300213485Syongari#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1301213485Syongari 1302213485Syongari#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1303213485Syongari#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1304213485Syongari 1305226871Syongari/* Clock Speed Override Policy register */ 1306226871Syongari#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1307226871Syongari 1308213485Syongari/* CPMU Clock Status register */ 1309213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1310213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1311213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1312213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1313213485Syongari 1314213485Syongari/* CPMU Mutex Request register */ 1315213485Syongari#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1316213485Syongari#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1317213485Syongari 1318213485Syongari/* CPMU GPHY Strap register */ 1319213485Syongari#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1320213485Syongari 132184059Swpaul/* 132284059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 132384059Swpaul */ 1324166676Sjkim#define BGE_MBCF_MODE 0x3800 1325166676Sjkim#define BGE_MBCF_STATUS 0x3804 132684059Swpaul 132784059Swpaul/* Mbuf Cluster Free mode register */ 1328166676Sjkim#define BGE_MBCFMODE_RESET 0x00000001 1329166676Sjkim#define BGE_MBCFMODE_ENABLE 0x00000002 1330166676Sjkim#define BGE_MBCFMODE_ATTN 0x00000004 133184059Swpaul 133284059Swpaul/* Mbuf Cluster Free status register */ 1333166676Sjkim#define BGE_MBCFSTAT_ERROR 0x00000004 133484059Swpaul 133584059Swpaul/* 133684059Swpaul * Host Coalescing Control registers 133784059Swpaul */ 1338166676Sjkim#define BGE_HCC_MODE 0x3C00 1339166676Sjkim#define BGE_HCC_STATUS 0x3C04 1340166676Sjkim#define BGE_HCC_RX_COAL_TICKS 0x3C08 1341166676Sjkim#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1342166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1343166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1344166676Sjkim#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1345166676Sjkim#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1346166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1347166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1348166676Sjkim#define BGE_HCC_STATS_TICKS 0x3C28 1349166676Sjkim#define BGE_HCC_STATS_ADDR_HI 0x3C30 1350166676Sjkim#define BGE_HCC_STATS_ADDR_LO 0x3C34 1351166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1352166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1353166676Sjkim#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1354166676Sjkim#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1355166676Sjkim#define BGE_FLOW_ATTN 0x3C48 1356166676Sjkim#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1357166676Sjkim#define BGE_HCC_STD_BD_CONS 0x3C54 1358166676Sjkim#define BGE_HCC_MINI_BD_CONS 0x3C58 1359166676Sjkim#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1360166676Sjkim#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1361166676Sjkim#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1362166676Sjkim#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1363166676Sjkim#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1364166676Sjkim#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1365166676Sjkim#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1366166676Sjkim#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1367166676Sjkim#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1368166676Sjkim#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1369166676Sjkim#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1370166676Sjkim#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1371166676Sjkim#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1372166676Sjkim#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1373166676Sjkim#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1374166676Sjkim#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1375166676Sjkim#define BGE_HCC_TX_BD_CONS0 0x3CC0 1376166676Sjkim#define BGE_HCC_TX_BD_CONS1 0x3CC4 1377166676Sjkim#define BGE_HCC_TX_BD_CONS2 0x3CC8 1378166676Sjkim#define BGE_HCC_TX_BD_CONS3 0x3CCC 1379166676Sjkim#define BGE_HCC_TX_BD_CONS4 0x3CD0 1380166676Sjkim#define BGE_HCC_TX_BD_CONS5 0x3CD4 1381166676Sjkim#define BGE_HCC_TX_BD_CONS6 0x3CD8 1382166676Sjkim#define BGE_HCC_TX_BD_CONS7 0x3CDC 1383166676Sjkim#define BGE_HCC_TX_BD_CONS8 0x3CE0 1384166676Sjkim#define BGE_HCC_TX_BD_CONS9 0x3CE4 1385166676Sjkim#define BGE_HCC_TX_BD_CONS10 0x3CE8 1386166676Sjkim#define BGE_HCC_TX_BD_CONS11 0x3CEC 1387166676Sjkim#define BGE_HCC_TX_BD_CONS12 0x3CF0 1388166676Sjkim#define BGE_HCC_TX_BD_CONS13 0x3CF4 1389166676Sjkim#define BGE_HCC_TX_BD_CONS14 0x3CF8 1390166676Sjkim#define BGE_HCC_TX_BD_CONS15 0x3CFC 139184059Swpaul 139284059Swpaul 139384059Swpaul/* Host coalescing mode register */ 1394166676Sjkim#define BGE_HCCMODE_RESET 0x00000001 1395166676Sjkim#define BGE_HCCMODE_ENABLE 0x00000002 1396166676Sjkim#define BGE_HCCMODE_ATTN 0x00000004 1397166676Sjkim#define BGE_HCCMODE_COAL_NOW 0x00000008 1398166676Sjkim#define BGE_HCCMODE_MSI_BITS 0x00000070 1399166676Sjkim#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 140084059Swpaul 1401166676Sjkim#define BGE_STATBLKSZ_FULL 0x00000000 1402166676Sjkim#define BGE_STATBLKSZ_64BYTE 0x00000080 1403166676Sjkim#define BGE_STATBLKSZ_32BYTE 0x00000100 140484059Swpaul 140584059Swpaul/* Host coalescing status register */ 1406166676Sjkim#define BGE_HCCSTAT_ERROR 0x00000004 140784059Swpaul 140884059Swpaul/* Flow attention register */ 1409166676Sjkim#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1410166676Sjkim#define BGE_FLOWATTN_MEMARB 0x00000080 1411166676Sjkim#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1412166676Sjkim#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1413166676Sjkim#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1414166676Sjkim#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1415166676Sjkim#define BGE_FLOWATTN_RDBDI 0x00080000 1416166676Sjkim#define BGE_FLOWATTN_RXLS 0x00100000 1417166676Sjkim#define BGE_FLOWATTN_RXLP 0x00200000 1418166676Sjkim#define BGE_FLOWATTN_RBDC 0x00400000 1419166676Sjkim#define BGE_FLOWATTN_RBDI 0x00800000 1420166676Sjkim#define BGE_FLOWATTN_SDC 0x08000000 1421166676Sjkim#define BGE_FLOWATTN_SDI 0x10000000 1422166676Sjkim#define BGE_FLOWATTN_SRS 0x20000000 1423166676Sjkim#define BGE_FLOWATTN_SBDC 0x40000000 1424166676Sjkim#define BGE_FLOWATTN_SBDI 0x80000000 142584059Swpaul 142684059Swpaul/* 142784059Swpaul * Memory arbiter registers 142884059Swpaul */ 1429166676Sjkim#define BGE_MARB_MODE 0x4000 1430166676Sjkim#define BGE_MARB_STATUS 0x4004 1431166676Sjkim#define BGE_MARB_TRAPADDR_HI 0x4008 1432166676Sjkim#define BGE_MARB_TRAPADDR_LO 0x400C 143384059Swpaul 143484059Swpaul/* Memory arbiter mode register */ 1435166676Sjkim#define BGE_MARBMODE_RESET 0x00000001 1436166676Sjkim#define BGE_MARBMODE_ENABLE 0x00000002 1437166676Sjkim#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1438166676Sjkim#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1439166676Sjkim#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1440166676Sjkim#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1441166676Sjkim#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1442166676Sjkim#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1443166676Sjkim#define BGE_MARBMODE_PCI_TRAP 0x00000100 1444166676Sjkim#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1445166676Sjkim#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1446166676Sjkim#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1447166676Sjkim#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1448166676Sjkim#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1449166676Sjkim#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1450166676Sjkim#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1451166676Sjkim#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1452166676Sjkim#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1453166676Sjkim#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1454166676Sjkim#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1455166676Sjkim#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1456166676Sjkim#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1457166676Sjkim#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1458166676Sjkim#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1459166676Sjkim#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1460166676Sjkim#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 146184059Swpaul 146284059Swpaul/* Memory arbiter status register */ 1463166676Sjkim#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1464166676Sjkim#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1465166676Sjkim#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1466166676Sjkim#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1467166676Sjkim#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1468166676Sjkim#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1469166676Sjkim#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1470166676Sjkim#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1471166676Sjkim#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1472166676Sjkim#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1473166676Sjkim#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1474166676Sjkim#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1475166676Sjkim#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1476166676Sjkim#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1477166676Sjkim#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1478166676Sjkim#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1479166676Sjkim#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1480166676Sjkim#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1481166676Sjkim#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1482166676Sjkim#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1483166676Sjkim#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1484166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1485166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1486166676Sjkim#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 148784059Swpaul 148884059Swpaul/* 148984059Swpaul * Buffer manager control registers 149084059Swpaul */ 1491166676Sjkim#define BGE_BMAN_MODE 0x4400 1492166676Sjkim#define BGE_BMAN_STATUS 0x4404 1493166676Sjkim#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1494166676Sjkim#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1495166676Sjkim#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1496166676Sjkim#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1497166676Sjkim#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1498166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1499166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1500166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1501166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1502166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1503166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1504166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1505166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1506166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1507166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1508166676Sjkim#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1509166676Sjkim#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1510166676Sjkim#define BGE_BMAN_HWDIAG_1 0x444C 1511166676Sjkim#define BGE_BMAN_HWDIAG_2 0x4450 1512166676Sjkim#define BGE_BMAN_HWDIAG_3 0x4454 151384059Swpaul 151484059Swpaul/* Buffer manager mode register */ 1515166676Sjkim#define BGE_BMANMODE_RESET 0x00000001 1516166676Sjkim#define BGE_BMANMODE_ENABLE 0x00000002 1517166676Sjkim#define BGE_BMANMODE_ATTN 0x00000004 1518166676Sjkim#define BGE_BMANMODE_TESTMODE 0x00000008 1519166676Sjkim#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1520221818Syongari#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 152184059Swpaul 152284059Swpaul/* Buffer manager status register */ 1523166676Sjkim#define BGE_BMANSTAT_ERRO 0x00000004 1524166676Sjkim#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 152584059Swpaul 152684059Swpaul 152784059Swpaul/* 152884059Swpaul * Read DMA Control registers 152984059Swpaul */ 1530166676Sjkim#define BGE_RDMA_MODE 0x4800 1531166676Sjkim#define BGE_RDMA_STATUS 0x4804 1532213411Syongari#define BGE_RDMA_RSRVCTRL 0x4900 1533221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 153484059Swpaul 153584059Swpaul/* Read DMA mode register */ 1536166676Sjkim#define BGE_RDMAMODE_RESET 0x00000001 1537166676Sjkim#define BGE_RDMAMODE_ENABLE 0x00000002 1538166676Sjkim#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1539166676Sjkim#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1540166676Sjkim#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1541166676Sjkim#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1542166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1543166676Sjkim#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1544166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1545166676Sjkim#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1546166676Sjkim#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1547197832Sstas#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1548197832Sstas#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1549197832Sstas#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1550190194Smarius#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1551190194Smarius#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1552214428Syongari#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1553199671Syongari#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1554199671Syongari#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1555226871Syongari#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 155684059Swpaul 155784059Swpaul/* Read DMA status register */ 1558166676Sjkim#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1559166676Sjkim#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1560166676Sjkim#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1561166676Sjkim#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1562166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1563166676Sjkim#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1564166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1565166676Sjkim#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 156684059Swpaul 1567213411Syongari/* Read DMA Reserved Control register */ 1568213411Syongari#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1569221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1570221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1571221818Syongari#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1572221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1573221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1574221818Syongari#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1575213411Syongari 1576228479Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1577221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1578221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1579221818Syongari 158084059Swpaul/* 158184059Swpaul * Write DMA control registers 158284059Swpaul */ 1583166676Sjkim#define BGE_WDMA_MODE 0x4C00 1584166676Sjkim#define BGE_WDMA_STATUS 0x4C04 158584059Swpaul 158684059Swpaul/* Write DMA mode register */ 1587166676Sjkim#define BGE_WDMAMODE_RESET 0x00000001 1588166676Sjkim#define BGE_WDMAMODE_ENABLE 0x00000002 1589166676Sjkim#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1590166676Sjkim#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1591166676Sjkim#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1592166676Sjkim#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1593166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1594166676Sjkim#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1595166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1596166676Sjkim#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1597166676Sjkim#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1598197837Sstas#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1599213333Syongari#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 160084059Swpaul 160184059Swpaul/* Write DMA status register */ 1602166676Sjkim#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1603166676Sjkim#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1604166676Sjkim#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1605166676Sjkim#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1606166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1607166676Sjkim#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1608166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1609166676Sjkim#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 161084059Swpaul 161184059Swpaul 161284059Swpaul/* 161384059Swpaul * RX CPU registers 161484059Swpaul */ 1615166676Sjkim#define BGE_RXCPU_MODE 0x5000 1616166676Sjkim#define BGE_RXCPU_STATUS 0x5004 1617166676Sjkim#define BGE_RXCPU_PC 0x501C 161884059Swpaul 161984059Swpaul/* RX CPU mode register */ 1620166676Sjkim#define BGE_RXCPUMODE_RESET 0x00000001 1621166676Sjkim#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1622166676Sjkim#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1623166676Sjkim#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1624166676Sjkim#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1625166676Sjkim#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1626166676Sjkim#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1627166676Sjkim#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1628166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1629166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1630166676Sjkim#define BGE_RXCPUMODE_HALTCPU 0x00000400 1631166676Sjkim#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1632166676Sjkim#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1633166676Sjkim#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 163484059Swpaul 163584059Swpaul/* RX CPU status register */ 1636166676Sjkim#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1637166676Sjkim#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1638166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1639166676Sjkim#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1640166676Sjkim#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1641166676Sjkim#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1642166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1643166676Sjkim#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1644166676Sjkim#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1645166676Sjkim#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1646166676Sjkim#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1647166676Sjkim#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1648166676Sjkim#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1649166676Sjkim#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1650166676Sjkim#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1651166676Sjkim#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1652166676Sjkim#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 165384059Swpaul 1654178667Sjhb/* 1655178667Sjhb * V? CPU registers 1656178667Sjhb */ 1657178667Sjhb#define BGE_VCPU_STATUS 0x5100 1658178667Sjhb#define BGE_VCPU_EXT_CTRL 0x6890 165984059Swpaul 1660178667Sjhb#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1661178667Sjhb#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1662178667Sjhb 1663178667Sjhb#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1664178667Sjhb#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1665178667Sjhb 166684059Swpaul/* 166784059Swpaul * TX CPU registers 166884059Swpaul */ 1669166676Sjkim#define BGE_TXCPU_MODE 0x5400 1670166676Sjkim#define BGE_TXCPU_STATUS 0x5404 1671166676Sjkim#define BGE_TXCPU_PC 0x541C 167284059Swpaul 167384059Swpaul/* TX CPU mode register */ 1674166676Sjkim#define BGE_TXCPUMODE_RESET 0x00000001 1675166676Sjkim#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1676166676Sjkim#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1677166676Sjkim#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1678166676Sjkim#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1679166676Sjkim#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1680166676Sjkim#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1681166676Sjkim#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1682166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1683166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1684166676Sjkim#define BGE_TXCPUMODE_HALTCPU 0x00000400 1685166676Sjkim#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1686166676Sjkim#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 168784059Swpaul 168884059Swpaul/* TX CPU status register */ 1689166676Sjkim#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1690166676Sjkim#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1691166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1692166676Sjkim#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1693166676Sjkim#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1694166676Sjkim#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1695166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1696166676Sjkim#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1697166676Sjkim#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1698166676Sjkim#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1699166676Sjkim#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1700166676Sjkim#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1701166676Sjkim#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1702166676Sjkim#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1703166676Sjkim#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1704166676Sjkim#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1705166676Sjkim#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 170684059Swpaul 170784059Swpaul 170884059Swpaul/* 170984059Swpaul * Low priority mailbox registers 171084059Swpaul */ 1711166676Sjkim#define BGE_LPMBX_IRQ0_HI 0x5800 1712166676Sjkim#define BGE_LPMBX_IRQ0_LO 0x5804 1713166676Sjkim#define BGE_LPMBX_IRQ1_HI 0x5808 1714166676Sjkim#define BGE_LPMBX_IRQ1_LO 0x580C 1715166676Sjkim#define BGE_LPMBX_IRQ2_HI 0x5810 1716166676Sjkim#define BGE_LPMBX_IRQ2_LO 0x5814 1717166676Sjkim#define BGE_LPMBX_IRQ3_HI 0x5818 1718166676Sjkim#define BGE_LPMBX_IRQ3_LO 0x581C 1719166676Sjkim#define BGE_LPMBX_GEN0_HI 0x5820 1720166676Sjkim#define BGE_LPMBX_GEN0_LO 0x5824 1721166676Sjkim#define BGE_LPMBX_GEN1_HI 0x5828 1722166676Sjkim#define BGE_LPMBX_GEN1_LO 0x582C 1723166676Sjkim#define BGE_LPMBX_GEN2_HI 0x5830 1724166676Sjkim#define BGE_LPMBX_GEN2_LO 0x5834 1725166676Sjkim#define BGE_LPMBX_GEN3_HI 0x5828 1726166676Sjkim#define BGE_LPMBX_GEN3_LO 0x582C 1727166676Sjkim#define BGE_LPMBX_GEN4_HI 0x5840 1728166676Sjkim#define BGE_LPMBX_GEN4_LO 0x5844 1729166676Sjkim#define BGE_LPMBX_GEN5_HI 0x5848 1730166676Sjkim#define BGE_LPMBX_GEN5_LO 0x584C 1731166676Sjkim#define BGE_LPMBX_GEN6_HI 0x5850 1732166676Sjkim#define BGE_LPMBX_GEN6_LO 0x5854 1733166676Sjkim#define BGE_LPMBX_GEN7_HI 0x5858 1734166676Sjkim#define BGE_LPMBX_GEN7_LO 0x585C 1735166676Sjkim#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1736166676Sjkim#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1737166676Sjkim#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1738166676Sjkim#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1739166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1740166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1741166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1742166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1743166676Sjkim#define BGE_LPMBX_RX_CONS0_HI 0x5880 1744166676Sjkim#define BGE_LPMBX_RX_CONS0_LO 0x5884 1745166676Sjkim#define BGE_LPMBX_RX_CONS1_HI 0x5888 1746166676Sjkim#define BGE_LPMBX_RX_CONS1_LO 0x588C 1747166676Sjkim#define BGE_LPMBX_RX_CONS2_HI 0x5890 1748166676Sjkim#define BGE_LPMBX_RX_CONS2_LO 0x5894 1749166676Sjkim#define BGE_LPMBX_RX_CONS3_HI 0x5898 1750166676Sjkim#define BGE_LPMBX_RX_CONS3_LO 0x589C 1751166676Sjkim#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1752166676Sjkim#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1753166676Sjkim#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1754166676Sjkim#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1755166676Sjkim#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1756166676Sjkim#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1757166676Sjkim#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1758166676Sjkim#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1759166676Sjkim#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1760166676Sjkim#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1761166676Sjkim#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1762166676Sjkim#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1763166676Sjkim#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1764166676Sjkim#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1765166676Sjkim#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1766166676Sjkim#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1767166676Sjkim#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1768166676Sjkim#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1769166676Sjkim#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1770166676Sjkim#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1771166676Sjkim#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1772166676Sjkim#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1773166676Sjkim#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1774166676Sjkim#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1775166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1776166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1777166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1778166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1779166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1780166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1781166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1782166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1783166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1784166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1785166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1786166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1787166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1788166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1789166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1790166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1791166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1792166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1793166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1794166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1795166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1796166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1797166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1798166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1799166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1800166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1801166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1802166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1803166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1804166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1805166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1806166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1807166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1808166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1809166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1810166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1811166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1812166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1813166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1814166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1815166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1816166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1817166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1818166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1819166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1820166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1821166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1822166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1823166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1824166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1825166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1826166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1827166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1828166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1829166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1830166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1831166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1832166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1833166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1834166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1835166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1836166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1837166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1838166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 183984059Swpaul 184084059Swpaul/* 184184059Swpaul * Flow throw Queue reset register 184284059Swpaul */ 1843166676Sjkim#define BGE_FTQ_RESET 0x5C00 184484059Swpaul 1845166676Sjkim#define BGE_FTQRESET_DMAREAD 0x00000002 1846166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1847166676Sjkim#define BGE_FTQRESET_DMADONE 0x00000010 1848166676Sjkim#define BGE_FTQRESET_SBDC 0x00000020 1849166676Sjkim#define BGE_FTQRESET_SDI 0x00000040 1850166676Sjkim#define BGE_FTQRESET_WDMA 0x00000080 1851166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1852166676Sjkim#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1853166676Sjkim#define BGE_FTQRESET_SDC 0x00000400 1854166676Sjkim#define BGE_FTQRESET_HCC 0x00000800 1855166676Sjkim#define BGE_FTQRESET_TXFIFO 0x00001000 1856166676Sjkim#define BGE_FTQRESET_MBC 0x00002000 1857166676Sjkim#define BGE_FTQRESET_RBDC 0x00004000 1858166676Sjkim#define BGE_FTQRESET_RXLP 0x00008000 1859166676Sjkim#define BGE_FTQRESET_RDBDI 0x00010000 1860166676Sjkim#define BGE_FTQRESET_RDC 0x00020000 1861166676Sjkim#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 186284059Swpaul 186384059Swpaul/* 186484059Swpaul * Message Signaled Interrupt registers 186584059Swpaul */ 1866166676Sjkim#define BGE_MSI_MODE 0x6000 1867166676Sjkim#define BGE_MSI_STATUS 0x6004 1868166676Sjkim#define BGE_MSI_FIFOACCESS 0x6008 186984059Swpaul 187084059Swpaul/* MSI mode register */ 1871166676Sjkim#define BGE_MSIMODE_RESET 0x00000001 1872166676Sjkim#define BGE_MSIMODE_ENABLE 0x00000002 1873198967Syongari#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1874198967Syongari#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 187584059Swpaul 187684059Swpaul/* MSI status register */ 1877166676Sjkim#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1878166676Sjkim#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1879166676Sjkim#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1880166676Sjkim#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1881166676Sjkim#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 188284059Swpaul 188384059Swpaul 188484059Swpaul/* 188584059Swpaul * DMA Completion registers 188684059Swpaul */ 1887166676Sjkim#define BGE_DMAC_MODE 0x6400 188884059Swpaul 188984059Swpaul/* DMA Completion mode register */ 1890166676Sjkim#define BGE_DMACMODE_RESET 0x00000001 1891166676Sjkim#define BGE_DMACMODE_ENABLE 0x00000002 189284059Swpaul 189384059Swpaul 189484059Swpaul/* 189584059Swpaul * General control registers. 189684059Swpaul */ 1897166676Sjkim#define BGE_MODE_CTL 0x6800 1898166676Sjkim#define BGE_MISC_CFG 0x6804 1899166676Sjkim#define BGE_MISC_LOCAL_CTL 0x6808 1900226820Syongari#define BGE_RX_CPU_EVENT 0x6810 1901226820Syongari#define BGE_TX_CPU_EVENT 0x6820 1902166676Sjkim#define BGE_EE_ADDR 0x6838 1903166676Sjkim#define BGE_EE_DATA 0x683C 1904166676Sjkim#define BGE_EE_CTL 0x6840 1905166676Sjkim#define BGE_MDI_CTL 0x6844 1906166676Sjkim#define BGE_EE_DELAY 0x6848 1907166676Sjkim#define BGE_FASTBOOT_PC 0x6894 190884059Swpaul 1909226866Syongari#define BGE_RX_CPU_DRV_EVENT 0x00004000 1910226866Syongari 1911178667Sjhb/* 1912178667Sjhb * NVRAM Control registers 1913178667Sjhb */ 1914178667Sjhb#define BGE_NVRAM_CMD 0x7000 1915178667Sjhb#define BGE_NVRAM_STAT 0x7004 1916178667Sjhb#define BGE_NVRAM_WRDATA 0x7008 1917178667Sjhb#define BGE_NVRAM_ADDR 0x700c 1918178667Sjhb#define BGE_NVRAM_RDDATA 0x7010 1919178667Sjhb#define BGE_NVRAM_CFG1 0x7014 1920178667Sjhb#define BGE_NVRAM_CFG2 0x7018 1921178667Sjhb#define BGE_NVRAM_CFG3 0x701c 1922178667Sjhb#define BGE_NVRAM_SWARB 0x7020 1923178667Sjhb#define BGE_NVRAM_ACCESS 0x7024 1924178667Sjhb#define BGE_NVRAM_WRITE1 0x7028 1925178667Sjhb 1926178667Sjhb#define BGE_NVRAMCMD_RESET 0x00000001 1927178667Sjhb#define BGE_NVRAMCMD_DONE 0x00000008 1928178667Sjhb#define BGE_NVRAMCMD_START 0x00000010 1929178667Sjhb#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1930178667Sjhb#define BGE_NVRAMCMD_ERASE 0x00000040 1931178667Sjhb#define BGE_NVRAMCMD_FIRST 0x00000080 1932178667Sjhb#define BGE_NVRAMCMD_LAST 0x00000100 1933178667Sjhb 1934178667Sjhb#define BGE_NVRAM_READCMD \ 1935178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1936178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1937178667Sjhb#define BGE_NVRAM_WRITECMD \ 1938178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1939178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1940178667Sjhb 1941178667Sjhb#define BGE_NVRAMSWARB_SET0 0x00000001 1942178667Sjhb#define BGE_NVRAMSWARB_SET1 0x00000002 1943178667Sjhb#define BGE_NVRAMSWARB_SET2 0x00000003 1944178667Sjhb#define BGE_NVRAMSWARB_SET3 0x00000004 1945178667Sjhb#define BGE_NVRAMSWARB_CLR0 0x00000010 1946178667Sjhb#define BGE_NVRAMSWARB_CLR1 0x00000020 1947178667Sjhb#define BGE_NVRAMSWARB_CLR2 0x00000040 1948178667Sjhb#define BGE_NVRAMSWARB_CLR3 0x00000080 1949178667Sjhb#define BGE_NVRAMSWARB_GNT0 0x00000100 1950178667Sjhb#define BGE_NVRAMSWARB_GNT1 0x00000200 1951178667Sjhb#define BGE_NVRAMSWARB_GNT2 0x00000400 1952178667Sjhb#define BGE_NVRAMSWARB_GNT3 0x00000800 1953178667Sjhb#define BGE_NVRAMSWARB_REQ0 0x00001000 1954178667Sjhb#define BGE_NVRAMSWARB_REQ1 0x00002000 1955178667Sjhb#define BGE_NVRAMSWARB_REQ2 0x00004000 1956178667Sjhb#define BGE_NVRAMSWARB_REQ3 0x00008000 1957178667Sjhb 1958178667Sjhb#define BGE_NVRAMACC_ENABLE 0x00000001 1959178667Sjhb#define BGE_NVRAMACC_WRENABLE 0x00000002 1960178667Sjhb 196184059Swpaul/* Mode control register */ 1962166676Sjkim#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1963166676Sjkim#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1964166676Sjkim#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1965166676Sjkim#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1966166676Sjkim#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1967226871Syongari#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 1968226871Syongari#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 1969166676Sjkim#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1970166676Sjkim#define BGE_MODECTL_NO_RX_CRC 0x00000400 1971166676Sjkim#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1972166676Sjkim#define BGE_MODECTL_NO_TX_INTR 0x00002000 1973166676Sjkim#define BGE_MODECTL_NO_RX_INTR 0x00004000 1974166676Sjkim#define BGE_MODECTL_FORCE_PCI32 0x00008000 1975226871Syongari#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 1976166676Sjkim#define BGE_MODECTL_STACKUP 0x00010000 1977166676Sjkim#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1978226871Syongari#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 1979166676Sjkim#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1980166676Sjkim#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1981166676Sjkim#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1982166676Sjkim#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1983166676Sjkim#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1984166676Sjkim#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1985166676Sjkim#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1986166676Sjkim#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1987166676Sjkim#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 198884059Swpaul 198984059Swpaul/* Misc. config register */ 1990166676Sjkim#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1991166676Sjkim#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1992178785Sbz#define BGE_MISCCFG_BOARD_ID 0x0001E000 1993178785Sbz#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1994178785Sbz#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1995178667Sjhb#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1996210152Syongari#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 199784059Swpaul 1998166676Sjkim#define BGE_32BITTIME_66MHZ (0x41 << 1) 199984059Swpaul 200084059Swpaul/* Misc. Local Control */ 2001166676Sjkim#define BGE_MLC_INTR_STATE 0x00000001 2002166676Sjkim#define BGE_MLC_INTR_CLR 0x00000002 2003166676Sjkim#define BGE_MLC_INTR_SET 0x00000004 2004166676Sjkim#define BGE_MLC_INTR_ONATTN 0x00000008 2005166676Sjkim#define BGE_MLC_MISCIO_IN0 0x00000100 2006166676Sjkim#define BGE_MLC_MISCIO_IN1 0x00000200 2007166676Sjkim#define BGE_MLC_MISCIO_IN2 0x00000400 2008166676Sjkim#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2009166676Sjkim#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2010166676Sjkim#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2011166676Sjkim#define BGE_MLC_MISCIO_OUT0 0x00004000 2012166676Sjkim#define BGE_MLC_MISCIO_OUT1 0x00008000 2013166676Sjkim#define BGE_MLC_MISCIO_OUT2 0x00010000 2014166676Sjkim#define BGE_MLC_EXTRAM_ENB 0x00020000 2015166676Sjkim#define BGE_MLC_SRAM_SIZE 0x001C0000 2016166676Sjkim#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2017166676Sjkim#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2018166676Sjkim#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2019166676Sjkim#define BGE_MLC_AUTO_EEPROM 0x01000000 202084059Swpaul 2021166676Sjkim#define BGE_SSRAMSIZE_256KB 0x00000000 2022166676Sjkim#define BGE_SSRAMSIZE_512KB 0x00040000 2023166676Sjkim#define BGE_SSRAMSIZE_1MB 0x00080000 2024166676Sjkim#define BGE_SSRAMSIZE_2MB 0x000C0000 2025166676Sjkim#define BGE_SSRAMSIZE_4MB 0x00100000 2026166676Sjkim#define BGE_SSRAMSIZE_8MB 0x00140000 2027166676Sjkim#define BGE_SSRAMSIZE_16M 0x00180000 202884059Swpaul 202984059Swpaul/* EEPROM address register */ 2030166676Sjkim#define BGE_EEADDR_ADDRESS 0x0000FFFC 2031166676Sjkim#define BGE_EEADDR_HALFCLK 0x01FF0000 2032166676Sjkim#define BGE_EEADDR_START 0x02000000 2033166676Sjkim#define BGE_EEADDR_DEVID 0x1C000000 2034166676Sjkim#define BGE_EEADDR_RESET 0x20000000 2035166676Sjkim#define BGE_EEADDR_DONE 0x40000000 2036166676Sjkim#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 203784059Swpaul 2038166676Sjkim#define BGE_EEDEVID(x) ((x & 7) << 26) 2039166676Sjkim#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2040166676Sjkim#define BGE_HALFCLK_384SCL 0x60 2041166676Sjkim#define BGE_EE_READCMD \ 204284059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 204384059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2044166676Sjkim#define BGE_EE_WRCMD \ 204584059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 204684059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 204784059Swpaul 204884059Swpaul/* EEPROM Control register */ 2049166676Sjkim#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2050166676Sjkim#define BGE_EECTL_CLKOUT 0x00000002 2051166676Sjkim#define BGE_EECTL_CLKIN 0x00000004 2052166676Sjkim#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2053166676Sjkim#define BGE_EECTL_DATAOUT 0x00000010 2054166676Sjkim#define BGE_EECTL_DATAIN 0x00000020 205584059Swpaul 205684059Swpaul/* MDI (MII/GMII) access register */ 2057166676Sjkim#define BGE_MDI_DATA 0x00000001 2058166676Sjkim#define BGE_MDI_DIR 0x00000002 2059166676Sjkim#define BGE_MDI_SEL 0x00000004 2060166676Sjkim#define BGE_MDI_CLK 0x00000008 206184059Swpaul 2062166676Sjkim#define BGE_MEMWIN_START 0x00008000 2063166676Sjkim#define BGE_MEMWIN_END 0x0000FFFF 206484059Swpaul 206584059Swpaul 2066166676Sjkim#define BGE_MEMWIN_READ(sc, x, val) \ 206784059Swpaul do { \ 206884059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 206984059Swpaul (0xFFFF0000 & x), 4); \ 207084059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 207184059Swpaul } while(0) 207284059Swpaul 2073166676Sjkim#define BGE_MEMWIN_WRITE(sc, x, val) \ 207484059Swpaul do { \ 207584059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 207684059Swpaul (0xFFFF0000 & x), 4); \ 207784059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 207884059Swpaul } while(0) 207984059Swpaul 208084059Swpaul/* 2081161847Sdavidch * This magic number is written to the firmware mailbox at 0xb50 2082161847Sdavidch * before a software reset is issued. After the internal firmware 2083199661Syongari * has completed its initialization it will write the opposite of 2084226814Syongari * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2085226814Syongari * allowing the driver to synchronize with the firmware. 208684059Swpaul */ 2087226814Syongari#define BGE_SRAM_FW_MB_MAGIC 0x4B657654 208884059Swpaul 208984059Swpaultypedef struct { 2090159395Sglebius uint32_t bge_addr_hi; 2091159395Sglebius uint32_t bge_addr_lo; 209284059Swpaul} bge_hostaddr; 2093118026Swpaul 2094166676Sjkim#define BGE_HOSTADDR(x, y) \ 2095115200Sps do { \ 2096159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2097159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2098115200Sps } while(0) 209984059Swpaul 2100166676Sjkim#define BGE_ADDR_LO(y) \ 2101159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 2102166676Sjkim#define BGE_ADDR_HI(y) \ 2103159395Sglebius ((uint64_t) (y) >> 32) 2104118026Swpaul 210584059Swpaul/* Ring control block structure */ 210684059Swpaulstruct bge_rcb { 210784059Swpaul bge_hostaddr bge_hostaddr; 2108159395Sglebius uint32_t bge_maxlen_flags; 2109159395Sglebius uint32_t bge_nicaddr; 211084059Swpaul}; 2111153437Syongari 2112153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 2113183896Smarius bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2114166676Sjkim#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 211584059Swpaul 2116166676Sjkim#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2117166676Sjkim#define BGE_RCB_FLAG_RING_DISABLED 0x0002 211884059Swpaul 211984059Swpaulstruct bge_tx_bd { 212084059Swpaul bge_hostaddr bge_addr; 2121153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2122159395Sglebius uint16_t bge_flags; 2123159395Sglebius uint16_t bge_len; 2124159395Sglebius uint16_t bge_vlan_tag; 2125199671Syongari uint16_t bge_mss; 2126153437Syongari#else 2127159395Sglebius uint16_t bge_len; 2128159395Sglebius uint16_t bge_flags; 2129199671Syongari uint16_t bge_mss; 2130159395Sglebius uint16_t bge_vlan_tag; 2131153437Syongari#endif 213284059Swpaul}; 213384059Swpaul 2134166676Sjkim#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2135166676Sjkim#define BGE_TXBDFLAG_IP_CSUM 0x0002 2136166676Sjkim#define BGE_TXBDFLAG_END 0x0004 2137166676Sjkim#define BGE_TXBDFLAG_IP_FRAG 0x0008 2138214428Syongari#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2139166676Sjkim#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2140214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2141214428Syongari#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2142166676Sjkim#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2143166676Sjkim#define BGE_TXBDFLAG_COAL_NOW 0x0080 2144166676Sjkim#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2145166676Sjkim#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2146214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2147214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2148166676Sjkim#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2149214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2150214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2151214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2152166676Sjkim#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2153166676Sjkim#define BGE_TXBDFLAG_NO_CRC 0x8000 215484059Swpaul 2155214428Syongari#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2156214428Syongari/* Bits [1:0] of the MSS header length. */ 2157214428Syongari#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2158214428Syongari 2159166676Sjkim#define BGE_NIC_TXRING_ADDR(ringno, size) \ 216084059Swpaul BGE_SEND_RING_1_TO_4 + \ 216184059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 216284059Swpaul 216384059Swpaulstruct bge_rx_bd { 216484059Swpaul bge_hostaddr bge_addr; 2165153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2166159395Sglebius uint16_t bge_len; 2167159395Sglebius uint16_t bge_idx; 2168159395Sglebius uint16_t bge_flags; 2169159395Sglebius uint16_t bge_type; 2170159395Sglebius uint16_t bge_tcp_udp_csum; 2171159395Sglebius uint16_t bge_ip_csum; 2172159395Sglebius uint16_t bge_vlan_tag; 2173159395Sglebius uint16_t bge_error_flag; 2174153437Syongari#else 2175159395Sglebius uint16_t bge_idx; 2176159395Sglebius uint16_t bge_len; 2177159395Sglebius uint16_t bge_type; 2178159395Sglebius uint16_t bge_flags; 2179159395Sglebius uint16_t bge_ip_csum; 2180159395Sglebius uint16_t bge_tcp_udp_csum; 2181159395Sglebius uint16_t bge_error_flag; 2182159395Sglebius uint16_t bge_vlan_tag; 2183153437Syongari#endif 2184159395Sglebius uint32_t bge_rsvd; 2185159395Sglebius uint32_t bge_opaque; 218684059Swpaul}; 218784059Swpaul 2188153239Sglebiusstruct bge_extrx_bd { 2189153239Sglebius bge_hostaddr bge_addr1; 2190153239Sglebius bge_hostaddr bge_addr2; 2191153239Sglebius bge_hostaddr bge_addr3; 2192153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2193159395Sglebius uint16_t bge_len2; 2194159395Sglebius uint16_t bge_len1; 2195159395Sglebius uint16_t bge_rsvd1; 2196159395Sglebius uint16_t bge_len3; 2197153437Syongari#else 2198159395Sglebius uint16_t bge_len1; 2199159395Sglebius uint16_t bge_len2; 2200159395Sglebius uint16_t bge_len3; 2201159395Sglebius uint16_t bge_rsvd1; 2202153437Syongari#endif 2203153239Sglebius bge_hostaddr bge_addr0; 2204153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2205159395Sglebius uint16_t bge_len0; 2206159395Sglebius uint16_t bge_idx; 2207159395Sglebius uint16_t bge_flags; 2208159395Sglebius uint16_t bge_type; 2209159395Sglebius uint16_t bge_tcp_udp_csum; 2210159395Sglebius uint16_t bge_ip_csum; 2211159395Sglebius uint16_t bge_vlan_tag; 2212159395Sglebius uint16_t bge_error_flag; 2213153437Syongari#else 2214159395Sglebius uint16_t bge_idx; 2215159395Sglebius uint16_t bge_len0; 2216159395Sglebius uint16_t bge_type; 2217159395Sglebius uint16_t bge_flags; 2218159395Sglebius uint16_t bge_ip_csum; 2219159395Sglebius uint16_t bge_tcp_udp_csum; 2220159395Sglebius uint16_t bge_error_flag; 2221159395Sglebius uint16_t bge_vlan_tag; 2222153437Syongari#endif 2223159395Sglebius uint32_t bge_rsvd0; 2224159395Sglebius uint32_t bge_opaque; 2225153239Sglebius}; 2226153239Sglebius 2227166676Sjkim#define BGE_RXBDFLAG_END 0x0004 2228166676Sjkim#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2229166676Sjkim#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2230166676Sjkim#define BGE_RXBDFLAG_ERROR 0x0400 2231166676Sjkim#define BGE_RXBDFLAG_MINI_RING 0x0800 2232166676Sjkim#define BGE_RXBDFLAG_IP_CSUM 0x1000 2233166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2234166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2235214428Syongari#define BGE_RXBDFLAG_IPV6 0x8000 223684059Swpaul 2237166676Sjkim#define BGE_RXERRFLAG_BAD_CRC 0x0001 2238166676Sjkim#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2239166676Sjkim#define BGE_RXERRFLAG_LINK_LOST 0x0004 2240166676Sjkim#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2241166676Sjkim#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2242166676Sjkim#define BGE_RXERRFLAG_RUNT 0x0020 2243166676Sjkim#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2244166676Sjkim#define BGE_RXERRFLAG_GIANT 0x0080 2245214428Syongari#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 224684059Swpaul 224784059Swpaulstruct bge_sts_idx { 2248153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2249159395Sglebius uint16_t bge_rx_prod_idx; 2250159395Sglebius uint16_t bge_tx_cons_idx; 2251153437Syongari#else 2252159395Sglebius uint16_t bge_tx_cons_idx; 2253159395Sglebius uint16_t bge_rx_prod_idx; 2254153437Syongari#endif 225584059Swpaul}; 225684059Swpaul 225784059Swpaulstruct bge_status_block { 2258159395Sglebius uint32_t bge_status; 2259214428Syongari uint32_t bge_status_tag; 2260153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2261159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2262159395Sglebius uint16_t bge_rx_std_cons_idx; 2263159395Sglebius uint16_t bge_rx_mini_cons_idx; 2264159395Sglebius uint16_t bge_rsvd1; 2265153437Syongari#else 2266159395Sglebius uint16_t bge_rx_std_cons_idx; 2267159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2268159395Sglebius uint16_t bge_rsvd1; 2269159395Sglebius uint16_t bge_rx_mini_cons_idx; 2270153437Syongari#endif 227184059Swpaul struct bge_sts_idx bge_idx[16]; 227284059Swpaul}; 227384059Swpaul 2274166676Sjkim#define BGE_STATFLAG_UPDATED 0x00000001 2275166676Sjkim#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2276166676Sjkim#define BGE_STATFLAG_ERROR 0x00000004 227784059Swpaul 227884059Swpaul 227984059Swpaul/* 228084059Swpaul * Broadcom Vendor ID 228184059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 228284059Swpaul * even though they're now manufactured by Broadcom) 228384059Swpaul */ 2284166676Sjkim#define BCOM_VENDORID 0x14E4 2285166676Sjkim#define BCOM_DEVICEID_BCM5700 0x1644 2286166676Sjkim#define BCOM_DEVICEID_BCM5701 0x1645 2287166676Sjkim#define BCOM_DEVICEID_BCM5702 0x1646 2288166676Sjkim#define BCOM_DEVICEID_BCM5702X 0x16A6 2289166676Sjkim#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2290166676Sjkim#define BCOM_DEVICEID_BCM5703 0x1647 2291166676Sjkim#define BCOM_DEVICEID_BCM5703X 0x16A7 2292166676Sjkim#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2293166676Sjkim#define BCOM_DEVICEID_BCM5704C 0x1648 2294166676Sjkim#define BCOM_DEVICEID_BCM5704S 0x16A8 2295166676Sjkim#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2296166676Sjkim#define BCOM_DEVICEID_BCM5705 0x1653 2297166676Sjkim#define BCOM_DEVICEID_BCM5705K 0x1654 2298166676Sjkim#define BCOM_DEVICEID_BCM5705F 0x166E 2299166676Sjkim#define BCOM_DEVICEID_BCM5705M 0x165D 2300166676Sjkim#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2301166676Sjkim#define BCOM_DEVICEID_BCM5714C 0x1668 2302166676Sjkim#define BCOM_DEVICEID_BCM5714S 0x1669 2303166676Sjkim#define BCOM_DEVICEID_BCM5715 0x1678 2304166676Sjkim#define BCOM_DEVICEID_BCM5715S 0x1679 2305214428Syongari#define BCOM_DEVICEID_BCM5717 0x1655 2306214428Syongari#define BCOM_DEVICEID_BCM5718 0x1656 2307221818Syongari#define BCOM_DEVICEID_BCM5719 0x1657 2308226871Syongari#define BCOM_DEVICEID_BCM5720_PP 0x1658 /* Not released to public. */ 2309226871Syongari#define BCOM_DEVICEID_BCM5720 0x165F 2310166676Sjkim#define BCOM_DEVICEID_BCM5721 0x1659 2311176883Sjhb#define BCOM_DEVICEID_BCM5722 0x165A 2312197832Sstas#define BCOM_DEVICEID_BCM5723 0x165B 2313166676Sjkim#define BCOM_DEVICEID_BCM5750 0x1676 2314166676Sjkim#define BCOM_DEVICEID_BCM5750M 0x167C 2315166676Sjkim#define BCOM_DEVICEID_BCM5751 0x1677 2316166676Sjkim#define BCOM_DEVICEID_BCM5751F 0x167E 2317166676Sjkim#define BCOM_DEVICEID_BCM5751M 0x167D 2318166676Sjkim#define BCOM_DEVICEID_BCM5752 0x1600 2319166676Sjkim#define BCOM_DEVICEID_BCM5752M 0x1601 2320166676Sjkim#define BCOM_DEVICEID_BCM5753 0x16F7 2321166676Sjkim#define BCOM_DEVICEID_BCM5753F 0x16FE 2322166676Sjkim#define BCOM_DEVICEID_BCM5753M 0x16FD 2323166676Sjkim#define BCOM_DEVICEID_BCM5754 0x167A 2324166676Sjkim#define BCOM_DEVICEID_BCM5754M 0x1672 2325166676Sjkim#define BCOM_DEVICEID_BCM5755 0x167B 2326166676Sjkim#define BCOM_DEVICEID_BCM5755M 0x1673 2327202268Sdelphij#define BCOM_DEVICEID_BCM5756 0x1674 2328197832Sstas#define BCOM_DEVICEID_BCM5761 0x1681 2329197832Sstas#define BCOM_DEVICEID_BCM5761E 0x1680 2330197832Sstas#define BCOM_DEVICEID_BCM5761S 0x1688 2331197832Sstas#define BCOM_DEVICEID_BCM5761SE 0x1689 2332197832Sstas#define BCOM_DEVICEID_BCM5764 0x1684 2333166676Sjkim#define BCOM_DEVICEID_BCM5780 0x166A 2334166676Sjkim#define BCOM_DEVICEID_BCM5780S 0x166B 2335166676Sjkim#define BCOM_DEVICEID_BCM5781 0x16DD 2336166676Sjkim#define BCOM_DEVICEID_BCM5782 0x1696 2337197832Sstas#define BCOM_DEVICEID_BCM5784 0x1698 2338197832Sstas#define BCOM_DEVICEID_BCM5785F 0x16a0 2339197832Sstas#define BCOM_DEVICEID_BCM5785G 0x1699 2340166676Sjkim#define BCOM_DEVICEID_BCM5786 0x169A 2341166676Sjkim#define BCOM_DEVICEID_BCM5787 0x169B 2342166676Sjkim#define BCOM_DEVICEID_BCM5787M 0x1693 2343197832Sstas#define BCOM_DEVICEID_BCM5787F 0x167f 2344166676Sjkim#define BCOM_DEVICEID_BCM5788 0x169C 2345166676Sjkim#define BCOM_DEVICEID_BCM5789 0x169D 2346166676Sjkim#define BCOM_DEVICEID_BCM5901 0x170D 2347166676Sjkim#define BCOM_DEVICEID_BCM5901A2 0x170E 2348166676Sjkim#define BCOM_DEVICEID_BCM5903M 0x16FF 2349178667Sjhb#define BCOM_DEVICEID_BCM5906 0x1712 2350178667Sjhb#define BCOM_DEVICEID_BCM5906M 0x1713 2351197832Sstas#define BCOM_DEVICEID_BCM57760 0x1690 2352221445Syongari#define BCOM_DEVICEID_BCM57761 0x16B0 2353221445Syongari#define BCOM_DEVICEID_BCM57765 0x16B4 2354197832Sstas#define BCOM_DEVICEID_BCM57780 0x1692 2355221445Syongari#define BCOM_DEVICEID_BCM57781 0x16B1 2356221445Syongari#define BCOM_DEVICEID_BCM57785 0x16B5 2357197832Sstas#define BCOM_DEVICEID_BCM57788 0x1691 2358197832Sstas#define BCOM_DEVICEID_BCM57790 0x1694 2359221445Syongari#define BCOM_DEVICEID_BCM57791 0x16B2 2360221445Syongari#define BCOM_DEVICEID_BCM57795 0x16B6 236184059Swpaul 236284059Swpaul/* 236384059Swpaul * Alteon AceNIC PCI vendor/device ID. 236484059Swpaul */ 2365166676Sjkim#define ALTEON_VENDORID 0x12AE 2366166676Sjkim#define ALTEON_DEVICEID_ACENIC 0x0001 2367166676Sjkim#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2368166676Sjkim#define ALTEON_DEVICEID_BCM5700 0x0003 2369166676Sjkim#define ALTEON_DEVICEID_BCM5701 0x0004 237084059Swpaul 237184059Swpaul/* 2372162982Sglebius * 3Com 3c996 PCI vendor/device ID. 237384059Swpaul */ 2374166676Sjkim#define TC_VENDORID 0x10B7 2375166676Sjkim#define TC_DEVICEID_3C996 0x0003 237684059Swpaul 237784059Swpaul/* 237884059Swpaul * SysKonnect PCI vendor ID 237984059Swpaul */ 2380166676Sjkim#define SK_VENDORID 0x1148 2381166676Sjkim#define SK_DEVICEID_ALTIMA 0x4400 2382166676Sjkim#define SK_SUBSYSID_9D21 0x4421 2383166676Sjkim#define SK_SUBSYSID_9D41 0x4441 238484059Swpaul 238584059Swpaul/* 238689835Sjdp * Altima PCI vendor/device ID. 238789835Sjdp */ 2388166676Sjkim#define ALTIMA_VENDORID 0x173b 2389166676Sjkim#define ALTIMA_DEVICE_AC1000 0x03e8 2390166676Sjkim#define ALTIMA_DEVICE_AC1002 0x03e9 2391166676Sjkim#define ALTIMA_DEVICE_AC9100 0x03ea 239289835Sjdp 239389835Sjdp/* 2394119157Sambrisko * Dell PCI vendor ID 2395119157Sambrisko */ 2396119157Sambrisko 2397166676Sjkim#define DELL_VENDORID 0x1028 2398119157Sambrisko 2399119157Sambrisko/* 2400159637Sglebius * Apple PCI vendor ID. 2401159637Sglebius */ 2402166676Sjkim#define APPLE_VENDORID 0x106b 2403166676Sjkim#define APPLE_DEVICE_BCM5701 0x1645 2404159637Sglebius 2405159637Sglebius/* 2406169152Smarius * Sun PCI vendor ID 2407169152Smarius */ 2408169152Smarius#define SUN_VENDORID 0x108e 2409169152Smarius 2410169152Smarius/* 2411197832Sstas * Fujitsu vendor/device IDs 2412197832Sstas */ 2413197832Sstas#define FJTSU_VENDORID 0x10cf 2414197832Sstas#define FJTSU_DEVICEID_PW008GE5 0x11a1 2415197832Sstas#define FJTSU_DEVICEID_PW008GE4 0x11a2 2416197832Sstas#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2417197832Sstas 2418197832Sstas/* 241984059Swpaul * Offset of MAC address inside EEPROM. 242084059Swpaul */ 2421166676Sjkim#define BGE_EE_MAC_OFFSET 0x7C 2422178667Sjhb#define BGE_EE_MAC_OFFSET_5906 0x10 2423166676Sjkim#define BGE_EE_HWCFG_OFFSET 0xC8 242484059Swpaul 2425166676Sjkim#define BGE_HWCFG_VOLTAGE 0x00000003 2426166676Sjkim#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2427166676Sjkim#define BGE_HWCFG_MEDIA 0x00000030 2428166676Sjkim#define BGE_HWCFG_ASF 0x00000080 242993751Swpaul 2430166676Sjkim#define BGE_VOLTAGE_1POINT3 0x00000000 2431166676Sjkim#define BGE_VOLTAGE_1POINT8 0x00000001 243293751Swpaul 2433166676Sjkim#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2434166676Sjkim#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2435166676Sjkim#define BGE_PHYLEDMODE_SINGLELED 0x00000008 243693751Swpaul 2437166676Sjkim#define BGE_MEDIA_UNSPEC 0x00000000 2438166676Sjkim#define BGE_MEDIA_COPPER 0x00000010 2439166676Sjkim#define BGE_MEDIA_FIBER 0x00000020 244093751Swpaul 2441166676Sjkim#define BGE_TICKS_PER_SEC 1000000 244284059Swpaul 244384059Swpaul/* 244484059Swpaul * Ring size constants. 244584059Swpaul */ 2446166676Sjkim#define BGE_EVENT_RING_CNT 256 2447166676Sjkim#define BGE_CMD_RING_CNT 64 2448166676Sjkim#define BGE_STD_RX_RING_CNT 512 2449166676Sjkim#define BGE_JUMBO_RX_RING_CNT 256 2450166676Sjkim#define BGE_MINI_RX_RING_CNT 1024 2451166676Sjkim#define BGE_RETURN_RING_CNT 1024 245284059Swpaul 2453117659Swpaul/* 5705 has smaller return ring size */ 2454117659Swpaul 2455166676Sjkim#define BGE_RETURN_RING_CNT_5705 512 2456117659Swpaul 245784059Swpaul/* 245884059Swpaul * Possible TX ring sizes. 245984059Swpaul */ 2460166676Sjkim#define BGE_TX_RING_CNT_128 128 2461166676Sjkim#define BGE_TX_RING_BASE_128 0x3800 246284059Swpaul 2463166676Sjkim#define BGE_TX_RING_CNT_256 256 2464166676Sjkim#define BGE_TX_RING_BASE_256 0x3000 246584059Swpaul 2466166676Sjkim#define BGE_TX_RING_CNT_512 512 2467166676Sjkim#define BGE_TX_RING_BASE_512 0x2000 246884059Swpaul 2469166676Sjkim#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2470166676Sjkim#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 247184059Swpaul 247284059Swpaul/* 247384059Swpaul * Tigon III statistics counters. 247484059Swpaul */ 2475117659Swpaul/* Statistics maintained MAC Receive block. */ 2476117659Swpaulstruct bge_rx_mac_stats { 247784059Swpaul bge_hostaddr ifHCInOctets; 247884059Swpaul bge_hostaddr Reserved1; 247984059Swpaul bge_hostaddr etherStatsFragments; 248084059Swpaul bge_hostaddr ifHCInUcastPkts; 248184059Swpaul bge_hostaddr ifHCInMulticastPkts; 248284059Swpaul bge_hostaddr ifHCInBroadcastPkts; 248384059Swpaul bge_hostaddr dot3StatsFCSErrors; 248484059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 248584059Swpaul bge_hostaddr xonPauseFramesReceived; 248684059Swpaul bge_hostaddr xoffPauseFramesReceived; 248784059Swpaul bge_hostaddr macControlFramesReceived; 248884059Swpaul bge_hostaddr xoffStateEntered; 248984059Swpaul bge_hostaddr dot3StatsFramesTooLong; 249084059Swpaul bge_hostaddr etherStatsJabbers; 249184059Swpaul bge_hostaddr etherStatsUndersizePkts; 249284059Swpaul bge_hostaddr inRangeLengthError; 249384059Swpaul bge_hostaddr outRangeLengthError; 249484059Swpaul bge_hostaddr etherStatsPkts64Octets; 249584059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 249684059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 249784059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 249884059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 249984059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 250084059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 250184059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 250284059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 250384059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2504117659Swpaul}; 250584059Swpaul 250684059Swpaul 2507117659Swpaul/* Statistics maintained MAC Transmit block. */ 2508117659Swpaulstruct bge_tx_mac_stats { 250984059Swpaul bge_hostaddr ifHCOutOctets; 251084059Swpaul bge_hostaddr Reserved2; 251184059Swpaul bge_hostaddr etherStatsCollisions; 251284059Swpaul bge_hostaddr outXonSent; 251384059Swpaul bge_hostaddr outXoffSent; 251484059Swpaul bge_hostaddr flowControlDone; 251584059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 251684059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 251784059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 251884059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 251984059Swpaul bge_hostaddr Reserved3; 252084059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 252184059Swpaul bge_hostaddr dot3StatsLateCollisions; 252284059Swpaul bge_hostaddr dot3Collided2Times; 252384059Swpaul bge_hostaddr dot3Collided3Times; 252484059Swpaul bge_hostaddr dot3Collided4Times; 252584059Swpaul bge_hostaddr dot3Collided5Times; 252684059Swpaul bge_hostaddr dot3Collided6Times; 252784059Swpaul bge_hostaddr dot3Collided7Times; 252884059Swpaul bge_hostaddr dot3Collided8Times; 252984059Swpaul bge_hostaddr dot3Collided9Times; 253084059Swpaul bge_hostaddr dot3Collided10Times; 253184059Swpaul bge_hostaddr dot3Collided11Times; 253284059Swpaul bge_hostaddr dot3Collided12Times; 253384059Swpaul bge_hostaddr dot3Collided13Times; 253484059Swpaul bge_hostaddr dot3Collided14Times; 253584059Swpaul bge_hostaddr dot3Collided15Times; 253684059Swpaul bge_hostaddr ifHCOutUcastPkts; 253784059Swpaul bge_hostaddr ifHCOutMulticastPkts; 253884059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 253984059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 254084059Swpaul bge_hostaddr ifOutDiscards; 254184059Swpaul bge_hostaddr ifOutErrors; 2542117659Swpaul}; 254384059Swpaul 2544117659Swpaul/* Stats counters access through registers */ 2545213283Syongaristruct bge_mac_stats { 2546213283Syongari /* TX MAC statistics */ 2547213283Syongari uint64_t ifHCOutOctets; 2548213283Syongari uint64_t Reserved0; 2549213283Syongari uint64_t etherStatsCollisions; 2550213283Syongari uint64_t outXonSent; 2551213283Syongari uint64_t outXoffSent; 2552213283Syongari uint64_t Reserved1; 2553213283Syongari uint64_t dot3StatsInternalMacTransmitErrors; 2554213283Syongari uint64_t dot3StatsSingleCollisionFrames; 2555213283Syongari uint64_t dot3StatsMultipleCollisionFrames; 2556213283Syongari uint64_t dot3StatsDeferredTransmissions; 2557213283Syongari uint64_t Reserved2; 2558213283Syongari uint64_t dot3StatsExcessiveCollisions; 2559213283Syongari uint64_t dot3StatsLateCollisions; 2560213283Syongari uint64_t Reserved3[14]; 2561213283Syongari uint64_t ifHCOutUcastPkts; 2562213283Syongari uint64_t ifHCOutMulticastPkts; 2563213283Syongari uint64_t ifHCOutBroadcastPkts; 2564213283Syongari uint64_t Reserved4[2]; 2565213283Syongari /* RX MAC statistics */ 2566213283Syongari uint64_t ifHCInOctets; 2567213283Syongari uint64_t Reserved5; 2568213283Syongari uint64_t etherStatsFragments; 2569213283Syongari uint64_t ifHCInUcastPkts; 2570213283Syongari uint64_t ifHCInMulticastPkts; 2571213283Syongari uint64_t ifHCInBroadcastPkts; 2572213283Syongari uint64_t dot3StatsFCSErrors; 2573213283Syongari uint64_t dot3StatsAlignmentErrors; 2574213283Syongari uint64_t xonPauseFramesReceived; 2575213283Syongari uint64_t xoffPauseFramesReceived; 2576213283Syongari uint64_t macControlFramesReceived; 2577213283Syongari uint64_t xoffStateEntered; 2578213283Syongari uint64_t dot3StatsFramesTooLong; 2579213283Syongari uint64_t etherStatsJabbers; 2580213283Syongari uint64_t etherStatsUndersizePkts; 2581213283Syongari /* Receive List Placement control */ 2582213283Syongari uint64_t FramesDroppedDueToFilters; 2583213283Syongari uint64_t DmaWriteQueueFull; 2584213283Syongari uint64_t DmaWriteHighPriQueueFull; 2585213283Syongari uint64_t NoMoreRxBDs; 2586213283Syongari uint64_t InputDiscards; 2587213283Syongari uint64_t InputErrors; 2588213283Syongari uint64_t RecvThresholdHit; 2589117659Swpaul}; 2590117659Swpaul 2591117659Swpaulstruct bge_stats { 2592159395Sglebius uint8_t Reserved0[256]; 2593117659Swpaul 2594117659Swpaul /* Statistics maintained by Receive MAC. */ 2595117659Swpaul struct bge_rx_mac_stats rxstats; 2596117659Swpaul 2597117659Swpaul bge_hostaddr Unused1[37]; 2598117659Swpaul 2599117659Swpaul /* Statistics maintained by Transmit MAC. */ 2600117659Swpaul struct bge_tx_mac_stats txstats; 2601117659Swpaul 260284059Swpaul bge_hostaddr Unused2[31]; 260384059Swpaul 260484059Swpaul /* Statistics maintained by Receive List Placement. */ 260584059Swpaul bge_hostaddr COSIfHCInPkts[16]; 260684059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 260784059Swpaul bge_hostaddr nicDmaWriteQueueFull; 260884059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 260984059Swpaul bge_hostaddr nicNoMoreRxBDs; 261084059Swpaul bge_hostaddr ifInDiscards; 261184059Swpaul bge_hostaddr ifInErrors; 261284059Swpaul bge_hostaddr nicRecvThresholdHit; 261384059Swpaul 261484059Swpaul bge_hostaddr Unused3[9]; 261584059Swpaul 261684059Swpaul /* Statistics maintained by Send Data Initiator. */ 261784059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 261884059Swpaul bge_hostaddr nicDmaReadQueueFull; 261984059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 262084059Swpaul bge_hostaddr nicSendDataCompQueueFull; 262184059Swpaul 262284059Swpaul /* Statistics maintained by Host Coalescing. */ 262384059Swpaul bge_hostaddr nicRingSetSendProdIndex; 262484059Swpaul bge_hostaddr nicRingStatusUpdate; 262584059Swpaul bge_hostaddr nicInterrupts; 262684059Swpaul bge_hostaddr nicAvoidedInterrupts; 262784059Swpaul bge_hostaddr nicSendThresholdHit; 262884059Swpaul 2629159395Sglebius uint8_t Reserved4[320]; 263084059Swpaul}; 263184059Swpaul 263284059Swpaul/* 263384059Swpaul * Tigon general information block. This resides in host memory 263484059Swpaul * and contains the status counters, ring control blocks and 263584059Swpaul * producer pointers. 263684059Swpaul */ 263784059Swpaul 263884059Swpaulstruct bge_gib { 263984059Swpaul struct bge_stats bge_stats; 264084059Swpaul struct bge_rcb bge_tx_rcb[16]; 264184059Swpaul struct bge_rcb bge_std_rx_rcb; 264284059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 264384059Swpaul struct bge_rcb bge_mini_rx_rcb; 264484059Swpaul struct bge_rcb bge_return_rcb; 264584059Swpaul}; 264684059Swpaul 2647166676Sjkim#define BGE_FRAMELEN 1518 2648166676Sjkim#define BGE_MAX_FRAMELEN 1536 2649166676Sjkim#define BGE_JUMBO_FRAMELEN 9018 2650166676Sjkim#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2651166676Sjkim#define BGE_MIN_FRAMELEN 60 265284059Swpaul 265384059Swpaul/* 265484059Swpaul * Other utility macros. 265584059Swpaul */ 2656166676Sjkim#define BGE_INC(x, y) (x) = (x + 1) % y 265784059Swpaul 265884059Swpaul/* 265984059Swpaul * Register access macros. The Tigon always uses memory mapped register 266084059Swpaul * accesses and all registers must be accessed with 32 bit operations. 266184059Swpaul */ 266284059Swpaul 2663166676Sjkim#define CSR_WRITE_4(sc, reg, val) \ 2664183896Smarius bus_write_4(sc->bge_res, reg, val) 266584059Swpaul 2666166676Sjkim#define CSR_READ_4(sc, reg) \ 2667183896Smarius bus_read_4(sc->bge_res, reg) 266884059Swpaul 2669166676Sjkim#define BGE_SETBIT(sc, reg, x) \ 2670106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2671166676Sjkim#define BGE_CLRBIT(sc, reg, x) \ 2672106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 267384059Swpaul 2674166676Sjkim#define PCI_SETBIT(dev, reg, x, s) \ 2675106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2676166676Sjkim#define PCI_CLRBIT(dev, reg, x, s) \ 2677106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 267884059Swpaul 267984059Swpaul/* 2680208917Syongari * Memory management stuff. 268184059Swpaul */ 268284059Swpaul 2683166676Sjkim#define BGE_NSEG_JUMBO 4 2684199671Syongari#define BGE_NSEG_NEW 32 2685199671Syongari#define BGE_TSOSEG_SZ 4096 2686153239Sglebius 2687199670Syongari/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2688199670Syongari#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2689199670Syongari#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2690199670Syongari#else 2691199670Syongari#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2692199670Syongari#endif 2693199670Syongari 2694212065Syongari#ifdef PAE 2695212065Syongari#define BGE_DMA_BNDRY 0x80000000 2696212065Syongari#else 2697212061Syongari#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2698212065Syongari#define BGE_DMA_BNDRY 0x100000000 2699212061Syongari#else 2700212065Syongari#define BGE_DMA_BNDRY 0 2701212061Syongari#endif 2702212065Syongari#endif 2703212061Syongari 270484059Swpaul/* 270584059Swpaul * Ring structures. Most of these reside in host memory and we tell 270684059Swpaul * the NIC where they are via the ring control blocks. The exceptions 270784059Swpaul * are the tx and command rings, which live in NIC memory and which 270884059Swpaul * we access via the shared memory window. 270984059Swpaul */ 2710118026Swpaul 271184059Swpaulstruct bge_ring_data { 2712118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2713118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2714153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2715118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2716118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2717118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2718118026Swpaul struct bge_tx_bd *bge_tx_ring; 2719118026Swpaul bus_addr_t bge_tx_ring_paddr; 2720118026Swpaul struct bge_status_block *bge_status_block; 2721118026Swpaul bus_addr_t bge_status_block_paddr; 2722118026Swpaul struct bge_stats *bge_stats; 2723118026Swpaul bus_addr_t bge_stats_paddr; 272484059Swpaul struct bge_gib bge_info; 272584059Swpaul}; 272684059Swpaul 2727166676Sjkim#define BGE_STD_RX_RING_SZ \ 2728118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2729166676Sjkim#define BGE_JUMBO_RX_RING_SZ \ 2730153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2731166676Sjkim#define BGE_TX_RING_SZ \ 2732118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2733166676Sjkim#define BGE_RX_RTN_RING_SZ(x) \ 2734118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2735118026Swpaul 2736166676Sjkim#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2737118026Swpaul 2738166676Sjkim#define BGE_STATS_SZ sizeof (struct bge_stats) 2739118026Swpaul 274084059Swpaul/* 274184059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 274284059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 274384059Swpaul * not the other way around. 274484059Swpaul */ 274584059Swpaulstruct bge_chain_data { 2746118026Swpaul bus_dma_tag_t bge_parent_tag; 2747212061Syongari bus_dma_tag_t bge_buffer_tag; 2748118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2749118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2750118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2751118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2752118026Swpaul bus_dma_tag_t bge_status_tag; 2753118026Swpaul bus_dma_tag_t bge_stats_tag; 2754198927Syongari bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2755198927Syongari bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2756198927Syongari bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2757118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2758199011Syongari bus_dmamap_t bge_rx_std_sparemap; 2759118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2760199011Syongari bus_dmamap_t bge_rx_jumbo_sparemap; 2761118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2762118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2763118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2764118026Swpaul bus_dmamap_t bge_tx_ring_map; 2765118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2766118026Swpaul bus_dmamap_t bge_status_map; 2767118026Swpaul bus_dmamap_t bge_stats_map; 276884059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 276984059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 277084059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2771208862Syongari int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2772208862Syongari int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 277384059Swpaul}; 277484059Swpaul 2775118026Swpaulstruct bge_dmamap_arg { 2776118026Swpaul bus_addr_t bge_busaddr; 2777118026Swpaul}; 2778118026Swpaul 2779166676Sjkim#define BGE_HWREV_TIGON 0x01 2780166676Sjkim#define BGE_HWREV_TIGON_II 0x02 2781166676Sjkim#define BGE_TIMEOUT 100000 2782166676Sjkim#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 278384059Swpaul 278484059Swpaulstruct bge_bcom_hack { 278584059Swpaul int reg; 278684059Swpaul int val; 278784059Swpaul}; 278884059Swpaul 2789166676Sjkim#define ASF_ENABLE 1 2790166676Sjkim#define ASF_NEW_HANDSHAKE 2 2791166676Sjkim#define ASF_STACKUP 4 2792162169Sambrisko 279384059Swpaulstruct bge_softc { 2794147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 279584059Swpaul device_t bge_dev; 2796122497Ssam struct mtx bge_mtx; 279784059Swpaul device_t bge_miibus; 279884059Swpaul void *bge_intrhand; 279984059Swpaul struct resource *bge_irq; 280084059Swpaul struct resource *bge_res; 280184059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2802199664Syongari int bge_expcap; 2803199664Syongari int bge_msicap; 2804199664Syongari int bge_pcixcap; 2805161546Sglebius uint32_t bge_flags; 2806166676Sjkim#define BGE_FLAG_TBI 0x00000001 2807166676Sjkim#define BGE_FLAG_JUMBO 0x00000002 2808220368Syongari#define BGE_FLAG_JUMBO_STD 0x00000004 2809178996Smarius#define BGE_FLAG_EADDR 0x00000008 2810202293Syongari#define BGE_FLAG_MII_SERDES 0x00000010 2811213485Syongari#define BGE_FLAG_CPMU_PRESENT 0x00000020 2812214428Syongari#define BGE_FLAG_TAGGED_STATUS 0x00000040 2813166676Sjkim#define BGE_FLAG_MSI 0x00000100 2814166676Sjkim#define BGE_FLAG_PCIX 0x00000200 2815166676Sjkim#define BGE_FLAG_PCIE 0x00000400 2816199671Syongari#define BGE_FLAG_TSO 0x00000800 2817214428Syongari#define BGE_FLAG_TSO3 0x00001000 2818214428Syongari#define BGE_FLAG_JUMBO_FRAME 0x00002000 2819213464Syongari#define BGE_FLAG_5700_FAMILY 0x00010000 2820213464Syongari#define BGE_FLAG_5705_PLUS 0x00020000 2821213464Syongari#define BGE_FLAG_5714_FAMILY 0x00040000 2822213464Syongari#define BGE_FLAG_575X_PLUS 0x00080000 2823213464Syongari#define BGE_FLAG_5755_PLUS 0x00100000 2824213464Syongari#define BGE_FLAG_5788 0x00200000 2825214428Syongari#define BGE_FLAG_5717_PLUS 0x00400000 2826213464Syongari#define BGE_FLAG_40BIT_BUG 0x01000000 2827213464Syongari#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2828213464Syongari#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2829214087Syongari#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2830226807Syongari#define BGE_FLAG_4K_RDMA_BUG 0x10000000 2831213464Syongari uint32_t bge_phy_flags; 2832221468Syongari#define BGE_PHY_NO_WIRESPEED 0x00000001 2833213464Syongari#define BGE_PHY_ADC_BUG 0x00000002 2834213464Syongari#define BGE_PHY_5704_A0_BUG 0x00000004 2835213464Syongari#define BGE_PHY_JITTER_BUG 0x00000008 2836213464Syongari#define BGE_PHY_BER_BUG 0x00000010 2837213464Syongari#define BGE_PHY_ADJUST_TRIM 0x00000020 2838213464Syongari#define BGE_PHY_CRC_BUG 0x00000040 2839213464Syongari#define BGE_PHY_NO_3LED 0x00000080 2840159395Sglebius uint32_t bge_chipid; 2841197832Sstas uint32_t bge_asicrev; 2842197832Sstas uint32_t bge_chiprev; 2843162169Sambrisko uint8_t bge_asf_mode; 2844162169Sambrisko uint8_t bge_asf_count; 2845118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 284684059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 2847159395Sglebius uint16_t bge_tx_saved_considx; 2848159395Sglebius uint16_t bge_rx_saved_considx; 2849159395Sglebius uint16_t bge_ev_saved_considx; 2850159395Sglebius uint16_t bge_return_ring_cnt; 2851159395Sglebius uint16_t bge_std; /* current std ring head */ 2852159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 2853159395Sglebius uint32_t bge_stat_ticks; 2854159395Sglebius uint32_t bge_rx_coal_ticks; 2855159395Sglebius uint32_t bge_tx_coal_ticks; 2856159395Sglebius uint32_t bge_tx_prodidx; 2857159395Sglebius uint32_t bge_rx_max_coal_bds; 2858159395Sglebius uint32_t bge_tx_max_coal_bds; 2859213485Syongari uint32_t bge_mi_mode; 286084059Swpaul int bge_if_flags; 286184059Swpaul int bge_txcnt; 2862155180Soleg int bge_link; /* link state */ 2863155180Soleg int bge_link_evt; /* pending link event */ 2864164769Sglebius int bge_timer; 2865200264Syongari int bge_forced_collapse; 2866211596Syongari int bge_forced_udpcsum; 2867230337Syongari int bge_msi; 2868211596Syongari int bge_csum_features; 2869122497Ssam struct callout bge_stat_ch; 2870164780Sjkim uint32_t bge_rx_discards; 2871164780Sjkim uint32_t bge_tx_discards; 2872164780Sjkim uint32_t bge_tx_collisions; 2873151553Sglebius#ifdef DEVICE_POLLING 2874151553Sglebius int rxcycles; 2875151553Sglebius#endif /* DEVICE_POLLING */ 2876213283Syongari struct bge_mac_stats bge_mac_stats; 2877199668Syongari struct task bge_intr_task; 2878199668Syongari struct taskqueue *bge_tq; 287984059Swpaul}; 2880122497Ssam 2881122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2882122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2883122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2884122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2885122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2886122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2887