if_bgereg.h revision 226814
1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 226814 2011-10-26 21:05:45Z yongari $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 64166676Sjkim#define BGE_PAGE_ZERO 0x00000000 65166676Sjkim#define BGE_PAGE_ZERO_END 0x000000FF 66166676Sjkim#define BGE_SEND_RING_RCB 0x00000100 67166676Sjkim#define BGE_SEND_RING_RCB_END 0x000001FF 68166676Sjkim#define BGE_RX_RETURN_RING_RCB 0x00000200 69166676Sjkim#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70166676Sjkim#define BGE_STATS_BLOCK 0x00000300 71166676Sjkim#define BGE_STATS_BLOCK_END 0x00000AFF 72166676Sjkim#define BGE_STATUS_BLOCK 0x00000B00 73166676Sjkim#define BGE_STATUS_BLOCK_END 0x00000B4F 74226814Syongari#define BGE_SRAM_FW_MB 0x00000B50 75226814Syongari#define BGE_SRAM_DATA_SIG 0x00000B54 76226814Syongari#define BGE_SRAM_DATA_CFG 0x00000B58 77226814Syongari#define BGE_SRAM_FW_CMD_MB 0x00000B78 78226814Syongari#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 79226814Syongari#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 80166676Sjkim#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81166676Sjkim#define BGE_UNMAPPED 0x00001000 82166676Sjkim#define BGE_UNMAPPED_END 0x00001FFF 83166676Sjkim#define BGE_DMA_DESCRIPTORS 0x00002000 84166676Sjkim#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85214428Syongari#define BGE_SEND_RING_5717 0x00004000 86166676Sjkim#define BGE_SEND_RING_1_TO_4 0x00004000 87166676Sjkim#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8884059Swpaul 89166676Sjkim/* Firmware interface */ 90226814Syongari#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 91166676Sjkim#define BGE_FW_DRV_ALIVE 0x00000001 92166676Sjkim#define BGE_FW_PAUSE 0x00000002 93166676Sjkim 9484059Swpaul/* Mappings for internal memory configuration */ 95166676Sjkim#define BGE_STD_RX_RINGS 0x00006000 96166676Sjkim#define BGE_STD_RX_RINGS_END 0x00006FFF 97166676Sjkim#define BGE_JUMBO_RX_RINGS 0x00007000 98166676Sjkim#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 99166676Sjkim#define BGE_BUFFPOOL_1 0x00008000 100166676Sjkim#define BGE_BUFFPOOL_1_END 0x0000FFFF 101166676Sjkim#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 102166676Sjkim#define BGE_BUFFPOOL_2_END 0x00017FFF 103166676Sjkim#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 104166676Sjkim#define BGE_BUFFPOOL_3_END 0x0001FFFF 105214428Syongari#define BGE_STD_RX_RINGS_5717 0x00040000 106214428Syongari#define BGE_JUMBO_RX_RINGS_5717 0x00044400 10784059Swpaul 10884059Swpaul/* Mappings for external SSRAM configurations */ 109166676Sjkim#define BGE_SEND_RING_5_TO_6 0x00006000 110166676Sjkim#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 111166676Sjkim#define BGE_SEND_RING_7_TO_8 0x00007000 112166676Sjkim#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 113166676Sjkim#define BGE_SEND_RING_9_TO_16 0x00008000 114166676Sjkim#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 115166676Sjkim#define BGE_EXT_STD_RX_RINGS 0x0000C000 116166676Sjkim#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 117166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 118166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 119166676Sjkim#define BGE_MINI_RX_RINGS 0x0000E000 120166676Sjkim#define BGE_MINI_RX_RINGS_END 0x0000FFFF 121166676Sjkim#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 122166676Sjkim#define BGE_AVAIL_REGION1_END 0x00017FFF 123166676Sjkim#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 124166676Sjkim#define BGE_AVAIL_REGION2_END 0x0001FFFF 125166676Sjkim#define BGE_EXT_SSRAM 0x00020000 126166676Sjkim#define BGE_EXT_SSRAM_END 0x000FFFFF 12784059Swpaul 12884059Swpaul 12984059Swpaul/* 13084059Swpaul * BCM570x register offsets. These are memory mapped registers 13184059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 13284059Swpaul * Each register must be accessed using 32 bit operations. 13384059Swpaul * 13484059Swpaul * All registers are accessed through a 32K shared memory block. 13584059Swpaul * The first group of registers are actually copies of the PCI 13684059Swpaul * configuration space registers. 13784059Swpaul */ 13884059Swpaul 13984059Swpaul/* 14084059Swpaul * PCI registers defined in the PCI 2.2 spec. 14184059Swpaul */ 142166676Sjkim#define BGE_PCI_VID 0x00 143166676Sjkim#define BGE_PCI_DID 0x02 144166676Sjkim#define BGE_PCI_CMD 0x04 145166676Sjkim#define BGE_PCI_STS 0x06 146166676Sjkim#define BGE_PCI_REV 0x08 147166676Sjkim#define BGE_PCI_CLASS 0x09 148166676Sjkim#define BGE_PCI_CACHESZ 0x0C 149166676Sjkim#define BGE_PCI_LATTIMER 0x0D 150166676Sjkim#define BGE_PCI_HDRTYPE 0x0E 151166676Sjkim#define BGE_PCI_BIST 0x0F 152166676Sjkim#define BGE_PCI_BAR0 0x10 153166676Sjkim#define BGE_PCI_BAR1 0x14 154166676Sjkim#define BGE_PCI_SUBSYS 0x2C 155166676Sjkim#define BGE_PCI_SUBVID 0x2E 156166676Sjkim#define BGE_PCI_ROMBASE 0x30 157166676Sjkim#define BGE_PCI_CAPPTR 0x34 158166676Sjkim#define BGE_PCI_INTLINE 0x3C 159166676Sjkim#define BGE_PCI_INTPIN 0x3D 160166676Sjkim#define BGE_PCI_MINGNT 0x3E 161166676Sjkim#define BGE_PCI_MAXLAT 0x3F 162166676Sjkim#define BGE_PCI_PCIXCAP 0x40 163166676Sjkim#define BGE_PCI_NEXTPTR_PM 0x41 164166676Sjkim#define BGE_PCI_PCIX_CMD 0x42 165166676Sjkim#define BGE_PCI_PCIX_STS 0x44 166166676Sjkim#define BGE_PCI_PWRMGMT_CAPID 0x48 167166676Sjkim#define BGE_PCI_NEXTPTR_VPD 0x49 168166676Sjkim#define BGE_PCI_PWRMGMT_CAPS 0x4A 169166676Sjkim#define BGE_PCI_PWRMGMT_CMD 0x4C 170166676Sjkim#define BGE_PCI_PWRMGMT_STS 0x4D 171166676Sjkim#define BGE_PCI_PWRMGMT_DATA 0x4F 172166676Sjkim#define BGE_PCI_VPD_CAPID 0x50 173166676Sjkim#define BGE_PCI_NEXTPTR_MSI 0x51 174166676Sjkim#define BGE_PCI_VPD_ADDR 0x52 175166676Sjkim#define BGE_PCI_VPD_DATA 0x54 176166676Sjkim#define BGE_PCI_MSI_CAPID 0x58 177166676Sjkim#define BGE_PCI_NEXTPTR_NONE 0x59 178166676Sjkim#define BGE_PCI_MSI_CTL 0x5A 179166676Sjkim#define BGE_PCI_MSI_ADDR_HI 0x5C 180166676Sjkim#define BGE_PCI_MSI_ADDR_LO 0x60 181166676Sjkim#define BGE_PCI_MSI_DATA 0x64 18284059Swpaul 183190194Smarius/* 184190194Smarius * PCI Express definitions 185190194Smarius * According to 186190194Smarius * PCI Express base specification, REV. 1.0a 187190194Smarius */ 188190194Smarius 189190194Smarius/* PCI Express device control, 16bits */ 190190194Smarius#define BGE_PCIE_DEVCTL 0x08 191190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 192190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 193190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 194190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 195190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 196190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 197190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 198190194Smarius 199135772Sps/* PCI MSI. ??? */ 200166676Sjkim#define BGE_PCIE_CAPID_REG 0xD0 201166676Sjkim#define BGE_PCIE_CAPID 0x10 202135772Sps 20384059Swpaul/* 20484059Swpaul * PCI registers specific to the BCM570x family. 20584059Swpaul */ 206166676Sjkim#define BGE_PCI_MISC_CTL 0x68 207166676Sjkim#define BGE_PCI_DMA_RW_CTL 0x6C 208166676Sjkim#define BGE_PCI_PCISTATE 0x70 209166676Sjkim#define BGE_PCI_CLKCTL 0x74 210166676Sjkim#define BGE_PCI_REG_BASEADDR 0x78 211166676Sjkim#define BGE_PCI_MEMWIN_BASEADDR 0x7C 212166676Sjkim#define BGE_PCI_REG_DATA 0x80 213166676Sjkim#define BGE_PCI_MEMWIN_DATA 0x84 214166676Sjkim#define BGE_PCI_MODECTL 0x88 215166676Sjkim#define BGE_PCI_MISC_CFG 0x8C 216166676Sjkim#define BGE_PCI_MISC_LOCALCTL 0x90 217166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 218166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 219166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 220166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 221166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 222166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 223166676Sjkim#define BGE_PCI_ISR_MBX_HI 0xB0 224166676Sjkim#define BGE_PCI_ISR_MBX_LO 0xB4 225197832Sstas#define BGE_PCI_PRODID_ASICREV 0xBC 226214428Syongari#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 227221445Syongari#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 22884059Swpaul 22984059Swpaul/* PCI Misc. Host control register */ 230166676Sjkim#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 231166676Sjkim#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 232166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 233166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 234166676Sjkim#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 235166676Sjkim#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 236166676Sjkim#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 237166676Sjkim#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 238214428Syongari#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 239166676Sjkim#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 240197832Sstas#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 24184059Swpaul 242166676Sjkim#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 243153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 244166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 245153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME| \ 246153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 247153437Syongari#else 248166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 249153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 250153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 251153437Syongari#endif 25284059Swpaul 253166676Sjkim#define BGE_INIT \ 254153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 255153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 25684059Swpaul 257197832Sstas#define BGE_CHIPID_TIGON_I 0x4000 258197832Sstas#define BGE_CHIPID_TIGON_II 0x6000 259197832Sstas#define BGE_CHIPID_BCM5700_A0 0x7000 260197832Sstas#define BGE_CHIPID_BCM5700_A1 0x7001 261197832Sstas#define BGE_CHIPID_BCM5700_B0 0x7100 262197832Sstas#define BGE_CHIPID_BCM5700_B1 0x7101 263197832Sstas#define BGE_CHIPID_BCM5700_B2 0x7102 264197832Sstas#define BGE_CHIPID_BCM5700_B3 0x7103 265197832Sstas#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 266197832Sstas#define BGE_CHIPID_BCM5700_C0 0x7200 267197832Sstas#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 268197832Sstas#define BGE_CHIPID_BCM5701_B0 0x0100 269197832Sstas#define BGE_CHIPID_BCM5701_B2 0x0102 270197832Sstas#define BGE_CHIPID_BCM5701_B5 0x0105 271197832Sstas#define BGE_CHIPID_BCM5703_A0 0x1000 272197832Sstas#define BGE_CHIPID_BCM5703_A1 0x1001 273197832Sstas#define BGE_CHIPID_BCM5703_A2 0x1002 274197832Sstas#define BGE_CHIPID_BCM5703_A3 0x1003 275197832Sstas#define BGE_CHIPID_BCM5703_B0 0x1100 276197832Sstas#define BGE_CHIPID_BCM5704_A0 0x2000 277197832Sstas#define BGE_CHIPID_BCM5704_A1 0x2001 278197832Sstas#define BGE_CHIPID_BCM5704_A2 0x2002 279197832Sstas#define BGE_CHIPID_BCM5704_A3 0x2003 280197832Sstas#define BGE_CHIPID_BCM5704_B0 0x2100 281197832Sstas#define BGE_CHIPID_BCM5705_A0 0x3000 282197832Sstas#define BGE_CHIPID_BCM5705_A1 0x3001 283197832Sstas#define BGE_CHIPID_BCM5705_A2 0x3002 284197832Sstas#define BGE_CHIPID_BCM5705_A3 0x3003 285197832Sstas#define BGE_CHIPID_BCM5750_A0 0x4000 286197832Sstas#define BGE_CHIPID_BCM5750_A1 0x4001 287197832Sstas#define BGE_CHIPID_BCM5750_A3 0x4000 288197832Sstas#define BGE_CHIPID_BCM5750_B0 0x4100 289197832Sstas#define BGE_CHIPID_BCM5750_B1 0x4101 290197832Sstas#define BGE_CHIPID_BCM5750_C0 0x4200 291197832Sstas#define BGE_CHIPID_BCM5750_C1 0x4201 292197832Sstas#define BGE_CHIPID_BCM5750_C2 0x4202 293197832Sstas#define BGE_CHIPID_BCM5714_A0 0x5000 294197832Sstas#define BGE_CHIPID_BCM5752_A0 0x6000 295197832Sstas#define BGE_CHIPID_BCM5752_A1 0x6001 296197832Sstas#define BGE_CHIPID_BCM5752_A2 0x6002 297197832Sstas#define BGE_CHIPID_BCM5714_B0 0x8000 298197832Sstas#define BGE_CHIPID_BCM5714_B3 0x8003 299197832Sstas#define BGE_CHIPID_BCM5715_A0 0x9000 300197832Sstas#define BGE_CHIPID_BCM5715_A1 0x9001 301197832Sstas#define BGE_CHIPID_BCM5715_A3 0x9003 302197832Sstas#define BGE_CHIPID_BCM5755_A0 0xa000 303197832Sstas#define BGE_CHIPID_BCM5755_A1 0xa001 304197832Sstas#define BGE_CHIPID_BCM5755_A2 0xa002 305197832Sstas#define BGE_CHIPID_BCM5722_A0 0xa200 306197832Sstas#define BGE_CHIPID_BCM5754_A0 0xb000 307197832Sstas#define BGE_CHIPID_BCM5754_A1 0xb001 308197832Sstas#define BGE_CHIPID_BCM5754_A2 0xb002 309197832Sstas#define BGE_CHIPID_BCM5761_A0 0x5761000 310197832Sstas#define BGE_CHIPID_BCM5761_A1 0x5761100 311197832Sstas#define BGE_CHIPID_BCM5784_A0 0x5784000 312197832Sstas#define BGE_CHIPID_BCM5784_A1 0x5784100 313197832Sstas#define BGE_CHIPID_BCM5787_A0 0xb000 314197832Sstas#define BGE_CHIPID_BCM5787_A1 0xb001 315197832Sstas#define BGE_CHIPID_BCM5787_A2 0xb002 316214251Syongari#define BGE_CHIPID_BCM5906_A0 0xc000 317197832Sstas#define BGE_CHIPID_BCM5906_A1 0xc001 318197832Sstas#define BGE_CHIPID_BCM5906_A2 0xc002 319197832Sstas#define BGE_CHIPID_BCM57780_A0 0x57780000 320197832Sstas#define BGE_CHIPID_BCM57780_A1 0x57780001 321214428Syongari#define BGE_CHIPID_BCM5717_A0 0x05717000 322214428Syongari#define BGE_CHIPID_BCM5717_B0 0x05717100 323221818Syongari#define BGE_CHIPID_BCM5719_A0 0x05719000 324221445Syongari#define BGE_CHIPID_BCM57765_A0 0x57785000 325221445Syongari#define BGE_CHIPID_BCM57765_B0 0x57785100 32684059Swpaul 32793751Swpaul/* shorthand one */ 328197832Sstas#define BGE_ASICREV(x) ((x) >> 12) 329166676Sjkim#define BGE_ASICREV_BCM5701 0x00 330166676Sjkim#define BGE_ASICREV_BCM5703 0x01 331166676Sjkim#define BGE_ASICREV_BCM5704 0x02 332166676Sjkim#define BGE_ASICREV_BCM5705 0x03 333166676Sjkim#define BGE_ASICREV_BCM5750 0x04 334166676Sjkim#define BGE_ASICREV_BCM5714_A0 0x05 335166676Sjkim#define BGE_ASICREV_BCM5752 0x06 336166676Sjkim#define BGE_ASICREV_BCM5700 0x07 337166676Sjkim#define BGE_ASICREV_BCM5780 0x08 338166676Sjkim#define BGE_ASICREV_BCM5714 0x09 339166676Sjkim#define BGE_ASICREV_BCM5755 0x0a 340166676Sjkim#define BGE_ASICREV_BCM5754 0x0b 341166676Sjkim#define BGE_ASICREV_BCM5787 0x0b 342178667Sjhb#define BGE_ASICREV_BCM5906 0x0c 343197832Sstas/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 344197832Sstas#define BGE_ASICREV_USE_PRODID_REG 0x0f 345197832Sstas/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 346214428Syongari#define BGE_ASICREV_BCM5717 0x5717 347221818Syongari#define BGE_ASICREV_BCM5719 0x5719 348197832Sstas#define BGE_ASICREV_BCM5761 0x5761 349197832Sstas#define BGE_ASICREV_BCM5784 0x5784 350197832Sstas#define BGE_ASICREV_BCM5785 0x5785 351221445Syongari#define BGE_ASICREV_BCM57765 0x57785 352197832Sstas#define BGE_ASICREV_BCM57780 0x57780 35393751Swpaul 354114813Sps/* chip revisions */ 355197832Sstas#define BGE_CHIPREV(x) ((x) >> 8) 356166676Sjkim#define BGE_CHIPREV_5700_AX 0x70 357166676Sjkim#define BGE_CHIPREV_5700_BX 0x71 358166676Sjkim#define BGE_CHIPREV_5700_CX 0x72 359166676Sjkim#define BGE_CHIPREV_5701_AX 0x00 360166676Sjkim#define BGE_CHIPREV_5703_AX 0x10 361166676Sjkim#define BGE_CHIPREV_5704_AX 0x20 362166676Sjkim#define BGE_CHIPREV_5704_BX 0x21 363166676Sjkim#define BGE_CHIPREV_5750_AX 0x40 364166676Sjkim#define BGE_CHIPREV_5750_BX 0x41 365197832Sstas/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 366214428Syongari#define BGE_CHIPREV_5717_AX 0x57170 367214428Syongari#define BGE_CHIPREV_5717_BX 0x57171 368197832Sstas#define BGE_CHIPREV_5761_AX 0x57611 369197832Sstas#define BGE_CHIPREV_5784_AX 0x57841 370114813Sps 37184059Swpaul/* PCI DMA Read/Write Control register */ 372166676Sjkim#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 373214428Syongari#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 374166676Sjkim#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 375166676Sjkim#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 376169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 377169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 378169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 379166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 380166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 381166676Sjkim#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 382166676Sjkim#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 383166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 384166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 38584059Swpaul 386166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 387166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 388166676Sjkim#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 389166676Sjkim#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 39084059Swpaul 391221818Syongari#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 392221445Syongari#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 393221445Syongari 394166676Sjkim#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 395166676Sjkim#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 396166676Sjkim#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 397166676Sjkim#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 398166676Sjkim#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 399166676Sjkim#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 400166676Sjkim#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 401166676Sjkim#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 40284059Swpaul 403166676Sjkim#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 404166676Sjkim#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 405166676Sjkim#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 406166676Sjkim#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 407166676Sjkim#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 408166676Sjkim#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 409166676Sjkim#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 410166676Sjkim#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 411166676Sjkim 41284059Swpaul/* 41384059Swpaul * PCI state register -- note, this register is read only 41484059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 41584059Swpaul * register is set. 41684059Swpaul */ 417166676Sjkim#define BGE_PCISTATE_FORCE_RESET 0x00000001 418166676Sjkim#define BGE_PCISTATE_INTR_STATE 0x00000002 419166676Sjkim#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 420166676Sjkim#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 421166676Sjkim#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 422166676Sjkim#define BGE_PCISTATE_WANT_EXPROM 0x00000020 423166676Sjkim#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 424166676Sjkim#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 425166676Sjkim#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 42684059Swpaul 42784059Swpaul/* 42884059Swpaul * PCI Clock Control register -- note, this register is read only 42984059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 43084059Swpaul * register is set. 43184059Swpaul */ 432166676Sjkim#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 433166676Sjkim#define BGE_PCICLOCKCTL_M66EN 0x00000080 434166676Sjkim#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 435166676Sjkim#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 436166676Sjkim#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 437166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 438166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 439166676Sjkim#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 440166676Sjkim#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 441166676Sjkim#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 44284059Swpaul 44384059Swpaul 44484059Swpaul#ifndef PCIM_CMD_MWIEN 445166676Sjkim#define PCIM_CMD_MWIEN 0x0010 44684059Swpaul#endif 447190319Smarius#ifndef PCIM_CMD_INTxDIS 448190319Smarius#define PCIM_CMD_INTxDIS 0x0400 449190319Smarius#endif 45084059Swpaul 45184059Swpaul/* 45284059Swpaul * High priority mailbox registers 45384059Swpaul * Each mailbox is 64-bits wide, though we only use the 45484059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 45584059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 45684059Swpaul * has been updated. 45784059Swpaul */ 458166676Sjkim#define BGE_MBX_IRQ0_HI 0x0200 459166676Sjkim#define BGE_MBX_IRQ0_LO 0x0204 460166676Sjkim#define BGE_MBX_IRQ1_HI 0x0208 461166676Sjkim#define BGE_MBX_IRQ1_LO 0x020C 462166676Sjkim#define BGE_MBX_IRQ2_HI 0x0210 463166676Sjkim#define BGE_MBX_IRQ2_LO 0x0214 464166676Sjkim#define BGE_MBX_IRQ3_HI 0x0218 465166676Sjkim#define BGE_MBX_IRQ3_LO 0x021C 466166676Sjkim#define BGE_MBX_GEN0_HI 0x0220 467166676Sjkim#define BGE_MBX_GEN0_LO 0x0224 468166676Sjkim#define BGE_MBX_GEN1_HI 0x0228 469166676Sjkim#define BGE_MBX_GEN1_LO 0x022C 470166676Sjkim#define BGE_MBX_GEN2_HI 0x0230 471166676Sjkim#define BGE_MBX_GEN2_LO 0x0234 472166676Sjkim#define BGE_MBX_GEN3_HI 0x0228 473166676Sjkim#define BGE_MBX_GEN3_LO 0x022C 474166676Sjkim#define BGE_MBX_GEN4_HI 0x0240 475166676Sjkim#define BGE_MBX_GEN4_LO 0x0244 476166676Sjkim#define BGE_MBX_GEN5_HI 0x0248 477166676Sjkim#define BGE_MBX_GEN5_LO 0x024C 478166676Sjkim#define BGE_MBX_GEN6_HI 0x0250 479166676Sjkim#define BGE_MBX_GEN6_LO 0x0254 480166676Sjkim#define BGE_MBX_GEN7_HI 0x0258 481166676Sjkim#define BGE_MBX_GEN7_LO 0x025C 482166676Sjkim#define BGE_MBX_RELOAD_STATS_HI 0x0260 483166676Sjkim#define BGE_MBX_RELOAD_STATS_LO 0x0264 484166676Sjkim#define BGE_MBX_RX_STD_PROD_HI 0x0268 485166676Sjkim#define BGE_MBX_RX_STD_PROD_LO 0x026C 486166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 487166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 488166676Sjkim#define BGE_MBX_RX_MINI_PROD_HI 0x0278 489166676Sjkim#define BGE_MBX_RX_MINI_PROD_LO 0x027C 490166676Sjkim#define BGE_MBX_RX_CONS0_HI 0x0280 491166676Sjkim#define BGE_MBX_RX_CONS0_LO 0x0284 492166676Sjkim#define BGE_MBX_RX_CONS1_HI 0x0288 493166676Sjkim#define BGE_MBX_RX_CONS1_LO 0x028C 494166676Sjkim#define BGE_MBX_RX_CONS2_HI 0x0290 495166676Sjkim#define BGE_MBX_RX_CONS2_LO 0x0294 496166676Sjkim#define BGE_MBX_RX_CONS3_HI 0x0298 497166676Sjkim#define BGE_MBX_RX_CONS3_LO 0x029C 498166676Sjkim#define BGE_MBX_RX_CONS4_HI 0x02A0 499166676Sjkim#define BGE_MBX_RX_CONS4_LO 0x02A4 500166676Sjkim#define BGE_MBX_RX_CONS5_HI 0x02A8 501166676Sjkim#define BGE_MBX_RX_CONS5_LO 0x02AC 502166676Sjkim#define BGE_MBX_RX_CONS6_HI 0x02B0 503166676Sjkim#define BGE_MBX_RX_CONS6_LO 0x02B4 504166676Sjkim#define BGE_MBX_RX_CONS7_HI 0x02B8 505166676Sjkim#define BGE_MBX_RX_CONS7_LO 0x02BC 506166676Sjkim#define BGE_MBX_RX_CONS8_HI 0x02C0 507166676Sjkim#define BGE_MBX_RX_CONS8_LO 0x02C4 508166676Sjkim#define BGE_MBX_RX_CONS9_HI 0x02C8 509166676Sjkim#define BGE_MBX_RX_CONS9_LO 0x02CC 510166676Sjkim#define BGE_MBX_RX_CONS10_HI 0x02D0 511166676Sjkim#define BGE_MBX_RX_CONS10_LO 0x02D4 512166676Sjkim#define BGE_MBX_RX_CONS11_HI 0x02D8 513166676Sjkim#define BGE_MBX_RX_CONS11_LO 0x02DC 514166676Sjkim#define BGE_MBX_RX_CONS12_HI 0x02E0 515166676Sjkim#define BGE_MBX_RX_CONS12_LO 0x02E4 516166676Sjkim#define BGE_MBX_RX_CONS13_HI 0x02E8 517166676Sjkim#define BGE_MBX_RX_CONS13_LO 0x02EC 518166676Sjkim#define BGE_MBX_RX_CONS14_HI 0x02F0 519166676Sjkim#define BGE_MBX_RX_CONS14_LO 0x02F4 520166676Sjkim#define BGE_MBX_RX_CONS15_HI 0x02F8 521166676Sjkim#define BGE_MBX_RX_CONS15_LO 0x02FC 522166676Sjkim#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 523166676Sjkim#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 524166676Sjkim#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 525166676Sjkim#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 526166676Sjkim#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 527166676Sjkim#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 528166676Sjkim#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 529166676Sjkim#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 530166676Sjkim#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 531166676Sjkim#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 532166676Sjkim#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 533166676Sjkim#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 534166676Sjkim#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 535166676Sjkim#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 536166676Sjkim#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 537166676Sjkim#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 538166676Sjkim#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 539166676Sjkim#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 540166676Sjkim#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 541166676Sjkim#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 542166676Sjkim#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 543166676Sjkim#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 544166676Sjkim#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 545166676Sjkim#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 546166676Sjkim#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 547166676Sjkim#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 548166676Sjkim#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 549166676Sjkim#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 550166676Sjkim#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 551166676Sjkim#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 552166676Sjkim#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 553166676Sjkim#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 554166676Sjkim#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 555166676Sjkim#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 556166676Sjkim#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 557166676Sjkim#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 558166676Sjkim#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 559166676Sjkim#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 560166676Sjkim#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 561166676Sjkim#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 562166676Sjkim#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 563166676Sjkim#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 564166676Sjkim#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 565166676Sjkim#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 566166676Sjkim#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 567166676Sjkim#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 568166676Sjkim#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 569166676Sjkim#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 570166676Sjkim#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 571166676Sjkim#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 572166676Sjkim#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 573166676Sjkim#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 574166676Sjkim#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 575166676Sjkim#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 576166676Sjkim#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 577166676Sjkim#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 578166676Sjkim#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 579166676Sjkim#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 580166676Sjkim#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 581166676Sjkim#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 582166676Sjkim#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 583166676Sjkim#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 584166676Sjkim#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 585166676Sjkim#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 58684059Swpaul 587166676Sjkim#define BGE_TX_RINGS_MAX 4 588166676Sjkim#define BGE_TX_RINGS_EXTSSRAM_MAX 16 589166676Sjkim#define BGE_RX_RINGS_MAX 16 590214428Syongari#define BGE_RX_RINGS_MAX_5717 17 59184059Swpaul 59284059Swpaul/* Ethernet MAC control registers */ 593166676Sjkim#define BGE_MAC_MODE 0x0400 594166676Sjkim#define BGE_MAC_STS 0x0404 595166676Sjkim#define BGE_MAC_EVT_ENB 0x0408 596166676Sjkim#define BGE_MAC_LED_CTL 0x040C 597166676Sjkim#define BGE_MAC_ADDR1_LO 0x0410 598166676Sjkim#define BGE_MAC_ADDR1_HI 0x0414 599166676Sjkim#define BGE_MAC_ADDR2_LO 0x0418 600166676Sjkim#define BGE_MAC_ADDR2_HI 0x041C 601166676Sjkim#define BGE_MAC_ADDR3_LO 0x0420 602166676Sjkim#define BGE_MAC_ADDR3_HI 0x0424 603166676Sjkim#define BGE_MAC_ADDR4_LO 0x0428 604166676Sjkim#define BGE_MAC_ADDR4_HI 0x042C 605166676Sjkim#define BGE_WOL_PATPTR 0x0430 606166676Sjkim#define BGE_WOL_PATCFG 0x0434 607166676Sjkim#define BGE_TX_RANDOM_BACKOFF 0x0438 608166676Sjkim#define BGE_RX_MTU 0x043C 609166676Sjkim#define BGE_GBIT_PCS_TEST 0x0440 610166676Sjkim#define BGE_TX_TBI_AUTONEG 0x0444 611166676Sjkim#define BGE_RX_TBI_AUTONEG 0x0448 612166676Sjkim#define BGE_MI_COMM 0x044C 613166676Sjkim#define BGE_MI_STS 0x0450 614166676Sjkim#define BGE_MI_MODE 0x0454 615166676Sjkim#define BGE_AUTOPOLL_STS 0x0458 616166676Sjkim#define BGE_TX_MODE 0x045C 617166676Sjkim#define BGE_TX_STS 0x0460 618166676Sjkim#define BGE_TX_LENGTHS 0x0464 619166676Sjkim#define BGE_RX_MODE 0x0468 620166676Sjkim#define BGE_RX_STS 0x046C 621166676Sjkim#define BGE_MAR0 0x0470 622166676Sjkim#define BGE_MAR1 0x0474 623166676Sjkim#define BGE_MAR2 0x0478 624166676Sjkim#define BGE_MAR3 0x047C 625166676Sjkim#define BGE_RX_BD_RULES_CTL0 0x0480 626166676Sjkim#define BGE_RX_BD_RULES_MASKVAL0 0x0484 627166676Sjkim#define BGE_RX_BD_RULES_CTL1 0x0488 628166676Sjkim#define BGE_RX_BD_RULES_MASKVAL1 0x048C 629166676Sjkim#define BGE_RX_BD_RULES_CTL2 0x0490 630166676Sjkim#define BGE_RX_BD_RULES_MASKVAL2 0x0494 631166676Sjkim#define BGE_RX_BD_RULES_CTL3 0x0498 632166676Sjkim#define BGE_RX_BD_RULES_MASKVAL3 0x049C 633166676Sjkim#define BGE_RX_BD_RULES_CTL4 0x04A0 634166676Sjkim#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 635166676Sjkim#define BGE_RX_BD_RULES_CTL5 0x04A8 636166676Sjkim#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 637166676Sjkim#define BGE_RX_BD_RULES_CTL6 0x04B0 638166676Sjkim#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 639166676Sjkim#define BGE_RX_BD_RULES_CTL7 0x04B8 640166676Sjkim#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 641166676Sjkim#define BGE_RX_BD_RULES_CTL8 0x04C0 642166676Sjkim#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 643166676Sjkim#define BGE_RX_BD_RULES_CTL9 0x04C8 644166676Sjkim#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 645166676Sjkim#define BGE_RX_BD_RULES_CTL10 0x04D0 646166676Sjkim#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 647166676Sjkim#define BGE_RX_BD_RULES_CTL11 0x04D8 648166676Sjkim#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 649166676Sjkim#define BGE_RX_BD_RULES_CTL12 0x04E0 650166676Sjkim#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 651166676Sjkim#define BGE_RX_BD_RULES_CTL13 0x04E8 652166676Sjkim#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 653166676Sjkim#define BGE_RX_BD_RULES_CTL14 0x04F0 654166676Sjkim#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 655166676Sjkim#define BGE_RX_BD_RULES_CTL15 0x04F8 656166676Sjkim#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 657166676Sjkim#define BGE_RX_RULES_CFG 0x0500 658213255Syongari#define BGE_MAX_RX_FRAME_LOWAT 0x0504 659166676Sjkim#define BGE_SERDES_CFG 0x0590 660166676Sjkim#define BGE_SERDES_STS 0x0594 661166676Sjkim#define BGE_SGDIG_CFG 0x05B0 662166676Sjkim#define BGE_SGDIG_STS 0x05B4 663213283Syongari#define BGE_TX_MAC_STATS_OCTETS 0x0800 664213283Syongari#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 665213283Syongari#define BGE_TX_MAC_STATS_COLLS 0x0808 666213283Syongari#define BGE_TX_MAC_STATS_XON_SENT 0x080C 667213283Syongari#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 668213283Syongari#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 669213283Syongari#define BGE_TX_MAC_STATS_ERRORS 0x0818 670213283Syongari#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 671213283Syongari#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 672213283Syongari#define BGE_TX_MAC_STATS_DEFERRED 0x0824 673213283Syongari#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 674213283Syongari#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 675213283Syongari#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 676213283Syongari#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 677213283Syongari#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 678213283Syongari#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 679213283Syongari#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 680213283Syongari#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 681213283Syongari#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 682213283Syongari#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 683213283Syongari#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 684213283Syongari#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 685213283Syongari#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 686213283Syongari#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 687213283Syongari#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 688213283Syongari#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 689213283Syongari#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 690213283Syongari#define BGE_TX_MAC_STATS_UCAST 0x086C 691213283Syongari#define BGE_TX_MAC_STATS_MCAST 0x0870 692213283Syongari#define BGE_TX_MAC_STATS_BCAST 0x0874 693213283Syongari#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 694213283Syongari#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 695213283Syongari#define BGE_RX_MAC_STATS_OCTESTS 0x0880 696213283Syongari#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 697213283Syongari#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 698213283Syongari#define BGE_RX_MAC_STATS_UCAST 0x088C 699213283Syongari#define BGE_RX_MAC_STATS_MCAST 0x0890 700213283Syongari#define BGE_RX_MAC_STATS_BCAST 0x0894 701213283Syongari#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 702213283Syongari#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 703213283Syongari#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 704213283Syongari#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 705213283Syongari#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 706213283Syongari#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 707213283Syongari#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 708213283Syongari#define BGE_RX_MAC_STATS_JABBERS 0x08B4 709213283Syongari#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 71084059Swpaul 71184059Swpaul/* Ethernet MAC Mode register */ 712166676Sjkim#define BGE_MACMODE_RESET 0x00000001 713166676Sjkim#define BGE_MACMODE_HALF_DUPLEX 0x00000002 714166676Sjkim#define BGE_MACMODE_PORTMODE 0x0000000C 715166676Sjkim#define BGE_MACMODE_LOOPBACK 0x00000010 716166676Sjkim#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 717166676Sjkim#define BGE_MACMODE_TX_BURST_ENB 0x00000100 718166676Sjkim#define BGE_MACMODE_MAX_DEFER 0x00000200 719166676Sjkim#define BGE_MACMODE_LINK_POLARITY 0x00000400 720166676Sjkim#define BGE_MACMODE_RX_STATS_ENB 0x00000800 721166676Sjkim#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 722166676Sjkim#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 723166676Sjkim#define BGE_MACMODE_TX_STATS_ENB 0x00004000 724166676Sjkim#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 725166676Sjkim#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 726166676Sjkim#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 727166676Sjkim#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 728166676Sjkim#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 729166676Sjkim#define BGE_MACMODE_MIP_ENB 0x00100000 730166676Sjkim#define BGE_MACMODE_TXDMA_ENB 0x00200000 731166676Sjkim#define BGE_MACMODE_RXDMA_ENB 0x00400000 732166676Sjkim#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 73384059Swpaul 734166676Sjkim#define BGE_PORTMODE_NONE 0x00000000 735166676Sjkim#define BGE_PORTMODE_MII 0x00000004 736166676Sjkim#define BGE_PORTMODE_GMII 0x00000008 737166676Sjkim#define BGE_PORTMODE_TBI 0x0000000C 73884059Swpaul 73984059Swpaul/* MAC Status register */ 740166676Sjkim#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 741166676Sjkim#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 742166676Sjkim#define BGE_MACSTAT_RX_CFG 0x00000004 743166676Sjkim#define BGE_MACSTAT_CFG_CHANGED 0x00000008 744166676Sjkim#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 745166676Sjkim#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 746166676Sjkim#define BGE_MACSTAT_LINK_CHANGED 0x00001000 747166676Sjkim#define BGE_MACSTAT_MI_COMPLETE 0x00400000 748166676Sjkim#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 749166676Sjkim#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 750166676Sjkim#define BGE_MACSTAT_ODI_ERROR 0x02000000 751166676Sjkim#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 752166676Sjkim#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 75384059Swpaul 75484059Swpaul/* MAC Event Enable Register */ 755166676Sjkim#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 756166676Sjkim#define BGE_EVTENB_LINK_CHANGED 0x00001000 757166676Sjkim#define BGE_EVTENB_MI_COMPLETE 0x00400000 758166676Sjkim#define BGE_EVTENB_MI_INTERRUPT 0x00800000 759166676Sjkim#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 760166676Sjkim#define BGE_EVTENB_ODI_ERROR 0x02000000 761166676Sjkim#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 762166676Sjkim#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 76384059Swpaul 76484059Swpaul/* LED Control Register */ 765166676Sjkim#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 766166676Sjkim#define BGE_LEDCTL_1000MBPS_LED 0x00000002 767166676Sjkim#define BGE_LEDCTL_100MBPS_LED 0x00000004 768166676Sjkim#define BGE_LEDCTL_10MBPS_LED 0x00000008 769166676Sjkim#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 770166676Sjkim#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 771166676Sjkim#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 772166676Sjkim#define BGE_LEDCTL_1000MBPS_STS 0x00000080 773166676Sjkim#define BGE_LEDCTL_100MBPS_STS 0x00000100 774166676Sjkim#define BGE_LEDCTL_10MBPS_STS 0x00000200 775166676Sjkim#define BGE_LEDCTL_TRADLED_STS 0x00000400 776166676Sjkim#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 777166676Sjkim#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 77884059Swpaul 77984059Swpaul/* TX backoff seed register */ 780166676Sjkim#define BGE_TX_BACKOFF_SEED_MASK 0x3F 78184059Swpaul 78284059Swpaul/* Autopoll status register */ 783166676Sjkim#define BGE_AUTOPOLLSTS_ERROR 0x00000001 78484059Swpaul 78584059Swpaul/* Transmit MAC mode register */ 786166676Sjkim#define BGE_TXMODE_RESET 0x00000001 787166676Sjkim#define BGE_TXMODE_ENABLE 0x00000002 788166676Sjkim#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 789166676Sjkim#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 790166676Sjkim#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 791214216Syongari#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 79284059Swpaul 79384059Swpaul/* Transmit MAC status register */ 794166676Sjkim#define BGE_TXSTAT_RX_XOFFED 0x00000001 795166676Sjkim#define BGE_TXSTAT_SENT_XOFF 0x00000002 796166676Sjkim#define BGE_TXSTAT_SENT_XON 0x00000004 797166676Sjkim#define BGE_TXSTAT_LINK_UP 0x00000008 798166676Sjkim#define BGE_TXSTAT_ODI_UFLOW 0x00000010 799166676Sjkim#define BGE_TXSTAT_ODI_OFLOW 0x00000020 80084059Swpaul 80184059Swpaul/* Transmit MAC lengths register */ 802166676Sjkim#define BGE_TXLEN_SLOTTIME 0x000000FF 803166676Sjkim#define BGE_TXLEN_IPG 0x00000F00 804166676Sjkim#define BGE_TXLEN_CRS 0x00003000 80584059Swpaul 80684059Swpaul/* Receive MAC mode register */ 807166676Sjkim#define BGE_RXMODE_RESET 0x00000001 808166676Sjkim#define BGE_RXMODE_ENABLE 0x00000002 809166676Sjkim#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 810166676Sjkim#define BGE_RXMODE_RX_GIANTS 0x00000020 811166676Sjkim#define BGE_RXMODE_RX_RUNTS 0x00000040 812166676Sjkim#define BGE_RXMODE_8022_LENCHECK 0x00000080 813166676Sjkim#define BGE_RXMODE_RX_PROMISC 0x00000100 814166676Sjkim#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 815166676Sjkim#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 81684059Swpaul 81784059Swpaul/* Receive MAC status register */ 818166676Sjkim#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 819166676Sjkim#define BGE_RXSTAT_RCVD_XOFF 0x00000002 820166676Sjkim#define BGE_RXSTAT_RCVD_XON 0x00000004 82184059Swpaul 82284059Swpaul/* Receive Rules Control register */ 823166676Sjkim#define BGE_RXRULECTL_OFFSET 0x000000FF 824166676Sjkim#define BGE_RXRULECTL_CLASS 0x00001F00 825166676Sjkim#define BGE_RXRULECTL_HDRTYPE 0x0000E000 826166676Sjkim#define BGE_RXRULECTL_COMPARE_OP 0x00030000 827166676Sjkim#define BGE_RXRULECTL_MAP 0x01000000 828166676Sjkim#define BGE_RXRULECTL_DISCARD 0x02000000 829166676Sjkim#define BGE_RXRULECTL_MASK 0x04000000 830166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 831166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 832166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 833166676Sjkim#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 83484059Swpaul 83584059Swpaul/* Receive Rules Mask register */ 836166676Sjkim#define BGE_RXRULEMASK_VALUE 0x0000FFFF 837166676Sjkim#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 83884059Swpaul 839130273Swpaul/* SERDES configuration register */ 840166676Sjkim#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 841166676Sjkim#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 842166676Sjkim#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 843166676Sjkim#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 844166676Sjkim#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 845166676Sjkim#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 846166676Sjkim#define BGE_SERDESCFG_TXMODE 0x00001000 847166676Sjkim#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 848166676Sjkim#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 849166676Sjkim#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 850166676Sjkim#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 851166676Sjkim#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 852166676Sjkim#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 853166676Sjkim#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 854166676Sjkim#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 855166676Sjkim#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 856130273Swpaul 857130273Swpaul/* SERDES status register */ 858166676Sjkim#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 859166676Sjkim#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 860130273Swpaul 861130273Swpaul/* SGDIG config (not documented) */ 862166676Sjkim#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 863166676Sjkim#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 864166676Sjkim#define BGE_SGDIGCFG_SEND 0x40000000 865166676Sjkim#define BGE_SGDIGCFG_AUTO 0x80000000 866130273Swpaul 867130273Swpaul/* SGDIG status (not documented) */ 868214428Syongari#define BGE_SGDIGSTS_DONE 0x00000002 869214428Syongari#define BGE_SGDIGSTS_IS_SERDES 0x00000100 870166676Sjkim#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 871166676Sjkim#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 872130273Swpaul 873130273Swpaul 87484059Swpaul/* MI communication register */ 875166676Sjkim#define BGE_MICOMM_DATA 0x0000FFFF 876166676Sjkim#define BGE_MICOMM_REG 0x001F0000 877166676Sjkim#define BGE_MICOMM_PHY 0x03E00000 878166676Sjkim#define BGE_MICOMM_CMD 0x0C000000 879166676Sjkim#define BGE_MICOMM_READFAIL 0x10000000 880166676Sjkim#define BGE_MICOMM_BUSY 0x20000000 88184059Swpaul 882166676Sjkim#define BGE_MIREG(x) ((x & 0x1F) << 16) 883166676Sjkim#define BGE_MIPHY(x) ((x & 0x1F) << 21) 884166676Sjkim#define BGE_MICMD_WRITE 0x04000000 885166676Sjkim#define BGE_MICMD_READ 0x08000000 88684059Swpaul 88784059Swpaul/* MI status register */ 888166676Sjkim#define BGE_MISTS_LINK 0x00000001 889166676Sjkim#define BGE_MISTS_10MBPS 0x00000002 89084059Swpaul 891213485Syongari#define BGE_MIMODE_CLK_10MHZ 0x00000001 892166676Sjkim#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 893166676Sjkim#define BGE_MIMODE_AUTOPOLL 0x00000010 894166676Sjkim#define BGE_MIMODE_CLKCNT 0x001F0000 895213485Syongari#define BGE_MIMODE_500KHZ_CONST 0x00008000 896213485Syongari#define BGE_MIMODE_BASE 0x000C0000 89784059Swpaul 89884059Swpaul 89984059Swpaul/* 90084059Swpaul * Send data initiator control registers. 90184059Swpaul */ 902166676Sjkim#define BGE_SDI_MODE 0x0C00 903166676Sjkim#define BGE_SDI_STATUS 0x0C04 904166676Sjkim#define BGE_SDI_STATS_CTL 0x0C08 905166676Sjkim#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 906166676Sjkim#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 907214219Syongari#define BGE_ISO_PKT_TX 0x0C20 908166676Sjkim#define BGE_LOCSTATS_COS0 0x0C80 909166676Sjkim#define BGE_LOCSTATS_COS1 0x0C84 910166676Sjkim#define BGE_LOCSTATS_COS2 0x0C88 911166676Sjkim#define BGE_LOCSTATS_COS3 0x0C8C 912166676Sjkim#define BGE_LOCSTATS_COS4 0x0C90 913166676Sjkim#define BGE_LOCSTATS_COS5 0x0C84 914166676Sjkim#define BGE_LOCSTATS_COS6 0x0C98 915166676Sjkim#define BGE_LOCSTATS_COS7 0x0C9C 916166676Sjkim#define BGE_LOCSTATS_COS8 0x0CA0 917166676Sjkim#define BGE_LOCSTATS_COS9 0x0CA4 918166676Sjkim#define BGE_LOCSTATS_COS10 0x0CA8 919166676Sjkim#define BGE_LOCSTATS_COS11 0x0CAC 920166676Sjkim#define BGE_LOCSTATS_COS12 0x0CB0 921166676Sjkim#define BGE_LOCSTATS_COS13 0x0CB4 922166676Sjkim#define BGE_LOCSTATS_COS14 0x0CB8 923166676Sjkim#define BGE_LOCSTATS_COS15 0x0CBC 924166676Sjkim#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 925166676Sjkim#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 926166676Sjkim#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 927166676Sjkim#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 928166676Sjkim#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 929166676Sjkim#define BGE_LOCSTATS_IRQS 0x0CD4 930166676Sjkim#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 931166676Sjkim#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 93284059Swpaul 93384059Swpaul/* Send Data Initiator mode register */ 934166676Sjkim#define BGE_SDIMODE_RESET 0x00000001 935166676Sjkim#define BGE_SDIMODE_ENABLE 0x00000002 936166676Sjkim#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 937214428Syongari#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 93884059Swpaul 93984059Swpaul/* Send Data Initiator stats register */ 940166676Sjkim#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 94184059Swpaul 94284059Swpaul/* Send Data Initiator stats control register */ 943166676Sjkim#define BGE_SDISTATSCTL_ENABLE 0x00000001 944166676Sjkim#define BGE_SDISTATSCTL_FASTER 0x00000002 945166676Sjkim#define BGE_SDISTATSCTL_CLEAR 0x00000004 946166676Sjkim#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 947166676Sjkim#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 94884059Swpaul 94984059Swpaul/* 95084059Swpaul * Send Data Completion Control registers 95184059Swpaul */ 952166676Sjkim#define BGE_SDC_MODE 0x1000 953166676Sjkim#define BGE_SDC_STATUS 0x1004 95484059Swpaul 95584059Swpaul/* Send Data completion mode register */ 956166676Sjkim#define BGE_SDCMODE_RESET 0x00000001 957166676Sjkim#define BGE_SDCMODE_ENABLE 0x00000002 958166676Sjkim#define BGE_SDCMODE_ATTN 0x00000004 959197832Sstas#define BGE_SDCMODE_CDELAY 0x00000010 96084059Swpaul 96184059Swpaul/* Send Data completion status register */ 962166676Sjkim#define BGE_SDCSTAT_ATTN 0x00000004 96384059Swpaul 96484059Swpaul/* 96584059Swpaul * Send BD Ring Selector Control registers 96684059Swpaul */ 967166676Sjkim#define BGE_SRS_MODE 0x1400 968166676Sjkim#define BGE_SRS_STATUS 0x1404 969166676Sjkim#define BGE_SRS_HWDIAG 0x1408 970166676Sjkim#define BGE_SRS_LOC_NIC_CONS0 0x1440 971166676Sjkim#define BGE_SRS_LOC_NIC_CONS1 0x1444 972166676Sjkim#define BGE_SRS_LOC_NIC_CONS2 0x1448 973166676Sjkim#define BGE_SRS_LOC_NIC_CONS3 0x144C 974166676Sjkim#define BGE_SRS_LOC_NIC_CONS4 0x1450 975166676Sjkim#define BGE_SRS_LOC_NIC_CONS5 0x1454 976166676Sjkim#define BGE_SRS_LOC_NIC_CONS6 0x1458 977166676Sjkim#define BGE_SRS_LOC_NIC_CONS7 0x145C 978166676Sjkim#define BGE_SRS_LOC_NIC_CONS8 0x1460 979166676Sjkim#define BGE_SRS_LOC_NIC_CONS9 0x1464 980166676Sjkim#define BGE_SRS_LOC_NIC_CONS10 0x1468 981166676Sjkim#define BGE_SRS_LOC_NIC_CONS11 0x146C 982166676Sjkim#define BGE_SRS_LOC_NIC_CONS12 0x1470 983166676Sjkim#define BGE_SRS_LOC_NIC_CONS13 0x1474 984166676Sjkim#define BGE_SRS_LOC_NIC_CONS14 0x1478 985166676Sjkim#define BGE_SRS_LOC_NIC_CONS15 0x147C 98684059Swpaul 98784059Swpaul/* Send BD Ring Selector Mode register */ 988166676Sjkim#define BGE_SRSMODE_RESET 0x00000001 989166676Sjkim#define BGE_SRSMODE_ENABLE 0x00000002 990166676Sjkim#define BGE_SRSMODE_ATTN 0x00000004 99184059Swpaul 99284059Swpaul/* Send BD Ring Selector Status register */ 993166676Sjkim#define BGE_SRSSTAT_ERROR 0x00000004 99484059Swpaul 99584059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 996166676Sjkim#define BGE_SRSHWDIAG_STATE 0x0000000F 997166676Sjkim#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 998166676Sjkim#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 999166676Sjkim#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 100084059Swpaul 100184059Swpaul/* 100284059Swpaul * Send BD Initiator Selector Control registers 100384059Swpaul */ 1004166676Sjkim#define BGE_SBDI_MODE 0x1800 1005166676Sjkim#define BGE_SBDI_STATUS 0x1804 1006166676Sjkim#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1007166676Sjkim#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1008166676Sjkim#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1009166676Sjkim#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1010166676Sjkim#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1011166676Sjkim#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1012166676Sjkim#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1013166676Sjkim#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1014166676Sjkim#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1015166676Sjkim#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1016166676Sjkim#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1017166676Sjkim#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1018166676Sjkim#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1019166676Sjkim#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1020166676Sjkim#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1021166676Sjkim#define BGE_SBDI_LOC_NIC_PROD15 0x1844 102284059Swpaul 102384059Swpaul/* Send BD Initiator Mode register */ 1024166676Sjkim#define BGE_SBDIMODE_RESET 0x00000001 1025166676Sjkim#define BGE_SBDIMODE_ENABLE 0x00000002 1026166676Sjkim#define BGE_SBDIMODE_ATTN 0x00000004 102784059Swpaul 102884059Swpaul/* Send BD Initiator Status register */ 1029166676Sjkim#define BGE_SBDISTAT_ERROR 0x00000004 103084059Swpaul 103184059Swpaul/* 103284059Swpaul * Send BD Completion Control registers 103384059Swpaul */ 1034166676Sjkim#define BGE_SBDC_MODE 0x1C00 1035166676Sjkim#define BGE_SBDC_STATUS 0x1C04 103684059Swpaul 103784059Swpaul/* Send BD Completion Control Mode register */ 1038166676Sjkim#define BGE_SBDCMODE_RESET 0x00000001 1039166676Sjkim#define BGE_SBDCMODE_ENABLE 0x00000002 1040166676Sjkim#define BGE_SBDCMODE_ATTN 0x00000004 104184059Swpaul 104284059Swpaul/* Send BD Completion Control Status register */ 1043166676Sjkim#define BGE_SBDCSTAT_ATTN 0x00000004 104484059Swpaul 104584059Swpaul/* 104684059Swpaul * Receive List Placement Control registers 104784059Swpaul */ 1048166676Sjkim#define BGE_RXLP_MODE 0x2000 1049166676Sjkim#define BGE_RXLP_STATUS 0x2004 1050166676Sjkim#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1051166676Sjkim#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1052166676Sjkim#define BGE_RXLP_CFG 0x2010 1053166676Sjkim#define BGE_RXLP_STATS_CTL 0x2014 1054166676Sjkim#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1055166676Sjkim#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1056166676Sjkim#define BGE_RXLP_HEAD0 0x2100 1057166676Sjkim#define BGE_RXLP_TAIL0 0x2104 1058166676Sjkim#define BGE_RXLP_COUNT0 0x2108 1059166676Sjkim#define BGE_RXLP_HEAD1 0x2110 1060166676Sjkim#define BGE_RXLP_TAIL1 0x2114 1061166676Sjkim#define BGE_RXLP_COUNT1 0x2118 1062166676Sjkim#define BGE_RXLP_HEAD2 0x2120 1063166676Sjkim#define BGE_RXLP_TAIL2 0x2124 1064166676Sjkim#define BGE_RXLP_COUNT2 0x2128 1065166676Sjkim#define BGE_RXLP_HEAD3 0x2130 1066166676Sjkim#define BGE_RXLP_TAIL3 0x2134 1067166676Sjkim#define BGE_RXLP_COUNT3 0x2138 1068166676Sjkim#define BGE_RXLP_HEAD4 0x2140 1069166676Sjkim#define BGE_RXLP_TAIL4 0x2144 1070166676Sjkim#define BGE_RXLP_COUNT4 0x2148 1071166676Sjkim#define BGE_RXLP_HEAD5 0x2150 1072166676Sjkim#define BGE_RXLP_TAIL5 0x2154 1073166676Sjkim#define BGE_RXLP_COUNT5 0x2158 1074166676Sjkim#define BGE_RXLP_HEAD6 0x2160 1075166676Sjkim#define BGE_RXLP_TAIL6 0x2164 1076166676Sjkim#define BGE_RXLP_COUNT6 0x2168 1077166676Sjkim#define BGE_RXLP_HEAD7 0x2170 1078166676Sjkim#define BGE_RXLP_TAIL7 0x2174 1079166676Sjkim#define BGE_RXLP_COUNT7 0x2178 1080166676Sjkim#define BGE_RXLP_HEAD8 0x2180 1081166676Sjkim#define BGE_RXLP_TAIL8 0x2184 1082166676Sjkim#define BGE_RXLP_COUNT8 0x2188 1083166676Sjkim#define BGE_RXLP_HEAD9 0x2190 1084166676Sjkim#define BGE_RXLP_TAIL9 0x2194 1085166676Sjkim#define BGE_RXLP_COUNT9 0x2198 1086166676Sjkim#define BGE_RXLP_HEAD10 0x21A0 1087166676Sjkim#define BGE_RXLP_TAIL10 0x21A4 1088166676Sjkim#define BGE_RXLP_COUNT10 0x21A8 1089166676Sjkim#define BGE_RXLP_HEAD11 0x21B0 1090166676Sjkim#define BGE_RXLP_TAIL11 0x21B4 1091166676Sjkim#define BGE_RXLP_COUNT11 0x21B8 1092166676Sjkim#define BGE_RXLP_HEAD12 0x21C0 1093166676Sjkim#define BGE_RXLP_TAIL12 0x21C4 1094166676Sjkim#define BGE_RXLP_COUNT12 0x21C8 1095166676Sjkim#define BGE_RXLP_HEAD13 0x21D0 1096166676Sjkim#define BGE_RXLP_TAIL13 0x21D4 1097166676Sjkim#define BGE_RXLP_COUNT13 0x21D8 1098166676Sjkim#define BGE_RXLP_HEAD14 0x21E0 1099166676Sjkim#define BGE_RXLP_TAIL14 0x21E4 1100166676Sjkim#define BGE_RXLP_COUNT14 0x21E8 1101166676Sjkim#define BGE_RXLP_HEAD15 0x21F0 1102166676Sjkim#define BGE_RXLP_TAIL15 0x21F4 1103166676Sjkim#define BGE_RXLP_COUNT15 0x21F8 1104166676Sjkim#define BGE_RXLP_LOCSTAT_COS0 0x2200 1105166676Sjkim#define BGE_RXLP_LOCSTAT_COS1 0x2204 1106166676Sjkim#define BGE_RXLP_LOCSTAT_COS2 0x2208 1107166676Sjkim#define BGE_RXLP_LOCSTAT_COS3 0x220C 1108166676Sjkim#define BGE_RXLP_LOCSTAT_COS4 0x2210 1109166676Sjkim#define BGE_RXLP_LOCSTAT_COS5 0x2214 1110166676Sjkim#define BGE_RXLP_LOCSTAT_COS6 0x2218 1111166676Sjkim#define BGE_RXLP_LOCSTAT_COS7 0x221C 1112166676Sjkim#define BGE_RXLP_LOCSTAT_COS8 0x2220 1113166676Sjkim#define BGE_RXLP_LOCSTAT_COS9 0x2224 1114166676Sjkim#define BGE_RXLP_LOCSTAT_COS10 0x2228 1115166676Sjkim#define BGE_RXLP_LOCSTAT_COS11 0x222C 1116166676Sjkim#define BGE_RXLP_LOCSTAT_COS12 0x2230 1117166676Sjkim#define BGE_RXLP_LOCSTAT_COS13 0x2234 1118166676Sjkim#define BGE_RXLP_LOCSTAT_COS14 0x2238 1119166676Sjkim#define BGE_RXLP_LOCSTAT_COS15 0x223C 1120166676Sjkim#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1121166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1122166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1123166676Sjkim#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1124166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1125166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1126166676Sjkim#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 112784059Swpaul 112884059Swpaul 112984059Swpaul/* Receive List Placement mode register */ 1130166676Sjkim#define BGE_RXLPMODE_RESET 0x00000001 1131166676Sjkim#define BGE_RXLPMODE_ENABLE 0x00000002 1132166676Sjkim#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1133166676Sjkim#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1134166676Sjkim#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 113584059Swpaul 113684059Swpaul/* Receive List Placement Status register */ 1137166676Sjkim#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1138166676Sjkim#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1139166676Sjkim#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 114084059Swpaul 114184059Swpaul/* 114284059Swpaul * Receive Data and Receive BD Initiator Control Registers 114384059Swpaul */ 1144166676Sjkim#define BGE_RDBDI_MODE 0x2400 1145166676Sjkim#define BGE_RDBDI_STATUS 0x2404 1146166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1147166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1148166676Sjkim#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1149166676Sjkim#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1150166676Sjkim#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1151166676Sjkim#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1152166676Sjkim#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1153166676Sjkim#define BGE_RX_STD_RCB_NICADDR 0x245C 1154166676Sjkim#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1155166676Sjkim#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1156166676Sjkim#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1157166676Sjkim#define BGE_RX_MINI_RCB_NICADDR 0x246C 1158166676Sjkim#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1159166676Sjkim#define BGE_RDBDI_STD_RX_CONS 0x2474 1160166676Sjkim#define BGE_RDBDI_MINI_RX_CONS 0x2478 1161166676Sjkim#define BGE_RDBDI_RETURN_PROD0 0x2480 1162166676Sjkim#define BGE_RDBDI_RETURN_PROD1 0x2484 1163166676Sjkim#define BGE_RDBDI_RETURN_PROD2 0x2488 1164166676Sjkim#define BGE_RDBDI_RETURN_PROD3 0x248C 1165166676Sjkim#define BGE_RDBDI_RETURN_PROD4 0x2490 1166166676Sjkim#define BGE_RDBDI_RETURN_PROD5 0x2494 1167166676Sjkim#define BGE_RDBDI_RETURN_PROD6 0x2498 1168166676Sjkim#define BGE_RDBDI_RETURN_PROD7 0x249C 1169166676Sjkim#define BGE_RDBDI_RETURN_PROD8 0x24A0 1170166676Sjkim#define BGE_RDBDI_RETURN_PROD9 0x24A4 1171166676Sjkim#define BGE_RDBDI_RETURN_PROD10 0x24A8 1172166676Sjkim#define BGE_RDBDI_RETURN_PROD11 0x24AC 1173166676Sjkim#define BGE_RDBDI_RETURN_PROD12 0x24B0 1174166676Sjkim#define BGE_RDBDI_RETURN_PROD13 0x24B4 1175166676Sjkim#define BGE_RDBDI_RETURN_PROD14 0x24B8 1176166676Sjkim#define BGE_RDBDI_RETURN_PROD15 0x24BC 1177166676Sjkim#define BGE_RDBDI_HWDIAG 0x24C0 117884059Swpaul 117984059Swpaul 118084059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 1181166676Sjkim#define BGE_RDBDIMODE_RESET 0x00000001 1182166676Sjkim#define BGE_RDBDIMODE_ENABLE 0x00000002 1183166676Sjkim#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1184166676Sjkim#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1185166676Sjkim#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 118684059Swpaul 118784059Swpaul/* Receive Data and Receive BD Initiator Status register */ 1188166676Sjkim#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1189166676Sjkim#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1190166676Sjkim#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 119184059Swpaul 119284059Swpaul 119384059Swpaul/* 119484059Swpaul * Receive Data Completion Control registers 119584059Swpaul */ 1196166676Sjkim#define BGE_RDC_MODE 0x2800 119784059Swpaul 119884059Swpaul/* Receive Data Completion Mode register */ 1199166676Sjkim#define BGE_RDCMODE_RESET 0x00000001 1200166676Sjkim#define BGE_RDCMODE_ENABLE 0x00000002 1201166676Sjkim#define BGE_RDCMODE_ATTN 0x00000004 120284059Swpaul 120384059Swpaul/* 120484059Swpaul * Receive BD Initiator Control registers 120584059Swpaul */ 1206166676Sjkim#define BGE_RBDI_MODE 0x2C00 1207166676Sjkim#define BGE_RBDI_STATUS 0x2C04 1208166676Sjkim#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1209166676Sjkim#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1210166676Sjkim#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1211166676Sjkim#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1212166676Sjkim#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1213166676Sjkim#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 121484059Swpaul 1215214428Syongari#define BGE_STD_REPLENISH_LWM 0x2D00 1216214428Syongari#define BGE_JMB_REPLENISH_LWM 0x2D04 1217214428Syongari 121884059Swpaul/* Receive BD Initiator Mode register */ 1219166676Sjkim#define BGE_RBDIMODE_RESET 0x00000001 1220166676Sjkim#define BGE_RBDIMODE_ENABLE 0x00000002 1221166676Sjkim#define BGE_RBDIMODE_ATTN 0x00000004 122284059Swpaul 122384059Swpaul/* Receive BD Initiator Status register */ 1224166676Sjkim#define BGE_RBDISTAT_ATTN 0x00000004 122584059Swpaul 122684059Swpaul/* 122784059Swpaul * Receive BD Completion Control registers 122884059Swpaul */ 1229166676Sjkim#define BGE_RBDC_MODE 0x3000 1230166676Sjkim#define BGE_RBDC_STATUS 0x3004 1231166676Sjkim#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1232166676Sjkim#define BGE_RBDC_STD_BD_PROD 0x300C 1233166676Sjkim#define BGE_RBDC_MINI_BD_PROD 0x3010 123484059Swpaul 123584059Swpaul/* Receive BD completion mode register */ 1236166676Sjkim#define BGE_RBDCMODE_RESET 0x00000001 1237166676Sjkim#define BGE_RBDCMODE_ENABLE 0x00000002 1238166676Sjkim#define BGE_RBDCMODE_ATTN 0x00000004 123984059Swpaul 124084059Swpaul/* Receive BD completion status register */ 1241166676Sjkim#define BGE_RBDCSTAT_ERROR 0x00000004 124284059Swpaul 124384059Swpaul/* 124484059Swpaul * Receive List Selector Control registers 124584059Swpaul */ 1246166676Sjkim#define BGE_RXLS_MODE 0x3400 1247166676Sjkim#define BGE_RXLS_STATUS 0x3404 124884059Swpaul 124984059Swpaul/* Receive List Selector Mode register */ 1250166676Sjkim#define BGE_RXLSMODE_RESET 0x00000001 1251166676Sjkim#define BGE_RXLSMODE_ENABLE 0x00000002 1252166676Sjkim#define BGE_RXLSMODE_ATTN 0x00000004 125384059Swpaul 125484059Swpaul/* Receive List Selector Status register */ 1255166676Sjkim#define BGE_RXLSSTAT_ERROR 0x00000004 125684059Swpaul 1257213485Syongari#define BGE_CPMU_CTRL 0x3600 1258213485Syongari#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1259213485Syongari#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1260213485Syongari#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1261213485Syongari#define BGE_CPMU_HST_ACC 0x361C 1262213485Syongari#define BGE_CPMU_CLCK_STAT 0x3630 1263213485Syongari#define BGE_CPMU_MUTEX_REQ 0x365C 1264213485Syongari#define BGE_CPMU_MUTEX_GNT 0x3660 1265213485Syongari#define BGE_CPMU_PHY_STRAP 0x3664 1266213485Syongari 1267213485Syongari/* Central Power Management Unit (CPMU) register */ 1268213485Syongari#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1269213485Syongari#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1270213485Syongari#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1271213485Syongari#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1272213485Syongari 1273213485Syongari/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1274213485Syongari#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1275213485Syongari#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1276213485Syongari 1277213485Syongari/* Link Speed 1000MB Power Mode Clock Policy register */ 1278213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1279213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1280213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1281213485Syongari 1282213485Syongari/* Link Aware Power Mode Clock Policy register */ 1283213485Syongari#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1284213485Syongari#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1285213485Syongari 1286213485Syongari#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1287213485Syongari#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1288213485Syongari 1289213485Syongari/* CPMU Clock Status register */ 1290213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1291213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1292213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1293213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1294213485Syongari 1295213485Syongari/* CPMU Mutex Request register */ 1296213485Syongari#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1297213485Syongari#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1298213485Syongari 1299213485Syongari/* CPMU GPHY Strap register */ 1300213485Syongari#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1301213485Syongari 130284059Swpaul/* 130384059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 130484059Swpaul */ 1305166676Sjkim#define BGE_MBCF_MODE 0x3800 1306166676Sjkim#define BGE_MBCF_STATUS 0x3804 130784059Swpaul 130884059Swpaul/* Mbuf Cluster Free mode register */ 1309166676Sjkim#define BGE_MBCFMODE_RESET 0x00000001 1310166676Sjkim#define BGE_MBCFMODE_ENABLE 0x00000002 1311166676Sjkim#define BGE_MBCFMODE_ATTN 0x00000004 131284059Swpaul 131384059Swpaul/* Mbuf Cluster Free status register */ 1314166676Sjkim#define BGE_MBCFSTAT_ERROR 0x00000004 131584059Swpaul 131684059Swpaul/* 131784059Swpaul * Host Coalescing Control registers 131884059Swpaul */ 1319166676Sjkim#define BGE_HCC_MODE 0x3C00 1320166676Sjkim#define BGE_HCC_STATUS 0x3C04 1321166676Sjkim#define BGE_HCC_RX_COAL_TICKS 0x3C08 1322166676Sjkim#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1323166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1324166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1325166676Sjkim#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1326166676Sjkim#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1327166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1328166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1329166676Sjkim#define BGE_HCC_STATS_TICKS 0x3C28 1330166676Sjkim#define BGE_HCC_STATS_ADDR_HI 0x3C30 1331166676Sjkim#define BGE_HCC_STATS_ADDR_LO 0x3C34 1332166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1333166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1334166676Sjkim#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1335166676Sjkim#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1336166676Sjkim#define BGE_FLOW_ATTN 0x3C48 1337166676Sjkim#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1338166676Sjkim#define BGE_HCC_STD_BD_CONS 0x3C54 1339166676Sjkim#define BGE_HCC_MINI_BD_CONS 0x3C58 1340166676Sjkim#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1341166676Sjkim#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1342166676Sjkim#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1343166676Sjkim#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1344166676Sjkim#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1345166676Sjkim#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1346166676Sjkim#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1347166676Sjkim#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1348166676Sjkim#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1349166676Sjkim#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1350166676Sjkim#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1351166676Sjkim#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1352166676Sjkim#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1353166676Sjkim#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1354166676Sjkim#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1355166676Sjkim#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1356166676Sjkim#define BGE_HCC_TX_BD_CONS0 0x3CC0 1357166676Sjkim#define BGE_HCC_TX_BD_CONS1 0x3CC4 1358166676Sjkim#define BGE_HCC_TX_BD_CONS2 0x3CC8 1359166676Sjkim#define BGE_HCC_TX_BD_CONS3 0x3CCC 1360166676Sjkim#define BGE_HCC_TX_BD_CONS4 0x3CD0 1361166676Sjkim#define BGE_HCC_TX_BD_CONS5 0x3CD4 1362166676Sjkim#define BGE_HCC_TX_BD_CONS6 0x3CD8 1363166676Sjkim#define BGE_HCC_TX_BD_CONS7 0x3CDC 1364166676Sjkim#define BGE_HCC_TX_BD_CONS8 0x3CE0 1365166676Sjkim#define BGE_HCC_TX_BD_CONS9 0x3CE4 1366166676Sjkim#define BGE_HCC_TX_BD_CONS10 0x3CE8 1367166676Sjkim#define BGE_HCC_TX_BD_CONS11 0x3CEC 1368166676Sjkim#define BGE_HCC_TX_BD_CONS12 0x3CF0 1369166676Sjkim#define BGE_HCC_TX_BD_CONS13 0x3CF4 1370166676Sjkim#define BGE_HCC_TX_BD_CONS14 0x3CF8 1371166676Sjkim#define BGE_HCC_TX_BD_CONS15 0x3CFC 137284059Swpaul 137384059Swpaul 137484059Swpaul/* Host coalescing mode register */ 1375166676Sjkim#define BGE_HCCMODE_RESET 0x00000001 1376166676Sjkim#define BGE_HCCMODE_ENABLE 0x00000002 1377166676Sjkim#define BGE_HCCMODE_ATTN 0x00000004 1378166676Sjkim#define BGE_HCCMODE_COAL_NOW 0x00000008 1379166676Sjkim#define BGE_HCCMODE_MSI_BITS 0x00000070 1380166676Sjkim#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 138184059Swpaul 1382166676Sjkim#define BGE_STATBLKSZ_FULL 0x00000000 1383166676Sjkim#define BGE_STATBLKSZ_64BYTE 0x00000080 1384166676Sjkim#define BGE_STATBLKSZ_32BYTE 0x00000100 138584059Swpaul 138684059Swpaul/* Host coalescing status register */ 1387166676Sjkim#define BGE_HCCSTAT_ERROR 0x00000004 138884059Swpaul 138984059Swpaul/* Flow attention register */ 1390166676Sjkim#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1391166676Sjkim#define BGE_FLOWATTN_MEMARB 0x00000080 1392166676Sjkim#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1393166676Sjkim#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1394166676Sjkim#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1395166676Sjkim#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1396166676Sjkim#define BGE_FLOWATTN_RDBDI 0x00080000 1397166676Sjkim#define BGE_FLOWATTN_RXLS 0x00100000 1398166676Sjkim#define BGE_FLOWATTN_RXLP 0x00200000 1399166676Sjkim#define BGE_FLOWATTN_RBDC 0x00400000 1400166676Sjkim#define BGE_FLOWATTN_RBDI 0x00800000 1401166676Sjkim#define BGE_FLOWATTN_SDC 0x08000000 1402166676Sjkim#define BGE_FLOWATTN_SDI 0x10000000 1403166676Sjkim#define BGE_FLOWATTN_SRS 0x20000000 1404166676Sjkim#define BGE_FLOWATTN_SBDC 0x40000000 1405166676Sjkim#define BGE_FLOWATTN_SBDI 0x80000000 140684059Swpaul 140784059Swpaul/* 140884059Swpaul * Memory arbiter registers 140984059Swpaul */ 1410166676Sjkim#define BGE_MARB_MODE 0x4000 1411166676Sjkim#define BGE_MARB_STATUS 0x4004 1412166676Sjkim#define BGE_MARB_TRAPADDR_HI 0x4008 1413166676Sjkim#define BGE_MARB_TRAPADDR_LO 0x400C 141484059Swpaul 141584059Swpaul/* Memory arbiter mode register */ 1416166676Sjkim#define BGE_MARBMODE_RESET 0x00000001 1417166676Sjkim#define BGE_MARBMODE_ENABLE 0x00000002 1418166676Sjkim#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1419166676Sjkim#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1420166676Sjkim#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1421166676Sjkim#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1422166676Sjkim#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1423166676Sjkim#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1424166676Sjkim#define BGE_MARBMODE_PCI_TRAP 0x00000100 1425166676Sjkim#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1426166676Sjkim#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1427166676Sjkim#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1428166676Sjkim#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1429166676Sjkim#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1430166676Sjkim#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1431166676Sjkim#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1432166676Sjkim#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1433166676Sjkim#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1434166676Sjkim#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1435166676Sjkim#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1436166676Sjkim#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1437166676Sjkim#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1438166676Sjkim#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1439166676Sjkim#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1440166676Sjkim#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1441166676Sjkim#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 144284059Swpaul 144384059Swpaul/* Memory arbiter status register */ 1444166676Sjkim#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1445166676Sjkim#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1446166676Sjkim#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1447166676Sjkim#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1448166676Sjkim#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1449166676Sjkim#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1450166676Sjkim#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1451166676Sjkim#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1452166676Sjkim#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1453166676Sjkim#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1454166676Sjkim#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1455166676Sjkim#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1456166676Sjkim#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1457166676Sjkim#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1458166676Sjkim#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1459166676Sjkim#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1460166676Sjkim#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1461166676Sjkim#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1462166676Sjkim#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1463166676Sjkim#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1464166676Sjkim#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1465166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1466166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1467166676Sjkim#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 146884059Swpaul 146984059Swpaul/* 147084059Swpaul * Buffer manager control registers 147184059Swpaul */ 1472166676Sjkim#define BGE_BMAN_MODE 0x4400 1473166676Sjkim#define BGE_BMAN_STATUS 0x4404 1474166676Sjkim#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1475166676Sjkim#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1476166676Sjkim#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1477166676Sjkim#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1478166676Sjkim#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1479166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1480166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1481166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1482166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1483166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1484166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1485166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1486166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1487166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1488166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1489166676Sjkim#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1490166676Sjkim#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1491166676Sjkim#define BGE_BMAN_HWDIAG_1 0x444C 1492166676Sjkim#define BGE_BMAN_HWDIAG_2 0x4450 1493166676Sjkim#define BGE_BMAN_HWDIAG_3 0x4454 149484059Swpaul 149584059Swpaul/* Buffer manager mode register */ 1496166676Sjkim#define BGE_BMANMODE_RESET 0x00000001 1497166676Sjkim#define BGE_BMANMODE_ENABLE 0x00000002 1498166676Sjkim#define BGE_BMANMODE_ATTN 0x00000004 1499166676Sjkim#define BGE_BMANMODE_TESTMODE 0x00000008 1500166676Sjkim#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1501221818Syongari#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 150284059Swpaul 150384059Swpaul/* Buffer manager status register */ 1504166676Sjkim#define BGE_BMANSTAT_ERRO 0x00000004 1505166676Sjkim#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 150684059Swpaul 150784059Swpaul 150884059Swpaul/* 150984059Swpaul * Read DMA Control registers 151084059Swpaul */ 1511166676Sjkim#define BGE_RDMA_MODE 0x4800 1512166676Sjkim#define BGE_RDMA_STATUS 0x4804 1513213411Syongari#define BGE_RDMA_RSRVCTRL 0x4900 1514221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 151584059Swpaul 151684059Swpaul/* Read DMA mode register */ 1517166676Sjkim#define BGE_RDMAMODE_RESET 0x00000001 1518166676Sjkim#define BGE_RDMAMODE_ENABLE 0x00000002 1519166676Sjkim#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1520166676Sjkim#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1521166676Sjkim#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1522166676Sjkim#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1523166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1524166676Sjkim#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1525166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1526166676Sjkim#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1527166676Sjkim#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1528197832Sstas#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1529197832Sstas#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1530197832Sstas#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1531190194Smarius#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1532190194Smarius#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1533214428Syongari#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1534199671Syongari#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1535199671Syongari#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 153684059Swpaul 153784059Swpaul/* Read DMA status register */ 1538166676Sjkim#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1539166676Sjkim#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1540166676Sjkim#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1541166676Sjkim#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1542166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1543166676Sjkim#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1544166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1545166676Sjkim#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 154684059Swpaul 1547213411Syongari/* Read DMA Reserved Control register */ 1548213411Syongari#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1549221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1550221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1551221818Syongari#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1552221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1553221818Syongari#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1554221818Syongari#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1555213411Syongari 1556221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1557221818Syongari#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1558221818Syongari 155984059Swpaul/* 156084059Swpaul * Write DMA control registers 156184059Swpaul */ 1562166676Sjkim#define BGE_WDMA_MODE 0x4C00 1563166676Sjkim#define BGE_WDMA_STATUS 0x4C04 156484059Swpaul 156584059Swpaul/* Write DMA mode register */ 1566166676Sjkim#define BGE_WDMAMODE_RESET 0x00000001 1567166676Sjkim#define BGE_WDMAMODE_ENABLE 0x00000002 1568166676Sjkim#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1569166676Sjkim#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1570166676Sjkim#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1571166676Sjkim#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1572166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1573166676Sjkim#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1574166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1575166676Sjkim#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1576166676Sjkim#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1577197837Sstas#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1578213333Syongari#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 157984059Swpaul 158084059Swpaul/* Write DMA status register */ 1581166676Sjkim#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1582166676Sjkim#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1583166676Sjkim#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1584166676Sjkim#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1585166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1586166676Sjkim#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1587166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1588166676Sjkim#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 158984059Swpaul 159084059Swpaul 159184059Swpaul/* 159284059Swpaul * RX CPU registers 159384059Swpaul */ 1594166676Sjkim#define BGE_RXCPU_MODE 0x5000 1595166676Sjkim#define BGE_RXCPU_STATUS 0x5004 1596166676Sjkim#define BGE_RXCPU_PC 0x501C 159784059Swpaul 159884059Swpaul/* RX CPU mode register */ 1599166676Sjkim#define BGE_RXCPUMODE_RESET 0x00000001 1600166676Sjkim#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1601166676Sjkim#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1602166676Sjkim#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1603166676Sjkim#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1604166676Sjkim#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1605166676Sjkim#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1606166676Sjkim#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1607166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1608166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1609166676Sjkim#define BGE_RXCPUMODE_HALTCPU 0x00000400 1610166676Sjkim#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1611166676Sjkim#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1612166676Sjkim#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 161384059Swpaul 161484059Swpaul/* RX CPU status register */ 1615166676Sjkim#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1616166676Sjkim#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1617166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1618166676Sjkim#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1619166676Sjkim#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1620166676Sjkim#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1621166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1622166676Sjkim#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1623166676Sjkim#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1624166676Sjkim#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1625166676Sjkim#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1626166676Sjkim#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1627166676Sjkim#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1628166676Sjkim#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1629166676Sjkim#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1630166676Sjkim#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1631166676Sjkim#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 163284059Swpaul 1633178667Sjhb/* 1634178667Sjhb * V? CPU registers 1635178667Sjhb */ 1636178667Sjhb#define BGE_VCPU_STATUS 0x5100 1637178667Sjhb#define BGE_VCPU_EXT_CTRL 0x6890 163884059Swpaul 1639178667Sjhb#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1640178667Sjhb#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1641178667Sjhb 1642178667Sjhb#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1643178667Sjhb#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1644178667Sjhb 164584059Swpaul/* 164684059Swpaul * TX CPU registers 164784059Swpaul */ 1648166676Sjkim#define BGE_TXCPU_MODE 0x5400 1649166676Sjkim#define BGE_TXCPU_STATUS 0x5404 1650166676Sjkim#define BGE_TXCPU_PC 0x541C 165184059Swpaul 165284059Swpaul/* TX CPU mode register */ 1653166676Sjkim#define BGE_TXCPUMODE_RESET 0x00000001 1654166676Sjkim#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1655166676Sjkim#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1656166676Sjkim#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1657166676Sjkim#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1658166676Sjkim#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1659166676Sjkim#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1660166676Sjkim#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1661166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1662166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1663166676Sjkim#define BGE_TXCPUMODE_HALTCPU 0x00000400 1664166676Sjkim#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1665166676Sjkim#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 166684059Swpaul 166784059Swpaul/* TX CPU status register */ 1668166676Sjkim#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1669166676Sjkim#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1670166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1671166676Sjkim#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1672166676Sjkim#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1673166676Sjkim#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1674166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1675166676Sjkim#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1676166676Sjkim#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1677166676Sjkim#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1678166676Sjkim#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1679166676Sjkim#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1680166676Sjkim#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1681166676Sjkim#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1682166676Sjkim#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1683166676Sjkim#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1684166676Sjkim#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 168584059Swpaul 168684059Swpaul 168784059Swpaul/* 168884059Swpaul * Low priority mailbox registers 168984059Swpaul */ 1690166676Sjkim#define BGE_LPMBX_IRQ0_HI 0x5800 1691166676Sjkim#define BGE_LPMBX_IRQ0_LO 0x5804 1692166676Sjkim#define BGE_LPMBX_IRQ1_HI 0x5808 1693166676Sjkim#define BGE_LPMBX_IRQ1_LO 0x580C 1694166676Sjkim#define BGE_LPMBX_IRQ2_HI 0x5810 1695166676Sjkim#define BGE_LPMBX_IRQ2_LO 0x5814 1696166676Sjkim#define BGE_LPMBX_IRQ3_HI 0x5818 1697166676Sjkim#define BGE_LPMBX_IRQ3_LO 0x581C 1698166676Sjkim#define BGE_LPMBX_GEN0_HI 0x5820 1699166676Sjkim#define BGE_LPMBX_GEN0_LO 0x5824 1700166676Sjkim#define BGE_LPMBX_GEN1_HI 0x5828 1701166676Sjkim#define BGE_LPMBX_GEN1_LO 0x582C 1702166676Sjkim#define BGE_LPMBX_GEN2_HI 0x5830 1703166676Sjkim#define BGE_LPMBX_GEN2_LO 0x5834 1704166676Sjkim#define BGE_LPMBX_GEN3_HI 0x5828 1705166676Sjkim#define BGE_LPMBX_GEN3_LO 0x582C 1706166676Sjkim#define BGE_LPMBX_GEN4_HI 0x5840 1707166676Sjkim#define BGE_LPMBX_GEN4_LO 0x5844 1708166676Sjkim#define BGE_LPMBX_GEN5_HI 0x5848 1709166676Sjkim#define BGE_LPMBX_GEN5_LO 0x584C 1710166676Sjkim#define BGE_LPMBX_GEN6_HI 0x5850 1711166676Sjkim#define BGE_LPMBX_GEN6_LO 0x5854 1712166676Sjkim#define BGE_LPMBX_GEN7_HI 0x5858 1713166676Sjkim#define BGE_LPMBX_GEN7_LO 0x585C 1714166676Sjkim#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1715166676Sjkim#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1716166676Sjkim#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1717166676Sjkim#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1718166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1719166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1720166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1721166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1722166676Sjkim#define BGE_LPMBX_RX_CONS0_HI 0x5880 1723166676Sjkim#define BGE_LPMBX_RX_CONS0_LO 0x5884 1724166676Sjkim#define BGE_LPMBX_RX_CONS1_HI 0x5888 1725166676Sjkim#define BGE_LPMBX_RX_CONS1_LO 0x588C 1726166676Sjkim#define BGE_LPMBX_RX_CONS2_HI 0x5890 1727166676Sjkim#define BGE_LPMBX_RX_CONS2_LO 0x5894 1728166676Sjkim#define BGE_LPMBX_RX_CONS3_HI 0x5898 1729166676Sjkim#define BGE_LPMBX_RX_CONS3_LO 0x589C 1730166676Sjkim#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1731166676Sjkim#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1732166676Sjkim#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1733166676Sjkim#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1734166676Sjkim#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1735166676Sjkim#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1736166676Sjkim#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1737166676Sjkim#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1738166676Sjkim#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1739166676Sjkim#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1740166676Sjkim#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1741166676Sjkim#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1742166676Sjkim#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1743166676Sjkim#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1744166676Sjkim#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1745166676Sjkim#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1746166676Sjkim#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1747166676Sjkim#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1748166676Sjkim#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1749166676Sjkim#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1750166676Sjkim#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1751166676Sjkim#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1752166676Sjkim#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1753166676Sjkim#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1754166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1755166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1756166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1757166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1758166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1759166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1760166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1761166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1762166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1763166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1764166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1765166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1766166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1767166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1768166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1769166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1770166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1771166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1772166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1773166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1774166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1775166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1776166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1777166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1778166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1779166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1780166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1781166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1782166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1783166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1784166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1785166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1786166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1787166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1788166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1789166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1790166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1791166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1792166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1793166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1794166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1795166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1796166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1797166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1798166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1799166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1800166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1801166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1802166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1803166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1804166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1805166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1806166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1807166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1808166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1809166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1810166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1811166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1812166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1813166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1814166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1815166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1816166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1817166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 181884059Swpaul 181984059Swpaul/* 182084059Swpaul * Flow throw Queue reset register 182184059Swpaul */ 1822166676Sjkim#define BGE_FTQ_RESET 0x5C00 182384059Swpaul 1824166676Sjkim#define BGE_FTQRESET_DMAREAD 0x00000002 1825166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1826166676Sjkim#define BGE_FTQRESET_DMADONE 0x00000010 1827166676Sjkim#define BGE_FTQRESET_SBDC 0x00000020 1828166676Sjkim#define BGE_FTQRESET_SDI 0x00000040 1829166676Sjkim#define BGE_FTQRESET_WDMA 0x00000080 1830166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1831166676Sjkim#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1832166676Sjkim#define BGE_FTQRESET_SDC 0x00000400 1833166676Sjkim#define BGE_FTQRESET_HCC 0x00000800 1834166676Sjkim#define BGE_FTQRESET_TXFIFO 0x00001000 1835166676Sjkim#define BGE_FTQRESET_MBC 0x00002000 1836166676Sjkim#define BGE_FTQRESET_RBDC 0x00004000 1837166676Sjkim#define BGE_FTQRESET_RXLP 0x00008000 1838166676Sjkim#define BGE_FTQRESET_RDBDI 0x00010000 1839166676Sjkim#define BGE_FTQRESET_RDC 0x00020000 1840166676Sjkim#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 184184059Swpaul 184284059Swpaul/* 184384059Swpaul * Message Signaled Interrupt registers 184484059Swpaul */ 1845166676Sjkim#define BGE_MSI_MODE 0x6000 1846166676Sjkim#define BGE_MSI_STATUS 0x6004 1847166676Sjkim#define BGE_MSI_FIFOACCESS 0x6008 184884059Swpaul 184984059Swpaul/* MSI mode register */ 1850166676Sjkim#define BGE_MSIMODE_RESET 0x00000001 1851166676Sjkim#define BGE_MSIMODE_ENABLE 0x00000002 1852198967Syongari#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1853198967Syongari#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 185484059Swpaul 185584059Swpaul/* MSI status register */ 1856166676Sjkim#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1857166676Sjkim#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1858166676Sjkim#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1859166676Sjkim#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1860166676Sjkim#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 186184059Swpaul 186284059Swpaul 186384059Swpaul/* 186484059Swpaul * DMA Completion registers 186584059Swpaul */ 1866166676Sjkim#define BGE_DMAC_MODE 0x6400 186784059Swpaul 186884059Swpaul/* DMA Completion mode register */ 1869166676Sjkim#define BGE_DMACMODE_RESET 0x00000001 1870166676Sjkim#define BGE_DMACMODE_ENABLE 0x00000002 187184059Swpaul 187284059Swpaul 187384059Swpaul/* 187484059Swpaul * General control registers. 187584059Swpaul */ 1876166676Sjkim#define BGE_MODE_CTL 0x6800 1877166676Sjkim#define BGE_MISC_CFG 0x6804 1878166676Sjkim#define BGE_MISC_LOCAL_CTL 0x6808 1879166676Sjkim#define BGE_CPU_EVENT 0x6810 1880166676Sjkim#define BGE_EE_ADDR 0x6838 1881166676Sjkim#define BGE_EE_DATA 0x683C 1882166676Sjkim#define BGE_EE_CTL 0x6840 1883166676Sjkim#define BGE_MDI_CTL 0x6844 1884166676Sjkim#define BGE_EE_DELAY 0x6848 1885166676Sjkim#define BGE_FASTBOOT_PC 0x6894 188684059Swpaul 1887178667Sjhb/* 1888178667Sjhb * NVRAM Control registers 1889178667Sjhb */ 1890178667Sjhb#define BGE_NVRAM_CMD 0x7000 1891178667Sjhb#define BGE_NVRAM_STAT 0x7004 1892178667Sjhb#define BGE_NVRAM_WRDATA 0x7008 1893178667Sjhb#define BGE_NVRAM_ADDR 0x700c 1894178667Sjhb#define BGE_NVRAM_RDDATA 0x7010 1895178667Sjhb#define BGE_NVRAM_CFG1 0x7014 1896178667Sjhb#define BGE_NVRAM_CFG2 0x7018 1897178667Sjhb#define BGE_NVRAM_CFG3 0x701c 1898178667Sjhb#define BGE_NVRAM_SWARB 0x7020 1899178667Sjhb#define BGE_NVRAM_ACCESS 0x7024 1900178667Sjhb#define BGE_NVRAM_WRITE1 0x7028 1901178667Sjhb 1902178667Sjhb#define BGE_NVRAMCMD_RESET 0x00000001 1903178667Sjhb#define BGE_NVRAMCMD_DONE 0x00000008 1904178667Sjhb#define BGE_NVRAMCMD_START 0x00000010 1905178667Sjhb#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1906178667Sjhb#define BGE_NVRAMCMD_ERASE 0x00000040 1907178667Sjhb#define BGE_NVRAMCMD_FIRST 0x00000080 1908178667Sjhb#define BGE_NVRAMCMD_LAST 0x00000100 1909178667Sjhb 1910178667Sjhb#define BGE_NVRAM_READCMD \ 1911178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1912178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1913178667Sjhb#define BGE_NVRAM_WRITECMD \ 1914178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1915178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1916178667Sjhb 1917178667Sjhb#define BGE_NVRAMSWARB_SET0 0x00000001 1918178667Sjhb#define BGE_NVRAMSWARB_SET1 0x00000002 1919178667Sjhb#define BGE_NVRAMSWARB_SET2 0x00000003 1920178667Sjhb#define BGE_NVRAMSWARB_SET3 0x00000004 1921178667Sjhb#define BGE_NVRAMSWARB_CLR0 0x00000010 1922178667Sjhb#define BGE_NVRAMSWARB_CLR1 0x00000020 1923178667Sjhb#define BGE_NVRAMSWARB_CLR2 0x00000040 1924178667Sjhb#define BGE_NVRAMSWARB_CLR3 0x00000080 1925178667Sjhb#define BGE_NVRAMSWARB_GNT0 0x00000100 1926178667Sjhb#define BGE_NVRAMSWARB_GNT1 0x00000200 1927178667Sjhb#define BGE_NVRAMSWARB_GNT2 0x00000400 1928178667Sjhb#define BGE_NVRAMSWARB_GNT3 0x00000800 1929178667Sjhb#define BGE_NVRAMSWARB_REQ0 0x00001000 1930178667Sjhb#define BGE_NVRAMSWARB_REQ1 0x00002000 1931178667Sjhb#define BGE_NVRAMSWARB_REQ2 0x00004000 1932178667Sjhb#define BGE_NVRAMSWARB_REQ3 0x00008000 1933178667Sjhb 1934178667Sjhb#define BGE_NVRAMACC_ENABLE 0x00000001 1935178667Sjhb#define BGE_NVRAMACC_WRENABLE 0x00000002 1936178667Sjhb 193784059Swpaul/* Mode control register */ 1938166676Sjkim#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1939166676Sjkim#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1940166676Sjkim#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1941166676Sjkim#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1942166676Sjkim#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1943166676Sjkim#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1944166676Sjkim#define BGE_MODECTL_NO_RX_CRC 0x00000400 1945166676Sjkim#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1946166676Sjkim#define BGE_MODECTL_NO_TX_INTR 0x00002000 1947166676Sjkim#define BGE_MODECTL_NO_RX_INTR 0x00004000 1948166676Sjkim#define BGE_MODECTL_FORCE_PCI32 0x00008000 1949166676Sjkim#define BGE_MODECTL_STACKUP 0x00010000 1950166676Sjkim#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1951166676Sjkim#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1952166676Sjkim#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1953166676Sjkim#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1954166676Sjkim#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1955166676Sjkim#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1956166676Sjkim#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1957166676Sjkim#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1958166676Sjkim#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1959166676Sjkim#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 196084059Swpaul 196184059Swpaul/* Misc. config register */ 1962166676Sjkim#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1963166676Sjkim#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1964178785Sbz#define BGE_MISCCFG_BOARD_ID 0x0001E000 1965178785Sbz#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1966178785Sbz#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1967178667Sjhb#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1968210152Syongari#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 196984059Swpaul 1970166676Sjkim#define BGE_32BITTIME_66MHZ (0x41 << 1) 197184059Swpaul 197284059Swpaul/* Misc. Local Control */ 1973166676Sjkim#define BGE_MLC_INTR_STATE 0x00000001 1974166676Sjkim#define BGE_MLC_INTR_CLR 0x00000002 1975166676Sjkim#define BGE_MLC_INTR_SET 0x00000004 1976166676Sjkim#define BGE_MLC_INTR_ONATTN 0x00000008 1977166676Sjkim#define BGE_MLC_MISCIO_IN0 0x00000100 1978166676Sjkim#define BGE_MLC_MISCIO_IN1 0x00000200 1979166676Sjkim#define BGE_MLC_MISCIO_IN2 0x00000400 1980166676Sjkim#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1981166676Sjkim#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1982166676Sjkim#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1983166676Sjkim#define BGE_MLC_MISCIO_OUT0 0x00004000 1984166676Sjkim#define BGE_MLC_MISCIO_OUT1 0x00008000 1985166676Sjkim#define BGE_MLC_MISCIO_OUT2 0x00010000 1986166676Sjkim#define BGE_MLC_EXTRAM_ENB 0x00020000 1987166676Sjkim#define BGE_MLC_SRAM_SIZE 0x001C0000 1988166676Sjkim#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1989166676Sjkim#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1990166676Sjkim#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1991166676Sjkim#define BGE_MLC_AUTO_EEPROM 0x01000000 199284059Swpaul 1993166676Sjkim#define BGE_SSRAMSIZE_256KB 0x00000000 1994166676Sjkim#define BGE_SSRAMSIZE_512KB 0x00040000 1995166676Sjkim#define BGE_SSRAMSIZE_1MB 0x00080000 1996166676Sjkim#define BGE_SSRAMSIZE_2MB 0x000C0000 1997166676Sjkim#define BGE_SSRAMSIZE_4MB 0x00100000 1998166676Sjkim#define BGE_SSRAMSIZE_8MB 0x00140000 1999166676Sjkim#define BGE_SSRAMSIZE_16M 0x00180000 200084059Swpaul 200184059Swpaul/* EEPROM address register */ 2002166676Sjkim#define BGE_EEADDR_ADDRESS 0x0000FFFC 2003166676Sjkim#define BGE_EEADDR_HALFCLK 0x01FF0000 2004166676Sjkim#define BGE_EEADDR_START 0x02000000 2005166676Sjkim#define BGE_EEADDR_DEVID 0x1C000000 2006166676Sjkim#define BGE_EEADDR_RESET 0x20000000 2007166676Sjkim#define BGE_EEADDR_DONE 0x40000000 2008166676Sjkim#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 200984059Swpaul 2010166676Sjkim#define BGE_EEDEVID(x) ((x & 7) << 26) 2011166676Sjkim#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2012166676Sjkim#define BGE_HALFCLK_384SCL 0x60 2013166676Sjkim#define BGE_EE_READCMD \ 201484059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 201584059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2016166676Sjkim#define BGE_EE_WRCMD \ 201784059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 201884059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 201984059Swpaul 202084059Swpaul/* EEPROM Control register */ 2021166676Sjkim#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2022166676Sjkim#define BGE_EECTL_CLKOUT 0x00000002 2023166676Sjkim#define BGE_EECTL_CLKIN 0x00000004 2024166676Sjkim#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2025166676Sjkim#define BGE_EECTL_DATAOUT 0x00000010 2026166676Sjkim#define BGE_EECTL_DATAIN 0x00000020 202784059Swpaul 202884059Swpaul/* MDI (MII/GMII) access register */ 2029166676Sjkim#define BGE_MDI_DATA 0x00000001 2030166676Sjkim#define BGE_MDI_DIR 0x00000002 2031166676Sjkim#define BGE_MDI_SEL 0x00000004 2032166676Sjkim#define BGE_MDI_CLK 0x00000008 203384059Swpaul 2034166676Sjkim#define BGE_MEMWIN_START 0x00008000 2035166676Sjkim#define BGE_MEMWIN_END 0x0000FFFF 203684059Swpaul 203784059Swpaul 2038166676Sjkim#define BGE_MEMWIN_READ(sc, x, val) \ 203984059Swpaul do { \ 204084059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 204184059Swpaul (0xFFFF0000 & x), 4); \ 204284059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 204384059Swpaul } while(0) 204484059Swpaul 2045166676Sjkim#define BGE_MEMWIN_WRITE(sc, x, val) \ 204684059Swpaul do { \ 204784059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 204884059Swpaul (0xFFFF0000 & x), 4); \ 204984059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 205084059Swpaul } while(0) 205184059Swpaul 205284059Swpaul/* 2053161847Sdavidch * This magic number is written to the firmware mailbox at 0xb50 2054161847Sdavidch * before a software reset is issued. After the internal firmware 2055199661Syongari * has completed its initialization it will write the opposite of 2056226814Syongari * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2057226814Syongari * allowing the driver to synchronize with the firmware. 205884059Swpaul */ 2059226814Syongari#define BGE_SRAM_FW_MB_MAGIC 0x4B657654 206084059Swpaul 206184059Swpaultypedef struct { 2062159395Sglebius uint32_t bge_addr_hi; 2063159395Sglebius uint32_t bge_addr_lo; 206484059Swpaul} bge_hostaddr; 2065118026Swpaul 2066166676Sjkim#define BGE_HOSTADDR(x, y) \ 2067115200Sps do { \ 2068159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2069159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2070115200Sps } while(0) 207184059Swpaul 2072166676Sjkim#define BGE_ADDR_LO(y) \ 2073159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 2074166676Sjkim#define BGE_ADDR_HI(y) \ 2075159395Sglebius ((uint64_t) (y) >> 32) 2076118026Swpaul 207784059Swpaul/* Ring control block structure */ 207884059Swpaulstruct bge_rcb { 207984059Swpaul bge_hostaddr bge_hostaddr; 2080159395Sglebius uint32_t bge_maxlen_flags; 2081159395Sglebius uint32_t bge_nicaddr; 208284059Swpaul}; 2083153437Syongari 2084153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 2085183896Smarius bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2086166676Sjkim#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 208784059Swpaul 2088166676Sjkim#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2089166676Sjkim#define BGE_RCB_FLAG_RING_DISABLED 0x0002 209084059Swpaul 209184059Swpaulstruct bge_tx_bd { 209284059Swpaul bge_hostaddr bge_addr; 2093153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2094159395Sglebius uint16_t bge_flags; 2095159395Sglebius uint16_t bge_len; 2096159395Sglebius uint16_t bge_vlan_tag; 2097199671Syongari uint16_t bge_mss; 2098153437Syongari#else 2099159395Sglebius uint16_t bge_len; 2100159395Sglebius uint16_t bge_flags; 2101199671Syongari uint16_t bge_mss; 2102159395Sglebius uint16_t bge_vlan_tag; 2103153437Syongari#endif 210484059Swpaul}; 210584059Swpaul 2106166676Sjkim#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2107166676Sjkim#define BGE_TXBDFLAG_IP_CSUM 0x0002 2108166676Sjkim#define BGE_TXBDFLAG_END 0x0004 2109166676Sjkim#define BGE_TXBDFLAG_IP_FRAG 0x0008 2110214428Syongari#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2111166676Sjkim#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2112214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2113214428Syongari#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2114166676Sjkim#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2115166676Sjkim#define BGE_TXBDFLAG_COAL_NOW 0x0080 2116166676Sjkim#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2117166676Sjkim#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2118214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2119214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2120166676Sjkim#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2121214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2122214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2123214428Syongari#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2124166676Sjkim#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2125166676Sjkim#define BGE_TXBDFLAG_NO_CRC 0x8000 212684059Swpaul 2127214428Syongari#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2128214428Syongari/* Bits [1:0] of the MSS header length. */ 2129214428Syongari#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2130214428Syongari 2131166676Sjkim#define BGE_NIC_TXRING_ADDR(ringno, size) \ 213284059Swpaul BGE_SEND_RING_1_TO_4 + \ 213384059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 213484059Swpaul 213584059Swpaulstruct bge_rx_bd { 213684059Swpaul bge_hostaddr bge_addr; 2137153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2138159395Sglebius uint16_t bge_len; 2139159395Sglebius uint16_t bge_idx; 2140159395Sglebius uint16_t bge_flags; 2141159395Sglebius uint16_t bge_type; 2142159395Sglebius uint16_t bge_tcp_udp_csum; 2143159395Sglebius uint16_t bge_ip_csum; 2144159395Sglebius uint16_t bge_vlan_tag; 2145159395Sglebius uint16_t bge_error_flag; 2146153437Syongari#else 2147159395Sglebius uint16_t bge_idx; 2148159395Sglebius uint16_t bge_len; 2149159395Sglebius uint16_t bge_type; 2150159395Sglebius uint16_t bge_flags; 2151159395Sglebius uint16_t bge_ip_csum; 2152159395Sglebius uint16_t bge_tcp_udp_csum; 2153159395Sglebius uint16_t bge_error_flag; 2154159395Sglebius uint16_t bge_vlan_tag; 2155153437Syongari#endif 2156159395Sglebius uint32_t bge_rsvd; 2157159395Sglebius uint32_t bge_opaque; 215884059Swpaul}; 215984059Swpaul 2160153239Sglebiusstruct bge_extrx_bd { 2161153239Sglebius bge_hostaddr bge_addr1; 2162153239Sglebius bge_hostaddr bge_addr2; 2163153239Sglebius bge_hostaddr bge_addr3; 2164153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2165159395Sglebius uint16_t bge_len2; 2166159395Sglebius uint16_t bge_len1; 2167159395Sglebius uint16_t bge_rsvd1; 2168159395Sglebius uint16_t bge_len3; 2169153437Syongari#else 2170159395Sglebius uint16_t bge_len1; 2171159395Sglebius uint16_t bge_len2; 2172159395Sglebius uint16_t bge_len3; 2173159395Sglebius uint16_t bge_rsvd1; 2174153437Syongari#endif 2175153239Sglebius bge_hostaddr bge_addr0; 2176153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2177159395Sglebius uint16_t bge_len0; 2178159395Sglebius uint16_t bge_idx; 2179159395Sglebius uint16_t bge_flags; 2180159395Sglebius uint16_t bge_type; 2181159395Sglebius uint16_t bge_tcp_udp_csum; 2182159395Sglebius uint16_t bge_ip_csum; 2183159395Sglebius uint16_t bge_vlan_tag; 2184159395Sglebius uint16_t bge_error_flag; 2185153437Syongari#else 2186159395Sglebius uint16_t bge_idx; 2187159395Sglebius uint16_t bge_len0; 2188159395Sglebius uint16_t bge_type; 2189159395Sglebius uint16_t bge_flags; 2190159395Sglebius uint16_t bge_ip_csum; 2191159395Sglebius uint16_t bge_tcp_udp_csum; 2192159395Sglebius uint16_t bge_error_flag; 2193159395Sglebius uint16_t bge_vlan_tag; 2194153437Syongari#endif 2195159395Sglebius uint32_t bge_rsvd0; 2196159395Sglebius uint32_t bge_opaque; 2197153239Sglebius}; 2198153239Sglebius 2199166676Sjkim#define BGE_RXBDFLAG_END 0x0004 2200166676Sjkim#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2201166676Sjkim#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2202166676Sjkim#define BGE_RXBDFLAG_ERROR 0x0400 2203166676Sjkim#define BGE_RXBDFLAG_MINI_RING 0x0800 2204166676Sjkim#define BGE_RXBDFLAG_IP_CSUM 0x1000 2205166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2206166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2207214428Syongari#define BGE_RXBDFLAG_IPV6 0x8000 220884059Swpaul 2209166676Sjkim#define BGE_RXERRFLAG_BAD_CRC 0x0001 2210166676Sjkim#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2211166676Sjkim#define BGE_RXERRFLAG_LINK_LOST 0x0004 2212166676Sjkim#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2213166676Sjkim#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2214166676Sjkim#define BGE_RXERRFLAG_RUNT 0x0020 2215166676Sjkim#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2216166676Sjkim#define BGE_RXERRFLAG_GIANT 0x0080 2217214428Syongari#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 221884059Swpaul 221984059Swpaulstruct bge_sts_idx { 2220153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2221159395Sglebius uint16_t bge_rx_prod_idx; 2222159395Sglebius uint16_t bge_tx_cons_idx; 2223153437Syongari#else 2224159395Sglebius uint16_t bge_tx_cons_idx; 2225159395Sglebius uint16_t bge_rx_prod_idx; 2226153437Syongari#endif 222784059Swpaul}; 222884059Swpaul 222984059Swpaulstruct bge_status_block { 2230159395Sglebius uint32_t bge_status; 2231214428Syongari uint32_t bge_status_tag; 2232153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2233159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2234159395Sglebius uint16_t bge_rx_std_cons_idx; 2235159395Sglebius uint16_t bge_rx_mini_cons_idx; 2236159395Sglebius uint16_t bge_rsvd1; 2237153437Syongari#else 2238159395Sglebius uint16_t bge_rx_std_cons_idx; 2239159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2240159395Sglebius uint16_t bge_rsvd1; 2241159395Sglebius uint16_t bge_rx_mini_cons_idx; 2242153437Syongari#endif 224384059Swpaul struct bge_sts_idx bge_idx[16]; 224484059Swpaul}; 224584059Swpaul 2246166676Sjkim#define BGE_STATFLAG_UPDATED 0x00000001 2247166676Sjkim#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2248166676Sjkim#define BGE_STATFLAG_ERROR 0x00000004 224984059Swpaul 225084059Swpaul 225184059Swpaul/* 225284059Swpaul * Broadcom Vendor ID 225384059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 225484059Swpaul * even though they're now manufactured by Broadcom) 225584059Swpaul */ 2256166676Sjkim#define BCOM_VENDORID 0x14E4 2257166676Sjkim#define BCOM_DEVICEID_BCM5700 0x1644 2258166676Sjkim#define BCOM_DEVICEID_BCM5701 0x1645 2259166676Sjkim#define BCOM_DEVICEID_BCM5702 0x1646 2260166676Sjkim#define BCOM_DEVICEID_BCM5702X 0x16A6 2261166676Sjkim#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2262166676Sjkim#define BCOM_DEVICEID_BCM5703 0x1647 2263166676Sjkim#define BCOM_DEVICEID_BCM5703X 0x16A7 2264166676Sjkim#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2265166676Sjkim#define BCOM_DEVICEID_BCM5704C 0x1648 2266166676Sjkim#define BCOM_DEVICEID_BCM5704S 0x16A8 2267166676Sjkim#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2268166676Sjkim#define BCOM_DEVICEID_BCM5705 0x1653 2269166676Sjkim#define BCOM_DEVICEID_BCM5705K 0x1654 2270166676Sjkim#define BCOM_DEVICEID_BCM5705F 0x166E 2271166676Sjkim#define BCOM_DEVICEID_BCM5705M 0x165D 2272166676Sjkim#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2273166676Sjkim#define BCOM_DEVICEID_BCM5714C 0x1668 2274166676Sjkim#define BCOM_DEVICEID_BCM5714S 0x1669 2275166676Sjkim#define BCOM_DEVICEID_BCM5715 0x1678 2276166676Sjkim#define BCOM_DEVICEID_BCM5715S 0x1679 2277214428Syongari#define BCOM_DEVICEID_BCM5717 0x1655 2278214428Syongari#define BCOM_DEVICEID_BCM5718 0x1656 2279221818Syongari#define BCOM_DEVICEID_BCM5719 0x1657 2280166676Sjkim#define BCOM_DEVICEID_BCM5720 0x1658 2281166676Sjkim#define BCOM_DEVICEID_BCM5721 0x1659 2282176883Sjhb#define BCOM_DEVICEID_BCM5722 0x165A 2283197832Sstas#define BCOM_DEVICEID_BCM5723 0x165B 2284166676Sjkim#define BCOM_DEVICEID_BCM5750 0x1676 2285166676Sjkim#define BCOM_DEVICEID_BCM5750M 0x167C 2286166676Sjkim#define BCOM_DEVICEID_BCM5751 0x1677 2287166676Sjkim#define BCOM_DEVICEID_BCM5751F 0x167E 2288166676Sjkim#define BCOM_DEVICEID_BCM5751M 0x167D 2289166676Sjkim#define BCOM_DEVICEID_BCM5752 0x1600 2290166676Sjkim#define BCOM_DEVICEID_BCM5752M 0x1601 2291166676Sjkim#define BCOM_DEVICEID_BCM5753 0x16F7 2292166676Sjkim#define BCOM_DEVICEID_BCM5753F 0x16FE 2293166676Sjkim#define BCOM_DEVICEID_BCM5753M 0x16FD 2294166676Sjkim#define BCOM_DEVICEID_BCM5754 0x167A 2295166676Sjkim#define BCOM_DEVICEID_BCM5754M 0x1672 2296166676Sjkim#define BCOM_DEVICEID_BCM5755 0x167B 2297166676Sjkim#define BCOM_DEVICEID_BCM5755M 0x1673 2298202268Sdelphij#define BCOM_DEVICEID_BCM5756 0x1674 2299197832Sstas#define BCOM_DEVICEID_BCM5761 0x1681 2300197832Sstas#define BCOM_DEVICEID_BCM5761E 0x1680 2301197832Sstas#define BCOM_DEVICEID_BCM5761S 0x1688 2302197832Sstas#define BCOM_DEVICEID_BCM5761SE 0x1689 2303197832Sstas#define BCOM_DEVICEID_BCM5764 0x1684 2304166676Sjkim#define BCOM_DEVICEID_BCM5780 0x166A 2305166676Sjkim#define BCOM_DEVICEID_BCM5780S 0x166B 2306166676Sjkim#define BCOM_DEVICEID_BCM5781 0x16DD 2307166676Sjkim#define BCOM_DEVICEID_BCM5782 0x1696 2308197832Sstas#define BCOM_DEVICEID_BCM5784 0x1698 2309197832Sstas#define BCOM_DEVICEID_BCM5785F 0x16a0 2310197832Sstas#define BCOM_DEVICEID_BCM5785G 0x1699 2311166676Sjkim#define BCOM_DEVICEID_BCM5786 0x169A 2312166676Sjkim#define BCOM_DEVICEID_BCM5787 0x169B 2313166676Sjkim#define BCOM_DEVICEID_BCM5787M 0x1693 2314197832Sstas#define BCOM_DEVICEID_BCM5787F 0x167f 2315166676Sjkim#define BCOM_DEVICEID_BCM5788 0x169C 2316166676Sjkim#define BCOM_DEVICEID_BCM5789 0x169D 2317166676Sjkim#define BCOM_DEVICEID_BCM5901 0x170D 2318166676Sjkim#define BCOM_DEVICEID_BCM5901A2 0x170E 2319166676Sjkim#define BCOM_DEVICEID_BCM5903M 0x16FF 2320178667Sjhb#define BCOM_DEVICEID_BCM5906 0x1712 2321178667Sjhb#define BCOM_DEVICEID_BCM5906M 0x1713 2322197832Sstas#define BCOM_DEVICEID_BCM57760 0x1690 2323221445Syongari#define BCOM_DEVICEID_BCM57761 0x16B0 2324221445Syongari#define BCOM_DEVICEID_BCM57765 0x16B4 2325197832Sstas#define BCOM_DEVICEID_BCM57780 0x1692 2326221445Syongari#define BCOM_DEVICEID_BCM57781 0x16B1 2327221445Syongari#define BCOM_DEVICEID_BCM57785 0x16B5 2328197832Sstas#define BCOM_DEVICEID_BCM57788 0x1691 2329197832Sstas#define BCOM_DEVICEID_BCM57790 0x1694 2330221445Syongari#define BCOM_DEVICEID_BCM57791 0x16B2 2331221445Syongari#define BCOM_DEVICEID_BCM57795 0x16B6 233284059Swpaul 233384059Swpaul/* 233484059Swpaul * Alteon AceNIC PCI vendor/device ID. 233584059Swpaul */ 2336166676Sjkim#define ALTEON_VENDORID 0x12AE 2337166676Sjkim#define ALTEON_DEVICEID_ACENIC 0x0001 2338166676Sjkim#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2339166676Sjkim#define ALTEON_DEVICEID_BCM5700 0x0003 2340166676Sjkim#define ALTEON_DEVICEID_BCM5701 0x0004 234184059Swpaul 234284059Swpaul/* 2343162982Sglebius * 3Com 3c996 PCI vendor/device ID. 234484059Swpaul */ 2345166676Sjkim#define TC_VENDORID 0x10B7 2346166676Sjkim#define TC_DEVICEID_3C996 0x0003 234784059Swpaul 234884059Swpaul/* 234984059Swpaul * SysKonnect PCI vendor ID 235084059Swpaul */ 2351166676Sjkim#define SK_VENDORID 0x1148 2352166676Sjkim#define SK_DEVICEID_ALTIMA 0x4400 2353166676Sjkim#define SK_SUBSYSID_9D21 0x4421 2354166676Sjkim#define SK_SUBSYSID_9D41 0x4441 235584059Swpaul 235684059Swpaul/* 235789835Sjdp * Altima PCI vendor/device ID. 235889835Sjdp */ 2359166676Sjkim#define ALTIMA_VENDORID 0x173b 2360166676Sjkim#define ALTIMA_DEVICE_AC1000 0x03e8 2361166676Sjkim#define ALTIMA_DEVICE_AC1002 0x03e9 2362166676Sjkim#define ALTIMA_DEVICE_AC9100 0x03ea 236389835Sjdp 236489835Sjdp/* 2365119157Sambrisko * Dell PCI vendor ID 2366119157Sambrisko */ 2367119157Sambrisko 2368166676Sjkim#define DELL_VENDORID 0x1028 2369119157Sambrisko 2370119157Sambrisko/* 2371159637Sglebius * Apple PCI vendor ID. 2372159637Sglebius */ 2373166676Sjkim#define APPLE_VENDORID 0x106b 2374166676Sjkim#define APPLE_DEVICE_BCM5701 0x1645 2375159637Sglebius 2376159637Sglebius/* 2377169152Smarius * Sun PCI vendor ID 2378169152Smarius */ 2379169152Smarius#define SUN_VENDORID 0x108e 2380169152Smarius 2381169152Smarius/* 2382197832Sstas * Fujitsu vendor/device IDs 2383197832Sstas */ 2384197832Sstas#define FJTSU_VENDORID 0x10cf 2385197832Sstas#define FJTSU_DEVICEID_PW008GE5 0x11a1 2386197832Sstas#define FJTSU_DEVICEID_PW008GE4 0x11a2 2387197832Sstas#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2388197832Sstas 2389197832Sstas/* 239084059Swpaul * Offset of MAC address inside EEPROM. 239184059Swpaul */ 2392166676Sjkim#define BGE_EE_MAC_OFFSET 0x7C 2393178667Sjhb#define BGE_EE_MAC_OFFSET_5906 0x10 2394166676Sjkim#define BGE_EE_HWCFG_OFFSET 0xC8 239584059Swpaul 2396166676Sjkim#define BGE_HWCFG_VOLTAGE 0x00000003 2397166676Sjkim#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2398166676Sjkim#define BGE_HWCFG_MEDIA 0x00000030 2399166676Sjkim#define BGE_HWCFG_ASF 0x00000080 240093751Swpaul 2401166676Sjkim#define BGE_VOLTAGE_1POINT3 0x00000000 2402166676Sjkim#define BGE_VOLTAGE_1POINT8 0x00000001 240393751Swpaul 2404166676Sjkim#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2405166676Sjkim#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2406166676Sjkim#define BGE_PHYLEDMODE_SINGLELED 0x00000008 240793751Swpaul 2408166676Sjkim#define BGE_MEDIA_UNSPEC 0x00000000 2409166676Sjkim#define BGE_MEDIA_COPPER 0x00000010 2410166676Sjkim#define BGE_MEDIA_FIBER 0x00000020 241193751Swpaul 2412166676Sjkim#define BGE_TICKS_PER_SEC 1000000 241384059Swpaul 241484059Swpaul/* 241584059Swpaul * Ring size constants. 241684059Swpaul */ 2417166676Sjkim#define BGE_EVENT_RING_CNT 256 2418166676Sjkim#define BGE_CMD_RING_CNT 64 2419166676Sjkim#define BGE_STD_RX_RING_CNT 512 2420166676Sjkim#define BGE_JUMBO_RX_RING_CNT 256 2421166676Sjkim#define BGE_MINI_RX_RING_CNT 1024 2422166676Sjkim#define BGE_RETURN_RING_CNT 1024 242384059Swpaul 2424117659Swpaul/* 5705 has smaller return ring size */ 2425117659Swpaul 2426166676Sjkim#define BGE_RETURN_RING_CNT_5705 512 2427117659Swpaul 242884059Swpaul/* 242984059Swpaul * Possible TX ring sizes. 243084059Swpaul */ 2431166676Sjkim#define BGE_TX_RING_CNT_128 128 2432166676Sjkim#define BGE_TX_RING_BASE_128 0x3800 243384059Swpaul 2434166676Sjkim#define BGE_TX_RING_CNT_256 256 2435166676Sjkim#define BGE_TX_RING_BASE_256 0x3000 243684059Swpaul 2437166676Sjkim#define BGE_TX_RING_CNT_512 512 2438166676Sjkim#define BGE_TX_RING_BASE_512 0x2000 243984059Swpaul 2440166676Sjkim#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2441166676Sjkim#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 244284059Swpaul 244384059Swpaul/* 244484059Swpaul * Tigon III statistics counters. 244584059Swpaul */ 2446117659Swpaul/* Statistics maintained MAC Receive block. */ 2447117659Swpaulstruct bge_rx_mac_stats { 244884059Swpaul bge_hostaddr ifHCInOctets; 244984059Swpaul bge_hostaddr Reserved1; 245084059Swpaul bge_hostaddr etherStatsFragments; 245184059Swpaul bge_hostaddr ifHCInUcastPkts; 245284059Swpaul bge_hostaddr ifHCInMulticastPkts; 245384059Swpaul bge_hostaddr ifHCInBroadcastPkts; 245484059Swpaul bge_hostaddr dot3StatsFCSErrors; 245584059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 245684059Swpaul bge_hostaddr xonPauseFramesReceived; 245784059Swpaul bge_hostaddr xoffPauseFramesReceived; 245884059Swpaul bge_hostaddr macControlFramesReceived; 245984059Swpaul bge_hostaddr xoffStateEntered; 246084059Swpaul bge_hostaddr dot3StatsFramesTooLong; 246184059Swpaul bge_hostaddr etherStatsJabbers; 246284059Swpaul bge_hostaddr etherStatsUndersizePkts; 246384059Swpaul bge_hostaddr inRangeLengthError; 246484059Swpaul bge_hostaddr outRangeLengthError; 246584059Swpaul bge_hostaddr etherStatsPkts64Octets; 246684059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 246784059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 246884059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 246984059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 247084059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 247184059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 247284059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 247384059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 247484059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2475117659Swpaul}; 247684059Swpaul 247784059Swpaul 2478117659Swpaul/* Statistics maintained MAC Transmit block. */ 2479117659Swpaulstruct bge_tx_mac_stats { 248084059Swpaul bge_hostaddr ifHCOutOctets; 248184059Swpaul bge_hostaddr Reserved2; 248284059Swpaul bge_hostaddr etherStatsCollisions; 248384059Swpaul bge_hostaddr outXonSent; 248484059Swpaul bge_hostaddr outXoffSent; 248584059Swpaul bge_hostaddr flowControlDone; 248684059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 248784059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 248884059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 248984059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 249084059Swpaul bge_hostaddr Reserved3; 249184059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 249284059Swpaul bge_hostaddr dot3StatsLateCollisions; 249384059Swpaul bge_hostaddr dot3Collided2Times; 249484059Swpaul bge_hostaddr dot3Collided3Times; 249584059Swpaul bge_hostaddr dot3Collided4Times; 249684059Swpaul bge_hostaddr dot3Collided5Times; 249784059Swpaul bge_hostaddr dot3Collided6Times; 249884059Swpaul bge_hostaddr dot3Collided7Times; 249984059Swpaul bge_hostaddr dot3Collided8Times; 250084059Swpaul bge_hostaddr dot3Collided9Times; 250184059Swpaul bge_hostaddr dot3Collided10Times; 250284059Swpaul bge_hostaddr dot3Collided11Times; 250384059Swpaul bge_hostaddr dot3Collided12Times; 250484059Swpaul bge_hostaddr dot3Collided13Times; 250584059Swpaul bge_hostaddr dot3Collided14Times; 250684059Swpaul bge_hostaddr dot3Collided15Times; 250784059Swpaul bge_hostaddr ifHCOutUcastPkts; 250884059Swpaul bge_hostaddr ifHCOutMulticastPkts; 250984059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 251084059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 251184059Swpaul bge_hostaddr ifOutDiscards; 251284059Swpaul bge_hostaddr ifOutErrors; 2513117659Swpaul}; 251484059Swpaul 2515117659Swpaul/* Stats counters access through registers */ 2516213283Syongaristruct bge_mac_stats { 2517213283Syongari /* TX MAC statistics */ 2518213283Syongari uint64_t ifHCOutOctets; 2519213283Syongari uint64_t Reserved0; 2520213283Syongari uint64_t etherStatsCollisions; 2521213283Syongari uint64_t outXonSent; 2522213283Syongari uint64_t outXoffSent; 2523213283Syongari uint64_t Reserved1; 2524213283Syongari uint64_t dot3StatsInternalMacTransmitErrors; 2525213283Syongari uint64_t dot3StatsSingleCollisionFrames; 2526213283Syongari uint64_t dot3StatsMultipleCollisionFrames; 2527213283Syongari uint64_t dot3StatsDeferredTransmissions; 2528213283Syongari uint64_t Reserved2; 2529213283Syongari uint64_t dot3StatsExcessiveCollisions; 2530213283Syongari uint64_t dot3StatsLateCollisions; 2531213283Syongari uint64_t Reserved3[14]; 2532213283Syongari uint64_t ifHCOutUcastPkts; 2533213283Syongari uint64_t ifHCOutMulticastPkts; 2534213283Syongari uint64_t ifHCOutBroadcastPkts; 2535213283Syongari uint64_t Reserved4[2]; 2536213283Syongari /* RX MAC statistics */ 2537213283Syongari uint64_t ifHCInOctets; 2538213283Syongari uint64_t Reserved5; 2539213283Syongari uint64_t etherStatsFragments; 2540213283Syongari uint64_t ifHCInUcastPkts; 2541213283Syongari uint64_t ifHCInMulticastPkts; 2542213283Syongari uint64_t ifHCInBroadcastPkts; 2543213283Syongari uint64_t dot3StatsFCSErrors; 2544213283Syongari uint64_t dot3StatsAlignmentErrors; 2545213283Syongari uint64_t xonPauseFramesReceived; 2546213283Syongari uint64_t xoffPauseFramesReceived; 2547213283Syongari uint64_t macControlFramesReceived; 2548213283Syongari uint64_t xoffStateEntered; 2549213283Syongari uint64_t dot3StatsFramesTooLong; 2550213283Syongari uint64_t etherStatsJabbers; 2551213283Syongari uint64_t etherStatsUndersizePkts; 2552213283Syongari /* Receive List Placement control */ 2553213283Syongari uint64_t FramesDroppedDueToFilters; 2554213283Syongari uint64_t DmaWriteQueueFull; 2555213283Syongari uint64_t DmaWriteHighPriQueueFull; 2556213283Syongari uint64_t NoMoreRxBDs; 2557213283Syongari uint64_t InputDiscards; 2558213283Syongari uint64_t InputErrors; 2559213283Syongari uint64_t RecvThresholdHit; 2560117659Swpaul}; 2561117659Swpaul 2562117659Swpaulstruct bge_stats { 2563159395Sglebius uint8_t Reserved0[256]; 2564117659Swpaul 2565117659Swpaul /* Statistics maintained by Receive MAC. */ 2566117659Swpaul struct bge_rx_mac_stats rxstats; 2567117659Swpaul 2568117659Swpaul bge_hostaddr Unused1[37]; 2569117659Swpaul 2570117659Swpaul /* Statistics maintained by Transmit MAC. */ 2571117659Swpaul struct bge_tx_mac_stats txstats; 2572117659Swpaul 257384059Swpaul bge_hostaddr Unused2[31]; 257484059Swpaul 257584059Swpaul /* Statistics maintained by Receive List Placement. */ 257684059Swpaul bge_hostaddr COSIfHCInPkts[16]; 257784059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 257884059Swpaul bge_hostaddr nicDmaWriteQueueFull; 257984059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 258084059Swpaul bge_hostaddr nicNoMoreRxBDs; 258184059Swpaul bge_hostaddr ifInDiscards; 258284059Swpaul bge_hostaddr ifInErrors; 258384059Swpaul bge_hostaddr nicRecvThresholdHit; 258484059Swpaul 258584059Swpaul bge_hostaddr Unused3[9]; 258684059Swpaul 258784059Swpaul /* Statistics maintained by Send Data Initiator. */ 258884059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 258984059Swpaul bge_hostaddr nicDmaReadQueueFull; 259084059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 259184059Swpaul bge_hostaddr nicSendDataCompQueueFull; 259284059Swpaul 259384059Swpaul /* Statistics maintained by Host Coalescing. */ 259484059Swpaul bge_hostaddr nicRingSetSendProdIndex; 259584059Swpaul bge_hostaddr nicRingStatusUpdate; 259684059Swpaul bge_hostaddr nicInterrupts; 259784059Swpaul bge_hostaddr nicAvoidedInterrupts; 259884059Swpaul bge_hostaddr nicSendThresholdHit; 259984059Swpaul 2600159395Sglebius uint8_t Reserved4[320]; 260184059Swpaul}; 260284059Swpaul 260384059Swpaul/* 260484059Swpaul * Tigon general information block. This resides in host memory 260584059Swpaul * and contains the status counters, ring control blocks and 260684059Swpaul * producer pointers. 260784059Swpaul */ 260884059Swpaul 260984059Swpaulstruct bge_gib { 261084059Swpaul struct bge_stats bge_stats; 261184059Swpaul struct bge_rcb bge_tx_rcb[16]; 261284059Swpaul struct bge_rcb bge_std_rx_rcb; 261384059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 261484059Swpaul struct bge_rcb bge_mini_rx_rcb; 261584059Swpaul struct bge_rcb bge_return_rcb; 261684059Swpaul}; 261784059Swpaul 2618166676Sjkim#define BGE_FRAMELEN 1518 2619166676Sjkim#define BGE_MAX_FRAMELEN 1536 2620166676Sjkim#define BGE_JUMBO_FRAMELEN 9018 2621166676Sjkim#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2622166676Sjkim#define BGE_MIN_FRAMELEN 60 262384059Swpaul 262484059Swpaul/* 262584059Swpaul * Other utility macros. 262684059Swpaul */ 2627166676Sjkim#define BGE_INC(x, y) (x) = (x + 1) % y 262884059Swpaul 262984059Swpaul/* 263084059Swpaul * Register access macros. The Tigon always uses memory mapped register 263184059Swpaul * accesses and all registers must be accessed with 32 bit operations. 263284059Swpaul */ 263384059Swpaul 2634166676Sjkim#define CSR_WRITE_4(sc, reg, val) \ 2635183896Smarius bus_write_4(sc->bge_res, reg, val) 263684059Swpaul 2637166676Sjkim#define CSR_READ_4(sc, reg) \ 2638183896Smarius bus_read_4(sc->bge_res, reg) 263984059Swpaul 2640166676Sjkim#define BGE_SETBIT(sc, reg, x) \ 2641106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2642166676Sjkim#define BGE_CLRBIT(sc, reg, x) \ 2643106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 264484059Swpaul 2645166676Sjkim#define PCI_SETBIT(dev, reg, x, s) \ 2646106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2647166676Sjkim#define PCI_CLRBIT(dev, reg, x, s) \ 2648106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 264984059Swpaul 265084059Swpaul/* 2651208917Syongari * Memory management stuff. 265284059Swpaul */ 265384059Swpaul 2654166676Sjkim#define BGE_NSEG_JUMBO 4 2655199671Syongari#define BGE_NSEG_NEW 32 2656199671Syongari#define BGE_TSOSEG_SZ 4096 2657153239Sglebius 2658199670Syongari/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2659199670Syongari#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2660199670Syongari#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2661199670Syongari#else 2662199670Syongari#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2663199670Syongari#endif 2664199670Syongari 2665212065Syongari#ifdef PAE 2666212065Syongari#define BGE_DMA_BNDRY 0x80000000 2667212065Syongari#else 2668212061Syongari#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2669212065Syongari#define BGE_DMA_BNDRY 0x100000000 2670212061Syongari#else 2671212065Syongari#define BGE_DMA_BNDRY 0 2672212061Syongari#endif 2673212065Syongari#endif 2674212061Syongari 267584059Swpaul/* 267684059Swpaul * Ring structures. Most of these reside in host memory and we tell 267784059Swpaul * the NIC where they are via the ring control blocks. The exceptions 267884059Swpaul * are the tx and command rings, which live in NIC memory and which 267984059Swpaul * we access via the shared memory window. 268084059Swpaul */ 2681118026Swpaul 268284059Swpaulstruct bge_ring_data { 2683118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2684118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2685153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2686118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2687118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2688118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2689118026Swpaul struct bge_tx_bd *bge_tx_ring; 2690118026Swpaul bus_addr_t bge_tx_ring_paddr; 2691118026Swpaul struct bge_status_block *bge_status_block; 2692118026Swpaul bus_addr_t bge_status_block_paddr; 2693118026Swpaul struct bge_stats *bge_stats; 2694118026Swpaul bus_addr_t bge_stats_paddr; 269584059Swpaul struct bge_gib bge_info; 269684059Swpaul}; 269784059Swpaul 2698166676Sjkim#define BGE_STD_RX_RING_SZ \ 2699118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2700166676Sjkim#define BGE_JUMBO_RX_RING_SZ \ 2701153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2702166676Sjkim#define BGE_TX_RING_SZ \ 2703118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2704166676Sjkim#define BGE_RX_RTN_RING_SZ(x) \ 2705118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2706118026Swpaul 2707166676Sjkim#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2708118026Swpaul 2709166676Sjkim#define BGE_STATS_SZ sizeof (struct bge_stats) 2710118026Swpaul 271184059Swpaul/* 271284059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 271384059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 271484059Swpaul * not the other way around. 271584059Swpaul */ 271684059Swpaulstruct bge_chain_data { 2717118026Swpaul bus_dma_tag_t bge_parent_tag; 2718212061Syongari bus_dma_tag_t bge_buffer_tag; 2719118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2720118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2721118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2722118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2723118026Swpaul bus_dma_tag_t bge_status_tag; 2724118026Swpaul bus_dma_tag_t bge_stats_tag; 2725198927Syongari bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2726198927Syongari bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2727198927Syongari bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2728118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2729199011Syongari bus_dmamap_t bge_rx_std_sparemap; 2730118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2731199011Syongari bus_dmamap_t bge_rx_jumbo_sparemap; 2732118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2733118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2734118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2735118026Swpaul bus_dmamap_t bge_tx_ring_map; 2736118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2737118026Swpaul bus_dmamap_t bge_status_map; 2738118026Swpaul bus_dmamap_t bge_stats_map; 273984059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 274084059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 274184059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2742208862Syongari int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2743208862Syongari int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 274484059Swpaul}; 274584059Swpaul 2746118026Swpaulstruct bge_dmamap_arg { 2747118026Swpaul bus_addr_t bge_busaddr; 2748118026Swpaul}; 2749118026Swpaul 2750166676Sjkim#define BGE_HWREV_TIGON 0x01 2751166676Sjkim#define BGE_HWREV_TIGON_II 0x02 2752166676Sjkim#define BGE_TIMEOUT 100000 2753166676Sjkim#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 275484059Swpaul 275584059Swpaulstruct bge_bcom_hack { 275684059Swpaul int reg; 275784059Swpaul int val; 275884059Swpaul}; 275984059Swpaul 2760166676Sjkim#define ASF_ENABLE 1 2761166676Sjkim#define ASF_NEW_HANDSHAKE 2 2762166676Sjkim#define ASF_STACKUP 4 2763162169Sambrisko 276484059Swpaulstruct bge_softc { 2765147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 276684059Swpaul device_t bge_dev; 2767122497Ssam struct mtx bge_mtx; 276884059Swpaul device_t bge_miibus; 276984059Swpaul void *bge_intrhand; 277084059Swpaul struct resource *bge_irq; 277184059Swpaul struct resource *bge_res; 277284059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2773199664Syongari int bge_expcap; 2774199664Syongari int bge_msicap; 2775199664Syongari int bge_pcixcap; 2776161546Sglebius uint32_t bge_flags; 2777166676Sjkim#define BGE_FLAG_TBI 0x00000001 2778166676Sjkim#define BGE_FLAG_JUMBO 0x00000002 2779220368Syongari#define BGE_FLAG_JUMBO_STD 0x00000004 2780178996Smarius#define BGE_FLAG_EADDR 0x00000008 2781202293Syongari#define BGE_FLAG_MII_SERDES 0x00000010 2782213485Syongari#define BGE_FLAG_CPMU_PRESENT 0x00000020 2783214428Syongari#define BGE_FLAG_TAGGED_STATUS 0x00000040 2784166676Sjkim#define BGE_FLAG_MSI 0x00000100 2785166676Sjkim#define BGE_FLAG_PCIX 0x00000200 2786166676Sjkim#define BGE_FLAG_PCIE 0x00000400 2787199671Syongari#define BGE_FLAG_TSO 0x00000800 2788214428Syongari#define BGE_FLAG_TSO3 0x00001000 2789214428Syongari#define BGE_FLAG_JUMBO_FRAME 0x00002000 2790213464Syongari#define BGE_FLAG_5700_FAMILY 0x00010000 2791213464Syongari#define BGE_FLAG_5705_PLUS 0x00020000 2792213464Syongari#define BGE_FLAG_5714_FAMILY 0x00040000 2793213464Syongari#define BGE_FLAG_575X_PLUS 0x00080000 2794213464Syongari#define BGE_FLAG_5755_PLUS 0x00100000 2795213464Syongari#define BGE_FLAG_5788 0x00200000 2796214428Syongari#define BGE_FLAG_5717_PLUS 0x00400000 2797213464Syongari#define BGE_FLAG_40BIT_BUG 0x01000000 2798213464Syongari#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2799213464Syongari#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2800214087Syongari#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2801226807Syongari#define BGE_FLAG_4K_RDMA_BUG 0x10000000 2802213464Syongari uint32_t bge_phy_flags; 2803221468Syongari#define BGE_PHY_NO_WIRESPEED 0x00000001 2804213464Syongari#define BGE_PHY_ADC_BUG 0x00000002 2805213464Syongari#define BGE_PHY_5704_A0_BUG 0x00000004 2806213464Syongari#define BGE_PHY_JITTER_BUG 0x00000008 2807213464Syongari#define BGE_PHY_BER_BUG 0x00000010 2808213464Syongari#define BGE_PHY_ADJUST_TRIM 0x00000020 2809213464Syongari#define BGE_PHY_CRC_BUG 0x00000040 2810213464Syongari#define BGE_PHY_NO_3LED 0x00000080 2811159395Sglebius uint32_t bge_chipid; 2812197832Sstas uint32_t bge_asicrev; 2813197832Sstas uint32_t bge_chiprev; 2814162169Sambrisko uint8_t bge_asf_mode; 2815162169Sambrisko uint8_t bge_asf_count; 2816118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 281784059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 2818159395Sglebius uint16_t bge_tx_saved_considx; 2819159395Sglebius uint16_t bge_rx_saved_considx; 2820159395Sglebius uint16_t bge_ev_saved_considx; 2821159395Sglebius uint16_t bge_return_ring_cnt; 2822159395Sglebius uint16_t bge_std; /* current std ring head */ 2823159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 2824159395Sglebius uint32_t bge_stat_ticks; 2825159395Sglebius uint32_t bge_rx_coal_ticks; 2826159395Sglebius uint32_t bge_tx_coal_ticks; 2827159395Sglebius uint32_t bge_tx_prodidx; 2828159395Sglebius uint32_t bge_rx_max_coal_bds; 2829159395Sglebius uint32_t bge_tx_max_coal_bds; 2830213485Syongari uint32_t bge_mi_mode; 283184059Swpaul int bge_if_flags; 283284059Swpaul int bge_txcnt; 2833155180Soleg int bge_link; /* link state */ 2834155180Soleg int bge_link_evt; /* pending link event */ 2835164769Sglebius int bge_timer; 2836200264Syongari int bge_forced_collapse; 2837211596Syongari int bge_forced_udpcsum; 2838211596Syongari int bge_csum_features; 2839122497Ssam struct callout bge_stat_ch; 2840164780Sjkim uint32_t bge_rx_discards; 2841164780Sjkim uint32_t bge_tx_discards; 2842164780Sjkim uint32_t bge_tx_collisions; 2843151553Sglebius#ifdef DEVICE_POLLING 2844151553Sglebius int rxcycles; 2845151553Sglebius#endif /* DEVICE_POLLING */ 2846213283Syongari struct bge_mac_stats bge_mac_stats; 2847199668Syongari struct task bge_intr_task; 2848199668Syongari struct taskqueue *bge_tq; 284984059Swpaul}; 2850122497Ssam 2851122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2852122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2853122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2854122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2855122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2856122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2857