if_bgereg.h revision 221445
1249259Sdim/*- 2249259Sdim * Copyright (c) 2001 Wind River Systems 3249259Sdim * Copyright (c) 1997, 1998, 1999, 2001 4249259Sdim * Bill Paul <wpaul@windriver.com>. All rights reserved. 5249259Sdim * 6249259Sdim * Redistribution and use in source and binary forms, with or without 7249259Sdim * modification, are permitted provided that the following conditions 8249259Sdim * are met: 9249259Sdim * 1. Redistributions of source code must retain the above copyright 10249259Sdim * notice, this list of conditions and the following disclaimer. 11249259Sdim * 2. Redistributions in binary form must reproduce the above copyright 12249259Sdim * notice, this list of conditions and the following disclaimer in the 13249259Sdim * documentation and/or other materials provided with the distribution. 14249259Sdim * 3. All advertising materials mentioning features or use of this software 15249259Sdim * must display the following acknowledgement: 16249259Sdim * This product includes software developed by Bill Paul. 17249259Sdim * 4. Neither the name of the author nor the names of any co-contributors 18249259Sdim * may be used to endorse or promote products derived from this software 19249259Sdim * without specific prior written permission. 20263508Sdim * 21263508Sdim * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22263508Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23263508Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24263508Sdim * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25263508Sdim * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26263508Sdim * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27249259Sdim * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28249259Sdim * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29249259Sdim * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30249259Sdim * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31263508Sdim * THE POSSIBILITY OF SUCH DAMAGE. 32263508Sdim * 33263508Sdim * $FreeBSD: head/sys/dev/bge/if_bgereg.h 221445 2011-05-04 17:04:31Z yongari $ 34263508Sdim */ 35263508Sdim 36263508Sdim/* 37263508Sdim * BCM570x memory map. The internal memory layout varies somewhat 38249259Sdim * depending on whether or not we have external SSRAM attached. 39249259Sdim * The BCM5700 can have up to 16MB of external memory. The BCM5701 40249259Sdim * is apparently not designed to use external SSRAM. The mappings 41249259Sdim * up to the first 4 send rings are the same for both internal and 42249259Sdim * external memory configurations. Note that mini RX ring space is 43249259Sdim * only available with external SSRAM configurations, which means 44249259Sdim * the mini RX ring is not supported on the BCM5701. 45249259Sdim * 46249259Sdim * The NIC's memory can be accessed by the host in one of 3 ways: 47249259Sdim * 48249259Sdim * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49249259Sdim * registers in PCI config space can be used to read any 32-bit 50249259Sdim * address within the NIC's memory. 51249259Sdim * 52249259Sdim * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53249259Sdim * space can be used in conjunction with the memory window in the 54249259Sdim * device register space at offset 0x8000 to read any 32K chunk 55249259Sdim * of NIC memory. 56249259Sdim * 57249259Sdim * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58249259Sdim * set, the device I/O mapping consumes 32MB of host address space, 59249259Sdim * allowing all of the registers and internal NIC memory to be 60249259Sdim * accessed directly. NIC memory addresses are offset by 0x01000000. 61249259Sdim * Flat mode consumes so much host address space that it is not 62249259Sdim * recommended. 63249259Sdim */ 64249259Sdim#define BGE_PAGE_ZERO 0x00000000 65249259Sdim#define BGE_PAGE_ZERO_END 0x000000FF 66249259Sdim#define BGE_SEND_RING_RCB 0x00000100 67249259Sdim#define BGE_SEND_RING_RCB_END 0x000001FF 68249259Sdim#define BGE_RX_RETURN_RING_RCB 0x00000200 69249259Sdim#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70249259Sdim#define BGE_STATS_BLOCK 0x00000300 71249259Sdim#define BGE_STATS_BLOCK_END 0x00000AFF 72263508Sdim#define BGE_STATUS_BLOCK 0x00000B00 73249259Sdim#define BGE_STATUS_BLOCK_END 0x00000B4F 74249259Sdim#define BGE_SOFTWARE_GENCOMM 0x00000B50 75249259Sdim#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76249259Sdim#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77249259Sdim#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78249259Sdim#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79249259Sdim#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80249259Sdim#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81249259Sdim#define BGE_UNMAPPED 0x00001000 82249259Sdim#define BGE_UNMAPPED_END 0x00001FFF 83249259Sdim#define BGE_DMA_DESCRIPTORS 0x00002000 84249259Sdim#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85249259Sdim#define BGE_SEND_RING_5717 0x00004000 86249259Sdim#define BGE_SEND_RING_1_TO_4 0x00004000 87249259Sdim#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 88249259Sdim 89249259Sdim/* Firmware interface */ 90249259Sdim#define BGE_FW_DRV_ALIVE 0x00000001 91263508Sdim#define BGE_FW_PAUSE 0x00000002 92249259Sdim 93249259Sdim/* Mappings for internal memory configuration */ 94249259Sdim#define BGE_STD_RX_RINGS 0x00006000 95249259Sdim#define BGE_STD_RX_RINGS_END 0x00006FFF 96249259Sdim#define BGE_JUMBO_RX_RINGS 0x00007000 97249259Sdim#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 98249259Sdim#define BGE_BUFFPOOL_1 0x00008000 99249259Sdim#define BGE_BUFFPOOL_1_END 0x0000FFFF 100249259Sdim#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 101249259Sdim#define BGE_BUFFPOOL_2_END 0x00017FFF 102249259Sdim#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 103249259Sdim#define BGE_BUFFPOOL_3_END 0x0001FFFF 104249259Sdim#define BGE_STD_RX_RINGS_5717 0x00040000 105249259Sdim#define BGE_JUMBO_RX_RINGS_5717 0x00044400 106249259Sdim 107249259Sdim/* Mappings for external SSRAM configurations */ 108249259Sdim#define BGE_SEND_RING_5_TO_6 0x00006000 109263508Sdim#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 110249259Sdim#define BGE_SEND_RING_7_TO_8 0x00007000 111249259Sdim#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 112249259Sdim#define BGE_SEND_RING_9_TO_16 0x00008000 113249259Sdim#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 114249259Sdim#define BGE_EXT_STD_RX_RINGS 0x0000C000 115249259Sdim#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 116249259Sdim#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 117249259Sdim#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 118249259Sdim#define BGE_MINI_RX_RINGS 0x0000E000 119249259Sdim#define BGE_MINI_RX_RINGS_END 0x0000FFFF 120249259Sdim#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 121249259Sdim#define BGE_AVAIL_REGION1_END 0x00017FFF 122249259Sdim#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 123249259Sdim#define BGE_AVAIL_REGION2_END 0x0001FFFF 124249259Sdim#define BGE_EXT_SSRAM 0x00020000 125249259Sdim#define BGE_EXT_SSRAM_END 0x000FFFFF 126263508Sdim 127249259Sdim 128249259Sdim/* 129249259Sdim * BCM570x register offsets. These are memory mapped registers 130249259Sdim * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 131249259Sdim * Each register must be accessed using 32 bit operations. 132249259Sdim * 133249259Sdim * All registers are accessed through a 32K shared memory block. 134249259Sdim * The first group of registers are actually copies of the PCI 135249259Sdim * configuration space registers. 136249259Sdim */ 137249259Sdim 138249259Sdim/* 139249259Sdim * PCI registers defined in the PCI 2.2 spec. 140249259Sdim */ 141249259Sdim#define BGE_PCI_VID 0x00 142249259Sdim#define BGE_PCI_DID 0x02 143249259Sdim#define BGE_PCI_CMD 0x04 144263508Sdim#define BGE_PCI_STS 0x06 145249259Sdim#define BGE_PCI_REV 0x08 146249259Sdim#define BGE_PCI_CLASS 0x09 147249259Sdim#define BGE_PCI_CACHESZ 0x0C 148249259Sdim#define BGE_PCI_LATTIMER 0x0D 149249259Sdim#define BGE_PCI_HDRTYPE 0x0E 150249259Sdim#define BGE_PCI_BIST 0x0F 151249259Sdim#define BGE_PCI_BAR0 0x10 152249259Sdim#define BGE_PCI_BAR1 0x14 153249259Sdim#define BGE_PCI_SUBSYS 0x2C 154249259Sdim#define BGE_PCI_SUBVID 0x2E 155249259Sdim#define BGE_PCI_ROMBASE 0x30 156249259Sdim#define BGE_PCI_CAPPTR 0x34 157249259Sdim#define BGE_PCI_INTLINE 0x3C 158249259Sdim#define BGE_PCI_INTPIN 0x3D 159249259Sdim#define BGE_PCI_MINGNT 0x3E 160249259Sdim#define BGE_PCI_MAXLAT 0x3F 161249259Sdim#define BGE_PCI_PCIXCAP 0x40 162263508Sdim#define BGE_PCI_NEXTPTR_PM 0x41 163249259Sdim#define BGE_PCI_PCIX_CMD 0x42 164249259Sdim#define BGE_PCI_PCIX_STS 0x44 165249259Sdim#define BGE_PCI_PWRMGMT_CAPID 0x48 166249259Sdim#define BGE_PCI_NEXTPTR_VPD 0x49 167249259Sdim#define BGE_PCI_PWRMGMT_CAPS 0x4A 168249259Sdim#define BGE_PCI_PWRMGMT_CMD 0x4C 169249259Sdim#define BGE_PCI_PWRMGMT_STS 0x4D 170249259Sdim#define BGE_PCI_PWRMGMT_DATA 0x4F 171249259Sdim#define BGE_PCI_VPD_CAPID 0x50 172249259Sdim#define BGE_PCI_NEXTPTR_MSI 0x51 173249259Sdim#define BGE_PCI_VPD_ADDR 0x52 174249259Sdim#define BGE_PCI_VPD_DATA 0x54 175249259Sdim#define BGE_PCI_MSI_CAPID 0x58 176249259Sdim#define BGE_PCI_NEXTPTR_NONE 0x59 177249259Sdim#define BGE_PCI_MSI_CTL 0x5A 178249259Sdim#define BGE_PCI_MSI_ADDR_HI 0x5C 179249259Sdim#define BGE_PCI_MSI_ADDR_LO 0x60 180249259Sdim#define BGE_PCI_MSI_DATA 0x64 181249259Sdim 182249259Sdim/* 183249259Sdim * PCI Express definitions 184249259Sdim * According to 185263508Sdim * PCI Express base specification, REV. 1.0a 186263508Sdim */ 187249259Sdim 188249259Sdim/* PCI Express device control, 16bits */ 189249259Sdim#define BGE_PCIE_DEVCTL 0x08 190249259Sdim#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 191249259Sdim#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 192249259Sdim#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 193249259Sdim#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 194249259Sdim#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 195249259Sdim#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 196249259Sdim#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 197249259Sdim 198249259Sdim/* PCI MSI. ??? */ 199249259Sdim#define BGE_PCIE_CAPID_REG 0xD0 200249259Sdim#define BGE_PCIE_CAPID 0x10 201249259Sdim 202249259Sdim/* 203249259Sdim * PCI registers specific to the BCM570x family. 204249259Sdim */ 205263508Sdim#define BGE_PCI_MISC_CTL 0x68 206263508Sdim#define BGE_PCI_DMA_RW_CTL 0x6C 207249259Sdim#define BGE_PCI_PCISTATE 0x70 208249259Sdim#define BGE_PCI_CLKCTL 0x74 209249259Sdim#define BGE_PCI_REG_BASEADDR 0x78 210249259Sdim#define BGE_PCI_MEMWIN_BASEADDR 0x7C 211249259Sdim#define BGE_PCI_REG_DATA 0x80 212263508Sdim#define BGE_PCI_MEMWIN_DATA 0x84 213263508Sdim#define BGE_PCI_MODECTL 0x88 214263508Sdim#define BGE_PCI_MISC_CFG 0x8C 215263508Sdim#define BGE_PCI_MISC_LOCALCTL 0x90 216263508Sdim#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 217263508Sdim#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 218263508Sdim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 219263508Sdim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 220249259Sdim#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 221263508Sdim#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 222263508Sdim#define BGE_PCI_ISR_MBX_HI 0xB0 223263508Sdim#define BGE_PCI_ISR_MBX_LO 0xB4 224249259Sdim#define BGE_PCI_PRODID_ASICREV 0xBC 225249259Sdim#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 226263508Sdim#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 227263508Sdim 228263508Sdim/* PCI Misc. Host control register */ 229263508Sdim#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 230263508Sdim#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 231249259Sdim#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 232249259Sdim#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 233249259Sdim#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 234249259Sdim#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 235263508Sdim#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 236263508Sdim#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 237249259Sdim#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 238249259Sdim#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 239249259Sdim#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 240249259Sdim 241249259Sdim#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 242263508Sdim#if BYTE_ORDER == LITTLE_ENDIAN 243263508Sdim#define BGE_DMA_SWAP_OPTIONS \ 244263508Sdim BGE_MODECTL_WORDSWAP_NONFRAME| \ 245263508Sdim BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 246263508Sdim#else 247263508Sdim#define BGE_DMA_SWAP_OPTIONS \ 248263508Sdim BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 249249259Sdim BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 250263508Sdim#endif 251263508Sdim 252249259Sdim#define BGE_INIT \ 253249259Sdim (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 254263508Sdim BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 255263508Sdim 256263508Sdim#define BGE_CHIPID_TIGON_I 0x4000 257263508Sdim#define BGE_CHIPID_TIGON_II 0x6000 258263508Sdim#define BGE_CHIPID_BCM5700_A0 0x7000 259249259Sdim#define BGE_CHIPID_BCM5700_A1 0x7001 260249259Sdim#define BGE_CHIPID_BCM5700_B0 0x7100 261249259Sdim#define BGE_CHIPID_BCM5700_B1 0x7101 262249259Sdim#define BGE_CHIPID_BCM5700_B2 0x7102 263263508Sdim#define BGE_CHIPID_BCM5700_B3 0x7103 264263508Sdim#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 265249259Sdim#define BGE_CHIPID_BCM5700_C0 0x7200 266249259Sdim#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 267249259Sdim#define BGE_CHIPID_BCM5701_B0 0x0100 268249259Sdim#define BGE_CHIPID_BCM5701_B2 0x0102 269249259Sdim#define BGE_CHIPID_BCM5701_B5 0x0105 270249259Sdim#define BGE_CHIPID_BCM5703_A0 0x1000 271249259Sdim#define BGE_CHIPID_BCM5703_A1 0x1001 272249259Sdim#define BGE_CHIPID_BCM5703_A2 0x1002 273249259Sdim#define BGE_CHIPID_BCM5703_A3 0x1003 274249259Sdim#define BGE_CHIPID_BCM5703_B0 0x1100 275249259Sdim#define BGE_CHIPID_BCM5704_A0 0x2000 276249259Sdim#define BGE_CHIPID_BCM5704_A1 0x2001 277249259Sdim#define BGE_CHIPID_BCM5704_A2 0x2002 278249259Sdim#define BGE_CHIPID_BCM5704_A3 0x2003 279249259Sdim#define BGE_CHIPID_BCM5704_B0 0x2100 280249259Sdim#define BGE_CHIPID_BCM5705_A0 0x3000 281249259Sdim#define BGE_CHIPID_BCM5705_A1 0x3001 282263508Sdim#define BGE_CHIPID_BCM5705_A2 0x3002 283249259Sdim#define BGE_CHIPID_BCM5705_A3 0x3003 284249259Sdim#define BGE_CHIPID_BCM5750_A0 0x4000 285249259Sdim#define BGE_CHIPID_BCM5750_A1 0x4001 286249259Sdim#define BGE_CHIPID_BCM5750_A3 0x4000 287249259Sdim#define BGE_CHIPID_BCM5750_B0 0x4100 288249259Sdim#define BGE_CHIPID_BCM5750_B1 0x4101 289249259Sdim#define BGE_CHIPID_BCM5750_C0 0x4200 290249259Sdim#define BGE_CHIPID_BCM5750_C1 0x4201 291249259Sdim#define BGE_CHIPID_BCM5750_C2 0x4202 292249259Sdim#define BGE_CHIPID_BCM5714_A0 0x5000 293249259Sdim#define BGE_CHIPID_BCM5752_A0 0x6000 294249259Sdim#define BGE_CHIPID_BCM5752_A1 0x6001 295249259Sdim#define BGE_CHIPID_BCM5752_A2 0x6002 296249259Sdim#define BGE_CHIPID_BCM5714_B0 0x8000 297249259Sdim#define BGE_CHIPID_BCM5714_B3 0x8003 298249259Sdim#define BGE_CHIPID_BCM5715_A0 0x9000 299249259Sdim#define BGE_CHIPID_BCM5715_A1 0x9001 300249259Sdim#define BGE_CHIPID_BCM5715_A3 0x9003 301249259Sdim#define BGE_CHIPID_BCM5755_A0 0xa000 302249259Sdim#define BGE_CHIPID_BCM5755_A1 0xa001 303249259Sdim#define BGE_CHIPID_BCM5755_A2 0xa002 304249259Sdim#define BGE_CHIPID_BCM5722_A0 0xa200 305249259Sdim#define BGE_CHIPID_BCM5754_A0 0xb000 306249259Sdim#define BGE_CHIPID_BCM5754_A1 0xb001 307249259Sdim#define BGE_CHIPID_BCM5754_A2 0xb002 308249259Sdim#define BGE_CHIPID_BCM5761_A0 0x5761000 309249259Sdim#define BGE_CHIPID_BCM5761_A1 0x5761100 310249259Sdim#define BGE_CHIPID_BCM5784_A0 0x5784000 311249259Sdim#define BGE_CHIPID_BCM5784_A1 0x5784100 312249259Sdim#define BGE_CHIPID_BCM5787_A0 0xb000 313263508Sdim#define BGE_CHIPID_BCM5787_A1 0xb001 314263508Sdim#define BGE_CHIPID_BCM5787_A2 0xb002 315263508Sdim#define BGE_CHIPID_BCM5906_A0 0xc000 316263508Sdim#define BGE_CHIPID_BCM5906_A1 0xc001 317263508Sdim#define BGE_CHIPID_BCM5906_A2 0xc002 318263508Sdim#define BGE_CHIPID_BCM57780_A0 0x57780000 319263508Sdim#define BGE_CHIPID_BCM57780_A1 0x57780001 320263508Sdim#define BGE_CHIPID_BCM5717_A0 0x05717000 321263508Sdim#define BGE_CHIPID_BCM5717_B0 0x05717100 322263508Sdim#define BGE_CHIPID_BCM57765_A0 0x57785000 323263508Sdim#define BGE_CHIPID_BCM57765_B0 0x57785100 324263508Sdim 325263508Sdim/* shorthand one */ 326263508Sdim#define BGE_ASICREV(x) ((x) >> 12) 327263508Sdim#define BGE_ASICREV_BCM5701 0x00 328263508Sdim#define BGE_ASICREV_BCM5703 0x01 329263508Sdim#define BGE_ASICREV_BCM5704 0x02 330263508Sdim#define BGE_ASICREV_BCM5705 0x03 331263508Sdim#define BGE_ASICREV_BCM5750 0x04 332263508Sdim#define BGE_ASICREV_BCM5714_A0 0x05 333263508Sdim#define BGE_ASICREV_BCM5752 0x06 334263508Sdim#define BGE_ASICREV_BCM5700 0x07 335263508Sdim#define BGE_ASICREV_BCM5780 0x08 336263508Sdim#define BGE_ASICREV_BCM5714 0x09 337249259Sdim#define BGE_ASICREV_BCM5755 0x0a 338249259Sdim#define BGE_ASICREV_BCM5754 0x0b 339249259Sdim#define BGE_ASICREV_BCM5787 0x0b 340251662Sdim#define BGE_ASICREV_BCM5906 0x0c 341251662Sdim/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 342251662Sdim#define BGE_ASICREV_USE_PRODID_REG 0x0f 343251662Sdim/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 344251662Sdim#define BGE_ASICREV_BCM5717 0x5717 345251662Sdim#define BGE_ASICREV_BCM5761 0x5761 346251662Sdim#define BGE_ASICREV_BCM5784 0x5784 347251662Sdim#define BGE_ASICREV_BCM5785 0x5785 348251662Sdim#define BGE_ASICREV_BCM57765 0x57785 349251662Sdim#define BGE_ASICREV_BCM57780 0x57780 350251662Sdim 351251662Sdim/* chip revisions */ 352249259Sdim#define BGE_CHIPREV(x) ((x) >> 8) 353251662Sdim#define BGE_CHIPREV_5700_AX 0x70 354251662Sdim#define BGE_CHIPREV_5700_BX 0x71 355251662Sdim#define BGE_CHIPREV_5700_CX 0x72 356251662Sdim#define BGE_CHIPREV_5701_AX 0x00 357251662Sdim#define BGE_CHIPREV_5703_AX 0x10 358251662Sdim#define BGE_CHIPREV_5704_AX 0x20 359249259Sdim#define BGE_CHIPREV_5704_BX 0x21 360249259Sdim#define BGE_CHIPREV_5750_AX 0x40 361251662Sdim#define BGE_CHIPREV_5750_BX 0x41 362251662Sdim/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 363251662Sdim#define BGE_CHIPREV_5717_AX 0x57170 364251662Sdim#define BGE_CHIPREV_5717_BX 0x57171 365251662Sdim#define BGE_CHIPREV_5761_AX 0x57611 366251662Sdim#define BGE_CHIPREV_5784_AX 0x57841 367249259Sdim 368249259Sdim/* PCI DMA Read/Write Control register */ 369249259Sdim#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 370249259Sdim#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 371249259Sdim#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 372249259Sdim#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 373249259Sdim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 374249259Sdim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 375249259Sdim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 376249259Sdim#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 377249259Sdim#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 378249259Sdim#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 379249259Sdim#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 380249259Sdim#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 381249259Sdim#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 382249259Sdim 383249259Sdim#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 384249259Sdim#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 385249259Sdim#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 386249259Sdim#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 387249259Sdim 388249259Sdim#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 389249259Sdim 390249259Sdim#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 391249259Sdim#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 392249259Sdim#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 393249259Sdim#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 394249259Sdim#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 395249259Sdim#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 396249259Sdim#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 397249259Sdim#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 398249259Sdim 399249259Sdim#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 400249259Sdim#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 401249259Sdim#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 402249259Sdim#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 403249259Sdim#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 404249259Sdim#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 405249259Sdim#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 406249259Sdim#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 407249259Sdim 408249259Sdim/* 409249259Sdim * PCI state register -- note, this register is read only 410249259Sdim * unless the PCISTATE_WR bit of the PCI Misc. Host Control 411249259Sdim * register is set. 412249259Sdim */ 413249259Sdim#define BGE_PCISTATE_FORCE_RESET 0x00000001 414249259Sdim#define BGE_PCISTATE_INTR_STATE 0x00000002 415249259Sdim#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 416249259Sdim#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 417249259Sdim#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 418249259Sdim#define BGE_PCISTATE_WANT_EXPROM 0x00000020 419249259Sdim#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 420249259Sdim#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 421249259Sdim#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 422249259Sdim 423249259Sdim/* 424249259Sdim * PCI Clock Control register -- note, this register is read only 425249259Sdim * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 426249259Sdim * register is set. 427249259Sdim */ 428249259Sdim#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 429249259Sdim#define BGE_PCICLOCKCTL_M66EN 0x00000080 430249259Sdim#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 431249259Sdim#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 432249259Sdim#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 433249259Sdim#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 434249259Sdim#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 435249259Sdim#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 436249259Sdim#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 437249259Sdim#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 438249259Sdim 439249259Sdim 440249259Sdim#ifndef PCIM_CMD_MWIEN 441249259Sdim#define PCIM_CMD_MWIEN 0x0010 442249259Sdim#endif 443249259Sdim#ifndef PCIM_CMD_INTxDIS 444249259Sdim#define PCIM_CMD_INTxDIS 0x0400 445249259Sdim#endif 446263508Sdim 447249259Sdim/* 448249259Sdim * High priority mailbox registers 449249259Sdim * Each mailbox is 64-bits wide, though we only use the 450249259Sdim * lower 32 bits. To write a 64-bit value, write the upper 32 bits 451249259Sdim * first. The NIC will load the mailbox after the lower 32 bit word 452249259Sdim * has been updated. 453249259Sdim */ 454249259Sdim#define BGE_MBX_IRQ0_HI 0x0200 455249259Sdim#define BGE_MBX_IRQ0_LO 0x0204 456249259Sdim#define BGE_MBX_IRQ1_HI 0x0208 457249259Sdim#define BGE_MBX_IRQ1_LO 0x020C 458249259Sdim#define BGE_MBX_IRQ2_HI 0x0210 459249259Sdim#define BGE_MBX_IRQ2_LO 0x0214 460249259Sdim#define BGE_MBX_IRQ3_HI 0x0218 461249259Sdim#define BGE_MBX_IRQ3_LO 0x021C 462249259Sdim#define BGE_MBX_GEN0_HI 0x0220 463249259Sdim#define BGE_MBX_GEN0_LO 0x0224 464249259Sdim#define BGE_MBX_GEN1_HI 0x0228 465249259Sdim#define BGE_MBX_GEN1_LO 0x022C 466249259Sdim#define BGE_MBX_GEN2_HI 0x0230 467249259Sdim#define BGE_MBX_GEN2_LO 0x0234 468249259Sdim#define BGE_MBX_GEN3_HI 0x0228 469249259Sdim#define BGE_MBX_GEN3_LO 0x022C 470249259Sdim#define BGE_MBX_GEN4_HI 0x0240 471249259Sdim#define BGE_MBX_GEN4_LO 0x0244 472249259Sdim#define BGE_MBX_GEN5_HI 0x0248 473249259Sdim#define BGE_MBX_GEN5_LO 0x024C 474249259Sdim#define BGE_MBX_GEN6_HI 0x0250 475249259Sdim#define BGE_MBX_GEN6_LO 0x0254 476249259Sdim#define BGE_MBX_GEN7_HI 0x0258 477249259Sdim#define BGE_MBX_GEN7_LO 0x025C 478249259Sdim#define BGE_MBX_RELOAD_STATS_HI 0x0260 479249259Sdim#define BGE_MBX_RELOAD_STATS_LO 0x0264 480249259Sdim#define BGE_MBX_RX_STD_PROD_HI 0x0268 481#define BGE_MBX_RX_STD_PROD_LO 0x026C 482#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 483#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 484#define BGE_MBX_RX_MINI_PROD_HI 0x0278 485#define BGE_MBX_RX_MINI_PROD_LO 0x027C 486#define BGE_MBX_RX_CONS0_HI 0x0280 487#define BGE_MBX_RX_CONS0_LO 0x0284 488#define BGE_MBX_RX_CONS1_HI 0x0288 489#define BGE_MBX_RX_CONS1_LO 0x028C 490#define BGE_MBX_RX_CONS2_HI 0x0290 491#define BGE_MBX_RX_CONS2_LO 0x0294 492#define BGE_MBX_RX_CONS3_HI 0x0298 493#define BGE_MBX_RX_CONS3_LO 0x029C 494#define BGE_MBX_RX_CONS4_HI 0x02A0 495#define BGE_MBX_RX_CONS4_LO 0x02A4 496#define BGE_MBX_RX_CONS5_HI 0x02A8 497#define BGE_MBX_RX_CONS5_LO 0x02AC 498#define BGE_MBX_RX_CONS6_HI 0x02B0 499#define BGE_MBX_RX_CONS6_LO 0x02B4 500#define BGE_MBX_RX_CONS7_HI 0x02B8 501#define BGE_MBX_RX_CONS7_LO 0x02BC 502#define BGE_MBX_RX_CONS8_HI 0x02C0 503#define BGE_MBX_RX_CONS8_LO 0x02C4 504#define BGE_MBX_RX_CONS9_HI 0x02C8 505#define BGE_MBX_RX_CONS9_LO 0x02CC 506#define BGE_MBX_RX_CONS10_HI 0x02D0 507#define BGE_MBX_RX_CONS10_LO 0x02D4 508#define BGE_MBX_RX_CONS11_HI 0x02D8 509#define BGE_MBX_RX_CONS11_LO 0x02DC 510#define BGE_MBX_RX_CONS12_HI 0x02E0 511#define BGE_MBX_RX_CONS12_LO 0x02E4 512#define BGE_MBX_RX_CONS13_HI 0x02E8 513#define BGE_MBX_RX_CONS13_LO 0x02EC 514#define BGE_MBX_RX_CONS14_HI 0x02F0 515#define BGE_MBX_RX_CONS14_LO 0x02F4 516#define BGE_MBX_RX_CONS15_HI 0x02F8 517#define BGE_MBX_RX_CONS15_LO 0x02FC 518#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 519#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 520#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 521#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 522#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 523#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 524#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 525#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 526#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 527#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 528#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 529#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 530#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 531#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 532#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 533#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 534#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 535#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 536#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 537#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 538#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 539#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 540#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 541#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 542#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 543#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 544#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 545#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 546#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 547#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 548#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 549#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 550#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 551#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 552#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 553#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 554#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 555#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 556#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 557#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 558#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 559#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 560#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 561#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 562#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 563#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 564#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 565#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 566#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 567#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 568#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 569#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 570#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 571#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 572#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 573#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 574#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 575#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 576#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 577#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 578#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 579#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 580#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 581#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 582 583#define BGE_TX_RINGS_MAX 4 584#define BGE_TX_RINGS_EXTSSRAM_MAX 16 585#define BGE_RX_RINGS_MAX 16 586#define BGE_RX_RINGS_MAX_5717 17 587 588/* Ethernet MAC control registers */ 589#define BGE_MAC_MODE 0x0400 590#define BGE_MAC_STS 0x0404 591#define BGE_MAC_EVT_ENB 0x0408 592#define BGE_MAC_LED_CTL 0x040C 593#define BGE_MAC_ADDR1_LO 0x0410 594#define BGE_MAC_ADDR1_HI 0x0414 595#define BGE_MAC_ADDR2_LO 0x0418 596#define BGE_MAC_ADDR2_HI 0x041C 597#define BGE_MAC_ADDR3_LO 0x0420 598#define BGE_MAC_ADDR3_HI 0x0424 599#define BGE_MAC_ADDR4_LO 0x0428 600#define BGE_MAC_ADDR4_HI 0x042C 601#define BGE_WOL_PATPTR 0x0430 602#define BGE_WOL_PATCFG 0x0434 603#define BGE_TX_RANDOM_BACKOFF 0x0438 604#define BGE_RX_MTU 0x043C 605#define BGE_GBIT_PCS_TEST 0x0440 606#define BGE_TX_TBI_AUTONEG 0x0444 607#define BGE_RX_TBI_AUTONEG 0x0448 608#define BGE_MI_COMM 0x044C 609#define BGE_MI_STS 0x0450 610#define BGE_MI_MODE 0x0454 611#define BGE_AUTOPOLL_STS 0x0458 612#define BGE_TX_MODE 0x045C 613#define BGE_TX_STS 0x0460 614#define BGE_TX_LENGTHS 0x0464 615#define BGE_RX_MODE 0x0468 616#define BGE_RX_STS 0x046C 617#define BGE_MAR0 0x0470 618#define BGE_MAR1 0x0474 619#define BGE_MAR2 0x0478 620#define BGE_MAR3 0x047C 621#define BGE_RX_BD_RULES_CTL0 0x0480 622#define BGE_RX_BD_RULES_MASKVAL0 0x0484 623#define BGE_RX_BD_RULES_CTL1 0x0488 624#define BGE_RX_BD_RULES_MASKVAL1 0x048C 625#define BGE_RX_BD_RULES_CTL2 0x0490 626#define BGE_RX_BD_RULES_MASKVAL2 0x0494 627#define BGE_RX_BD_RULES_CTL3 0x0498 628#define BGE_RX_BD_RULES_MASKVAL3 0x049C 629#define BGE_RX_BD_RULES_CTL4 0x04A0 630#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 631#define BGE_RX_BD_RULES_CTL5 0x04A8 632#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 633#define BGE_RX_BD_RULES_CTL6 0x04B0 634#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 635#define BGE_RX_BD_RULES_CTL7 0x04B8 636#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 637#define BGE_RX_BD_RULES_CTL8 0x04C0 638#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 639#define BGE_RX_BD_RULES_CTL9 0x04C8 640#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 641#define BGE_RX_BD_RULES_CTL10 0x04D0 642#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 643#define BGE_RX_BD_RULES_CTL11 0x04D8 644#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 645#define BGE_RX_BD_RULES_CTL12 0x04E0 646#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 647#define BGE_RX_BD_RULES_CTL13 0x04E8 648#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 649#define BGE_RX_BD_RULES_CTL14 0x04F0 650#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 651#define BGE_RX_BD_RULES_CTL15 0x04F8 652#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 653#define BGE_RX_RULES_CFG 0x0500 654#define BGE_MAX_RX_FRAME_LOWAT 0x0504 655#define BGE_SERDES_CFG 0x0590 656#define BGE_SERDES_STS 0x0594 657#define BGE_SGDIG_CFG 0x05B0 658#define BGE_SGDIG_STS 0x05B4 659#define BGE_TX_MAC_STATS_OCTETS 0x0800 660#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 661#define BGE_TX_MAC_STATS_COLLS 0x0808 662#define BGE_TX_MAC_STATS_XON_SENT 0x080C 663#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 664#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 665#define BGE_TX_MAC_STATS_ERRORS 0x0818 666#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 667#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 668#define BGE_TX_MAC_STATS_DEFERRED 0x0824 669#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 670#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 671#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 672#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 673#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 674#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 675#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 676#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 677#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 678#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 679#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 680#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 681#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 682#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 683#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 684#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 685#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 686#define BGE_TX_MAC_STATS_UCAST 0x086C 687#define BGE_TX_MAC_STATS_MCAST 0x0870 688#define BGE_TX_MAC_STATS_BCAST 0x0874 689#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 690#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 691#define BGE_RX_MAC_STATS_OCTESTS 0x0880 692#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 693#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 694#define BGE_RX_MAC_STATS_UCAST 0x088C 695#define BGE_RX_MAC_STATS_MCAST 0x0890 696#define BGE_RX_MAC_STATS_BCAST 0x0894 697#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 698#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 699#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 700#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 701#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 702#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 703#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 704#define BGE_RX_MAC_STATS_JABBERS 0x08B4 705#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 706 707/* Ethernet MAC Mode register */ 708#define BGE_MACMODE_RESET 0x00000001 709#define BGE_MACMODE_HALF_DUPLEX 0x00000002 710#define BGE_MACMODE_PORTMODE 0x0000000C 711#define BGE_MACMODE_LOOPBACK 0x00000010 712#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 713#define BGE_MACMODE_TX_BURST_ENB 0x00000100 714#define BGE_MACMODE_MAX_DEFER 0x00000200 715#define BGE_MACMODE_LINK_POLARITY 0x00000400 716#define BGE_MACMODE_RX_STATS_ENB 0x00000800 717#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 718#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 719#define BGE_MACMODE_TX_STATS_ENB 0x00004000 720#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 721#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 722#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 723#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 724#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 725#define BGE_MACMODE_MIP_ENB 0x00100000 726#define BGE_MACMODE_TXDMA_ENB 0x00200000 727#define BGE_MACMODE_RXDMA_ENB 0x00400000 728#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 729 730#define BGE_PORTMODE_NONE 0x00000000 731#define BGE_PORTMODE_MII 0x00000004 732#define BGE_PORTMODE_GMII 0x00000008 733#define BGE_PORTMODE_TBI 0x0000000C 734 735/* MAC Status register */ 736#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 737#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 738#define BGE_MACSTAT_RX_CFG 0x00000004 739#define BGE_MACSTAT_CFG_CHANGED 0x00000008 740#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 741#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 742#define BGE_MACSTAT_LINK_CHANGED 0x00001000 743#define BGE_MACSTAT_MI_COMPLETE 0x00400000 744#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 745#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 746#define BGE_MACSTAT_ODI_ERROR 0x02000000 747#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 748#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 749 750/* MAC Event Enable Register */ 751#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 752#define BGE_EVTENB_LINK_CHANGED 0x00001000 753#define BGE_EVTENB_MI_COMPLETE 0x00400000 754#define BGE_EVTENB_MI_INTERRUPT 0x00800000 755#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 756#define BGE_EVTENB_ODI_ERROR 0x02000000 757#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 758#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 759 760/* LED Control Register */ 761#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 762#define BGE_LEDCTL_1000MBPS_LED 0x00000002 763#define BGE_LEDCTL_100MBPS_LED 0x00000004 764#define BGE_LEDCTL_10MBPS_LED 0x00000008 765#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 766#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 767#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 768#define BGE_LEDCTL_1000MBPS_STS 0x00000080 769#define BGE_LEDCTL_100MBPS_STS 0x00000100 770#define BGE_LEDCTL_10MBPS_STS 0x00000200 771#define BGE_LEDCTL_TRADLED_STS 0x00000400 772#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 773#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 774 775/* TX backoff seed register */ 776#define BGE_TX_BACKOFF_SEED_MASK 0x3F 777 778/* Autopoll status register */ 779#define BGE_AUTOPOLLSTS_ERROR 0x00000001 780 781/* Transmit MAC mode register */ 782#define BGE_TXMODE_RESET 0x00000001 783#define BGE_TXMODE_ENABLE 0x00000002 784#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 785#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 786#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 787#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 788 789/* Transmit MAC status register */ 790#define BGE_TXSTAT_RX_XOFFED 0x00000001 791#define BGE_TXSTAT_SENT_XOFF 0x00000002 792#define BGE_TXSTAT_SENT_XON 0x00000004 793#define BGE_TXSTAT_LINK_UP 0x00000008 794#define BGE_TXSTAT_ODI_UFLOW 0x00000010 795#define BGE_TXSTAT_ODI_OFLOW 0x00000020 796 797/* Transmit MAC lengths register */ 798#define BGE_TXLEN_SLOTTIME 0x000000FF 799#define BGE_TXLEN_IPG 0x00000F00 800#define BGE_TXLEN_CRS 0x00003000 801 802/* Receive MAC mode register */ 803#define BGE_RXMODE_RESET 0x00000001 804#define BGE_RXMODE_ENABLE 0x00000002 805#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 806#define BGE_RXMODE_RX_GIANTS 0x00000020 807#define BGE_RXMODE_RX_RUNTS 0x00000040 808#define BGE_RXMODE_8022_LENCHECK 0x00000080 809#define BGE_RXMODE_RX_PROMISC 0x00000100 810#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 811#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 812 813/* Receive MAC status register */ 814#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 815#define BGE_RXSTAT_RCVD_XOFF 0x00000002 816#define BGE_RXSTAT_RCVD_XON 0x00000004 817 818/* Receive Rules Control register */ 819#define BGE_RXRULECTL_OFFSET 0x000000FF 820#define BGE_RXRULECTL_CLASS 0x00001F00 821#define BGE_RXRULECTL_HDRTYPE 0x0000E000 822#define BGE_RXRULECTL_COMPARE_OP 0x00030000 823#define BGE_RXRULECTL_MAP 0x01000000 824#define BGE_RXRULECTL_DISCARD 0x02000000 825#define BGE_RXRULECTL_MASK 0x04000000 826#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 827#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 828#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 829#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 830 831/* Receive Rules Mask register */ 832#define BGE_RXRULEMASK_VALUE 0x0000FFFF 833#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 834 835/* SERDES configuration register */ 836#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 837#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 838#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 839#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 840#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 841#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 842#define BGE_SERDESCFG_TXMODE 0x00001000 843#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 844#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 845#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 846#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 847#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 848#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 849#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 850#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 851#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 852 853/* SERDES status register */ 854#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 855#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 856 857/* SGDIG config (not documented) */ 858#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 859#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 860#define BGE_SGDIGCFG_SEND 0x40000000 861#define BGE_SGDIGCFG_AUTO 0x80000000 862 863/* SGDIG status (not documented) */ 864#define BGE_SGDIGSTS_DONE 0x00000002 865#define BGE_SGDIGSTS_IS_SERDES 0x00000100 866#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 867#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 868 869 870/* MI communication register */ 871#define BGE_MICOMM_DATA 0x0000FFFF 872#define BGE_MICOMM_REG 0x001F0000 873#define BGE_MICOMM_PHY 0x03E00000 874#define BGE_MICOMM_CMD 0x0C000000 875#define BGE_MICOMM_READFAIL 0x10000000 876#define BGE_MICOMM_BUSY 0x20000000 877 878#define BGE_MIREG(x) ((x & 0x1F) << 16) 879#define BGE_MIPHY(x) ((x & 0x1F) << 21) 880#define BGE_MICMD_WRITE 0x04000000 881#define BGE_MICMD_READ 0x08000000 882 883/* MI status register */ 884#define BGE_MISTS_LINK 0x00000001 885#define BGE_MISTS_10MBPS 0x00000002 886 887#define BGE_MIMODE_CLK_10MHZ 0x00000001 888#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 889#define BGE_MIMODE_AUTOPOLL 0x00000010 890#define BGE_MIMODE_CLKCNT 0x001F0000 891#define BGE_MIMODE_500KHZ_CONST 0x00008000 892#define BGE_MIMODE_BASE 0x000C0000 893 894 895/* 896 * Send data initiator control registers. 897 */ 898#define BGE_SDI_MODE 0x0C00 899#define BGE_SDI_STATUS 0x0C04 900#define BGE_SDI_STATS_CTL 0x0C08 901#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 902#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 903#define BGE_ISO_PKT_TX 0x0C20 904#define BGE_LOCSTATS_COS0 0x0C80 905#define BGE_LOCSTATS_COS1 0x0C84 906#define BGE_LOCSTATS_COS2 0x0C88 907#define BGE_LOCSTATS_COS3 0x0C8C 908#define BGE_LOCSTATS_COS4 0x0C90 909#define BGE_LOCSTATS_COS5 0x0C84 910#define BGE_LOCSTATS_COS6 0x0C98 911#define BGE_LOCSTATS_COS7 0x0C9C 912#define BGE_LOCSTATS_COS8 0x0CA0 913#define BGE_LOCSTATS_COS9 0x0CA4 914#define BGE_LOCSTATS_COS10 0x0CA8 915#define BGE_LOCSTATS_COS11 0x0CAC 916#define BGE_LOCSTATS_COS12 0x0CB0 917#define BGE_LOCSTATS_COS13 0x0CB4 918#define BGE_LOCSTATS_COS14 0x0CB8 919#define BGE_LOCSTATS_COS15 0x0CBC 920#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 921#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 922#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 923#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 924#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 925#define BGE_LOCSTATS_IRQS 0x0CD4 926#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 927#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 928 929/* Send Data Initiator mode register */ 930#define BGE_SDIMODE_RESET 0x00000001 931#define BGE_SDIMODE_ENABLE 0x00000002 932#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 933#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 934 935/* Send Data Initiator stats register */ 936#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 937 938/* Send Data Initiator stats control register */ 939#define BGE_SDISTATSCTL_ENABLE 0x00000001 940#define BGE_SDISTATSCTL_FASTER 0x00000002 941#define BGE_SDISTATSCTL_CLEAR 0x00000004 942#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 943#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 944 945/* 946 * Send Data Completion Control registers 947 */ 948#define BGE_SDC_MODE 0x1000 949#define BGE_SDC_STATUS 0x1004 950 951/* Send Data completion mode register */ 952#define BGE_SDCMODE_RESET 0x00000001 953#define BGE_SDCMODE_ENABLE 0x00000002 954#define BGE_SDCMODE_ATTN 0x00000004 955#define BGE_SDCMODE_CDELAY 0x00000010 956 957/* Send Data completion status register */ 958#define BGE_SDCSTAT_ATTN 0x00000004 959 960/* 961 * Send BD Ring Selector Control registers 962 */ 963#define BGE_SRS_MODE 0x1400 964#define BGE_SRS_STATUS 0x1404 965#define BGE_SRS_HWDIAG 0x1408 966#define BGE_SRS_LOC_NIC_CONS0 0x1440 967#define BGE_SRS_LOC_NIC_CONS1 0x1444 968#define BGE_SRS_LOC_NIC_CONS2 0x1448 969#define BGE_SRS_LOC_NIC_CONS3 0x144C 970#define BGE_SRS_LOC_NIC_CONS4 0x1450 971#define BGE_SRS_LOC_NIC_CONS5 0x1454 972#define BGE_SRS_LOC_NIC_CONS6 0x1458 973#define BGE_SRS_LOC_NIC_CONS7 0x145C 974#define BGE_SRS_LOC_NIC_CONS8 0x1460 975#define BGE_SRS_LOC_NIC_CONS9 0x1464 976#define BGE_SRS_LOC_NIC_CONS10 0x1468 977#define BGE_SRS_LOC_NIC_CONS11 0x146C 978#define BGE_SRS_LOC_NIC_CONS12 0x1470 979#define BGE_SRS_LOC_NIC_CONS13 0x1474 980#define BGE_SRS_LOC_NIC_CONS14 0x1478 981#define BGE_SRS_LOC_NIC_CONS15 0x147C 982 983/* Send BD Ring Selector Mode register */ 984#define BGE_SRSMODE_RESET 0x00000001 985#define BGE_SRSMODE_ENABLE 0x00000002 986#define BGE_SRSMODE_ATTN 0x00000004 987 988/* Send BD Ring Selector Status register */ 989#define BGE_SRSSTAT_ERROR 0x00000004 990 991/* Send BD Ring Selector HW Diagnostics register */ 992#define BGE_SRSHWDIAG_STATE 0x0000000F 993#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 994#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 995#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 996 997/* 998 * Send BD Initiator Selector Control registers 999 */ 1000#define BGE_SBDI_MODE 0x1800 1001#define BGE_SBDI_STATUS 0x1804 1002#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1003#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1004#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1005#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1006#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1007#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1008#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1009#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1010#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1011#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1012#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1013#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1014#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1015#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1016#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1017#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1018 1019/* Send BD Initiator Mode register */ 1020#define BGE_SBDIMODE_RESET 0x00000001 1021#define BGE_SBDIMODE_ENABLE 0x00000002 1022#define BGE_SBDIMODE_ATTN 0x00000004 1023 1024/* Send BD Initiator Status register */ 1025#define BGE_SBDISTAT_ERROR 0x00000004 1026 1027/* 1028 * Send BD Completion Control registers 1029 */ 1030#define BGE_SBDC_MODE 0x1C00 1031#define BGE_SBDC_STATUS 0x1C04 1032 1033/* Send BD Completion Control Mode register */ 1034#define BGE_SBDCMODE_RESET 0x00000001 1035#define BGE_SBDCMODE_ENABLE 0x00000002 1036#define BGE_SBDCMODE_ATTN 0x00000004 1037 1038/* Send BD Completion Control Status register */ 1039#define BGE_SBDCSTAT_ATTN 0x00000004 1040 1041/* 1042 * Receive List Placement Control registers 1043 */ 1044#define BGE_RXLP_MODE 0x2000 1045#define BGE_RXLP_STATUS 0x2004 1046#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1047#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1048#define BGE_RXLP_CFG 0x2010 1049#define BGE_RXLP_STATS_CTL 0x2014 1050#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1051#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1052#define BGE_RXLP_HEAD0 0x2100 1053#define BGE_RXLP_TAIL0 0x2104 1054#define BGE_RXLP_COUNT0 0x2108 1055#define BGE_RXLP_HEAD1 0x2110 1056#define BGE_RXLP_TAIL1 0x2114 1057#define BGE_RXLP_COUNT1 0x2118 1058#define BGE_RXLP_HEAD2 0x2120 1059#define BGE_RXLP_TAIL2 0x2124 1060#define BGE_RXLP_COUNT2 0x2128 1061#define BGE_RXLP_HEAD3 0x2130 1062#define BGE_RXLP_TAIL3 0x2134 1063#define BGE_RXLP_COUNT3 0x2138 1064#define BGE_RXLP_HEAD4 0x2140 1065#define BGE_RXLP_TAIL4 0x2144 1066#define BGE_RXLP_COUNT4 0x2148 1067#define BGE_RXLP_HEAD5 0x2150 1068#define BGE_RXLP_TAIL5 0x2154 1069#define BGE_RXLP_COUNT5 0x2158 1070#define BGE_RXLP_HEAD6 0x2160 1071#define BGE_RXLP_TAIL6 0x2164 1072#define BGE_RXLP_COUNT6 0x2168 1073#define BGE_RXLP_HEAD7 0x2170 1074#define BGE_RXLP_TAIL7 0x2174 1075#define BGE_RXLP_COUNT7 0x2178 1076#define BGE_RXLP_HEAD8 0x2180 1077#define BGE_RXLP_TAIL8 0x2184 1078#define BGE_RXLP_COUNT8 0x2188 1079#define BGE_RXLP_HEAD9 0x2190 1080#define BGE_RXLP_TAIL9 0x2194 1081#define BGE_RXLP_COUNT9 0x2198 1082#define BGE_RXLP_HEAD10 0x21A0 1083#define BGE_RXLP_TAIL10 0x21A4 1084#define BGE_RXLP_COUNT10 0x21A8 1085#define BGE_RXLP_HEAD11 0x21B0 1086#define BGE_RXLP_TAIL11 0x21B4 1087#define BGE_RXLP_COUNT11 0x21B8 1088#define BGE_RXLP_HEAD12 0x21C0 1089#define BGE_RXLP_TAIL12 0x21C4 1090#define BGE_RXLP_COUNT12 0x21C8 1091#define BGE_RXLP_HEAD13 0x21D0 1092#define BGE_RXLP_TAIL13 0x21D4 1093#define BGE_RXLP_COUNT13 0x21D8 1094#define BGE_RXLP_HEAD14 0x21E0 1095#define BGE_RXLP_TAIL14 0x21E4 1096#define BGE_RXLP_COUNT14 0x21E8 1097#define BGE_RXLP_HEAD15 0x21F0 1098#define BGE_RXLP_TAIL15 0x21F4 1099#define BGE_RXLP_COUNT15 0x21F8 1100#define BGE_RXLP_LOCSTAT_COS0 0x2200 1101#define BGE_RXLP_LOCSTAT_COS1 0x2204 1102#define BGE_RXLP_LOCSTAT_COS2 0x2208 1103#define BGE_RXLP_LOCSTAT_COS3 0x220C 1104#define BGE_RXLP_LOCSTAT_COS4 0x2210 1105#define BGE_RXLP_LOCSTAT_COS5 0x2214 1106#define BGE_RXLP_LOCSTAT_COS6 0x2218 1107#define BGE_RXLP_LOCSTAT_COS7 0x221C 1108#define BGE_RXLP_LOCSTAT_COS8 0x2220 1109#define BGE_RXLP_LOCSTAT_COS9 0x2224 1110#define BGE_RXLP_LOCSTAT_COS10 0x2228 1111#define BGE_RXLP_LOCSTAT_COS11 0x222C 1112#define BGE_RXLP_LOCSTAT_COS12 0x2230 1113#define BGE_RXLP_LOCSTAT_COS13 0x2234 1114#define BGE_RXLP_LOCSTAT_COS14 0x2238 1115#define BGE_RXLP_LOCSTAT_COS15 0x223C 1116#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1117#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1118#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1119#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1120#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1121#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1122#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1123 1124 1125/* Receive List Placement mode register */ 1126#define BGE_RXLPMODE_RESET 0x00000001 1127#define BGE_RXLPMODE_ENABLE 0x00000002 1128#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1129#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1130#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1131 1132/* Receive List Placement Status register */ 1133#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1134#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1135#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1136 1137/* 1138 * Receive Data and Receive BD Initiator Control Registers 1139 */ 1140#define BGE_RDBDI_MODE 0x2400 1141#define BGE_RDBDI_STATUS 0x2404 1142#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1143#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1144#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1145#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1146#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1147#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1148#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1149#define BGE_RX_STD_RCB_NICADDR 0x245C 1150#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1151#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1152#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1153#define BGE_RX_MINI_RCB_NICADDR 0x246C 1154#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1155#define BGE_RDBDI_STD_RX_CONS 0x2474 1156#define BGE_RDBDI_MINI_RX_CONS 0x2478 1157#define BGE_RDBDI_RETURN_PROD0 0x2480 1158#define BGE_RDBDI_RETURN_PROD1 0x2484 1159#define BGE_RDBDI_RETURN_PROD2 0x2488 1160#define BGE_RDBDI_RETURN_PROD3 0x248C 1161#define BGE_RDBDI_RETURN_PROD4 0x2490 1162#define BGE_RDBDI_RETURN_PROD5 0x2494 1163#define BGE_RDBDI_RETURN_PROD6 0x2498 1164#define BGE_RDBDI_RETURN_PROD7 0x249C 1165#define BGE_RDBDI_RETURN_PROD8 0x24A0 1166#define BGE_RDBDI_RETURN_PROD9 0x24A4 1167#define BGE_RDBDI_RETURN_PROD10 0x24A8 1168#define BGE_RDBDI_RETURN_PROD11 0x24AC 1169#define BGE_RDBDI_RETURN_PROD12 0x24B0 1170#define BGE_RDBDI_RETURN_PROD13 0x24B4 1171#define BGE_RDBDI_RETURN_PROD14 0x24B8 1172#define BGE_RDBDI_RETURN_PROD15 0x24BC 1173#define BGE_RDBDI_HWDIAG 0x24C0 1174 1175 1176/* Receive Data and Receive BD Initiator Mode register */ 1177#define BGE_RDBDIMODE_RESET 0x00000001 1178#define BGE_RDBDIMODE_ENABLE 0x00000002 1179#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1180#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1181#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1182 1183/* Receive Data and Receive BD Initiator Status register */ 1184#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1185#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1186#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1187 1188 1189/* 1190 * Receive Data Completion Control registers 1191 */ 1192#define BGE_RDC_MODE 0x2800 1193 1194/* Receive Data Completion Mode register */ 1195#define BGE_RDCMODE_RESET 0x00000001 1196#define BGE_RDCMODE_ENABLE 0x00000002 1197#define BGE_RDCMODE_ATTN 0x00000004 1198 1199/* 1200 * Receive BD Initiator Control registers 1201 */ 1202#define BGE_RBDI_MODE 0x2C00 1203#define BGE_RBDI_STATUS 0x2C04 1204#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1205#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1206#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1207#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1208#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1209#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1210 1211#define BGE_STD_REPLENISH_LWM 0x2D00 1212#define BGE_JMB_REPLENISH_LWM 0x2D04 1213 1214/* Receive BD Initiator Mode register */ 1215#define BGE_RBDIMODE_RESET 0x00000001 1216#define BGE_RBDIMODE_ENABLE 0x00000002 1217#define BGE_RBDIMODE_ATTN 0x00000004 1218 1219/* Receive BD Initiator Status register */ 1220#define BGE_RBDISTAT_ATTN 0x00000004 1221 1222/* 1223 * Receive BD Completion Control registers 1224 */ 1225#define BGE_RBDC_MODE 0x3000 1226#define BGE_RBDC_STATUS 0x3004 1227#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1228#define BGE_RBDC_STD_BD_PROD 0x300C 1229#define BGE_RBDC_MINI_BD_PROD 0x3010 1230 1231/* Receive BD completion mode register */ 1232#define BGE_RBDCMODE_RESET 0x00000001 1233#define BGE_RBDCMODE_ENABLE 0x00000002 1234#define BGE_RBDCMODE_ATTN 0x00000004 1235 1236/* Receive BD completion status register */ 1237#define BGE_RBDCSTAT_ERROR 0x00000004 1238 1239/* 1240 * Receive List Selector Control registers 1241 */ 1242#define BGE_RXLS_MODE 0x3400 1243#define BGE_RXLS_STATUS 0x3404 1244 1245/* Receive List Selector Mode register */ 1246#define BGE_RXLSMODE_RESET 0x00000001 1247#define BGE_RXLSMODE_ENABLE 0x00000002 1248#define BGE_RXLSMODE_ATTN 0x00000004 1249 1250/* Receive List Selector Status register */ 1251#define BGE_RXLSSTAT_ERROR 0x00000004 1252 1253#define BGE_CPMU_CTRL 0x3600 1254#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1255#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1256#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1257#define BGE_CPMU_HST_ACC 0x361C 1258#define BGE_CPMU_CLCK_STAT 0x3630 1259#define BGE_CPMU_MUTEX_REQ 0x365C 1260#define BGE_CPMU_MUTEX_GNT 0x3660 1261#define BGE_CPMU_PHY_STRAP 0x3664 1262 1263/* Central Power Management Unit (CPMU) register */ 1264#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1265#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1266#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1267#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1268 1269/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1270#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1271#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1272 1273/* Link Speed 1000MB Power Mode Clock Policy register */ 1274#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1275#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1276#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1277 1278/* Link Aware Power Mode Clock Policy register */ 1279#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1280#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1281 1282#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1283#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1284 1285/* CPMU Clock Status register */ 1286#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1287#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1288#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1289#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1290 1291/* CPMU Mutex Request register */ 1292#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1293#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1294 1295/* CPMU GPHY Strap register */ 1296#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1297 1298/* 1299 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1300 */ 1301#define BGE_MBCF_MODE 0x3800 1302#define BGE_MBCF_STATUS 0x3804 1303 1304/* Mbuf Cluster Free mode register */ 1305#define BGE_MBCFMODE_RESET 0x00000001 1306#define BGE_MBCFMODE_ENABLE 0x00000002 1307#define BGE_MBCFMODE_ATTN 0x00000004 1308 1309/* Mbuf Cluster Free status register */ 1310#define BGE_MBCFSTAT_ERROR 0x00000004 1311 1312/* 1313 * Host Coalescing Control registers 1314 */ 1315#define BGE_HCC_MODE 0x3C00 1316#define BGE_HCC_STATUS 0x3C04 1317#define BGE_HCC_RX_COAL_TICKS 0x3C08 1318#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1319#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1320#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1321#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1322#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1323#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1324#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1325#define BGE_HCC_STATS_TICKS 0x3C28 1326#define BGE_HCC_STATS_ADDR_HI 0x3C30 1327#define BGE_HCC_STATS_ADDR_LO 0x3C34 1328#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1329#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1330#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1331#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1332#define BGE_FLOW_ATTN 0x3C48 1333#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1334#define BGE_HCC_STD_BD_CONS 0x3C54 1335#define BGE_HCC_MINI_BD_CONS 0x3C58 1336#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1337#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1338#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1339#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1340#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1341#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1342#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1343#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1344#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1345#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1346#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1347#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1348#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1349#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1350#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1351#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1352#define BGE_HCC_TX_BD_CONS0 0x3CC0 1353#define BGE_HCC_TX_BD_CONS1 0x3CC4 1354#define BGE_HCC_TX_BD_CONS2 0x3CC8 1355#define BGE_HCC_TX_BD_CONS3 0x3CCC 1356#define BGE_HCC_TX_BD_CONS4 0x3CD0 1357#define BGE_HCC_TX_BD_CONS5 0x3CD4 1358#define BGE_HCC_TX_BD_CONS6 0x3CD8 1359#define BGE_HCC_TX_BD_CONS7 0x3CDC 1360#define BGE_HCC_TX_BD_CONS8 0x3CE0 1361#define BGE_HCC_TX_BD_CONS9 0x3CE4 1362#define BGE_HCC_TX_BD_CONS10 0x3CE8 1363#define BGE_HCC_TX_BD_CONS11 0x3CEC 1364#define BGE_HCC_TX_BD_CONS12 0x3CF0 1365#define BGE_HCC_TX_BD_CONS13 0x3CF4 1366#define BGE_HCC_TX_BD_CONS14 0x3CF8 1367#define BGE_HCC_TX_BD_CONS15 0x3CFC 1368 1369 1370/* Host coalescing mode register */ 1371#define BGE_HCCMODE_RESET 0x00000001 1372#define BGE_HCCMODE_ENABLE 0x00000002 1373#define BGE_HCCMODE_ATTN 0x00000004 1374#define BGE_HCCMODE_COAL_NOW 0x00000008 1375#define BGE_HCCMODE_MSI_BITS 0x00000070 1376#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1377 1378#define BGE_STATBLKSZ_FULL 0x00000000 1379#define BGE_STATBLKSZ_64BYTE 0x00000080 1380#define BGE_STATBLKSZ_32BYTE 0x00000100 1381 1382/* Host coalescing status register */ 1383#define BGE_HCCSTAT_ERROR 0x00000004 1384 1385/* Flow attention register */ 1386#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1387#define BGE_FLOWATTN_MEMARB 0x00000080 1388#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1389#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1390#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1391#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1392#define BGE_FLOWATTN_RDBDI 0x00080000 1393#define BGE_FLOWATTN_RXLS 0x00100000 1394#define BGE_FLOWATTN_RXLP 0x00200000 1395#define BGE_FLOWATTN_RBDC 0x00400000 1396#define BGE_FLOWATTN_RBDI 0x00800000 1397#define BGE_FLOWATTN_SDC 0x08000000 1398#define BGE_FLOWATTN_SDI 0x10000000 1399#define BGE_FLOWATTN_SRS 0x20000000 1400#define BGE_FLOWATTN_SBDC 0x40000000 1401#define BGE_FLOWATTN_SBDI 0x80000000 1402 1403/* 1404 * Memory arbiter registers 1405 */ 1406#define BGE_MARB_MODE 0x4000 1407#define BGE_MARB_STATUS 0x4004 1408#define BGE_MARB_TRAPADDR_HI 0x4008 1409#define BGE_MARB_TRAPADDR_LO 0x400C 1410 1411/* Memory arbiter mode register */ 1412#define BGE_MARBMODE_RESET 0x00000001 1413#define BGE_MARBMODE_ENABLE 0x00000002 1414#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1415#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1416#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1417#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1418#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1419#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1420#define BGE_MARBMODE_PCI_TRAP 0x00000100 1421#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1422#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1423#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1424#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1425#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1426#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1427#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1428#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1429#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1430#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1431#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1432#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1433#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1434#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1435#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1436#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1437#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1438 1439/* Memory arbiter status register */ 1440#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1441#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1442#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1443#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1444#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1445#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1446#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1447#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1448#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1449#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1450#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1451#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1452#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1453#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1454#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1455#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1456#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1457#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1458#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1459#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1460#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1461#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1462#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1463#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1464 1465/* 1466 * Buffer manager control registers 1467 */ 1468#define BGE_BMAN_MODE 0x4400 1469#define BGE_BMAN_STATUS 0x4404 1470#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1471#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1472#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1473#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1474#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1475#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1476#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1477#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1478#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1479#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1480#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1481#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1482#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1483#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1484#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1485#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1486#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1487#define BGE_BMAN_HWDIAG_1 0x444C 1488#define BGE_BMAN_HWDIAG_2 0x4450 1489#define BGE_BMAN_HWDIAG_3 0x4454 1490 1491/* Buffer manager mode register */ 1492#define BGE_BMANMODE_RESET 0x00000001 1493#define BGE_BMANMODE_ENABLE 0x00000002 1494#define BGE_BMANMODE_ATTN 0x00000004 1495#define BGE_BMANMODE_TESTMODE 0x00000008 1496#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1497 1498/* Buffer manager status register */ 1499#define BGE_BMANSTAT_ERRO 0x00000004 1500#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1501 1502 1503/* 1504 * Read DMA Control registers 1505 */ 1506#define BGE_RDMA_MODE 0x4800 1507#define BGE_RDMA_STATUS 0x4804 1508#define BGE_RDMA_RSRVCTRL 0x4900 1509 1510/* Read DMA mode register */ 1511#define BGE_RDMAMODE_RESET 0x00000001 1512#define BGE_RDMAMODE_ENABLE 0x00000002 1513#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1514#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1515#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1516#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1517#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1518#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1519#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1520#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1521#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1522#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1523#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1524#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1525#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1526#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1527#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1528#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1529#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1530 1531/* Read DMA status register */ 1532#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1533#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1534#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1535#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1536#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1537#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1538#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1539#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1540 1541/* Read DMA Reserved Control register */ 1542#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1543 1544/* 1545 * Write DMA control registers 1546 */ 1547#define BGE_WDMA_MODE 0x4C00 1548#define BGE_WDMA_STATUS 0x4C04 1549 1550/* Write DMA mode register */ 1551#define BGE_WDMAMODE_RESET 0x00000001 1552#define BGE_WDMAMODE_ENABLE 0x00000002 1553#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1554#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1555#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1556#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1557#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1558#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1559#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1560#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1561#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1562#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1563#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1564 1565/* Write DMA status register */ 1566#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1567#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1568#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1569#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1570#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1571#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1572#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1573#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1574 1575 1576/* 1577 * RX CPU registers 1578 */ 1579#define BGE_RXCPU_MODE 0x5000 1580#define BGE_RXCPU_STATUS 0x5004 1581#define BGE_RXCPU_PC 0x501C 1582 1583/* RX CPU mode register */ 1584#define BGE_RXCPUMODE_RESET 0x00000001 1585#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1586#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1587#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1588#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1589#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1590#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1591#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1592#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1593#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1594#define BGE_RXCPUMODE_HALTCPU 0x00000400 1595#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1596#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1597#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1598 1599/* RX CPU status register */ 1600#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1601#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1602#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1603#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1604#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1605#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1606#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1607#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1608#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1609#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1610#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1611#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1612#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1613#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1614#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1615#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1616#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1617 1618/* 1619 * V? CPU registers 1620 */ 1621#define BGE_VCPU_STATUS 0x5100 1622#define BGE_VCPU_EXT_CTRL 0x6890 1623 1624#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1625#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1626 1627#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1628#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1629 1630/* 1631 * TX CPU registers 1632 */ 1633#define BGE_TXCPU_MODE 0x5400 1634#define BGE_TXCPU_STATUS 0x5404 1635#define BGE_TXCPU_PC 0x541C 1636 1637/* TX CPU mode register */ 1638#define BGE_TXCPUMODE_RESET 0x00000001 1639#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1640#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1641#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1642#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1643#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1644#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1645#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1646#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1647#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1648#define BGE_TXCPUMODE_HALTCPU 0x00000400 1649#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1650#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1651 1652/* TX CPU status register */ 1653#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1654#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1655#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1656#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1657#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1658#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1659#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1660#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1661#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1662#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1663#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1664#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1665#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1666#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1667#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1668#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1669#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1670 1671 1672/* 1673 * Low priority mailbox registers 1674 */ 1675#define BGE_LPMBX_IRQ0_HI 0x5800 1676#define BGE_LPMBX_IRQ0_LO 0x5804 1677#define BGE_LPMBX_IRQ1_HI 0x5808 1678#define BGE_LPMBX_IRQ1_LO 0x580C 1679#define BGE_LPMBX_IRQ2_HI 0x5810 1680#define BGE_LPMBX_IRQ2_LO 0x5814 1681#define BGE_LPMBX_IRQ3_HI 0x5818 1682#define BGE_LPMBX_IRQ3_LO 0x581C 1683#define BGE_LPMBX_GEN0_HI 0x5820 1684#define BGE_LPMBX_GEN0_LO 0x5824 1685#define BGE_LPMBX_GEN1_HI 0x5828 1686#define BGE_LPMBX_GEN1_LO 0x582C 1687#define BGE_LPMBX_GEN2_HI 0x5830 1688#define BGE_LPMBX_GEN2_LO 0x5834 1689#define BGE_LPMBX_GEN3_HI 0x5828 1690#define BGE_LPMBX_GEN3_LO 0x582C 1691#define BGE_LPMBX_GEN4_HI 0x5840 1692#define BGE_LPMBX_GEN4_LO 0x5844 1693#define BGE_LPMBX_GEN5_HI 0x5848 1694#define BGE_LPMBX_GEN5_LO 0x584C 1695#define BGE_LPMBX_GEN6_HI 0x5850 1696#define BGE_LPMBX_GEN6_LO 0x5854 1697#define BGE_LPMBX_GEN7_HI 0x5858 1698#define BGE_LPMBX_GEN7_LO 0x585C 1699#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1700#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1701#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1702#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1703#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1704#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1705#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1706#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1707#define BGE_LPMBX_RX_CONS0_HI 0x5880 1708#define BGE_LPMBX_RX_CONS0_LO 0x5884 1709#define BGE_LPMBX_RX_CONS1_HI 0x5888 1710#define BGE_LPMBX_RX_CONS1_LO 0x588C 1711#define BGE_LPMBX_RX_CONS2_HI 0x5890 1712#define BGE_LPMBX_RX_CONS2_LO 0x5894 1713#define BGE_LPMBX_RX_CONS3_HI 0x5898 1714#define BGE_LPMBX_RX_CONS3_LO 0x589C 1715#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1716#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1717#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1718#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1719#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1720#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1721#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1722#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1723#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1724#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1725#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1726#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1727#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1728#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1729#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1730#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1731#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1732#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1733#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1734#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1735#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1736#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1737#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1738#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1739#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1740#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1741#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1742#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1743#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1744#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1745#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1746#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1747#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1748#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1749#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1750#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1751#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1752#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1753#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1754#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1755#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1756#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1757#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1758#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1759#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1760#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1761#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1762#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1763#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1764#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1765#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1766#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1767#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1768#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1769#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1770#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1771#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1772#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1773#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1774#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1775#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1776#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1777#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1778#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1779#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1780#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1781#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1782#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1783#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1784#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1785#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1786#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1787#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1788#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1789#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1790#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1791#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1792#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1793#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1794#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1795#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1796#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1797#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1798#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1799#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1800#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1801#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1802#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1803 1804/* 1805 * Flow throw Queue reset register 1806 */ 1807#define BGE_FTQ_RESET 0x5C00 1808 1809#define BGE_FTQRESET_DMAREAD 0x00000002 1810#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1811#define BGE_FTQRESET_DMADONE 0x00000010 1812#define BGE_FTQRESET_SBDC 0x00000020 1813#define BGE_FTQRESET_SDI 0x00000040 1814#define BGE_FTQRESET_WDMA 0x00000080 1815#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1816#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1817#define BGE_FTQRESET_SDC 0x00000400 1818#define BGE_FTQRESET_HCC 0x00000800 1819#define BGE_FTQRESET_TXFIFO 0x00001000 1820#define BGE_FTQRESET_MBC 0x00002000 1821#define BGE_FTQRESET_RBDC 0x00004000 1822#define BGE_FTQRESET_RXLP 0x00008000 1823#define BGE_FTQRESET_RDBDI 0x00010000 1824#define BGE_FTQRESET_RDC 0x00020000 1825#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1826 1827/* 1828 * Message Signaled Interrupt registers 1829 */ 1830#define BGE_MSI_MODE 0x6000 1831#define BGE_MSI_STATUS 0x6004 1832#define BGE_MSI_FIFOACCESS 0x6008 1833 1834/* MSI mode register */ 1835#define BGE_MSIMODE_RESET 0x00000001 1836#define BGE_MSIMODE_ENABLE 0x00000002 1837#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1838#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1839 1840/* MSI status register */ 1841#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1842#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1843#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1844#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1845#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1846 1847 1848/* 1849 * DMA Completion registers 1850 */ 1851#define BGE_DMAC_MODE 0x6400 1852 1853/* DMA Completion mode register */ 1854#define BGE_DMACMODE_RESET 0x00000001 1855#define BGE_DMACMODE_ENABLE 0x00000002 1856 1857 1858/* 1859 * General control registers. 1860 */ 1861#define BGE_MODE_CTL 0x6800 1862#define BGE_MISC_CFG 0x6804 1863#define BGE_MISC_LOCAL_CTL 0x6808 1864#define BGE_CPU_EVENT 0x6810 1865#define BGE_EE_ADDR 0x6838 1866#define BGE_EE_DATA 0x683C 1867#define BGE_EE_CTL 0x6840 1868#define BGE_MDI_CTL 0x6844 1869#define BGE_EE_DELAY 0x6848 1870#define BGE_FASTBOOT_PC 0x6894 1871 1872/* 1873 * NVRAM Control registers 1874 */ 1875#define BGE_NVRAM_CMD 0x7000 1876#define BGE_NVRAM_STAT 0x7004 1877#define BGE_NVRAM_WRDATA 0x7008 1878#define BGE_NVRAM_ADDR 0x700c 1879#define BGE_NVRAM_RDDATA 0x7010 1880#define BGE_NVRAM_CFG1 0x7014 1881#define BGE_NVRAM_CFG2 0x7018 1882#define BGE_NVRAM_CFG3 0x701c 1883#define BGE_NVRAM_SWARB 0x7020 1884#define BGE_NVRAM_ACCESS 0x7024 1885#define BGE_NVRAM_WRITE1 0x7028 1886 1887#define BGE_NVRAMCMD_RESET 0x00000001 1888#define BGE_NVRAMCMD_DONE 0x00000008 1889#define BGE_NVRAMCMD_START 0x00000010 1890#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1891#define BGE_NVRAMCMD_ERASE 0x00000040 1892#define BGE_NVRAMCMD_FIRST 0x00000080 1893#define BGE_NVRAMCMD_LAST 0x00000100 1894 1895#define BGE_NVRAM_READCMD \ 1896 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1897 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1898#define BGE_NVRAM_WRITECMD \ 1899 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1900 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1901 1902#define BGE_NVRAMSWARB_SET0 0x00000001 1903#define BGE_NVRAMSWARB_SET1 0x00000002 1904#define BGE_NVRAMSWARB_SET2 0x00000003 1905#define BGE_NVRAMSWARB_SET3 0x00000004 1906#define BGE_NVRAMSWARB_CLR0 0x00000010 1907#define BGE_NVRAMSWARB_CLR1 0x00000020 1908#define BGE_NVRAMSWARB_CLR2 0x00000040 1909#define BGE_NVRAMSWARB_CLR3 0x00000080 1910#define BGE_NVRAMSWARB_GNT0 0x00000100 1911#define BGE_NVRAMSWARB_GNT1 0x00000200 1912#define BGE_NVRAMSWARB_GNT2 0x00000400 1913#define BGE_NVRAMSWARB_GNT3 0x00000800 1914#define BGE_NVRAMSWARB_REQ0 0x00001000 1915#define BGE_NVRAMSWARB_REQ1 0x00002000 1916#define BGE_NVRAMSWARB_REQ2 0x00004000 1917#define BGE_NVRAMSWARB_REQ3 0x00008000 1918 1919#define BGE_NVRAMACC_ENABLE 0x00000001 1920#define BGE_NVRAMACC_WRENABLE 0x00000002 1921 1922/* Mode control register */ 1923#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1924#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1925#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1926#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1927#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1928#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1929#define BGE_MODECTL_NO_RX_CRC 0x00000400 1930#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1931#define BGE_MODECTL_NO_TX_INTR 0x00002000 1932#define BGE_MODECTL_NO_RX_INTR 0x00004000 1933#define BGE_MODECTL_FORCE_PCI32 0x00008000 1934#define BGE_MODECTL_STACKUP 0x00010000 1935#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1936#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1937#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1938#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1939#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1940#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1941#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1942#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1943#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1944#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1945 1946/* Misc. config register */ 1947#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1948#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1949#define BGE_MISCCFG_BOARD_ID 0x0001E000 1950#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1951#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1952#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1953#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1954 1955#define BGE_32BITTIME_66MHZ (0x41 << 1) 1956 1957/* Misc. Local Control */ 1958#define BGE_MLC_INTR_STATE 0x00000001 1959#define BGE_MLC_INTR_CLR 0x00000002 1960#define BGE_MLC_INTR_SET 0x00000004 1961#define BGE_MLC_INTR_ONATTN 0x00000008 1962#define BGE_MLC_MISCIO_IN0 0x00000100 1963#define BGE_MLC_MISCIO_IN1 0x00000200 1964#define BGE_MLC_MISCIO_IN2 0x00000400 1965#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1966#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1967#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1968#define BGE_MLC_MISCIO_OUT0 0x00004000 1969#define BGE_MLC_MISCIO_OUT1 0x00008000 1970#define BGE_MLC_MISCIO_OUT2 0x00010000 1971#define BGE_MLC_EXTRAM_ENB 0x00020000 1972#define BGE_MLC_SRAM_SIZE 0x001C0000 1973#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1974#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1975#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1976#define BGE_MLC_AUTO_EEPROM 0x01000000 1977 1978#define BGE_SSRAMSIZE_256KB 0x00000000 1979#define BGE_SSRAMSIZE_512KB 0x00040000 1980#define BGE_SSRAMSIZE_1MB 0x00080000 1981#define BGE_SSRAMSIZE_2MB 0x000C0000 1982#define BGE_SSRAMSIZE_4MB 0x00100000 1983#define BGE_SSRAMSIZE_8MB 0x00140000 1984#define BGE_SSRAMSIZE_16M 0x00180000 1985 1986/* EEPROM address register */ 1987#define BGE_EEADDR_ADDRESS 0x0000FFFC 1988#define BGE_EEADDR_HALFCLK 0x01FF0000 1989#define BGE_EEADDR_START 0x02000000 1990#define BGE_EEADDR_DEVID 0x1C000000 1991#define BGE_EEADDR_RESET 0x20000000 1992#define BGE_EEADDR_DONE 0x40000000 1993#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1994 1995#define BGE_EEDEVID(x) ((x & 7) << 26) 1996#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1997#define BGE_HALFCLK_384SCL 0x60 1998#define BGE_EE_READCMD \ 1999 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2000 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2001#define BGE_EE_WRCMD \ 2002 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2003 BGE_EEADDR_START|BGE_EEADDR_DONE) 2004 2005/* EEPROM Control register */ 2006#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2007#define BGE_EECTL_CLKOUT 0x00000002 2008#define BGE_EECTL_CLKIN 0x00000004 2009#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2010#define BGE_EECTL_DATAOUT 0x00000010 2011#define BGE_EECTL_DATAIN 0x00000020 2012 2013/* MDI (MII/GMII) access register */ 2014#define BGE_MDI_DATA 0x00000001 2015#define BGE_MDI_DIR 0x00000002 2016#define BGE_MDI_SEL 0x00000004 2017#define BGE_MDI_CLK 0x00000008 2018 2019#define BGE_MEMWIN_START 0x00008000 2020#define BGE_MEMWIN_END 0x0000FFFF 2021 2022 2023#define BGE_MEMWIN_READ(sc, x, val) \ 2024 do { \ 2025 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2026 (0xFFFF0000 & x), 4); \ 2027 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2028 } while(0) 2029 2030#define BGE_MEMWIN_WRITE(sc, x, val) \ 2031 do { \ 2032 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2033 (0xFFFF0000 & x), 4); \ 2034 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2035 } while(0) 2036 2037/* 2038 * This magic number is written to the firmware mailbox at 0xb50 2039 * before a software reset is issued. After the internal firmware 2040 * has completed its initialization it will write the opposite of 2041 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2042 * driver to synchronize with the firmware. 2043 */ 2044#define BGE_MAGIC_NUMBER 0x4B657654 2045 2046typedef struct { 2047 uint32_t bge_addr_hi; 2048 uint32_t bge_addr_lo; 2049} bge_hostaddr; 2050 2051#define BGE_HOSTADDR(x, y) \ 2052 do { \ 2053 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2054 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2055 } while(0) 2056 2057#define BGE_ADDR_LO(y) \ 2058 ((uint64_t) (y) & 0xFFFFFFFF) 2059#define BGE_ADDR_HI(y) \ 2060 ((uint64_t) (y) >> 32) 2061 2062/* Ring control block structure */ 2063struct bge_rcb { 2064 bge_hostaddr bge_hostaddr; 2065 uint32_t bge_maxlen_flags; 2066 uint32_t bge_nicaddr; 2067}; 2068 2069#define RCB_WRITE_4(sc, rcb, offset, val) \ 2070 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2071#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2072 2073#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2074#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2075 2076struct bge_tx_bd { 2077 bge_hostaddr bge_addr; 2078#if BYTE_ORDER == LITTLE_ENDIAN 2079 uint16_t bge_flags; 2080 uint16_t bge_len; 2081 uint16_t bge_vlan_tag; 2082 uint16_t bge_mss; 2083#else 2084 uint16_t bge_len; 2085 uint16_t bge_flags; 2086 uint16_t bge_mss; 2087 uint16_t bge_vlan_tag; 2088#endif 2089}; 2090 2091#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2092#define BGE_TXBDFLAG_IP_CSUM 0x0002 2093#define BGE_TXBDFLAG_END 0x0004 2094#define BGE_TXBDFLAG_IP_FRAG 0x0008 2095#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2096#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2097#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2098#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2099#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2100#define BGE_TXBDFLAG_COAL_NOW 0x0080 2101#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2102#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2103#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2104#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2105#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2106#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2107#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2108#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2109#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2110#define BGE_TXBDFLAG_NO_CRC 0x8000 2111 2112#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2113/* Bits [1:0] of the MSS header length. */ 2114#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2115 2116#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2117 BGE_SEND_RING_1_TO_4 + \ 2118 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2119 2120struct bge_rx_bd { 2121 bge_hostaddr bge_addr; 2122#if BYTE_ORDER == LITTLE_ENDIAN 2123 uint16_t bge_len; 2124 uint16_t bge_idx; 2125 uint16_t bge_flags; 2126 uint16_t bge_type; 2127 uint16_t bge_tcp_udp_csum; 2128 uint16_t bge_ip_csum; 2129 uint16_t bge_vlan_tag; 2130 uint16_t bge_error_flag; 2131#else 2132 uint16_t bge_idx; 2133 uint16_t bge_len; 2134 uint16_t bge_type; 2135 uint16_t bge_flags; 2136 uint16_t bge_ip_csum; 2137 uint16_t bge_tcp_udp_csum; 2138 uint16_t bge_error_flag; 2139 uint16_t bge_vlan_tag; 2140#endif 2141 uint32_t bge_rsvd; 2142 uint32_t bge_opaque; 2143}; 2144 2145struct bge_extrx_bd { 2146 bge_hostaddr bge_addr1; 2147 bge_hostaddr bge_addr2; 2148 bge_hostaddr bge_addr3; 2149#if BYTE_ORDER == LITTLE_ENDIAN 2150 uint16_t bge_len2; 2151 uint16_t bge_len1; 2152 uint16_t bge_rsvd1; 2153 uint16_t bge_len3; 2154#else 2155 uint16_t bge_len1; 2156 uint16_t bge_len2; 2157 uint16_t bge_len3; 2158 uint16_t bge_rsvd1; 2159#endif 2160 bge_hostaddr bge_addr0; 2161#if BYTE_ORDER == LITTLE_ENDIAN 2162 uint16_t bge_len0; 2163 uint16_t bge_idx; 2164 uint16_t bge_flags; 2165 uint16_t bge_type; 2166 uint16_t bge_tcp_udp_csum; 2167 uint16_t bge_ip_csum; 2168 uint16_t bge_vlan_tag; 2169 uint16_t bge_error_flag; 2170#else 2171 uint16_t bge_idx; 2172 uint16_t bge_len0; 2173 uint16_t bge_type; 2174 uint16_t bge_flags; 2175 uint16_t bge_ip_csum; 2176 uint16_t bge_tcp_udp_csum; 2177 uint16_t bge_error_flag; 2178 uint16_t bge_vlan_tag; 2179#endif 2180 uint32_t bge_rsvd0; 2181 uint32_t bge_opaque; 2182}; 2183 2184#define BGE_RXBDFLAG_END 0x0004 2185#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2186#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2187#define BGE_RXBDFLAG_ERROR 0x0400 2188#define BGE_RXBDFLAG_MINI_RING 0x0800 2189#define BGE_RXBDFLAG_IP_CSUM 0x1000 2190#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2191#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2192#define BGE_RXBDFLAG_IPV6 0x8000 2193 2194#define BGE_RXERRFLAG_BAD_CRC 0x0001 2195#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2196#define BGE_RXERRFLAG_LINK_LOST 0x0004 2197#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2198#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2199#define BGE_RXERRFLAG_RUNT 0x0020 2200#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2201#define BGE_RXERRFLAG_GIANT 0x0080 2202#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2203 2204struct bge_sts_idx { 2205#if BYTE_ORDER == LITTLE_ENDIAN 2206 uint16_t bge_rx_prod_idx; 2207 uint16_t bge_tx_cons_idx; 2208#else 2209 uint16_t bge_tx_cons_idx; 2210 uint16_t bge_rx_prod_idx; 2211#endif 2212}; 2213 2214struct bge_status_block { 2215 uint32_t bge_status; 2216 uint32_t bge_status_tag; 2217#if BYTE_ORDER == LITTLE_ENDIAN 2218 uint16_t bge_rx_jumbo_cons_idx; 2219 uint16_t bge_rx_std_cons_idx; 2220 uint16_t bge_rx_mini_cons_idx; 2221 uint16_t bge_rsvd1; 2222#else 2223 uint16_t bge_rx_std_cons_idx; 2224 uint16_t bge_rx_jumbo_cons_idx; 2225 uint16_t bge_rsvd1; 2226 uint16_t bge_rx_mini_cons_idx; 2227#endif 2228 struct bge_sts_idx bge_idx[16]; 2229}; 2230 2231#define BGE_STATFLAG_UPDATED 0x00000001 2232#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2233#define BGE_STATFLAG_ERROR 0x00000004 2234 2235 2236/* 2237 * Broadcom Vendor ID 2238 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2239 * even though they're now manufactured by Broadcom) 2240 */ 2241#define BCOM_VENDORID 0x14E4 2242#define BCOM_DEVICEID_BCM5700 0x1644 2243#define BCOM_DEVICEID_BCM5701 0x1645 2244#define BCOM_DEVICEID_BCM5702 0x1646 2245#define BCOM_DEVICEID_BCM5702X 0x16A6 2246#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2247#define BCOM_DEVICEID_BCM5703 0x1647 2248#define BCOM_DEVICEID_BCM5703X 0x16A7 2249#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2250#define BCOM_DEVICEID_BCM5704C 0x1648 2251#define BCOM_DEVICEID_BCM5704S 0x16A8 2252#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2253#define BCOM_DEVICEID_BCM5705 0x1653 2254#define BCOM_DEVICEID_BCM5705K 0x1654 2255#define BCOM_DEVICEID_BCM5705F 0x166E 2256#define BCOM_DEVICEID_BCM5705M 0x165D 2257#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2258#define BCOM_DEVICEID_BCM5714C 0x1668 2259#define BCOM_DEVICEID_BCM5714S 0x1669 2260#define BCOM_DEVICEID_BCM5715 0x1678 2261#define BCOM_DEVICEID_BCM5715S 0x1679 2262#define BCOM_DEVICEID_BCM5717 0x1655 2263#define BCOM_DEVICEID_BCM5718 0x1656 2264#define BCOM_DEVICEID_BCM5720 0x1658 2265#define BCOM_DEVICEID_BCM5721 0x1659 2266#define BCOM_DEVICEID_BCM5722 0x165A 2267#define BCOM_DEVICEID_BCM5723 0x165B 2268#define BCOM_DEVICEID_BCM5750 0x1676 2269#define BCOM_DEVICEID_BCM5750M 0x167C 2270#define BCOM_DEVICEID_BCM5751 0x1677 2271#define BCOM_DEVICEID_BCM5751F 0x167E 2272#define BCOM_DEVICEID_BCM5751M 0x167D 2273#define BCOM_DEVICEID_BCM5752 0x1600 2274#define BCOM_DEVICEID_BCM5752M 0x1601 2275#define BCOM_DEVICEID_BCM5753 0x16F7 2276#define BCOM_DEVICEID_BCM5753F 0x16FE 2277#define BCOM_DEVICEID_BCM5753M 0x16FD 2278#define BCOM_DEVICEID_BCM5754 0x167A 2279#define BCOM_DEVICEID_BCM5754M 0x1672 2280#define BCOM_DEVICEID_BCM5755 0x167B 2281#define BCOM_DEVICEID_BCM5755M 0x1673 2282#define BCOM_DEVICEID_BCM5756 0x1674 2283#define BCOM_DEVICEID_BCM5761 0x1681 2284#define BCOM_DEVICEID_BCM5761E 0x1680 2285#define BCOM_DEVICEID_BCM5761S 0x1688 2286#define BCOM_DEVICEID_BCM5761SE 0x1689 2287#define BCOM_DEVICEID_BCM5764 0x1684 2288#define BCOM_DEVICEID_BCM5780 0x166A 2289#define BCOM_DEVICEID_BCM5780S 0x166B 2290#define BCOM_DEVICEID_BCM5781 0x16DD 2291#define BCOM_DEVICEID_BCM5782 0x1696 2292#define BCOM_DEVICEID_BCM5784 0x1698 2293#define BCOM_DEVICEID_BCM5785F 0x16a0 2294#define BCOM_DEVICEID_BCM5785G 0x1699 2295#define BCOM_DEVICEID_BCM5786 0x169A 2296#define BCOM_DEVICEID_BCM5787 0x169B 2297#define BCOM_DEVICEID_BCM5787M 0x1693 2298#define BCOM_DEVICEID_BCM5787F 0x167f 2299#define BCOM_DEVICEID_BCM5788 0x169C 2300#define BCOM_DEVICEID_BCM5789 0x169D 2301#define BCOM_DEVICEID_BCM5901 0x170D 2302#define BCOM_DEVICEID_BCM5901A2 0x170E 2303#define BCOM_DEVICEID_BCM5903M 0x16FF 2304#define BCOM_DEVICEID_BCM5906 0x1712 2305#define BCOM_DEVICEID_BCM5906M 0x1713 2306#define BCOM_DEVICEID_BCM57760 0x1690 2307#define BCOM_DEVICEID_BCM57761 0x16B0 2308#define BCOM_DEVICEID_BCM57765 0x16B4 2309#define BCOM_DEVICEID_BCM57780 0x1692 2310#define BCOM_DEVICEID_BCM57781 0x16B1 2311#define BCOM_DEVICEID_BCM57785 0x16B5 2312#define BCOM_DEVICEID_BCM57788 0x1691 2313#define BCOM_DEVICEID_BCM57790 0x1694 2314#define BCOM_DEVICEID_BCM57791 0x16B2 2315#define BCOM_DEVICEID_BCM57795 0x16B6 2316 2317/* 2318 * Alteon AceNIC PCI vendor/device ID. 2319 */ 2320#define ALTEON_VENDORID 0x12AE 2321#define ALTEON_DEVICEID_ACENIC 0x0001 2322#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2323#define ALTEON_DEVICEID_BCM5700 0x0003 2324#define ALTEON_DEVICEID_BCM5701 0x0004 2325 2326/* 2327 * 3Com 3c996 PCI vendor/device ID. 2328 */ 2329#define TC_VENDORID 0x10B7 2330#define TC_DEVICEID_3C996 0x0003 2331 2332/* 2333 * SysKonnect PCI vendor ID 2334 */ 2335#define SK_VENDORID 0x1148 2336#define SK_DEVICEID_ALTIMA 0x4400 2337#define SK_SUBSYSID_9D21 0x4421 2338#define SK_SUBSYSID_9D41 0x4441 2339 2340/* 2341 * Altima PCI vendor/device ID. 2342 */ 2343#define ALTIMA_VENDORID 0x173b 2344#define ALTIMA_DEVICE_AC1000 0x03e8 2345#define ALTIMA_DEVICE_AC1002 0x03e9 2346#define ALTIMA_DEVICE_AC9100 0x03ea 2347 2348/* 2349 * Dell PCI vendor ID 2350 */ 2351 2352#define DELL_VENDORID 0x1028 2353 2354/* 2355 * Apple PCI vendor ID. 2356 */ 2357#define APPLE_VENDORID 0x106b 2358#define APPLE_DEVICE_BCM5701 0x1645 2359 2360/* 2361 * Sun PCI vendor ID 2362 */ 2363#define SUN_VENDORID 0x108e 2364 2365/* 2366 * Fujitsu vendor/device IDs 2367 */ 2368#define FJTSU_VENDORID 0x10cf 2369#define FJTSU_DEVICEID_PW008GE5 0x11a1 2370#define FJTSU_DEVICEID_PW008GE4 0x11a2 2371#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2372 2373/* 2374 * Offset of MAC address inside EEPROM. 2375 */ 2376#define BGE_EE_MAC_OFFSET 0x7C 2377#define BGE_EE_MAC_OFFSET_5906 0x10 2378#define BGE_EE_HWCFG_OFFSET 0xC8 2379 2380#define BGE_HWCFG_VOLTAGE 0x00000003 2381#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2382#define BGE_HWCFG_MEDIA 0x00000030 2383#define BGE_HWCFG_ASF 0x00000080 2384 2385#define BGE_VOLTAGE_1POINT3 0x00000000 2386#define BGE_VOLTAGE_1POINT8 0x00000001 2387 2388#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2389#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2390#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2391 2392#define BGE_MEDIA_UNSPEC 0x00000000 2393#define BGE_MEDIA_COPPER 0x00000010 2394#define BGE_MEDIA_FIBER 0x00000020 2395 2396#define BGE_TICKS_PER_SEC 1000000 2397 2398/* 2399 * Ring size constants. 2400 */ 2401#define BGE_EVENT_RING_CNT 256 2402#define BGE_CMD_RING_CNT 64 2403#define BGE_STD_RX_RING_CNT 512 2404#define BGE_JUMBO_RX_RING_CNT 256 2405#define BGE_MINI_RX_RING_CNT 1024 2406#define BGE_RETURN_RING_CNT 1024 2407 2408/* 5705 has smaller return ring size */ 2409 2410#define BGE_RETURN_RING_CNT_5705 512 2411 2412/* 2413 * Possible TX ring sizes. 2414 */ 2415#define BGE_TX_RING_CNT_128 128 2416#define BGE_TX_RING_BASE_128 0x3800 2417 2418#define BGE_TX_RING_CNT_256 256 2419#define BGE_TX_RING_BASE_256 0x3000 2420 2421#define BGE_TX_RING_CNT_512 512 2422#define BGE_TX_RING_BASE_512 0x2000 2423 2424#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2425#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2426 2427/* 2428 * Tigon III statistics counters. 2429 */ 2430/* Statistics maintained MAC Receive block. */ 2431struct bge_rx_mac_stats { 2432 bge_hostaddr ifHCInOctets; 2433 bge_hostaddr Reserved1; 2434 bge_hostaddr etherStatsFragments; 2435 bge_hostaddr ifHCInUcastPkts; 2436 bge_hostaddr ifHCInMulticastPkts; 2437 bge_hostaddr ifHCInBroadcastPkts; 2438 bge_hostaddr dot3StatsFCSErrors; 2439 bge_hostaddr dot3StatsAlignmentErrors; 2440 bge_hostaddr xonPauseFramesReceived; 2441 bge_hostaddr xoffPauseFramesReceived; 2442 bge_hostaddr macControlFramesReceived; 2443 bge_hostaddr xoffStateEntered; 2444 bge_hostaddr dot3StatsFramesTooLong; 2445 bge_hostaddr etherStatsJabbers; 2446 bge_hostaddr etherStatsUndersizePkts; 2447 bge_hostaddr inRangeLengthError; 2448 bge_hostaddr outRangeLengthError; 2449 bge_hostaddr etherStatsPkts64Octets; 2450 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2451 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2452 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2453 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2454 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2455 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2456 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2457 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2458 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2459}; 2460 2461 2462/* Statistics maintained MAC Transmit block. */ 2463struct bge_tx_mac_stats { 2464 bge_hostaddr ifHCOutOctets; 2465 bge_hostaddr Reserved2; 2466 bge_hostaddr etherStatsCollisions; 2467 bge_hostaddr outXonSent; 2468 bge_hostaddr outXoffSent; 2469 bge_hostaddr flowControlDone; 2470 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2471 bge_hostaddr dot3StatsSingleCollisionFrames; 2472 bge_hostaddr dot3StatsMultipleCollisionFrames; 2473 bge_hostaddr dot3StatsDeferredTransmissions; 2474 bge_hostaddr Reserved3; 2475 bge_hostaddr dot3StatsExcessiveCollisions; 2476 bge_hostaddr dot3StatsLateCollisions; 2477 bge_hostaddr dot3Collided2Times; 2478 bge_hostaddr dot3Collided3Times; 2479 bge_hostaddr dot3Collided4Times; 2480 bge_hostaddr dot3Collided5Times; 2481 bge_hostaddr dot3Collided6Times; 2482 bge_hostaddr dot3Collided7Times; 2483 bge_hostaddr dot3Collided8Times; 2484 bge_hostaddr dot3Collided9Times; 2485 bge_hostaddr dot3Collided10Times; 2486 bge_hostaddr dot3Collided11Times; 2487 bge_hostaddr dot3Collided12Times; 2488 bge_hostaddr dot3Collided13Times; 2489 bge_hostaddr dot3Collided14Times; 2490 bge_hostaddr dot3Collided15Times; 2491 bge_hostaddr ifHCOutUcastPkts; 2492 bge_hostaddr ifHCOutMulticastPkts; 2493 bge_hostaddr ifHCOutBroadcastPkts; 2494 bge_hostaddr dot3StatsCarrierSenseErrors; 2495 bge_hostaddr ifOutDiscards; 2496 bge_hostaddr ifOutErrors; 2497}; 2498 2499/* Stats counters access through registers */ 2500struct bge_mac_stats { 2501 /* TX MAC statistics */ 2502 uint64_t ifHCOutOctets; 2503 uint64_t Reserved0; 2504 uint64_t etherStatsCollisions; 2505 uint64_t outXonSent; 2506 uint64_t outXoffSent; 2507 uint64_t Reserved1; 2508 uint64_t dot3StatsInternalMacTransmitErrors; 2509 uint64_t dot3StatsSingleCollisionFrames; 2510 uint64_t dot3StatsMultipleCollisionFrames; 2511 uint64_t dot3StatsDeferredTransmissions; 2512 uint64_t Reserved2; 2513 uint64_t dot3StatsExcessiveCollisions; 2514 uint64_t dot3StatsLateCollisions; 2515 uint64_t Reserved3[14]; 2516 uint64_t ifHCOutUcastPkts; 2517 uint64_t ifHCOutMulticastPkts; 2518 uint64_t ifHCOutBroadcastPkts; 2519 uint64_t Reserved4[2]; 2520 /* RX MAC statistics */ 2521 uint64_t ifHCInOctets; 2522 uint64_t Reserved5; 2523 uint64_t etherStatsFragments; 2524 uint64_t ifHCInUcastPkts; 2525 uint64_t ifHCInMulticastPkts; 2526 uint64_t ifHCInBroadcastPkts; 2527 uint64_t dot3StatsFCSErrors; 2528 uint64_t dot3StatsAlignmentErrors; 2529 uint64_t xonPauseFramesReceived; 2530 uint64_t xoffPauseFramesReceived; 2531 uint64_t macControlFramesReceived; 2532 uint64_t xoffStateEntered; 2533 uint64_t dot3StatsFramesTooLong; 2534 uint64_t etherStatsJabbers; 2535 uint64_t etherStatsUndersizePkts; 2536 /* Receive List Placement control */ 2537 uint64_t FramesDroppedDueToFilters; 2538 uint64_t DmaWriteQueueFull; 2539 uint64_t DmaWriteHighPriQueueFull; 2540 uint64_t NoMoreRxBDs; 2541 uint64_t InputDiscards; 2542 uint64_t InputErrors; 2543 uint64_t RecvThresholdHit; 2544}; 2545 2546struct bge_stats { 2547 uint8_t Reserved0[256]; 2548 2549 /* Statistics maintained by Receive MAC. */ 2550 struct bge_rx_mac_stats rxstats; 2551 2552 bge_hostaddr Unused1[37]; 2553 2554 /* Statistics maintained by Transmit MAC. */ 2555 struct bge_tx_mac_stats txstats; 2556 2557 bge_hostaddr Unused2[31]; 2558 2559 /* Statistics maintained by Receive List Placement. */ 2560 bge_hostaddr COSIfHCInPkts[16]; 2561 bge_hostaddr COSFramesDroppedDueToFilters; 2562 bge_hostaddr nicDmaWriteQueueFull; 2563 bge_hostaddr nicDmaWriteHighPriQueueFull; 2564 bge_hostaddr nicNoMoreRxBDs; 2565 bge_hostaddr ifInDiscards; 2566 bge_hostaddr ifInErrors; 2567 bge_hostaddr nicRecvThresholdHit; 2568 2569 bge_hostaddr Unused3[9]; 2570 2571 /* Statistics maintained by Send Data Initiator. */ 2572 bge_hostaddr COSIfHCOutPkts[16]; 2573 bge_hostaddr nicDmaReadQueueFull; 2574 bge_hostaddr nicDmaReadHighPriQueueFull; 2575 bge_hostaddr nicSendDataCompQueueFull; 2576 2577 /* Statistics maintained by Host Coalescing. */ 2578 bge_hostaddr nicRingSetSendProdIndex; 2579 bge_hostaddr nicRingStatusUpdate; 2580 bge_hostaddr nicInterrupts; 2581 bge_hostaddr nicAvoidedInterrupts; 2582 bge_hostaddr nicSendThresholdHit; 2583 2584 uint8_t Reserved4[320]; 2585}; 2586 2587/* 2588 * Tigon general information block. This resides in host memory 2589 * and contains the status counters, ring control blocks and 2590 * producer pointers. 2591 */ 2592 2593struct bge_gib { 2594 struct bge_stats bge_stats; 2595 struct bge_rcb bge_tx_rcb[16]; 2596 struct bge_rcb bge_std_rx_rcb; 2597 struct bge_rcb bge_jumbo_rx_rcb; 2598 struct bge_rcb bge_mini_rx_rcb; 2599 struct bge_rcb bge_return_rcb; 2600}; 2601 2602#define BGE_FRAMELEN 1518 2603#define BGE_MAX_FRAMELEN 1536 2604#define BGE_JUMBO_FRAMELEN 9018 2605#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2606#define BGE_MIN_FRAMELEN 60 2607 2608/* 2609 * Other utility macros. 2610 */ 2611#define BGE_INC(x, y) (x) = (x + 1) % y 2612 2613/* 2614 * Register access macros. The Tigon always uses memory mapped register 2615 * accesses and all registers must be accessed with 32 bit operations. 2616 */ 2617 2618#define CSR_WRITE_4(sc, reg, val) \ 2619 bus_write_4(sc->bge_res, reg, val) 2620 2621#define CSR_READ_4(sc, reg) \ 2622 bus_read_4(sc->bge_res, reg) 2623 2624#define BGE_SETBIT(sc, reg, x) \ 2625 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2626#define BGE_CLRBIT(sc, reg, x) \ 2627 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2628 2629#define PCI_SETBIT(dev, reg, x, s) \ 2630 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2631#define PCI_CLRBIT(dev, reg, x, s) \ 2632 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2633 2634/* 2635 * Memory management stuff. 2636 */ 2637 2638#define BGE_NSEG_JUMBO 4 2639#define BGE_NSEG_NEW 32 2640#define BGE_TSOSEG_SZ 4096 2641 2642/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2643#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2644#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2645#else 2646#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2647#endif 2648 2649#ifdef PAE 2650#define BGE_DMA_BNDRY 0x80000000 2651#else 2652#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2653#define BGE_DMA_BNDRY 0x100000000 2654#else 2655#define BGE_DMA_BNDRY 0 2656#endif 2657#endif 2658 2659/* 2660 * Ring structures. Most of these reside in host memory and we tell 2661 * the NIC where they are via the ring control blocks. The exceptions 2662 * are the tx and command rings, which live in NIC memory and which 2663 * we access via the shared memory window. 2664 */ 2665 2666struct bge_ring_data { 2667 struct bge_rx_bd *bge_rx_std_ring; 2668 bus_addr_t bge_rx_std_ring_paddr; 2669 struct bge_extrx_bd *bge_rx_jumbo_ring; 2670 bus_addr_t bge_rx_jumbo_ring_paddr; 2671 struct bge_rx_bd *bge_rx_return_ring; 2672 bus_addr_t bge_rx_return_ring_paddr; 2673 struct bge_tx_bd *bge_tx_ring; 2674 bus_addr_t bge_tx_ring_paddr; 2675 struct bge_status_block *bge_status_block; 2676 bus_addr_t bge_status_block_paddr; 2677 struct bge_stats *bge_stats; 2678 bus_addr_t bge_stats_paddr; 2679 struct bge_gib bge_info; 2680}; 2681 2682#define BGE_STD_RX_RING_SZ \ 2683 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2684#define BGE_JUMBO_RX_RING_SZ \ 2685 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2686#define BGE_TX_RING_SZ \ 2687 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2688#define BGE_RX_RTN_RING_SZ(x) \ 2689 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2690 2691#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2692 2693#define BGE_STATS_SZ sizeof (struct bge_stats) 2694 2695/* 2696 * Mbuf pointers. We need these to keep track of the virtual addresses 2697 * of our mbuf chains since we can only convert from physical to virtual, 2698 * not the other way around. 2699 */ 2700struct bge_chain_data { 2701 bus_dma_tag_t bge_parent_tag; 2702 bus_dma_tag_t bge_buffer_tag; 2703 bus_dma_tag_t bge_rx_std_ring_tag; 2704 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2705 bus_dma_tag_t bge_rx_return_ring_tag; 2706 bus_dma_tag_t bge_tx_ring_tag; 2707 bus_dma_tag_t bge_status_tag; 2708 bus_dma_tag_t bge_stats_tag; 2709 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2710 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2711 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2712 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2713 bus_dmamap_t bge_rx_std_sparemap; 2714 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2715 bus_dmamap_t bge_rx_jumbo_sparemap; 2716 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2717 bus_dmamap_t bge_rx_std_ring_map; 2718 bus_dmamap_t bge_rx_jumbo_ring_map; 2719 bus_dmamap_t bge_tx_ring_map; 2720 bus_dmamap_t bge_rx_return_ring_map; 2721 bus_dmamap_t bge_status_map; 2722 bus_dmamap_t bge_stats_map; 2723 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2724 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2725 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2726 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2727 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2728}; 2729 2730struct bge_dmamap_arg { 2731 bus_addr_t bge_busaddr; 2732}; 2733 2734#define BGE_HWREV_TIGON 0x01 2735#define BGE_HWREV_TIGON_II 0x02 2736#define BGE_TIMEOUT 100000 2737#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2738 2739struct bge_bcom_hack { 2740 int reg; 2741 int val; 2742}; 2743 2744#define ASF_ENABLE 1 2745#define ASF_NEW_HANDSHAKE 2 2746#define ASF_STACKUP 4 2747 2748struct bge_softc { 2749 struct ifnet *bge_ifp; /* interface info */ 2750 device_t bge_dev; 2751 struct mtx bge_mtx; 2752 device_t bge_miibus; 2753 void *bge_intrhand; 2754 struct resource *bge_irq; 2755 struct resource *bge_res; 2756 struct ifmedia bge_ifmedia; /* TBI media info */ 2757 int bge_expcap; 2758 int bge_msicap; 2759 int bge_pcixcap; 2760 uint32_t bge_flags; 2761#define BGE_FLAG_TBI 0x00000001 2762#define BGE_FLAG_JUMBO 0x00000002 2763#define BGE_FLAG_JUMBO_STD 0x00000004 2764#define BGE_FLAG_EADDR 0x00000008 2765#define BGE_FLAG_MII_SERDES 0x00000010 2766#define BGE_FLAG_CPMU_PRESENT 0x00000020 2767#define BGE_FLAG_TAGGED_STATUS 0x00000040 2768#define BGE_FLAG_MSI 0x00000100 2769#define BGE_FLAG_PCIX 0x00000200 2770#define BGE_FLAG_PCIE 0x00000400 2771#define BGE_FLAG_TSO 0x00000800 2772#define BGE_FLAG_TSO3 0x00001000 2773#define BGE_FLAG_JUMBO_FRAME 0x00002000 2774#define BGE_FLAG_5700_FAMILY 0x00010000 2775#define BGE_FLAG_5705_PLUS 0x00020000 2776#define BGE_FLAG_5714_FAMILY 0x00040000 2777#define BGE_FLAG_575X_PLUS 0x00080000 2778#define BGE_FLAG_5755_PLUS 0x00100000 2779#define BGE_FLAG_5788 0x00200000 2780#define BGE_FLAG_5717_PLUS 0x00400000 2781#define BGE_FLAG_40BIT_BUG 0x01000000 2782#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2783#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2784#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2785 uint32_t bge_phy_flags; 2786#define BGE_PHY_WIRESPEED 0x00000001 2787#define BGE_PHY_ADC_BUG 0x00000002 2788#define BGE_PHY_5704_A0_BUG 0x00000004 2789#define BGE_PHY_JITTER_BUG 0x00000008 2790#define BGE_PHY_BER_BUG 0x00000010 2791#define BGE_PHY_ADJUST_TRIM 0x00000020 2792#define BGE_PHY_CRC_BUG 0x00000040 2793#define BGE_PHY_NO_3LED 0x00000080 2794 uint32_t bge_chipid; 2795 uint32_t bge_asicrev; 2796 uint32_t bge_chiprev; 2797 uint8_t bge_asf_mode; 2798 uint8_t bge_asf_count; 2799 struct bge_ring_data bge_ldata; /* rings */ 2800 struct bge_chain_data bge_cdata; /* mbufs */ 2801 uint16_t bge_tx_saved_considx; 2802 uint16_t bge_rx_saved_considx; 2803 uint16_t bge_ev_saved_considx; 2804 uint16_t bge_return_ring_cnt; 2805 uint16_t bge_std; /* current std ring head */ 2806 uint16_t bge_jumbo; /* current jumo ring head */ 2807 uint32_t bge_stat_ticks; 2808 uint32_t bge_rx_coal_ticks; 2809 uint32_t bge_tx_coal_ticks; 2810 uint32_t bge_tx_prodidx; 2811 uint32_t bge_rx_max_coal_bds; 2812 uint32_t bge_tx_max_coal_bds; 2813 uint32_t bge_mi_mode; 2814 int bge_if_flags; 2815 int bge_txcnt; 2816 int bge_link; /* link state */ 2817 int bge_link_evt; /* pending link event */ 2818 int bge_timer; 2819 int bge_forced_collapse; 2820 int bge_forced_udpcsum; 2821 int bge_csum_features; 2822 struct callout bge_stat_ch; 2823 uint32_t bge_rx_discards; 2824 uint32_t bge_tx_discards; 2825 uint32_t bge_tx_collisions; 2826#ifdef DEVICE_POLLING 2827 int rxcycles; 2828#endif /* DEVICE_POLLING */ 2829 struct bge_mac_stats bge_mac_stats; 2830 struct task bge_intr_task; 2831 struct taskqueue *bge_tq; 2832}; 2833 2834#define BGE_LOCK_INIT(_sc, _name) \ 2835 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2836#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2837#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2838#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2839#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2840