if_bgereg.h revision 214251
1238104Sdes/*- 2238104Sdes * Copyright (c) 2001 Wind River Systems 3238104Sdes * Copyright (c) 1997, 1998, 1999, 2001 4238104Sdes * Bill Paul <wpaul@windriver.com>. All rights reserved. 5238104Sdes * 6238104Sdes * Redistribution and use in source and binary forms, with or without 7238104Sdes * modification, are permitted provided that the following conditions 8238104Sdes * are met: 9238104Sdes * 1. Redistributions of source code must retain the above copyright 10238104Sdes * notice, this list of conditions and the following disclaimer. 11238104Sdes * 2. Redistributions in binary form must reproduce the above copyright 12238104Sdes * notice, this list of conditions and the following disclaimer in the 13238104Sdes * documentation and/or other materials provided with the distribution. 14238104Sdes * 3. All advertising materials mentioning features or use of this software 15238104Sdes * must display the following acknowledgement: 16238104Sdes * This product includes software developed by Bill Paul. 17238104Sdes * 4. Neither the name of the author nor the names of any co-contributors 18238104Sdes * may be used to endorse or promote products derived from this software 19238104Sdes * without specific prior written permission. 20238104Sdes * 21238104Sdes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22238104Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23238104Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24238104Sdes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25238104Sdes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26238104Sdes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27238104Sdes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28238104Sdes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29238104Sdes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30238104Sdes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31238104Sdes * THE POSSIBILITY OF SUCH DAMAGE. 32238104Sdes * 33238104Sdes * $FreeBSD: head/sys/dev/bge/if_bgereg.h 214251 2010-10-23 21:25:50Z yongari $ 34238104Sdes */ 35238104Sdes 36238104Sdes/* 37238104Sdes * BCM570x memory map. The internal memory layout varies somewhat 38238104Sdes * depending on whether or not we have external SSRAM attached. 39238104Sdes * The BCM5700 can have up to 16MB of external memory. The BCM5701 40238104Sdes * is apparently not designed to use external SSRAM. The mappings 41238104Sdes * up to the first 4 send rings are the same for both internal and 42238104Sdes * external memory configurations. Note that mini RX ring space is 43238104Sdes * only available with external SSRAM configurations, which means 44238104Sdes * the mini RX ring is not supported on the BCM5701. 45238104Sdes * 46238104Sdes * The NIC's memory can be accessed by the host in one of 3 ways: 47238104Sdes * 48238104Sdes * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49238104Sdes * registers in PCI config space can be used to read any 32-bit 50238104Sdes * address within the NIC's memory. 51238104Sdes * 52238104Sdes * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53238104Sdes * space can be used in conjunction with the memory window in the 54238104Sdes * device register space at offset 0x8000 to read any 32K chunk 55238104Sdes * of NIC memory. 56238104Sdes * 57238104Sdes * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58238104Sdes * set, the device I/O mapping consumes 32MB of host address space, 59238104Sdes * allowing all of the registers and internal NIC memory to be 60238104Sdes * accessed directly. NIC memory addresses are offset by 0x01000000. 61238104Sdes * Flat mode consumes so much host address space that it is not 62238104Sdes * recommended. 63238104Sdes */ 64238104Sdes#define BGE_PAGE_ZERO 0x00000000 65238104Sdes#define BGE_PAGE_ZERO_END 0x000000FF 66238104Sdes#define BGE_SEND_RING_RCB 0x00000100 67238104Sdes#define BGE_SEND_RING_RCB_END 0x000001FF 68238104Sdes#define BGE_RX_RETURN_RING_RCB 0x00000200 69238104Sdes#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70238104Sdes#define BGE_STATS_BLOCK 0x00000300 71238104Sdes#define BGE_STATS_BLOCK_END 0x00000AFF 72238104Sdes#define BGE_STATUS_BLOCK 0x00000B00 73238104Sdes#define BGE_STATUS_BLOCK_END 0x00000B4F 74238104Sdes#define BGE_SOFTWARE_GENCOMM 0x00000B50 75238104Sdes#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76238104Sdes#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77238104Sdes#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78238104Sdes#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79238104Sdes#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80238104Sdes#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81238104Sdes#define BGE_UNMAPPED 0x00001000 82238104Sdes#define BGE_UNMAPPED_END 0x00001FFF 83238104Sdes#define BGE_DMA_DESCRIPTORS 0x00002000 84238104Sdes#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85238104Sdes#define BGE_SEND_RING_1_TO_4 0x00004000 86238104Sdes#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 87238104Sdes 88238104Sdes/* Firmware interface */ 89238104Sdes#define BGE_FW_DRV_ALIVE 0x00000001 90238104Sdes#define BGE_FW_PAUSE 0x00000002 91238104Sdes 92238104Sdes/* Mappings for internal memory configuration */ 93238104Sdes#define BGE_STD_RX_RINGS 0x00006000 94238104Sdes#define BGE_STD_RX_RINGS_END 0x00006FFF 95238104Sdes#define BGE_JUMBO_RX_RINGS 0x00007000 96238104Sdes#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97238104Sdes#define BGE_BUFFPOOL_1 0x00008000 98238104Sdes#define BGE_BUFFPOOL_1_END 0x0000FFFF 99238104Sdes#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 100238104Sdes#define BGE_BUFFPOOL_2_END 0x00017FFF 101238104Sdes#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 102238104Sdes#define BGE_BUFFPOOL_3_END 0x0001FFFF 103238104Sdes 104238104Sdes/* Mappings for external SSRAM configurations */ 105238104Sdes#define BGE_SEND_RING_5_TO_6 0x00006000 106238104Sdes#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107238104Sdes#define BGE_SEND_RING_7_TO_8 0x00007000 108238104Sdes#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109238104Sdes#define BGE_SEND_RING_9_TO_16 0x00008000 110#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111#define BGE_EXT_STD_RX_RINGS 0x0000C000 112#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115#define BGE_MINI_RX_RINGS 0x0000E000 116#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 118#define BGE_AVAIL_REGION1_END 0x00017FFF 119#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 120#define BGE_AVAIL_REGION2_END 0x0001FFFF 121#define BGE_EXT_SSRAM 0x00020000 122#define BGE_EXT_SSRAM_END 0x000FFFFF 123 124 125/* 126 * BCM570x register offsets. These are memory mapped registers 127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 128 * Each register must be accessed using 32 bit operations. 129 * 130 * All registers are accessed through a 32K shared memory block. 131 * The first group of registers are actually copies of the PCI 132 * configuration space registers. 133 */ 134 135/* 136 * PCI registers defined in the PCI 2.2 spec. 137 */ 138#define BGE_PCI_VID 0x00 139#define BGE_PCI_DID 0x02 140#define BGE_PCI_CMD 0x04 141#define BGE_PCI_STS 0x06 142#define BGE_PCI_REV 0x08 143#define BGE_PCI_CLASS 0x09 144#define BGE_PCI_CACHESZ 0x0C 145#define BGE_PCI_LATTIMER 0x0D 146#define BGE_PCI_HDRTYPE 0x0E 147#define BGE_PCI_BIST 0x0F 148#define BGE_PCI_BAR0 0x10 149#define BGE_PCI_BAR1 0x14 150#define BGE_PCI_SUBSYS 0x2C 151#define BGE_PCI_SUBVID 0x2E 152#define BGE_PCI_ROMBASE 0x30 153#define BGE_PCI_CAPPTR 0x34 154#define BGE_PCI_INTLINE 0x3C 155#define BGE_PCI_INTPIN 0x3D 156#define BGE_PCI_MINGNT 0x3E 157#define BGE_PCI_MAXLAT 0x3F 158#define BGE_PCI_PCIXCAP 0x40 159#define BGE_PCI_NEXTPTR_PM 0x41 160#define BGE_PCI_PCIX_CMD 0x42 161#define BGE_PCI_PCIX_STS 0x44 162#define BGE_PCI_PWRMGMT_CAPID 0x48 163#define BGE_PCI_NEXTPTR_VPD 0x49 164#define BGE_PCI_PWRMGMT_CAPS 0x4A 165#define BGE_PCI_PWRMGMT_CMD 0x4C 166#define BGE_PCI_PWRMGMT_STS 0x4D 167#define BGE_PCI_PWRMGMT_DATA 0x4F 168#define BGE_PCI_VPD_CAPID 0x50 169#define BGE_PCI_NEXTPTR_MSI 0x51 170#define BGE_PCI_VPD_ADDR 0x52 171#define BGE_PCI_VPD_DATA 0x54 172#define BGE_PCI_MSI_CAPID 0x58 173#define BGE_PCI_NEXTPTR_NONE 0x59 174#define BGE_PCI_MSI_CTL 0x5A 175#define BGE_PCI_MSI_ADDR_HI 0x5C 176#define BGE_PCI_MSI_ADDR_LO 0x60 177#define BGE_PCI_MSI_DATA 0x64 178 179/* 180 * PCI Express definitions 181 * According to 182 * PCI Express base specification, REV. 1.0a 183 */ 184 185/* PCI Express device control, 16bits */ 186#define BGE_PCIE_DEVCTL 0x08 187#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194 195/* PCI MSI. ??? */ 196#define BGE_PCIE_CAPID_REG 0xD0 197#define BGE_PCIE_CAPID 0x10 198 199/* 200 * PCI registers specific to the BCM570x family. 201 */ 202#define BGE_PCI_MISC_CTL 0x68 203#define BGE_PCI_DMA_RW_CTL 0x6C 204#define BGE_PCI_PCISTATE 0x70 205#define BGE_PCI_CLKCTL 0x74 206#define BGE_PCI_REG_BASEADDR 0x78 207#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208#define BGE_PCI_REG_DATA 0x80 209#define BGE_PCI_MEMWIN_DATA 0x84 210#define BGE_PCI_MODECTL 0x88 211#define BGE_PCI_MISC_CFG 0x8C 212#define BGE_PCI_MISC_LOCALCTL 0x90 213#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219#define BGE_PCI_ISR_MBX_HI 0xB0 220#define BGE_PCI_ISR_MBX_LO 0xB4 221#define BGE_PCI_PRODID_ASICREV 0xBC 222 223/* PCI Misc. Host control register */ 224#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 225#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 226#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 227#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 228#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 229#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 230#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 231#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 232#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 233#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 234 235#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 236#if BYTE_ORDER == LITTLE_ENDIAN 237#define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME| \ 239 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 240#else 241#define BGE_DMA_SWAP_OPTIONS \ 242 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 243 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 244#endif 245 246#define BGE_INIT \ 247 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 248 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 249 250#define BGE_CHIPID_TIGON_I 0x4000 251#define BGE_CHIPID_TIGON_II 0x6000 252#define BGE_CHIPID_BCM5700_A0 0x7000 253#define BGE_CHIPID_BCM5700_A1 0x7001 254#define BGE_CHIPID_BCM5700_B0 0x7100 255#define BGE_CHIPID_BCM5700_B1 0x7101 256#define BGE_CHIPID_BCM5700_B2 0x7102 257#define BGE_CHIPID_BCM5700_B3 0x7103 258#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 259#define BGE_CHIPID_BCM5700_C0 0x7200 260#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 261#define BGE_CHIPID_BCM5701_B0 0x0100 262#define BGE_CHIPID_BCM5701_B2 0x0102 263#define BGE_CHIPID_BCM5701_B5 0x0105 264#define BGE_CHIPID_BCM5703_A0 0x1000 265#define BGE_CHIPID_BCM5703_A1 0x1001 266#define BGE_CHIPID_BCM5703_A2 0x1002 267#define BGE_CHIPID_BCM5703_A3 0x1003 268#define BGE_CHIPID_BCM5703_B0 0x1100 269#define BGE_CHIPID_BCM5704_A0 0x2000 270#define BGE_CHIPID_BCM5704_A1 0x2001 271#define BGE_CHIPID_BCM5704_A2 0x2002 272#define BGE_CHIPID_BCM5704_A3 0x2003 273#define BGE_CHIPID_BCM5704_B0 0x2100 274#define BGE_CHIPID_BCM5705_A0 0x3000 275#define BGE_CHIPID_BCM5705_A1 0x3001 276#define BGE_CHIPID_BCM5705_A2 0x3002 277#define BGE_CHIPID_BCM5705_A3 0x3003 278#define BGE_CHIPID_BCM5750_A0 0x4000 279#define BGE_CHIPID_BCM5750_A1 0x4001 280#define BGE_CHIPID_BCM5750_A3 0x4000 281#define BGE_CHIPID_BCM5750_B0 0x4100 282#define BGE_CHIPID_BCM5750_B1 0x4101 283#define BGE_CHIPID_BCM5750_C0 0x4200 284#define BGE_CHIPID_BCM5750_C1 0x4201 285#define BGE_CHIPID_BCM5750_C2 0x4202 286#define BGE_CHIPID_BCM5714_A0 0x5000 287#define BGE_CHIPID_BCM5752_A0 0x6000 288#define BGE_CHIPID_BCM5752_A1 0x6001 289#define BGE_CHIPID_BCM5752_A2 0x6002 290#define BGE_CHIPID_BCM5714_B0 0x8000 291#define BGE_CHIPID_BCM5714_B3 0x8003 292#define BGE_CHIPID_BCM5715_A0 0x9000 293#define BGE_CHIPID_BCM5715_A1 0x9001 294#define BGE_CHIPID_BCM5715_A3 0x9003 295#define BGE_CHIPID_BCM5755_A0 0xa000 296#define BGE_CHIPID_BCM5755_A1 0xa001 297#define BGE_CHIPID_BCM5755_A2 0xa002 298#define BGE_CHIPID_BCM5722_A0 0xa200 299#define BGE_CHIPID_BCM5754_A0 0xb000 300#define BGE_CHIPID_BCM5754_A1 0xb001 301#define BGE_CHIPID_BCM5754_A2 0xb002 302#define BGE_CHIPID_BCM5761_A0 0x5761000 303#define BGE_CHIPID_BCM5761_A1 0x5761100 304#define BGE_CHIPID_BCM5784_A0 0x5784000 305#define BGE_CHIPID_BCM5784_A1 0x5784100 306#define BGE_CHIPID_BCM5787_A0 0xb000 307#define BGE_CHIPID_BCM5787_A1 0xb001 308#define BGE_CHIPID_BCM5787_A2 0xb002 309#define BGE_CHIPID_BCM5906_A0 0xc000 310#define BGE_CHIPID_BCM5906_A1 0xc001 311#define BGE_CHIPID_BCM5906_A2 0xc002 312#define BGE_CHIPID_BCM57780_A0 0x57780000 313#define BGE_CHIPID_BCM57780_A1 0x57780001 314 315/* shorthand one */ 316#define BGE_ASICREV(x) ((x) >> 12) 317#define BGE_ASICREV_BCM5701 0x00 318#define BGE_ASICREV_BCM5703 0x01 319#define BGE_ASICREV_BCM5704 0x02 320#define BGE_ASICREV_BCM5705 0x03 321#define BGE_ASICREV_BCM5750 0x04 322#define BGE_ASICREV_BCM5714_A0 0x05 323#define BGE_ASICREV_BCM5752 0x06 324#define BGE_ASICREV_BCM5700 0x07 325#define BGE_ASICREV_BCM5780 0x08 326#define BGE_ASICREV_BCM5714 0x09 327#define BGE_ASICREV_BCM5755 0x0a 328#define BGE_ASICREV_BCM5754 0x0b 329#define BGE_ASICREV_BCM5787 0x0b 330#define BGE_ASICREV_BCM5906 0x0c 331/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 332#define BGE_ASICREV_USE_PRODID_REG 0x0f 333/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 334#define BGE_ASICREV_BCM5761 0x5761 335#define BGE_ASICREV_BCM5784 0x5784 336#define BGE_ASICREV_BCM5785 0x5785 337#define BGE_ASICREV_BCM57780 0x57780 338 339/* chip revisions */ 340#define BGE_CHIPREV(x) ((x) >> 8) 341#define BGE_CHIPREV_5700_AX 0x70 342#define BGE_CHIPREV_5700_BX 0x71 343#define BGE_CHIPREV_5700_CX 0x72 344#define BGE_CHIPREV_5701_AX 0x00 345#define BGE_CHIPREV_5703_AX 0x10 346#define BGE_CHIPREV_5704_AX 0x20 347#define BGE_CHIPREV_5704_BX 0x21 348#define BGE_CHIPREV_5750_AX 0x40 349#define BGE_CHIPREV_5750_BX 0x41 350/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 351#define BGE_CHIPREV_5761_AX 0x57611 352#define BGE_CHIPREV_5784_AX 0x57841 353 354/* PCI DMA Read/Write Control register */ 355#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 356#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 357#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 358#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 359#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 360#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 361#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 362#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 363#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 364#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 365#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 366#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 367 368#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 369#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 370#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 371#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 372 373#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 374#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 375#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 376#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 377#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 378#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 379#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 380#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 381 382#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 383#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 384#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 385#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 386#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 387#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 388#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 389#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 390 391/* 392 * PCI state register -- note, this register is read only 393 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 394 * register is set. 395 */ 396#define BGE_PCISTATE_FORCE_RESET 0x00000001 397#define BGE_PCISTATE_INTR_STATE 0x00000002 398#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 399#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 400#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 401#define BGE_PCISTATE_WANT_EXPROM 0x00000020 402#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 403#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 404#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 405 406/* 407 * PCI Clock Control register -- note, this register is read only 408 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 409 * register is set. 410 */ 411#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 412#define BGE_PCICLOCKCTL_M66EN 0x00000080 413#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 414#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 415#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 416#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 417#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 418#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 419#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 420#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 421 422 423#ifndef PCIM_CMD_MWIEN 424#define PCIM_CMD_MWIEN 0x0010 425#endif 426#ifndef PCIM_CMD_INTxDIS 427#define PCIM_CMD_INTxDIS 0x0400 428#endif 429 430/* 431 * High priority mailbox registers 432 * Each mailbox is 64-bits wide, though we only use the 433 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 434 * first. The NIC will load the mailbox after the lower 32 bit word 435 * has been updated. 436 */ 437#define BGE_MBX_IRQ0_HI 0x0200 438#define BGE_MBX_IRQ0_LO 0x0204 439#define BGE_MBX_IRQ1_HI 0x0208 440#define BGE_MBX_IRQ1_LO 0x020C 441#define BGE_MBX_IRQ2_HI 0x0210 442#define BGE_MBX_IRQ2_LO 0x0214 443#define BGE_MBX_IRQ3_HI 0x0218 444#define BGE_MBX_IRQ3_LO 0x021C 445#define BGE_MBX_GEN0_HI 0x0220 446#define BGE_MBX_GEN0_LO 0x0224 447#define BGE_MBX_GEN1_HI 0x0228 448#define BGE_MBX_GEN1_LO 0x022C 449#define BGE_MBX_GEN2_HI 0x0230 450#define BGE_MBX_GEN2_LO 0x0234 451#define BGE_MBX_GEN3_HI 0x0228 452#define BGE_MBX_GEN3_LO 0x022C 453#define BGE_MBX_GEN4_HI 0x0240 454#define BGE_MBX_GEN4_LO 0x0244 455#define BGE_MBX_GEN5_HI 0x0248 456#define BGE_MBX_GEN5_LO 0x024C 457#define BGE_MBX_GEN6_HI 0x0250 458#define BGE_MBX_GEN6_LO 0x0254 459#define BGE_MBX_GEN7_HI 0x0258 460#define BGE_MBX_GEN7_LO 0x025C 461#define BGE_MBX_RELOAD_STATS_HI 0x0260 462#define BGE_MBX_RELOAD_STATS_LO 0x0264 463#define BGE_MBX_RX_STD_PROD_HI 0x0268 464#define BGE_MBX_RX_STD_PROD_LO 0x026C 465#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 466#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 467#define BGE_MBX_RX_MINI_PROD_HI 0x0278 468#define BGE_MBX_RX_MINI_PROD_LO 0x027C 469#define BGE_MBX_RX_CONS0_HI 0x0280 470#define BGE_MBX_RX_CONS0_LO 0x0284 471#define BGE_MBX_RX_CONS1_HI 0x0288 472#define BGE_MBX_RX_CONS1_LO 0x028C 473#define BGE_MBX_RX_CONS2_HI 0x0290 474#define BGE_MBX_RX_CONS2_LO 0x0294 475#define BGE_MBX_RX_CONS3_HI 0x0298 476#define BGE_MBX_RX_CONS3_LO 0x029C 477#define BGE_MBX_RX_CONS4_HI 0x02A0 478#define BGE_MBX_RX_CONS4_LO 0x02A4 479#define BGE_MBX_RX_CONS5_HI 0x02A8 480#define BGE_MBX_RX_CONS5_LO 0x02AC 481#define BGE_MBX_RX_CONS6_HI 0x02B0 482#define BGE_MBX_RX_CONS6_LO 0x02B4 483#define BGE_MBX_RX_CONS7_HI 0x02B8 484#define BGE_MBX_RX_CONS7_LO 0x02BC 485#define BGE_MBX_RX_CONS8_HI 0x02C0 486#define BGE_MBX_RX_CONS8_LO 0x02C4 487#define BGE_MBX_RX_CONS9_HI 0x02C8 488#define BGE_MBX_RX_CONS9_LO 0x02CC 489#define BGE_MBX_RX_CONS10_HI 0x02D0 490#define BGE_MBX_RX_CONS10_LO 0x02D4 491#define BGE_MBX_RX_CONS11_HI 0x02D8 492#define BGE_MBX_RX_CONS11_LO 0x02DC 493#define BGE_MBX_RX_CONS12_HI 0x02E0 494#define BGE_MBX_RX_CONS12_LO 0x02E4 495#define BGE_MBX_RX_CONS13_HI 0x02E8 496#define BGE_MBX_RX_CONS13_LO 0x02EC 497#define BGE_MBX_RX_CONS14_HI 0x02F0 498#define BGE_MBX_RX_CONS14_LO 0x02F4 499#define BGE_MBX_RX_CONS15_HI 0x02F8 500#define BGE_MBX_RX_CONS15_LO 0x02FC 501#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 502#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 503#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 504#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 505#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 506#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 507#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 508#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 509#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 510#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 511#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 512#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 513#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 514#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 515#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 516#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 517#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 518#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 519#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 520#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 521#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 522#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 523#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 524#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 525#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 526#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 527#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 528#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 529#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 530#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 531#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 532#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 533#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 534#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 535#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 536#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 537#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 538#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 539#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 540#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 541#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 542#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 543#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 544#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 545#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 546#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 547#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 548#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 549#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 550#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 551#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 552#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 553#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 554#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 555#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 556#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 557#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 558#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 559#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 560#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 561#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 562#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 563#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 564#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 565 566#define BGE_TX_RINGS_MAX 4 567#define BGE_TX_RINGS_EXTSSRAM_MAX 16 568#define BGE_RX_RINGS_MAX 16 569 570/* Ethernet MAC control registers */ 571#define BGE_MAC_MODE 0x0400 572#define BGE_MAC_STS 0x0404 573#define BGE_MAC_EVT_ENB 0x0408 574#define BGE_MAC_LED_CTL 0x040C 575#define BGE_MAC_ADDR1_LO 0x0410 576#define BGE_MAC_ADDR1_HI 0x0414 577#define BGE_MAC_ADDR2_LO 0x0418 578#define BGE_MAC_ADDR2_HI 0x041C 579#define BGE_MAC_ADDR3_LO 0x0420 580#define BGE_MAC_ADDR3_HI 0x0424 581#define BGE_MAC_ADDR4_LO 0x0428 582#define BGE_MAC_ADDR4_HI 0x042C 583#define BGE_WOL_PATPTR 0x0430 584#define BGE_WOL_PATCFG 0x0434 585#define BGE_TX_RANDOM_BACKOFF 0x0438 586#define BGE_RX_MTU 0x043C 587#define BGE_GBIT_PCS_TEST 0x0440 588#define BGE_TX_TBI_AUTONEG 0x0444 589#define BGE_RX_TBI_AUTONEG 0x0448 590#define BGE_MI_COMM 0x044C 591#define BGE_MI_STS 0x0450 592#define BGE_MI_MODE 0x0454 593#define BGE_AUTOPOLL_STS 0x0458 594#define BGE_TX_MODE 0x045C 595#define BGE_TX_STS 0x0460 596#define BGE_TX_LENGTHS 0x0464 597#define BGE_RX_MODE 0x0468 598#define BGE_RX_STS 0x046C 599#define BGE_MAR0 0x0470 600#define BGE_MAR1 0x0474 601#define BGE_MAR2 0x0478 602#define BGE_MAR3 0x047C 603#define BGE_RX_BD_RULES_CTL0 0x0480 604#define BGE_RX_BD_RULES_MASKVAL0 0x0484 605#define BGE_RX_BD_RULES_CTL1 0x0488 606#define BGE_RX_BD_RULES_MASKVAL1 0x048C 607#define BGE_RX_BD_RULES_CTL2 0x0490 608#define BGE_RX_BD_RULES_MASKVAL2 0x0494 609#define BGE_RX_BD_RULES_CTL3 0x0498 610#define BGE_RX_BD_RULES_MASKVAL3 0x049C 611#define BGE_RX_BD_RULES_CTL4 0x04A0 612#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 613#define BGE_RX_BD_RULES_CTL5 0x04A8 614#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 615#define BGE_RX_BD_RULES_CTL6 0x04B0 616#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 617#define BGE_RX_BD_RULES_CTL7 0x04B8 618#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 619#define BGE_RX_BD_RULES_CTL8 0x04C0 620#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 621#define BGE_RX_BD_RULES_CTL9 0x04C8 622#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 623#define BGE_RX_BD_RULES_CTL10 0x04D0 624#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 625#define BGE_RX_BD_RULES_CTL11 0x04D8 626#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 627#define BGE_RX_BD_RULES_CTL12 0x04E0 628#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 629#define BGE_RX_BD_RULES_CTL13 0x04E8 630#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 631#define BGE_RX_BD_RULES_CTL14 0x04F0 632#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 633#define BGE_RX_BD_RULES_CTL15 0x04F8 634#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 635#define BGE_RX_RULES_CFG 0x0500 636#define BGE_MAX_RX_FRAME_LOWAT 0x0504 637#define BGE_SERDES_CFG 0x0590 638#define BGE_SERDES_STS 0x0594 639#define BGE_SGDIG_CFG 0x05B0 640#define BGE_SGDIG_STS 0x05B4 641#define BGE_TX_MAC_STATS_OCTETS 0x0800 642#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 643#define BGE_TX_MAC_STATS_COLLS 0x0808 644#define BGE_TX_MAC_STATS_XON_SENT 0x080C 645#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 646#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 647#define BGE_TX_MAC_STATS_ERRORS 0x0818 648#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 649#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 650#define BGE_TX_MAC_STATS_DEFERRED 0x0824 651#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 652#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 653#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 654#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 655#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 656#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 657#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 658#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 659#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 660#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 661#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 662#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 663#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 664#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 665#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 666#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 667#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 668#define BGE_TX_MAC_STATS_UCAST 0x086C 669#define BGE_TX_MAC_STATS_MCAST 0x0870 670#define BGE_TX_MAC_STATS_BCAST 0x0874 671#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 672#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 673#define BGE_RX_MAC_STATS_OCTESTS 0x0880 674#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 675#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 676#define BGE_RX_MAC_STATS_UCAST 0x088C 677#define BGE_RX_MAC_STATS_MCAST 0x0890 678#define BGE_RX_MAC_STATS_BCAST 0x0894 679#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 680#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 681#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 682#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 683#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 684#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 685#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 686#define BGE_RX_MAC_STATS_JABBERS 0x08B4 687#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 688 689/* Ethernet MAC Mode register */ 690#define BGE_MACMODE_RESET 0x00000001 691#define BGE_MACMODE_HALF_DUPLEX 0x00000002 692#define BGE_MACMODE_PORTMODE 0x0000000C 693#define BGE_MACMODE_LOOPBACK 0x00000010 694#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 695#define BGE_MACMODE_TX_BURST_ENB 0x00000100 696#define BGE_MACMODE_MAX_DEFER 0x00000200 697#define BGE_MACMODE_LINK_POLARITY 0x00000400 698#define BGE_MACMODE_RX_STATS_ENB 0x00000800 699#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 700#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 701#define BGE_MACMODE_TX_STATS_ENB 0x00004000 702#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 703#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 704#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 705#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 706#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 707#define BGE_MACMODE_MIP_ENB 0x00100000 708#define BGE_MACMODE_TXDMA_ENB 0x00200000 709#define BGE_MACMODE_RXDMA_ENB 0x00400000 710#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 711 712#define BGE_PORTMODE_NONE 0x00000000 713#define BGE_PORTMODE_MII 0x00000004 714#define BGE_PORTMODE_GMII 0x00000008 715#define BGE_PORTMODE_TBI 0x0000000C 716 717/* MAC Status register */ 718#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 719#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 720#define BGE_MACSTAT_RX_CFG 0x00000004 721#define BGE_MACSTAT_CFG_CHANGED 0x00000008 722#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 723#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 724#define BGE_MACSTAT_LINK_CHANGED 0x00001000 725#define BGE_MACSTAT_MI_COMPLETE 0x00400000 726#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 727#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 728#define BGE_MACSTAT_ODI_ERROR 0x02000000 729#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 730#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 731 732/* MAC Event Enable Register */ 733#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 734#define BGE_EVTENB_LINK_CHANGED 0x00001000 735#define BGE_EVTENB_MI_COMPLETE 0x00400000 736#define BGE_EVTENB_MI_INTERRUPT 0x00800000 737#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 738#define BGE_EVTENB_ODI_ERROR 0x02000000 739#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 740#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 741 742/* LED Control Register */ 743#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 744#define BGE_LEDCTL_1000MBPS_LED 0x00000002 745#define BGE_LEDCTL_100MBPS_LED 0x00000004 746#define BGE_LEDCTL_10MBPS_LED 0x00000008 747#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 748#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 749#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 750#define BGE_LEDCTL_1000MBPS_STS 0x00000080 751#define BGE_LEDCTL_100MBPS_STS 0x00000100 752#define BGE_LEDCTL_10MBPS_STS 0x00000200 753#define BGE_LEDCTL_TRADLED_STS 0x00000400 754#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 755#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 756 757/* TX backoff seed register */ 758#define BGE_TX_BACKOFF_SEED_MASK 0x3F 759 760/* Autopoll status register */ 761#define BGE_AUTOPOLLSTS_ERROR 0x00000001 762 763/* Transmit MAC mode register */ 764#define BGE_TXMODE_RESET 0x00000001 765#define BGE_TXMODE_ENABLE 0x00000002 766#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 767#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 768#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 769#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 770 771/* Transmit MAC status register */ 772#define BGE_TXSTAT_RX_XOFFED 0x00000001 773#define BGE_TXSTAT_SENT_XOFF 0x00000002 774#define BGE_TXSTAT_SENT_XON 0x00000004 775#define BGE_TXSTAT_LINK_UP 0x00000008 776#define BGE_TXSTAT_ODI_UFLOW 0x00000010 777#define BGE_TXSTAT_ODI_OFLOW 0x00000020 778 779/* Transmit MAC lengths register */ 780#define BGE_TXLEN_SLOTTIME 0x000000FF 781#define BGE_TXLEN_IPG 0x00000F00 782#define BGE_TXLEN_CRS 0x00003000 783 784/* Receive MAC mode register */ 785#define BGE_RXMODE_RESET 0x00000001 786#define BGE_RXMODE_ENABLE 0x00000002 787#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 788#define BGE_RXMODE_RX_GIANTS 0x00000020 789#define BGE_RXMODE_RX_RUNTS 0x00000040 790#define BGE_RXMODE_8022_LENCHECK 0x00000080 791#define BGE_RXMODE_RX_PROMISC 0x00000100 792#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 793#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 794 795/* Receive MAC status register */ 796#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 797#define BGE_RXSTAT_RCVD_XOFF 0x00000002 798#define BGE_RXSTAT_RCVD_XON 0x00000004 799 800/* Receive Rules Control register */ 801#define BGE_RXRULECTL_OFFSET 0x000000FF 802#define BGE_RXRULECTL_CLASS 0x00001F00 803#define BGE_RXRULECTL_HDRTYPE 0x0000E000 804#define BGE_RXRULECTL_COMPARE_OP 0x00030000 805#define BGE_RXRULECTL_MAP 0x01000000 806#define BGE_RXRULECTL_DISCARD 0x02000000 807#define BGE_RXRULECTL_MASK 0x04000000 808#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 809#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 810#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 811#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 812 813/* Receive Rules Mask register */ 814#define BGE_RXRULEMASK_VALUE 0x0000FFFF 815#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 816 817/* SERDES configuration register */ 818#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 819#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 820#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 821#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 822#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 823#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 824#define BGE_SERDESCFG_TXMODE 0x00001000 825#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 826#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 827#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 828#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 829#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 830#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 831#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 832#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 833#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 834 835/* SERDES status register */ 836#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 837#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 838 839/* SGDIG config (not documented) */ 840#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 841#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 842#define BGE_SGDIGCFG_SEND 0x40000000 843#define BGE_SGDIGCFG_AUTO 0x80000000 844 845/* SGDIG status (not documented) */ 846#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 847#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 848#define BGE_SGDIGSTS_DONE 0x00000002 849 850 851/* MI communication register */ 852#define BGE_MICOMM_DATA 0x0000FFFF 853#define BGE_MICOMM_REG 0x001F0000 854#define BGE_MICOMM_PHY 0x03E00000 855#define BGE_MICOMM_CMD 0x0C000000 856#define BGE_MICOMM_READFAIL 0x10000000 857#define BGE_MICOMM_BUSY 0x20000000 858 859#define BGE_MIREG(x) ((x & 0x1F) << 16) 860#define BGE_MIPHY(x) ((x & 0x1F) << 21) 861#define BGE_MICMD_WRITE 0x04000000 862#define BGE_MICMD_READ 0x08000000 863 864/* MI status register */ 865#define BGE_MISTS_LINK 0x00000001 866#define BGE_MISTS_10MBPS 0x00000002 867 868#define BGE_MIMODE_CLK_10MHZ 0x00000001 869#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 870#define BGE_MIMODE_AUTOPOLL 0x00000010 871#define BGE_MIMODE_CLKCNT 0x001F0000 872#define BGE_MIMODE_500KHZ_CONST 0x00008000 873#define BGE_MIMODE_BASE 0x000C0000 874 875 876/* 877 * Send data initiator control registers. 878 */ 879#define BGE_SDI_MODE 0x0C00 880#define BGE_SDI_STATUS 0x0C04 881#define BGE_SDI_STATS_CTL 0x0C08 882#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 883#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 884#define BGE_ISO_PKT_TX 0x0C20 885#define BGE_LOCSTATS_COS0 0x0C80 886#define BGE_LOCSTATS_COS1 0x0C84 887#define BGE_LOCSTATS_COS2 0x0C88 888#define BGE_LOCSTATS_COS3 0x0C8C 889#define BGE_LOCSTATS_COS4 0x0C90 890#define BGE_LOCSTATS_COS5 0x0C84 891#define BGE_LOCSTATS_COS6 0x0C98 892#define BGE_LOCSTATS_COS7 0x0C9C 893#define BGE_LOCSTATS_COS8 0x0CA0 894#define BGE_LOCSTATS_COS9 0x0CA4 895#define BGE_LOCSTATS_COS10 0x0CA8 896#define BGE_LOCSTATS_COS11 0x0CAC 897#define BGE_LOCSTATS_COS12 0x0CB0 898#define BGE_LOCSTATS_COS13 0x0CB4 899#define BGE_LOCSTATS_COS14 0x0CB8 900#define BGE_LOCSTATS_COS15 0x0CBC 901#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 902#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 903#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 904#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 905#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 906#define BGE_LOCSTATS_IRQS 0x0CD4 907#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 908#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 909 910/* Send Data Initiator mode register */ 911#define BGE_SDIMODE_RESET 0x00000001 912#define BGE_SDIMODE_ENABLE 0x00000002 913#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 914 915/* Send Data Initiator stats register */ 916#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 917 918/* Send Data Initiator stats control register */ 919#define BGE_SDISTATSCTL_ENABLE 0x00000001 920#define BGE_SDISTATSCTL_FASTER 0x00000002 921#define BGE_SDISTATSCTL_CLEAR 0x00000004 922#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 923#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 924 925/* 926 * Send Data Completion Control registers 927 */ 928#define BGE_SDC_MODE 0x1000 929#define BGE_SDC_STATUS 0x1004 930 931/* Send Data completion mode register */ 932#define BGE_SDCMODE_RESET 0x00000001 933#define BGE_SDCMODE_ENABLE 0x00000002 934#define BGE_SDCMODE_ATTN 0x00000004 935#define BGE_SDCMODE_CDELAY 0x00000010 936 937/* Send Data completion status register */ 938#define BGE_SDCSTAT_ATTN 0x00000004 939 940/* 941 * Send BD Ring Selector Control registers 942 */ 943#define BGE_SRS_MODE 0x1400 944#define BGE_SRS_STATUS 0x1404 945#define BGE_SRS_HWDIAG 0x1408 946#define BGE_SRS_LOC_NIC_CONS0 0x1440 947#define BGE_SRS_LOC_NIC_CONS1 0x1444 948#define BGE_SRS_LOC_NIC_CONS2 0x1448 949#define BGE_SRS_LOC_NIC_CONS3 0x144C 950#define BGE_SRS_LOC_NIC_CONS4 0x1450 951#define BGE_SRS_LOC_NIC_CONS5 0x1454 952#define BGE_SRS_LOC_NIC_CONS6 0x1458 953#define BGE_SRS_LOC_NIC_CONS7 0x145C 954#define BGE_SRS_LOC_NIC_CONS8 0x1460 955#define BGE_SRS_LOC_NIC_CONS9 0x1464 956#define BGE_SRS_LOC_NIC_CONS10 0x1468 957#define BGE_SRS_LOC_NIC_CONS11 0x146C 958#define BGE_SRS_LOC_NIC_CONS12 0x1470 959#define BGE_SRS_LOC_NIC_CONS13 0x1474 960#define BGE_SRS_LOC_NIC_CONS14 0x1478 961#define BGE_SRS_LOC_NIC_CONS15 0x147C 962 963/* Send BD Ring Selector Mode register */ 964#define BGE_SRSMODE_RESET 0x00000001 965#define BGE_SRSMODE_ENABLE 0x00000002 966#define BGE_SRSMODE_ATTN 0x00000004 967 968/* Send BD Ring Selector Status register */ 969#define BGE_SRSSTAT_ERROR 0x00000004 970 971/* Send BD Ring Selector HW Diagnostics register */ 972#define BGE_SRSHWDIAG_STATE 0x0000000F 973#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 974#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 975#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 976 977/* 978 * Send BD Initiator Selector Control registers 979 */ 980#define BGE_SBDI_MODE 0x1800 981#define BGE_SBDI_STATUS 0x1804 982#define BGE_SBDI_LOC_NIC_PROD0 0x1808 983#define BGE_SBDI_LOC_NIC_PROD1 0x180C 984#define BGE_SBDI_LOC_NIC_PROD2 0x1810 985#define BGE_SBDI_LOC_NIC_PROD3 0x1814 986#define BGE_SBDI_LOC_NIC_PROD4 0x1818 987#define BGE_SBDI_LOC_NIC_PROD5 0x181C 988#define BGE_SBDI_LOC_NIC_PROD6 0x1820 989#define BGE_SBDI_LOC_NIC_PROD7 0x1824 990#define BGE_SBDI_LOC_NIC_PROD8 0x1828 991#define BGE_SBDI_LOC_NIC_PROD9 0x182C 992#define BGE_SBDI_LOC_NIC_PROD10 0x1830 993#define BGE_SBDI_LOC_NIC_PROD11 0x1834 994#define BGE_SBDI_LOC_NIC_PROD12 0x1838 995#define BGE_SBDI_LOC_NIC_PROD13 0x183C 996#define BGE_SBDI_LOC_NIC_PROD14 0x1840 997#define BGE_SBDI_LOC_NIC_PROD15 0x1844 998 999/* Send BD Initiator Mode register */ 1000#define BGE_SBDIMODE_RESET 0x00000001 1001#define BGE_SBDIMODE_ENABLE 0x00000002 1002#define BGE_SBDIMODE_ATTN 0x00000004 1003 1004/* Send BD Initiator Status register */ 1005#define BGE_SBDISTAT_ERROR 0x00000004 1006 1007/* 1008 * Send BD Completion Control registers 1009 */ 1010#define BGE_SBDC_MODE 0x1C00 1011#define BGE_SBDC_STATUS 0x1C04 1012 1013/* Send BD Completion Control Mode register */ 1014#define BGE_SBDCMODE_RESET 0x00000001 1015#define BGE_SBDCMODE_ENABLE 0x00000002 1016#define BGE_SBDCMODE_ATTN 0x00000004 1017 1018/* Send BD Completion Control Status register */ 1019#define BGE_SBDCSTAT_ATTN 0x00000004 1020 1021/* 1022 * Receive List Placement Control registers 1023 */ 1024#define BGE_RXLP_MODE 0x2000 1025#define BGE_RXLP_STATUS 0x2004 1026#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1027#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1028#define BGE_RXLP_CFG 0x2010 1029#define BGE_RXLP_STATS_CTL 0x2014 1030#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1031#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1032#define BGE_RXLP_HEAD0 0x2100 1033#define BGE_RXLP_TAIL0 0x2104 1034#define BGE_RXLP_COUNT0 0x2108 1035#define BGE_RXLP_HEAD1 0x2110 1036#define BGE_RXLP_TAIL1 0x2114 1037#define BGE_RXLP_COUNT1 0x2118 1038#define BGE_RXLP_HEAD2 0x2120 1039#define BGE_RXLP_TAIL2 0x2124 1040#define BGE_RXLP_COUNT2 0x2128 1041#define BGE_RXLP_HEAD3 0x2130 1042#define BGE_RXLP_TAIL3 0x2134 1043#define BGE_RXLP_COUNT3 0x2138 1044#define BGE_RXLP_HEAD4 0x2140 1045#define BGE_RXLP_TAIL4 0x2144 1046#define BGE_RXLP_COUNT4 0x2148 1047#define BGE_RXLP_HEAD5 0x2150 1048#define BGE_RXLP_TAIL5 0x2154 1049#define BGE_RXLP_COUNT5 0x2158 1050#define BGE_RXLP_HEAD6 0x2160 1051#define BGE_RXLP_TAIL6 0x2164 1052#define BGE_RXLP_COUNT6 0x2168 1053#define BGE_RXLP_HEAD7 0x2170 1054#define BGE_RXLP_TAIL7 0x2174 1055#define BGE_RXLP_COUNT7 0x2178 1056#define BGE_RXLP_HEAD8 0x2180 1057#define BGE_RXLP_TAIL8 0x2184 1058#define BGE_RXLP_COUNT8 0x2188 1059#define BGE_RXLP_HEAD9 0x2190 1060#define BGE_RXLP_TAIL9 0x2194 1061#define BGE_RXLP_COUNT9 0x2198 1062#define BGE_RXLP_HEAD10 0x21A0 1063#define BGE_RXLP_TAIL10 0x21A4 1064#define BGE_RXLP_COUNT10 0x21A8 1065#define BGE_RXLP_HEAD11 0x21B0 1066#define BGE_RXLP_TAIL11 0x21B4 1067#define BGE_RXLP_COUNT11 0x21B8 1068#define BGE_RXLP_HEAD12 0x21C0 1069#define BGE_RXLP_TAIL12 0x21C4 1070#define BGE_RXLP_COUNT12 0x21C8 1071#define BGE_RXLP_HEAD13 0x21D0 1072#define BGE_RXLP_TAIL13 0x21D4 1073#define BGE_RXLP_COUNT13 0x21D8 1074#define BGE_RXLP_HEAD14 0x21E0 1075#define BGE_RXLP_TAIL14 0x21E4 1076#define BGE_RXLP_COUNT14 0x21E8 1077#define BGE_RXLP_HEAD15 0x21F0 1078#define BGE_RXLP_TAIL15 0x21F4 1079#define BGE_RXLP_COUNT15 0x21F8 1080#define BGE_RXLP_LOCSTAT_COS0 0x2200 1081#define BGE_RXLP_LOCSTAT_COS1 0x2204 1082#define BGE_RXLP_LOCSTAT_COS2 0x2208 1083#define BGE_RXLP_LOCSTAT_COS3 0x220C 1084#define BGE_RXLP_LOCSTAT_COS4 0x2210 1085#define BGE_RXLP_LOCSTAT_COS5 0x2214 1086#define BGE_RXLP_LOCSTAT_COS6 0x2218 1087#define BGE_RXLP_LOCSTAT_COS7 0x221C 1088#define BGE_RXLP_LOCSTAT_COS8 0x2220 1089#define BGE_RXLP_LOCSTAT_COS9 0x2224 1090#define BGE_RXLP_LOCSTAT_COS10 0x2228 1091#define BGE_RXLP_LOCSTAT_COS11 0x222C 1092#define BGE_RXLP_LOCSTAT_COS12 0x2230 1093#define BGE_RXLP_LOCSTAT_COS13 0x2234 1094#define BGE_RXLP_LOCSTAT_COS14 0x2238 1095#define BGE_RXLP_LOCSTAT_COS15 0x223C 1096#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1097#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1098#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1099#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1100#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1101#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1102#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1103 1104 1105/* Receive List Placement mode register */ 1106#define BGE_RXLPMODE_RESET 0x00000001 1107#define BGE_RXLPMODE_ENABLE 0x00000002 1108#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1109#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1110#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1111 1112/* Receive List Placement Status register */ 1113#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1114#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1115#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1116 1117/* 1118 * Receive Data and Receive BD Initiator Control Registers 1119 */ 1120#define BGE_RDBDI_MODE 0x2400 1121#define BGE_RDBDI_STATUS 0x2404 1122#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1123#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1124#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1125#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1126#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1127#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1128#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1129#define BGE_RX_STD_RCB_NICADDR 0x245C 1130#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1131#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1132#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1133#define BGE_RX_MINI_RCB_NICADDR 0x246C 1134#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1135#define BGE_RDBDI_STD_RX_CONS 0x2474 1136#define BGE_RDBDI_MINI_RX_CONS 0x2478 1137#define BGE_RDBDI_RETURN_PROD0 0x2480 1138#define BGE_RDBDI_RETURN_PROD1 0x2484 1139#define BGE_RDBDI_RETURN_PROD2 0x2488 1140#define BGE_RDBDI_RETURN_PROD3 0x248C 1141#define BGE_RDBDI_RETURN_PROD4 0x2490 1142#define BGE_RDBDI_RETURN_PROD5 0x2494 1143#define BGE_RDBDI_RETURN_PROD6 0x2498 1144#define BGE_RDBDI_RETURN_PROD7 0x249C 1145#define BGE_RDBDI_RETURN_PROD8 0x24A0 1146#define BGE_RDBDI_RETURN_PROD9 0x24A4 1147#define BGE_RDBDI_RETURN_PROD10 0x24A8 1148#define BGE_RDBDI_RETURN_PROD11 0x24AC 1149#define BGE_RDBDI_RETURN_PROD12 0x24B0 1150#define BGE_RDBDI_RETURN_PROD13 0x24B4 1151#define BGE_RDBDI_RETURN_PROD14 0x24B8 1152#define BGE_RDBDI_RETURN_PROD15 0x24BC 1153#define BGE_RDBDI_HWDIAG 0x24C0 1154 1155 1156/* Receive Data and Receive BD Initiator Mode register */ 1157#define BGE_RDBDIMODE_RESET 0x00000001 1158#define BGE_RDBDIMODE_ENABLE 0x00000002 1159#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1160#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1161#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1162 1163/* Receive Data and Receive BD Initiator Status register */ 1164#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1165#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1166#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1167 1168 1169/* 1170 * Receive Data Completion Control registers 1171 */ 1172#define BGE_RDC_MODE 0x2800 1173 1174/* Receive Data Completion Mode register */ 1175#define BGE_RDCMODE_RESET 0x00000001 1176#define BGE_RDCMODE_ENABLE 0x00000002 1177#define BGE_RDCMODE_ATTN 0x00000004 1178 1179/* 1180 * Receive BD Initiator Control registers 1181 */ 1182#define BGE_RBDI_MODE 0x2C00 1183#define BGE_RBDI_STATUS 0x2C04 1184#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1185#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1186#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1187#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1188#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1189#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1190 1191/* Receive BD Initiator Mode register */ 1192#define BGE_RBDIMODE_RESET 0x00000001 1193#define BGE_RBDIMODE_ENABLE 0x00000002 1194#define BGE_RBDIMODE_ATTN 0x00000004 1195 1196/* Receive BD Initiator Status register */ 1197#define BGE_RBDISTAT_ATTN 0x00000004 1198 1199/* 1200 * Receive BD Completion Control registers 1201 */ 1202#define BGE_RBDC_MODE 0x3000 1203#define BGE_RBDC_STATUS 0x3004 1204#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1205#define BGE_RBDC_STD_BD_PROD 0x300C 1206#define BGE_RBDC_MINI_BD_PROD 0x3010 1207 1208/* Receive BD completion mode register */ 1209#define BGE_RBDCMODE_RESET 0x00000001 1210#define BGE_RBDCMODE_ENABLE 0x00000002 1211#define BGE_RBDCMODE_ATTN 0x00000004 1212 1213/* Receive BD completion status register */ 1214#define BGE_RBDCSTAT_ERROR 0x00000004 1215 1216/* 1217 * Receive List Selector Control registers 1218 */ 1219#define BGE_RXLS_MODE 0x3400 1220#define BGE_RXLS_STATUS 0x3404 1221 1222/* Receive List Selector Mode register */ 1223#define BGE_RXLSMODE_RESET 0x00000001 1224#define BGE_RXLSMODE_ENABLE 0x00000002 1225#define BGE_RXLSMODE_ATTN 0x00000004 1226 1227/* Receive List Selector Status register */ 1228#define BGE_RXLSSTAT_ERROR 0x00000004 1229 1230#define BGE_CPMU_CTRL 0x3600 1231#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1232#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1233#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1234#define BGE_CPMU_HST_ACC 0x361C 1235#define BGE_CPMU_CLCK_STAT 0x3630 1236#define BGE_CPMU_MUTEX_REQ 0x365C 1237#define BGE_CPMU_MUTEX_GNT 0x3660 1238#define BGE_CPMU_PHY_STRAP 0x3664 1239 1240/* Central Power Management Unit (CPMU) register */ 1241#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1242#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1243#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1244#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1245 1246/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1247#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1248#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1249 1250/* Link Speed 1000MB Power Mode Clock Policy register */ 1251#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1252#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1253#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1254 1255/* Link Aware Power Mode Clock Policy register */ 1256#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1257#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1258 1259#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1260#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1261 1262/* CPMU Clock Status register */ 1263#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1264#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1265#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1266#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1267 1268/* CPMU Mutex Request register */ 1269#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1270#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1271 1272/* CPMU GPHY Strap register */ 1273#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1274 1275/* 1276 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1277 */ 1278#define BGE_MBCF_MODE 0x3800 1279#define BGE_MBCF_STATUS 0x3804 1280 1281/* Mbuf Cluster Free mode register */ 1282#define BGE_MBCFMODE_RESET 0x00000001 1283#define BGE_MBCFMODE_ENABLE 0x00000002 1284#define BGE_MBCFMODE_ATTN 0x00000004 1285 1286/* Mbuf Cluster Free status register */ 1287#define BGE_MBCFSTAT_ERROR 0x00000004 1288 1289/* 1290 * Host Coalescing Control registers 1291 */ 1292#define BGE_HCC_MODE 0x3C00 1293#define BGE_HCC_STATUS 0x3C04 1294#define BGE_HCC_RX_COAL_TICKS 0x3C08 1295#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1296#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1297#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1298#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1299#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1300#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1301#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1302#define BGE_HCC_STATS_TICKS 0x3C28 1303#define BGE_HCC_STATS_ADDR_HI 0x3C30 1304#define BGE_HCC_STATS_ADDR_LO 0x3C34 1305#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1306#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1307#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1308#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1309#define BGE_FLOW_ATTN 0x3C48 1310#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1311#define BGE_HCC_STD_BD_CONS 0x3C54 1312#define BGE_HCC_MINI_BD_CONS 0x3C58 1313#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1314#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1315#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1316#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1317#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1318#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1319#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1320#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1321#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1322#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1323#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1324#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1325#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1326#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1327#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1328#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1329#define BGE_HCC_TX_BD_CONS0 0x3CC0 1330#define BGE_HCC_TX_BD_CONS1 0x3CC4 1331#define BGE_HCC_TX_BD_CONS2 0x3CC8 1332#define BGE_HCC_TX_BD_CONS3 0x3CCC 1333#define BGE_HCC_TX_BD_CONS4 0x3CD0 1334#define BGE_HCC_TX_BD_CONS5 0x3CD4 1335#define BGE_HCC_TX_BD_CONS6 0x3CD8 1336#define BGE_HCC_TX_BD_CONS7 0x3CDC 1337#define BGE_HCC_TX_BD_CONS8 0x3CE0 1338#define BGE_HCC_TX_BD_CONS9 0x3CE4 1339#define BGE_HCC_TX_BD_CONS10 0x3CE8 1340#define BGE_HCC_TX_BD_CONS11 0x3CEC 1341#define BGE_HCC_TX_BD_CONS12 0x3CF0 1342#define BGE_HCC_TX_BD_CONS13 0x3CF4 1343#define BGE_HCC_TX_BD_CONS14 0x3CF8 1344#define BGE_HCC_TX_BD_CONS15 0x3CFC 1345 1346 1347/* Host coalescing mode register */ 1348#define BGE_HCCMODE_RESET 0x00000001 1349#define BGE_HCCMODE_ENABLE 0x00000002 1350#define BGE_HCCMODE_ATTN 0x00000004 1351#define BGE_HCCMODE_COAL_NOW 0x00000008 1352#define BGE_HCCMODE_MSI_BITS 0x00000070 1353#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1354 1355#define BGE_STATBLKSZ_FULL 0x00000000 1356#define BGE_STATBLKSZ_64BYTE 0x00000080 1357#define BGE_STATBLKSZ_32BYTE 0x00000100 1358 1359/* Host coalescing status register */ 1360#define BGE_HCCSTAT_ERROR 0x00000004 1361 1362/* Flow attention register */ 1363#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1364#define BGE_FLOWATTN_MEMARB 0x00000080 1365#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1366#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1367#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1368#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1369#define BGE_FLOWATTN_RDBDI 0x00080000 1370#define BGE_FLOWATTN_RXLS 0x00100000 1371#define BGE_FLOWATTN_RXLP 0x00200000 1372#define BGE_FLOWATTN_RBDC 0x00400000 1373#define BGE_FLOWATTN_RBDI 0x00800000 1374#define BGE_FLOWATTN_SDC 0x08000000 1375#define BGE_FLOWATTN_SDI 0x10000000 1376#define BGE_FLOWATTN_SRS 0x20000000 1377#define BGE_FLOWATTN_SBDC 0x40000000 1378#define BGE_FLOWATTN_SBDI 0x80000000 1379 1380/* 1381 * Memory arbiter registers 1382 */ 1383#define BGE_MARB_MODE 0x4000 1384#define BGE_MARB_STATUS 0x4004 1385#define BGE_MARB_TRAPADDR_HI 0x4008 1386#define BGE_MARB_TRAPADDR_LO 0x400C 1387 1388/* Memory arbiter mode register */ 1389#define BGE_MARBMODE_RESET 0x00000001 1390#define BGE_MARBMODE_ENABLE 0x00000002 1391#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1392#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1393#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1394#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1395#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1396#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1397#define BGE_MARBMODE_PCI_TRAP 0x00000100 1398#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1399#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1400#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1401#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1402#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1403#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1404#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1405#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1406#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1407#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1408#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1409#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1410#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1411#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1412#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1413#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1414#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1415 1416/* Memory arbiter status register */ 1417#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1418#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1419#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1420#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1421#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1422#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1423#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1424#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1425#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1426#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1427#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1428#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1429#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1430#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1431#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1432#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1433#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1434#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1435#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1436#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1437#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1438#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1439#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1440#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1441 1442/* 1443 * Buffer manager control registers 1444 */ 1445#define BGE_BMAN_MODE 0x4400 1446#define BGE_BMAN_STATUS 0x4404 1447#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1448#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1449#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1450#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1451#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1452#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1453#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1454#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1455#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1456#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1457#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1458#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1459#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1460#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1461#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1462#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1463#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1464#define BGE_BMAN_HWDIAG_1 0x444C 1465#define BGE_BMAN_HWDIAG_2 0x4450 1466#define BGE_BMAN_HWDIAG_3 0x4454 1467 1468/* Buffer manager mode register */ 1469#define BGE_BMANMODE_RESET 0x00000001 1470#define BGE_BMANMODE_ENABLE 0x00000002 1471#define BGE_BMANMODE_ATTN 0x00000004 1472#define BGE_BMANMODE_TESTMODE 0x00000008 1473#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1474 1475/* Buffer manager status register */ 1476#define BGE_BMANSTAT_ERRO 0x00000004 1477#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1478 1479 1480/* 1481 * Read DMA Control registers 1482 */ 1483#define BGE_RDMA_MODE 0x4800 1484#define BGE_RDMA_STATUS 0x4804 1485#define BGE_RDMA_RSRVCTRL 0x4900 1486 1487/* Read DMA mode register */ 1488#define BGE_RDMAMODE_RESET 0x00000001 1489#define BGE_RDMAMODE_ENABLE 0x00000002 1490#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1491#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1492#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1493#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1494#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1495#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1496#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1497#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1498#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1499#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1500#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1501#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1502#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1503#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1504#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1505#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1506 1507/* Read DMA status register */ 1508#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1509#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1510#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1511#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1512#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1513#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1514#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1515#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1516 1517/* Read DMA Reserved Control register */ 1518#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1519 1520/* 1521 * Write DMA control registers 1522 */ 1523#define BGE_WDMA_MODE 0x4C00 1524#define BGE_WDMA_STATUS 0x4C04 1525 1526/* Write DMA mode register */ 1527#define BGE_WDMAMODE_RESET 0x00000001 1528#define BGE_WDMAMODE_ENABLE 0x00000002 1529#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1530#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1531#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1532#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1533#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1534#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1535#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1536#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1537#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1538#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1539#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1540 1541/* Write DMA status register */ 1542#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1543#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1544#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1545#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1546#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1547#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1548#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1549#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1550 1551 1552/* 1553 * RX CPU registers 1554 */ 1555#define BGE_RXCPU_MODE 0x5000 1556#define BGE_RXCPU_STATUS 0x5004 1557#define BGE_RXCPU_PC 0x501C 1558 1559/* RX CPU mode register */ 1560#define BGE_RXCPUMODE_RESET 0x00000001 1561#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1562#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1563#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1564#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1565#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1566#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1567#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1568#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1569#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1570#define BGE_RXCPUMODE_HALTCPU 0x00000400 1571#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1572#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1573#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1574 1575/* RX CPU status register */ 1576#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1577#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1578#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1579#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1580#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1581#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1582#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1583#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1584#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1585#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1586#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1587#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1588#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1589#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1590#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1591#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1592#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1593 1594/* 1595 * V? CPU registers 1596 */ 1597#define BGE_VCPU_STATUS 0x5100 1598#define BGE_VCPU_EXT_CTRL 0x6890 1599 1600#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1601#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1602 1603#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1604#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1605 1606/* 1607 * TX CPU registers 1608 */ 1609#define BGE_TXCPU_MODE 0x5400 1610#define BGE_TXCPU_STATUS 0x5404 1611#define BGE_TXCPU_PC 0x541C 1612 1613/* TX CPU mode register */ 1614#define BGE_TXCPUMODE_RESET 0x00000001 1615#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1616#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1617#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1618#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1619#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1620#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1621#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1622#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1623#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1624#define BGE_TXCPUMODE_HALTCPU 0x00000400 1625#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1626#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1627 1628/* TX CPU status register */ 1629#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1630#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1631#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1632#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1633#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1634#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1635#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1636#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1637#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1638#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1639#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1640#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1641#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1642#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1643#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1644#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1645#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1646 1647 1648/* 1649 * Low priority mailbox registers 1650 */ 1651#define BGE_LPMBX_IRQ0_HI 0x5800 1652#define BGE_LPMBX_IRQ0_LO 0x5804 1653#define BGE_LPMBX_IRQ1_HI 0x5808 1654#define BGE_LPMBX_IRQ1_LO 0x580C 1655#define BGE_LPMBX_IRQ2_HI 0x5810 1656#define BGE_LPMBX_IRQ2_LO 0x5814 1657#define BGE_LPMBX_IRQ3_HI 0x5818 1658#define BGE_LPMBX_IRQ3_LO 0x581C 1659#define BGE_LPMBX_GEN0_HI 0x5820 1660#define BGE_LPMBX_GEN0_LO 0x5824 1661#define BGE_LPMBX_GEN1_HI 0x5828 1662#define BGE_LPMBX_GEN1_LO 0x582C 1663#define BGE_LPMBX_GEN2_HI 0x5830 1664#define BGE_LPMBX_GEN2_LO 0x5834 1665#define BGE_LPMBX_GEN3_HI 0x5828 1666#define BGE_LPMBX_GEN3_LO 0x582C 1667#define BGE_LPMBX_GEN4_HI 0x5840 1668#define BGE_LPMBX_GEN4_LO 0x5844 1669#define BGE_LPMBX_GEN5_HI 0x5848 1670#define BGE_LPMBX_GEN5_LO 0x584C 1671#define BGE_LPMBX_GEN6_HI 0x5850 1672#define BGE_LPMBX_GEN6_LO 0x5854 1673#define BGE_LPMBX_GEN7_HI 0x5858 1674#define BGE_LPMBX_GEN7_LO 0x585C 1675#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1676#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1677#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1678#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1679#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1680#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1681#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1682#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1683#define BGE_LPMBX_RX_CONS0_HI 0x5880 1684#define BGE_LPMBX_RX_CONS0_LO 0x5884 1685#define BGE_LPMBX_RX_CONS1_HI 0x5888 1686#define BGE_LPMBX_RX_CONS1_LO 0x588C 1687#define BGE_LPMBX_RX_CONS2_HI 0x5890 1688#define BGE_LPMBX_RX_CONS2_LO 0x5894 1689#define BGE_LPMBX_RX_CONS3_HI 0x5898 1690#define BGE_LPMBX_RX_CONS3_LO 0x589C 1691#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1692#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1693#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1694#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1695#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1696#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1697#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1698#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1699#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1700#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1701#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1702#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1703#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1704#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1705#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1706#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1707#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1708#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1709#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1710#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1711#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1712#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1713#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1714#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1715#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1716#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1717#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1718#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1719#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1720#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1721#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1722#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1723#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1724#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1725#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1726#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1727#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1728#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1729#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1730#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1731#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1732#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1733#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1734#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1735#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1736#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1737#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1738#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1739#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1740#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1741#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1742#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1743#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1744#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1745#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1746#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1747#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1748#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1749#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1750#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1751#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1752#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1753#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1754#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1755#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1756#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1757#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1758#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1759#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1760#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1761#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1762#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1763#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1764#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1765#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1766#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1767#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1768#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1769#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1770#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1771#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1772#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1773#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1774#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1775#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1776#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1777#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1778#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1779 1780/* 1781 * Flow throw Queue reset register 1782 */ 1783#define BGE_FTQ_RESET 0x5C00 1784 1785#define BGE_FTQRESET_DMAREAD 0x00000002 1786#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1787#define BGE_FTQRESET_DMADONE 0x00000010 1788#define BGE_FTQRESET_SBDC 0x00000020 1789#define BGE_FTQRESET_SDI 0x00000040 1790#define BGE_FTQRESET_WDMA 0x00000080 1791#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1792#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1793#define BGE_FTQRESET_SDC 0x00000400 1794#define BGE_FTQRESET_HCC 0x00000800 1795#define BGE_FTQRESET_TXFIFO 0x00001000 1796#define BGE_FTQRESET_MBC 0x00002000 1797#define BGE_FTQRESET_RBDC 0x00004000 1798#define BGE_FTQRESET_RXLP 0x00008000 1799#define BGE_FTQRESET_RDBDI 0x00010000 1800#define BGE_FTQRESET_RDC 0x00020000 1801#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1802 1803/* 1804 * Message Signaled Interrupt registers 1805 */ 1806#define BGE_MSI_MODE 0x6000 1807#define BGE_MSI_STATUS 0x6004 1808#define BGE_MSI_FIFOACCESS 0x6008 1809 1810/* MSI mode register */ 1811#define BGE_MSIMODE_RESET 0x00000001 1812#define BGE_MSIMODE_ENABLE 0x00000002 1813#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1814#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1815 1816/* MSI status register */ 1817#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1818#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1819#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1820#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1821#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1822 1823 1824/* 1825 * DMA Completion registers 1826 */ 1827#define BGE_DMAC_MODE 0x6400 1828 1829/* DMA Completion mode register */ 1830#define BGE_DMACMODE_RESET 0x00000001 1831#define BGE_DMACMODE_ENABLE 0x00000002 1832 1833 1834/* 1835 * General control registers. 1836 */ 1837#define BGE_MODE_CTL 0x6800 1838#define BGE_MISC_CFG 0x6804 1839#define BGE_MISC_LOCAL_CTL 0x6808 1840#define BGE_CPU_EVENT 0x6810 1841#define BGE_EE_ADDR 0x6838 1842#define BGE_EE_DATA 0x683C 1843#define BGE_EE_CTL 0x6840 1844#define BGE_MDI_CTL 0x6844 1845#define BGE_EE_DELAY 0x6848 1846#define BGE_FASTBOOT_PC 0x6894 1847 1848/* 1849 * NVRAM Control registers 1850 */ 1851#define BGE_NVRAM_CMD 0x7000 1852#define BGE_NVRAM_STAT 0x7004 1853#define BGE_NVRAM_WRDATA 0x7008 1854#define BGE_NVRAM_ADDR 0x700c 1855#define BGE_NVRAM_RDDATA 0x7010 1856#define BGE_NVRAM_CFG1 0x7014 1857#define BGE_NVRAM_CFG2 0x7018 1858#define BGE_NVRAM_CFG3 0x701c 1859#define BGE_NVRAM_SWARB 0x7020 1860#define BGE_NVRAM_ACCESS 0x7024 1861#define BGE_NVRAM_WRITE1 0x7028 1862 1863#define BGE_NVRAMCMD_RESET 0x00000001 1864#define BGE_NVRAMCMD_DONE 0x00000008 1865#define BGE_NVRAMCMD_START 0x00000010 1866#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1867#define BGE_NVRAMCMD_ERASE 0x00000040 1868#define BGE_NVRAMCMD_FIRST 0x00000080 1869#define BGE_NVRAMCMD_LAST 0x00000100 1870 1871#define BGE_NVRAM_READCMD \ 1872 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1873 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1874#define BGE_NVRAM_WRITECMD \ 1875 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1876 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1877 1878#define BGE_NVRAMSWARB_SET0 0x00000001 1879#define BGE_NVRAMSWARB_SET1 0x00000002 1880#define BGE_NVRAMSWARB_SET2 0x00000003 1881#define BGE_NVRAMSWARB_SET3 0x00000004 1882#define BGE_NVRAMSWARB_CLR0 0x00000010 1883#define BGE_NVRAMSWARB_CLR1 0x00000020 1884#define BGE_NVRAMSWARB_CLR2 0x00000040 1885#define BGE_NVRAMSWARB_CLR3 0x00000080 1886#define BGE_NVRAMSWARB_GNT0 0x00000100 1887#define BGE_NVRAMSWARB_GNT1 0x00000200 1888#define BGE_NVRAMSWARB_GNT2 0x00000400 1889#define BGE_NVRAMSWARB_GNT3 0x00000800 1890#define BGE_NVRAMSWARB_REQ0 0x00001000 1891#define BGE_NVRAMSWARB_REQ1 0x00002000 1892#define BGE_NVRAMSWARB_REQ2 0x00004000 1893#define BGE_NVRAMSWARB_REQ3 0x00008000 1894 1895#define BGE_NVRAMACC_ENABLE 0x00000001 1896#define BGE_NVRAMACC_WRENABLE 0x00000002 1897 1898/* Mode control register */ 1899#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1900#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1901#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1902#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1903#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1904#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1905#define BGE_MODECTL_NO_RX_CRC 0x00000400 1906#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1907#define BGE_MODECTL_NO_TX_INTR 0x00002000 1908#define BGE_MODECTL_NO_RX_INTR 0x00004000 1909#define BGE_MODECTL_FORCE_PCI32 0x00008000 1910#define BGE_MODECTL_STACKUP 0x00010000 1911#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1912#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1913#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1914#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1915#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1916#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1917#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1918#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1919#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1920#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1921 1922/* Misc. config register */ 1923#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1924#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1925#define BGE_MISCCFG_BOARD_ID 0x0001E000 1926#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1927#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1928#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1929#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1930 1931#define BGE_32BITTIME_66MHZ (0x41 << 1) 1932 1933/* Misc. Local Control */ 1934#define BGE_MLC_INTR_STATE 0x00000001 1935#define BGE_MLC_INTR_CLR 0x00000002 1936#define BGE_MLC_INTR_SET 0x00000004 1937#define BGE_MLC_INTR_ONATTN 0x00000008 1938#define BGE_MLC_MISCIO_IN0 0x00000100 1939#define BGE_MLC_MISCIO_IN1 0x00000200 1940#define BGE_MLC_MISCIO_IN2 0x00000400 1941#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1942#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1943#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1944#define BGE_MLC_MISCIO_OUT0 0x00004000 1945#define BGE_MLC_MISCIO_OUT1 0x00008000 1946#define BGE_MLC_MISCIO_OUT2 0x00010000 1947#define BGE_MLC_EXTRAM_ENB 0x00020000 1948#define BGE_MLC_SRAM_SIZE 0x001C0000 1949#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1950#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1951#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1952#define BGE_MLC_AUTO_EEPROM 0x01000000 1953 1954#define BGE_SSRAMSIZE_256KB 0x00000000 1955#define BGE_SSRAMSIZE_512KB 0x00040000 1956#define BGE_SSRAMSIZE_1MB 0x00080000 1957#define BGE_SSRAMSIZE_2MB 0x000C0000 1958#define BGE_SSRAMSIZE_4MB 0x00100000 1959#define BGE_SSRAMSIZE_8MB 0x00140000 1960#define BGE_SSRAMSIZE_16M 0x00180000 1961 1962/* EEPROM address register */ 1963#define BGE_EEADDR_ADDRESS 0x0000FFFC 1964#define BGE_EEADDR_HALFCLK 0x01FF0000 1965#define BGE_EEADDR_START 0x02000000 1966#define BGE_EEADDR_DEVID 0x1C000000 1967#define BGE_EEADDR_RESET 0x20000000 1968#define BGE_EEADDR_DONE 0x40000000 1969#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1970 1971#define BGE_EEDEVID(x) ((x & 7) << 26) 1972#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1973#define BGE_HALFCLK_384SCL 0x60 1974#define BGE_EE_READCMD \ 1975 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1976 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1977#define BGE_EE_WRCMD \ 1978 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1979 BGE_EEADDR_START|BGE_EEADDR_DONE) 1980 1981/* EEPROM Control register */ 1982#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1983#define BGE_EECTL_CLKOUT 0x00000002 1984#define BGE_EECTL_CLKIN 0x00000004 1985#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1986#define BGE_EECTL_DATAOUT 0x00000010 1987#define BGE_EECTL_DATAIN 0x00000020 1988 1989/* MDI (MII/GMII) access register */ 1990#define BGE_MDI_DATA 0x00000001 1991#define BGE_MDI_DIR 0x00000002 1992#define BGE_MDI_SEL 0x00000004 1993#define BGE_MDI_CLK 0x00000008 1994 1995#define BGE_MEMWIN_START 0x00008000 1996#define BGE_MEMWIN_END 0x0000FFFF 1997 1998 1999#define BGE_MEMWIN_READ(sc, x, val) \ 2000 do { \ 2001 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2002 (0xFFFF0000 & x), 4); \ 2003 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2004 } while(0) 2005 2006#define BGE_MEMWIN_WRITE(sc, x, val) \ 2007 do { \ 2008 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2009 (0xFFFF0000 & x), 4); \ 2010 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2011 } while(0) 2012 2013/* 2014 * This magic number is written to the firmware mailbox at 0xb50 2015 * before a software reset is issued. After the internal firmware 2016 * has completed its initialization it will write the opposite of 2017 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2018 * driver to synchronize with the firmware. 2019 */ 2020#define BGE_MAGIC_NUMBER 0x4B657654 2021 2022typedef struct { 2023 uint32_t bge_addr_hi; 2024 uint32_t bge_addr_lo; 2025} bge_hostaddr; 2026 2027#define BGE_HOSTADDR(x, y) \ 2028 do { \ 2029 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2030 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2031 } while(0) 2032 2033#define BGE_ADDR_LO(y) \ 2034 ((uint64_t) (y) & 0xFFFFFFFF) 2035#define BGE_ADDR_HI(y) \ 2036 ((uint64_t) (y) >> 32) 2037 2038/* Ring control block structure */ 2039struct bge_rcb { 2040 bge_hostaddr bge_hostaddr; 2041 uint32_t bge_maxlen_flags; 2042 uint32_t bge_nicaddr; 2043}; 2044 2045#define RCB_WRITE_4(sc, rcb, offset, val) \ 2046 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2047#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2048 2049#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2050#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2051 2052struct bge_tx_bd { 2053 bge_hostaddr bge_addr; 2054#if BYTE_ORDER == LITTLE_ENDIAN 2055 uint16_t bge_flags; 2056 uint16_t bge_len; 2057 uint16_t bge_vlan_tag; 2058 uint16_t bge_mss; 2059#else 2060 uint16_t bge_len; 2061 uint16_t bge_flags; 2062 uint16_t bge_mss; 2063 uint16_t bge_vlan_tag; 2064#endif 2065}; 2066 2067#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2068#define BGE_TXBDFLAG_IP_CSUM 0x0002 2069#define BGE_TXBDFLAG_END 0x0004 2070#define BGE_TXBDFLAG_IP_FRAG 0x0008 2071#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2072#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2073#define BGE_TXBDFLAG_COAL_NOW 0x0080 2074#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2075#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2076#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2077#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2078#define BGE_TXBDFLAG_NO_CRC 0x8000 2079 2080#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2081 BGE_SEND_RING_1_TO_4 + \ 2082 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2083 2084struct bge_rx_bd { 2085 bge_hostaddr bge_addr; 2086#if BYTE_ORDER == LITTLE_ENDIAN 2087 uint16_t bge_len; 2088 uint16_t bge_idx; 2089 uint16_t bge_flags; 2090 uint16_t bge_type; 2091 uint16_t bge_tcp_udp_csum; 2092 uint16_t bge_ip_csum; 2093 uint16_t bge_vlan_tag; 2094 uint16_t bge_error_flag; 2095#else 2096 uint16_t bge_idx; 2097 uint16_t bge_len; 2098 uint16_t bge_type; 2099 uint16_t bge_flags; 2100 uint16_t bge_ip_csum; 2101 uint16_t bge_tcp_udp_csum; 2102 uint16_t bge_error_flag; 2103 uint16_t bge_vlan_tag; 2104#endif 2105 uint32_t bge_rsvd; 2106 uint32_t bge_opaque; 2107}; 2108 2109struct bge_extrx_bd { 2110 bge_hostaddr bge_addr1; 2111 bge_hostaddr bge_addr2; 2112 bge_hostaddr bge_addr3; 2113#if BYTE_ORDER == LITTLE_ENDIAN 2114 uint16_t bge_len2; 2115 uint16_t bge_len1; 2116 uint16_t bge_rsvd1; 2117 uint16_t bge_len3; 2118#else 2119 uint16_t bge_len1; 2120 uint16_t bge_len2; 2121 uint16_t bge_len3; 2122 uint16_t bge_rsvd1; 2123#endif 2124 bge_hostaddr bge_addr0; 2125#if BYTE_ORDER == LITTLE_ENDIAN 2126 uint16_t bge_len0; 2127 uint16_t bge_idx; 2128 uint16_t bge_flags; 2129 uint16_t bge_type; 2130 uint16_t bge_tcp_udp_csum; 2131 uint16_t bge_ip_csum; 2132 uint16_t bge_vlan_tag; 2133 uint16_t bge_error_flag; 2134#else 2135 uint16_t bge_idx; 2136 uint16_t bge_len0; 2137 uint16_t bge_type; 2138 uint16_t bge_flags; 2139 uint16_t bge_ip_csum; 2140 uint16_t bge_tcp_udp_csum; 2141 uint16_t bge_error_flag; 2142 uint16_t bge_vlan_tag; 2143#endif 2144 uint32_t bge_rsvd0; 2145 uint32_t bge_opaque; 2146}; 2147 2148#define BGE_RXBDFLAG_END 0x0004 2149#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2150#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2151#define BGE_RXBDFLAG_ERROR 0x0400 2152#define BGE_RXBDFLAG_MINI_RING 0x0800 2153#define BGE_RXBDFLAG_IP_CSUM 0x1000 2154#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2155#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2156 2157#define BGE_RXERRFLAG_BAD_CRC 0x0001 2158#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2159#define BGE_RXERRFLAG_LINK_LOST 0x0004 2160#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2161#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2162#define BGE_RXERRFLAG_RUNT 0x0020 2163#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2164#define BGE_RXERRFLAG_GIANT 0x0080 2165 2166struct bge_sts_idx { 2167#if BYTE_ORDER == LITTLE_ENDIAN 2168 uint16_t bge_rx_prod_idx; 2169 uint16_t bge_tx_cons_idx; 2170#else 2171 uint16_t bge_tx_cons_idx; 2172 uint16_t bge_rx_prod_idx; 2173#endif 2174}; 2175 2176struct bge_status_block { 2177 uint32_t bge_status; 2178 uint32_t bge_rsvd0; 2179#if BYTE_ORDER == LITTLE_ENDIAN 2180 uint16_t bge_rx_jumbo_cons_idx; 2181 uint16_t bge_rx_std_cons_idx; 2182 uint16_t bge_rx_mini_cons_idx; 2183 uint16_t bge_rsvd1; 2184#else 2185 uint16_t bge_rx_std_cons_idx; 2186 uint16_t bge_rx_jumbo_cons_idx; 2187 uint16_t bge_rsvd1; 2188 uint16_t bge_rx_mini_cons_idx; 2189#endif 2190 struct bge_sts_idx bge_idx[16]; 2191}; 2192 2193#define BGE_STATFLAG_UPDATED 0x00000001 2194#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2195#define BGE_STATFLAG_ERROR 0x00000004 2196 2197 2198/* 2199 * Broadcom Vendor ID 2200 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2201 * even though they're now manufactured by Broadcom) 2202 */ 2203#define BCOM_VENDORID 0x14E4 2204#define BCOM_DEVICEID_BCM5700 0x1644 2205#define BCOM_DEVICEID_BCM5701 0x1645 2206#define BCOM_DEVICEID_BCM5702 0x1646 2207#define BCOM_DEVICEID_BCM5702X 0x16A6 2208#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2209#define BCOM_DEVICEID_BCM5703 0x1647 2210#define BCOM_DEVICEID_BCM5703X 0x16A7 2211#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2212#define BCOM_DEVICEID_BCM5704C 0x1648 2213#define BCOM_DEVICEID_BCM5704S 0x16A8 2214#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2215#define BCOM_DEVICEID_BCM5705 0x1653 2216#define BCOM_DEVICEID_BCM5705K 0x1654 2217#define BCOM_DEVICEID_BCM5705F 0x166E 2218#define BCOM_DEVICEID_BCM5705M 0x165D 2219#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2220#define BCOM_DEVICEID_BCM5714C 0x1668 2221#define BCOM_DEVICEID_BCM5714S 0x1669 2222#define BCOM_DEVICEID_BCM5715 0x1678 2223#define BCOM_DEVICEID_BCM5715S 0x1679 2224#define BCOM_DEVICEID_BCM5720 0x1658 2225#define BCOM_DEVICEID_BCM5721 0x1659 2226#define BCOM_DEVICEID_BCM5722 0x165A 2227#define BCOM_DEVICEID_BCM5723 0x165B 2228#define BCOM_DEVICEID_BCM5750 0x1676 2229#define BCOM_DEVICEID_BCM5750M 0x167C 2230#define BCOM_DEVICEID_BCM5751 0x1677 2231#define BCOM_DEVICEID_BCM5751F 0x167E 2232#define BCOM_DEVICEID_BCM5751M 0x167D 2233#define BCOM_DEVICEID_BCM5752 0x1600 2234#define BCOM_DEVICEID_BCM5752M 0x1601 2235#define BCOM_DEVICEID_BCM5753 0x16F7 2236#define BCOM_DEVICEID_BCM5753F 0x16FE 2237#define BCOM_DEVICEID_BCM5753M 0x16FD 2238#define BCOM_DEVICEID_BCM5754 0x167A 2239#define BCOM_DEVICEID_BCM5754M 0x1672 2240#define BCOM_DEVICEID_BCM5755 0x167B 2241#define BCOM_DEVICEID_BCM5755M 0x1673 2242#define BCOM_DEVICEID_BCM5756 0x1674 2243#define BCOM_DEVICEID_BCM5761 0x1681 2244#define BCOM_DEVICEID_BCM5761E 0x1680 2245#define BCOM_DEVICEID_BCM5761S 0x1688 2246#define BCOM_DEVICEID_BCM5761SE 0x1689 2247#define BCOM_DEVICEID_BCM5764 0x1684 2248#define BCOM_DEVICEID_BCM5780 0x166A 2249#define BCOM_DEVICEID_BCM5780S 0x166B 2250#define BCOM_DEVICEID_BCM5781 0x16DD 2251#define BCOM_DEVICEID_BCM5782 0x1696 2252#define BCOM_DEVICEID_BCM5784 0x1698 2253#define BCOM_DEVICEID_BCM5785F 0x16a0 2254#define BCOM_DEVICEID_BCM5785G 0x1699 2255#define BCOM_DEVICEID_BCM5786 0x169A 2256#define BCOM_DEVICEID_BCM5787 0x169B 2257#define BCOM_DEVICEID_BCM5787M 0x1693 2258#define BCOM_DEVICEID_BCM5787F 0x167f 2259#define BCOM_DEVICEID_BCM5788 0x169C 2260#define BCOM_DEVICEID_BCM5789 0x169D 2261#define BCOM_DEVICEID_BCM5901 0x170D 2262#define BCOM_DEVICEID_BCM5901A2 0x170E 2263#define BCOM_DEVICEID_BCM5903M 0x16FF 2264#define BCOM_DEVICEID_BCM5906 0x1712 2265#define BCOM_DEVICEID_BCM5906M 0x1713 2266#define BCOM_DEVICEID_BCM57760 0x1690 2267#define BCOM_DEVICEID_BCM57780 0x1692 2268#define BCOM_DEVICEID_BCM57788 0x1691 2269#define BCOM_DEVICEID_BCM57790 0x1694 2270 2271/* 2272 * Alteon AceNIC PCI vendor/device ID. 2273 */ 2274#define ALTEON_VENDORID 0x12AE 2275#define ALTEON_DEVICEID_ACENIC 0x0001 2276#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2277#define ALTEON_DEVICEID_BCM5700 0x0003 2278#define ALTEON_DEVICEID_BCM5701 0x0004 2279 2280/* 2281 * 3Com 3c996 PCI vendor/device ID. 2282 */ 2283#define TC_VENDORID 0x10B7 2284#define TC_DEVICEID_3C996 0x0003 2285 2286/* 2287 * SysKonnect PCI vendor ID 2288 */ 2289#define SK_VENDORID 0x1148 2290#define SK_DEVICEID_ALTIMA 0x4400 2291#define SK_SUBSYSID_9D21 0x4421 2292#define SK_SUBSYSID_9D41 0x4441 2293 2294/* 2295 * Altima PCI vendor/device ID. 2296 */ 2297#define ALTIMA_VENDORID 0x173b 2298#define ALTIMA_DEVICE_AC1000 0x03e8 2299#define ALTIMA_DEVICE_AC1002 0x03e9 2300#define ALTIMA_DEVICE_AC9100 0x03ea 2301 2302/* 2303 * Dell PCI vendor ID 2304 */ 2305 2306#define DELL_VENDORID 0x1028 2307 2308/* 2309 * Apple PCI vendor ID. 2310 */ 2311#define APPLE_VENDORID 0x106b 2312#define APPLE_DEVICE_BCM5701 0x1645 2313 2314/* 2315 * Sun PCI vendor ID 2316 */ 2317#define SUN_VENDORID 0x108e 2318 2319/* 2320 * Fujitsu vendor/device IDs 2321 */ 2322#define FJTSU_VENDORID 0x10cf 2323#define FJTSU_DEVICEID_PW008GE5 0x11a1 2324#define FJTSU_DEVICEID_PW008GE4 0x11a2 2325#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2326 2327/* 2328 * Offset of MAC address inside EEPROM. 2329 */ 2330#define BGE_EE_MAC_OFFSET 0x7C 2331#define BGE_EE_MAC_OFFSET_5906 0x10 2332#define BGE_EE_HWCFG_OFFSET 0xC8 2333 2334#define BGE_HWCFG_VOLTAGE 0x00000003 2335#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2336#define BGE_HWCFG_MEDIA 0x00000030 2337#define BGE_HWCFG_ASF 0x00000080 2338 2339#define BGE_VOLTAGE_1POINT3 0x00000000 2340#define BGE_VOLTAGE_1POINT8 0x00000001 2341 2342#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2343#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2344#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2345 2346#define BGE_MEDIA_UNSPEC 0x00000000 2347#define BGE_MEDIA_COPPER 0x00000010 2348#define BGE_MEDIA_FIBER 0x00000020 2349 2350#define BGE_TICKS_PER_SEC 1000000 2351 2352/* 2353 * Ring size constants. 2354 */ 2355#define BGE_EVENT_RING_CNT 256 2356#define BGE_CMD_RING_CNT 64 2357#define BGE_STD_RX_RING_CNT 512 2358#define BGE_JUMBO_RX_RING_CNT 256 2359#define BGE_MINI_RX_RING_CNT 1024 2360#define BGE_RETURN_RING_CNT 1024 2361 2362/* 5705 has smaller return ring size */ 2363 2364#define BGE_RETURN_RING_CNT_5705 512 2365 2366/* 2367 * Possible TX ring sizes. 2368 */ 2369#define BGE_TX_RING_CNT_128 128 2370#define BGE_TX_RING_BASE_128 0x3800 2371 2372#define BGE_TX_RING_CNT_256 256 2373#define BGE_TX_RING_BASE_256 0x3000 2374 2375#define BGE_TX_RING_CNT_512 512 2376#define BGE_TX_RING_BASE_512 0x2000 2377 2378#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2379#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2380 2381/* 2382 * Tigon III statistics counters. 2383 */ 2384/* Statistics maintained MAC Receive block. */ 2385struct bge_rx_mac_stats { 2386 bge_hostaddr ifHCInOctets; 2387 bge_hostaddr Reserved1; 2388 bge_hostaddr etherStatsFragments; 2389 bge_hostaddr ifHCInUcastPkts; 2390 bge_hostaddr ifHCInMulticastPkts; 2391 bge_hostaddr ifHCInBroadcastPkts; 2392 bge_hostaddr dot3StatsFCSErrors; 2393 bge_hostaddr dot3StatsAlignmentErrors; 2394 bge_hostaddr xonPauseFramesReceived; 2395 bge_hostaddr xoffPauseFramesReceived; 2396 bge_hostaddr macControlFramesReceived; 2397 bge_hostaddr xoffStateEntered; 2398 bge_hostaddr dot3StatsFramesTooLong; 2399 bge_hostaddr etherStatsJabbers; 2400 bge_hostaddr etherStatsUndersizePkts; 2401 bge_hostaddr inRangeLengthError; 2402 bge_hostaddr outRangeLengthError; 2403 bge_hostaddr etherStatsPkts64Octets; 2404 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2405 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2406 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2407 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2408 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2409 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2410 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2411 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2412 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2413}; 2414 2415 2416/* Statistics maintained MAC Transmit block. */ 2417struct bge_tx_mac_stats { 2418 bge_hostaddr ifHCOutOctets; 2419 bge_hostaddr Reserved2; 2420 bge_hostaddr etherStatsCollisions; 2421 bge_hostaddr outXonSent; 2422 bge_hostaddr outXoffSent; 2423 bge_hostaddr flowControlDone; 2424 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2425 bge_hostaddr dot3StatsSingleCollisionFrames; 2426 bge_hostaddr dot3StatsMultipleCollisionFrames; 2427 bge_hostaddr dot3StatsDeferredTransmissions; 2428 bge_hostaddr Reserved3; 2429 bge_hostaddr dot3StatsExcessiveCollisions; 2430 bge_hostaddr dot3StatsLateCollisions; 2431 bge_hostaddr dot3Collided2Times; 2432 bge_hostaddr dot3Collided3Times; 2433 bge_hostaddr dot3Collided4Times; 2434 bge_hostaddr dot3Collided5Times; 2435 bge_hostaddr dot3Collided6Times; 2436 bge_hostaddr dot3Collided7Times; 2437 bge_hostaddr dot3Collided8Times; 2438 bge_hostaddr dot3Collided9Times; 2439 bge_hostaddr dot3Collided10Times; 2440 bge_hostaddr dot3Collided11Times; 2441 bge_hostaddr dot3Collided12Times; 2442 bge_hostaddr dot3Collided13Times; 2443 bge_hostaddr dot3Collided14Times; 2444 bge_hostaddr dot3Collided15Times; 2445 bge_hostaddr ifHCOutUcastPkts; 2446 bge_hostaddr ifHCOutMulticastPkts; 2447 bge_hostaddr ifHCOutBroadcastPkts; 2448 bge_hostaddr dot3StatsCarrierSenseErrors; 2449 bge_hostaddr ifOutDiscards; 2450 bge_hostaddr ifOutErrors; 2451}; 2452 2453/* Stats counters access through registers */ 2454struct bge_mac_stats { 2455 /* TX MAC statistics */ 2456 uint64_t ifHCOutOctets; 2457 uint64_t Reserved0; 2458 uint64_t etherStatsCollisions; 2459 uint64_t outXonSent; 2460 uint64_t outXoffSent; 2461 uint64_t Reserved1; 2462 uint64_t dot3StatsInternalMacTransmitErrors; 2463 uint64_t dot3StatsSingleCollisionFrames; 2464 uint64_t dot3StatsMultipleCollisionFrames; 2465 uint64_t dot3StatsDeferredTransmissions; 2466 uint64_t Reserved2; 2467 uint64_t dot3StatsExcessiveCollisions; 2468 uint64_t dot3StatsLateCollisions; 2469 uint64_t Reserved3[14]; 2470 uint64_t ifHCOutUcastPkts; 2471 uint64_t ifHCOutMulticastPkts; 2472 uint64_t ifHCOutBroadcastPkts; 2473 uint64_t Reserved4[2]; 2474 /* RX MAC statistics */ 2475 uint64_t ifHCInOctets; 2476 uint64_t Reserved5; 2477 uint64_t etherStatsFragments; 2478 uint64_t ifHCInUcastPkts; 2479 uint64_t ifHCInMulticastPkts; 2480 uint64_t ifHCInBroadcastPkts; 2481 uint64_t dot3StatsFCSErrors; 2482 uint64_t dot3StatsAlignmentErrors; 2483 uint64_t xonPauseFramesReceived; 2484 uint64_t xoffPauseFramesReceived; 2485 uint64_t macControlFramesReceived; 2486 uint64_t xoffStateEntered; 2487 uint64_t dot3StatsFramesTooLong; 2488 uint64_t etherStatsJabbers; 2489 uint64_t etherStatsUndersizePkts; 2490 /* Receive List Placement control */ 2491 uint64_t FramesDroppedDueToFilters; 2492 uint64_t DmaWriteQueueFull; 2493 uint64_t DmaWriteHighPriQueueFull; 2494 uint64_t NoMoreRxBDs; 2495 uint64_t InputDiscards; 2496 uint64_t InputErrors; 2497 uint64_t RecvThresholdHit; 2498}; 2499 2500struct bge_stats { 2501 uint8_t Reserved0[256]; 2502 2503 /* Statistics maintained by Receive MAC. */ 2504 struct bge_rx_mac_stats rxstats; 2505 2506 bge_hostaddr Unused1[37]; 2507 2508 /* Statistics maintained by Transmit MAC. */ 2509 struct bge_tx_mac_stats txstats; 2510 2511 bge_hostaddr Unused2[31]; 2512 2513 /* Statistics maintained by Receive List Placement. */ 2514 bge_hostaddr COSIfHCInPkts[16]; 2515 bge_hostaddr COSFramesDroppedDueToFilters; 2516 bge_hostaddr nicDmaWriteQueueFull; 2517 bge_hostaddr nicDmaWriteHighPriQueueFull; 2518 bge_hostaddr nicNoMoreRxBDs; 2519 bge_hostaddr ifInDiscards; 2520 bge_hostaddr ifInErrors; 2521 bge_hostaddr nicRecvThresholdHit; 2522 2523 bge_hostaddr Unused3[9]; 2524 2525 /* Statistics maintained by Send Data Initiator. */ 2526 bge_hostaddr COSIfHCOutPkts[16]; 2527 bge_hostaddr nicDmaReadQueueFull; 2528 bge_hostaddr nicDmaReadHighPriQueueFull; 2529 bge_hostaddr nicSendDataCompQueueFull; 2530 2531 /* Statistics maintained by Host Coalescing. */ 2532 bge_hostaddr nicRingSetSendProdIndex; 2533 bge_hostaddr nicRingStatusUpdate; 2534 bge_hostaddr nicInterrupts; 2535 bge_hostaddr nicAvoidedInterrupts; 2536 bge_hostaddr nicSendThresholdHit; 2537 2538 uint8_t Reserved4[320]; 2539}; 2540 2541/* 2542 * Tigon general information block. This resides in host memory 2543 * and contains the status counters, ring control blocks and 2544 * producer pointers. 2545 */ 2546 2547struct bge_gib { 2548 struct bge_stats bge_stats; 2549 struct bge_rcb bge_tx_rcb[16]; 2550 struct bge_rcb bge_std_rx_rcb; 2551 struct bge_rcb bge_jumbo_rx_rcb; 2552 struct bge_rcb bge_mini_rx_rcb; 2553 struct bge_rcb bge_return_rcb; 2554}; 2555 2556#define BGE_FRAMELEN 1518 2557#define BGE_MAX_FRAMELEN 1536 2558#define BGE_JUMBO_FRAMELEN 9018 2559#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2560#define BGE_MIN_FRAMELEN 60 2561 2562/* 2563 * Other utility macros. 2564 */ 2565#define BGE_INC(x, y) (x) = (x + 1) % y 2566 2567/* 2568 * Register access macros. The Tigon always uses memory mapped register 2569 * accesses and all registers must be accessed with 32 bit operations. 2570 */ 2571 2572#define CSR_WRITE_4(sc, reg, val) \ 2573 bus_write_4(sc->bge_res, reg, val) 2574 2575#define CSR_READ_4(sc, reg) \ 2576 bus_read_4(sc->bge_res, reg) 2577 2578#define BGE_SETBIT(sc, reg, x) \ 2579 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2580#define BGE_CLRBIT(sc, reg, x) \ 2581 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2582 2583#define PCI_SETBIT(dev, reg, x, s) \ 2584 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2585#define PCI_CLRBIT(dev, reg, x, s) \ 2586 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2587 2588/* 2589 * Memory management stuff. 2590 */ 2591 2592#define BGE_NSEG_JUMBO 4 2593#define BGE_NSEG_NEW 32 2594#define BGE_TSOSEG_SZ 4096 2595 2596/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2597#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2598#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2599#else 2600#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2601#endif 2602 2603#ifdef PAE 2604#define BGE_DMA_BNDRY 0x80000000 2605#else 2606#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2607#define BGE_DMA_BNDRY 0x100000000 2608#else 2609#define BGE_DMA_BNDRY 0 2610#endif 2611#endif 2612 2613/* 2614 * Ring structures. Most of these reside in host memory and we tell 2615 * the NIC where they are via the ring control blocks. The exceptions 2616 * are the tx and command rings, which live in NIC memory and which 2617 * we access via the shared memory window. 2618 */ 2619 2620struct bge_ring_data { 2621 struct bge_rx_bd *bge_rx_std_ring; 2622 bus_addr_t bge_rx_std_ring_paddr; 2623 struct bge_extrx_bd *bge_rx_jumbo_ring; 2624 bus_addr_t bge_rx_jumbo_ring_paddr; 2625 struct bge_rx_bd *bge_rx_return_ring; 2626 bus_addr_t bge_rx_return_ring_paddr; 2627 struct bge_tx_bd *bge_tx_ring; 2628 bus_addr_t bge_tx_ring_paddr; 2629 struct bge_status_block *bge_status_block; 2630 bus_addr_t bge_status_block_paddr; 2631 struct bge_stats *bge_stats; 2632 bus_addr_t bge_stats_paddr; 2633 struct bge_gib bge_info; 2634}; 2635 2636#define BGE_STD_RX_RING_SZ \ 2637 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2638#define BGE_JUMBO_RX_RING_SZ \ 2639 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2640#define BGE_TX_RING_SZ \ 2641 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2642#define BGE_RX_RTN_RING_SZ(x) \ 2643 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2644 2645#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2646 2647#define BGE_STATS_SZ sizeof (struct bge_stats) 2648 2649/* 2650 * Mbuf pointers. We need these to keep track of the virtual addresses 2651 * of our mbuf chains since we can only convert from physical to virtual, 2652 * not the other way around. 2653 */ 2654struct bge_chain_data { 2655 bus_dma_tag_t bge_parent_tag; 2656 bus_dma_tag_t bge_buffer_tag; 2657 bus_dma_tag_t bge_rx_std_ring_tag; 2658 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2659 bus_dma_tag_t bge_rx_return_ring_tag; 2660 bus_dma_tag_t bge_tx_ring_tag; 2661 bus_dma_tag_t bge_status_tag; 2662 bus_dma_tag_t bge_stats_tag; 2663 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2664 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2665 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2666 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2667 bus_dmamap_t bge_rx_std_sparemap; 2668 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2669 bus_dmamap_t bge_rx_jumbo_sparemap; 2670 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2671 bus_dmamap_t bge_rx_std_ring_map; 2672 bus_dmamap_t bge_rx_jumbo_ring_map; 2673 bus_dmamap_t bge_tx_ring_map; 2674 bus_dmamap_t bge_rx_return_ring_map; 2675 bus_dmamap_t bge_status_map; 2676 bus_dmamap_t bge_stats_map; 2677 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2678 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2679 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2680 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2681 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2682}; 2683 2684struct bge_dmamap_arg { 2685 bus_addr_t bge_busaddr; 2686}; 2687 2688#define BGE_HWREV_TIGON 0x01 2689#define BGE_HWREV_TIGON_II 0x02 2690#define BGE_TIMEOUT 100000 2691#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2692 2693struct bge_bcom_hack { 2694 int reg; 2695 int val; 2696}; 2697 2698#define ASF_ENABLE 1 2699#define ASF_NEW_HANDSHAKE 2 2700#define ASF_STACKUP 4 2701 2702struct bge_softc { 2703 struct ifnet *bge_ifp; /* interface info */ 2704 device_t bge_dev; 2705 struct mtx bge_mtx; 2706 device_t bge_miibus; 2707 void *bge_intrhand; 2708 struct resource *bge_irq; 2709 struct resource *bge_res; 2710 struct ifmedia bge_ifmedia; /* TBI media info */ 2711 int bge_expcap; 2712 int bge_msicap; 2713 int bge_pcixcap; 2714 uint32_t bge_flags; 2715#define BGE_FLAG_TBI 0x00000001 2716#define BGE_FLAG_JUMBO 0x00000002 2717#define BGE_FLAG_EADDR 0x00000008 2718#define BGE_FLAG_MII_SERDES 0x00000010 2719#define BGE_FLAG_CPMU_PRESENT 0x00000020 2720#define BGE_FLAG_MSI 0x00000100 2721#define BGE_FLAG_PCIX 0x00000200 2722#define BGE_FLAG_PCIE 0x00000400 2723#define BGE_FLAG_TSO 0x00000800 2724#define BGE_FLAG_5700_FAMILY 0x00010000 2725#define BGE_FLAG_5705_PLUS 0x00020000 2726#define BGE_FLAG_5714_FAMILY 0x00040000 2727#define BGE_FLAG_575X_PLUS 0x00080000 2728#define BGE_FLAG_5755_PLUS 0x00100000 2729#define BGE_FLAG_5788 0x00200000 2730#define BGE_FLAG_40BIT_BUG 0x01000000 2731#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2732#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2733#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2734 uint32_t bge_phy_flags; 2735#define BGE_PHY_WIRESPEED 0x00000001 2736#define BGE_PHY_ADC_BUG 0x00000002 2737#define BGE_PHY_5704_A0_BUG 0x00000004 2738#define BGE_PHY_JITTER_BUG 0x00000008 2739#define BGE_PHY_BER_BUG 0x00000010 2740#define BGE_PHY_ADJUST_TRIM 0x00000020 2741#define BGE_PHY_CRC_BUG 0x00000040 2742#define BGE_PHY_NO_3LED 0x00000080 2743 uint32_t bge_chipid; 2744 uint32_t bge_asicrev; 2745 uint32_t bge_chiprev; 2746 uint8_t bge_asf_mode; 2747 uint8_t bge_asf_count; 2748 struct bge_ring_data bge_ldata; /* rings */ 2749 struct bge_chain_data bge_cdata; /* mbufs */ 2750 uint16_t bge_tx_saved_considx; 2751 uint16_t bge_rx_saved_considx; 2752 uint16_t bge_ev_saved_considx; 2753 uint16_t bge_return_ring_cnt; 2754 uint16_t bge_std; /* current std ring head */ 2755 uint16_t bge_jumbo; /* current jumo ring head */ 2756 uint32_t bge_stat_ticks; 2757 uint32_t bge_rx_coal_ticks; 2758 uint32_t bge_tx_coal_ticks; 2759 uint32_t bge_tx_prodidx; 2760 uint32_t bge_rx_max_coal_bds; 2761 uint32_t bge_tx_max_coal_bds; 2762 uint32_t bge_mi_mode; 2763 int bge_if_flags; 2764 int bge_txcnt; 2765 int bge_link; /* link state */ 2766 int bge_link_evt; /* pending link event */ 2767 int bge_timer; 2768 int bge_forced_collapse; 2769 int bge_forced_udpcsum; 2770 int bge_csum_features; 2771 struct callout bge_stat_ch; 2772 uint32_t bge_rx_discards; 2773 uint32_t bge_tx_discards; 2774 uint32_t bge_tx_collisions; 2775#ifdef DEVICE_POLLING 2776 int rxcycles; 2777#endif /* DEVICE_POLLING */ 2778 struct bge_mac_stats bge_mac_stats; 2779 struct task bge_intr_task; 2780 struct taskqueue *bge_tq; 2781}; 2782 2783#define BGE_LOCK_INIT(_sc, _name) \ 2784 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2785#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2786#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2787#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2788#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2789