if_bgereg.h revision 214216
1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 214216 2010-10-22 18:31:44Z yongari $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 64166676Sjkim#define BGE_PAGE_ZERO 0x00000000 65166676Sjkim#define BGE_PAGE_ZERO_END 0x000000FF 66166676Sjkim#define BGE_SEND_RING_RCB 0x00000100 67166676Sjkim#define BGE_SEND_RING_RCB_END 0x000001FF 68166676Sjkim#define BGE_RX_RETURN_RING_RCB 0x00000200 69166676Sjkim#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70166676Sjkim#define BGE_STATS_BLOCK 0x00000300 71166676Sjkim#define BGE_STATS_BLOCK_END 0x00000AFF 72166676Sjkim#define BGE_STATUS_BLOCK 0x00000B00 73166676Sjkim#define BGE_STATUS_BLOCK_END 0x00000B4F 74166676Sjkim#define BGE_SOFTWARE_GENCOMM 0x00000B50 75166676Sjkim#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76166676Sjkim#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77166676Sjkim#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78166676Sjkim#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79166676Sjkim#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80166676Sjkim#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81166676Sjkim#define BGE_UNMAPPED 0x00001000 82166676Sjkim#define BGE_UNMAPPED_END 0x00001FFF 83166676Sjkim#define BGE_DMA_DESCRIPTORS 0x00002000 84166676Sjkim#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85166676Sjkim#define BGE_SEND_RING_1_TO_4 0x00004000 86166676Sjkim#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8784059Swpaul 88166676Sjkim/* Firmware interface */ 89166676Sjkim#define BGE_FW_DRV_ALIVE 0x00000001 90166676Sjkim#define BGE_FW_PAUSE 0x00000002 91166676Sjkim 9284059Swpaul/* Mappings for internal memory configuration */ 93166676Sjkim#define BGE_STD_RX_RINGS 0x00006000 94166676Sjkim#define BGE_STD_RX_RINGS_END 0x00006FFF 95166676Sjkim#define BGE_JUMBO_RX_RINGS 0x00007000 96166676Sjkim#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97166676Sjkim#define BGE_BUFFPOOL_1 0x00008000 98166676Sjkim#define BGE_BUFFPOOL_1_END 0x0000FFFF 99166676Sjkim#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 100166676Sjkim#define BGE_BUFFPOOL_2_END 0x00017FFF 101166676Sjkim#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 102166676Sjkim#define BGE_BUFFPOOL_3_END 0x0001FFFF 10384059Swpaul 10484059Swpaul/* Mappings for external SSRAM configurations */ 105166676Sjkim#define BGE_SEND_RING_5_TO_6 0x00006000 106166676Sjkim#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107166676Sjkim#define BGE_SEND_RING_7_TO_8 0x00007000 108166676Sjkim#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109166676Sjkim#define BGE_SEND_RING_9_TO_16 0x00008000 110166676Sjkim#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111166676Sjkim#define BGE_EXT_STD_RX_RINGS 0x0000C000 112166676Sjkim#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115166676Sjkim#define BGE_MINI_RX_RINGS 0x0000E000 116166676Sjkim#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117166676Sjkim#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 118166676Sjkim#define BGE_AVAIL_REGION1_END 0x00017FFF 119166676Sjkim#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 120166676Sjkim#define BGE_AVAIL_REGION2_END 0x0001FFFF 121166676Sjkim#define BGE_EXT_SSRAM 0x00020000 122166676Sjkim#define BGE_EXT_SSRAM_END 0x000FFFFF 12384059Swpaul 12484059Swpaul 12584059Swpaul/* 12684059Swpaul * BCM570x register offsets. These are memory mapped registers 12784059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12884059Swpaul * Each register must be accessed using 32 bit operations. 12984059Swpaul * 13084059Swpaul * All registers are accessed through a 32K shared memory block. 13184059Swpaul * The first group of registers are actually copies of the PCI 13284059Swpaul * configuration space registers. 13384059Swpaul */ 13484059Swpaul 13584059Swpaul/* 13684059Swpaul * PCI registers defined in the PCI 2.2 spec. 13784059Swpaul */ 138166676Sjkim#define BGE_PCI_VID 0x00 139166676Sjkim#define BGE_PCI_DID 0x02 140166676Sjkim#define BGE_PCI_CMD 0x04 141166676Sjkim#define BGE_PCI_STS 0x06 142166676Sjkim#define BGE_PCI_REV 0x08 143166676Sjkim#define BGE_PCI_CLASS 0x09 144166676Sjkim#define BGE_PCI_CACHESZ 0x0C 145166676Sjkim#define BGE_PCI_LATTIMER 0x0D 146166676Sjkim#define BGE_PCI_HDRTYPE 0x0E 147166676Sjkim#define BGE_PCI_BIST 0x0F 148166676Sjkim#define BGE_PCI_BAR0 0x10 149166676Sjkim#define BGE_PCI_BAR1 0x14 150166676Sjkim#define BGE_PCI_SUBSYS 0x2C 151166676Sjkim#define BGE_PCI_SUBVID 0x2E 152166676Sjkim#define BGE_PCI_ROMBASE 0x30 153166676Sjkim#define BGE_PCI_CAPPTR 0x34 154166676Sjkim#define BGE_PCI_INTLINE 0x3C 155166676Sjkim#define BGE_PCI_INTPIN 0x3D 156166676Sjkim#define BGE_PCI_MINGNT 0x3E 157166676Sjkim#define BGE_PCI_MAXLAT 0x3F 158166676Sjkim#define BGE_PCI_PCIXCAP 0x40 159166676Sjkim#define BGE_PCI_NEXTPTR_PM 0x41 160166676Sjkim#define BGE_PCI_PCIX_CMD 0x42 161166676Sjkim#define BGE_PCI_PCIX_STS 0x44 162166676Sjkim#define BGE_PCI_PWRMGMT_CAPID 0x48 163166676Sjkim#define BGE_PCI_NEXTPTR_VPD 0x49 164166676Sjkim#define BGE_PCI_PWRMGMT_CAPS 0x4A 165166676Sjkim#define BGE_PCI_PWRMGMT_CMD 0x4C 166166676Sjkim#define BGE_PCI_PWRMGMT_STS 0x4D 167166676Sjkim#define BGE_PCI_PWRMGMT_DATA 0x4F 168166676Sjkim#define BGE_PCI_VPD_CAPID 0x50 169166676Sjkim#define BGE_PCI_NEXTPTR_MSI 0x51 170166676Sjkim#define BGE_PCI_VPD_ADDR 0x52 171166676Sjkim#define BGE_PCI_VPD_DATA 0x54 172166676Sjkim#define BGE_PCI_MSI_CAPID 0x58 173166676Sjkim#define BGE_PCI_NEXTPTR_NONE 0x59 174166676Sjkim#define BGE_PCI_MSI_CTL 0x5A 175166676Sjkim#define BGE_PCI_MSI_ADDR_HI 0x5C 176166676Sjkim#define BGE_PCI_MSI_ADDR_LO 0x60 177166676Sjkim#define BGE_PCI_MSI_DATA 0x64 17884059Swpaul 179190194Smarius/* 180190194Smarius * PCI Express definitions 181190194Smarius * According to 182190194Smarius * PCI Express base specification, REV. 1.0a 183190194Smarius */ 184190194Smarius 185190194Smarius/* PCI Express device control, 16bits */ 186190194Smarius#define BGE_PCIE_DEVCTL 0x08 187190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194190194Smarius 195135772Sps/* PCI MSI. ??? */ 196166676Sjkim#define BGE_PCIE_CAPID_REG 0xD0 197166676Sjkim#define BGE_PCIE_CAPID 0x10 198135772Sps 19984059Swpaul/* 20084059Swpaul * PCI registers specific to the BCM570x family. 20184059Swpaul */ 202166676Sjkim#define BGE_PCI_MISC_CTL 0x68 203166676Sjkim#define BGE_PCI_DMA_RW_CTL 0x6C 204166676Sjkim#define BGE_PCI_PCISTATE 0x70 205166676Sjkim#define BGE_PCI_CLKCTL 0x74 206166676Sjkim#define BGE_PCI_REG_BASEADDR 0x78 207166676Sjkim#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208166676Sjkim#define BGE_PCI_REG_DATA 0x80 209166676Sjkim#define BGE_PCI_MEMWIN_DATA 0x84 210166676Sjkim#define BGE_PCI_MODECTL 0x88 211166676Sjkim#define BGE_PCI_MISC_CFG 0x8C 212166676Sjkim#define BGE_PCI_MISC_LOCALCTL 0x90 213166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219166676Sjkim#define BGE_PCI_ISR_MBX_HI 0xB0 220166676Sjkim#define BGE_PCI_ISR_MBX_LO 0xB4 221197832Sstas#define BGE_PCI_PRODID_ASICREV 0xBC 22284059Swpaul 22384059Swpaul/* PCI Misc. Host control register */ 224166676Sjkim#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 225166676Sjkim#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 226166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 227166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 228166676Sjkim#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 229166676Sjkim#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 230166676Sjkim#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 231166676Sjkim#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 232166676Sjkim#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 233197832Sstas#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 23484059Swpaul 235166676Sjkim#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 236153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 237166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 238153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME| \ 239153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 240153437Syongari#else 241166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 242153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 243153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 244153437Syongari#endif 24584059Swpaul 246166676Sjkim#define BGE_INIT \ 247153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 248153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 24984059Swpaul 250197832Sstas#define BGE_CHIPID_TIGON_I 0x4000 251197832Sstas#define BGE_CHIPID_TIGON_II 0x6000 252197832Sstas#define BGE_CHIPID_BCM5700_A0 0x7000 253197832Sstas#define BGE_CHIPID_BCM5700_A1 0x7001 254197832Sstas#define BGE_CHIPID_BCM5700_B0 0x7100 255197832Sstas#define BGE_CHIPID_BCM5700_B1 0x7101 256197832Sstas#define BGE_CHIPID_BCM5700_B2 0x7102 257197832Sstas#define BGE_CHIPID_BCM5700_B3 0x7103 258197832Sstas#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 259197832Sstas#define BGE_CHIPID_BCM5700_C0 0x7200 260197832Sstas#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 261197832Sstas#define BGE_CHIPID_BCM5701_B0 0x0100 262197832Sstas#define BGE_CHIPID_BCM5701_B2 0x0102 263197832Sstas#define BGE_CHIPID_BCM5701_B5 0x0105 264197832Sstas#define BGE_CHIPID_BCM5703_A0 0x1000 265197832Sstas#define BGE_CHIPID_BCM5703_A1 0x1001 266197832Sstas#define BGE_CHIPID_BCM5703_A2 0x1002 267197832Sstas#define BGE_CHIPID_BCM5703_A3 0x1003 268197832Sstas#define BGE_CHIPID_BCM5703_B0 0x1100 269197832Sstas#define BGE_CHIPID_BCM5704_A0 0x2000 270197832Sstas#define BGE_CHIPID_BCM5704_A1 0x2001 271197832Sstas#define BGE_CHIPID_BCM5704_A2 0x2002 272197832Sstas#define BGE_CHIPID_BCM5704_A3 0x2003 273197832Sstas#define BGE_CHIPID_BCM5704_B0 0x2100 274197832Sstas#define BGE_CHIPID_BCM5705_A0 0x3000 275197832Sstas#define BGE_CHIPID_BCM5705_A1 0x3001 276197832Sstas#define BGE_CHIPID_BCM5705_A2 0x3002 277197832Sstas#define BGE_CHIPID_BCM5705_A3 0x3003 278197832Sstas#define BGE_CHIPID_BCM5750_A0 0x4000 279197832Sstas#define BGE_CHIPID_BCM5750_A1 0x4001 280197832Sstas#define BGE_CHIPID_BCM5750_A3 0x4000 281197832Sstas#define BGE_CHIPID_BCM5750_B0 0x4100 282197832Sstas#define BGE_CHIPID_BCM5750_B1 0x4101 283197832Sstas#define BGE_CHIPID_BCM5750_C0 0x4200 284197832Sstas#define BGE_CHIPID_BCM5750_C1 0x4201 285197832Sstas#define BGE_CHIPID_BCM5750_C2 0x4202 286197832Sstas#define BGE_CHIPID_BCM5714_A0 0x5000 287197832Sstas#define BGE_CHIPID_BCM5752_A0 0x6000 288197832Sstas#define BGE_CHIPID_BCM5752_A1 0x6001 289197832Sstas#define BGE_CHIPID_BCM5752_A2 0x6002 290197832Sstas#define BGE_CHIPID_BCM5714_B0 0x8000 291197832Sstas#define BGE_CHIPID_BCM5714_B3 0x8003 292197832Sstas#define BGE_CHIPID_BCM5715_A0 0x9000 293197832Sstas#define BGE_CHIPID_BCM5715_A1 0x9001 294197832Sstas#define BGE_CHIPID_BCM5715_A3 0x9003 295197832Sstas#define BGE_CHIPID_BCM5755_A0 0xa000 296197832Sstas#define BGE_CHIPID_BCM5755_A1 0xa001 297197832Sstas#define BGE_CHIPID_BCM5755_A2 0xa002 298197832Sstas#define BGE_CHIPID_BCM5722_A0 0xa200 299197832Sstas#define BGE_CHIPID_BCM5754_A0 0xb000 300197832Sstas#define BGE_CHIPID_BCM5754_A1 0xb001 301197832Sstas#define BGE_CHIPID_BCM5754_A2 0xb002 302197832Sstas#define BGE_CHIPID_BCM5761_A0 0x5761000 303197832Sstas#define BGE_CHIPID_BCM5761_A1 0x5761100 304197832Sstas#define BGE_CHIPID_BCM5784_A0 0x5784000 305197832Sstas#define BGE_CHIPID_BCM5784_A1 0x5784100 306197832Sstas#define BGE_CHIPID_BCM5787_A0 0xb000 307197832Sstas#define BGE_CHIPID_BCM5787_A1 0xb001 308197832Sstas#define BGE_CHIPID_BCM5787_A2 0xb002 309197832Sstas#define BGE_CHIPID_BCM5906_A1 0xc001 310197832Sstas#define BGE_CHIPID_BCM5906_A2 0xc002 311197832Sstas#define BGE_CHIPID_BCM57780_A0 0x57780000 312197832Sstas#define BGE_CHIPID_BCM57780_A1 0x57780001 31384059Swpaul 31493751Swpaul/* shorthand one */ 315197832Sstas#define BGE_ASICREV(x) ((x) >> 12) 316166676Sjkim#define BGE_ASICREV_BCM5701 0x00 317166676Sjkim#define BGE_ASICREV_BCM5703 0x01 318166676Sjkim#define BGE_ASICREV_BCM5704 0x02 319166676Sjkim#define BGE_ASICREV_BCM5705 0x03 320166676Sjkim#define BGE_ASICREV_BCM5750 0x04 321166676Sjkim#define BGE_ASICREV_BCM5714_A0 0x05 322166676Sjkim#define BGE_ASICREV_BCM5752 0x06 323166676Sjkim#define BGE_ASICREV_BCM5700 0x07 324166676Sjkim#define BGE_ASICREV_BCM5780 0x08 325166676Sjkim#define BGE_ASICREV_BCM5714 0x09 326166676Sjkim#define BGE_ASICREV_BCM5755 0x0a 327166676Sjkim#define BGE_ASICREV_BCM5754 0x0b 328166676Sjkim#define BGE_ASICREV_BCM5787 0x0b 329178667Sjhb#define BGE_ASICREV_BCM5906 0x0c 330197832Sstas/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 331197832Sstas#define BGE_ASICREV_USE_PRODID_REG 0x0f 332197832Sstas/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 333197832Sstas#define BGE_ASICREV_BCM5761 0x5761 334197832Sstas#define BGE_ASICREV_BCM5784 0x5784 335197832Sstas#define BGE_ASICREV_BCM5785 0x5785 336197832Sstas#define BGE_ASICREV_BCM57780 0x57780 33793751Swpaul 338114813Sps/* chip revisions */ 339197832Sstas#define BGE_CHIPREV(x) ((x) >> 8) 340166676Sjkim#define BGE_CHIPREV_5700_AX 0x70 341166676Sjkim#define BGE_CHIPREV_5700_BX 0x71 342166676Sjkim#define BGE_CHIPREV_5700_CX 0x72 343166676Sjkim#define BGE_CHIPREV_5701_AX 0x00 344166676Sjkim#define BGE_CHIPREV_5703_AX 0x10 345166676Sjkim#define BGE_CHIPREV_5704_AX 0x20 346166676Sjkim#define BGE_CHIPREV_5704_BX 0x21 347166676Sjkim#define BGE_CHIPREV_5750_AX 0x40 348166676Sjkim#define BGE_CHIPREV_5750_BX 0x41 349197832Sstas/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 350197832Sstas#define BGE_CHIPREV_5761_AX 0x57611 351197832Sstas#define BGE_CHIPREV_5784_AX 0x57841 352114813Sps 35384059Swpaul/* PCI DMA Read/Write Control register */ 354166676Sjkim#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 355166676Sjkim#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 356166676Sjkim#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 357169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 358169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 359169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 360166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 361166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 362166676Sjkim#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 363166676Sjkim#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 364166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 365166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 36684059Swpaul 367166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 368166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 369166676Sjkim#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 370166676Sjkim#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 37184059Swpaul 372166676Sjkim#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 373166676Sjkim#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 374166676Sjkim#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 375166676Sjkim#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 376166676Sjkim#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 377166676Sjkim#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 378166676Sjkim#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 379166676Sjkim#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 38084059Swpaul 381166676Sjkim#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 382166676Sjkim#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 383166676Sjkim#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 384166676Sjkim#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 385166676Sjkim#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 386166676Sjkim#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 387166676Sjkim#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 388166676Sjkim#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 389166676Sjkim 39084059Swpaul/* 39184059Swpaul * PCI state register -- note, this register is read only 39284059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 39384059Swpaul * register is set. 39484059Swpaul */ 395166676Sjkim#define BGE_PCISTATE_FORCE_RESET 0x00000001 396166676Sjkim#define BGE_PCISTATE_INTR_STATE 0x00000002 397166676Sjkim#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 398166676Sjkim#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 399166676Sjkim#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 400166676Sjkim#define BGE_PCISTATE_WANT_EXPROM 0x00000020 401166676Sjkim#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 402166676Sjkim#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 403166676Sjkim#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 40484059Swpaul 40584059Swpaul/* 40684059Swpaul * PCI Clock Control register -- note, this register is read only 40784059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 40884059Swpaul * register is set. 40984059Swpaul */ 410166676Sjkim#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 411166676Sjkim#define BGE_PCICLOCKCTL_M66EN 0x00000080 412166676Sjkim#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 413166676Sjkim#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 414166676Sjkim#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 415166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 416166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 417166676Sjkim#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 418166676Sjkim#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 419166676Sjkim#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 42084059Swpaul 42184059Swpaul 42284059Swpaul#ifndef PCIM_CMD_MWIEN 423166676Sjkim#define PCIM_CMD_MWIEN 0x0010 42484059Swpaul#endif 425190319Smarius#ifndef PCIM_CMD_INTxDIS 426190319Smarius#define PCIM_CMD_INTxDIS 0x0400 427190319Smarius#endif 42884059Swpaul 42984059Swpaul/* 43084059Swpaul * High priority mailbox registers 43184059Swpaul * Each mailbox is 64-bits wide, though we only use the 43284059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 43384059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 43484059Swpaul * has been updated. 43584059Swpaul */ 436166676Sjkim#define BGE_MBX_IRQ0_HI 0x0200 437166676Sjkim#define BGE_MBX_IRQ0_LO 0x0204 438166676Sjkim#define BGE_MBX_IRQ1_HI 0x0208 439166676Sjkim#define BGE_MBX_IRQ1_LO 0x020C 440166676Sjkim#define BGE_MBX_IRQ2_HI 0x0210 441166676Sjkim#define BGE_MBX_IRQ2_LO 0x0214 442166676Sjkim#define BGE_MBX_IRQ3_HI 0x0218 443166676Sjkim#define BGE_MBX_IRQ3_LO 0x021C 444166676Sjkim#define BGE_MBX_GEN0_HI 0x0220 445166676Sjkim#define BGE_MBX_GEN0_LO 0x0224 446166676Sjkim#define BGE_MBX_GEN1_HI 0x0228 447166676Sjkim#define BGE_MBX_GEN1_LO 0x022C 448166676Sjkim#define BGE_MBX_GEN2_HI 0x0230 449166676Sjkim#define BGE_MBX_GEN2_LO 0x0234 450166676Sjkim#define BGE_MBX_GEN3_HI 0x0228 451166676Sjkim#define BGE_MBX_GEN3_LO 0x022C 452166676Sjkim#define BGE_MBX_GEN4_HI 0x0240 453166676Sjkim#define BGE_MBX_GEN4_LO 0x0244 454166676Sjkim#define BGE_MBX_GEN5_HI 0x0248 455166676Sjkim#define BGE_MBX_GEN5_LO 0x024C 456166676Sjkim#define BGE_MBX_GEN6_HI 0x0250 457166676Sjkim#define BGE_MBX_GEN6_LO 0x0254 458166676Sjkim#define BGE_MBX_GEN7_HI 0x0258 459166676Sjkim#define BGE_MBX_GEN7_LO 0x025C 460166676Sjkim#define BGE_MBX_RELOAD_STATS_HI 0x0260 461166676Sjkim#define BGE_MBX_RELOAD_STATS_LO 0x0264 462166676Sjkim#define BGE_MBX_RX_STD_PROD_HI 0x0268 463166676Sjkim#define BGE_MBX_RX_STD_PROD_LO 0x026C 464166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 465166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 466166676Sjkim#define BGE_MBX_RX_MINI_PROD_HI 0x0278 467166676Sjkim#define BGE_MBX_RX_MINI_PROD_LO 0x027C 468166676Sjkim#define BGE_MBX_RX_CONS0_HI 0x0280 469166676Sjkim#define BGE_MBX_RX_CONS0_LO 0x0284 470166676Sjkim#define BGE_MBX_RX_CONS1_HI 0x0288 471166676Sjkim#define BGE_MBX_RX_CONS1_LO 0x028C 472166676Sjkim#define BGE_MBX_RX_CONS2_HI 0x0290 473166676Sjkim#define BGE_MBX_RX_CONS2_LO 0x0294 474166676Sjkim#define BGE_MBX_RX_CONS3_HI 0x0298 475166676Sjkim#define BGE_MBX_RX_CONS3_LO 0x029C 476166676Sjkim#define BGE_MBX_RX_CONS4_HI 0x02A0 477166676Sjkim#define BGE_MBX_RX_CONS4_LO 0x02A4 478166676Sjkim#define BGE_MBX_RX_CONS5_HI 0x02A8 479166676Sjkim#define BGE_MBX_RX_CONS5_LO 0x02AC 480166676Sjkim#define BGE_MBX_RX_CONS6_HI 0x02B0 481166676Sjkim#define BGE_MBX_RX_CONS6_LO 0x02B4 482166676Sjkim#define BGE_MBX_RX_CONS7_HI 0x02B8 483166676Sjkim#define BGE_MBX_RX_CONS7_LO 0x02BC 484166676Sjkim#define BGE_MBX_RX_CONS8_HI 0x02C0 485166676Sjkim#define BGE_MBX_RX_CONS8_LO 0x02C4 486166676Sjkim#define BGE_MBX_RX_CONS9_HI 0x02C8 487166676Sjkim#define BGE_MBX_RX_CONS9_LO 0x02CC 488166676Sjkim#define BGE_MBX_RX_CONS10_HI 0x02D0 489166676Sjkim#define BGE_MBX_RX_CONS10_LO 0x02D4 490166676Sjkim#define BGE_MBX_RX_CONS11_HI 0x02D8 491166676Sjkim#define BGE_MBX_RX_CONS11_LO 0x02DC 492166676Sjkim#define BGE_MBX_RX_CONS12_HI 0x02E0 493166676Sjkim#define BGE_MBX_RX_CONS12_LO 0x02E4 494166676Sjkim#define BGE_MBX_RX_CONS13_HI 0x02E8 495166676Sjkim#define BGE_MBX_RX_CONS13_LO 0x02EC 496166676Sjkim#define BGE_MBX_RX_CONS14_HI 0x02F0 497166676Sjkim#define BGE_MBX_RX_CONS14_LO 0x02F4 498166676Sjkim#define BGE_MBX_RX_CONS15_HI 0x02F8 499166676Sjkim#define BGE_MBX_RX_CONS15_LO 0x02FC 500166676Sjkim#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 501166676Sjkim#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 502166676Sjkim#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 503166676Sjkim#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 504166676Sjkim#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 505166676Sjkim#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 506166676Sjkim#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 507166676Sjkim#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 508166676Sjkim#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 509166676Sjkim#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 510166676Sjkim#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 511166676Sjkim#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 512166676Sjkim#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 513166676Sjkim#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 514166676Sjkim#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 515166676Sjkim#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 516166676Sjkim#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 517166676Sjkim#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 518166676Sjkim#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 519166676Sjkim#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 520166676Sjkim#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 521166676Sjkim#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 522166676Sjkim#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 523166676Sjkim#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 524166676Sjkim#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 525166676Sjkim#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 526166676Sjkim#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 527166676Sjkim#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 528166676Sjkim#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 529166676Sjkim#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 530166676Sjkim#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 531166676Sjkim#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 532166676Sjkim#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 533166676Sjkim#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 534166676Sjkim#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 535166676Sjkim#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 536166676Sjkim#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 537166676Sjkim#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 538166676Sjkim#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 539166676Sjkim#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 540166676Sjkim#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 541166676Sjkim#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 542166676Sjkim#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 543166676Sjkim#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 544166676Sjkim#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 545166676Sjkim#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 546166676Sjkim#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 547166676Sjkim#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 548166676Sjkim#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 549166676Sjkim#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 550166676Sjkim#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 551166676Sjkim#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 552166676Sjkim#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 553166676Sjkim#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 554166676Sjkim#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 555166676Sjkim#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 556166676Sjkim#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 557166676Sjkim#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 558166676Sjkim#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 559166676Sjkim#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 560166676Sjkim#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 561166676Sjkim#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 562166676Sjkim#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 563166676Sjkim#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 56484059Swpaul 565166676Sjkim#define BGE_TX_RINGS_MAX 4 566166676Sjkim#define BGE_TX_RINGS_EXTSSRAM_MAX 16 567166676Sjkim#define BGE_RX_RINGS_MAX 16 56884059Swpaul 56984059Swpaul/* Ethernet MAC control registers */ 570166676Sjkim#define BGE_MAC_MODE 0x0400 571166676Sjkim#define BGE_MAC_STS 0x0404 572166676Sjkim#define BGE_MAC_EVT_ENB 0x0408 573166676Sjkim#define BGE_MAC_LED_CTL 0x040C 574166676Sjkim#define BGE_MAC_ADDR1_LO 0x0410 575166676Sjkim#define BGE_MAC_ADDR1_HI 0x0414 576166676Sjkim#define BGE_MAC_ADDR2_LO 0x0418 577166676Sjkim#define BGE_MAC_ADDR2_HI 0x041C 578166676Sjkim#define BGE_MAC_ADDR3_LO 0x0420 579166676Sjkim#define BGE_MAC_ADDR3_HI 0x0424 580166676Sjkim#define BGE_MAC_ADDR4_LO 0x0428 581166676Sjkim#define BGE_MAC_ADDR4_HI 0x042C 582166676Sjkim#define BGE_WOL_PATPTR 0x0430 583166676Sjkim#define BGE_WOL_PATCFG 0x0434 584166676Sjkim#define BGE_TX_RANDOM_BACKOFF 0x0438 585166676Sjkim#define BGE_RX_MTU 0x043C 586166676Sjkim#define BGE_GBIT_PCS_TEST 0x0440 587166676Sjkim#define BGE_TX_TBI_AUTONEG 0x0444 588166676Sjkim#define BGE_RX_TBI_AUTONEG 0x0448 589166676Sjkim#define BGE_MI_COMM 0x044C 590166676Sjkim#define BGE_MI_STS 0x0450 591166676Sjkim#define BGE_MI_MODE 0x0454 592166676Sjkim#define BGE_AUTOPOLL_STS 0x0458 593166676Sjkim#define BGE_TX_MODE 0x045C 594166676Sjkim#define BGE_TX_STS 0x0460 595166676Sjkim#define BGE_TX_LENGTHS 0x0464 596166676Sjkim#define BGE_RX_MODE 0x0468 597166676Sjkim#define BGE_RX_STS 0x046C 598166676Sjkim#define BGE_MAR0 0x0470 599166676Sjkim#define BGE_MAR1 0x0474 600166676Sjkim#define BGE_MAR2 0x0478 601166676Sjkim#define BGE_MAR3 0x047C 602166676Sjkim#define BGE_RX_BD_RULES_CTL0 0x0480 603166676Sjkim#define BGE_RX_BD_RULES_MASKVAL0 0x0484 604166676Sjkim#define BGE_RX_BD_RULES_CTL1 0x0488 605166676Sjkim#define BGE_RX_BD_RULES_MASKVAL1 0x048C 606166676Sjkim#define BGE_RX_BD_RULES_CTL2 0x0490 607166676Sjkim#define BGE_RX_BD_RULES_MASKVAL2 0x0494 608166676Sjkim#define BGE_RX_BD_RULES_CTL3 0x0498 609166676Sjkim#define BGE_RX_BD_RULES_MASKVAL3 0x049C 610166676Sjkim#define BGE_RX_BD_RULES_CTL4 0x04A0 611166676Sjkim#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 612166676Sjkim#define BGE_RX_BD_RULES_CTL5 0x04A8 613166676Sjkim#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 614166676Sjkim#define BGE_RX_BD_RULES_CTL6 0x04B0 615166676Sjkim#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 616166676Sjkim#define BGE_RX_BD_RULES_CTL7 0x04B8 617166676Sjkim#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 618166676Sjkim#define BGE_RX_BD_RULES_CTL8 0x04C0 619166676Sjkim#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 620166676Sjkim#define BGE_RX_BD_RULES_CTL9 0x04C8 621166676Sjkim#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 622166676Sjkim#define BGE_RX_BD_RULES_CTL10 0x04D0 623166676Sjkim#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 624166676Sjkim#define BGE_RX_BD_RULES_CTL11 0x04D8 625166676Sjkim#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 626166676Sjkim#define BGE_RX_BD_RULES_CTL12 0x04E0 627166676Sjkim#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 628166676Sjkim#define BGE_RX_BD_RULES_CTL13 0x04E8 629166676Sjkim#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 630166676Sjkim#define BGE_RX_BD_RULES_CTL14 0x04F0 631166676Sjkim#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 632166676Sjkim#define BGE_RX_BD_RULES_CTL15 0x04F8 633166676Sjkim#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 634166676Sjkim#define BGE_RX_RULES_CFG 0x0500 635213255Syongari#define BGE_MAX_RX_FRAME_LOWAT 0x0504 636166676Sjkim#define BGE_SERDES_CFG 0x0590 637166676Sjkim#define BGE_SERDES_STS 0x0594 638166676Sjkim#define BGE_SGDIG_CFG 0x05B0 639166676Sjkim#define BGE_SGDIG_STS 0x05B4 640213283Syongari#define BGE_TX_MAC_STATS_OCTETS 0x0800 641213283Syongari#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 642213283Syongari#define BGE_TX_MAC_STATS_COLLS 0x0808 643213283Syongari#define BGE_TX_MAC_STATS_XON_SENT 0x080C 644213283Syongari#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 645213283Syongari#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 646213283Syongari#define BGE_TX_MAC_STATS_ERRORS 0x0818 647213283Syongari#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 648213283Syongari#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 649213283Syongari#define BGE_TX_MAC_STATS_DEFERRED 0x0824 650213283Syongari#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 651213283Syongari#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 652213283Syongari#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 653213283Syongari#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 654213283Syongari#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 655213283Syongari#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 656213283Syongari#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 657213283Syongari#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 658213283Syongari#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 659213283Syongari#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 660213283Syongari#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 661213283Syongari#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 662213283Syongari#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 663213283Syongari#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 664213283Syongari#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 665213283Syongari#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 666213283Syongari#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 667213283Syongari#define BGE_TX_MAC_STATS_UCAST 0x086C 668213283Syongari#define BGE_TX_MAC_STATS_MCAST 0x0870 669213283Syongari#define BGE_TX_MAC_STATS_BCAST 0x0874 670213283Syongari#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 671213283Syongari#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 672213283Syongari#define BGE_RX_MAC_STATS_OCTESTS 0x0880 673213283Syongari#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 674213283Syongari#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 675213283Syongari#define BGE_RX_MAC_STATS_UCAST 0x088C 676213283Syongari#define BGE_RX_MAC_STATS_MCAST 0x0890 677213283Syongari#define BGE_RX_MAC_STATS_BCAST 0x0894 678213283Syongari#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 679213283Syongari#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 680213283Syongari#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 681213283Syongari#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 682213283Syongari#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 683213283Syongari#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 684213283Syongari#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 685213283Syongari#define BGE_RX_MAC_STATS_JABBERS 0x08B4 686213283Syongari#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 68784059Swpaul 68884059Swpaul/* Ethernet MAC Mode register */ 689166676Sjkim#define BGE_MACMODE_RESET 0x00000001 690166676Sjkim#define BGE_MACMODE_HALF_DUPLEX 0x00000002 691166676Sjkim#define BGE_MACMODE_PORTMODE 0x0000000C 692166676Sjkim#define BGE_MACMODE_LOOPBACK 0x00000010 693166676Sjkim#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 694166676Sjkim#define BGE_MACMODE_TX_BURST_ENB 0x00000100 695166676Sjkim#define BGE_MACMODE_MAX_DEFER 0x00000200 696166676Sjkim#define BGE_MACMODE_LINK_POLARITY 0x00000400 697166676Sjkim#define BGE_MACMODE_RX_STATS_ENB 0x00000800 698166676Sjkim#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 699166676Sjkim#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 700166676Sjkim#define BGE_MACMODE_TX_STATS_ENB 0x00004000 701166676Sjkim#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 702166676Sjkim#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 703166676Sjkim#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 704166676Sjkim#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 705166676Sjkim#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 706166676Sjkim#define BGE_MACMODE_MIP_ENB 0x00100000 707166676Sjkim#define BGE_MACMODE_TXDMA_ENB 0x00200000 708166676Sjkim#define BGE_MACMODE_RXDMA_ENB 0x00400000 709166676Sjkim#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 71084059Swpaul 711166676Sjkim#define BGE_PORTMODE_NONE 0x00000000 712166676Sjkim#define BGE_PORTMODE_MII 0x00000004 713166676Sjkim#define BGE_PORTMODE_GMII 0x00000008 714166676Sjkim#define BGE_PORTMODE_TBI 0x0000000C 71584059Swpaul 71684059Swpaul/* MAC Status register */ 717166676Sjkim#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 718166676Sjkim#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 719166676Sjkim#define BGE_MACSTAT_RX_CFG 0x00000004 720166676Sjkim#define BGE_MACSTAT_CFG_CHANGED 0x00000008 721166676Sjkim#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 722166676Sjkim#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 723166676Sjkim#define BGE_MACSTAT_LINK_CHANGED 0x00001000 724166676Sjkim#define BGE_MACSTAT_MI_COMPLETE 0x00400000 725166676Sjkim#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 726166676Sjkim#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 727166676Sjkim#define BGE_MACSTAT_ODI_ERROR 0x02000000 728166676Sjkim#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 729166676Sjkim#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 73084059Swpaul 73184059Swpaul/* MAC Event Enable Register */ 732166676Sjkim#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 733166676Sjkim#define BGE_EVTENB_LINK_CHANGED 0x00001000 734166676Sjkim#define BGE_EVTENB_MI_COMPLETE 0x00400000 735166676Sjkim#define BGE_EVTENB_MI_INTERRUPT 0x00800000 736166676Sjkim#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 737166676Sjkim#define BGE_EVTENB_ODI_ERROR 0x02000000 738166676Sjkim#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 739166676Sjkim#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 74084059Swpaul 74184059Swpaul/* LED Control Register */ 742166676Sjkim#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 743166676Sjkim#define BGE_LEDCTL_1000MBPS_LED 0x00000002 744166676Sjkim#define BGE_LEDCTL_100MBPS_LED 0x00000004 745166676Sjkim#define BGE_LEDCTL_10MBPS_LED 0x00000008 746166676Sjkim#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 747166676Sjkim#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 748166676Sjkim#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 749166676Sjkim#define BGE_LEDCTL_1000MBPS_STS 0x00000080 750166676Sjkim#define BGE_LEDCTL_100MBPS_STS 0x00000100 751166676Sjkim#define BGE_LEDCTL_10MBPS_STS 0x00000200 752166676Sjkim#define BGE_LEDCTL_TRADLED_STS 0x00000400 753166676Sjkim#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 754166676Sjkim#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 75584059Swpaul 75684059Swpaul/* TX backoff seed register */ 757166676Sjkim#define BGE_TX_BACKOFF_SEED_MASK 0x3F 75884059Swpaul 75984059Swpaul/* Autopoll status register */ 760166676Sjkim#define BGE_AUTOPOLLSTS_ERROR 0x00000001 76184059Swpaul 76284059Swpaul/* Transmit MAC mode register */ 763166676Sjkim#define BGE_TXMODE_RESET 0x00000001 764166676Sjkim#define BGE_TXMODE_ENABLE 0x00000002 765166676Sjkim#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 766166676Sjkim#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 767166676Sjkim#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 768214216Syongari#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 76984059Swpaul 77084059Swpaul/* Transmit MAC status register */ 771166676Sjkim#define BGE_TXSTAT_RX_XOFFED 0x00000001 772166676Sjkim#define BGE_TXSTAT_SENT_XOFF 0x00000002 773166676Sjkim#define BGE_TXSTAT_SENT_XON 0x00000004 774166676Sjkim#define BGE_TXSTAT_LINK_UP 0x00000008 775166676Sjkim#define BGE_TXSTAT_ODI_UFLOW 0x00000010 776166676Sjkim#define BGE_TXSTAT_ODI_OFLOW 0x00000020 77784059Swpaul 77884059Swpaul/* Transmit MAC lengths register */ 779166676Sjkim#define BGE_TXLEN_SLOTTIME 0x000000FF 780166676Sjkim#define BGE_TXLEN_IPG 0x00000F00 781166676Sjkim#define BGE_TXLEN_CRS 0x00003000 78284059Swpaul 78384059Swpaul/* Receive MAC mode register */ 784166676Sjkim#define BGE_RXMODE_RESET 0x00000001 785166676Sjkim#define BGE_RXMODE_ENABLE 0x00000002 786166676Sjkim#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 787166676Sjkim#define BGE_RXMODE_RX_GIANTS 0x00000020 788166676Sjkim#define BGE_RXMODE_RX_RUNTS 0x00000040 789166676Sjkim#define BGE_RXMODE_8022_LENCHECK 0x00000080 790166676Sjkim#define BGE_RXMODE_RX_PROMISC 0x00000100 791166676Sjkim#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 792166676Sjkim#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 79384059Swpaul 79484059Swpaul/* Receive MAC status register */ 795166676Sjkim#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 796166676Sjkim#define BGE_RXSTAT_RCVD_XOFF 0x00000002 797166676Sjkim#define BGE_RXSTAT_RCVD_XON 0x00000004 79884059Swpaul 79984059Swpaul/* Receive Rules Control register */ 800166676Sjkim#define BGE_RXRULECTL_OFFSET 0x000000FF 801166676Sjkim#define BGE_RXRULECTL_CLASS 0x00001F00 802166676Sjkim#define BGE_RXRULECTL_HDRTYPE 0x0000E000 803166676Sjkim#define BGE_RXRULECTL_COMPARE_OP 0x00030000 804166676Sjkim#define BGE_RXRULECTL_MAP 0x01000000 805166676Sjkim#define BGE_RXRULECTL_DISCARD 0x02000000 806166676Sjkim#define BGE_RXRULECTL_MASK 0x04000000 807166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 808166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 809166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 810166676Sjkim#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 81184059Swpaul 81284059Swpaul/* Receive Rules Mask register */ 813166676Sjkim#define BGE_RXRULEMASK_VALUE 0x0000FFFF 814166676Sjkim#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 81584059Swpaul 816130273Swpaul/* SERDES configuration register */ 817166676Sjkim#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 818166676Sjkim#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 819166676Sjkim#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 820166676Sjkim#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 821166676Sjkim#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 822166676Sjkim#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 823166676Sjkim#define BGE_SERDESCFG_TXMODE 0x00001000 824166676Sjkim#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 825166676Sjkim#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 826166676Sjkim#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 827166676Sjkim#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 828166676Sjkim#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 829166676Sjkim#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 830166676Sjkim#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 831166676Sjkim#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 832166676Sjkim#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 833130273Swpaul 834130273Swpaul/* SERDES status register */ 835166676Sjkim#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 836166676Sjkim#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 837130273Swpaul 838130273Swpaul/* SGDIG config (not documented) */ 839166676Sjkim#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 840166676Sjkim#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 841166676Sjkim#define BGE_SGDIGCFG_SEND 0x40000000 842166676Sjkim#define BGE_SGDIGCFG_AUTO 0x80000000 843130273Swpaul 844130273Swpaul/* SGDIG status (not documented) */ 845166676Sjkim#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 846166676Sjkim#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 847166676Sjkim#define BGE_SGDIGSTS_DONE 0x00000002 848130273Swpaul 849130273Swpaul 85084059Swpaul/* MI communication register */ 851166676Sjkim#define BGE_MICOMM_DATA 0x0000FFFF 852166676Sjkim#define BGE_MICOMM_REG 0x001F0000 853166676Sjkim#define BGE_MICOMM_PHY 0x03E00000 854166676Sjkim#define BGE_MICOMM_CMD 0x0C000000 855166676Sjkim#define BGE_MICOMM_READFAIL 0x10000000 856166676Sjkim#define BGE_MICOMM_BUSY 0x20000000 85784059Swpaul 858166676Sjkim#define BGE_MIREG(x) ((x & 0x1F) << 16) 859166676Sjkim#define BGE_MIPHY(x) ((x & 0x1F) << 21) 860166676Sjkim#define BGE_MICMD_WRITE 0x04000000 861166676Sjkim#define BGE_MICMD_READ 0x08000000 86284059Swpaul 86384059Swpaul/* MI status register */ 864166676Sjkim#define BGE_MISTS_LINK 0x00000001 865166676Sjkim#define BGE_MISTS_10MBPS 0x00000002 86684059Swpaul 867213485Syongari#define BGE_MIMODE_CLK_10MHZ 0x00000001 868166676Sjkim#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 869166676Sjkim#define BGE_MIMODE_AUTOPOLL 0x00000010 870166676Sjkim#define BGE_MIMODE_CLKCNT 0x001F0000 871213485Syongari#define BGE_MIMODE_500KHZ_CONST 0x00008000 872213485Syongari#define BGE_MIMODE_BASE 0x000C0000 87384059Swpaul 87484059Swpaul 87584059Swpaul/* 87684059Swpaul * Send data initiator control registers. 87784059Swpaul */ 878166676Sjkim#define BGE_SDI_MODE 0x0C00 879166676Sjkim#define BGE_SDI_STATUS 0x0C04 880166676Sjkim#define BGE_SDI_STATS_CTL 0x0C08 881166676Sjkim#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 882166676Sjkim#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 883166676Sjkim#define BGE_LOCSTATS_COS0 0x0C80 884166676Sjkim#define BGE_LOCSTATS_COS1 0x0C84 885166676Sjkim#define BGE_LOCSTATS_COS2 0x0C88 886166676Sjkim#define BGE_LOCSTATS_COS3 0x0C8C 887166676Sjkim#define BGE_LOCSTATS_COS4 0x0C90 888166676Sjkim#define BGE_LOCSTATS_COS5 0x0C84 889166676Sjkim#define BGE_LOCSTATS_COS6 0x0C98 890166676Sjkim#define BGE_LOCSTATS_COS7 0x0C9C 891166676Sjkim#define BGE_LOCSTATS_COS8 0x0CA0 892166676Sjkim#define BGE_LOCSTATS_COS9 0x0CA4 893166676Sjkim#define BGE_LOCSTATS_COS10 0x0CA8 894166676Sjkim#define BGE_LOCSTATS_COS11 0x0CAC 895166676Sjkim#define BGE_LOCSTATS_COS12 0x0CB0 896166676Sjkim#define BGE_LOCSTATS_COS13 0x0CB4 897166676Sjkim#define BGE_LOCSTATS_COS14 0x0CB8 898166676Sjkim#define BGE_LOCSTATS_COS15 0x0CBC 899166676Sjkim#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 900166676Sjkim#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 901166676Sjkim#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 902166676Sjkim#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 903166676Sjkim#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 904166676Sjkim#define BGE_LOCSTATS_IRQS 0x0CD4 905166676Sjkim#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 906166676Sjkim#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 90784059Swpaul 90884059Swpaul/* Send Data Initiator mode register */ 909166676Sjkim#define BGE_SDIMODE_RESET 0x00000001 910166676Sjkim#define BGE_SDIMODE_ENABLE 0x00000002 911166676Sjkim#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 91284059Swpaul 91384059Swpaul/* Send Data Initiator stats register */ 914166676Sjkim#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 91584059Swpaul 91684059Swpaul/* Send Data Initiator stats control register */ 917166676Sjkim#define BGE_SDISTATSCTL_ENABLE 0x00000001 918166676Sjkim#define BGE_SDISTATSCTL_FASTER 0x00000002 919166676Sjkim#define BGE_SDISTATSCTL_CLEAR 0x00000004 920166676Sjkim#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 921166676Sjkim#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 92284059Swpaul 92384059Swpaul/* 92484059Swpaul * Send Data Completion Control registers 92584059Swpaul */ 926166676Sjkim#define BGE_SDC_MODE 0x1000 927166676Sjkim#define BGE_SDC_STATUS 0x1004 92884059Swpaul 92984059Swpaul/* Send Data completion mode register */ 930166676Sjkim#define BGE_SDCMODE_RESET 0x00000001 931166676Sjkim#define BGE_SDCMODE_ENABLE 0x00000002 932166676Sjkim#define BGE_SDCMODE_ATTN 0x00000004 933197832Sstas#define BGE_SDCMODE_CDELAY 0x00000010 93484059Swpaul 93584059Swpaul/* Send Data completion status register */ 936166676Sjkim#define BGE_SDCSTAT_ATTN 0x00000004 93784059Swpaul 93884059Swpaul/* 93984059Swpaul * Send BD Ring Selector Control registers 94084059Swpaul */ 941166676Sjkim#define BGE_SRS_MODE 0x1400 942166676Sjkim#define BGE_SRS_STATUS 0x1404 943166676Sjkim#define BGE_SRS_HWDIAG 0x1408 944166676Sjkim#define BGE_SRS_LOC_NIC_CONS0 0x1440 945166676Sjkim#define BGE_SRS_LOC_NIC_CONS1 0x1444 946166676Sjkim#define BGE_SRS_LOC_NIC_CONS2 0x1448 947166676Sjkim#define BGE_SRS_LOC_NIC_CONS3 0x144C 948166676Sjkim#define BGE_SRS_LOC_NIC_CONS4 0x1450 949166676Sjkim#define BGE_SRS_LOC_NIC_CONS5 0x1454 950166676Sjkim#define BGE_SRS_LOC_NIC_CONS6 0x1458 951166676Sjkim#define BGE_SRS_LOC_NIC_CONS7 0x145C 952166676Sjkim#define BGE_SRS_LOC_NIC_CONS8 0x1460 953166676Sjkim#define BGE_SRS_LOC_NIC_CONS9 0x1464 954166676Sjkim#define BGE_SRS_LOC_NIC_CONS10 0x1468 955166676Sjkim#define BGE_SRS_LOC_NIC_CONS11 0x146C 956166676Sjkim#define BGE_SRS_LOC_NIC_CONS12 0x1470 957166676Sjkim#define BGE_SRS_LOC_NIC_CONS13 0x1474 958166676Sjkim#define BGE_SRS_LOC_NIC_CONS14 0x1478 959166676Sjkim#define BGE_SRS_LOC_NIC_CONS15 0x147C 96084059Swpaul 96184059Swpaul/* Send BD Ring Selector Mode register */ 962166676Sjkim#define BGE_SRSMODE_RESET 0x00000001 963166676Sjkim#define BGE_SRSMODE_ENABLE 0x00000002 964166676Sjkim#define BGE_SRSMODE_ATTN 0x00000004 96584059Swpaul 96684059Swpaul/* Send BD Ring Selector Status register */ 967166676Sjkim#define BGE_SRSSTAT_ERROR 0x00000004 96884059Swpaul 96984059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 970166676Sjkim#define BGE_SRSHWDIAG_STATE 0x0000000F 971166676Sjkim#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 972166676Sjkim#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 973166676Sjkim#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 97484059Swpaul 97584059Swpaul/* 97684059Swpaul * Send BD Initiator Selector Control registers 97784059Swpaul */ 978166676Sjkim#define BGE_SBDI_MODE 0x1800 979166676Sjkim#define BGE_SBDI_STATUS 0x1804 980166676Sjkim#define BGE_SBDI_LOC_NIC_PROD0 0x1808 981166676Sjkim#define BGE_SBDI_LOC_NIC_PROD1 0x180C 982166676Sjkim#define BGE_SBDI_LOC_NIC_PROD2 0x1810 983166676Sjkim#define BGE_SBDI_LOC_NIC_PROD3 0x1814 984166676Sjkim#define BGE_SBDI_LOC_NIC_PROD4 0x1818 985166676Sjkim#define BGE_SBDI_LOC_NIC_PROD5 0x181C 986166676Sjkim#define BGE_SBDI_LOC_NIC_PROD6 0x1820 987166676Sjkim#define BGE_SBDI_LOC_NIC_PROD7 0x1824 988166676Sjkim#define BGE_SBDI_LOC_NIC_PROD8 0x1828 989166676Sjkim#define BGE_SBDI_LOC_NIC_PROD9 0x182C 990166676Sjkim#define BGE_SBDI_LOC_NIC_PROD10 0x1830 991166676Sjkim#define BGE_SBDI_LOC_NIC_PROD11 0x1834 992166676Sjkim#define BGE_SBDI_LOC_NIC_PROD12 0x1838 993166676Sjkim#define BGE_SBDI_LOC_NIC_PROD13 0x183C 994166676Sjkim#define BGE_SBDI_LOC_NIC_PROD14 0x1840 995166676Sjkim#define BGE_SBDI_LOC_NIC_PROD15 0x1844 99684059Swpaul 99784059Swpaul/* Send BD Initiator Mode register */ 998166676Sjkim#define BGE_SBDIMODE_RESET 0x00000001 999166676Sjkim#define BGE_SBDIMODE_ENABLE 0x00000002 1000166676Sjkim#define BGE_SBDIMODE_ATTN 0x00000004 100184059Swpaul 100284059Swpaul/* Send BD Initiator Status register */ 1003166676Sjkim#define BGE_SBDISTAT_ERROR 0x00000004 100484059Swpaul 100584059Swpaul/* 100684059Swpaul * Send BD Completion Control registers 100784059Swpaul */ 1008166676Sjkim#define BGE_SBDC_MODE 0x1C00 1009166676Sjkim#define BGE_SBDC_STATUS 0x1C04 101084059Swpaul 101184059Swpaul/* Send BD Completion Control Mode register */ 1012166676Sjkim#define BGE_SBDCMODE_RESET 0x00000001 1013166676Sjkim#define BGE_SBDCMODE_ENABLE 0x00000002 1014166676Sjkim#define BGE_SBDCMODE_ATTN 0x00000004 101584059Swpaul 101684059Swpaul/* Send BD Completion Control Status register */ 1017166676Sjkim#define BGE_SBDCSTAT_ATTN 0x00000004 101884059Swpaul 101984059Swpaul/* 102084059Swpaul * Receive List Placement Control registers 102184059Swpaul */ 1022166676Sjkim#define BGE_RXLP_MODE 0x2000 1023166676Sjkim#define BGE_RXLP_STATUS 0x2004 1024166676Sjkim#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1025166676Sjkim#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1026166676Sjkim#define BGE_RXLP_CFG 0x2010 1027166676Sjkim#define BGE_RXLP_STATS_CTL 0x2014 1028166676Sjkim#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1029166676Sjkim#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1030166676Sjkim#define BGE_RXLP_HEAD0 0x2100 1031166676Sjkim#define BGE_RXLP_TAIL0 0x2104 1032166676Sjkim#define BGE_RXLP_COUNT0 0x2108 1033166676Sjkim#define BGE_RXLP_HEAD1 0x2110 1034166676Sjkim#define BGE_RXLP_TAIL1 0x2114 1035166676Sjkim#define BGE_RXLP_COUNT1 0x2118 1036166676Sjkim#define BGE_RXLP_HEAD2 0x2120 1037166676Sjkim#define BGE_RXLP_TAIL2 0x2124 1038166676Sjkim#define BGE_RXLP_COUNT2 0x2128 1039166676Sjkim#define BGE_RXLP_HEAD3 0x2130 1040166676Sjkim#define BGE_RXLP_TAIL3 0x2134 1041166676Sjkim#define BGE_RXLP_COUNT3 0x2138 1042166676Sjkim#define BGE_RXLP_HEAD4 0x2140 1043166676Sjkim#define BGE_RXLP_TAIL4 0x2144 1044166676Sjkim#define BGE_RXLP_COUNT4 0x2148 1045166676Sjkim#define BGE_RXLP_HEAD5 0x2150 1046166676Sjkim#define BGE_RXLP_TAIL5 0x2154 1047166676Sjkim#define BGE_RXLP_COUNT5 0x2158 1048166676Sjkim#define BGE_RXLP_HEAD6 0x2160 1049166676Sjkim#define BGE_RXLP_TAIL6 0x2164 1050166676Sjkim#define BGE_RXLP_COUNT6 0x2168 1051166676Sjkim#define BGE_RXLP_HEAD7 0x2170 1052166676Sjkim#define BGE_RXLP_TAIL7 0x2174 1053166676Sjkim#define BGE_RXLP_COUNT7 0x2178 1054166676Sjkim#define BGE_RXLP_HEAD8 0x2180 1055166676Sjkim#define BGE_RXLP_TAIL8 0x2184 1056166676Sjkim#define BGE_RXLP_COUNT8 0x2188 1057166676Sjkim#define BGE_RXLP_HEAD9 0x2190 1058166676Sjkim#define BGE_RXLP_TAIL9 0x2194 1059166676Sjkim#define BGE_RXLP_COUNT9 0x2198 1060166676Sjkim#define BGE_RXLP_HEAD10 0x21A0 1061166676Sjkim#define BGE_RXLP_TAIL10 0x21A4 1062166676Sjkim#define BGE_RXLP_COUNT10 0x21A8 1063166676Sjkim#define BGE_RXLP_HEAD11 0x21B0 1064166676Sjkim#define BGE_RXLP_TAIL11 0x21B4 1065166676Sjkim#define BGE_RXLP_COUNT11 0x21B8 1066166676Sjkim#define BGE_RXLP_HEAD12 0x21C0 1067166676Sjkim#define BGE_RXLP_TAIL12 0x21C4 1068166676Sjkim#define BGE_RXLP_COUNT12 0x21C8 1069166676Sjkim#define BGE_RXLP_HEAD13 0x21D0 1070166676Sjkim#define BGE_RXLP_TAIL13 0x21D4 1071166676Sjkim#define BGE_RXLP_COUNT13 0x21D8 1072166676Sjkim#define BGE_RXLP_HEAD14 0x21E0 1073166676Sjkim#define BGE_RXLP_TAIL14 0x21E4 1074166676Sjkim#define BGE_RXLP_COUNT14 0x21E8 1075166676Sjkim#define BGE_RXLP_HEAD15 0x21F0 1076166676Sjkim#define BGE_RXLP_TAIL15 0x21F4 1077166676Sjkim#define BGE_RXLP_COUNT15 0x21F8 1078166676Sjkim#define BGE_RXLP_LOCSTAT_COS0 0x2200 1079166676Sjkim#define BGE_RXLP_LOCSTAT_COS1 0x2204 1080166676Sjkim#define BGE_RXLP_LOCSTAT_COS2 0x2208 1081166676Sjkim#define BGE_RXLP_LOCSTAT_COS3 0x220C 1082166676Sjkim#define BGE_RXLP_LOCSTAT_COS4 0x2210 1083166676Sjkim#define BGE_RXLP_LOCSTAT_COS5 0x2214 1084166676Sjkim#define BGE_RXLP_LOCSTAT_COS6 0x2218 1085166676Sjkim#define BGE_RXLP_LOCSTAT_COS7 0x221C 1086166676Sjkim#define BGE_RXLP_LOCSTAT_COS8 0x2220 1087166676Sjkim#define BGE_RXLP_LOCSTAT_COS9 0x2224 1088166676Sjkim#define BGE_RXLP_LOCSTAT_COS10 0x2228 1089166676Sjkim#define BGE_RXLP_LOCSTAT_COS11 0x222C 1090166676Sjkim#define BGE_RXLP_LOCSTAT_COS12 0x2230 1091166676Sjkim#define BGE_RXLP_LOCSTAT_COS13 0x2234 1092166676Sjkim#define BGE_RXLP_LOCSTAT_COS14 0x2238 1093166676Sjkim#define BGE_RXLP_LOCSTAT_COS15 0x223C 1094166676Sjkim#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1095166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1096166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1097166676Sjkim#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1098166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1099166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1100166676Sjkim#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 110184059Swpaul 110284059Swpaul 110384059Swpaul/* Receive List Placement mode register */ 1104166676Sjkim#define BGE_RXLPMODE_RESET 0x00000001 1105166676Sjkim#define BGE_RXLPMODE_ENABLE 0x00000002 1106166676Sjkim#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1107166676Sjkim#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1108166676Sjkim#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 110984059Swpaul 111084059Swpaul/* Receive List Placement Status register */ 1111166676Sjkim#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1112166676Sjkim#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1113166676Sjkim#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 111484059Swpaul 111584059Swpaul/* 111684059Swpaul * Receive Data and Receive BD Initiator Control Registers 111784059Swpaul */ 1118166676Sjkim#define BGE_RDBDI_MODE 0x2400 1119166676Sjkim#define BGE_RDBDI_STATUS 0x2404 1120166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1121166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1122166676Sjkim#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1123166676Sjkim#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1124166676Sjkim#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1125166676Sjkim#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1126166676Sjkim#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1127166676Sjkim#define BGE_RX_STD_RCB_NICADDR 0x245C 1128166676Sjkim#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1129166676Sjkim#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1130166676Sjkim#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1131166676Sjkim#define BGE_RX_MINI_RCB_NICADDR 0x246C 1132166676Sjkim#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1133166676Sjkim#define BGE_RDBDI_STD_RX_CONS 0x2474 1134166676Sjkim#define BGE_RDBDI_MINI_RX_CONS 0x2478 1135166676Sjkim#define BGE_RDBDI_RETURN_PROD0 0x2480 1136166676Sjkim#define BGE_RDBDI_RETURN_PROD1 0x2484 1137166676Sjkim#define BGE_RDBDI_RETURN_PROD2 0x2488 1138166676Sjkim#define BGE_RDBDI_RETURN_PROD3 0x248C 1139166676Sjkim#define BGE_RDBDI_RETURN_PROD4 0x2490 1140166676Sjkim#define BGE_RDBDI_RETURN_PROD5 0x2494 1141166676Sjkim#define BGE_RDBDI_RETURN_PROD6 0x2498 1142166676Sjkim#define BGE_RDBDI_RETURN_PROD7 0x249C 1143166676Sjkim#define BGE_RDBDI_RETURN_PROD8 0x24A0 1144166676Sjkim#define BGE_RDBDI_RETURN_PROD9 0x24A4 1145166676Sjkim#define BGE_RDBDI_RETURN_PROD10 0x24A8 1146166676Sjkim#define BGE_RDBDI_RETURN_PROD11 0x24AC 1147166676Sjkim#define BGE_RDBDI_RETURN_PROD12 0x24B0 1148166676Sjkim#define BGE_RDBDI_RETURN_PROD13 0x24B4 1149166676Sjkim#define BGE_RDBDI_RETURN_PROD14 0x24B8 1150166676Sjkim#define BGE_RDBDI_RETURN_PROD15 0x24BC 1151166676Sjkim#define BGE_RDBDI_HWDIAG 0x24C0 115284059Swpaul 115384059Swpaul 115484059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 1155166676Sjkim#define BGE_RDBDIMODE_RESET 0x00000001 1156166676Sjkim#define BGE_RDBDIMODE_ENABLE 0x00000002 1157166676Sjkim#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1158166676Sjkim#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1159166676Sjkim#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 116084059Swpaul 116184059Swpaul/* Receive Data and Receive BD Initiator Status register */ 1162166676Sjkim#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1163166676Sjkim#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1164166676Sjkim#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 116584059Swpaul 116684059Swpaul 116784059Swpaul/* 116884059Swpaul * Receive Data Completion Control registers 116984059Swpaul */ 1170166676Sjkim#define BGE_RDC_MODE 0x2800 117184059Swpaul 117284059Swpaul/* Receive Data Completion Mode register */ 1173166676Sjkim#define BGE_RDCMODE_RESET 0x00000001 1174166676Sjkim#define BGE_RDCMODE_ENABLE 0x00000002 1175166676Sjkim#define BGE_RDCMODE_ATTN 0x00000004 117684059Swpaul 117784059Swpaul/* 117884059Swpaul * Receive BD Initiator Control registers 117984059Swpaul */ 1180166676Sjkim#define BGE_RBDI_MODE 0x2C00 1181166676Sjkim#define BGE_RBDI_STATUS 0x2C04 1182166676Sjkim#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1183166676Sjkim#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1184166676Sjkim#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1185166676Sjkim#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1186166676Sjkim#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1187166676Sjkim#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 118884059Swpaul 118984059Swpaul/* Receive BD Initiator Mode register */ 1190166676Sjkim#define BGE_RBDIMODE_RESET 0x00000001 1191166676Sjkim#define BGE_RBDIMODE_ENABLE 0x00000002 1192166676Sjkim#define BGE_RBDIMODE_ATTN 0x00000004 119384059Swpaul 119484059Swpaul/* Receive BD Initiator Status register */ 1195166676Sjkim#define BGE_RBDISTAT_ATTN 0x00000004 119684059Swpaul 119784059Swpaul/* 119884059Swpaul * Receive BD Completion Control registers 119984059Swpaul */ 1200166676Sjkim#define BGE_RBDC_MODE 0x3000 1201166676Sjkim#define BGE_RBDC_STATUS 0x3004 1202166676Sjkim#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1203166676Sjkim#define BGE_RBDC_STD_BD_PROD 0x300C 1204166676Sjkim#define BGE_RBDC_MINI_BD_PROD 0x3010 120584059Swpaul 120684059Swpaul/* Receive BD completion mode register */ 1207166676Sjkim#define BGE_RBDCMODE_RESET 0x00000001 1208166676Sjkim#define BGE_RBDCMODE_ENABLE 0x00000002 1209166676Sjkim#define BGE_RBDCMODE_ATTN 0x00000004 121084059Swpaul 121184059Swpaul/* Receive BD completion status register */ 1212166676Sjkim#define BGE_RBDCSTAT_ERROR 0x00000004 121384059Swpaul 121484059Swpaul/* 121584059Swpaul * Receive List Selector Control registers 121684059Swpaul */ 1217166676Sjkim#define BGE_RXLS_MODE 0x3400 1218166676Sjkim#define BGE_RXLS_STATUS 0x3404 121984059Swpaul 122084059Swpaul/* Receive List Selector Mode register */ 1221166676Sjkim#define BGE_RXLSMODE_RESET 0x00000001 1222166676Sjkim#define BGE_RXLSMODE_ENABLE 0x00000002 1223166676Sjkim#define BGE_RXLSMODE_ATTN 0x00000004 122484059Swpaul 122584059Swpaul/* Receive List Selector Status register */ 1226166676Sjkim#define BGE_RXLSSTAT_ERROR 0x00000004 122784059Swpaul 1228213485Syongari#define BGE_CPMU_CTRL 0x3600 1229213485Syongari#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1230213485Syongari#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1231213485Syongari#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1232213485Syongari#define BGE_CPMU_HST_ACC 0x361C 1233213485Syongari#define BGE_CPMU_CLCK_STAT 0x3630 1234213485Syongari#define BGE_CPMU_MUTEX_REQ 0x365C 1235213485Syongari#define BGE_CPMU_MUTEX_GNT 0x3660 1236213485Syongari#define BGE_CPMU_PHY_STRAP 0x3664 1237213485Syongari 1238213485Syongari/* Central Power Management Unit (CPMU) register */ 1239213485Syongari#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1240213485Syongari#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1241213485Syongari#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1242213485Syongari#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1243213485Syongari 1244213485Syongari/* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1245213485Syongari#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1246213485Syongari#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1247213485Syongari 1248213485Syongari/* Link Speed 1000MB Power Mode Clock Policy register */ 1249213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1250213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1251213485Syongari#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1252213485Syongari 1253213485Syongari/* Link Aware Power Mode Clock Policy register */ 1254213485Syongari#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1255213485Syongari#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1256213485Syongari 1257213485Syongari#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1258213485Syongari#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1259213485Syongari 1260213485Syongari/* CPMU Clock Status register */ 1261213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1262213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1263213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1264213485Syongari#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1265213485Syongari 1266213485Syongari/* CPMU Mutex Request register */ 1267213485Syongari#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1268213485Syongari#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1269213485Syongari 1270213485Syongari/* CPMU GPHY Strap register */ 1271213485Syongari#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1272213485Syongari 127384059Swpaul/* 127484059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 127584059Swpaul */ 1276166676Sjkim#define BGE_MBCF_MODE 0x3800 1277166676Sjkim#define BGE_MBCF_STATUS 0x3804 127884059Swpaul 127984059Swpaul/* Mbuf Cluster Free mode register */ 1280166676Sjkim#define BGE_MBCFMODE_RESET 0x00000001 1281166676Sjkim#define BGE_MBCFMODE_ENABLE 0x00000002 1282166676Sjkim#define BGE_MBCFMODE_ATTN 0x00000004 128384059Swpaul 128484059Swpaul/* Mbuf Cluster Free status register */ 1285166676Sjkim#define BGE_MBCFSTAT_ERROR 0x00000004 128684059Swpaul 128784059Swpaul/* 128884059Swpaul * Host Coalescing Control registers 128984059Swpaul */ 1290166676Sjkim#define BGE_HCC_MODE 0x3C00 1291166676Sjkim#define BGE_HCC_STATUS 0x3C04 1292166676Sjkim#define BGE_HCC_RX_COAL_TICKS 0x3C08 1293166676Sjkim#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1294166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1295166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1296166676Sjkim#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1297166676Sjkim#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1298166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1299166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1300166676Sjkim#define BGE_HCC_STATS_TICKS 0x3C28 1301166676Sjkim#define BGE_HCC_STATS_ADDR_HI 0x3C30 1302166676Sjkim#define BGE_HCC_STATS_ADDR_LO 0x3C34 1303166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1304166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1305166676Sjkim#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1306166676Sjkim#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1307166676Sjkim#define BGE_FLOW_ATTN 0x3C48 1308166676Sjkim#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1309166676Sjkim#define BGE_HCC_STD_BD_CONS 0x3C54 1310166676Sjkim#define BGE_HCC_MINI_BD_CONS 0x3C58 1311166676Sjkim#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1312166676Sjkim#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1313166676Sjkim#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1314166676Sjkim#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1315166676Sjkim#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1316166676Sjkim#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1317166676Sjkim#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1318166676Sjkim#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1319166676Sjkim#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1320166676Sjkim#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1321166676Sjkim#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1322166676Sjkim#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1323166676Sjkim#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1324166676Sjkim#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1325166676Sjkim#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1326166676Sjkim#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1327166676Sjkim#define BGE_HCC_TX_BD_CONS0 0x3CC0 1328166676Sjkim#define BGE_HCC_TX_BD_CONS1 0x3CC4 1329166676Sjkim#define BGE_HCC_TX_BD_CONS2 0x3CC8 1330166676Sjkim#define BGE_HCC_TX_BD_CONS3 0x3CCC 1331166676Sjkim#define BGE_HCC_TX_BD_CONS4 0x3CD0 1332166676Sjkim#define BGE_HCC_TX_BD_CONS5 0x3CD4 1333166676Sjkim#define BGE_HCC_TX_BD_CONS6 0x3CD8 1334166676Sjkim#define BGE_HCC_TX_BD_CONS7 0x3CDC 1335166676Sjkim#define BGE_HCC_TX_BD_CONS8 0x3CE0 1336166676Sjkim#define BGE_HCC_TX_BD_CONS9 0x3CE4 1337166676Sjkim#define BGE_HCC_TX_BD_CONS10 0x3CE8 1338166676Sjkim#define BGE_HCC_TX_BD_CONS11 0x3CEC 1339166676Sjkim#define BGE_HCC_TX_BD_CONS12 0x3CF0 1340166676Sjkim#define BGE_HCC_TX_BD_CONS13 0x3CF4 1341166676Sjkim#define BGE_HCC_TX_BD_CONS14 0x3CF8 1342166676Sjkim#define BGE_HCC_TX_BD_CONS15 0x3CFC 134384059Swpaul 134484059Swpaul 134584059Swpaul/* Host coalescing mode register */ 1346166676Sjkim#define BGE_HCCMODE_RESET 0x00000001 1347166676Sjkim#define BGE_HCCMODE_ENABLE 0x00000002 1348166676Sjkim#define BGE_HCCMODE_ATTN 0x00000004 1349166676Sjkim#define BGE_HCCMODE_COAL_NOW 0x00000008 1350166676Sjkim#define BGE_HCCMODE_MSI_BITS 0x00000070 1351166676Sjkim#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 135284059Swpaul 1353166676Sjkim#define BGE_STATBLKSZ_FULL 0x00000000 1354166676Sjkim#define BGE_STATBLKSZ_64BYTE 0x00000080 1355166676Sjkim#define BGE_STATBLKSZ_32BYTE 0x00000100 135684059Swpaul 135784059Swpaul/* Host coalescing status register */ 1358166676Sjkim#define BGE_HCCSTAT_ERROR 0x00000004 135984059Swpaul 136084059Swpaul/* Flow attention register */ 1361166676Sjkim#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1362166676Sjkim#define BGE_FLOWATTN_MEMARB 0x00000080 1363166676Sjkim#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1364166676Sjkim#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1365166676Sjkim#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1366166676Sjkim#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1367166676Sjkim#define BGE_FLOWATTN_RDBDI 0x00080000 1368166676Sjkim#define BGE_FLOWATTN_RXLS 0x00100000 1369166676Sjkim#define BGE_FLOWATTN_RXLP 0x00200000 1370166676Sjkim#define BGE_FLOWATTN_RBDC 0x00400000 1371166676Sjkim#define BGE_FLOWATTN_RBDI 0x00800000 1372166676Sjkim#define BGE_FLOWATTN_SDC 0x08000000 1373166676Sjkim#define BGE_FLOWATTN_SDI 0x10000000 1374166676Sjkim#define BGE_FLOWATTN_SRS 0x20000000 1375166676Sjkim#define BGE_FLOWATTN_SBDC 0x40000000 1376166676Sjkim#define BGE_FLOWATTN_SBDI 0x80000000 137784059Swpaul 137884059Swpaul/* 137984059Swpaul * Memory arbiter registers 138084059Swpaul */ 1381166676Sjkim#define BGE_MARB_MODE 0x4000 1382166676Sjkim#define BGE_MARB_STATUS 0x4004 1383166676Sjkim#define BGE_MARB_TRAPADDR_HI 0x4008 1384166676Sjkim#define BGE_MARB_TRAPADDR_LO 0x400C 138584059Swpaul 138684059Swpaul/* Memory arbiter mode register */ 1387166676Sjkim#define BGE_MARBMODE_RESET 0x00000001 1388166676Sjkim#define BGE_MARBMODE_ENABLE 0x00000002 1389166676Sjkim#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1390166676Sjkim#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1391166676Sjkim#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1392166676Sjkim#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1393166676Sjkim#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1394166676Sjkim#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1395166676Sjkim#define BGE_MARBMODE_PCI_TRAP 0x00000100 1396166676Sjkim#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1397166676Sjkim#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1398166676Sjkim#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1399166676Sjkim#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1400166676Sjkim#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1401166676Sjkim#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1402166676Sjkim#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1403166676Sjkim#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1404166676Sjkim#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1405166676Sjkim#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1406166676Sjkim#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1407166676Sjkim#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1408166676Sjkim#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1409166676Sjkim#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1410166676Sjkim#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1411166676Sjkim#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1412166676Sjkim#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 141384059Swpaul 141484059Swpaul/* Memory arbiter status register */ 1415166676Sjkim#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1416166676Sjkim#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1417166676Sjkim#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1418166676Sjkim#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1419166676Sjkim#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1420166676Sjkim#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1421166676Sjkim#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1422166676Sjkim#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1423166676Sjkim#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1424166676Sjkim#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1425166676Sjkim#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1426166676Sjkim#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1427166676Sjkim#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1428166676Sjkim#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1429166676Sjkim#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1430166676Sjkim#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1431166676Sjkim#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1432166676Sjkim#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1433166676Sjkim#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1434166676Sjkim#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1435166676Sjkim#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1436166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1437166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1438166676Sjkim#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 143984059Swpaul 144084059Swpaul/* 144184059Swpaul * Buffer manager control registers 144284059Swpaul */ 1443166676Sjkim#define BGE_BMAN_MODE 0x4400 1444166676Sjkim#define BGE_BMAN_STATUS 0x4404 1445166676Sjkim#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1446166676Sjkim#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1447166676Sjkim#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1448166676Sjkim#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1449166676Sjkim#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1450166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1451166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1452166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1453166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1454166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1455166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1456166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1457166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1458166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1459166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1460166676Sjkim#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1461166676Sjkim#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1462166676Sjkim#define BGE_BMAN_HWDIAG_1 0x444C 1463166676Sjkim#define BGE_BMAN_HWDIAG_2 0x4450 1464166676Sjkim#define BGE_BMAN_HWDIAG_3 0x4454 146584059Swpaul 146684059Swpaul/* Buffer manager mode register */ 1467166676Sjkim#define BGE_BMANMODE_RESET 0x00000001 1468166676Sjkim#define BGE_BMANMODE_ENABLE 0x00000002 1469166676Sjkim#define BGE_BMANMODE_ATTN 0x00000004 1470166676Sjkim#define BGE_BMANMODE_TESTMODE 0x00000008 1471166676Sjkim#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 147284059Swpaul 147384059Swpaul/* Buffer manager status register */ 1474166676Sjkim#define BGE_BMANSTAT_ERRO 0x00000004 1475166676Sjkim#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 147684059Swpaul 147784059Swpaul 147884059Swpaul/* 147984059Swpaul * Read DMA Control registers 148084059Swpaul */ 1481166676Sjkim#define BGE_RDMA_MODE 0x4800 1482166676Sjkim#define BGE_RDMA_STATUS 0x4804 1483213411Syongari#define BGE_RDMA_RSRVCTRL 0x4900 148484059Swpaul 148584059Swpaul/* Read DMA mode register */ 1486166676Sjkim#define BGE_RDMAMODE_RESET 0x00000001 1487166676Sjkim#define BGE_RDMAMODE_ENABLE 0x00000002 1488166676Sjkim#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1489166676Sjkim#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1490166676Sjkim#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1491166676Sjkim#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1492166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1493166676Sjkim#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1494166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1495166676Sjkim#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1496166676Sjkim#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1497197832Sstas#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1498197832Sstas#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1499197832Sstas#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1500190194Smarius#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1501190194Smarius#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1502199671Syongari#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1503199671Syongari#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 150484059Swpaul 150584059Swpaul/* Read DMA status register */ 1506166676Sjkim#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1507166676Sjkim#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1508166676Sjkim#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1509166676Sjkim#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1510166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1511166676Sjkim#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1512166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1513166676Sjkim#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 151484059Swpaul 1515213411Syongari/* Read DMA Reserved Control register */ 1516213411Syongari#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1517213411Syongari 151884059Swpaul/* 151984059Swpaul * Write DMA control registers 152084059Swpaul */ 1521166676Sjkim#define BGE_WDMA_MODE 0x4C00 1522166676Sjkim#define BGE_WDMA_STATUS 0x4C04 152384059Swpaul 152484059Swpaul/* Write DMA mode register */ 1525166676Sjkim#define BGE_WDMAMODE_RESET 0x00000001 1526166676Sjkim#define BGE_WDMAMODE_ENABLE 0x00000002 1527166676Sjkim#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1528166676Sjkim#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1529166676Sjkim#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1530166676Sjkim#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1531166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1532166676Sjkim#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1533166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1534166676Sjkim#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1535166676Sjkim#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1536197837Sstas#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1537213333Syongari#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 153884059Swpaul 153984059Swpaul/* Write DMA status register */ 1540166676Sjkim#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1541166676Sjkim#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1542166676Sjkim#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1543166676Sjkim#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1544166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1545166676Sjkim#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1546166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1547166676Sjkim#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 154884059Swpaul 154984059Swpaul 155084059Swpaul/* 155184059Swpaul * RX CPU registers 155284059Swpaul */ 1553166676Sjkim#define BGE_RXCPU_MODE 0x5000 1554166676Sjkim#define BGE_RXCPU_STATUS 0x5004 1555166676Sjkim#define BGE_RXCPU_PC 0x501C 155684059Swpaul 155784059Swpaul/* RX CPU mode register */ 1558166676Sjkim#define BGE_RXCPUMODE_RESET 0x00000001 1559166676Sjkim#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1560166676Sjkim#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1561166676Sjkim#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1562166676Sjkim#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1563166676Sjkim#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1564166676Sjkim#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1565166676Sjkim#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1566166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1567166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1568166676Sjkim#define BGE_RXCPUMODE_HALTCPU 0x00000400 1569166676Sjkim#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1570166676Sjkim#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1571166676Sjkim#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 157284059Swpaul 157384059Swpaul/* RX CPU status register */ 1574166676Sjkim#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1575166676Sjkim#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1576166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1577166676Sjkim#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1578166676Sjkim#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1579166676Sjkim#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1580166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1581166676Sjkim#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1582166676Sjkim#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1583166676Sjkim#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1584166676Sjkim#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1585166676Sjkim#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1586166676Sjkim#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1587166676Sjkim#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1588166676Sjkim#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1589166676Sjkim#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1590166676Sjkim#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 159184059Swpaul 1592178667Sjhb/* 1593178667Sjhb * V? CPU registers 1594178667Sjhb */ 1595178667Sjhb#define BGE_VCPU_STATUS 0x5100 1596178667Sjhb#define BGE_VCPU_EXT_CTRL 0x6890 159784059Swpaul 1598178667Sjhb#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1599178667Sjhb#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1600178667Sjhb 1601178667Sjhb#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1602178667Sjhb#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1603178667Sjhb 160484059Swpaul/* 160584059Swpaul * TX CPU registers 160684059Swpaul */ 1607166676Sjkim#define BGE_TXCPU_MODE 0x5400 1608166676Sjkim#define BGE_TXCPU_STATUS 0x5404 1609166676Sjkim#define BGE_TXCPU_PC 0x541C 161084059Swpaul 161184059Swpaul/* TX CPU mode register */ 1612166676Sjkim#define BGE_TXCPUMODE_RESET 0x00000001 1613166676Sjkim#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1614166676Sjkim#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1615166676Sjkim#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1616166676Sjkim#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1617166676Sjkim#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1618166676Sjkim#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1619166676Sjkim#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1620166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1621166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1622166676Sjkim#define BGE_TXCPUMODE_HALTCPU 0x00000400 1623166676Sjkim#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1624166676Sjkim#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 162584059Swpaul 162684059Swpaul/* TX CPU status register */ 1627166676Sjkim#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1628166676Sjkim#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1629166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1630166676Sjkim#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1631166676Sjkim#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1632166676Sjkim#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1633166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1634166676Sjkim#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1635166676Sjkim#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1636166676Sjkim#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1637166676Sjkim#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1638166676Sjkim#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1639166676Sjkim#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1640166676Sjkim#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1641166676Sjkim#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1642166676Sjkim#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1643166676Sjkim#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 164484059Swpaul 164584059Swpaul 164684059Swpaul/* 164784059Swpaul * Low priority mailbox registers 164884059Swpaul */ 1649166676Sjkim#define BGE_LPMBX_IRQ0_HI 0x5800 1650166676Sjkim#define BGE_LPMBX_IRQ0_LO 0x5804 1651166676Sjkim#define BGE_LPMBX_IRQ1_HI 0x5808 1652166676Sjkim#define BGE_LPMBX_IRQ1_LO 0x580C 1653166676Sjkim#define BGE_LPMBX_IRQ2_HI 0x5810 1654166676Sjkim#define BGE_LPMBX_IRQ2_LO 0x5814 1655166676Sjkim#define BGE_LPMBX_IRQ3_HI 0x5818 1656166676Sjkim#define BGE_LPMBX_IRQ3_LO 0x581C 1657166676Sjkim#define BGE_LPMBX_GEN0_HI 0x5820 1658166676Sjkim#define BGE_LPMBX_GEN0_LO 0x5824 1659166676Sjkim#define BGE_LPMBX_GEN1_HI 0x5828 1660166676Sjkim#define BGE_LPMBX_GEN1_LO 0x582C 1661166676Sjkim#define BGE_LPMBX_GEN2_HI 0x5830 1662166676Sjkim#define BGE_LPMBX_GEN2_LO 0x5834 1663166676Sjkim#define BGE_LPMBX_GEN3_HI 0x5828 1664166676Sjkim#define BGE_LPMBX_GEN3_LO 0x582C 1665166676Sjkim#define BGE_LPMBX_GEN4_HI 0x5840 1666166676Sjkim#define BGE_LPMBX_GEN4_LO 0x5844 1667166676Sjkim#define BGE_LPMBX_GEN5_HI 0x5848 1668166676Sjkim#define BGE_LPMBX_GEN5_LO 0x584C 1669166676Sjkim#define BGE_LPMBX_GEN6_HI 0x5850 1670166676Sjkim#define BGE_LPMBX_GEN6_LO 0x5854 1671166676Sjkim#define BGE_LPMBX_GEN7_HI 0x5858 1672166676Sjkim#define BGE_LPMBX_GEN7_LO 0x585C 1673166676Sjkim#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1674166676Sjkim#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1675166676Sjkim#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1676166676Sjkim#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1677166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1678166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1679166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1680166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1681166676Sjkim#define BGE_LPMBX_RX_CONS0_HI 0x5880 1682166676Sjkim#define BGE_LPMBX_RX_CONS0_LO 0x5884 1683166676Sjkim#define BGE_LPMBX_RX_CONS1_HI 0x5888 1684166676Sjkim#define BGE_LPMBX_RX_CONS1_LO 0x588C 1685166676Sjkim#define BGE_LPMBX_RX_CONS2_HI 0x5890 1686166676Sjkim#define BGE_LPMBX_RX_CONS2_LO 0x5894 1687166676Sjkim#define BGE_LPMBX_RX_CONS3_HI 0x5898 1688166676Sjkim#define BGE_LPMBX_RX_CONS3_LO 0x589C 1689166676Sjkim#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1690166676Sjkim#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1691166676Sjkim#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1692166676Sjkim#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1693166676Sjkim#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1694166676Sjkim#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1695166676Sjkim#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1696166676Sjkim#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1697166676Sjkim#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1698166676Sjkim#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1699166676Sjkim#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1700166676Sjkim#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1701166676Sjkim#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1702166676Sjkim#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1703166676Sjkim#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1704166676Sjkim#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1705166676Sjkim#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1706166676Sjkim#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1707166676Sjkim#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1708166676Sjkim#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1709166676Sjkim#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1710166676Sjkim#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1711166676Sjkim#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1712166676Sjkim#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1713166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1714166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1715166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1716166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1717166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1718166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1719166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1720166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1721166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1722166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1723166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1724166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1725166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1726166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1727166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1728166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1729166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1730166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1731166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1732166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1733166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1734166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1735166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1736166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1737166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1738166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1739166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1740166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1741166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1742166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1743166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1744166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1745166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1746166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1747166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1748166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1749166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1750166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1751166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1752166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1753166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1754166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1755166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1756166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1757166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1758166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1759166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1760166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1761166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1762166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1763166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1764166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1765166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1766166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1767166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1768166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1769166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1770166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1771166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1772166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1773166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1774166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1775166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1776166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 177784059Swpaul 177884059Swpaul/* 177984059Swpaul * Flow throw Queue reset register 178084059Swpaul */ 1781166676Sjkim#define BGE_FTQ_RESET 0x5C00 178284059Swpaul 1783166676Sjkim#define BGE_FTQRESET_DMAREAD 0x00000002 1784166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1785166676Sjkim#define BGE_FTQRESET_DMADONE 0x00000010 1786166676Sjkim#define BGE_FTQRESET_SBDC 0x00000020 1787166676Sjkim#define BGE_FTQRESET_SDI 0x00000040 1788166676Sjkim#define BGE_FTQRESET_WDMA 0x00000080 1789166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1790166676Sjkim#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1791166676Sjkim#define BGE_FTQRESET_SDC 0x00000400 1792166676Sjkim#define BGE_FTQRESET_HCC 0x00000800 1793166676Sjkim#define BGE_FTQRESET_TXFIFO 0x00001000 1794166676Sjkim#define BGE_FTQRESET_MBC 0x00002000 1795166676Sjkim#define BGE_FTQRESET_RBDC 0x00004000 1796166676Sjkim#define BGE_FTQRESET_RXLP 0x00008000 1797166676Sjkim#define BGE_FTQRESET_RDBDI 0x00010000 1798166676Sjkim#define BGE_FTQRESET_RDC 0x00020000 1799166676Sjkim#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 180084059Swpaul 180184059Swpaul/* 180284059Swpaul * Message Signaled Interrupt registers 180384059Swpaul */ 1804166676Sjkim#define BGE_MSI_MODE 0x6000 1805166676Sjkim#define BGE_MSI_STATUS 0x6004 1806166676Sjkim#define BGE_MSI_FIFOACCESS 0x6008 180784059Swpaul 180884059Swpaul/* MSI mode register */ 1809166676Sjkim#define BGE_MSIMODE_RESET 0x00000001 1810166676Sjkim#define BGE_MSIMODE_ENABLE 0x00000002 1811198967Syongari#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1812198967Syongari#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 181384059Swpaul 181484059Swpaul/* MSI status register */ 1815166676Sjkim#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1816166676Sjkim#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1817166676Sjkim#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1818166676Sjkim#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1819166676Sjkim#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 182084059Swpaul 182184059Swpaul 182284059Swpaul/* 182384059Swpaul * DMA Completion registers 182484059Swpaul */ 1825166676Sjkim#define BGE_DMAC_MODE 0x6400 182684059Swpaul 182784059Swpaul/* DMA Completion mode register */ 1828166676Sjkim#define BGE_DMACMODE_RESET 0x00000001 1829166676Sjkim#define BGE_DMACMODE_ENABLE 0x00000002 183084059Swpaul 183184059Swpaul 183284059Swpaul/* 183384059Swpaul * General control registers. 183484059Swpaul */ 1835166676Sjkim#define BGE_MODE_CTL 0x6800 1836166676Sjkim#define BGE_MISC_CFG 0x6804 1837166676Sjkim#define BGE_MISC_LOCAL_CTL 0x6808 1838166676Sjkim#define BGE_CPU_EVENT 0x6810 1839166676Sjkim#define BGE_EE_ADDR 0x6838 1840166676Sjkim#define BGE_EE_DATA 0x683C 1841166676Sjkim#define BGE_EE_CTL 0x6840 1842166676Sjkim#define BGE_MDI_CTL 0x6844 1843166676Sjkim#define BGE_EE_DELAY 0x6848 1844166676Sjkim#define BGE_FASTBOOT_PC 0x6894 184584059Swpaul 1846178667Sjhb/* 1847178667Sjhb * NVRAM Control registers 1848178667Sjhb */ 1849178667Sjhb#define BGE_NVRAM_CMD 0x7000 1850178667Sjhb#define BGE_NVRAM_STAT 0x7004 1851178667Sjhb#define BGE_NVRAM_WRDATA 0x7008 1852178667Sjhb#define BGE_NVRAM_ADDR 0x700c 1853178667Sjhb#define BGE_NVRAM_RDDATA 0x7010 1854178667Sjhb#define BGE_NVRAM_CFG1 0x7014 1855178667Sjhb#define BGE_NVRAM_CFG2 0x7018 1856178667Sjhb#define BGE_NVRAM_CFG3 0x701c 1857178667Sjhb#define BGE_NVRAM_SWARB 0x7020 1858178667Sjhb#define BGE_NVRAM_ACCESS 0x7024 1859178667Sjhb#define BGE_NVRAM_WRITE1 0x7028 1860178667Sjhb 1861178667Sjhb#define BGE_NVRAMCMD_RESET 0x00000001 1862178667Sjhb#define BGE_NVRAMCMD_DONE 0x00000008 1863178667Sjhb#define BGE_NVRAMCMD_START 0x00000010 1864178667Sjhb#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1865178667Sjhb#define BGE_NVRAMCMD_ERASE 0x00000040 1866178667Sjhb#define BGE_NVRAMCMD_FIRST 0x00000080 1867178667Sjhb#define BGE_NVRAMCMD_LAST 0x00000100 1868178667Sjhb 1869178667Sjhb#define BGE_NVRAM_READCMD \ 1870178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1871178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1872178667Sjhb#define BGE_NVRAM_WRITECMD \ 1873178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1874178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1875178667Sjhb 1876178667Sjhb#define BGE_NVRAMSWARB_SET0 0x00000001 1877178667Sjhb#define BGE_NVRAMSWARB_SET1 0x00000002 1878178667Sjhb#define BGE_NVRAMSWARB_SET2 0x00000003 1879178667Sjhb#define BGE_NVRAMSWARB_SET3 0x00000004 1880178667Sjhb#define BGE_NVRAMSWARB_CLR0 0x00000010 1881178667Sjhb#define BGE_NVRAMSWARB_CLR1 0x00000020 1882178667Sjhb#define BGE_NVRAMSWARB_CLR2 0x00000040 1883178667Sjhb#define BGE_NVRAMSWARB_CLR3 0x00000080 1884178667Sjhb#define BGE_NVRAMSWARB_GNT0 0x00000100 1885178667Sjhb#define BGE_NVRAMSWARB_GNT1 0x00000200 1886178667Sjhb#define BGE_NVRAMSWARB_GNT2 0x00000400 1887178667Sjhb#define BGE_NVRAMSWARB_GNT3 0x00000800 1888178667Sjhb#define BGE_NVRAMSWARB_REQ0 0x00001000 1889178667Sjhb#define BGE_NVRAMSWARB_REQ1 0x00002000 1890178667Sjhb#define BGE_NVRAMSWARB_REQ2 0x00004000 1891178667Sjhb#define BGE_NVRAMSWARB_REQ3 0x00008000 1892178667Sjhb 1893178667Sjhb#define BGE_NVRAMACC_ENABLE 0x00000001 1894178667Sjhb#define BGE_NVRAMACC_WRENABLE 0x00000002 1895178667Sjhb 189684059Swpaul/* Mode control register */ 1897166676Sjkim#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1898166676Sjkim#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1899166676Sjkim#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1900166676Sjkim#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1901166676Sjkim#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1902166676Sjkim#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1903166676Sjkim#define BGE_MODECTL_NO_RX_CRC 0x00000400 1904166676Sjkim#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1905166676Sjkim#define BGE_MODECTL_NO_TX_INTR 0x00002000 1906166676Sjkim#define BGE_MODECTL_NO_RX_INTR 0x00004000 1907166676Sjkim#define BGE_MODECTL_FORCE_PCI32 0x00008000 1908166676Sjkim#define BGE_MODECTL_STACKUP 0x00010000 1909166676Sjkim#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1910166676Sjkim#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1911166676Sjkim#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1912166676Sjkim#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1913166676Sjkim#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1914166676Sjkim#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1915166676Sjkim#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1916166676Sjkim#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1917166676Sjkim#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1918166676Sjkim#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 191984059Swpaul 192084059Swpaul/* Misc. config register */ 1921166676Sjkim#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1922166676Sjkim#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1923178785Sbz#define BGE_MISCCFG_BOARD_ID 0x0001E000 1924178785Sbz#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1925178785Sbz#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1926178667Sjhb#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1927210152Syongari#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 192884059Swpaul 1929166676Sjkim#define BGE_32BITTIME_66MHZ (0x41 << 1) 193084059Swpaul 193184059Swpaul/* Misc. Local Control */ 1932166676Sjkim#define BGE_MLC_INTR_STATE 0x00000001 1933166676Sjkim#define BGE_MLC_INTR_CLR 0x00000002 1934166676Sjkim#define BGE_MLC_INTR_SET 0x00000004 1935166676Sjkim#define BGE_MLC_INTR_ONATTN 0x00000008 1936166676Sjkim#define BGE_MLC_MISCIO_IN0 0x00000100 1937166676Sjkim#define BGE_MLC_MISCIO_IN1 0x00000200 1938166676Sjkim#define BGE_MLC_MISCIO_IN2 0x00000400 1939166676Sjkim#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1940166676Sjkim#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1941166676Sjkim#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1942166676Sjkim#define BGE_MLC_MISCIO_OUT0 0x00004000 1943166676Sjkim#define BGE_MLC_MISCIO_OUT1 0x00008000 1944166676Sjkim#define BGE_MLC_MISCIO_OUT2 0x00010000 1945166676Sjkim#define BGE_MLC_EXTRAM_ENB 0x00020000 1946166676Sjkim#define BGE_MLC_SRAM_SIZE 0x001C0000 1947166676Sjkim#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1948166676Sjkim#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1949166676Sjkim#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1950166676Sjkim#define BGE_MLC_AUTO_EEPROM 0x01000000 195184059Swpaul 1952166676Sjkim#define BGE_SSRAMSIZE_256KB 0x00000000 1953166676Sjkim#define BGE_SSRAMSIZE_512KB 0x00040000 1954166676Sjkim#define BGE_SSRAMSIZE_1MB 0x00080000 1955166676Sjkim#define BGE_SSRAMSIZE_2MB 0x000C0000 1956166676Sjkim#define BGE_SSRAMSIZE_4MB 0x00100000 1957166676Sjkim#define BGE_SSRAMSIZE_8MB 0x00140000 1958166676Sjkim#define BGE_SSRAMSIZE_16M 0x00180000 195984059Swpaul 196084059Swpaul/* EEPROM address register */ 1961166676Sjkim#define BGE_EEADDR_ADDRESS 0x0000FFFC 1962166676Sjkim#define BGE_EEADDR_HALFCLK 0x01FF0000 1963166676Sjkim#define BGE_EEADDR_START 0x02000000 1964166676Sjkim#define BGE_EEADDR_DEVID 0x1C000000 1965166676Sjkim#define BGE_EEADDR_RESET 0x20000000 1966166676Sjkim#define BGE_EEADDR_DONE 0x40000000 1967166676Sjkim#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 196884059Swpaul 1969166676Sjkim#define BGE_EEDEVID(x) ((x & 7) << 26) 1970166676Sjkim#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1971166676Sjkim#define BGE_HALFCLK_384SCL 0x60 1972166676Sjkim#define BGE_EE_READCMD \ 197384059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 197484059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1975166676Sjkim#define BGE_EE_WRCMD \ 197684059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 197784059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 197884059Swpaul 197984059Swpaul/* EEPROM Control register */ 1980166676Sjkim#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1981166676Sjkim#define BGE_EECTL_CLKOUT 0x00000002 1982166676Sjkim#define BGE_EECTL_CLKIN 0x00000004 1983166676Sjkim#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1984166676Sjkim#define BGE_EECTL_DATAOUT 0x00000010 1985166676Sjkim#define BGE_EECTL_DATAIN 0x00000020 198684059Swpaul 198784059Swpaul/* MDI (MII/GMII) access register */ 1988166676Sjkim#define BGE_MDI_DATA 0x00000001 1989166676Sjkim#define BGE_MDI_DIR 0x00000002 1990166676Sjkim#define BGE_MDI_SEL 0x00000004 1991166676Sjkim#define BGE_MDI_CLK 0x00000008 199284059Swpaul 1993166676Sjkim#define BGE_MEMWIN_START 0x00008000 1994166676Sjkim#define BGE_MEMWIN_END 0x0000FFFF 199584059Swpaul 199684059Swpaul 1997166676Sjkim#define BGE_MEMWIN_READ(sc, x, val) \ 199884059Swpaul do { \ 199984059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 200084059Swpaul (0xFFFF0000 & x), 4); \ 200184059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 200284059Swpaul } while(0) 200384059Swpaul 2004166676Sjkim#define BGE_MEMWIN_WRITE(sc, x, val) \ 200584059Swpaul do { \ 200684059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 200784059Swpaul (0xFFFF0000 & x), 4); \ 200884059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 200984059Swpaul } while(0) 201084059Swpaul 201184059Swpaul/* 2012161847Sdavidch * This magic number is written to the firmware mailbox at 0xb50 2013161847Sdavidch * before a software reset is issued. After the internal firmware 2014199661Syongari * has completed its initialization it will write the opposite of 2015161847Sdavidch * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2016161847Sdavidch * driver to synchronize with the firmware. 201784059Swpaul */ 2018166676Sjkim#define BGE_MAGIC_NUMBER 0x4B657654 201984059Swpaul 202084059Swpaultypedef struct { 2021159395Sglebius uint32_t bge_addr_hi; 2022159395Sglebius uint32_t bge_addr_lo; 202384059Swpaul} bge_hostaddr; 2024118026Swpaul 2025166676Sjkim#define BGE_HOSTADDR(x, y) \ 2026115200Sps do { \ 2027159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2028159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2029115200Sps } while(0) 203084059Swpaul 2031166676Sjkim#define BGE_ADDR_LO(y) \ 2032159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 2033166676Sjkim#define BGE_ADDR_HI(y) \ 2034159395Sglebius ((uint64_t) (y) >> 32) 2035118026Swpaul 203684059Swpaul/* Ring control block structure */ 203784059Swpaulstruct bge_rcb { 203884059Swpaul bge_hostaddr bge_hostaddr; 2039159395Sglebius uint32_t bge_maxlen_flags; 2040159395Sglebius uint32_t bge_nicaddr; 204184059Swpaul}; 2042153437Syongari 2043153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 2044183896Smarius bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2045166676Sjkim#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 204684059Swpaul 2047166676Sjkim#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2048166676Sjkim#define BGE_RCB_FLAG_RING_DISABLED 0x0002 204984059Swpaul 205084059Swpaulstruct bge_tx_bd { 205184059Swpaul bge_hostaddr bge_addr; 2052153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2053159395Sglebius uint16_t bge_flags; 2054159395Sglebius uint16_t bge_len; 2055159395Sglebius uint16_t bge_vlan_tag; 2056199671Syongari uint16_t bge_mss; 2057153437Syongari#else 2058159395Sglebius uint16_t bge_len; 2059159395Sglebius uint16_t bge_flags; 2060199671Syongari uint16_t bge_mss; 2061159395Sglebius uint16_t bge_vlan_tag; 2062153437Syongari#endif 206384059Swpaul}; 206484059Swpaul 2065166676Sjkim#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2066166676Sjkim#define BGE_TXBDFLAG_IP_CSUM 0x0002 2067166676Sjkim#define BGE_TXBDFLAG_END 0x0004 2068166676Sjkim#define BGE_TXBDFLAG_IP_FRAG 0x0008 2069166676Sjkim#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2070166676Sjkim#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2071166676Sjkim#define BGE_TXBDFLAG_COAL_NOW 0x0080 2072166676Sjkim#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2073166676Sjkim#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2074166676Sjkim#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2075166676Sjkim#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2076166676Sjkim#define BGE_TXBDFLAG_NO_CRC 0x8000 207784059Swpaul 2078166676Sjkim#define BGE_NIC_TXRING_ADDR(ringno, size) \ 207984059Swpaul BGE_SEND_RING_1_TO_4 + \ 208084059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 208184059Swpaul 208284059Swpaulstruct bge_rx_bd { 208384059Swpaul bge_hostaddr bge_addr; 2084153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2085159395Sglebius uint16_t bge_len; 2086159395Sglebius uint16_t bge_idx; 2087159395Sglebius uint16_t bge_flags; 2088159395Sglebius uint16_t bge_type; 2089159395Sglebius uint16_t bge_tcp_udp_csum; 2090159395Sglebius uint16_t bge_ip_csum; 2091159395Sglebius uint16_t bge_vlan_tag; 2092159395Sglebius uint16_t bge_error_flag; 2093153437Syongari#else 2094159395Sglebius uint16_t bge_idx; 2095159395Sglebius uint16_t bge_len; 2096159395Sglebius uint16_t bge_type; 2097159395Sglebius uint16_t bge_flags; 2098159395Sglebius uint16_t bge_ip_csum; 2099159395Sglebius uint16_t bge_tcp_udp_csum; 2100159395Sglebius uint16_t bge_error_flag; 2101159395Sglebius uint16_t bge_vlan_tag; 2102153437Syongari#endif 2103159395Sglebius uint32_t bge_rsvd; 2104159395Sglebius uint32_t bge_opaque; 210584059Swpaul}; 210684059Swpaul 2107153239Sglebiusstruct bge_extrx_bd { 2108153239Sglebius bge_hostaddr bge_addr1; 2109153239Sglebius bge_hostaddr bge_addr2; 2110153239Sglebius bge_hostaddr bge_addr3; 2111153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2112159395Sglebius uint16_t bge_len2; 2113159395Sglebius uint16_t bge_len1; 2114159395Sglebius uint16_t bge_rsvd1; 2115159395Sglebius uint16_t bge_len3; 2116153437Syongari#else 2117159395Sglebius uint16_t bge_len1; 2118159395Sglebius uint16_t bge_len2; 2119159395Sglebius uint16_t bge_len3; 2120159395Sglebius uint16_t bge_rsvd1; 2121153437Syongari#endif 2122153239Sglebius bge_hostaddr bge_addr0; 2123153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2124159395Sglebius uint16_t bge_len0; 2125159395Sglebius uint16_t bge_idx; 2126159395Sglebius uint16_t bge_flags; 2127159395Sglebius uint16_t bge_type; 2128159395Sglebius uint16_t bge_tcp_udp_csum; 2129159395Sglebius uint16_t bge_ip_csum; 2130159395Sglebius uint16_t bge_vlan_tag; 2131159395Sglebius uint16_t bge_error_flag; 2132153437Syongari#else 2133159395Sglebius uint16_t bge_idx; 2134159395Sglebius uint16_t bge_len0; 2135159395Sglebius uint16_t bge_type; 2136159395Sglebius uint16_t bge_flags; 2137159395Sglebius uint16_t bge_ip_csum; 2138159395Sglebius uint16_t bge_tcp_udp_csum; 2139159395Sglebius uint16_t bge_error_flag; 2140159395Sglebius uint16_t bge_vlan_tag; 2141153437Syongari#endif 2142159395Sglebius uint32_t bge_rsvd0; 2143159395Sglebius uint32_t bge_opaque; 2144153239Sglebius}; 2145153239Sglebius 2146166676Sjkim#define BGE_RXBDFLAG_END 0x0004 2147166676Sjkim#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2148166676Sjkim#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2149166676Sjkim#define BGE_RXBDFLAG_ERROR 0x0400 2150166676Sjkim#define BGE_RXBDFLAG_MINI_RING 0x0800 2151166676Sjkim#define BGE_RXBDFLAG_IP_CSUM 0x1000 2152166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2153166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 215484059Swpaul 2155166676Sjkim#define BGE_RXERRFLAG_BAD_CRC 0x0001 2156166676Sjkim#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2157166676Sjkim#define BGE_RXERRFLAG_LINK_LOST 0x0004 2158166676Sjkim#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2159166676Sjkim#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2160166676Sjkim#define BGE_RXERRFLAG_RUNT 0x0020 2161166676Sjkim#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2162166676Sjkim#define BGE_RXERRFLAG_GIANT 0x0080 216384059Swpaul 216484059Swpaulstruct bge_sts_idx { 2165153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2166159395Sglebius uint16_t bge_rx_prod_idx; 2167159395Sglebius uint16_t bge_tx_cons_idx; 2168153437Syongari#else 2169159395Sglebius uint16_t bge_tx_cons_idx; 2170159395Sglebius uint16_t bge_rx_prod_idx; 2171153437Syongari#endif 217284059Swpaul}; 217384059Swpaul 217484059Swpaulstruct bge_status_block { 2175159395Sglebius uint32_t bge_status; 2176159395Sglebius uint32_t bge_rsvd0; 2177153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2178159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2179159395Sglebius uint16_t bge_rx_std_cons_idx; 2180159395Sglebius uint16_t bge_rx_mini_cons_idx; 2181159395Sglebius uint16_t bge_rsvd1; 2182153437Syongari#else 2183159395Sglebius uint16_t bge_rx_std_cons_idx; 2184159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2185159395Sglebius uint16_t bge_rsvd1; 2186159395Sglebius uint16_t bge_rx_mini_cons_idx; 2187153437Syongari#endif 218884059Swpaul struct bge_sts_idx bge_idx[16]; 218984059Swpaul}; 219084059Swpaul 2191166676Sjkim#define BGE_STATFLAG_UPDATED 0x00000001 2192166676Sjkim#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2193166676Sjkim#define BGE_STATFLAG_ERROR 0x00000004 219484059Swpaul 219584059Swpaul 219684059Swpaul/* 219784059Swpaul * Broadcom Vendor ID 219884059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 219984059Swpaul * even though they're now manufactured by Broadcom) 220084059Swpaul */ 2201166676Sjkim#define BCOM_VENDORID 0x14E4 2202166676Sjkim#define BCOM_DEVICEID_BCM5700 0x1644 2203166676Sjkim#define BCOM_DEVICEID_BCM5701 0x1645 2204166676Sjkim#define BCOM_DEVICEID_BCM5702 0x1646 2205166676Sjkim#define BCOM_DEVICEID_BCM5702X 0x16A6 2206166676Sjkim#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2207166676Sjkim#define BCOM_DEVICEID_BCM5703 0x1647 2208166676Sjkim#define BCOM_DEVICEID_BCM5703X 0x16A7 2209166676Sjkim#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2210166676Sjkim#define BCOM_DEVICEID_BCM5704C 0x1648 2211166676Sjkim#define BCOM_DEVICEID_BCM5704S 0x16A8 2212166676Sjkim#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2213166676Sjkim#define BCOM_DEVICEID_BCM5705 0x1653 2214166676Sjkim#define BCOM_DEVICEID_BCM5705K 0x1654 2215166676Sjkim#define BCOM_DEVICEID_BCM5705F 0x166E 2216166676Sjkim#define BCOM_DEVICEID_BCM5705M 0x165D 2217166676Sjkim#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2218166676Sjkim#define BCOM_DEVICEID_BCM5714C 0x1668 2219166676Sjkim#define BCOM_DEVICEID_BCM5714S 0x1669 2220166676Sjkim#define BCOM_DEVICEID_BCM5715 0x1678 2221166676Sjkim#define BCOM_DEVICEID_BCM5715S 0x1679 2222166676Sjkim#define BCOM_DEVICEID_BCM5720 0x1658 2223166676Sjkim#define BCOM_DEVICEID_BCM5721 0x1659 2224176883Sjhb#define BCOM_DEVICEID_BCM5722 0x165A 2225197832Sstas#define BCOM_DEVICEID_BCM5723 0x165B 2226166676Sjkim#define BCOM_DEVICEID_BCM5750 0x1676 2227166676Sjkim#define BCOM_DEVICEID_BCM5750M 0x167C 2228166676Sjkim#define BCOM_DEVICEID_BCM5751 0x1677 2229166676Sjkim#define BCOM_DEVICEID_BCM5751F 0x167E 2230166676Sjkim#define BCOM_DEVICEID_BCM5751M 0x167D 2231166676Sjkim#define BCOM_DEVICEID_BCM5752 0x1600 2232166676Sjkim#define BCOM_DEVICEID_BCM5752M 0x1601 2233166676Sjkim#define BCOM_DEVICEID_BCM5753 0x16F7 2234166676Sjkim#define BCOM_DEVICEID_BCM5753F 0x16FE 2235166676Sjkim#define BCOM_DEVICEID_BCM5753M 0x16FD 2236166676Sjkim#define BCOM_DEVICEID_BCM5754 0x167A 2237166676Sjkim#define BCOM_DEVICEID_BCM5754M 0x1672 2238166676Sjkim#define BCOM_DEVICEID_BCM5755 0x167B 2239166676Sjkim#define BCOM_DEVICEID_BCM5755M 0x1673 2240202268Sdelphij#define BCOM_DEVICEID_BCM5756 0x1674 2241197832Sstas#define BCOM_DEVICEID_BCM5761 0x1681 2242197832Sstas#define BCOM_DEVICEID_BCM5761E 0x1680 2243197832Sstas#define BCOM_DEVICEID_BCM5761S 0x1688 2244197832Sstas#define BCOM_DEVICEID_BCM5761SE 0x1689 2245197832Sstas#define BCOM_DEVICEID_BCM5764 0x1684 2246166676Sjkim#define BCOM_DEVICEID_BCM5780 0x166A 2247166676Sjkim#define BCOM_DEVICEID_BCM5780S 0x166B 2248166676Sjkim#define BCOM_DEVICEID_BCM5781 0x16DD 2249166676Sjkim#define BCOM_DEVICEID_BCM5782 0x1696 2250197832Sstas#define BCOM_DEVICEID_BCM5784 0x1698 2251197832Sstas#define BCOM_DEVICEID_BCM5785F 0x16a0 2252197832Sstas#define BCOM_DEVICEID_BCM5785G 0x1699 2253166676Sjkim#define BCOM_DEVICEID_BCM5786 0x169A 2254166676Sjkim#define BCOM_DEVICEID_BCM5787 0x169B 2255166676Sjkim#define BCOM_DEVICEID_BCM5787M 0x1693 2256197832Sstas#define BCOM_DEVICEID_BCM5787F 0x167f 2257166676Sjkim#define BCOM_DEVICEID_BCM5788 0x169C 2258166676Sjkim#define BCOM_DEVICEID_BCM5789 0x169D 2259166676Sjkim#define BCOM_DEVICEID_BCM5901 0x170D 2260166676Sjkim#define BCOM_DEVICEID_BCM5901A2 0x170E 2261166676Sjkim#define BCOM_DEVICEID_BCM5903M 0x16FF 2262178667Sjhb#define BCOM_DEVICEID_BCM5906 0x1712 2263178667Sjhb#define BCOM_DEVICEID_BCM5906M 0x1713 2264197832Sstas#define BCOM_DEVICEID_BCM57760 0x1690 2265197832Sstas#define BCOM_DEVICEID_BCM57780 0x1692 2266197832Sstas#define BCOM_DEVICEID_BCM57788 0x1691 2267197832Sstas#define BCOM_DEVICEID_BCM57790 0x1694 226884059Swpaul 226984059Swpaul/* 227084059Swpaul * Alteon AceNIC PCI vendor/device ID. 227184059Swpaul */ 2272166676Sjkim#define ALTEON_VENDORID 0x12AE 2273166676Sjkim#define ALTEON_DEVICEID_ACENIC 0x0001 2274166676Sjkim#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2275166676Sjkim#define ALTEON_DEVICEID_BCM5700 0x0003 2276166676Sjkim#define ALTEON_DEVICEID_BCM5701 0x0004 227784059Swpaul 227884059Swpaul/* 2279162982Sglebius * 3Com 3c996 PCI vendor/device ID. 228084059Swpaul */ 2281166676Sjkim#define TC_VENDORID 0x10B7 2282166676Sjkim#define TC_DEVICEID_3C996 0x0003 228384059Swpaul 228484059Swpaul/* 228584059Swpaul * SysKonnect PCI vendor ID 228684059Swpaul */ 2287166676Sjkim#define SK_VENDORID 0x1148 2288166676Sjkim#define SK_DEVICEID_ALTIMA 0x4400 2289166676Sjkim#define SK_SUBSYSID_9D21 0x4421 2290166676Sjkim#define SK_SUBSYSID_9D41 0x4441 229184059Swpaul 229284059Swpaul/* 229389835Sjdp * Altima PCI vendor/device ID. 229489835Sjdp */ 2295166676Sjkim#define ALTIMA_VENDORID 0x173b 2296166676Sjkim#define ALTIMA_DEVICE_AC1000 0x03e8 2297166676Sjkim#define ALTIMA_DEVICE_AC1002 0x03e9 2298166676Sjkim#define ALTIMA_DEVICE_AC9100 0x03ea 229989835Sjdp 230089835Sjdp/* 2301119157Sambrisko * Dell PCI vendor ID 2302119157Sambrisko */ 2303119157Sambrisko 2304166676Sjkim#define DELL_VENDORID 0x1028 2305119157Sambrisko 2306119157Sambrisko/* 2307159637Sglebius * Apple PCI vendor ID. 2308159637Sglebius */ 2309166676Sjkim#define APPLE_VENDORID 0x106b 2310166676Sjkim#define APPLE_DEVICE_BCM5701 0x1645 2311159637Sglebius 2312159637Sglebius/* 2313169152Smarius * Sun PCI vendor ID 2314169152Smarius */ 2315169152Smarius#define SUN_VENDORID 0x108e 2316169152Smarius 2317169152Smarius/* 2318197832Sstas * Fujitsu vendor/device IDs 2319197832Sstas */ 2320197832Sstas#define FJTSU_VENDORID 0x10cf 2321197832Sstas#define FJTSU_DEVICEID_PW008GE5 0x11a1 2322197832Sstas#define FJTSU_DEVICEID_PW008GE4 0x11a2 2323197832Sstas#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2324197832Sstas 2325197832Sstas/* 232684059Swpaul * Offset of MAC address inside EEPROM. 232784059Swpaul */ 2328166676Sjkim#define BGE_EE_MAC_OFFSET 0x7C 2329178667Sjhb#define BGE_EE_MAC_OFFSET_5906 0x10 2330166676Sjkim#define BGE_EE_HWCFG_OFFSET 0xC8 233184059Swpaul 2332166676Sjkim#define BGE_HWCFG_VOLTAGE 0x00000003 2333166676Sjkim#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2334166676Sjkim#define BGE_HWCFG_MEDIA 0x00000030 2335166676Sjkim#define BGE_HWCFG_ASF 0x00000080 233693751Swpaul 2337166676Sjkim#define BGE_VOLTAGE_1POINT3 0x00000000 2338166676Sjkim#define BGE_VOLTAGE_1POINT8 0x00000001 233993751Swpaul 2340166676Sjkim#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2341166676Sjkim#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2342166676Sjkim#define BGE_PHYLEDMODE_SINGLELED 0x00000008 234393751Swpaul 2344166676Sjkim#define BGE_MEDIA_UNSPEC 0x00000000 2345166676Sjkim#define BGE_MEDIA_COPPER 0x00000010 2346166676Sjkim#define BGE_MEDIA_FIBER 0x00000020 234793751Swpaul 2348166676Sjkim#define BGE_TICKS_PER_SEC 1000000 234984059Swpaul 235084059Swpaul/* 235184059Swpaul * Ring size constants. 235284059Swpaul */ 2353166676Sjkim#define BGE_EVENT_RING_CNT 256 2354166676Sjkim#define BGE_CMD_RING_CNT 64 2355166676Sjkim#define BGE_STD_RX_RING_CNT 512 2356166676Sjkim#define BGE_JUMBO_RX_RING_CNT 256 2357166676Sjkim#define BGE_MINI_RX_RING_CNT 1024 2358166676Sjkim#define BGE_RETURN_RING_CNT 1024 235984059Swpaul 2360117659Swpaul/* 5705 has smaller return ring size */ 2361117659Swpaul 2362166676Sjkim#define BGE_RETURN_RING_CNT_5705 512 2363117659Swpaul 236484059Swpaul/* 236584059Swpaul * Possible TX ring sizes. 236684059Swpaul */ 2367166676Sjkim#define BGE_TX_RING_CNT_128 128 2368166676Sjkim#define BGE_TX_RING_BASE_128 0x3800 236984059Swpaul 2370166676Sjkim#define BGE_TX_RING_CNT_256 256 2371166676Sjkim#define BGE_TX_RING_BASE_256 0x3000 237284059Swpaul 2373166676Sjkim#define BGE_TX_RING_CNT_512 512 2374166676Sjkim#define BGE_TX_RING_BASE_512 0x2000 237584059Swpaul 2376166676Sjkim#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2377166676Sjkim#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 237884059Swpaul 237984059Swpaul/* 238084059Swpaul * Tigon III statistics counters. 238184059Swpaul */ 2382117659Swpaul/* Statistics maintained MAC Receive block. */ 2383117659Swpaulstruct bge_rx_mac_stats { 238484059Swpaul bge_hostaddr ifHCInOctets; 238584059Swpaul bge_hostaddr Reserved1; 238684059Swpaul bge_hostaddr etherStatsFragments; 238784059Swpaul bge_hostaddr ifHCInUcastPkts; 238884059Swpaul bge_hostaddr ifHCInMulticastPkts; 238984059Swpaul bge_hostaddr ifHCInBroadcastPkts; 239084059Swpaul bge_hostaddr dot3StatsFCSErrors; 239184059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 239284059Swpaul bge_hostaddr xonPauseFramesReceived; 239384059Swpaul bge_hostaddr xoffPauseFramesReceived; 239484059Swpaul bge_hostaddr macControlFramesReceived; 239584059Swpaul bge_hostaddr xoffStateEntered; 239684059Swpaul bge_hostaddr dot3StatsFramesTooLong; 239784059Swpaul bge_hostaddr etherStatsJabbers; 239884059Swpaul bge_hostaddr etherStatsUndersizePkts; 239984059Swpaul bge_hostaddr inRangeLengthError; 240084059Swpaul bge_hostaddr outRangeLengthError; 240184059Swpaul bge_hostaddr etherStatsPkts64Octets; 240284059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 240384059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 240484059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 240584059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 240684059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 240784059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 240884059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 240984059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 241084059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2411117659Swpaul}; 241284059Swpaul 241384059Swpaul 2414117659Swpaul/* Statistics maintained MAC Transmit block. */ 2415117659Swpaulstruct bge_tx_mac_stats { 241684059Swpaul bge_hostaddr ifHCOutOctets; 241784059Swpaul bge_hostaddr Reserved2; 241884059Swpaul bge_hostaddr etherStatsCollisions; 241984059Swpaul bge_hostaddr outXonSent; 242084059Swpaul bge_hostaddr outXoffSent; 242184059Swpaul bge_hostaddr flowControlDone; 242284059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 242384059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 242484059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 242584059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 242684059Swpaul bge_hostaddr Reserved3; 242784059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 242884059Swpaul bge_hostaddr dot3StatsLateCollisions; 242984059Swpaul bge_hostaddr dot3Collided2Times; 243084059Swpaul bge_hostaddr dot3Collided3Times; 243184059Swpaul bge_hostaddr dot3Collided4Times; 243284059Swpaul bge_hostaddr dot3Collided5Times; 243384059Swpaul bge_hostaddr dot3Collided6Times; 243484059Swpaul bge_hostaddr dot3Collided7Times; 243584059Swpaul bge_hostaddr dot3Collided8Times; 243684059Swpaul bge_hostaddr dot3Collided9Times; 243784059Swpaul bge_hostaddr dot3Collided10Times; 243884059Swpaul bge_hostaddr dot3Collided11Times; 243984059Swpaul bge_hostaddr dot3Collided12Times; 244084059Swpaul bge_hostaddr dot3Collided13Times; 244184059Swpaul bge_hostaddr dot3Collided14Times; 244284059Swpaul bge_hostaddr dot3Collided15Times; 244384059Swpaul bge_hostaddr ifHCOutUcastPkts; 244484059Swpaul bge_hostaddr ifHCOutMulticastPkts; 244584059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 244684059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 244784059Swpaul bge_hostaddr ifOutDiscards; 244884059Swpaul bge_hostaddr ifOutErrors; 2449117659Swpaul}; 245084059Swpaul 2451117659Swpaul/* Stats counters access through registers */ 2452213283Syongaristruct bge_mac_stats { 2453213283Syongari /* TX MAC statistics */ 2454213283Syongari uint64_t ifHCOutOctets; 2455213283Syongari uint64_t Reserved0; 2456213283Syongari uint64_t etherStatsCollisions; 2457213283Syongari uint64_t outXonSent; 2458213283Syongari uint64_t outXoffSent; 2459213283Syongari uint64_t Reserved1; 2460213283Syongari uint64_t dot3StatsInternalMacTransmitErrors; 2461213283Syongari uint64_t dot3StatsSingleCollisionFrames; 2462213283Syongari uint64_t dot3StatsMultipleCollisionFrames; 2463213283Syongari uint64_t dot3StatsDeferredTransmissions; 2464213283Syongari uint64_t Reserved2; 2465213283Syongari uint64_t dot3StatsExcessiveCollisions; 2466213283Syongari uint64_t dot3StatsLateCollisions; 2467213283Syongari uint64_t Reserved3[14]; 2468213283Syongari uint64_t ifHCOutUcastPkts; 2469213283Syongari uint64_t ifHCOutMulticastPkts; 2470213283Syongari uint64_t ifHCOutBroadcastPkts; 2471213283Syongari uint64_t Reserved4[2]; 2472213283Syongari /* RX MAC statistics */ 2473213283Syongari uint64_t ifHCInOctets; 2474213283Syongari uint64_t Reserved5; 2475213283Syongari uint64_t etherStatsFragments; 2476213283Syongari uint64_t ifHCInUcastPkts; 2477213283Syongari uint64_t ifHCInMulticastPkts; 2478213283Syongari uint64_t ifHCInBroadcastPkts; 2479213283Syongari uint64_t dot3StatsFCSErrors; 2480213283Syongari uint64_t dot3StatsAlignmentErrors; 2481213283Syongari uint64_t xonPauseFramesReceived; 2482213283Syongari uint64_t xoffPauseFramesReceived; 2483213283Syongari uint64_t macControlFramesReceived; 2484213283Syongari uint64_t xoffStateEntered; 2485213283Syongari uint64_t dot3StatsFramesTooLong; 2486213283Syongari uint64_t etherStatsJabbers; 2487213283Syongari uint64_t etherStatsUndersizePkts; 2488213283Syongari /* Receive List Placement control */ 2489213283Syongari uint64_t FramesDroppedDueToFilters; 2490213283Syongari uint64_t DmaWriteQueueFull; 2491213283Syongari uint64_t DmaWriteHighPriQueueFull; 2492213283Syongari uint64_t NoMoreRxBDs; 2493213283Syongari uint64_t InputDiscards; 2494213283Syongari uint64_t InputErrors; 2495213283Syongari uint64_t RecvThresholdHit; 2496117659Swpaul}; 2497117659Swpaul 2498117659Swpaulstruct bge_stats { 2499159395Sglebius uint8_t Reserved0[256]; 2500117659Swpaul 2501117659Swpaul /* Statistics maintained by Receive MAC. */ 2502117659Swpaul struct bge_rx_mac_stats rxstats; 2503117659Swpaul 2504117659Swpaul bge_hostaddr Unused1[37]; 2505117659Swpaul 2506117659Swpaul /* Statistics maintained by Transmit MAC. */ 2507117659Swpaul struct bge_tx_mac_stats txstats; 2508117659Swpaul 250984059Swpaul bge_hostaddr Unused2[31]; 251084059Swpaul 251184059Swpaul /* Statistics maintained by Receive List Placement. */ 251284059Swpaul bge_hostaddr COSIfHCInPkts[16]; 251384059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 251484059Swpaul bge_hostaddr nicDmaWriteQueueFull; 251584059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 251684059Swpaul bge_hostaddr nicNoMoreRxBDs; 251784059Swpaul bge_hostaddr ifInDiscards; 251884059Swpaul bge_hostaddr ifInErrors; 251984059Swpaul bge_hostaddr nicRecvThresholdHit; 252084059Swpaul 252184059Swpaul bge_hostaddr Unused3[9]; 252284059Swpaul 252384059Swpaul /* Statistics maintained by Send Data Initiator. */ 252484059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 252584059Swpaul bge_hostaddr nicDmaReadQueueFull; 252684059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 252784059Swpaul bge_hostaddr nicSendDataCompQueueFull; 252884059Swpaul 252984059Swpaul /* Statistics maintained by Host Coalescing. */ 253084059Swpaul bge_hostaddr nicRingSetSendProdIndex; 253184059Swpaul bge_hostaddr nicRingStatusUpdate; 253284059Swpaul bge_hostaddr nicInterrupts; 253384059Swpaul bge_hostaddr nicAvoidedInterrupts; 253484059Swpaul bge_hostaddr nicSendThresholdHit; 253584059Swpaul 2536159395Sglebius uint8_t Reserved4[320]; 253784059Swpaul}; 253884059Swpaul 253984059Swpaul/* 254084059Swpaul * Tigon general information block. This resides in host memory 254184059Swpaul * and contains the status counters, ring control blocks and 254284059Swpaul * producer pointers. 254384059Swpaul */ 254484059Swpaul 254584059Swpaulstruct bge_gib { 254684059Swpaul struct bge_stats bge_stats; 254784059Swpaul struct bge_rcb bge_tx_rcb[16]; 254884059Swpaul struct bge_rcb bge_std_rx_rcb; 254984059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 255084059Swpaul struct bge_rcb bge_mini_rx_rcb; 255184059Swpaul struct bge_rcb bge_return_rcb; 255284059Swpaul}; 255384059Swpaul 2554166676Sjkim#define BGE_FRAMELEN 1518 2555166676Sjkim#define BGE_MAX_FRAMELEN 1536 2556166676Sjkim#define BGE_JUMBO_FRAMELEN 9018 2557166676Sjkim#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2558166676Sjkim#define BGE_MIN_FRAMELEN 60 255984059Swpaul 256084059Swpaul/* 256184059Swpaul * Other utility macros. 256284059Swpaul */ 2563166676Sjkim#define BGE_INC(x, y) (x) = (x + 1) % y 256484059Swpaul 256584059Swpaul/* 256684059Swpaul * Register access macros. The Tigon always uses memory mapped register 256784059Swpaul * accesses and all registers must be accessed with 32 bit operations. 256884059Swpaul */ 256984059Swpaul 2570166676Sjkim#define CSR_WRITE_4(sc, reg, val) \ 2571183896Smarius bus_write_4(sc->bge_res, reg, val) 257284059Swpaul 2573166676Sjkim#define CSR_READ_4(sc, reg) \ 2574183896Smarius bus_read_4(sc->bge_res, reg) 257584059Swpaul 2576166676Sjkim#define BGE_SETBIT(sc, reg, x) \ 2577106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2578166676Sjkim#define BGE_CLRBIT(sc, reg, x) \ 2579106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 258084059Swpaul 2581166676Sjkim#define PCI_SETBIT(dev, reg, x, s) \ 2582106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2583166676Sjkim#define PCI_CLRBIT(dev, reg, x, s) \ 2584106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 258584059Swpaul 258684059Swpaul/* 2587208917Syongari * Memory management stuff. 258884059Swpaul */ 258984059Swpaul 2590166676Sjkim#define BGE_NSEG_JUMBO 4 2591199671Syongari#define BGE_NSEG_NEW 32 2592199671Syongari#define BGE_TSOSEG_SZ 4096 2593153239Sglebius 2594199670Syongari/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2595199670Syongari#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2596199670Syongari#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2597199670Syongari#else 2598199670Syongari#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2599199670Syongari#endif 2600199670Syongari 2601212065Syongari#ifdef PAE 2602212065Syongari#define BGE_DMA_BNDRY 0x80000000 2603212065Syongari#else 2604212061Syongari#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2605212065Syongari#define BGE_DMA_BNDRY 0x100000000 2606212061Syongari#else 2607212065Syongari#define BGE_DMA_BNDRY 0 2608212061Syongari#endif 2609212065Syongari#endif 2610212061Syongari 261184059Swpaul/* 261284059Swpaul * Ring structures. Most of these reside in host memory and we tell 261384059Swpaul * the NIC where they are via the ring control blocks. The exceptions 261484059Swpaul * are the tx and command rings, which live in NIC memory and which 261584059Swpaul * we access via the shared memory window. 261684059Swpaul */ 2617118026Swpaul 261884059Swpaulstruct bge_ring_data { 2619118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2620118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2621153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2622118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2623118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2624118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2625118026Swpaul struct bge_tx_bd *bge_tx_ring; 2626118026Swpaul bus_addr_t bge_tx_ring_paddr; 2627118026Swpaul struct bge_status_block *bge_status_block; 2628118026Swpaul bus_addr_t bge_status_block_paddr; 2629118026Swpaul struct bge_stats *bge_stats; 2630118026Swpaul bus_addr_t bge_stats_paddr; 263184059Swpaul struct bge_gib bge_info; 263284059Swpaul}; 263384059Swpaul 2634166676Sjkim#define BGE_STD_RX_RING_SZ \ 2635118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2636166676Sjkim#define BGE_JUMBO_RX_RING_SZ \ 2637153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2638166676Sjkim#define BGE_TX_RING_SZ \ 2639118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2640166676Sjkim#define BGE_RX_RTN_RING_SZ(x) \ 2641118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2642118026Swpaul 2643166676Sjkim#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2644118026Swpaul 2645166676Sjkim#define BGE_STATS_SZ sizeof (struct bge_stats) 2646118026Swpaul 264784059Swpaul/* 264884059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 264984059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 265084059Swpaul * not the other way around. 265184059Swpaul */ 265284059Swpaulstruct bge_chain_data { 2653118026Swpaul bus_dma_tag_t bge_parent_tag; 2654212061Syongari bus_dma_tag_t bge_buffer_tag; 2655118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2656118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2657118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2658118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2659118026Swpaul bus_dma_tag_t bge_status_tag; 2660118026Swpaul bus_dma_tag_t bge_stats_tag; 2661198927Syongari bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2662198927Syongari bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2663198927Syongari bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2664118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2665199011Syongari bus_dmamap_t bge_rx_std_sparemap; 2666118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2667199011Syongari bus_dmamap_t bge_rx_jumbo_sparemap; 2668118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2669118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2670118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2671118026Swpaul bus_dmamap_t bge_tx_ring_map; 2672118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2673118026Swpaul bus_dmamap_t bge_status_map; 2674118026Swpaul bus_dmamap_t bge_stats_map; 267584059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 267684059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 267784059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2678208862Syongari int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2679208862Syongari int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 268084059Swpaul}; 268184059Swpaul 2682118026Swpaulstruct bge_dmamap_arg { 2683118026Swpaul bus_addr_t bge_busaddr; 2684118026Swpaul}; 2685118026Swpaul 2686166676Sjkim#define BGE_HWREV_TIGON 0x01 2687166676Sjkim#define BGE_HWREV_TIGON_II 0x02 2688166676Sjkim#define BGE_TIMEOUT 100000 2689166676Sjkim#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 269084059Swpaul 269184059Swpaulstruct bge_bcom_hack { 269284059Swpaul int reg; 269384059Swpaul int val; 269484059Swpaul}; 269584059Swpaul 2696166676Sjkim#define ASF_ENABLE 1 2697166676Sjkim#define ASF_NEW_HANDSHAKE 2 2698166676Sjkim#define ASF_STACKUP 4 2699162169Sambrisko 270084059Swpaulstruct bge_softc { 2701147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 270284059Swpaul device_t bge_dev; 2703122497Ssam struct mtx bge_mtx; 270484059Swpaul device_t bge_miibus; 270584059Swpaul void *bge_intrhand; 270684059Swpaul struct resource *bge_irq; 270784059Swpaul struct resource *bge_res; 270884059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2709199664Syongari int bge_expcap; 2710199664Syongari int bge_msicap; 2711199664Syongari int bge_pcixcap; 2712161546Sglebius uint32_t bge_flags; 2713166676Sjkim#define BGE_FLAG_TBI 0x00000001 2714166676Sjkim#define BGE_FLAG_JUMBO 0x00000002 2715178996Smarius#define BGE_FLAG_EADDR 0x00000008 2716202293Syongari#define BGE_FLAG_MII_SERDES 0x00000010 2717213485Syongari#define BGE_FLAG_CPMU_PRESENT 0x00000020 2718166676Sjkim#define BGE_FLAG_MSI 0x00000100 2719166676Sjkim#define BGE_FLAG_PCIX 0x00000200 2720166676Sjkim#define BGE_FLAG_PCIE 0x00000400 2721199671Syongari#define BGE_FLAG_TSO 0x00000800 2722213464Syongari#define BGE_FLAG_5700_FAMILY 0x00010000 2723213464Syongari#define BGE_FLAG_5705_PLUS 0x00020000 2724213464Syongari#define BGE_FLAG_5714_FAMILY 0x00040000 2725213464Syongari#define BGE_FLAG_575X_PLUS 0x00080000 2726213464Syongari#define BGE_FLAG_5755_PLUS 0x00100000 2727213464Syongari#define BGE_FLAG_5788 0x00200000 2728213464Syongari#define BGE_FLAG_40BIT_BUG 0x01000000 2729213464Syongari#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2730213464Syongari#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2731214087Syongari#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2732213464Syongari uint32_t bge_phy_flags; 2733213464Syongari#define BGE_PHY_WIRESPEED 0x00000001 2734213464Syongari#define BGE_PHY_ADC_BUG 0x00000002 2735213464Syongari#define BGE_PHY_5704_A0_BUG 0x00000004 2736213464Syongari#define BGE_PHY_JITTER_BUG 0x00000008 2737213464Syongari#define BGE_PHY_BER_BUG 0x00000010 2738213464Syongari#define BGE_PHY_ADJUST_TRIM 0x00000020 2739213464Syongari#define BGE_PHY_CRC_BUG 0x00000040 2740213464Syongari#define BGE_PHY_NO_3LED 0x00000080 2741159395Sglebius uint32_t bge_chipid; 2742197832Sstas uint32_t bge_asicrev; 2743197832Sstas uint32_t bge_chiprev; 2744162169Sambrisko uint8_t bge_asf_mode; 2745162169Sambrisko uint8_t bge_asf_count; 2746118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 274784059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 2748159395Sglebius uint16_t bge_tx_saved_considx; 2749159395Sglebius uint16_t bge_rx_saved_considx; 2750159395Sglebius uint16_t bge_ev_saved_considx; 2751159395Sglebius uint16_t bge_return_ring_cnt; 2752159395Sglebius uint16_t bge_std; /* current std ring head */ 2753159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 2754159395Sglebius uint32_t bge_stat_ticks; 2755159395Sglebius uint32_t bge_rx_coal_ticks; 2756159395Sglebius uint32_t bge_tx_coal_ticks; 2757159395Sglebius uint32_t bge_tx_prodidx; 2758159395Sglebius uint32_t bge_rx_max_coal_bds; 2759159395Sglebius uint32_t bge_tx_max_coal_bds; 2760213485Syongari uint32_t bge_mi_mode; 276184059Swpaul int bge_if_flags; 276284059Swpaul int bge_txcnt; 2763155180Soleg int bge_link; /* link state */ 2764155180Soleg int bge_link_evt; /* pending link event */ 2765164769Sglebius int bge_timer; 2766200264Syongari int bge_forced_collapse; 2767211596Syongari int bge_forced_udpcsum; 2768211596Syongari int bge_csum_features; 2769122497Ssam struct callout bge_stat_ch; 2770164780Sjkim uint32_t bge_rx_discards; 2771164780Sjkim uint32_t bge_tx_discards; 2772164780Sjkim uint32_t bge_tx_collisions; 2773151553Sglebius#ifdef DEVICE_POLLING 2774151553Sglebius int rxcycles; 2775151553Sglebius#endif /* DEVICE_POLLING */ 2776213283Syongari struct bge_mac_stats bge_mac_stats; 2777199668Syongari struct task bge_intr_task; 2778199668Syongari struct taskqueue *bge_tq; 277984059Swpaul}; 2780122497Ssam 2781122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2782122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2783122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2784122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2785122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2786122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2787