if_bgereg.h revision 200264
1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 200264 2009-12-08 17:54:23Z yongari $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 64166676Sjkim#define BGE_PAGE_ZERO 0x00000000 65166676Sjkim#define BGE_PAGE_ZERO_END 0x000000FF 66166676Sjkim#define BGE_SEND_RING_RCB 0x00000100 67166676Sjkim#define BGE_SEND_RING_RCB_END 0x000001FF 68166676Sjkim#define BGE_RX_RETURN_RING_RCB 0x00000200 69166676Sjkim#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70166676Sjkim#define BGE_STATS_BLOCK 0x00000300 71166676Sjkim#define BGE_STATS_BLOCK_END 0x00000AFF 72166676Sjkim#define BGE_STATUS_BLOCK 0x00000B00 73166676Sjkim#define BGE_STATUS_BLOCK_END 0x00000B4F 74166676Sjkim#define BGE_SOFTWARE_GENCOMM 0x00000B50 75166676Sjkim#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76166676Sjkim#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77166676Sjkim#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78166676Sjkim#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79166676Sjkim#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80166676Sjkim#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81166676Sjkim#define BGE_UNMAPPED 0x00001000 82166676Sjkim#define BGE_UNMAPPED_END 0x00001FFF 83166676Sjkim#define BGE_DMA_DESCRIPTORS 0x00002000 84166676Sjkim#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85166676Sjkim#define BGE_SEND_RING_1_TO_4 0x00004000 86166676Sjkim#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8784059Swpaul 88166676Sjkim/* Firmware interface */ 89166676Sjkim#define BGE_FW_DRV_ALIVE 0x00000001 90166676Sjkim#define BGE_FW_PAUSE 0x00000002 91166676Sjkim 9284059Swpaul/* Mappings for internal memory configuration */ 93166676Sjkim#define BGE_STD_RX_RINGS 0x00006000 94166676Sjkim#define BGE_STD_RX_RINGS_END 0x00006FFF 95166676Sjkim#define BGE_JUMBO_RX_RINGS 0x00007000 96166676Sjkim#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97166676Sjkim#define BGE_BUFFPOOL_1 0x00008000 98166676Sjkim#define BGE_BUFFPOOL_1_END 0x0000FFFF 99166676Sjkim#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 100166676Sjkim#define BGE_BUFFPOOL_2_END 0x00017FFF 101166676Sjkim#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 102166676Sjkim#define BGE_BUFFPOOL_3_END 0x0001FFFF 10384059Swpaul 10484059Swpaul/* Mappings for external SSRAM configurations */ 105166676Sjkim#define BGE_SEND_RING_5_TO_6 0x00006000 106166676Sjkim#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107166676Sjkim#define BGE_SEND_RING_7_TO_8 0x00007000 108166676Sjkim#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109166676Sjkim#define BGE_SEND_RING_9_TO_16 0x00008000 110166676Sjkim#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111166676Sjkim#define BGE_EXT_STD_RX_RINGS 0x0000C000 112166676Sjkim#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115166676Sjkim#define BGE_MINI_RX_RINGS 0x0000E000 116166676Sjkim#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117166676Sjkim#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 118166676Sjkim#define BGE_AVAIL_REGION1_END 0x00017FFF 119166676Sjkim#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 120166676Sjkim#define BGE_AVAIL_REGION2_END 0x0001FFFF 121166676Sjkim#define BGE_EXT_SSRAM 0x00020000 122166676Sjkim#define BGE_EXT_SSRAM_END 0x000FFFFF 12384059Swpaul 12484059Swpaul 12584059Swpaul/* 12684059Swpaul * BCM570x register offsets. These are memory mapped registers 12784059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12884059Swpaul * Each register must be accessed using 32 bit operations. 12984059Swpaul * 13084059Swpaul * All registers are accessed through a 32K shared memory block. 13184059Swpaul * The first group of registers are actually copies of the PCI 13284059Swpaul * configuration space registers. 13384059Swpaul */ 13484059Swpaul 13584059Swpaul/* 13684059Swpaul * PCI registers defined in the PCI 2.2 spec. 13784059Swpaul */ 138166676Sjkim#define BGE_PCI_VID 0x00 139166676Sjkim#define BGE_PCI_DID 0x02 140166676Sjkim#define BGE_PCI_CMD 0x04 141166676Sjkim#define BGE_PCI_STS 0x06 142166676Sjkim#define BGE_PCI_REV 0x08 143166676Sjkim#define BGE_PCI_CLASS 0x09 144166676Sjkim#define BGE_PCI_CACHESZ 0x0C 145166676Sjkim#define BGE_PCI_LATTIMER 0x0D 146166676Sjkim#define BGE_PCI_HDRTYPE 0x0E 147166676Sjkim#define BGE_PCI_BIST 0x0F 148166676Sjkim#define BGE_PCI_BAR0 0x10 149166676Sjkim#define BGE_PCI_BAR1 0x14 150166676Sjkim#define BGE_PCI_SUBSYS 0x2C 151166676Sjkim#define BGE_PCI_SUBVID 0x2E 152166676Sjkim#define BGE_PCI_ROMBASE 0x30 153166676Sjkim#define BGE_PCI_CAPPTR 0x34 154166676Sjkim#define BGE_PCI_INTLINE 0x3C 155166676Sjkim#define BGE_PCI_INTPIN 0x3D 156166676Sjkim#define BGE_PCI_MINGNT 0x3E 157166676Sjkim#define BGE_PCI_MAXLAT 0x3F 158166676Sjkim#define BGE_PCI_PCIXCAP 0x40 159166676Sjkim#define BGE_PCI_NEXTPTR_PM 0x41 160166676Sjkim#define BGE_PCI_PCIX_CMD 0x42 161166676Sjkim#define BGE_PCI_PCIX_STS 0x44 162166676Sjkim#define BGE_PCI_PWRMGMT_CAPID 0x48 163166676Sjkim#define BGE_PCI_NEXTPTR_VPD 0x49 164166676Sjkim#define BGE_PCI_PWRMGMT_CAPS 0x4A 165166676Sjkim#define BGE_PCI_PWRMGMT_CMD 0x4C 166166676Sjkim#define BGE_PCI_PWRMGMT_STS 0x4D 167166676Sjkim#define BGE_PCI_PWRMGMT_DATA 0x4F 168166676Sjkim#define BGE_PCI_VPD_CAPID 0x50 169166676Sjkim#define BGE_PCI_NEXTPTR_MSI 0x51 170166676Sjkim#define BGE_PCI_VPD_ADDR 0x52 171166676Sjkim#define BGE_PCI_VPD_DATA 0x54 172166676Sjkim#define BGE_PCI_MSI_CAPID 0x58 173166676Sjkim#define BGE_PCI_NEXTPTR_NONE 0x59 174166676Sjkim#define BGE_PCI_MSI_CTL 0x5A 175166676Sjkim#define BGE_PCI_MSI_ADDR_HI 0x5C 176166676Sjkim#define BGE_PCI_MSI_ADDR_LO 0x60 177166676Sjkim#define BGE_PCI_MSI_DATA 0x64 17884059Swpaul 179190194Smarius/* 180190194Smarius * PCI Express definitions 181190194Smarius * According to 182190194Smarius * PCI Express base specification, REV. 1.0a 183190194Smarius */ 184190194Smarius 185190194Smarius/* PCI Express device control, 16bits */ 186190194Smarius#define BGE_PCIE_DEVCTL 0x08 187190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193190194Smarius#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194190194Smarius 195135772Sps/* PCI MSI. ??? */ 196166676Sjkim#define BGE_PCIE_CAPID_REG 0xD0 197166676Sjkim#define BGE_PCIE_CAPID 0x10 198135772Sps 19984059Swpaul/* 20084059Swpaul * PCI registers specific to the BCM570x family. 20184059Swpaul */ 202166676Sjkim#define BGE_PCI_MISC_CTL 0x68 203166676Sjkim#define BGE_PCI_DMA_RW_CTL 0x6C 204166676Sjkim#define BGE_PCI_PCISTATE 0x70 205166676Sjkim#define BGE_PCI_CLKCTL 0x74 206166676Sjkim#define BGE_PCI_REG_BASEADDR 0x78 207166676Sjkim#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208166676Sjkim#define BGE_PCI_REG_DATA 0x80 209166676Sjkim#define BGE_PCI_MEMWIN_DATA 0x84 210166676Sjkim#define BGE_PCI_MODECTL 0x88 211166676Sjkim#define BGE_PCI_MISC_CFG 0x8C 212166676Sjkim#define BGE_PCI_MISC_LOCALCTL 0x90 213166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219166676Sjkim#define BGE_PCI_ISR_MBX_HI 0xB0 220166676Sjkim#define BGE_PCI_ISR_MBX_LO 0xB4 221197832Sstas#define BGE_PCI_PRODID_ASICREV 0xBC 22284059Swpaul 22384059Swpaul/* PCI Misc. Host control register */ 224166676Sjkim#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 225166676Sjkim#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 226166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 227166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 228166676Sjkim#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 229166676Sjkim#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 230166676Sjkim#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 231166676Sjkim#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 232166676Sjkim#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 233197832Sstas#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 23484059Swpaul 235166676Sjkim#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 236153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 237166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 238153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME| \ 239153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 240153437Syongari#else 241166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 242153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 243153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 244153437Syongari#endif 24584059Swpaul 246166676Sjkim#define BGE_INIT \ 247153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 248153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 24984059Swpaul 250197832Sstas#define BGE_CHIPID_TIGON_I 0x4000 251197832Sstas#define BGE_CHIPID_TIGON_II 0x6000 252197832Sstas#define BGE_CHIPID_BCM5700_A0 0x7000 253197832Sstas#define BGE_CHIPID_BCM5700_A1 0x7001 254197832Sstas#define BGE_CHIPID_BCM5700_B0 0x7100 255197832Sstas#define BGE_CHIPID_BCM5700_B1 0x7101 256197832Sstas#define BGE_CHIPID_BCM5700_B2 0x7102 257197832Sstas#define BGE_CHIPID_BCM5700_B3 0x7103 258197832Sstas#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 259197832Sstas#define BGE_CHIPID_BCM5700_C0 0x7200 260197832Sstas#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 261197832Sstas#define BGE_CHIPID_BCM5701_B0 0x0100 262197832Sstas#define BGE_CHIPID_BCM5701_B2 0x0102 263197832Sstas#define BGE_CHIPID_BCM5701_B5 0x0105 264197832Sstas#define BGE_CHIPID_BCM5703_A0 0x1000 265197832Sstas#define BGE_CHIPID_BCM5703_A1 0x1001 266197832Sstas#define BGE_CHIPID_BCM5703_A2 0x1002 267197832Sstas#define BGE_CHIPID_BCM5703_A3 0x1003 268197832Sstas#define BGE_CHIPID_BCM5703_B0 0x1100 269197832Sstas#define BGE_CHIPID_BCM5704_A0 0x2000 270197832Sstas#define BGE_CHIPID_BCM5704_A1 0x2001 271197832Sstas#define BGE_CHIPID_BCM5704_A2 0x2002 272197832Sstas#define BGE_CHIPID_BCM5704_A3 0x2003 273197832Sstas#define BGE_CHIPID_BCM5704_B0 0x2100 274197832Sstas#define BGE_CHIPID_BCM5705_A0 0x3000 275197832Sstas#define BGE_CHIPID_BCM5705_A1 0x3001 276197832Sstas#define BGE_CHIPID_BCM5705_A2 0x3002 277197832Sstas#define BGE_CHIPID_BCM5705_A3 0x3003 278197832Sstas#define BGE_CHIPID_BCM5750_A0 0x4000 279197832Sstas#define BGE_CHIPID_BCM5750_A1 0x4001 280197832Sstas#define BGE_CHIPID_BCM5750_A3 0x4000 281197832Sstas#define BGE_CHIPID_BCM5750_B0 0x4100 282197832Sstas#define BGE_CHIPID_BCM5750_B1 0x4101 283197832Sstas#define BGE_CHIPID_BCM5750_C0 0x4200 284197832Sstas#define BGE_CHIPID_BCM5750_C1 0x4201 285197832Sstas#define BGE_CHIPID_BCM5750_C2 0x4202 286197832Sstas#define BGE_CHIPID_BCM5714_A0 0x5000 287197832Sstas#define BGE_CHIPID_BCM5752_A0 0x6000 288197832Sstas#define BGE_CHIPID_BCM5752_A1 0x6001 289197832Sstas#define BGE_CHIPID_BCM5752_A2 0x6002 290197832Sstas#define BGE_CHIPID_BCM5714_B0 0x8000 291197832Sstas#define BGE_CHIPID_BCM5714_B3 0x8003 292197832Sstas#define BGE_CHIPID_BCM5715_A0 0x9000 293197832Sstas#define BGE_CHIPID_BCM5715_A1 0x9001 294197832Sstas#define BGE_CHIPID_BCM5715_A3 0x9003 295197832Sstas#define BGE_CHIPID_BCM5755_A0 0xa000 296197832Sstas#define BGE_CHIPID_BCM5755_A1 0xa001 297197832Sstas#define BGE_CHIPID_BCM5755_A2 0xa002 298197832Sstas#define BGE_CHIPID_BCM5722_A0 0xa200 299197832Sstas#define BGE_CHIPID_BCM5754_A0 0xb000 300197832Sstas#define BGE_CHIPID_BCM5754_A1 0xb001 301197832Sstas#define BGE_CHIPID_BCM5754_A2 0xb002 302197832Sstas#define BGE_CHIPID_BCM5761_A0 0x5761000 303197832Sstas#define BGE_CHIPID_BCM5761_A1 0x5761100 304197832Sstas#define BGE_CHIPID_BCM5784_A0 0x5784000 305197832Sstas#define BGE_CHIPID_BCM5784_A1 0x5784100 306197832Sstas#define BGE_CHIPID_BCM5787_A0 0xb000 307197832Sstas#define BGE_CHIPID_BCM5787_A1 0xb001 308197832Sstas#define BGE_CHIPID_BCM5787_A2 0xb002 309197832Sstas#define BGE_CHIPID_BCM5906_A1 0xc001 310197832Sstas#define BGE_CHIPID_BCM5906_A2 0xc002 311197832Sstas#define BGE_CHIPID_BCM57780_A0 0x57780000 312197832Sstas#define BGE_CHIPID_BCM57780_A1 0x57780001 31384059Swpaul 31493751Swpaul/* shorthand one */ 315197832Sstas#define BGE_ASICREV(x) ((x) >> 12) 316166676Sjkim#define BGE_ASICREV_BCM5701 0x00 317166676Sjkim#define BGE_ASICREV_BCM5703 0x01 318166676Sjkim#define BGE_ASICREV_BCM5704 0x02 319166676Sjkim#define BGE_ASICREV_BCM5705 0x03 320166676Sjkim#define BGE_ASICREV_BCM5750 0x04 321166676Sjkim#define BGE_ASICREV_BCM5714_A0 0x05 322166676Sjkim#define BGE_ASICREV_BCM5752 0x06 323166676Sjkim#define BGE_ASICREV_BCM5700 0x07 324166676Sjkim#define BGE_ASICREV_BCM5780 0x08 325166676Sjkim#define BGE_ASICREV_BCM5714 0x09 326166676Sjkim#define BGE_ASICREV_BCM5755 0x0a 327166676Sjkim#define BGE_ASICREV_BCM5754 0x0b 328166676Sjkim#define BGE_ASICREV_BCM5787 0x0b 329178667Sjhb#define BGE_ASICREV_BCM5906 0x0c 330197832Sstas/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 331197832Sstas#define BGE_ASICREV_USE_PRODID_REG 0x0f 332197832Sstas/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 333197832Sstas#define BGE_ASICREV_BCM5761 0x5761 334197832Sstas#define BGE_ASICREV_BCM5784 0x5784 335197832Sstas#define BGE_ASICREV_BCM5785 0x5785 336197832Sstas#define BGE_ASICREV_BCM57780 0x57780 33793751Swpaul 338114813Sps/* chip revisions */ 339197832Sstas#define BGE_CHIPREV(x) ((x) >> 8) 340166676Sjkim#define BGE_CHIPREV_5700_AX 0x70 341166676Sjkim#define BGE_CHIPREV_5700_BX 0x71 342166676Sjkim#define BGE_CHIPREV_5700_CX 0x72 343166676Sjkim#define BGE_CHIPREV_5701_AX 0x00 344166676Sjkim#define BGE_CHIPREV_5703_AX 0x10 345166676Sjkim#define BGE_CHIPREV_5704_AX 0x20 346166676Sjkim#define BGE_CHIPREV_5704_BX 0x21 347166676Sjkim#define BGE_CHIPREV_5750_AX 0x40 348166676Sjkim#define BGE_CHIPREV_5750_BX 0x41 349197832Sstas/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 350197832Sstas#define BGE_CHIPREV_5761_AX 0x57611 351197832Sstas#define BGE_CHIPREV_5784_AX 0x57841 352114813Sps 35384059Swpaul/* PCI DMA Read/Write Control register */ 354166676Sjkim#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 355166676Sjkim#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 356166676Sjkim#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 357169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 358169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 359169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 360166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 361166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 362166676Sjkim#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 363166676Sjkim#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 364166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 365166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 36684059Swpaul 367166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 368166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 369166676Sjkim#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 370166676Sjkim#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 37184059Swpaul 372166676Sjkim#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 373166676Sjkim#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 374166676Sjkim#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 375166676Sjkim#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 376166676Sjkim#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 377166676Sjkim#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 378166676Sjkim#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 379166676Sjkim#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 38084059Swpaul 381166676Sjkim#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 382166676Sjkim#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 383166676Sjkim#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 384166676Sjkim#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 385166676Sjkim#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 386166676Sjkim#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 387166676Sjkim#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 388166676Sjkim#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 389166676Sjkim 39084059Swpaul/* 39184059Swpaul * PCI state register -- note, this register is read only 39284059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 39384059Swpaul * register is set. 39484059Swpaul */ 395166676Sjkim#define BGE_PCISTATE_FORCE_RESET 0x00000001 396166676Sjkim#define BGE_PCISTATE_INTR_STATE 0x00000002 397166676Sjkim#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 398166676Sjkim#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 399166676Sjkim#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 400166676Sjkim#define BGE_PCISTATE_WANT_EXPROM 0x00000020 401166676Sjkim#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 402166676Sjkim#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 403166676Sjkim#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 40484059Swpaul 40584059Swpaul/* 40684059Swpaul * PCI Clock Control register -- note, this register is read only 40784059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 40884059Swpaul * register is set. 40984059Swpaul */ 410166676Sjkim#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 411166676Sjkim#define BGE_PCICLOCKCTL_M66EN 0x00000080 412166676Sjkim#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 413166676Sjkim#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 414166676Sjkim#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 415166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 416166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 417166676Sjkim#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 418166676Sjkim#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 419166676Sjkim#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 42084059Swpaul 42184059Swpaul 42284059Swpaul#ifndef PCIM_CMD_MWIEN 423166676Sjkim#define PCIM_CMD_MWIEN 0x0010 42484059Swpaul#endif 425190319Smarius#ifndef PCIM_CMD_INTxDIS 426190319Smarius#define PCIM_CMD_INTxDIS 0x0400 427190319Smarius#endif 42884059Swpaul 42984059Swpaul/* 43084059Swpaul * High priority mailbox registers 43184059Swpaul * Each mailbox is 64-bits wide, though we only use the 43284059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 43384059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 43484059Swpaul * has been updated. 43584059Swpaul */ 436166676Sjkim#define BGE_MBX_IRQ0_HI 0x0200 437166676Sjkim#define BGE_MBX_IRQ0_LO 0x0204 438166676Sjkim#define BGE_MBX_IRQ1_HI 0x0208 439166676Sjkim#define BGE_MBX_IRQ1_LO 0x020C 440166676Sjkim#define BGE_MBX_IRQ2_HI 0x0210 441166676Sjkim#define BGE_MBX_IRQ2_LO 0x0214 442166676Sjkim#define BGE_MBX_IRQ3_HI 0x0218 443166676Sjkim#define BGE_MBX_IRQ3_LO 0x021C 444166676Sjkim#define BGE_MBX_GEN0_HI 0x0220 445166676Sjkim#define BGE_MBX_GEN0_LO 0x0224 446166676Sjkim#define BGE_MBX_GEN1_HI 0x0228 447166676Sjkim#define BGE_MBX_GEN1_LO 0x022C 448166676Sjkim#define BGE_MBX_GEN2_HI 0x0230 449166676Sjkim#define BGE_MBX_GEN2_LO 0x0234 450166676Sjkim#define BGE_MBX_GEN3_HI 0x0228 451166676Sjkim#define BGE_MBX_GEN3_LO 0x022C 452166676Sjkim#define BGE_MBX_GEN4_HI 0x0240 453166676Sjkim#define BGE_MBX_GEN4_LO 0x0244 454166676Sjkim#define BGE_MBX_GEN5_HI 0x0248 455166676Sjkim#define BGE_MBX_GEN5_LO 0x024C 456166676Sjkim#define BGE_MBX_GEN6_HI 0x0250 457166676Sjkim#define BGE_MBX_GEN6_LO 0x0254 458166676Sjkim#define BGE_MBX_GEN7_HI 0x0258 459166676Sjkim#define BGE_MBX_GEN7_LO 0x025C 460166676Sjkim#define BGE_MBX_RELOAD_STATS_HI 0x0260 461166676Sjkim#define BGE_MBX_RELOAD_STATS_LO 0x0264 462166676Sjkim#define BGE_MBX_RX_STD_PROD_HI 0x0268 463166676Sjkim#define BGE_MBX_RX_STD_PROD_LO 0x026C 464166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 465166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 466166676Sjkim#define BGE_MBX_RX_MINI_PROD_HI 0x0278 467166676Sjkim#define BGE_MBX_RX_MINI_PROD_LO 0x027C 468166676Sjkim#define BGE_MBX_RX_CONS0_HI 0x0280 469166676Sjkim#define BGE_MBX_RX_CONS0_LO 0x0284 470166676Sjkim#define BGE_MBX_RX_CONS1_HI 0x0288 471166676Sjkim#define BGE_MBX_RX_CONS1_LO 0x028C 472166676Sjkim#define BGE_MBX_RX_CONS2_HI 0x0290 473166676Sjkim#define BGE_MBX_RX_CONS2_LO 0x0294 474166676Sjkim#define BGE_MBX_RX_CONS3_HI 0x0298 475166676Sjkim#define BGE_MBX_RX_CONS3_LO 0x029C 476166676Sjkim#define BGE_MBX_RX_CONS4_HI 0x02A0 477166676Sjkim#define BGE_MBX_RX_CONS4_LO 0x02A4 478166676Sjkim#define BGE_MBX_RX_CONS5_HI 0x02A8 479166676Sjkim#define BGE_MBX_RX_CONS5_LO 0x02AC 480166676Sjkim#define BGE_MBX_RX_CONS6_HI 0x02B0 481166676Sjkim#define BGE_MBX_RX_CONS6_LO 0x02B4 482166676Sjkim#define BGE_MBX_RX_CONS7_HI 0x02B8 483166676Sjkim#define BGE_MBX_RX_CONS7_LO 0x02BC 484166676Sjkim#define BGE_MBX_RX_CONS8_HI 0x02C0 485166676Sjkim#define BGE_MBX_RX_CONS8_LO 0x02C4 486166676Sjkim#define BGE_MBX_RX_CONS9_HI 0x02C8 487166676Sjkim#define BGE_MBX_RX_CONS9_LO 0x02CC 488166676Sjkim#define BGE_MBX_RX_CONS10_HI 0x02D0 489166676Sjkim#define BGE_MBX_RX_CONS10_LO 0x02D4 490166676Sjkim#define BGE_MBX_RX_CONS11_HI 0x02D8 491166676Sjkim#define BGE_MBX_RX_CONS11_LO 0x02DC 492166676Sjkim#define BGE_MBX_RX_CONS12_HI 0x02E0 493166676Sjkim#define BGE_MBX_RX_CONS12_LO 0x02E4 494166676Sjkim#define BGE_MBX_RX_CONS13_HI 0x02E8 495166676Sjkim#define BGE_MBX_RX_CONS13_LO 0x02EC 496166676Sjkim#define BGE_MBX_RX_CONS14_HI 0x02F0 497166676Sjkim#define BGE_MBX_RX_CONS14_LO 0x02F4 498166676Sjkim#define BGE_MBX_RX_CONS15_HI 0x02F8 499166676Sjkim#define BGE_MBX_RX_CONS15_LO 0x02FC 500166676Sjkim#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 501166676Sjkim#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 502166676Sjkim#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 503166676Sjkim#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 504166676Sjkim#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 505166676Sjkim#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 506166676Sjkim#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 507166676Sjkim#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 508166676Sjkim#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 509166676Sjkim#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 510166676Sjkim#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 511166676Sjkim#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 512166676Sjkim#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 513166676Sjkim#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 514166676Sjkim#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 515166676Sjkim#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 516166676Sjkim#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 517166676Sjkim#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 518166676Sjkim#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 519166676Sjkim#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 520166676Sjkim#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 521166676Sjkim#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 522166676Sjkim#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 523166676Sjkim#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 524166676Sjkim#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 525166676Sjkim#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 526166676Sjkim#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 527166676Sjkim#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 528166676Sjkim#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 529166676Sjkim#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 530166676Sjkim#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 531166676Sjkim#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 532166676Sjkim#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 533166676Sjkim#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 534166676Sjkim#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 535166676Sjkim#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 536166676Sjkim#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 537166676Sjkim#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 538166676Sjkim#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 539166676Sjkim#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 540166676Sjkim#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 541166676Sjkim#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 542166676Sjkim#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 543166676Sjkim#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 544166676Sjkim#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 545166676Sjkim#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 546166676Sjkim#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 547166676Sjkim#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 548166676Sjkim#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 549166676Sjkim#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 550166676Sjkim#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 551166676Sjkim#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 552166676Sjkim#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 553166676Sjkim#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 554166676Sjkim#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 555166676Sjkim#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 556166676Sjkim#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 557166676Sjkim#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 558166676Sjkim#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 559166676Sjkim#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 560166676Sjkim#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 561166676Sjkim#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 562166676Sjkim#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 563166676Sjkim#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 56484059Swpaul 565166676Sjkim#define BGE_TX_RINGS_MAX 4 566166676Sjkim#define BGE_TX_RINGS_EXTSSRAM_MAX 16 567166676Sjkim#define BGE_RX_RINGS_MAX 16 56884059Swpaul 56984059Swpaul/* Ethernet MAC control registers */ 570166676Sjkim#define BGE_MAC_MODE 0x0400 571166676Sjkim#define BGE_MAC_STS 0x0404 572166676Sjkim#define BGE_MAC_EVT_ENB 0x0408 573166676Sjkim#define BGE_MAC_LED_CTL 0x040C 574166676Sjkim#define BGE_MAC_ADDR1_LO 0x0410 575166676Sjkim#define BGE_MAC_ADDR1_HI 0x0414 576166676Sjkim#define BGE_MAC_ADDR2_LO 0x0418 577166676Sjkim#define BGE_MAC_ADDR2_HI 0x041C 578166676Sjkim#define BGE_MAC_ADDR3_LO 0x0420 579166676Sjkim#define BGE_MAC_ADDR3_HI 0x0424 580166676Sjkim#define BGE_MAC_ADDR4_LO 0x0428 581166676Sjkim#define BGE_MAC_ADDR4_HI 0x042C 582166676Sjkim#define BGE_WOL_PATPTR 0x0430 583166676Sjkim#define BGE_WOL_PATCFG 0x0434 584166676Sjkim#define BGE_TX_RANDOM_BACKOFF 0x0438 585166676Sjkim#define BGE_RX_MTU 0x043C 586166676Sjkim#define BGE_GBIT_PCS_TEST 0x0440 587166676Sjkim#define BGE_TX_TBI_AUTONEG 0x0444 588166676Sjkim#define BGE_RX_TBI_AUTONEG 0x0448 589166676Sjkim#define BGE_MI_COMM 0x044C 590166676Sjkim#define BGE_MI_STS 0x0450 591166676Sjkim#define BGE_MI_MODE 0x0454 592166676Sjkim#define BGE_AUTOPOLL_STS 0x0458 593166676Sjkim#define BGE_TX_MODE 0x045C 594166676Sjkim#define BGE_TX_STS 0x0460 595166676Sjkim#define BGE_TX_LENGTHS 0x0464 596166676Sjkim#define BGE_RX_MODE 0x0468 597166676Sjkim#define BGE_RX_STS 0x046C 598166676Sjkim#define BGE_MAR0 0x0470 599166676Sjkim#define BGE_MAR1 0x0474 600166676Sjkim#define BGE_MAR2 0x0478 601166676Sjkim#define BGE_MAR3 0x047C 602166676Sjkim#define BGE_RX_BD_RULES_CTL0 0x0480 603166676Sjkim#define BGE_RX_BD_RULES_MASKVAL0 0x0484 604166676Sjkim#define BGE_RX_BD_RULES_CTL1 0x0488 605166676Sjkim#define BGE_RX_BD_RULES_MASKVAL1 0x048C 606166676Sjkim#define BGE_RX_BD_RULES_CTL2 0x0490 607166676Sjkim#define BGE_RX_BD_RULES_MASKVAL2 0x0494 608166676Sjkim#define BGE_RX_BD_RULES_CTL3 0x0498 609166676Sjkim#define BGE_RX_BD_RULES_MASKVAL3 0x049C 610166676Sjkim#define BGE_RX_BD_RULES_CTL4 0x04A0 611166676Sjkim#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 612166676Sjkim#define BGE_RX_BD_RULES_CTL5 0x04A8 613166676Sjkim#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 614166676Sjkim#define BGE_RX_BD_RULES_CTL6 0x04B0 615166676Sjkim#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 616166676Sjkim#define BGE_RX_BD_RULES_CTL7 0x04B8 617166676Sjkim#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 618166676Sjkim#define BGE_RX_BD_RULES_CTL8 0x04C0 619166676Sjkim#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 620166676Sjkim#define BGE_RX_BD_RULES_CTL9 0x04C8 621166676Sjkim#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 622166676Sjkim#define BGE_RX_BD_RULES_CTL10 0x04D0 623166676Sjkim#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 624166676Sjkim#define BGE_RX_BD_RULES_CTL11 0x04D8 625166676Sjkim#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 626166676Sjkim#define BGE_RX_BD_RULES_CTL12 0x04E0 627166676Sjkim#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 628166676Sjkim#define BGE_RX_BD_RULES_CTL13 0x04E8 629166676Sjkim#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 630166676Sjkim#define BGE_RX_BD_RULES_CTL14 0x04F0 631166676Sjkim#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 632166676Sjkim#define BGE_RX_BD_RULES_CTL15 0x04F8 633166676Sjkim#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 634166676Sjkim#define BGE_RX_RULES_CFG 0x0500 635166676Sjkim#define BGE_SERDES_CFG 0x0590 636166676Sjkim#define BGE_SERDES_STS 0x0594 637166676Sjkim#define BGE_SGDIG_CFG 0x05B0 638166676Sjkim#define BGE_SGDIG_STS 0x05B4 639166676Sjkim#define BGE_MAC_STATS 0x0800 64084059Swpaul 64184059Swpaul/* Ethernet MAC Mode register */ 642166676Sjkim#define BGE_MACMODE_RESET 0x00000001 643166676Sjkim#define BGE_MACMODE_HALF_DUPLEX 0x00000002 644166676Sjkim#define BGE_MACMODE_PORTMODE 0x0000000C 645166676Sjkim#define BGE_MACMODE_LOOPBACK 0x00000010 646166676Sjkim#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 647166676Sjkim#define BGE_MACMODE_TX_BURST_ENB 0x00000100 648166676Sjkim#define BGE_MACMODE_MAX_DEFER 0x00000200 649166676Sjkim#define BGE_MACMODE_LINK_POLARITY 0x00000400 650166676Sjkim#define BGE_MACMODE_RX_STATS_ENB 0x00000800 651166676Sjkim#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 652166676Sjkim#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 653166676Sjkim#define BGE_MACMODE_TX_STATS_ENB 0x00004000 654166676Sjkim#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 655166676Sjkim#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 656166676Sjkim#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 657166676Sjkim#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 658166676Sjkim#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 659166676Sjkim#define BGE_MACMODE_MIP_ENB 0x00100000 660166676Sjkim#define BGE_MACMODE_TXDMA_ENB 0x00200000 661166676Sjkim#define BGE_MACMODE_RXDMA_ENB 0x00400000 662166676Sjkim#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 66384059Swpaul 664166676Sjkim#define BGE_PORTMODE_NONE 0x00000000 665166676Sjkim#define BGE_PORTMODE_MII 0x00000004 666166676Sjkim#define BGE_PORTMODE_GMII 0x00000008 667166676Sjkim#define BGE_PORTMODE_TBI 0x0000000C 66884059Swpaul 66984059Swpaul/* MAC Status register */ 670166676Sjkim#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 671166676Sjkim#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 672166676Sjkim#define BGE_MACSTAT_RX_CFG 0x00000004 673166676Sjkim#define BGE_MACSTAT_CFG_CHANGED 0x00000008 674166676Sjkim#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 675166676Sjkim#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 676166676Sjkim#define BGE_MACSTAT_LINK_CHANGED 0x00001000 677166676Sjkim#define BGE_MACSTAT_MI_COMPLETE 0x00400000 678166676Sjkim#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 679166676Sjkim#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 680166676Sjkim#define BGE_MACSTAT_ODI_ERROR 0x02000000 681166676Sjkim#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 682166676Sjkim#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 68384059Swpaul 68484059Swpaul/* MAC Event Enable Register */ 685166676Sjkim#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 686166676Sjkim#define BGE_EVTENB_LINK_CHANGED 0x00001000 687166676Sjkim#define BGE_EVTENB_MI_COMPLETE 0x00400000 688166676Sjkim#define BGE_EVTENB_MI_INTERRUPT 0x00800000 689166676Sjkim#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 690166676Sjkim#define BGE_EVTENB_ODI_ERROR 0x02000000 691166676Sjkim#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 692166676Sjkim#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 69384059Swpaul 69484059Swpaul/* LED Control Register */ 695166676Sjkim#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 696166676Sjkim#define BGE_LEDCTL_1000MBPS_LED 0x00000002 697166676Sjkim#define BGE_LEDCTL_100MBPS_LED 0x00000004 698166676Sjkim#define BGE_LEDCTL_10MBPS_LED 0x00000008 699166676Sjkim#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 700166676Sjkim#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 701166676Sjkim#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 702166676Sjkim#define BGE_LEDCTL_1000MBPS_STS 0x00000080 703166676Sjkim#define BGE_LEDCTL_100MBPS_STS 0x00000100 704166676Sjkim#define BGE_LEDCTL_10MBPS_STS 0x00000200 705166676Sjkim#define BGE_LEDCTL_TRADLED_STS 0x00000400 706166676Sjkim#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 707166676Sjkim#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 70884059Swpaul 70984059Swpaul/* TX backoff seed register */ 710166676Sjkim#define BGE_TX_BACKOFF_SEED_MASK 0x3F 71184059Swpaul 71284059Swpaul/* Autopoll status register */ 713166676Sjkim#define BGE_AUTOPOLLSTS_ERROR 0x00000001 71484059Swpaul 71584059Swpaul/* Transmit MAC mode register */ 716166676Sjkim#define BGE_TXMODE_RESET 0x00000001 717166676Sjkim#define BGE_TXMODE_ENABLE 0x00000002 718166676Sjkim#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 719166676Sjkim#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 720166676Sjkim#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 72184059Swpaul 72284059Swpaul/* Transmit MAC status register */ 723166676Sjkim#define BGE_TXSTAT_RX_XOFFED 0x00000001 724166676Sjkim#define BGE_TXSTAT_SENT_XOFF 0x00000002 725166676Sjkim#define BGE_TXSTAT_SENT_XON 0x00000004 726166676Sjkim#define BGE_TXSTAT_LINK_UP 0x00000008 727166676Sjkim#define BGE_TXSTAT_ODI_UFLOW 0x00000010 728166676Sjkim#define BGE_TXSTAT_ODI_OFLOW 0x00000020 72984059Swpaul 73084059Swpaul/* Transmit MAC lengths register */ 731166676Sjkim#define BGE_TXLEN_SLOTTIME 0x000000FF 732166676Sjkim#define BGE_TXLEN_IPG 0x00000F00 733166676Sjkim#define BGE_TXLEN_CRS 0x00003000 73484059Swpaul 73584059Swpaul/* Receive MAC mode register */ 736166676Sjkim#define BGE_RXMODE_RESET 0x00000001 737166676Sjkim#define BGE_RXMODE_ENABLE 0x00000002 738166676Sjkim#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 739166676Sjkim#define BGE_RXMODE_RX_GIANTS 0x00000020 740166676Sjkim#define BGE_RXMODE_RX_RUNTS 0x00000040 741166676Sjkim#define BGE_RXMODE_8022_LENCHECK 0x00000080 742166676Sjkim#define BGE_RXMODE_RX_PROMISC 0x00000100 743166676Sjkim#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 744166676Sjkim#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 74584059Swpaul 74684059Swpaul/* Receive MAC status register */ 747166676Sjkim#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 748166676Sjkim#define BGE_RXSTAT_RCVD_XOFF 0x00000002 749166676Sjkim#define BGE_RXSTAT_RCVD_XON 0x00000004 75084059Swpaul 75184059Swpaul/* Receive Rules Control register */ 752166676Sjkim#define BGE_RXRULECTL_OFFSET 0x000000FF 753166676Sjkim#define BGE_RXRULECTL_CLASS 0x00001F00 754166676Sjkim#define BGE_RXRULECTL_HDRTYPE 0x0000E000 755166676Sjkim#define BGE_RXRULECTL_COMPARE_OP 0x00030000 756166676Sjkim#define BGE_RXRULECTL_MAP 0x01000000 757166676Sjkim#define BGE_RXRULECTL_DISCARD 0x02000000 758166676Sjkim#define BGE_RXRULECTL_MASK 0x04000000 759166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 760166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 761166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 762166676Sjkim#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 76384059Swpaul 76484059Swpaul/* Receive Rules Mask register */ 765166676Sjkim#define BGE_RXRULEMASK_VALUE 0x0000FFFF 766166676Sjkim#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 76784059Swpaul 768130273Swpaul/* SERDES configuration register */ 769166676Sjkim#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 770166676Sjkim#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 771166676Sjkim#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 772166676Sjkim#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 773166676Sjkim#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 774166676Sjkim#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 775166676Sjkim#define BGE_SERDESCFG_TXMODE 0x00001000 776166676Sjkim#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 777166676Sjkim#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 778166676Sjkim#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 779166676Sjkim#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 780166676Sjkim#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 781166676Sjkim#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 782166676Sjkim#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 783166676Sjkim#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 784166676Sjkim#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 785130273Swpaul 786130273Swpaul/* SERDES status register */ 787166676Sjkim#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 788166676Sjkim#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 789130273Swpaul 790130273Swpaul/* SGDIG config (not documented) */ 791166676Sjkim#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 792166676Sjkim#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 793166676Sjkim#define BGE_SGDIGCFG_SEND 0x40000000 794166676Sjkim#define BGE_SGDIGCFG_AUTO 0x80000000 795130273Swpaul 796130273Swpaul/* SGDIG status (not documented) */ 797166676Sjkim#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 798166676Sjkim#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 799166676Sjkim#define BGE_SGDIGSTS_DONE 0x00000002 800130273Swpaul 801130273Swpaul 80284059Swpaul/* MI communication register */ 803166676Sjkim#define BGE_MICOMM_DATA 0x0000FFFF 804166676Sjkim#define BGE_MICOMM_REG 0x001F0000 805166676Sjkim#define BGE_MICOMM_PHY 0x03E00000 806166676Sjkim#define BGE_MICOMM_CMD 0x0C000000 807166676Sjkim#define BGE_MICOMM_READFAIL 0x10000000 808166676Sjkim#define BGE_MICOMM_BUSY 0x20000000 80984059Swpaul 810166676Sjkim#define BGE_MIREG(x) ((x & 0x1F) << 16) 811166676Sjkim#define BGE_MIPHY(x) ((x & 0x1F) << 21) 812166676Sjkim#define BGE_MICMD_WRITE 0x04000000 813166676Sjkim#define BGE_MICMD_READ 0x08000000 81484059Swpaul 81584059Swpaul/* MI status register */ 816166676Sjkim#define BGE_MISTS_LINK 0x00000001 817166676Sjkim#define BGE_MISTS_10MBPS 0x00000002 81884059Swpaul 819166676Sjkim#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 820166676Sjkim#define BGE_MIMODE_AUTOPOLL 0x00000010 821166676Sjkim#define BGE_MIMODE_CLKCNT 0x001F0000 82284059Swpaul 82384059Swpaul 82484059Swpaul/* 82584059Swpaul * Send data initiator control registers. 82684059Swpaul */ 827166676Sjkim#define BGE_SDI_MODE 0x0C00 828166676Sjkim#define BGE_SDI_STATUS 0x0C04 829166676Sjkim#define BGE_SDI_STATS_CTL 0x0C08 830166676Sjkim#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 831166676Sjkim#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 832166676Sjkim#define BGE_LOCSTATS_COS0 0x0C80 833166676Sjkim#define BGE_LOCSTATS_COS1 0x0C84 834166676Sjkim#define BGE_LOCSTATS_COS2 0x0C88 835166676Sjkim#define BGE_LOCSTATS_COS3 0x0C8C 836166676Sjkim#define BGE_LOCSTATS_COS4 0x0C90 837166676Sjkim#define BGE_LOCSTATS_COS5 0x0C84 838166676Sjkim#define BGE_LOCSTATS_COS6 0x0C98 839166676Sjkim#define BGE_LOCSTATS_COS7 0x0C9C 840166676Sjkim#define BGE_LOCSTATS_COS8 0x0CA0 841166676Sjkim#define BGE_LOCSTATS_COS9 0x0CA4 842166676Sjkim#define BGE_LOCSTATS_COS10 0x0CA8 843166676Sjkim#define BGE_LOCSTATS_COS11 0x0CAC 844166676Sjkim#define BGE_LOCSTATS_COS12 0x0CB0 845166676Sjkim#define BGE_LOCSTATS_COS13 0x0CB4 846166676Sjkim#define BGE_LOCSTATS_COS14 0x0CB8 847166676Sjkim#define BGE_LOCSTATS_COS15 0x0CBC 848166676Sjkim#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 849166676Sjkim#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 850166676Sjkim#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 851166676Sjkim#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 852166676Sjkim#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 853166676Sjkim#define BGE_LOCSTATS_IRQS 0x0CD4 854166676Sjkim#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 855166676Sjkim#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 85684059Swpaul 85784059Swpaul/* Send Data Initiator mode register */ 858166676Sjkim#define BGE_SDIMODE_RESET 0x00000001 859166676Sjkim#define BGE_SDIMODE_ENABLE 0x00000002 860166676Sjkim#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 86184059Swpaul 86284059Swpaul/* Send Data Initiator stats register */ 863166676Sjkim#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 86484059Swpaul 86584059Swpaul/* Send Data Initiator stats control register */ 866166676Sjkim#define BGE_SDISTATSCTL_ENABLE 0x00000001 867166676Sjkim#define BGE_SDISTATSCTL_FASTER 0x00000002 868166676Sjkim#define BGE_SDISTATSCTL_CLEAR 0x00000004 869166676Sjkim#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 870166676Sjkim#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 87184059Swpaul 87284059Swpaul/* 87384059Swpaul * Send Data Completion Control registers 87484059Swpaul */ 875166676Sjkim#define BGE_SDC_MODE 0x1000 876166676Sjkim#define BGE_SDC_STATUS 0x1004 87784059Swpaul 87884059Swpaul/* Send Data completion mode register */ 879166676Sjkim#define BGE_SDCMODE_RESET 0x00000001 880166676Sjkim#define BGE_SDCMODE_ENABLE 0x00000002 881166676Sjkim#define BGE_SDCMODE_ATTN 0x00000004 882197832Sstas#define BGE_SDCMODE_CDELAY 0x00000010 88384059Swpaul 88484059Swpaul/* Send Data completion status register */ 885166676Sjkim#define BGE_SDCSTAT_ATTN 0x00000004 88684059Swpaul 88784059Swpaul/* 88884059Swpaul * Send BD Ring Selector Control registers 88984059Swpaul */ 890166676Sjkim#define BGE_SRS_MODE 0x1400 891166676Sjkim#define BGE_SRS_STATUS 0x1404 892166676Sjkim#define BGE_SRS_HWDIAG 0x1408 893166676Sjkim#define BGE_SRS_LOC_NIC_CONS0 0x1440 894166676Sjkim#define BGE_SRS_LOC_NIC_CONS1 0x1444 895166676Sjkim#define BGE_SRS_LOC_NIC_CONS2 0x1448 896166676Sjkim#define BGE_SRS_LOC_NIC_CONS3 0x144C 897166676Sjkim#define BGE_SRS_LOC_NIC_CONS4 0x1450 898166676Sjkim#define BGE_SRS_LOC_NIC_CONS5 0x1454 899166676Sjkim#define BGE_SRS_LOC_NIC_CONS6 0x1458 900166676Sjkim#define BGE_SRS_LOC_NIC_CONS7 0x145C 901166676Sjkim#define BGE_SRS_LOC_NIC_CONS8 0x1460 902166676Sjkim#define BGE_SRS_LOC_NIC_CONS9 0x1464 903166676Sjkim#define BGE_SRS_LOC_NIC_CONS10 0x1468 904166676Sjkim#define BGE_SRS_LOC_NIC_CONS11 0x146C 905166676Sjkim#define BGE_SRS_LOC_NIC_CONS12 0x1470 906166676Sjkim#define BGE_SRS_LOC_NIC_CONS13 0x1474 907166676Sjkim#define BGE_SRS_LOC_NIC_CONS14 0x1478 908166676Sjkim#define BGE_SRS_LOC_NIC_CONS15 0x147C 90984059Swpaul 91084059Swpaul/* Send BD Ring Selector Mode register */ 911166676Sjkim#define BGE_SRSMODE_RESET 0x00000001 912166676Sjkim#define BGE_SRSMODE_ENABLE 0x00000002 913166676Sjkim#define BGE_SRSMODE_ATTN 0x00000004 91484059Swpaul 91584059Swpaul/* Send BD Ring Selector Status register */ 916166676Sjkim#define BGE_SRSSTAT_ERROR 0x00000004 91784059Swpaul 91884059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 919166676Sjkim#define BGE_SRSHWDIAG_STATE 0x0000000F 920166676Sjkim#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 921166676Sjkim#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 922166676Sjkim#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 92384059Swpaul 92484059Swpaul/* 92584059Swpaul * Send BD Initiator Selector Control registers 92684059Swpaul */ 927166676Sjkim#define BGE_SBDI_MODE 0x1800 928166676Sjkim#define BGE_SBDI_STATUS 0x1804 929166676Sjkim#define BGE_SBDI_LOC_NIC_PROD0 0x1808 930166676Sjkim#define BGE_SBDI_LOC_NIC_PROD1 0x180C 931166676Sjkim#define BGE_SBDI_LOC_NIC_PROD2 0x1810 932166676Sjkim#define BGE_SBDI_LOC_NIC_PROD3 0x1814 933166676Sjkim#define BGE_SBDI_LOC_NIC_PROD4 0x1818 934166676Sjkim#define BGE_SBDI_LOC_NIC_PROD5 0x181C 935166676Sjkim#define BGE_SBDI_LOC_NIC_PROD6 0x1820 936166676Sjkim#define BGE_SBDI_LOC_NIC_PROD7 0x1824 937166676Sjkim#define BGE_SBDI_LOC_NIC_PROD8 0x1828 938166676Sjkim#define BGE_SBDI_LOC_NIC_PROD9 0x182C 939166676Sjkim#define BGE_SBDI_LOC_NIC_PROD10 0x1830 940166676Sjkim#define BGE_SBDI_LOC_NIC_PROD11 0x1834 941166676Sjkim#define BGE_SBDI_LOC_NIC_PROD12 0x1838 942166676Sjkim#define BGE_SBDI_LOC_NIC_PROD13 0x183C 943166676Sjkim#define BGE_SBDI_LOC_NIC_PROD14 0x1840 944166676Sjkim#define BGE_SBDI_LOC_NIC_PROD15 0x1844 94584059Swpaul 94684059Swpaul/* Send BD Initiator Mode register */ 947166676Sjkim#define BGE_SBDIMODE_RESET 0x00000001 948166676Sjkim#define BGE_SBDIMODE_ENABLE 0x00000002 949166676Sjkim#define BGE_SBDIMODE_ATTN 0x00000004 95084059Swpaul 95184059Swpaul/* Send BD Initiator Status register */ 952166676Sjkim#define BGE_SBDISTAT_ERROR 0x00000004 95384059Swpaul 95484059Swpaul/* 95584059Swpaul * Send BD Completion Control registers 95684059Swpaul */ 957166676Sjkim#define BGE_SBDC_MODE 0x1C00 958166676Sjkim#define BGE_SBDC_STATUS 0x1C04 95984059Swpaul 96084059Swpaul/* Send BD Completion Control Mode register */ 961166676Sjkim#define BGE_SBDCMODE_RESET 0x00000001 962166676Sjkim#define BGE_SBDCMODE_ENABLE 0x00000002 963166676Sjkim#define BGE_SBDCMODE_ATTN 0x00000004 96484059Swpaul 96584059Swpaul/* Send BD Completion Control Status register */ 966166676Sjkim#define BGE_SBDCSTAT_ATTN 0x00000004 96784059Swpaul 96884059Swpaul/* 96984059Swpaul * Receive List Placement Control registers 97084059Swpaul */ 971166676Sjkim#define BGE_RXLP_MODE 0x2000 972166676Sjkim#define BGE_RXLP_STATUS 0x2004 973166676Sjkim#define BGE_RXLP_SEL_LIST_LOCK 0x2008 974166676Sjkim#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 975166676Sjkim#define BGE_RXLP_CFG 0x2010 976166676Sjkim#define BGE_RXLP_STATS_CTL 0x2014 977166676Sjkim#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 978166676Sjkim#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 979166676Sjkim#define BGE_RXLP_HEAD0 0x2100 980166676Sjkim#define BGE_RXLP_TAIL0 0x2104 981166676Sjkim#define BGE_RXLP_COUNT0 0x2108 982166676Sjkim#define BGE_RXLP_HEAD1 0x2110 983166676Sjkim#define BGE_RXLP_TAIL1 0x2114 984166676Sjkim#define BGE_RXLP_COUNT1 0x2118 985166676Sjkim#define BGE_RXLP_HEAD2 0x2120 986166676Sjkim#define BGE_RXLP_TAIL2 0x2124 987166676Sjkim#define BGE_RXLP_COUNT2 0x2128 988166676Sjkim#define BGE_RXLP_HEAD3 0x2130 989166676Sjkim#define BGE_RXLP_TAIL3 0x2134 990166676Sjkim#define BGE_RXLP_COUNT3 0x2138 991166676Sjkim#define BGE_RXLP_HEAD4 0x2140 992166676Sjkim#define BGE_RXLP_TAIL4 0x2144 993166676Sjkim#define BGE_RXLP_COUNT4 0x2148 994166676Sjkim#define BGE_RXLP_HEAD5 0x2150 995166676Sjkim#define BGE_RXLP_TAIL5 0x2154 996166676Sjkim#define BGE_RXLP_COUNT5 0x2158 997166676Sjkim#define BGE_RXLP_HEAD6 0x2160 998166676Sjkim#define BGE_RXLP_TAIL6 0x2164 999166676Sjkim#define BGE_RXLP_COUNT6 0x2168 1000166676Sjkim#define BGE_RXLP_HEAD7 0x2170 1001166676Sjkim#define BGE_RXLP_TAIL7 0x2174 1002166676Sjkim#define BGE_RXLP_COUNT7 0x2178 1003166676Sjkim#define BGE_RXLP_HEAD8 0x2180 1004166676Sjkim#define BGE_RXLP_TAIL8 0x2184 1005166676Sjkim#define BGE_RXLP_COUNT8 0x2188 1006166676Sjkim#define BGE_RXLP_HEAD9 0x2190 1007166676Sjkim#define BGE_RXLP_TAIL9 0x2194 1008166676Sjkim#define BGE_RXLP_COUNT9 0x2198 1009166676Sjkim#define BGE_RXLP_HEAD10 0x21A0 1010166676Sjkim#define BGE_RXLP_TAIL10 0x21A4 1011166676Sjkim#define BGE_RXLP_COUNT10 0x21A8 1012166676Sjkim#define BGE_RXLP_HEAD11 0x21B0 1013166676Sjkim#define BGE_RXLP_TAIL11 0x21B4 1014166676Sjkim#define BGE_RXLP_COUNT11 0x21B8 1015166676Sjkim#define BGE_RXLP_HEAD12 0x21C0 1016166676Sjkim#define BGE_RXLP_TAIL12 0x21C4 1017166676Sjkim#define BGE_RXLP_COUNT12 0x21C8 1018166676Sjkim#define BGE_RXLP_HEAD13 0x21D0 1019166676Sjkim#define BGE_RXLP_TAIL13 0x21D4 1020166676Sjkim#define BGE_RXLP_COUNT13 0x21D8 1021166676Sjkim#define BGE_RXLP_HEAD14 0x21E0 1022166676Sjkim#define BGE_RXLP_TAIL14 0x21E4 1023166676Sjkim#define BGE_RXLP_COUNT14 0x21E8 1024166676Sjkim#define BGE_RXLP_HEAD15 0x21F0 1025166676Sjkim#define BGE_RXLP_TAIL15 0x21F4 1026166676Sjkim#define BGE_RXLP_COUNT15 0x21F8 1027166676Sjkim#define BGE_RXLP_LOCSTAT_COS0 0x2200 1028166676Sjkim#define BGE_RXLP_LOCSTAT_COS1 0x2204 1029166676Sjkim#define BGE_RXLP_LOCSTAT_COS2 0x2208 1030166676Sjkim#define BGE_RXLP_LOCSTAT_COS3 0x220C 1031166676Sjkim#define BGE_RXLP_LOCSTAT_COS4 0x2210 1032166676Sjkim#define BGE_RXLP_LOCSTAT_COS5 0x2214 1033166676Sjkim#define BGE_RXLP_LOCSTAT_COS6 0x2218 1034166676Sjkim#define BGE_RXLP_LOCSTAT_COS7 0x221C 1035166676Sjkim#define BGE_RXLP_LOCSTAT_COS8 0x2220 1036166676Sjkim#define BGE_RXLP_LOCSTAT_COS9 0x2224 1037166676Sjkim#define BGE_RXLP_LOCSTAT_COS10 0x2228 1038166676Sjkim#define BGE_RXLP_LOCSTAT_COS11 0x222C 1039166676Sjkim#define BGE_RXLP_LOCSTAT_COS12 0x2230 1040166676Sjkim#define BGE_RXLP_LOCSTAT_COS13 0x2234 1041166676Sjkim#define BGE_RXLP_LOCSTAT_COS14 0x2238 1042166676Sjkim#define BGE_RXLP_LOCSTAT_COS15 0x223C 1043166676Sjkim#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1044166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1045166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1046166676Sjkim#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1047166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1048166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1049166676Sjkim#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 105084059Swpaul 105184059Swpaul 105284059Swpaul/* Receive List Placement mode register */ 1053166676Sjkim#define BGE_RXLPMODE_RESET 0x00000001 1054166676Sjkim#define BGE_RXLPMODE_ENABLE 0x00000002 1055166676Sjkim#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1056166676Sjkim#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1057166676Sjkim#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 105884059Swpaul 105984059Swpaul/* Receive List Placement Status register */ 1060166676Sjkim#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1061166676Sjkim#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1062166676Sjkim#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 106384059Swpaul 106484059Swpaul/* 106584059Swpaul * Receive Data and Receive BD Initiator Control Registers 106684059Swpaul */ 1067166676Sjkim#define BGE_RDBDI_MODE 0x2400 1068166676Sjkim#define BGE_RDBDI_STATUS 0x2404 1069166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1070166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1071166676Sjkim#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1072166676Sjkim#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1073166676Sjkim#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1074166676Sjkim#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1075166676Sjkim#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1076166676Sjkim#define BGE_RX_STD_RCB_NICADDR 0x245C 1077166676Sjkim#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1078166676Sjkim#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1079166676Sjkim#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1080166676Sjkim#define BGE_RX_MINI_RCB_NICADDR 0x246C 1081166676Sjkim#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1082166676Sjkim#define BGE_RDBDI_STD_RX_CONS 0x2474 1083166676Sjkim#define BGE_RDBDI_MINI_RX_CONS 0x2478 1084166676Sjkim#define BGE_RDBDI_RETURN_PROD0 0x2480 1085166676Sjkim#define BGE_RDBDI_RETURN_PROD1 0x2484 1086166676Sjkim#define BGE_RDBDI_RETURN_PROD2 0x2488 1087166676Sjkim#define BGE_RDBDI_RETURN_PROD3 0x248C 1088166676Sjkim#define BGE_RDBDI_RETURN_PROD4 0x2490 1089166676Sjkim#define BGE_RDBDI_RETURN_PROD5 0x2494 1090166676Sjkim#define BGE_RDBDI_RETURN_PROD6 0x2498 1091166676Sjkim#define BGE_RDBDI_RETURN_PROD7 0x249C 1092166676Sjkim#define BGE_RDBDI_RETURN_PROD8 0x24A0 1093166676Sjkim#define BGE_RDBDI_RETURN_PROD9 0x24A4 1094166676Sjkim#define BGE_RDBDI_RETURN_PROD10 0x24A8 1095166676Sjkim#define BGE_RDBDI_RETURN_PROD11 0x24AC 1096166676Sjkim#define BGE_RDBDI_RETURN_PROD12 0x24B0 1097166676Sjkim#define BGE_RDBDI_RETURN_PROD13 0x24B4 1098166676Sjkim#define BGE_RDBDI_RETURN_PROD14 0x24B8 1099166676Sjkim#define BGE_RDBDI_RETURN_PROD15 0x24BC 1100166676Sjkim#define BGE_RDBDI_HWDIAG 0x24C0 110184059Swpaul 110284059Swpaul 110384059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 1104166676Sjkim#define BGE_RDBDIMODE_RESET 0x00000001 1105166676Sjkim#define BGE_RDBDIMODE_ENABLE 0x00000002 1106166676Sjkim#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1107166676Sjkim#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1108166676Sjkim#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 110984059Swpaul 111084059Swpaul/* Receive Data and Receive BD Initiator Status register */ 1111166676Sjkim#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1112166676Sjkim#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1113166676Sjkim#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 111484059Swpaul 111584059Swpaul 111684059Swpaul/* 111784059Swpaul * Receive Data Completion Control registers 111884059Swpaul */ 1119166676Sjkim#define BGE_RDC_MODE 0x2800 112084059Swpaul 112184059Swpaul/* Receive Data Completion Mode register */ 1122166676Sjkim#define BGE_RDCMODE_RESET 0x00000001 1123166676Sjkim#define BGE_RDCMODE_ENABLE 0x00000002 1124166676Sjkim#define BGE_RDCMODE_ATTN 0x00000004 112584059Swpaul 112684059Swpaul/* 112784059Swpaul * Receive BD Initiator Control registers 112884059Swpaul */ 1129166676Sjkim#define BGE_RBDI_MODE 0x2C00 1130166676Sjkim#define BGE_RBDI_STATUS 0x2C04 1131166676Sjkim#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1132166676Sjkim#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1133166676Sjkim#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1134166676Sjkim#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1135166676Sjkim#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1136166676Sjkim#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 113784059Swpaul 113884059Swpaul/* Receive BD Initiator Mode register */ 1139166676Sjkim#define BGE_RBDIMODE_RESET 0x00000001 1140166676Sjkim#define BGE_RBDIMODE_ENABLE 0x00000002 1141166676Sjkim#define BGE_RBDIMODE_ATTN 0x00000004 114284059Swpaul 114384059Swpaul/* Receive BD Initiator Status register */ 1144166676Sjkim#define BGE_RBDISTAT_ATTN 0x00000004 114584059Swpaul 114684059Swpaul/* 114784059Swpaul * Receive BD Completion Control registers 114884059Swpaul */ 1149166676Sjkim#define BGE_RBDC_MODE 0x3000 1150166676Sjkim#define BGE_RBDC_STATUS 0x3004 1151166676Sjkim#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1152166676Sjkim#define BGE_RBDC_STD_BD_PROD 0x300C 1153166676Sjkim#define BGE_RBDC_MINI_BD_PROD 0x3010 115484059Swpaul 115584059Swpaul/* Receive BD completion mode register */ 1156166676Sjkim#define BGE_RBDCMODE_RESET 0x00000001 1157166676Sjkim#define BGE_RBDCMODE_ENABLE 0x00000002 1158166676Sjkim#define BGE_RBDCMODE_ATTN 0x00000004 115984059Swpaul 116084059Swpaul/* Receive BD completion status register */ 1161166676Sjkim#define BGE_RBDCSTAT_ERROR 0x00000004 116284059Swpaul 116384059Swpaul/* 116484059Swpaul * Receive List Selector Control registers 116584059Swpaul */ 1166166676Sjkim#define BGE_RXLS_MODE 0x3400 1167166676Sjkim#define BGE_RXLS_STATUS 0x3404 116884059Swpaul 116984059Swpaul/* Receive List Selector Mode register */ 1170166676Sjkim#define BGE_RXLSMODE_RESET 0x00000001 1171166676Sjkim#define BGE_RXLSMODE_ENABLE 0x00000002 1172166676Sjkim#define BGE_RXLSMODE_ATTN 0x00000004 117384059Swpaul 117484059Swpaul/* Receive List Selector Status register */ 1175166676Sjkim#define BGE_RXLSSTAT_ERROR 0x00000004 117684059Swpaul 117784059Swpaul/* 117884059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 117984059Swpaul */ 1180166676Sjkim#define BGE_MBCF_MODE 0x3800 1181166676Sjkim#define BGE_MBCF_STATUS 0x3804 118284059Swpaul 118384059Swpaul/* Mbuf Cluster Free mode register */ 1184166676Sjkim#define BGE_MBCFMODE_RESET 0x00000001 1185166676Sjkim#define BGE_MBCFMODE_ENABLE 0x00000002 1186166676Sjkim#define BGE_MBCFMODE_ATTN 0x00000004 118784059Swpaul 118884059Swpaul/* Mbuf Cluster Free status register */ 1189166676Sjkim#define BGE_MBCFSTAT_ERROR 0x00000004 119084059Swpaul 119184059Swpaul/* 119284059Swpaul * Host Coalescing Control registers 119384059Swpaul */ 1194166676Sjkim#define BGE_HCC_MODE 0x3C00 1195166676Sjkim#define BGE_HCC_STATUS 0x3C04 1196166676Sjkim#define BGE_HCC_RX_COAL_TICKS 0x3C08 1197166676Sjkim#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1198166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1199166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1200166676Sjkim#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1201166676Sjkim#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1202166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1203166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1204166676Sjkim#define BGE_HCC_STATS_TICKS 0x3C28 1205166676Sjkim#define BGE_HCC_STATS_ADDR_HI 0x3C30 1206166676Sjkim#define BGE_HCC_STATS_ADDR_LO 0x3C34 1207166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1208166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1209166676Sjkim#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1210166676Sjkim#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1211166676Sjkim#define BGE_FLOW_ATTN 0x3C48 1212166676Sjkim#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1213166676Sjkim#define BGE_HCC_STD_BD_CONS 0x3C54 1214166676Sjkim#define BGE_HCC_MINI_BD_CONS 0x3C58 1215166676Sjkim#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1216166676Sjkim#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1217166676Sjkim#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1218166676Sjkim#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1219166676Sjkim#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1220166676Sjkim#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1221166676Sjkim#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1222166676Sjkim#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1223166676Sjkim#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1224166676Sjkim#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1225166676Sjkim#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1226166676Sjkim#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1227166676Sjkim#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1228166676Sjkim#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1229166676Sjkim#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1230166676Sjkim#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1231166676Sjkim#define BGE_HCC_TX_BD_CONS0 0x3CC0 1232166676Sjkim#define BGE_HCC_TX_BD_CONS1 0x3CC4 1233166676Sjkim#define BGE_HCC_TX_BD_CONS2 0x3CC8 1234166676Sjkim#define BGE_HCC_TX_BD_CONS3 0x3CCC 1235166676Sjkim#define BGE_HCC_TX_BD_CONS4 0x3CD0 1236166676Sjkim#define BGE_HCC_TX_BD_CONS5 0x3CD4 1237166676Sjkim#define BGE_HCC_TX_BD_CONS6 0x3CD8 1238166676Sjkim#define BGE_HCC_TX_BD_CONS7 0x3CDC 1239166676Sjkim#define BGE_HCC_TX_BD_CONS8 0x3CE0 1240166676Sjkim#define BGE_HCC_TX_BD_CONS9 0x3CE4 1241166676Sjkim#define BGE_HCC_TX_BD_CONS10 0x3CE8 1242166676Sjkim#define BGE_HCC_TX_BD_CONS11 0x3CEC 1243166676Sjkim#define BGE_HCC_TX_BD_CONS12 0x3CF0 1244166676Sjkim#define BGE_HCC_TX_BD_CONS13 0x3CF4 1245166676Sjkim#define BGE_HCC_TX_BD_CONS14 0x3CF8 1246166676Sjkim#define BGE_HCC_TX_BD_CONS15 0x3CFC 124784059Swpaul 124884059Swpaul 124984059Swpaul/* Host coalescing mode register */ 1250166676Sjkim#define BGE_HCCMODE_RESET 0x00000001 1251166676Sjkim#define BGE_HCCMODE_ENABLE 0x00000002 1252166676Sjkim#define BGE_HCCMODE_ATTN 0x00000004 1253166676Sjkim#define BGE_HCCMODE_COAL_NOW 0x00000008 1254166676Sjkim#define BGE_HCCMODE_MSI_BITS 0x00000070 1255166676Sjkim#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 125684059Swpaul 1257166676Sjkim#define BGE_STATBLKSZ_FULL 0x00000000 1258166676Sjkim#define BGE_STATBLKSZ_64BYTE 0x00000080 1259166676Sjkim#define BGE_STATBLKSZ_32BYTE 0x00000100 126084059Swpaul 126184059Swpaul/* Host coalescing status register */ 1262166676Sjkim#define BGE_HCCSTAT_ERROR 0x00000004 126384059Swpaul 126484059Swpaul/* Flow attention register */ 1265166676Sjkim#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1266166676Sjkim#define BGE_FLOWATTN_MEMARB 0x00000080 1267166676Sjkim#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1268166676Sjkim#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1269166676Sjkim#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1270166676Sjkim#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1271166676Sjkim#define BGE_FLOWATTN_RDBDI 0x00080000 1272166676Sjkim#define BGE_FLOWATTN_RXLS 0x00100000 1273166676Sjkim#define BGE_FLOWATTN_RXLP 0x00200000 1274166676Sjkim#define BGE_FLOWATTN_RBDC 0x00400000 1275166676Sjkim#define BGE_FLOWATTN_RBDI 0x00800000 1276166676Sjkim#define BGE_FLOWATTN_SDC 0x08000000 1277166676Sjkim#define BGE_FLOWATTN_SDI 0x10000000 1278166676Sjkim#define BGE_FLOWATTN_SRS 0x20000000 1279166676Sjkim#define BGE_FLOWATTN_SBDC 0x40000000 1280166676Sjkim#define BGE_FLOWATTN_SBDI 0x80000000 128184059Swpaul 128284059Swpaul/* 128384059Swpaul * Memory arbiter registers 128484059Swpaul */ 1285166676Sjkim#define BGE_MARB_MODE 0x4000 1286166676Sjkim#define BGE_MARB_STATUS 0x4004 1287166676Sjkim#define BGE_MARB_TRAPADDR_HI 0x4008 1288166676Sjkim#define BGE_MARB_TRAPADDR_LO 0x400C 128984059Swpaul 129084059Swpaul/* Memory arbiter mode register */ 1291166676Sjkim#define BGE_MARBMODE_RESET 0x00000001 1292166676Sjkim#define BGE_MARBMODE_ENABLE 0x00000002 1293166676Sjkim#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1294166676Sjkim#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1295166676Sjkim#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1296166676Sjkim#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1297166676Sjkim#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1298166676Sjkim#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1299166676Sjkim#define BGE_MARBMODE_PCI_TRAP 0x00000100 1300166676Sjkim#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1301166676Sjkim#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1302166676Sjkim#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1303166676Sjkim#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1304166676Sjkim#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1305166676Sjkim#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1306166676Sjkim#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1307166676Sjkim#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1308166676Sjkim#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1309166676Sjkim#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1310166676Sjkim#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1311166676Sjkim#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1312166676Sjkim#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1313166676Sjkim#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1314166676Sjkim#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1315166676Sjkim#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1316166676Sjkim#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 131784059Swpaul 131884059Swpaul/* Memory arbiter status register */ 1319166676Sjkim#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1320166676Sjkim#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1321166676Sjkim#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1322166676Sjkim#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1323166676Sjkim#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1324166676Sjkim#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1325166676Sjkim#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1326166676Sjkim#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1327166676Sjkim#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1328166676Sjkim#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1329166676Sjkim#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1330166676Sjkim#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1331166676Sjkim#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1332166676Sjkim#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1333166676Sjkim#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1334166676Sjkim#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1335166676Sjkim#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1336166676Sjkim#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1337166676Sjkim#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1338166676Sjkim#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1339166676Sjkim#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1340166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1341166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1342166676Sjkim#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 134384059Swpaul 134484059Swpaul/* 134584059Swpaul * Buffer manager control registers 134684059Swpaul */ 1347166676Sjkim#define BGE_BMAN_MODE 0x4400 1348166676Sjkim#define BGE_BMAN_STATUS 0x4404 1349166676Sjkim#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1350166676Sjkim#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1351166676Sjkim#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1352166676Sjkim#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1353166676Sjkim#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1354166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1355166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1356166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1357166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1358166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1359166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1360166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1361166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1362166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1363166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1364166676Sjkim#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1365166676Sjkim#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1366166676Sjkim#define BGE_BMAN_HWDIAG_1 0x444C 1367166676Sjkim#define BGE_BMAN_HWDIAG_2 0x4450 1368166676Sjkim#define BGE_BMAN_HWDIAG_3 0x4454 136984059Swpaul 137084059Swpaul/* Buffer manager mode register */ 1371166676Sjkim#define BGE_BMANMODE_RESET 0x00000001 1372166676Sjkim#define BGE_BMANMODE_ENABLE 0x00000002 1373166676Sjkim#define BGE_BMANMODE_ATTN 0x00000004 1374166676Sjkim#define BGE_BMANMODE_TESTMODE 0x00000008 1375166676Sjkim#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 137684059Swpaul 137784059Swpaul/* Buffer manager status register */ 1378166676Sjkim#define BGE_BMANSTAT_ERRO 0x00000004 1379166676Sjkim#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 138084059Swpaul 138184059Swpaul 138284059Swpaul/* 138384059Swpaul * Read DMA Control registers 138484059Swpaul */ 1385166676Sjkim#define BGE_RDMA_MODE 0x4800 1386166676Sjkim#define BGE_RDMA_STATUS 0x4804 138784059Swpaul 138884059Swpaul/* Read DMA mode register */ 1389166676Sjkim#define BGE_RDMAMODE_RESET 0x00000001 1390166676Sjkim#define BGE_RDMAMODE_ENABLE 0x00000002 1391166676Sjkim#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1392166676Sjkim#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1393166676Sjkim#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1394166676Sjkim#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1395166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1396166676Sjkim#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1397166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1398166676Sjkim#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1399166676Sjkim#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1400197832Sstas#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1401197832Sstas#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1402197832Sstas#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1403190194Smarius#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1404190194Smarius#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1405199671Syongari#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1406199671Syongari#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 140784059Swpaul 140884059Swpaul/* Read DMA status register */ 1409166676Sjkim#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1410166676Sjkim#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1411166676Sjkim#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1412166676Sjkim#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1413166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1414166676Sjkim#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1415166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1416166676Sjkim#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 141784059Swpaul 141884059Swpaul/* 141984059Swpaul * Write DMA control registers 142084059Swpaul */ 1421166676Sjkim#define BGE_WDMA_MODE 0x4C00 1422166676Sjkim#define BGE_WDMA_STATUS 0x4C04 142384059Swpaul 142484059Swpaul/* Write DMA mode register */ 1425166676Sjkim#define BGE_WDMAMODE_RESET 0x00000001 1426166676Sjkim#define BGE_WDMAMODE_ENABLE 0x00000002 1427166676Sjkim#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1428166676Sjkim#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1429166676Sjkim#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1430166676Sjkim#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1431166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1432166676Sjkim#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1433166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1434166676Sjkim#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1435166676Sjkim#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1436197837Sstas#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 143784059Swpaul 143884059Swpaul/* Write DMA status register */ 1439166676Sjkim#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1440166676Sjkim#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1441166676Sjkim#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1442166676Sjkim#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1443166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1444166676Sjkim#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1445166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1446166676Sjkim#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 144784059Swpaul 144884059Swpaul 144984059Swpaul/* 145084059Swpaul * RX CPU registers 145184059Swpaul */ 1452166676Sjkim#define BGE_RXCPU_MODE 0x5000 1453166676Sjkim#define BGE_RXCPU_STATUS 0x5004 1454166676Sjkim#define BGE_RXCPU_PC 0x501C 145584059Swpaul 145684059Swpaul/* RX CPU mode register */ 1457166676Sjkim#define BGE_RXCPUMODE_RESET 0x00000001 1458166676Sjkim#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1459166676Sjkim#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1460166676Sjkim#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1461166676Sjkim#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1462166676Sjkim#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1463166676Sjkim#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1464166676Sjkim#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1465166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1466166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1467166676Sjkim#define BGE_RXCPUMODE_HALTCPU 0x00000400 1468166676Sjkim#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1469166676Sjkim#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1470166676Sjkim#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 147184059Swpaul 147284059Swpaul/* RX CPU status register */ 1473166676Sjkim#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1474166676Sjkim#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1475166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1476166676Sjkim#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1477166676Sjkim#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1478166676Sjkim#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1479166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1480166676Sjkim#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1481166676Sjkim#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1482166676Sjkim#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1483166676Sjkim#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1484166676Sjkim#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1485166676Sjkim#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1486166676Sjkim#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1487166676Sjkim#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1488166676Sjkim#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1489166676Sjkim#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 149084059Swpaul 1491178667Sjhb/* 1492178667Sjhb * V? CPU registers 1493178667Sjhb */ 1494178667Sjhb#define BGE_VCPU_STATUS 0x5100 1495178667Sjhb#define BGE_VCPU_EXT_CTRL 0x6890 149684059Swpaul 1497178667Sjhb#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1498178667Sjhb#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1499178667Sjhb 1500178667Sjhb#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1501178667Sjhb#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1502178667Sjhb 150384059Swpaul/* 150484059Swpaul * TX CPU registers 150584059Swpaul */ 1506166676Sjkim#define BGE_TXCPU_MODE 0x5400 1507166676Sjkim#define BGE_TXCPU_STATUS 0x5404 1508166676Sjkim#define BGE_TXCPU_PC 0x541C 150984059Swpaul 151084059Swpaul/* TX CPU mode register */ 1511166676Sjkim#define BGE_TXCPUMODE_RESET 0x00000001 1512166676Sjkim#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1513166676Sjkim#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1514166676Sjkim#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1515166676Sjkim#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1516166676Sjkim#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1517166676Sjkim#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1518166676Sjkim#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1519166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1520166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1521166676Sjkim#define BGE_TXCPUMODE_HALTCPU 0x00000400 1522166676Sjkim#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1523166676Sjkim#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 152484059Swpaul 152584059Swpaul/* TX CPU status register */ 1526166676Sjkim#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1527166676Sjkim#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1528166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1529166676Sjkim#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1530166676Sjkim#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1531166676Sjkim#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1532166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1533166676Sjkim#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1534166676Sjkim#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1535166676Sjkim#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1536166676Sjkim#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1537166676Sjkim#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1538166676Sjkim#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1539166676Sjkim#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1540166676Sjkim#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1541166676Sjkim#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1542166676Sjkim#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 154384059Swpaul 154484059Swpaul 154584059Swpaul/* 154684059Swpaul * Low priority mailbox registers 154784059Swpaul */ 1548166676Sjkim#define BGE_LPMBX_IRQ0_HI 0x5800 1549166676Sjkim#define BGE_LPMBX_IRQ0_LO 0x5804 1550166676Sjkim#define BGE_LPMBX_IRQ1_HI 0x5808 1551166676Sjkim#define BGE_LPMBX_IRQ1_LO 0x580C 1552166676Sjkim#define BGE_LPMBX_IRQ2_HI 0x5810 1553166676Sjkim#define BGE_LPMBX_IRQ2_LO 0x5814 1554166676Sjkim#define BGE_LPMBX_IRQ3_HI 0x5818 1555166676Sjkim#define BGE_LPMBX_IRQ3_LO 0x581C 1556166676Sjkim#define BGE_LPMBX_GEN0_HI 0x5820 1557166676Sjkim#define BGE_LPMBX_GEN0_LO 0x5824 1558166676Sjkim#define BGE_LPMBX_GEN1_HI 0x5828 1559166676Sjkim#define BGE_LPMBX_GEN1_LO 0x582C 1560166676Sjkim#define BGE_LPMBX_GEN2_HI 0x5830 1561166676Sjkim#define BGE_LPMBX_GEN2_LO 0x5834 1562166676Sjkim#define BGE_LPMBX_GEN3_HI 0x5828 1563166676Sjkim#define BGE_LPMBX_GEN3_LO 0x582C 1564166676Sjkim#define BGE_LPMBX_GEN4_HI 0x5840 1565166676Sjkim#define BGE_LPMBX_GEN4_LO 0x5844 1566166676Sjkim#define BGE_LPMBX_GEN5_HI 0x5848 1567166676Sjkim#define BGE_LPMBX_GEN5_LO 0x584C 1568166676Sjkim#define BGE_LPMBX_GEN6_HI 0x5850 1569166676Sjkim#define BGE_LPMBX_GEN6_LO 0x5854 1570166676Sjkim#define BGE_LPMBX_GEN7_HI 0x5858 1571166676Sjkim#define BGE_LPMBX_GEN7_LO 0x585C 1572166676Sjkim#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1573166676Sjkim#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1574166676Sjkim#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1575166676Sjkim#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1576166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1577166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1578166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1579166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1580166676Sjkim#define BGE_LPMBX_RX_CONS0_HI 0x5880 1581166676Sjkim#define BGE_LPMBX_RX_CONS0_LO 0x5884 1582166676Sjkim#define BGE_LPMBX_RX_CONS1_HI 0x5888 1583166676Sjkim#define BGE_LPMBX_RX_CONS1_LO 0x588C 1584166676Sjkim#define BGE_LPMBX_RX_CONS2_HI 0x5890 1585166676Sjkim#define BGE_LPMBX_RX_CONS2_LO 0x5894 1586166676Sjkim#define BGE_LPMBX_RX_CONS3_HI 0x5898 1587166676Sjkim#define BGE_LPMBX_RX_CONS3_LO 0x589C 1588166676Sjkim#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1589166676Sjkim#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1590166676Sjkim#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1591166676Sjkim#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1592166676Sjkim#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1593166676Sjkim#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1594166676Sjkim#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1595166676Sjkim#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1596166676Sjkim#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1597166676Sjkim#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1598166676Sjkim#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1599166676Sjkim#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1600166676Sjkim#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1601166676Sjkim#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1602166676Sjkim#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1603166676Sjkim#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1604166676Sjkim#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1605166676Sjkim#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1606166676Sjkim#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1607166676Sjkim#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1608166676Sjkim#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1609166676Sjkim#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1610166676Sjkim#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1611166676Sjkim#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1612166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1613166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1614166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1615166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1616166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1617166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1618166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1619166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1620166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1621166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1622166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1623166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1624166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1625166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1626166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1627166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1628166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1629166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1630166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1631166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1632166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1633166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1634166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1635166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1636166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1637166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1638166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1639166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1640166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1641166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1642166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1643166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1644166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1645166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1646166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1647166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1648166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1649166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1650166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1651166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1652166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1653166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1654166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1655166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1656166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1657166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1658166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1659166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1660166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1661166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1662166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1663166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1664166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1665166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1666166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1667166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1668166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1669166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1670166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1671166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1672166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1673166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1674166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1675166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 167684059Swpaul 167784059Swpaul/* 167884059Swpaul * Flow throw Queue reset register 167984059Swpaul */ 1680166676Sjkim#define BGE_FTQ_RESET 0x5C00 168184059Swpaul 1682166676Sjkim#define BGE_FTQRESET_DMAREAD 0x00000002 1683166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1684166676Sjkim#define BGE_FTQRESET_DMADONE 0x00000010 1685166676Sjkim#define BGE_FTQRESET_SBDC 0x00000020 1686166676Sjkim#define BGE_FTQRESET_SDI 0x00000040 1687166676Sjkim#define BGE_FTQRESET_WDMA 0x00000080 1688166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1689166676Sjkim#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1690166676Sjkim#define BGE_FTQRESET_SDC 0x00000400 1691166676Sjkim#define BGE_FTQRESET_HCC 0x00000800 1692166676Sjkim#define BGE_FTQRESET_TXFIFO 0x00001000 1693166676Sjkim#define BGE_FTQRESET_MBC 0x00002000 1694166676Sjkim#define BGE_FTQRESET_RBDC 0x00004000 1695166676Sjkim#define BGE_FTQRESET_RXLP 0x00008000 1696166676Sjkim#define BGE_FTQRESET_RDBDI 0x00010000 1697166676Sjkim#define BGE_FTQRESET_RDC 0x00020000 1698166676Sjkim#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 169984059Swpaul 170084059Swpaul/* 170184059Swpaul * Message Signaled Interrupt registers 170284059Swpaul */ 1703166676Sjkim#define BGE_MSI_MODE 0x6000 1704166676Sjkim#define BGE_MSI_STATUS 0x6004 1705166676Sjkim#define BGE_MSI_FIFOACCESS 0x6008 170684059Swpaul 170784059Swpaul/* MSI mode register */ 1708166676Sjkim#define BGE_MSIMODE_RESET 0x00000001 1709166676Sjkim#define BGE_MSIMODE_ENABLE 0x00000002 1710198967Syongari#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1711198967Syongari#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 171284059Swpaul 171384059Swpaul/* MSI status register */ 1714166676Sjkim#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1715166676Sjkim#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1716166676Sjkim#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1717166676Sjkim#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1718166676Sjkim#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 171984059Swpaul 172084059Swpaul 172184059Swpaul/* 172284059Swpaul * DMA Completion registers 172384059Swpaul */ 1724166676Sjkim#define BGE_DMAC_MODE 0x6400 172584059Swpaul 172684059Swpaul/* DMA Completion mode register */ 1727166676Sjkim#define BGE_DMACMODE_RESET 0x00000001 1728166676Sjkim#define BGE_DMACMODE_ENABLE 0x00000002 172984059Swpaul 173084059Swpaul 173184059Swpaul/* 173284059Swpaul * General control registers. 173384059Swpaul */ 1734166676Sjkim#define BGE_MODE_CTL 0x6800 1735166676Sjkim#define BGE_MISC_CFG 0x6804 1736166676Sjkim#define BGE_MISC_LOCAL_CTL 0x6808 1737166676Sjkim#define BGE_CPU_EVENT 0x6810 1738166676Sjkim#define BGE_EE_ADDR 0x6838 1739166676Sjkim#define BGE_EE_DATA 0x683C 1740166676Sjkim#define BGE_EE_CTL 0x6840 1741166676Sjkim#define BGE_MDI_CTL 0x6844 1742166676Sjkim#define BGE_EE_DELAY 0x6848 1743166676Sjkim#define BGE_FASTBOOT_PC 0x6894 174484059Swpaul 1745178667Sjhb/* 1746178667Sjhb * NVRAM Control registers 1747178667Sjhb */ 1748178667Sjhb#define BGE_NVRAM_CMD 0x7000 1749178667Sjhb#define BGE_NVRAM_STAT 0x7004 1750178667Sjhb#define BGE_NVRAM_WRDATA 0x7008 1751178667Sjhb#define BGE_NVRAM_ADDR 0x700c 1752178667Sjhb#define BGE_NVRAM_RDDATA 0x7010 1753178667Sjhb#define BGE_NVRAM_CFG1 0x7014 1754178667Sjhb#define BGE_NVRAM_CFG2 0x7018 1755178667Sjhb#define BGE_NVRAM_CFG3 0x701c 1756178667Sjhb#define BGE_NVRAM_SWARB 0x7020 1757178667Sjhb#define BGE_NVRAM_ACCESS 0x7024 1758178667Sjhb#define BGE_NVRAM_WRITE1 0x7028 1759178667Sjhb 1760178667Sjhb#define BGE_NVRAMCMD_RESET 0x00000001 1761178667Sjhb#define BGE_NVRAMCMD_DONE 0x00000008 1762178667Sjhb#define BGE_NVRAMCMD_START 0x00000010 1763178667Sjhb#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1764178667Sjhb#define BGE_NVRAMCMD_ERASE 0x00000040 1765178667Sjhb#define BGE_NVRAMCMD_FIRST 0x00000080 1766178667Sjhb#define BGE_NVRAMCMD_LAST 0x00000100 1767178667Sjhb 1768178667Sjhb#define BGE_NVRAM_READCMD \ 1769178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1770178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1771178667Sjhb#define BGE_NVRAM_WRITECMD \ 1772178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1773178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1774178667Sjhb 1775178667Sjhb#define BGE_NVRAMSWARB_SET0 0x00000001 1776178667Sjhb#define BGE_NVRAMSWARB_SET1 0x00000002 1777178667Sjhb#define BGE_NVRAMSWARB_SET2 0x00000003 1778178667Sjhb#define BGE_NVRAMSWARB_SET3 0x00000004 1779178667Sjhb#define BGE_NVRAMSWARB_CLR0 0x00000010 1780178667Sjhb#define BGE_NVRAMSWARB_CLR1 0x00000020 1781178667Sjhb#define BGE_NVRAMSWARB_CLR2 0x00000040 1782178667Sjhb#define BGE_NVRAMSWARB_CLR3 0x00000080 1783178667Sjhb#define BGE_NVRAMSWARB_GNT0 0x00000100 1784178667Sjhb#define BGE_NVRAMSWARB_GNT1 0x00000200 1785178667Sjhb#define BGE_NVRAMSWARB_GNT2 0x00000400 1786178667Sjhb#define BGE_NVRAMSWARB_GNT3 0x00000800 1787178667Sjhb#define BGE_NVRAMSWARB_REQ0 0x00001000 1788178667Sjhb#define BGE_NVRAMSWARB_REQ1 0x00002000 1789178667Sjhb#define BGE_NVRAMSWARB_REQ2 0x00004000 1790178667Sjhb#define BGE_NVRAMSWARB_REQ3 0x00008000 1791178667Sjhb 1792178667Sjhb#define BGE_NVRAMACC_ENABLE 0x00000001 1793178667Sjhb#define BGE_NVRAMACC_WRENABLE 0x00000002 1794178667Sjhb 179584059Swpaul/* Mode control register */ 1796166676Sjkim#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1797166676Sjkim#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1798166676Sjkim#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1799166676Sjkim#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1800166676Sjkim#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1801166676Sjkim#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1802166676Sjkim#define BGE_MODECTL_NO_RX_CRC 0x00000400 1803166676Sjkim#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1804166676Sjkim#define BGE_MODECTL_NO_TX_INTR 0x00002000 1805166676Sjkim#define BGE_MODECTL_NO_RX_INTR 0x00004000 1806166676Sjkim#define BGE_MODECTL_FORCE_PCI32 0x00008000 1807166676Sjkim#define BGE_MODECTL_STACKUP 0x00010000 1808166676Sjkim#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1809166676Sjkim#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1810166676Sjkim#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1811166676Sjkim#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1812166676Sjkim#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1813166676Sjkim#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1814166676Sjkim#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1815166676Sjkim#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1816166676Sjkim#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1817166676Sjkim#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 181884059Swpaul 181984059Swpaul/* Misc. config register */ 1820166676Sjkim#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1821166676Sjkim#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1822178785Sbz#define BGE_MISCCFG_BOARD_ID 0x0001E000 1823178785Sbz#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1824178785Sbz#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1825178667Sjhb#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 182684059Swpaul 1827166676Sjkim#define BGE_32BITTIME_66MHZ (0x41 << 1) 182884059Swpaul 182984059Swpaul/* Misc. Local Control */ 1830166676Sjkim#define BGE_MLC_INTR_STATE 0x00000001 1831166676Sjkim#define BGE_MLC_INTR_CLR 0x00000002 1832166676Sjkim#define BGE_MLC_INTR_SET 0x00000004 1833166676Sjkim#define BGE_MLC_INTR_ONATTN 0x00000008 1834166676Sjkim#define BGE_MLC_MISCIO_IN0 0x00000100 1835166676Sjkim#define BGE_MLC_MISCIO_IN1 0x00000200 1836166676Sjkim#define BGE_MLC_MISCIO_IN2 0x00000400 1837166676Sjkim#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1838166676Sjkim#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1839166676Sjkim#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1840166676Sjkim#define BGE_MLC_MISCIO_OUT0 0x00004000 1841166676Sjkim#define BGE_MLC_MISCIO_OUT1 0x00008000 1842166676Sjkim#define BGE_MLC_MISCIO_OUT2 0x00010000 1843166676Sjkim#define BGE_MLC_EXTRAM_ENB 0x00020000 1844166676Sjkim#define BGE_MLC_SRAM_SIZE 0x001C0000 1845166676Sjkim#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1846166676Sjkim#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1847166676Sjkim#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1848166676Sjkim#define BGE_MLC_AUTO_EEPROM 0x01000000 184984059Swpaul 1850166676Sjkim#define BGE_SSRAMSIZE_256KB 0x00000000 1851166676Sjkim#define BGE_SSRAMSIZE_512KB 0x00040000 1852166676Sjkim#define BGE_SSRAMSIZE_1MB 0x00080000 1853166676Sjkim#define BGE_SSRAMSIZE_2MB 0x000C0000 1854166676Sjkim#define BGE_SSRAMSIZE_4MB 0x00100000 1855166676Sjkim#define BGE_SSRAMSIZE_8MB 0x00140000 1856166676Sjkim#define BGE_SSRAMSIZE_16M 0x00180000 185784059Swpaul 185884059Swpaul/* EEPROM address register */ 1859166676Sjkim#define BGE_EEADDR_ADDRESS 0x0000FFFC 1860166676Sjkim#define BGE_EEADDR_HALFCLK 0x01FF0000 1861166676Sjkim#define BGE_EEADDR_START 0x02000000 1862166676Sjkim#define BGE_EEADDR_DEVID 0x1C000000 1863166676Sjkim#define BGE_EEADDR_RESET 0x20000000 1864166676Sjkim#define BGE_EEADDR_DONE 0x40000000 1865166676Sjkim#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 186684059Swpaul 1867166676Sjkim#define BGE_EEDEVID(x) ((x & 7) << 26) 1868166676Sjkim#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1869166676Sjkim#define BGE_HALFCLK_384SCL 0x60 1870166676Sjkim#define BGE_EE_READCMD \ 187184059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 187284059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1873166676Sjkim#define BGE_EE_WRCMD \ 187484059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 187584059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 187684059Swpaul 187784059Swpaul/* EEPROM Control register */ 1878166676Sjkim#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1879166676Sjkim#define BGE_EECTL_CLKOUT 0x00000002 1880166676Sjkim#define BGE_EECTL_CLKIN 0x00000004 1881166676Sjkim#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1882166676Sjkim#define BGE_EECTL_DATAOUT 0x00000010 1883166676Sjkim#define BGE_EECTL_DATAIN 0x00000020 188484059Swpaul 188584059Swpaul/* MDI (MII/GMII) access register */ 1886166676Sjkim#define BGE_MDI_DATA 0x00000001 1887166676Sjkim#define BGE_MDI_DIR 0x00000002 1888166676Sjkim#define BGE_MDI_SEL 0x00000004 1889166676Sjkim#define BGE_MDI_CLK 0x00000008 189084059Swpaul 1891166676Sjkim#define BGE_MEMWIN_START 0x00008000 1892166676Sjkim#define BGE_MEMWIN_END 0x0000FFFF 189384059Swpaul 189484059Swpaul 1895166676Sjkim#define BGE_MEMWIN_READ(sc, x, val) \ 189684059Swpaul do { \ 189784059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 189884059Swpaul (0xFFFF0000 & x), 4); \ 189984059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 190084059Swpaul } while(0) 190184059Swpaul 1902166676Sjkim#define BGE_MEMWIN_WRITE(sc, x, val) \ 190384059Swpaul do { \ 190484059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 190584059Swpaul (0xFFFF0000 & x), 4); \ 190684059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 190784059Swpaul } while(0) 190884059Swpaul 190984059Swpaul/* 1910161847Sdavidch * This magic number is written to the firmware mailbox at 0xb50 1911161847Sdavidch * before a software reset is issued. After the internal firmware 1912199661Syongari * has completed its initialization it will write the opposite of 1913161847Sdavidch * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1914161847Sdavidch * driver to synchronize with the firmware. 191584059Swpaul */ 1916166676Sjkim#define BGE_MAGIC_NUMBER 0x4B657654 191784059Swpaul 191884059Swpaultypedef struct { 1919159395Sglebius uint32_t bge_addr_hi; 1920159395Sglebius uint32_t bge_addr_lo; 192184059Swpaul} bge_hostaddr; 1922118026Swpaul 1923166676Sjkim#define BGE_HOSTADDR(x, y) \ 1924115200Sps do { \ 1925159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1926159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1927115200Sps } while(0) 192884059Swpaul 1929166676Sjkim#define BGE_ADDR_LO(y) \ 1930159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 1931166676Sjkim#define BGE_ADDR_HI(y) \ 1932159395Sglebius ((uint64_t) (y) >> 32) 1933118026Swpaul 193484059Swpaul/* Ring control block structure */ 193584059Swpaulstruct bge_rcb { 193684059Swpaul bge_hostaddr bge_hostaddr; 1937159395Sglebius uint32_t bge_maxlen_flags; 1938159395Sglebius uint32_t bge_nicaddr; 193984059Swpaul}; 1940153437Syongari 1941153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 1942183896Smarius bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 1943166676Sjkim#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 194484059Swpaul 1945166676Sjkim#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1946166676Sjkim#define BGE_RCB_FLAG_RING_DISABLED 0x0002 194784059Swpaul 194884059Swpaulstruct bge_tx_bd { 194984059Swpaul bge_hostaddr bge_addr; 1950153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1951159395Sglebius uint16_t bge_flags; 1952159395Sglebius uint16_t bge_len; 1953159395Sglebius uint16_t bge_vlan_tag; 1954199671Syongari uint16_t bge_mss; 1955153437Syongari#else 1956159395Sglebius uint16_t bge_len; 1957159395Sglebius uint16_t bge_flags; 1958199671Syongari uint16_t bge_mss; 1959159395Sglebius uint16_t bge_vlan_tag; 1960153437Syongari#endif 196184059Swpaul}; 196284059Swpaul 1963166676Sjkim#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1964166676Sjkim#define BGE_TXBDFLAG_IP_CSUM 0x0002 1965166676Sjkim#define BGE_TXBDFLAG_END 0x0004 1966166676Sjkim#define BGE_TXBDFLAG_IP_FRAG 0x0008 1967166676Sjkim#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1968166676Sjkim#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1969166676Sjkim#define BGE_TXBDFLAG_COAL_NOW 0x0080 1970166676Sjkim#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1971166676Sjkim#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1972166676Sjkim#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1973166676Sjkim#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1974166676Sjkim#define BGE_TXBDFLAG_NO_CRC 0x8000 197584059Swpaul 1976166676Sjkim#define BGE_NIC_TXRING_ADDR(ringno, size) \ 197784059Swpaul BGE_SEND_RING_1_TO_4 + \ 197884059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 197984059Swpaul 198084059Swpaulstruct bge_rx_bd { 198184059Swpaul bge_hostaddr bge_addr; 1982153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1983159395Sglebius uint16_t bge_len; 1984159395Sglebius uint16_t bge_idx; 1985159395Sglebius uint16_t bge_flags; 1986159395Sglebius uint16_t bge_type; 1987159395Sglebius uint16_t bge_tcp_udp_csum; 1988159395Sglebius uint16_t bge_ip_csum; 1989159395Sglebius uint16_t bge_vlan_tag; 1990159395Sglebius uint16_t bge_error_flag; 1991153437Syongari#else 1992159395Sglebius uint16_t bge_idx; 1993159395Sglebius uint16_t bge_len; 1994159395Sglebius uint16_t bge_type; 1995159395Sglebius uint16_t bge_flags; 1996159395Sglebius uint16_t bge_ip_csum; 1997159395Sglebius uint16_t bge_tcp_udp_csum; 1998159395Sglebius uint16_t bge_error_flag; 1999159395Sglebius uint16_t bge_vlan_tag; 2000153437Syongari#endif 2001159395Sglebius uint32_t bge_rsvd; 2002159395Sglebius uint32_t bge_opaque; 200384059Swpaul}; 200484059Swpaul 2005153239Sglebiusstruct bge_extrx_bd { 2006153239Sglebius bge_hostaddr bge_addr1; 2007153239Sglebius bge_hostaddr bge_addr2; 2008153239Sglebius bge_hostaddr bge_addr3; 2009153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2010159395Sglebius uint16_t bge_len2; 2011159395Sglebius uint16_t bge_len1; 2012159395Sglebius uint16_t bge_rsvd1; 2013159395Sglebius uint16_t bge_len3; 2014153437Syongari#else 2015159395Sglebius uint16_t bge_len1; 2016159395Sglebius uint16_t bge_len2; 2017159395Sglebius uint16_t bge_len3; 2018159395Sglebius uint16_t bge_rsvd1; 2019153437Syongari#endif 2020153239Sglebius bge_hostaddr bge_addr0; 2021153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2022159395Sglebius uint16_t bge_len0; 2023159395Sglebius uint16_t bge_idx; 2024159395Sglebius uint16_t bge_flags; 2025159395Sglebius uint16_t bge_type; 2026159395Sglebius uint16_t bge_tcp_udp_csum; 2027159395Sglebius uint16_t bge_ip_csum; 2028159395Sglebius uint16_t bge_vlan_tag; 2029159395Sglebius uint16_t bge_error_flag; 2030153437Syongari#else 2031159395Sglebius uint16_t bge_idx; 2032159395Sglebius uint16_t bge_len0; 2033159395Sglebius uint16_t bge_type; 2034159395Sglebius uint16_t bge_flags; 2035159395Sglebius uint16_t bge_ip_csum; 2036159395Sglebius uint16_t bge_tcp_udp_csum; 2037159395Sglebius uint16_t bge_error_flag; 2038159395Sglebius uint16_t bge_vlan_tag; 2039153437Syongari#endif 2040159395Sglebius uint32_t bge_rsvd0; 2041159395Sglebius uint32_t bge_opaque; 2042153239Sglebius}; 2043153239Sglebius 2044166676Sjkim#define BGE_RXBDFLAG_END 0x0004 2045166676Sjkim#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2046166676Sjkim#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2047166676Sjkim#define BGE_RXBDFLAG_ERROR 0x0400 2048166676Sjkim#define BGE_RXBDFLAG_MINI_RING 0x0800 2049166676Sjkim#define BGE_RXBDFLAG_IP_CSUM 0x1000 2050166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2051166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 205284059Swpaul 2053166676Sjkim#define BGE_RXERRFLAG_BAD_CRC 0x0001 2054166676Sjkim#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2055166676Sjkim#define BGE_RXERRFLAG_LINK_LOST 0x0004 2056166676Sjkim#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2057166676Sjkim#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2058166676Sjkim#define BGE_RXERRFLAG_RUNT 0x0020 2059166676Sjkim#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2060166676Sjkim#define BGE_RXERRFLAG_GIANT 0x0080 206184059Swpaul 206284059Swpaulstruct bge_sts_idx { 2063153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2064159395Sglebius uint16_t bge_rx_prod_idx; 2065159395Sglebius uint16_t bge_tx_cons_idx; 2066153437Syongari#else 2067159395Sglebius uint16_t bge_tx_cons_idx; 2068159395Sglebius uint16_t bge_rx_prod_idx; 2069153437Syongari#endif 207084059Swpaul}; 207184059Swpaul 207284059Swpaulstruct bge_status_block { 2073159395Sglebius uint32_t bge_status; 2074159395Sglebius uint32_t bge_rsvd0; 2075153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2076159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2077159395Sglebius uint16_t bge_rx_std_cons_idx; 2078159395Sglebius uint16_t bge_rx_mini_cons_idx; 2079159395Sglebius uint16_t bge_rsvd1; 2080153437Syongari#else 2081159395Sglebius uint16_t bge_rx_std_cons_idx; 2082159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2083159395Sglebius uint16_t bge_rsvd1; 2084159395Sglebius uint16_t bge_rx_mini_cons_idx; 2085153437Syongari#endif 208684059Swpaul struct bge_sts_idx bge_idx[16]; 208784059Swpaul}; 208884059Swpaul 2089166676Sjkim#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2090166676Sjkim#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 209184059Swpaul 2092166676Sjkim#define BGE_STATFLAG_UPDATED 0x00000001 2093166676Sjkim#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2094166676Sjkim#define BGE_STATFLAG_ERROR 0x00000004 209584059Swpaul 209684059Swpaul 209784059Swpaul/* 209884059Swpaul * Broadcom Vendor ID 209984059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 210084059Swpaul * even though they're now manufactured by Broadcom) 210184059Swpaul */ 2102166676Sjkim#define BCOM_VENDORID 0x14E4 2103166676Sjkim#define BCOM_DEVICEID_BCM5700 0x1644 2104166676Sjkim#define BCOM_DEVICEID_BCM5701 0x1645 2105166676Sjkim#define BCOM_DEVICEID_BCM5702 0x1646 2106166676Sjkim#define BCOM_DEVICEID_BCM5702X 0x16A6 2107166676Sjkim#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2108166676Sjkim#define BCOM_DEVICEID_BCM5703 0x1647 2109166676Sjkim#define BCOM_DEVICEID_BCM5703X 0x16A7 2110166676Sjkim#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2111166676Sjkim#define BCOM_DEVICEID_BCM5704C 0x1648 2112166676Sjkim#define BCOM_DEVICEID_BCM5704S 0x16A8 2113166676Sjkim#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2114166676Sjkim#define BCOM_DEVICEID_BCM5705 0x1653 2115166676Sjkim#define BCOM_DEVICEID_BCM5705K 0x1654 2116166676Sjkim#define BCOM_DEVICEID_BCM5705F 0x166E 2117166676Sjkim#define BCOM_DEVICEID_BCM5705M 0x165D 2118166676Sjkim#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2119166676Sjkim#define BCOM_DEVICEID_BCM5714C 0x1668 2120166676Sjkim#define BCOM_DEVICEID_BCM5714S 0x1669 2121166676Sjkim#define BCOM_DEVICEID_BCM5715 0x1678 2122166676Sjkim#define BCOM_DEVICEID_BCM5715S 0x1679 2123166676Sjkim#define BCOM_DEVICEID_BCM5720 0x1658 2124166676Sjkim#define BCOM_DEVICEID_BCM5721 0x1659 2125176883Sjhb#define BCOM_DEVICEID_BCM5722 0x165A 2126197832Sstas#define BCOM_DEVICEID_BCM5723 0x165B 2127166676Sjkim#define BCOM_DEVICEID_BCM5750 0x1676 2128166676Sjkim#define BCOM_DEVICEID_BCM5750M 0x167C 2129166676Sjkim#define BCOM_DEVICEID_BCM5751 0x1677 2130166676Sjkim#define BCOM_DEVICEID_BCM5751F 0x167E 2131166676Sjkim#define BCOM_DEVICEID_BCM5751M 0x167D 2132166676Sjkim#define BCOM_DEVICEID_BCM5752 0x1600 2133166676Sjkim#define BCOM_DEVICEID_BCM5752M 0x1601 2134166676Sjkim#define BCOM_DEVICEID_BCM5753 0x16F7 2135166676Sjkim#define BCOM_DEVICEID_BCM5753F 0x16FE 2136166676Sjkim#define BCOM_DEVICEID_BCM5753M 0x16FD 2137166676Sjkim#define BCOM_DEVICEID_BCM5754 0x167A 2138166676Sjkim#define BCOM_DEVICEID_BCM5754M 0x1672 2139166676Sjkim#define BCOM_DEVICEID_BCM5755 0x167B 2140166676Sjkim#define BCOM_DEVICEID_BCM5755M 0x1673 2141197832Sstas#define BCOM_DEVICEID_BCM5761 0x1681 2142197832Sstas#define BCOM_DEVICEID_BCM5761E 0x1680 2143197832Sstas#define BCOM_DEVICEID_BCM5761S 0x1688 2144197832Sstas#define BCOM_DEVICEID_BCM5761SE 0x1689 2145197832Sstas#define BCOM_DEVICEID_BCM5764 0x1684 2146166676Sjkim#define BCOM_DEVICEID_BCM5780 0x166A 2147166676Sjkim#define BCOM_DEVICEID_BCM5780S 0x166B 2148166676Sjkim#define BCOM_DEVICEID_BCM5781 0x16DD 2149166676Sjkim#define BCOM_DEVICEID_BCM5782 0x1696 2150197832Sstas#define BCOM_DEVICEID_BCM5784 0x1698 2151197832Sstas#define BCOM_DEVICEID_BCM5785F 0x16a0 2152197832Sstas#define BCOM_DEVICEID_BCM5785G 0x1699 2153166676Sjkim#define BCOM_DEVICEID_BCM5786 0x169A 2154166676Sjkim#define BCOM_DEVICEID_BCM5787 0x169B 2155166676Sjkim#define BCOM_DEVICEID_BCM5787M 0x1693 2156197832Sstas#define BCOM_DEVICEID_BCM5787F 0x167f 2157166676Sjkim#define BCOM_DEVICEID_BCM5788 0x169C 2158166676Sjkim#define BCOM_DEVICEID_BCM5789 0x169D 2159166676Sjkim#define BCOM_DEVICEID_BCM5901 0x170D 2160166676Sjkim#define BCOM_DEVICEID_BCM5901A2 0x170E 2161166676Sjkim#define BCOM_DEVICEID_BCM5903M 0x16FF 2162178667Sjhb#define BCOM_DEVICEID_BCM5906 0x1712 2163178667Sjhb#define BCOM_DEVICEID_BCM5906M 0x1713 2164197832Sstas#define BCOM_DEVICEID_BCM57760 0x1690 2165197832Sstas#define BCOM_DEVICEID_BCM57780 0x1692 2166197832Sstas#define BCOM_DEVICEID_BCM57788 0x1691 2167197832Sstas#define BCOM_DEVICEID_BCM57790 0x1694 216884059Swpaul 216984059Swpaul/* 217084059Swpaul * Alteon AceNIC PCI vendor/device ID. 217184059Swpaul */ 2172166676Sjkim#define ALTEON_VENDORID 0x12AE 2173166676Sjkim#define ALTEON_DEVICEID_ACENIC 0x0001 2174166676Sjkim#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2175166676Sjkim#define ALTEON_DEVICEID_BCM5700 0x0003 2176166676Sjkim#define ALTEON_DEVICEID_BCM5701 0x0004 217784059Swpaul 217884059Swpaul/* 2179162982Sglebius * 3Com 3c996 PCI vendor/device ID. 218084059Swpaul */ 2181166676Sjkim#define TC_VENDORID 0x10B7 2182166676Sjkim#define TC_DEVICEID_3C996 0x0003 218384059Swpaul 218484059Swpaul/* 218584059Swpaul * SysKonnect PCI vendor ID 218684059Swpaul */ 2187166676Sjkim#define SK_VENDORID 0x1148 2188166676Sjkim#define SK_DEVICEID_ALTIMA 0x4400 2189166676Sjkim#define SK_SUBSYSID_9D21 0x4421 2190166676Sjkim#define SK_SUBSYSID_9D41 0x4441 219184059Swpaul 219284059Swpaul/* 219389835Sjdp * Altima PCI vendor/device ID. 219489835Sjdp */ 2195166676Sjkim#define ALTIMA_VENDORID 0x173b 2196166676Sjkim#define ALTIMA_DEVICE_AC1000 0x03e8 2197166676Sjkim#define ALTIMA_DEVICE_AC1002 0x03e9 2198166676Sjkim#define ALTIMA_DEVICE_AC9100 0x03ea 219989835Sjdp 220089835Sjdp/* 2201119157Sambrisko * Dell PCI vendor ID 2202119157Sambrisko */ 2203119157Sambrisko 2204166676Sjkim#define DELL_VENDORID 0x1028 2205119157Sambrisko 2206119157Sambrisko/* 2207159637Sglebius * Apple PCI vendor ID. 2208159637Sglebius */ 2209166676Sjkim#define APPLE_VENDORID 0x106b 2210166676Sjkim#define APPLE_DEVICE_BCM5701 0x1645 2211159637Sglebius 2212159637Sglebius/* 2213169152Smarius * Sun PCI vendor ID 2214169152Smarius */ 2215169152Smarius#define SUN_VENDORID 0x108e 2216169152Smarius 2217169152Smarius/* 2218197832Sstas * Fujitsu vendor/device IDs 2219197832Sstas */ 2220197832Sstas#define FJTSU_VENDORID 0x10cf 2221197832Sstas#define FJTSU_DEVICEID_PW008GE5 0x11a1 2222197832Sstas#define FJTSU_DEVICEID_PW008GE4 0x11a2 2223197832Sstas#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2224197832Sstas 2225197832Sstas/* 222684059Swpaul * Offset of MAC address inside EEPROM. 222784059Swpaul */ 2228166676Sjkim#define BGE_EE_MAC_OFFSET 0x7C 2229178667Sjhb#define BGE_EE_MAC_OFFSET_5906 0x10 2230166676Sjkim#define BGE_EE_HWCFG_OFFSET 0xC8 223184059Swpaul 2232166676Sjkim#define BGE_HWCFG_VOLTAGE 0x00000003 2233166676Sjkim#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2234166676Sjkim#define BGE_HWCFG_MEDIA 0x00000030 2235166676Sjkim#define BGE_HWCFG_ASF 0x00000080 223693751Swpaul 2237166676Sjkim#define BGE_VOLTAGE_1POINT3 0x00000000 2238166676Sjkim#define BGE_VOLTAGE_1POINT8 0x00000001 223993751Swpaul 2240166676Sjkim#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2241166676Sjkim#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2242166676Sjkim#define BGE_PHYLEDMODE_SINGLELED 0x00000008 224393751Swpaul 2244166676Sjkim#define BGE_MEDIA_UNSPEC 0x00000000 2245166676Sjkim#define BGE_MEDIA_COPPER 0x00000010 2246166676Sjkim#define BGE_MEDIA_FIBER 0x00000020 224793751Swpaul 2248166676Sjkim#define BGE_TICKS_PER_SEC 1000000 224984059Swpaul 225084059Swpaul/* 225184059Swpaul * Ring size constants. 225284059Swpaul */ 2253166676Sjkim#define BGE_EVENT_RING_CNT 256 2254166676Sjkim#define BGE_CMD_RING_CNT 64 2255166676Sjkim#define BGE_STD_RX_RING_CNT 512 2256166676Sjkim#define BGE_JUMBO_RX_RING_CNT 256 2257166676Sjkim#define BGE_MINI_RX_RING_CNT 1024 2258166676Sjkim#define BGE_RETURN_RING_CNT 1024 225984059Swpaul 2260117659Swpaul/* 5705 has smaller return ring size */ 2261117659Swpaul 2262166676Sjkim#define BGE_RETURN_RING_CNT_5705 512 2263117659Swpaul 226484059Swpaul/* 226584059Swpaul * Possible TX ring sizes. 226684059Swpaul */ 2267166676Sjkim#define BGE_TX_RING_CNT_128 128 2268166676Sjkim#define BGE_TX_RING_BASE_128 0x3800 226984059Swpaul 2270166676Sjkim#define BGE_TX_RING_CNT_256 256 2271166676Sjkim#define BGE_TX_RING_BASE_256 0x3000 227284059Swpaul 2273166676Sjkim#define BGE_TX_RING_CNT_512 512 2274166676Sjkim#define BGE_TX_RING_BASE_512 0x2000 227584059Swpaul 2276166676Sjkim#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2277166676Sjkim#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 227884059Swpaul 227984059Swpaul/* 228084059Swpaul * Tigon III statistics counters. 228184059Swpaul */ 2282117659Swpaul/* Statistics maintained MAC Receive block. */ 2283117659Swpaulstruct bge_rx_mac_stats { 228484059Swpaul bge_hostaddr ifHCInOctets; 228584059Swpaul bge_hostaddr Reserved1; 228684059Swpaul bge_hostaddr etherStatsFragments; 228784059Swpaul bge_hostaddr ifHCInUcastPkts; 228884059Swpaul bge_hostaddr ifHCInMulticastPkts; 228984059Swpaul bge_hostaddr ifHCInBroadcastPkts; 229084059Swpaul bge_hostaddr dot3StatsFCSErrors; 229184059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 229284059Swpaul bge_hostaddr xonPauseFramesReceived; 229384059Swpaul bge_hostaddr xoffPauseFramesReceived; 229484059Swpaul bge_hostaddr macControlFramesReceived; 229584059Swpaul bge_hostaddr xoffStateEntered; 229684059Swpaul bge_hostaddr dot3StatsFramesTooLong; 229784059Swpaul bge_hostaddr etherStatsJabbers; 229884059Swpaul bge_hostaddr etherStatsUndersizePkts; 229984059Swpaul bge_hostaddr inRangeLengthError; 230084059Swpaul bge_hostaddr outRangeLengthError; 230184059Swpaul bge_hostaddr etherStatsPkts64Octets; 230284059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 230384059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 230484059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 230584059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 230684059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 230784059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 230884059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 230984059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 231084059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2311117659Swpaul}; 231284059Swpaul 231384059Swpaul 2314117659Swpaul/* Statistics maintained MAC Transmit block. */ 2315117659Swpaulstruct bge_tx_mac_stats { 231684059Swpaul bge_hostaddr ifHCOutOctets; 231784059Swpaul bge_hostaddr Reserved2; 231884059Swpaul bge_hostaddr etherStatsCollisions; 231984059Swpaul bge_hostaddr outXonSent; 232084059Swpaul bge_hostaddr outXoffSent; 232184059Swpaul bge_hostaddr flowControlDone; 232284059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 232384059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 232484059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 232584059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 232684059Swpaul bge_hostaddr Reserved3; 232784059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 232884059Swpaul bge_hostaddr dot3StatsLateCollisions; 232984059Swpaul bge_hostaddr dot3Collided2Times; 233084059Swpaul bge_hostaddr dot3Collided3Times; 233184059Swpaul bge_hostaddr dot3Collided4Times; 233284059Swpaul bge_hostaddr dot3Collided5Times; 233384059Swpaul bge_hostaddr dot3Collided6Times; 233484059Swpaul bge_hostaddr dot3Collided7Times; 233584059Swpaul bge_hostaddr dot3Collided8Times; 233684059Swpaul bge_hostaddr dot3Collided9Times; 233784059Swpaul bge_hostaddr dot3Collided10Times; 233884059Swpaul bge_hostaddr dot3Collided11Times; 233984059Swpaul bge_hostaddr dot3Collided12Times; 234084059Swpaul bge_hostaddr dot3Collided13Times; 234184059Swpaul bge_hostaddr dot3Collided14Times; 234284059Swpaul bge_hostaddr dot3Collided15Times; 234384059Swpaul bge_hostaddr ifHCOutUcastPkts; 234484059Swpaul bge_hostaddr ifHCOutMulticastPkts; 234584059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 234684059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 234784059Swpaul bge_hostaddr ifOutDiscards; 234884059Swpaul bge_hostaddr ifOutErrors; 2349117659Swpaul}; 235084059Swpaul 2351117659Swpaul/* Stats counters access through registers */ 2352117659Swpaulstruct bge_mac_stats_regs { 2353159395Sglebius uint32_t ifHCOutOctets; 2354159395Sglebius uint32_t Reserved0; 2355159395Sglebius uint32_t etherStatsCollisions; 2356159395Sglebius uint32_t outXonSent; 2357159395Sglebius uint32_t outXoffSent; 2358159395Sglebius uint32_t Reserved1; 2359159395Sglebius uint32_t dot3StatsInternalMacTransmitErrors; 2360159395Sglebius uint32_t dot3StatsSingleCollisionFrames; 2361159395Sglebius uint32_t dot3StatsMultipleCollisionFrames; 2362159395Sglebius uint32_t dot3StatsDeferredTransmissions; 2363159395Sglebius uint32_t Reserved2; 2364159395Sglebius uint32_t dot3StatsExcessiveCollisions; 2365159395Sglebius uint32_t dot3StatsLateCollisions; 2366159395Sglebius uint32_t Reserved3[14]; 2367159395Sglebius uint32_t ifHCOutUcastPkts; 2368159395Sglebius uint32_t ifHCOutMulticastPkts; 2369159395Sglebius uint32_t ifHCOutBroadcastPkts; 2370159395Sglebius uint32_t Reserved4[2]; 2371159395Sglebius uint32_t ifHCInOctets; 2372159395Sglebius uint32_t Reserved5; 2373159395Sglebius uint32_t etherStatsFragments; 2374159395Sglebius uint32_t ifHCInUcastPkts; 2375159395Sglebius uint32_t ifHCInMulticastPkts; 2376159395Sglebius uint32_t ifHCInBroadcastPkts; 2377159395Sglebius uint32_t dot3StatsFCSErrors; 2378159395Sglebius uint32_t dot3StatsAlignmentErrors; 2379159395Sglebius uint32_t xonPauseFramesReceived; 2380159395Sglebius uint32_t xoffPauseFramesReceived; 2381159395Sglebius uint32_t macControlFramesReceived; 2382159395Sglebius uint32_t xoffStateEntered; 2383159395Sglebius uint32_t dot3StatsFramesTooLong; 2384159395Sglebius uint32_t etherStatsJabbers; 2385159395Sglebius uint32_t etherStatsUndersizePkts; 2386117659Swpaul}; 2387117659Swpaul 2388117659Swpaulstruct bge_stats { 2389159395Sglebius uint8_t Reserved0[256]; 2390117659Swpaul 2391117659Swpaul /* Statistics maintained by Receive MAC. */ 2392117659Swpaul struct bge_rx_mac_stats rxstats; 2393117659Swpaul 2394117659Swpaul bge_hostaddr Unused1[37]; 2395117659Swpaul 2396117659Swpaul /* Statistics maintained by Transmit MAC. */ 2397117659Swpaul struct bge_tx_mac_stats txstats; 2398117659Swpaul 239984059Swpaul bge_hostaddr Unused2[31]; 240084059Swpaul 240184059Swpaul /* Statistics maintained by Receive List Placement. */ 240284059Swpaul bge_hostaddr COSIfHCInPkts[16]; 240384059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 240484059Swpaul bge_hostaddr nicDmaWriteQueueFull; 240584059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 240684059Swpaul bge_hostaddr nicNoMoreRxBDs; 240784059Swpaul bge_hostaddr ifInDiscards; 240884059Swpaul bge_hostaddr ifInErrors; 240984059Swpaul bge_hostaddr nicRecvThresholdHit; 241084059Swpaul 241184059Swpaul bge_hostaddr Unused3[9]; 241284059Swpaul 241384059Swpaul /* Statistics maintained by Send Data Initiator. */ 241484059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 241584059Swpaul bge_hostaddr nicDmaReadQueueFull; 241684059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 241784059Swpaul bge_hostaddr nicSendDataCompQueueFull; 241884059Swpaul 241984059Swpaul /* Statistics maintained by Host Coalescing. */ 242084059Swpaul bge_hostaddr nicRingSetSendProdIndex; 242184059Swpaul bge_hostaddr nicRingStatusUpdate; 242284059Swpaul bge_hostaddr nicInterrupts; 242384059Swpaul bge_hostaddr nicAvoidedInterrupts; 242484059Swpaul bge_hostaddr nicSendThresholdHit; 242584059Swpaul 2426159395Sglebius uint8_t Reserved4[320]; 242784059Swpaul}; 242884059Swpaul 242984059Swpaul/* 243084059Swpaul * Tigon general information block. This resides in host memory 243184059Swpaul * and contains the status counters, ring control blocks and 243284059Swpaul * producer pointers. 243384059Swpaul */ 243484059Swpaul 243584059Swpaulstruct bge_gib { 243684059Swpaul struct bge_stats bge_stats; 243784059Swpaul struct bge_rcb bge_tx_rcb[16]; 243884059Swpaul struct bge_rcb bge_std_rx_rcb; 243984059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 244084059Swpaul struct bge_rcb bge_mini_rx_rcb; 244184059Swpaul struct bge_rcb bge_return_rcb; 244284059Swpaul}; 244384059Swpaul 2444166676Sjkim#define BGE_FRAMELEN 1518 2445166676Sjkim#define BGE_MAX_FRAMELEN 1536 2446166676Sjkim#define BGE_JUMBO_FRAMELEN 9018 2447166676Sjkim#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2448166676Sjkim#define BGE_MIN_FRAMELEN 60 244984059Swpaul 245084059Swpaul/* 245184059Swpaul * Other utility macros. 245284059Swpaul */ 2453166676Sjkim#define BGE_INC(x, y) (x) = (x + 1) % y 245484059Swpaul 245584059Swpaul/* 245684059Swpaul * Register access macros. The Tigon always uses memory mapped register 245784059Swpaul * accesses and all registers must be accessed with 32 bit operations. 245884059Swpaul */ 245984059Swpaul 2460166676Sjkim#define CSR_WRITE_4(sc, reg, val) \ 2461183896Smarius bus_write_4(sc->bge_res, reg, val) 246284059Swpaul 2463166676Sjkim#define CSR_READ_4(sc, reg) \ 2464183896Smarius bus_read_4(sc->bge_res, reg) 246584059Swpaul 2466166676Sjkim#define BGE_SETBIT(sc, reg, x) \ 2467106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2468166676Sjkim#define BGE_CLRBIT(sc, reg, x) \ 2469106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 247084059Swpaul 2471166676Sjkim#define PCI_SETBIT(dev, reg, x, s) \ 2472106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2473166676Sjkim#define PCI_CLRBIT(dev, reg, x, s) \ 2474106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 247584059Swpaul 247684059Swpaul/* 247784059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 247884059Swpaul * values are tuneable. They control the actual amount of buffers 247984059Swpaul * allocated for the standard, mini and jumbo receive rings. 248084059Swpaul */ 248184059Swpaul 2482166676Sjkim#define BGE_SSLOTS 256 2483166676Sjkim#define BGE_MSLOTS 256 2484166676Sjkim#define BGE_JSLOTS 384 248584059Swpaul 2486166676Sjkim#define BGE_NSEG_JUMBO 4 2487199671Syongari#define BGE_NSEG_NEW 32 2488199671Syongari#define BGE_TSOSEG_SZ 4096 2489153239Sglebius 2490199670Syongari/* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2491199670Syongari#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2492199670Syongari#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2493199670Syongari#else 2494199670Syongari#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2495199670Syongari#endif 2496199670Syongari 249784059Swpaul/* 249884059Swpaul * Ring structures. Most of these reside in host memory and we tell 249984059Swpaul * the NIC where they are via the ring control blocks. The exceptions 250084059Swpaul * are the tx and command rings, which live in NIC memory and which 250184059Swpaul * we access via the shared memory window. 250284059Swpaul */ 2503118026Swpaul 250484059Swpaulstruct bge_ring_data { 2505118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2506118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2507153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2508118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2509118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2510118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2511118026Swpaul struct bge_tx_bd *bge_tx_ring; 2512118026Swpaul bus_addr_t bge_tx_ring_paddr; 2513118026Swpaul struct bge_status_block *bge_status_block; 2514118026Swpaul bus_addr_t bge_status_block_paddr; 2515118026Swpaul struct bge_stats *bge_stats; 2516118026Swpaul bus_addr_t bge_stats_paddr; 251784059Swpaul struct bge_gib bge_info; 251884059Swpaul}; 251984059Swpaul 2520166676Sjkim#define BGE_STD_RX_RING_SZ \ 2521118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2522166676Sjkim#define BGE_JUMBO_RX_RING_SZ \ 2523153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2524166676Sjkim#define BGE_TX_RING_SZ \ 2525118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2526166676Sjkim#define BGE_RX_RTN_RING_SZ(x) \ 2527118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2528118026Swpaul 2529166676Sjkim#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2530118026Swpaul 2531166676Sjkim#define BGE_STATS_SZ sizeof (struct bge_stats) 2532118026Swpaul 253384059Swpaul/* 253484059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 253584059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 253684059Swpaul * not the other way around. 253784059Swpaul */ 253884059Swpaulstruct bge_chain_data { 2539118026Swpaul bus_dma_tag_t bge_parent_tag; 2540118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2541118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2542118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2543118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2544118026Swpaul bus_dma_tag_t bge_status_tag; 2545118026Swpaul bus_dma_tag_t bge_stats_tag; 2546198927Syongari bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2547198927Syongari bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2548198927Syongari bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2549118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2550199011Syongari bus_dmamap_t bge_rx_std_sparemap; 2551118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2552199011Syongari bus_dmamap_t bge_rx_jumbo_sparemap; 2553118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2554118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2555118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2556118026Swpaul bus_dmamap_t bge_tx_ring_map; 2557118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2558118026Swpaul bus_dmamap_t bge_status_map; 2559118026Swpaul bus_dmamap_t bge_stats_map; 256084059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 256184059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 256284059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 256384059Swpaul}; 256484059Swpaul 2565118026Swpaulstruct bge_dmamap_arg { 2566118026Swpaul struct bge_softc *sc; 2567118026Swpaul bus_addr_t bge_busaddr; 2568159395Sglebius uint16_t bge_flags; 2569118026Swpaul int bge_idx; 2570118026Swpaul int bge_maxsegs; 2571118026Swpaul struct bge_tx_bd *bge_ring; 2572118026Swpaul}; 2573118026Swpaul 2574166676Sjkim#define BGE_HWREV_TIGON 0x01 2575166676Sjkim#define BGE_HWREV_TIGON_II 0x02 2576166676Sjkim#define BGE_TIMEOUT 100000 2577166676Sjkim#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 257884059Swpaul 257984059Swpaulstruct bge_bcom_hack { 258084059Swpaul int reg; 258184059Swpaul int val; 258284059Swpaul}; 258384059Swpaul 2584166676Sjkim#define ASF_ENABLE 1 2585166676Sjkim#define ASF_NEW_HANDSHAKE 2 2586166676Sjkim#define ASF_STACKUP 4 2587162169Sambrisko 258884059Swpaulstruct bge_softc { 2589147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 259084059Swpaul device_t bge_dev; 2591122497Ssam struct mtx bge_mtx; 259284059Swpaul device_t bge_miibus; 259384059Swpaul void *bge_intrhand; 259484059Swpaul struct resource *bge_irq; 259584059Swpaul struct resource *bge_res; 259684059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2597199664Syongari int bge_expcap; 2598199664Syongari int bge_msicap; 2599199664Syongari int bge_pcixcap; 2600161546Sglebius uint32_t bge_flags; 2601166676Sjkim#define BGE_FLAG_TBI 0x00000001 2602166676Sjkim#define BGE_FLAG_JUMBO 0x00000002 2603175466Sjkim#define BGE_FLAG_WIRESPEED 0x00000004 2604178996Smarius#define BGE_FLAG_EADDR 0x00000008 2605166676Sjkim#define BGE_FLAG_MSI 0x00000100 2606166676Sjkim#define BGE_FLAG_PCIX 0x00000200 2607166676Sjkim#define BGE_FLAG_PCIE 0x00000400 2608199671Syongari#define BGE_FLAG_TSO 0x00000800 2609166676Sjkim#define BGE_FLAG_5700_FAMILY 0x00001000 2610166676Sjkim#define BGE_FLAG_5705_PLUS 0x00002000 2611166676Sjkim#define BGE_FLAG_5714_FAMILY 0x00004000 2612166676Sjkim#define BGE_FLAG_575X_PLUS 0x00008000 2613197832Sstas#define BGE_FLAG_5755_PLUS 0x00010000 2614199670Syongari#define BGE_FLAG_40BIT_BUG 0x00020000 2615199670Syongari#define BGE_FLAG_4G_BNDRY_BUG 0x00040000 2616166676Sjkim#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2617166676Sjkim#define BGE_FLAG_NO_3LED 0x00200000 2618166676Sjkim#define BGE_FLAG_ADC_BUG 0x00400000 2619166676Sjkim#define BGE_FLAG_5704_A0_BUG 0x00800000 2620166676Sjkim#define BGE_FLAG_JITTER_BUG 0x01000000 2621166676Sjkim#define BGE_FLAG_BER_BUG 0x02000000 2622166676Sjkim#define BGE_FLAG_ADJUST_TRIM 0x04000000 2623166677Sjkim#define BGE_FLAG_CRC_BUG 0x08000000 2624178785Sbz#define BGE_FLAG_5788 0x20000000 2625159395Sglebius uint32_t bge_chipid; 2626197832Sstas uint32_t bge_asicrev; 2627197832Sstas uint32_t bge_chiprev; 2628162169Sambrisko uint8_t bge_asf_mode; 2629162169Sambrisko uint8_t bge_asf_count; 2630118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 263184059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 2632159395Sglebius uint16_t bge_tx_saved_considx; 2633159395Sglebius uint16_t bge_rx_saved_considx; 2634159395Sglebius uint16_t bge_ev_saved_considx; 2635159395Sglebius uint16_t bge_return_ring_cnt; 2636159395Sglebius uint16_t bge_std; /* current std ring head */ 2637159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 2638159395Sglebius uint32_t bge_stat_ticks; 2639159395Sglebius uint32_t bge_rx_coal_ticks; 2640159395Sglebius uint32_t bge_tx_coal_ticks; 2641159395Sglebius uint32_t bge_tx_prodidx; 2642159395Sglebius uint32_t bge_rx_max_coal_bds; 2643159395Sglebius uint32_t bge_tx_max_coal_bds; 2644159395Sglebius uint32_t bge_tx_buf_ratio; 264584059Swpaul int bge_if_flags; 264684059Swpaul int bge_txcnt; 2647155180Soleg int bge_link; /* link state */ 2648155180Soleg int bge_link_evt; /* pending link event */ 2649164769Sglebius int bge_timer; 2650200264Syongari int bge_forced_collapse; 2651122497Ssam struct callout bge_stat_ch; 2652164780Sjkim uint32_t bge_rx_discards; 2653164780Sjkim uint32_t bge_tx_discards; 2654164780Sjkim uint32_t bge_tx_collisions; 2655151553Sglebius#ifdef DEVICE_POLLING 2656151553Sglebius int rxcycles; 2657151553Sglebius#endif /* DEVICE_POLLING */ 2658199668Syongari struct task bge_intr_task; 2659199668Syongari struct taskqueue *bge_tq; 266084059Swpaul}; 2661122497Ssam 2662122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2663122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2664122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2665122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2666122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2667122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2668