if_bgereg.h revision 183896
1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 183896 2008-10-14 20:28:42Z marius $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 64166676Sjkim#define BGE_PAGE_ZERO 0x00000000 65166676Sjkim#define BGE_PAGE_ZERO_END 0x000000FF 66166676Sjkim#define BGE_SEND_RING_RCB 0x00000100 67166676Sjkim#define BGE_SEND_RING_RCB_END 0x000001FF 68166676Sjkim#define BGE_RX_RETURN_RING_RCB 0x00000200 69166676Sjkim#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70166676Sjkim#define BGE_STATS_BLOCK 0x00000300 71166676Sjkim#define BGE_STATS_BLOCK_END 0x00000AFF 72166676Sjkim#define BGE_STATUS_BLOCK 0x00000B00 73166676Sjkim#define BGE_STATUS_BLOCK_END 0x00000B4F 74166676Sjkim#define BGE_SOFTWARE_GENCOMM 0x00000B50 75166676Sjkim#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76166676Sjkim#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77166676Sjkim#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78166676Sjkim#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79166676Sjkim#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80166676Sjkim#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81166676Sjkim#define BGE_UNMAPPED 0x00001000 82166676Sjkim#define BGE_UNMAPPED_END 0x00001FFF 83166676Sjkim#define BGE_DMA_DESCRIPTORS 0x00002000 84166676Sjkim#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85166676Sjkim#define BGE_SEND_RING_1_TO_4 0x00004000 86166676Sjkim#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8784059Swpaul 88166676Sjkim/* Firmware interface */ 89166676Sjkim#define BGE_FW_DRV_ALIVE 0x00000001 90166676Sjkim#define BGE_FW_PAUSE 0x00000002 91166676Sjkim 9284059Swpaul/* Mappings for internal memory configuration */ 93166676Sjkim#define BGE_STD_RX_RINGS 0x00006000 94166676Sjkim#define BGE_STD_RX_RINGS_END 0x00006FFF 95166676Sjkim#define BGE_JUMBO_RX_RINGS 0x00007000 96166676Sjkim#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97166676Sjkim#define BGE_BUFFPOOL_1 0x00008000 98166676Sjkim#define BGE_BUFFPOOL_1_END 0x0000FFFF 99166676Sjkim#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 100166676Sjkim#define BGE_BUFFPOOL_2_END 0x00017FFF 101166676Sjkim#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 102166676Sjkim#define BGE_BUFFPOOL_3_END 0x0001FFFF 10384059Swpaul 10484059Swpaul/* Mappings for external SSRAM configurations */ 105166676Sjkim#define BGE_SEND_RING_5_TO_6 0x00006000 106166676Sjkim#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107166676Sjkim#define BGE_SEND_RING_7_TO_8 0x00007000 108166676Sjkim#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109166676Sjkim#define BGE_SEND_RING_9_TO_16 0x00008000 110166676Sjkim#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111166676Sjkim#define BGE_EXT_STD_RX_RINGS 0x0000C000 112166676Sjkim#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115166676Sjkim#define BGE_MINI_RX_RINGS 0x0000E000 116166676Sjkim#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117166676Sjkim#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 118166676Sjkim#define BGE_AVAIL_REGION1_END 0x00017FFF 119166676Sjkim#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 120166676Sjkim#define BGE_AVAIL_REGION2_END 0x0001FFFF 121166676Sjkim#define BGE_EXT_SSRAM 0x00020000 122166676Sjkim#define BGE_EXT_SSRAM_END 0x000FFFFF 12384059Swpaul 12484059Swpaul 12584059Swpaul/* 12684059Swpaul * BCM570x register offsets. These are memory mapped registers 12784059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12884059Swpaul * Each register must be accessed using 32 bit operations. 12984059Swpaul * 13084059Swpaul * All registers are accessed through a 32K shared memory block. 13184059Swpaul * The first group of registers are actually copies of the PCI 13284059Swpaul * configuration space registers. 13384059Swpaul */ 13484059Swpaul 13584059Swpaul/* 13684059Swpaul * PCI registers defined in the PCI 2.2 spec. 13784059Swpaul */ 138166676Sjkim#define BGE_PCI_VID 0x00 139166676Sjkim#define BGE_PCI_DID 0x02 140166676Sjkim#define BGE_PCI_CMD 0x04 141166676Sjkim#define BGE_PCI_STS 0x06 142166676Sjkim#define BGE_PCI_REV 0x08 143166676Sjkim#define BGE_PCI_CLASS 0x09 144166676Sjkim#define BGE_PCI_CACHESZ 0x0C 145166676Sjkim#define BGE_PCI_LATTIMER 0x0D 146166676Sjkim#define BGE_PCI_HDRTYPE 0x0E 147166676Sjkim#define BGE_PCI_BIST 0x0F 148166676Sjkim#define BGE_PCI_BAR0 0x10 149166676Sjkim#define BGE_PCI_BAR1 0x14 150166676Sjkim#define BGE_PCI_SUBSYS 0x2C 151166676Sjkim#define BGE_PCI_SUBVID 0x2E 152166676Sjkim#define BGE_PCI_ROMBASE 0x30 153166676Sjkim#define BGE_PCI_CAPPTR 0x34 154166676Sjkim#define BGE_PCI_INTLINE 0x3C 155166676Sjkim#define BGE_PCI_INTPIN 0x3D 156166676Sjkim#define BGE_PCI_MINGNT 0x3E 157166676Sjkim#define BGE_PCI_MAXLAT 0x3F 158166676Sjkim#define BGE_PCI_PCIXCAP 0x40 159166676Sjkim#define BGE_PCI_NEXTPTR_PM 0x41 160166676Sjkim#define BGE_PCI_PCIX_CMD 0x42 161166676Sjkim#define BGE_PCI_PCIX_STS 0x44 162166676Sjkim#define BGE_PCI_PWRMGMT_CAPID 0x48 163166676Sjkim#define BGE_PCI_NEXTPTR_VPD 0x49 164166676Sjkim#define BGE_PCI_PWRMGMT_CAPS 0x4A 165166676Sjkim#define BGE_PCI_PWRMGMT_CMD 0x4C 166166676Sjkim#define BGE_PCI_PWRMGMT_STS 0x4D 167166676Sjkim#define BGE_PCI_PWRMGMT_DATA 0x4F 168166676Sjkim#define BGE_PCI_VPD_CAPID 0x50 169166676Sjkim#define BGE_PCI_NEXTPTR_MSI 0x51 170166676Sjkim#define BGE_PCI_VPD_ADDR 0x52 171166676Sjkim#define BGE_PCI_VPD_DATA 0x54 172166676Sjkim#define BGE_PCI_MSI_CAPID 0x58 173166676Sjkim#define BGE_PCI_NEXTPTR_NONE 0x59 174166676Sjkim#define BGE_PCI_MSI_CTL 0x5A 175166676Sjkim#define BGE_PCI_MSI_ADDR_HI 0x5C 176166676Sjkim#define BGE_PCI_MSI_ADDR_LO 0x60 177166676Sjkim#define BGE_PCI_MSI_DATA 0x64 17884059Swpaul 179135772Sps/* PCI MSI. ??? */ 180166676Sjkim#define BGE_PCIE_CAPID_REG 0xD0 181166676Sjkim#define BGE_PCIE_CAPID 0x10 182135772Sps 18384059Swpaul/* 18484059Swpaul * PCI registers specific to the BCM570x family. 18584059Swpaul */ 186166676Sjkim#define BGE_PCI_MISC_CTL 0x68 187166676Sjkim#define BGE_PCI_DMA_RW_CTL 0x6C 188166676Sjkim#define BGE_PCI_PCISTATE 0x70 189166676Sjkim#define BGE_PCI_CLKCTL 0x74 190166676Sjkim#define BGE_PCI_REG_BASEADDR 0x78 191166676Sjkim#define BGE_PCI_MEMWIN_BASEADDR 0x7C 192166676Sjkim#define BGE_PCI_REG_DATA 0x80 193166676Sjkim#define BGE_PCI_MEMWIN_DATA 0x84 194166676Sjkim#define BGE_PCI_MODECTL 0x88 195166676Sjkim#define BGE_PCI_MISC_CFG 0x8C 196166676Sjkim#define BGE_PCI_MISC_LOCALCTL 0x90 197166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 198166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 199166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 200166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 201166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 202166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 203166676Sjkim#define BGE_PCI_ISR_MBX_HI 0xB0 204166676Sjkim#define BGE_PCI_ISR_MBX_LO 0xB4 20584059Swpaul 20684059Swpaul/* PCI Misc. Host control register */ 207166676Sjkim#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 208166676Sjkim#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 209166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 210166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 211166676Sjkim#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 212166676Sjkim#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 213166676Sjkim#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 214166676Sjkim#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 215166676Sjkim#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 21684059Swpaul 217166676Sjkim#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 218153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 219166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 220153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME| \ 221153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 222153437Syongari#else 223166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 224153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 225153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 226153437Syongari#endif 22784059Swpaul 228166676Sjkim#define BGE_INIT \ 229153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 230153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 23184059Swpaul 232166676Sjkim#define BGE_CHIPID_TIGON_I 0x40000000 233166676Sjkim#define BGE_CHIPID_TIGON_II 0x60000000 234166676Sjkim#define BGE_CHIPID_BCM5700_A0 0x70000000 235166676Sjkim#define BGE_CHIPID_BCM5700_A1 0x70010000 236166676Sjkim#define BGE_CHIPID_BCM5700_B0 0x71000000 237166676Sjkim#define BGE_CHIPID_BCM5700_B1 0x71010000 238166676Sjkim#define BGE_CHIPID_BCM5700_B2 0x71020000 239166676Sjkim#define BGE_CHIPID_BCM5700_B3 0x71030000 240166676Sjkim#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 241166676Sjkim#define BGE_CHIPID_BCM5700_C0 0x72000000 242166676Sjkim#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 243166676Sjkim#define BGE_CHIPID_BCM5701_B0 0x01000000 244166676Sjkim#define BGE_CHIPID_BCM5701_B2 0x01020000 245166676Sjkim#define BGE_CHIPID_BCM5701_B5 0x01050000 246166676Sjkim#define BGE_CHIPID_BCM5703_A0 0x10000000 247166676Sjkim#define BGE_CHIPID_BCM5703_A1 0x10010000 248166676Sjkim#define BGE_CHIPID_BCM5703_A2 0x10020000 249166676Sjkim#define BGE_CHIPID_BCM5703_A3 0x10030000 250166676Sjkim#define BGE_CHIPID_BCM5703_B0 0x11000000 251166676Sjkim#define BGE_CHIPID_BCM5704_A0 0x20000000 252166676Sjkim#define BGE_CHIPID_BCM5704_A1 0x20010000 253166676Sjkim#define BGE_CHIPID_BCM5704_A2 0x20020000 254166676Sjkim#define BGE_CHIPID_BCM5704_A3 0x20030000 255166676Sjkim#define BGE_CHIPID_BCM5704_B0 0x21000000 256166676Sjkim#define BGE_CHIPID_BCM5705_A0 0x30000000 257166676Sjkim#define BGE_CHIPID_BCM5705_A1 0x30010000 258166676Sjkim#define BGE_CHIPID_BCM5705_A2 0x30020000 259166676Sjkim#define BGE_CHIPID_BCM5705_A3 0x30030000 260166676Sjkim#define BGE_CHIPID_BCM5750_A0 0x40000000 261166676Sjkim#define BGE_CHIPID_BCM5750_A1 0x40010000 262166676Sjkim#define BGE_CHIPID_BCM5750_A3 0x40030000 263166676Sjkim#define BGE_CHIPID_BCM5750_B0 0x41000000 264166676Sjkim#define BGE_CHIPID_BCM5750_B1 0x41010000 265166676Sjkim#define BGE_CHIPID_BCM5750_C0 0x42000000 266166676Sjkim#define BGE_CHIPID_BCM5750_C1 0x42010000 267166676Sjkim#define BGE_CHIPID_BCM5750_C2 0x42020000 268166676Sjkim#define BGE_CHIPID_BCM5714_A0 0x50000000 269166676Sjkim#define BGE_CHIPID_BCM5752_A0 0x60000000 270166676Sjkim#define BGE_CHIPID_BCM5752_A1 0x60010000 271166676Sjkim#define BGE_CHIPID_BCM5752_A2 0x60020000 272166676Sjkim#define BGE_CHIPID_BCM5714_B0 0x80000000 273166676Sjkim#define BGE_CHIPID_BCM5714_B3 0x80030000 274166676Sjkim#define BGE_CHIPID_BCM5715_A0 0x90000000 275166676Sjkim#define BGE_CHIPID_BCM5715_A1 0x90010000 276167351Sjkim#define BGE_CHIPID_BCM5715_A3 0x90030000 277166676Sjkim#define BGE_CHIPID_BCM5755_A0 0xa0000000 278166676Sjkim#define BGE_CHIPID_BCM5755_A1 0xa0010000 279166676Sjkim#define BGE_CHIPID_BCM5755_A2 0xa0020000 280176881Sjhb#define BGE_CHIPID_BCM5722_A0 0xa2000000 281166676Sjkim#define BGE_CHIPID_BCM5754_A0 0xb0000000 282166676Sjkim#define BGE_CHIPID_BCM5754_A1 0xb0010000 283166676Sjkim#define BGE_CHIPID_BCM5754_A2 0xb0020000 284166676Sjkim#define BGE_CHIPID_BCM5787_A0 0xb0000000 285166676Sjkim#define BGE_CHIPID_BCM5787_A1 0xb0010000 286166676Sjkim#define BGE_CHIPID_BCM5787_A2 0xb0020000 287178667Sjhb#define BGE_CHIPID_BCM5906_A1 0xc0010000 288178667Sjhb#define BGE_CHIPID_BCM5906_A2 0xc0020000 28984059Swpaul 29093751Swpaul/* shorthand one */ 291166676Sjkim#define BGE_ASICREV(x) ((x) >> 28) 292166676Sjkim#define BGE_ASICREV_BCM5701 0x00 293166676Sjkim#define BGE_ASICREV_BCM5703 0x01 294166676Sjkim#define BGE_ASICREV_BCM5704 0x02 295166676Sjkim#define BGE_ASICREV_BCM5705 0x03 296166676Sjkim#define BGE_ASICREV_BCM5750 0x04 297166676Sjkim#define BGE_ASICREV_BCM5714_A0 0x05 298166676Sjkim#define BGE_ASICREV_BCM5752 0x06 299166676Sjkim#define BGE_ASICREV_BCM5700 0x07 300166676Sjkim#define BGE_ASICREV_BCM5780 0x08 301166676Sjkim#define BGE_ASICREV_BCM5714 0x09 302166676Sjkim#define BGE_ASICREV_BCM5755 0x0a 303166676Sjkim#define BGE_ASICREV_BCM5754 0x0b 304166676Sjkim#define BGE_ASICREV_BCM5787 0x0b 305178667Sjhb#define BGE_ASICREV_BCM5906 0x0c 30693751Swpaul 307114813Sps/* chip revisions */ 308166676Sjkim#define BGE_CHIPREV(x) ((x) >> 24) 309166676Sjkim#define BGE_CHIPREV_5700_AX 0x70 310166676Sjkim#define BGE_CHIPREV_5700_BX 0x71 311166676Sjkim#define BGE_CHIPREV_5700_CX 0x72 312166676Sjkim#define BGE_CHIPREV_5701_AX 0x00 313166676Sjkim#define BGE_CHIPREV_5703_AX 0x10 314166676Sjkim#define BGE_CHIPREV_5704_AX 0x20 315166676Sjkim#define BGE_CHIPREV_5704_BX 0x21 316166676Sjkim#define BGE_CHIPREV_5750_AX 0x40 317166676Sjkim#define BGE_CHIPREV_5750_BX 0x41 318114813Sps 31984059Swpaul/* PCI DMA Read/Write Control register */ 320166676Sjkim#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 321166676Sjkim#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 322166676Sjkim#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 323169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 324169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 325169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 326166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 327166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 328166676Sjkim#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 329166676Sjkim#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 330166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 331166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 33284059Swpaul 333166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 334166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 335166676Sjkim#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 336166676Sjkim#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 33784059Swpaul 338166676Sjkim#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 339166676Sjkim#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 340166676Sjkim#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 341166676Sjkim#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 342166676Sjkim#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 343166676Sjkim#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 344166676Sjkim#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 345166676Sjkim#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 34684059Swpaul 347166676Sjkim#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 348166676Sjkim#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 349166676Sjkim#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 350166676Sjkim#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 351166676Sjkim#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 352166676Sjkim#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 353166676Sjkim#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 354166676Sjkim#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 355166676Sjkim 35684059Swpaul/* 35784059Swpaul * PCI state register -- note, this register is read only 35884059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 35984059Swpaul * register is set. 36084059Swpaul */ 361166676Sjkim#define BGE_PCISTATE_FORCE_RESET 0x00000001 362166676Sjkim#define BGE_PCISTATE_INTR_STATE 0x00000002 363166676Sjkim#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 364166676Sjkim#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 365166676Sjkim#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 366166676Sjkim#define BGE_PCISTATE_WANT_EXPROM 0x00000020 367166676Sjkim#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 368166676Sjkim#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 369166676Sjkim#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 37084059Swpaul 37184059Swpaul/* 37284059Swpaul * PCI Clock Control register -- note, this register is read only 37384059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 37484059Swpaul * register is set. 37584059Swpaul */ 376166676Sjkim#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 377166676Sjkim#define BGE_PCICLOCKCTL_M66EN 0x00000080 378166676Sjkim#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 379166676Sjkim#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 380166676Sjkim#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 381166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 382166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 383166676Sjkim#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 384166676Sjkim#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 385166676Sjkim#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 38684059Swpaul 38784059Swpaul 38884059Swpaul#ifndef PCIM_CMD_MWIEN 389166676Sjkim#define PCIM_CMD_MWIEN 0x0010 39084059Swpaul#endif 39184059Swpaul 39284059Swpaul/* 39384059Swpaul * High priority mailbox registers 39484059Swpaul * Each mailbox is 64-bits wide, though we only use the 39584059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 39684059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 39784059Swpaul * has been updated. 39884059Swpaul */ 399166676Sjkim#define BGE_MBX_IRQ0_HI 0x0200 400166676Sjkim#define BGE_MBX_IRQ0_LO 0x0204 401166676Sjkim#define BGE_MBX_IRQ1_HI 0x0208 402166676Sjkim#define BGE_MBX_IRQ1_LO 0x020C 403166676Sjkim#define BGE_MBX_IRQ2_HI 0x0210 404166676Sjkim#define BGE_MBX_IRQ2_LO 0x0214 405166676Sjkim#define BGE_MBX_IRQ3_HI 0x0218 406166676Sjkim#define BGE_MBX_IRQ3_LO 0x021C 407166676Sjkim#define BGE_MBX_GEN0_HI 0x0220 408166676Sjkim#define BGE_MBX_GEN0_LO 0x0224 409166676Sjkim#define BGE_MBX_GEN1_HI 0x0228 410166676Sjkim#define BGE_MBX_GEN1_LO 0x022C 411166676Sjkim#define BGE_MBX_GEN2_HI 0x0230 412166676Sjkim#define BGE_MBX_GEN2_LO 0x0234 413166676Sjkim#define BGE_MBX_GEN3_HI 0x0228 414166676Sjkim#define BGE_MBX_GEN3_LO 0x022C 415166676Sjkim#define BGE_MBX_GEN4_HI 0x0240 416166676Sjkim#define BGE_MBX_GEN4_LO 0x0244 417166676Sjkim#define BGE_MBX_GEN5_HI 0x0248 418166676Sjkim#define BGE_MBX_GEN5_LO 0x024C 419166676Sjkim#define BGE_MBX_GEN6_HI 0x0250 420166676Sjkim#define BGE_MBX_GEN6_LO 0x0254 421166676Sjkim#define BGE_MBX_GEN7_HI 0x0258 422166676Sjkim#define BGE_MBX_GEN7_LO 0x025C 423166676Sjkim#define BGE_MBX_RELOAD_STATS_HI 0x0260 424166676Sjkim#define BGE_MBX_RELOAD_STATS_LO 0x0264 425166676Sjkim#define BGE_MBX_RX_STD_PROD_HI 0x0268 426166676Sjkim#define BGE_MBX_RX_STD_PROD_LO 0x026C 427166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 428166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 429166676Sjkim#define BGE_MBX_RX_MINI_PROD_HI 0x0278 430166676Sjkim#define BGE_MBX_RX_MINI_PROD_LO 0x027C 431166676Sjkim#define BGE_MBX_RX_CONS0_HI 0x0280 432166676Sjkim#define BGE_MBX_RX_CONS0_LO 0x0284 433166676Sjkim#define BGE_MBX_RX_CONS1_HI 0x0288 434166676Sjkim#define BGE_MBX_RX_CONS1_LO 0x028C 435166676Sjkim#define BGE_MBX_RX_CONS2_HI 0x0290 436166676Sjkim#define BGE_MBX_RX_CONS2_LO 0x0294 437166676Sjkim#define BGE_MBX_RX_CONS3_HI 0x0298 438166676Sjkim#define BGE_MBX_RX_CONS3_LO 0x029C 439166676Sjkim#define BGE_MBX_RX_CONS4_HI 0x02A0 440166676Sjkim#define BGE_MBX_RX_CONS4_LO 0x02A4 441166676Sjkim#define BGE_MBX_RX_CONS5_HI 0x02A8 442166676Sjkim#define BGE_MBX_RX_CONS5_LO 0x02AC 443166676Sjkim#define BGE_MBX_RX_CONS6_HI 0x02B0 444166676Sjkim#define BGE_MBX_RX_CONS6_LO 0x02B4 445166676Sjkim#define BGE_MBX_RX_CONS7_HI 0x02B8 446166676Sjkim#define BGE_MBX_RX_CONS7_LO 0x02BC 447166676Sjkim#define BGE_MBX_RX_CONS8_HI 0x02C0 448166676Sjkim#define BGE_MBX_RX_CONS8_LO 0x02C4 449166676Sjkim#define BGE_MBX_RX_CONS9_HI 0x02C8 450166676Sjkim#define BGE_MBX_RX_CONS9_LO 0x02CC 451166676Sjkim#define BGE_MBX_RX_CONS10_HI 0x02D0 452166676Sjkim#define BGE_MBX_RX_CONS10_LO 0x02D4 453166676Sjkim#define BGE_MBX_RX_CONS11_HI 0x02D8 454166676Sjkim#define BGE_MBX_RX_CONS11_LO 0x02DC 455166676Sjkim#define BGE_MBX_RX_CONS12_HI 0x02E0 456166676Sjkim#define BGE_MBX_RX_CONS12_LO 0x02E4 457166676Sjkim#define BGE_MBX_RX_CONS13_HI 0x02E8 458166676Sjkim#define BGE_MBX_RX_CONS13_LO 0x02EC 459166676Sjkim#define BGE_MBX_RX_CONS14_HI 0x02F0 460166676Sjkim#define BGE_MBX_RX_CONS14_LO 0x02F4 461166676Sjkim#define BGE_MBX_RX_CONS15_HI 0x02F8 462166676Sjkim#define BGE_MBX_RX_CONS15_LO 0x02FC 463166676Sjkim#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 464166676Sjkim#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 465166676Sjkim#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 466166676Sjkim#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 467166676Sjkim#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 468166676Sjkim#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 469166676Sjkim#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 470166676Sjkim#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 471166676Sjkim#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 472166676Sjkim#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 473166676Sjkim#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 474166676Sjkim#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 475166676Sjkim#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 476166676Sjkim#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 477166676Sjkim#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 478166676Sjkim#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 479166676Sjkim#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 480166676Sjkim#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 481166676Sjkim#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 482166676Sjkim#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 483166676Sjkim#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 484166676Sjkim#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 485166676Sjkim#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 486166676Sjkim#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 487166676Sjkim#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 488166676Sjkim#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 489166676Sjkim#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 490166676Sjkim#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 491166676Sjkim#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 492166676Sjkim#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 493166676Sjkim#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 494166676Sjkim#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 495166676Sjkim#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 496166676Sjkim#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 497166676Sjkim#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 498166676Sjkim#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 499166676Sjkim#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 500166676Sjkim#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 501166676Sjkim#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 502166676Sjkim#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 503166676Sjkim#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 504166676Sjkim#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 505166676Sjkim#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 506166676Sjkim#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 507166676Sjkim#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 508166676Sjkim#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 509166676Sjkim#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 510166676Sjkim#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 511166676Sjkim#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 512166676Sjkim#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 513166676Sjkim#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 514166676Sjkim#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 515166676Sjkim#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 516166676Sjkim#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 517166676Sjkim#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 518166676Sjkim#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 519166676Sjkim#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 520166676Sjkim#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 521166676Sjkim#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 522166676Sjkim#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 523166676Sjkim#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 524166676Sjkim#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 525166676Sjkim#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 526166676Sjkim#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 52784059Swpaul 528166676Sjkim#define BGE_TX_RINGS_MAX 4 529166676Sjkim#define BGE_TX_RINGS_EXTSSRAM_MAX 16 530166676Sjkim#define BGE_RX_RINGS_MAX 16 53184059Swpaul 53284059Swpaul/* Ethernet MAC control registers */ 533166676Sjkim#define BGE_MAC_MODE 0x0400 534166676Sjkim#define BGE_MAC_STS 0x0404 535166676Sjkim#define BGE_MAC_EVT_ENB 0x0408 536166676Sjkim#define BGE_MAC_LED_CTL 0x040C 537166676Sjkim#define BGE_MAC_ADDR1_LO 0x0410 538166676Sjkim#define BGE_MAC_ADDR1_HI 0x0414 539166676Sjkim#define BGE_MAC_ADDR2_LO 0x0418 540166676Sjkim#define BGE_MAC_ADDR2_HI 0x041C 541166676Sjkim#define BGE_MAC_ADDR3_LO 0x0420 542166676Sjkim#define BGE_MAC_ADDR3_HI 0x0424 543166676Sjkim#define BGE_MAC_ADDR4_LO 0x0428 544166676Sjkim#define BGE_MAC_ADDR4_HI 0x042C 545166676Sjkim#define BGE_WOL_PATPTR 0x0430 546166676Sjkim#define BGE_WOL_PATCFG 0x0434 547166676Sjkim#define BGE_TX_RANDOM_BACKOFF 0x0438 548166676Sjkim#define BGE_RX_MTU 0x043C 549166676Sjkim#define BGE_GBIT_PCS_TEST 0x0440 550166676Sjkim#define BGE_TX_TBI_AUTONEG 0x0444 551166676Sjkim#define BGE_RX_TBI_AUTONEG 0x0448 552166676Sjkim#define BGE_MI_COMM 0x044C 553166676Sjkim#define BGE_MI_STS 0x0450 554166676Sjkim#define BGE_MI_MODE 0x0454 555166676Sjkim#define BGE_AUTOPOLL_STS 0x0458 556166676Sjkim#define BGE_TX_MODE 0x045C 557166676Sjkim#define BGE_TX_STS 0x0460 558166676Sjkim#define BGE_TX_LENGTHS 0x0464 559166676Sjkim#define BGE_RX_MODE 0x0468 560166676Sjkim#define BGE_RX_STS 0x046C 561166676Sjkim#define BGE_MAR0 0x0470 562166676Sjkim#define BGE_MAR1 0x0474 563166676Sjkim#define BGE_MAR2 0x0478 564166676Sjkim#define BGE_MAR3 0x047C 565166676Sjkim#define BGE_RX_BD_RULES_CTL0 0x0480 566166676Sjkim#define BGE_RX_BD_RULES_MASKVAL0 0x0484 567166676Sjkim#define BGE_RX_BD_RULES_CTL1 0x0488 568166676Sjkim#define BGE_RX_BD_RULES_MASKVAL1 0x048C 569166676Sjkim#define BGE_RX_BD_RULES_CTL2 0x0490 570166676Sjkim#define BGE_RX_BD_RULES_MASKVAL2 0x0494 571166676Sjkim#define BGE_RX_BD_RULES_CTL3 0x0498 572166676Sjkim#define BGE_RX_BD_RULES_MASKVAL3 0x049C 573166676Sjkim#define BGE_RX_BD_RULES_CTL4 0x04A0 574166676Sjkim#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 575166676Sjkim#define BGE_RX_BD_RULES_CTL5 0x04A8 576166676Sjkim#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 577166676Sjkim#define BGE_RX_BD_RULES_CTL6 0x04B0 578166676Sjkim#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 579166676Sjkim#define BGE_RX_BD_RULES_CTL7 0x04B8 580166676Sjkim#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 581166676Sjkim#define BGE_RX_BD_RULES_CTL8 0x04C0 582166676Sjkim#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 583166676Sjkim#define BGE_RX_BD_RULES_CTL9 0x04C8 584166676Sjkim#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 585166676Sjkim#define BGE_RX_BD_RULES_CTL10 0x04D0 586166676Sjkim#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 587166676Sjkim#define BGE_RX_BD_RULES_CTL11 0x04D8 588166676Sjkim#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 589166676Sjkim#define BGE_RX_BD_RULES_CTL12 0x04E0 590166676Sjkim#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 591166676Sjkim#define BGE_RX_BD_RULES_CTL13 0x04E8 592166676Sjkim#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 593166676Sjkim#define BGE_RX_BD_RULES_CTL14 0x04F0 594166676Sjkim#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 595166676Sjkim#define BGE_RX_BD_RULES_CTL15 0x04F8 596166676Sjkim#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 597166676Sjkim#define BGE_RX_RULES_CFG 0x0500 598166676Sjkim#define BGE_SERDES_CFG 0x0590 599166676Sjkim#define BGE_SERDES_STS 0x0594 600166676Sjkim#define BGE_SGDIG_CFG 0x05B0 601166676Sjkim#define BGE_SGDIG_STS 0x05B4 602166676Sjkim#define BGE_MAC_STATS 0x0800 60384059Swpaul 60484059Swpaul/* Ethernet MAC Mode register */ 605166676Sjkim#define BGE_MACMODE_RESET 0x00000001 606166676Sjkim#define BGE_MACMODE_HALF_DUPLEX 0x00000002 607166676Sjkim#define BGE_MACMODE_PORTMODE 0x0000000C 608166676Sjkim#define BGE_MACMODE_LOOPBACK 0x00000010 609166676Sjkim#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 610166676Sjkim#define BGE_MACMODE_TX_BURST_ENB 0x00000100 611166676Sjkim#define BGE_MACMODE_MAX_DEFER 0x00000200 612166676Sjkim#define BGE_MACMODE_LINK_POLARITY 0x00000400 613166676Sjkim#define BGE_MACMODE_RX_STATS_ENB 0x00000800 614166676Sjkim#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 615166676Sjkim#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 616166676Sjkim#define BGE_MACMODE_TX_STATS_ENB 0x00004000 617166676Sjkim#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 618166676Sjkim#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 619166676Sjkim#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 620166676Sjkim#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 621166676Sjkim#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 622166676Sjkim#define BGE_MACMODE_MIP_ENB 0x00100000 623166676Sjkim#define BGE_MACMODE_TXDMA_ENB 0x00200000 624166676Sjkim#define BGE_MACMODE_RXDMA_ENB 0x00400000 625166676Sjkim#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 62684059Swpaul 627166676Sjkim#define BGE_PORTMODE_NONE 0x00000000 628166676Sjkim#define BGE_PORTMODE_MII 0x00000004 629166676Sjkim#define BGE_PORTMODE_GMII 0x00000008 630166676Sjkim#define BGE_PORTMODE_TBI 0x0000000C 63184059Swpaul 63284059Swpaul/* MAC Status register */ 633166676Sjkim#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 634166676Sjkim#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 635166676Sjkim#define BGE_MACSTAT_RX_CFG 0x00000004 636166676Sjkim#define BGE_MACSTAT_CFG_CHANGED 0x00000008 637166676Sjkim#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 638166676Sjkim#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 639166676Sjkim#define BGE_MACSTAT_LINK_CHANGED 0x00001000 640166676Sjkim#define BGE_MACSTAT_MI_COMPLETE 0x00400000 641166676Sjkim#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 642166676Sjkim#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 643166676Sjkim#define BGE_MACSTAT_ODI_ERROR 0x02000000 644166676Sjkim#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 645166676Sjkim#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 64684059Swpaul 64784059Swpaul/* MAC Event Enable Register */ 648166676Sjkim#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 649166676Sjkim#define BGE_EVTENB_LINK_CHANGED 0x00001000 650166676Sjkim#define BGE_EVTENB_MI_COMPLETE 0x00400000 651166676Sjkim#define BGE_EVTENB_MI_INTERRUPT 0x00800000 652166676Sjkim#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 653166676Sjkim#define BGE_EVTENB_ODI_ERROR 0x02000000 654166676Sjkim#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 655166676Sjkim#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 65684059Swpaul 65784059Swpaul/* LED Control Register */ 658166676Sjkim#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 659166676Sjkim#define BGE_LEDCTL_1000MBPS_LED 0x00000002 660166676Sjkim#define BGE_LEDCTL_100MBPS_LED 0x00000004 661166676Sjkim#define BGE_LEDCTL_10MBPS_LED 0x00000008 662166676Sjkim#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 663166676Sjkim#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 664166676Sjkim#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 665166676Sjkim#define BGE_LEDCTL_1000MBPS_STS 0x00000080 666166676Sjkim#define BGE_LEDCTL_100MBPS_STS 0x00000100 667166676Sjkim#define BGE_LEDCTL_10MBPS_STS 0x00000200 668166676Sjkim#define BGE_LEDCTL_TRADLED_STS 0x00000400 669166676Sjkim#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 670166676Sjkim#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 67184059Swpaul 67284059Swpaul/* TX backoff seed register */ 673166676Sjkim#define BGE_TX_BACKOFF_SEED_MASK 0x3F 67484059Swpaul 67584059Swpaul/* Autopoll status register */ 676166676Sjkim#define BGE_AUTOPOLLSTS_ERROR 0x00000001 67784059Swpaul 67884059Swpaul/* Transmit MAC mode register */ 679166676Sjkim#define BGE_TXMODE_RESET 0x00000001 680166676Sjkim#define BGE_TXMODE_ENABLE 0x00000002 681166676Sjkim#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 682166676Sjkim#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 683166676Sjkim#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 68484059Swpaul 68584059Swpaul/* Transmit MAC status register */ 686166676Sjkim#define BGE_TXSTAT_RX_XOFFED 0x00000001 687166676Sjkim#define BGE_TXSTAT_SENT_XOFF 0x00000002 688166676Sjkim#define BGE_TXSTAT_SENT_XON 0x00000004 689166676Sjkim#define BGE_TXSTAT_LINK_UP 0x00000008 690166676Sjkim#define BGE_TXSTAT_ODI_UFLOW 0x00000010 691166676Sjkim#define BGE_TXSTAT_ODI_OFLOW 0x00000020 69284059Swpaul 69384059Swpaul/* Transmit MAC lengths register */ 694166676Sjkim#define BGE_TXLEN_SLOTTIME 0x000000FF 695166676Sjkim#define BGE_TXLEN_IPG 0x00000F00 696166676Sjkim#define BGE_TXLEN_CRS 0x00003000 69784059Swpaul 69884059Swpaul/* Receive MAC mode register */ 699166676Sjkim#define BGE_RXMODE_RESET 0x00000001 700166676Sjkim#define BGE_RXMODE_ENABLE 0x00000002 701166676Sjkim#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 702166676Sjkim#define BGE_RXMODE_RX_GIANTS 0x00000020 703166676Sjkim#define BGE_RXMODE_RX_RUNTS 0x00000040 704166676Sjkim#define BGE_RXMODE_8022_LENCHECK 0x00000080 705166676Sjkim#define BGE_RXMODE_RX_PROMISC 0x00000100 706166676Sjkim#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 707166676Sjkim#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 70884059Swpaul 70984059Swpaul/* Receive MAC status register */ 710166676Sjkim#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 711166676Sjkim#define BGE_RXSTAT_RCVD_XOFF 0x00000002 712166676Sjkim#define BGE_RXSTAT_RCVD_XON 0x00000004 71384059Swpaul 71484059Swpaul/* Receive Rules Control register */ 715166676Sjkim#define BGE_RXRULECTL_OFFSET 0x000000FF 716166676Sjkim#define BGE_RXRULECTL_CLASS 0x00001F00 717166676Sjkim#define BGE_RXRULECTL_HDRTYPE 0x0000E000 718166676Sjkim#define BGE_RXRULECTL_COMPARE_OP 0x00030000 719166676Sjkim#define BGE_RXRULECTL_MAP 0x01000000 720166676Sjkim#define BGE_RXRULECTL_DISCARD 0x02000000 721166676Sjkim#define BGE_RXRULECTL_MASK 0x04000000 722166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 723166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 724166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 725166676Sjkim#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 72684059Swpaul 72784059Swpaul/* Receive Rules Mask register */ 728166676Sjkim#define BGE_RXRULEMASK_VALUE 0x0000FFFF 729166676Sjkim#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 73084059Swpaul 731130273Swpaul/* SERDES configuration register */ 732166676Sjkim#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 733166676Sjkim#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 734166676Sjkim#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 735166676Sjkim#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 736166676Sjkim#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 737166676Sjkim#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 738166676Sjkim#define BGE_SERDESCFG_TXMODE 0x00001000 739166676Sjkim#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 740166676Sjkim#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 741166676Sjkim#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 742166676Sjkim#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 743166676Sjkim#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 744166676Sjkim#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 745166676Sjkim#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 746166676Sjkim#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 747166676Sjkim#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 748130273Swpaul 749130273Swpaul/* SERDES status register */ 750166676Sjkim#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 751166676Sjkim#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 752130273Swpaul 753130273Swpaul/* SGDIG config (not documented) */ 754166676Sjkim#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 755166676Sjkim#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 756166676Sjkim#define BGE_SGDIGCFG_SEND 0x40000000 757166676Sjkim#define BGE_SGDIGCFG_AUTO 0x80000000 758130273Swpaul 759130273Swpaul/* SGDIG status (not documented) */ 760166676Sjkim#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 761166676Sjkim#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 762166676Sjkim#define BGE_SGDIGSTS_DONE 0x00000002 763130273Swpaul 764130273Swpaul 76584059Swpaul/* MI communication register */ 766166676Sjkim#define BGE_MICOMM_DATA 0x0000FFFF 767166676Sjkim#define BGE_MICOMM_REG 0x001F0000 768166676Sjkim#define BGE_MICOMM_PHY 0x03E00000 769166676Sjkim#define BGE_MICOMM_CMD 0x0C000000 770166676Sjkim#define BGE_MICOMM_READFAIL 0x10000000 771166676Sjkim#define BGE_MICOMM_BUSY 0x20000000 77284059Swpaul 773166676Sjkim#define BGE_MIREG(x) ((x & 0x1F) << 16) 774166676Sjkim#define BGE_MIPHY(x) ((x & 0x1F) << 21) 775166676Sjkim#define BGE_MICMD_WRITE 0x04000000 776166676Sjkim#define BGE_MICMD_READ 0x08000000 77784059Swpaul 77884059Swpaul/* MI status register */ 779166676Sjkim#define BGE_MISTS_LINK 0x00000001 780166676Sjkim#define BGE_MISTS_10MBPS 0x00000002 78184059Swpaul 782166676Sjkim#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 783166676Sjkim#define BGE_MIMODE_AUTOPOLL 0x00000010 784166676Sjkim#define BGE_MIMODE_CLKCNT 0x001F0000 78584059Swpaul 78684059Swpaul 78784059Swpaul/* 78884059Swpaul * Send data initiator control registers. 78984059Swpaul */ 790166676Sjkim#define BGE_SDI_MODE 0x0C00 791166676Sjkim#define BGE_SDI_STATUS 0x0C04 792166676Sjkim#define BGE_SDI_STATS_CTL 0x0C08 793166676Sjkim#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 794166676Sjkim#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 795166676Sjkim#define BGE_LOCSTATS_COS0 0x0C80 796166676Sjkim#define BGE_LOCSTATS_COS1 0x0C84 797166676Sjkim#define BGE_LOCSTATS_COS2 0x0C88 798166676Sjkim#define BGE_LOCSTATS_COS3 0x0C8C 799166676Sjkim#define BGE_LOCSTATS_COS4 0x0C90 800166676Sjkim#define BGE_LOCSTATS_COS5 0x0C84 801166676Sjkim#define BGE_LOCSTATS_COS6 0x0C98 802166676Sjkim#define BGE_LOCSTATS_COS7 0x0C9C 803166676Sjkim#define BGE_LOCSTATS_COS8 0x0CA0 804166676Sjkim#define BGE_LOCSTATS_COS9 0x0CA4 805166676Sjkim#define BGE_LOCSTATS_COS10 0x0CA8 806166676Sjkim#define BGE_LOCSTATS_COS11 0x0CAC 807166676Sjkim#define BGE_LOCSTATS_COS12 0x0CB0 808166676Sjkim#define BGE_LOCSTATS_COS13 0x0CB4 809166676Sjkim#define BGE_LOCSTATS_COS14 0x0CB8 810166676Sjkim#define BGE_LOCSTATS_COS15 0x0CBC 811166676Sjkim#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 812166676Sjkim#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 813166676Sjkim#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 814166676Sjkim#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 815166676Sjkim#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 816166676Sjkim#define BGE_LOCSTATS_IRQS 0x0CD4 817166676Sjkim#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 818166676Sjkim#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 81984059Swpaul 82084059Swpaul/* Send Data Initiator mode register */ 821166676Sjkim#define BGE_SDIMODE_RESET 0x00000001 822166676Sjkim#define BGE_SDIMODE_ENABLE 0x00000002 823166676Sjkim#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 82484059Swpaul 82584059Swpaul/* Send Data Initiator stats register */ 826166676Sjkim#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 82784059Swpaul 82884059Swpaul/* Send Data Initiator stats control register */ 829166676Sjkim#define BGE_SDISTATSCTL_ENABLE 0x00000001 830166676Sjkim#define BGE_SDISTATSCTL_FASTER 0x00000002 831166676Sjkim#define BGE_SDISTATSCTL_CLEAR 0x00000004 832166676Sjkim#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 833166676Sjkim#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 83484059Swpaul 83584059Swpaul/* 83684059Swpaul * Send Data Completion Control registers 83784059Swpaul */ 838166676Sjkim#define BGE_SDC_MODE 0x1000 839166676Sjkim#define BGE_SDC_STATUS 0x1004 84084059Swpaul 84184059Swpaul/* Send Data completion mode register */ 842166676Sjkim#define BGE_SDCMODE_RESET 0x00000001 843166676Sjkim#define BGE_SDCMODE_ENABLE 0x00000002 844166676Sjkim#define BGE_SDCMODE_ATTN 0x00000004 84584059Swpaul 84684059Swpaul/* Send Data completion status register */ 847166676Sjkim#define BGE_SDCSTAT_ATTN 0x00000004 84884059Swpaul 84984059Swpaul/* 85084059Swpaul * Send BD Ring Selector Control registers 85184059Swpaul */ 852166676Sjkim#define BGE_SRS_MODE 0x1400 853166676Sjkim#define BGE_SRS_STATUS 0x1404 854166676Sjkim#define BGE_SRS_HWDIAG 0x1408 855166676Sjkim#define BGE_SRS_LOC_NIC_CONS0 0x1440 856166676Sjkim#define BGE_SRS_LOC_NIC_CONS1 0x1444 857166676Sjkim#define BGE_SRS_LOC_NIC_CONS2 0x1448 858166676Sjkim#define BGE_SRS_LOC_NIC_CONS3 0x144C 859166676Sjkim#define BGE_SRS_LOC_NIC_CONS4 0x1450 860166676Sjkim#define BGE_SRS_LOC_NIC_CONS5 0x1454 861166676Sjkim#define BGE_SRS_LOC_NIC_CONS6 0x1458 862166676Sjkim#define BGE_SRS_LOC_NIC_CONS7 0x145C 863166676Sjkim#define BGE_SRS_LOC_NIC_CONS8 0x1460 864166676Sjkim#define BGE_SRS_LOC_NIC_CONS9 0x1464 865166676Sjkim#define BGE_SRS_LOC_NIC_CONS10 0x1468 866166676Sjkim#define BGE_SRS_LOC_NIC_CONS11 0x146C 867166676Sjkim#define BGE_SRS_LOC_NIC_CONS12 0x1470 868166676Sjkim#define BGE_SRS_LOC_NIC_CONS13 0x1474 869166676Sjkim#define BGE_SRS_LOC_NIC_CONS14 0x1478 870166676Sjkim#define BGE_SRS_LOC_NIC_CONS15 0x147C 87184059Swpaul 87284059Swpaul/* Send BD Ring Selector Mode register */ 873166676Sjkim#define BGE_SRSMODE_RESET 0x00000001 874166676Sjkim#define BGE_SRSMODE_ENABLE 0x00000002 875166676Sjkim#define BGE_SRSMODE_ATTN 0x00000004 87684059Swpaul 87784059Swpaul/* Send BD Ring Selector Status register */ 878166676Sjkim#define BGE_SRSSTAT_ERROR 0x00000004 87984059Swpaul 88084059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 881166676Sjkim#define BGE_SRSHWDIAG_STATE 0x0000000F 882166676Sjkim#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 883166676Sjkim#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 884166676Sjkim#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 88584059Swpaul 88684059Swpaul/* 88784059Swpaul * Send BD Initiator Selector Control registers 88884059Swpaul */ 889166676Sjkim#define BGE_SBDI_MODE 0x1800 890166676Sjkim#define BGE_SBDI_STATUS 0x1804 891166676Sjkim#define BGE_SBDI_LOC_NIC_PROD0 0x1808 892166676Sjkim#define BGE_SBDI_LOC_NIC_PROD1 0x180C 893166676Sjkim#define BGE_SBDI_LOC_NIC_PROD2 0x1810 894166676Sjkim#define BGE_SBDI_LOC_NIC_PROD3 0x1814 895166676Sjkim#define BGE_SBDI_LOC_NIC_PROD4 0x1818 896166676Sjkim#define BGE_SBDI_LOC_NIC_PROD5 0x181C 897166676Sjkim#define BGE_SBDI_LOC_NIC_PROD6 0x1820 898166676Sjkim#define BGE_SBDI_LOC_NIC_PROD7 0x1824 899166676Sjkim#define BGE_SBDI_LOC_NIC_PROD8 0x1828 900166676Sjkim#define BGE_SBDI_LOC_NIC_PROD9 0x182C 901166676Sjkim#define BGE_SBDI_LOC_NIC_PROD10 0x1830 902166676Sjkim#define BGE_SBDI_LOC_NIC_PROD11 0x1834 903166676Sjkim#define BGE_SBDI_LOC_NIC_PROD12 0x1838 904166676Sjkim#define BGE_SBDI_LOC_NIC_PROD13 0x183C 905166676Sjkim#define BGE_SBDI_LOC_NIC_PROD14 0x1840 906166676Sjkim#define BGE_SBDI_LOC_NIC_PROD15 0x1844 90784059Swpaul 90884059Swpaul/* Send BD Initiator Mode register */ 909166676Sjkim#define BGE_SBDIMODE_RESET 0x00000001 910166676Sjkim#define BGE_SBDIMODE_ENABLE 0x00000002 911166676Sjkim#define BGE_SBDIMODE_ATTN 0x00000004 91284059Swpaul 91384059Swpaul/* Send BD Initiator Status register */ 914166676Sjkim#define BGE_SBDISTAT_ERROR 0x00000004 91584059Swpaul 91684059Swpaul/* 91784059Swpaul * Send BD Completion Control registers 91884059Swpaul */ 919166676Sjkim#define BGE_SBDC_MODE 0x1C00 920166676Sjkim#define BGE_SBDC_STATUS 0x1C04 92184059Swpaul 92284059Swpaul/* Send BD Completion Control Mode register */ 923166676Sjkim#define BGE_SBDCMODE_RESET 0x00000001 924166676Sjkim#define BGE_SBDCMODE_ENABLE 0x00000002 925166676Sjkim#define BGE_SBDCMODE_ATTN 0x00000004 92684059Swpaul 92784059Swpaul/* Send BD Completion Control Status register */ 928166676Sjkim#define BGE_SBDCSTAT_ATTN 0x00000004 92984059Swpaul 93084059Swpaul/* 93184059Swpaul * Receive List Placement Control registers 93284059Swpaul */ 933166676Sjkim#define BGE_RXLP_MODE 0x2000 934166676Sjkim#define BGE_RXLP_STATUS 0x2004 935166676Sjkim#define BGE_RXLP_SEL_LIST_LOCK 0x2008 936166676Sjkim#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 937166676Sjkim#define BGE_RXLP_CFG 0x2010 938166676Sjkim#define BGE_RXLP_STATS_CTL 0x2014 939166676Sjkim#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 940166676Sjkim#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 941166676Sjkim#define BGE_RXLP_HEAD0 0x2100 942166676Sjkim#define BGE_RXLP_TAIL0 0x2104 943166676Sjkim#define BGE_RXLP_COUNT0 0x2108 944166676Sjkim#define BGE_RXLP_HEAD1 0x2110 945166676Sjkim#define BGE_RXLP_TAIL1 0x2114 946166676Sjkim#define BGE_RXLP_COUNT1 0x2118 947166676Sjkim#define BGE_RXLP_HEAD2 0x2120 948166676Sjkim#define BGE_RXLP_TAIL2 0x2124 949166676Sjkim#define BGE_RXLP_COUNT2 0x2128 950166676Sjkim#define BGE_RXLP_HEAD3 0x2130 951166676Sjkim#define BGE_RXLP_TAIL3 0x2134 952166676Sjkim#define BGE_RXLP_COUNT3 0x2138 953166676Sjkim#define BGE_RXLP_HEAD4 0x2140 954166676Sjkim#define BGE_RXLP_TAIL4 0x2144 955166676Sjkim#define BGE_RXLP_COUNT4 0x2148 956166676Sjkim#define BGE_RXLP_HEAD5 0x2150 957166676Sjkim#define BGE_RXLP_TAIL5 0x2154 958166676Sjkim#define BGE_RXLP_COUNT5 0x2158 959166676Sjkim#define BGE_RXLP_HEAD6 0x2160 960166676Sjkim#define BGE_RXLP_TAIL6 0x2164 961166676Sjkim#define BGE_RXLP_COUNT6 0x2168 962166676Sjkim#define BGE_RXLP_HEAD7 0x2170 963166676Sjkim#define BGE_RXLP_TAIL7 0x2174 964166676Sjkim#define BGE_RXLP_COUNT7 0x2178 965166676Sjkim#define BGE_RXLP_HEAD8 0x2180 966166676Sjkim#define BGE_RXLP_TAIL8 0x2184 967166676Sjkim#define BGE_RXLP_COUNT8 0x2188 968166676Sjkim#define BGE_RXLP_HEAD9 0x2190 969166676Sjkim#define BGE_RXLP_TAIL9 0x2194 970166676Sjkim#define BGE_RXLP_COUNT9 0x2198 971166676Sjkim#define BGE_RXLP_HEAD10 0x21A0 972166676Sjkim#define BGE_RXLP_TAIL10 0x21A4 973166676Sjkim#define BGE_RXLP_COUNT10 0x21A8 974166676Sjkim#define BGE_RXLP_HEAD11 0x21B0 975166676Sjkim#define BGE_RXLP_TAIL11 0x21B4 976166676Sjkim#define BGE_RXLP_COUNT11 0x21B8 977166676Sjkim#define BGE_RXLP_HEAD12 0x21C0 978166676Sjkim#define BGE_RXLP_TAIL12 0x21C4 979166676Sjkim#define BGE_RXLP_COUNT12 0x21C8 980166676Sjkim#define BGE_RXLP_HEAD13 0x21D0 981166676Sjkim#define BGE_RXLP_TAIL13 0x21D4 982166676Sjkim#define BGE_RXLP_COUNT13 0x21D8 983166676Sjkim#define BGE_RXLP_HEAD14 0x21E0 984166676Sjkim#define BGE_RXLP_TAIL14 0x21E4 985166676Sjkim#define BGE_RXLP_COUNT14 0x21E8 986166676Sjkim#define BGE_RXLP_HEAD15 0x21F0 987166676Sjkim#define BGE_RXLP_TAIL15 0x21F4 988166676Sjkim#define BGE_RXLP_COUNT15 0x21F8 989166676Sjkim#define BGE_RXLP_LOCSTAT_COS0 0x2200 990166676Sjkim#define BGE_RXLP_LOCSTAT_COS1 0x2204 991166676Sjkim#define BGE_RXLP_LOCSTAT_COS2 0x2208 992166676Sjkim#define BGE_RXLP_LOCSTAT_COS3 0x220C 993166676Sjkim#define BGE_RXLP_LOCSTAT_COS4 0x2210 994166676Sjkim#define BGE_RXLP_LOCSTAT_COS5 0x2214 995166676Sjkim#define BGE_RXLP_LOCSTAT_COS6 0x2218 996166676Sjkim#define BGE_RXLP_LOCSTAT_COS7 0x221C 997166676Sjkim#define BGE_RXLP_LOCSTAT_COS8 0x2220 998166676Sjkim#define BGE_RXLP_LOCSTAT_COS9 0x2224 999166676Sjkim#define BGE_RXLP_LOCSTAT_COS10 0x2228 1000166676Sjkim#define BGE_RXLP_LOCSTAT_COS11 0x222C 1001166676Sjkim#define BGE_RXLP_LOCSTAT_COS12 0x2230 1002166676Sjkim#define BGE_RXLP_LOCSTAT_COS13 0x2234 1003166676Sjkim#define BGE_RXLP_LOCSTAT_COS14 0x2238 1004166676Sjkim#define BGE_RXLP_LOCSTAT_COS15 0x223C 1005166676Sjkim#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1006166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1007166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1008166676Sjkim#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1009166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1010166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1011166676Sjkim#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 101284059Swpaul 101384059Swpaul 101484059Swpaul/* Receive List Placement mode register */ 1015166676Sjkim#define BGE_RXLPMODE_RESET 0x00000001 1016166676Sjkim#define BGE_RXLPMODE_ENABLE 0x00000002 1017166676Sjkim#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1018166676Sjkim#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1019166676Sjkim#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 102084059Swpaul 102184059Swpaul/* Receive List Placement Status register */ 1022166676Sjkim#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1023166676Sjkim#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1024166676Sjkim#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 102584059Swpaul 102684059Swpaul/* 102784059Swpaul * Receive Data and Receive BD Initiator Control Registers 102884059Swpaul */ 1029166676Sjkim#define BGE_RDBDI_MODE 0x2400 1030166676Sjkim#define BGE_RDBDI_STATUS 0x2404 1031166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1032166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1033166676Sjkim#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1034166676Sjkim#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1035166676Sjkim#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1036166676Sjkim#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1037166676Sjkim#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1038166676Sjkim#define BGE_RX_STD_RCB_NICADDR 0x245C 1039166676Sjkim#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1040166676Sjkim#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1041166676Sjkim#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1042166676Sjkim#define BGE_RX_MINI_RCB_NICADDR 0x246C 1043166676Sjkim#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1044166676Sjkim#define BGE_RDBDI_STD_RX_CONS 0x2474 1045166676Sjkim#define BGE_RDBDI_MINI_RX_CONS 0x2478 1046166676Sjkim#define BGE_RDBDI_RETURN_PROD0 0x2480 1047166676Sjkim#define BGE_RDBDI_RETURN_PROD1 0x2484 1048166676Sjkim#define BGE_RDBDI_RETURN_PROD2 0x2488 1049166676Sjkim#define BGE_RDBDI_RETURN_PROD3 0x248C 1050166676Sjkim#define BGE_RDBDI_RETURN_PROD4 0x2490 1051166676Sjkim#define BGE_RDBDI_RETURN_PROD5 0x2494 1052166676Sjkim#define BGE_RDBDI_RETURN_PROD6 0x2498 1053166676Sjkim#define BGE_RDBDI_RETURN_PROD7 0x249C 1054166676Sjkim#define BGE_RDBDI_RETURN_PROD8 0x24A0 1055166676Sjkim#define BGE_RDBDI_RETURN_PROD9 0x24A4 1056166676Sjkim#define BGE_RDBDI_RETURN_PROD10 0x24A8 1057166676Sjkim#define BGE_RDBDI_RETURN_PROD11 0x24AC 1058166676Sjkim#define BGE_RDBDI_RETURN_PROD12 0x24B0 1059166676Sjkim#define BGE_RDBDI_RETURN_PROD13 0x24B4 1060166676Sjkim#define BGE_RDBDI_RETURN_PROD14 0x24B8 1061166676Sjkim#define BGE_RDBDI_RETURN_PROD15 0x24BC 1062166676Sjkim#define BGE_RDBDI_HWDIAG 0x24C0 106384059Swpaul 106484059Swpaul 106584059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 1066166676Sjkim#define BGE_RDBDIMODE_RESET 0x00000001 1067166676Sjkim#define BGE_RDBDIMODE_ENABLE 0x00000002 1068166676Sjkim#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1069166676Sjkim#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1070166676Sjkim#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 107184059Swpaul 107284059Swpaul/* Receive Data and Receive BD Initiator Status register */ 1073166676Sjkim#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1074166676Sjkim#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1075166676Sjkim#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 107684059Swpaul 107784059Swpaul 107884059Swpaul/* 107984059Swpaul * Receive Data Completion Control registers 108084059Swpaul */ 1081166676Sjkim#define BGE_RDC_MODE 0x2800 108284059Swpaul 108384059Swpaul/* Receive Data Completion Mode register */ 1084166676Sjkim#define BGE_RDCMODE_RESET 0x00000001 1085166676Sjkim#define BGE_RDCMODE_ENABLE 0x00000002 1086166676Sjkim#define BGE_RDCMODE_ATTN 0x00000004 108784059Swpaul 108884059Swpaul/* 108984059Swpaul * Receive BD Initiator Control registers 109084059Swpaul */ 1091166676Sjkim#define BGE_RBDI_MODE 0x2C00 1092166676Sjkim#define BGE_RBDI_STATUS 0x2C04 1093166676Sjkim#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1094166676Sjkim#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1095166676Sjkim#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1096166676Sjkim#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1097166676Sjkim#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1098166676Sjkim#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 109984059Swpaul 110084059Swpaul/* Receive BD Initiator Mode register */ 1101166676Sjkim#define BGE_RBDIMODE_RESET 0x00000001 1102166676Sjkim#define BGE_RBDIMODE_ENABLE 0x00000002 1103166676Sjkim#define BGE_RBDIMODE_ATTN 0x00000004 110484059Swpaul 110584059Swpaul/* Receive BD Initiator Status register */ 1106166676Sjkim#define BGE_RBDISTAT_ATTN 0x00000004 110784059Swpaul 110884059Swpaul/* 110984059Swpaul * Receive BD Completion Control registers 111084059Swpaul */ 1111166676Sjkim#define BGE_RBDC_MODE 0x3000 1112166676Sjkim#define BGE_RBDC_STATUS 0x3004 1113166676Sjkim#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1114166676Sjkim#define BGE_RBDC_STD_BD_PROD 0x300C 1115166676Sjkim#define BGE_RBDC_MINI_BD_PROD 0x3010 111684059Swpaul 111784059Swpaul/* Receive BD completion mode register */ 1118166676Sjkim#define BGE_RBDCMODE_RESET 0x00000001 1119166676Sjkim#define BGE_RBDCMODE_ENABLE 0x00000002 1120166676Sjkim#define BGE_RBDCMODE_ATTN 0x00000004 112184059Swpaul 112284059Swpaul/* Receive BD completion status register */ 1123166676Sjkim#define BGE_RBDCSTAT_ERROR 0x00000004 112484059Swpaul 112584059Swpaul/* 112684059Swpaul * Receive List Selector Control registers 112784059Swpaul */ 1128166676Sjkim#define BGE_RXLS_MODE 0x3400 1129166676Sjkim#define BGE_RXLS_STATUS 0x3404 113084059Swpaul 113184059Swpaul/* Receive List Selector Mode register */ 1132166676Sjkim#define BGE_RXLSMODE_RESET 0x00000001 1133166676Sjkim#define BGE_RXLSMODE_ENABLE 0x00000002 1134166676Sjkim#define BGE_RXLSMODE_ATTN 0x00000004 113584059Swpaul 113684059Swpaul/* Receive List Selector Status register */ 1137166676Sjkim#define BGE_RXLSSTAT_ERROR 0x00000004 113884059Swpaul 113984059Swpaul/* 114084059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 114184059Swpaul */ 1142166676Sjkim#define BGE_MBCF_MODE 0x3800 1143166676Sjkim#define BGE_MBCF_STATUS 0x3804 114484059Swpaul 114584059Swpaul/* Mbuf Cluster Free mode register */ 1146166676Sjkim#define BGE_MBCFMODE_RESET 0x00000001 1147166676Sjkim#define BGE_MBCFMODE_ENABLE 0x00000002 1148166676Sjkim#define BGE_MBCFMODE_ATTN 0x00000004 114984059Swpaul 115084059Swpaul/* Mbuf Cluster Free status register */ 1151166676Sjkim#define BGE_MBCFSTAT_ERROR 0x00000004 115284059Swpaul 115384059Swpaul/* 115484059Swpaul * Host Coalescing Control registers 115584059Swpaul */ 1156166676Sjkim#define BGE_HCC_MODE 0x3C00 1157166676Sjkim#define BGE_HCC_STATUS 0x3C04 1158166676Sjkim#define BGE_HCC_RX_COAL_TICKS 0x3C08 1159166676Sjkim#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1160166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1161166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1162166676Sjkim#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1163166676Sjkim#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1164166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1165166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1166166676Sjkim#define BGE_HCC_STATS_TICKS 0x3C28 1167166676Sjkim#define BGE_HCC_STATS_ADDR_HI 0x3C30 1168166676Sjkim#define BGE_HCC_STATS_ADDR_LO 0x3C34 1169166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1170166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1171166676Sjkim#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1172166676Sjkim#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1173166676Sjkim#define BGE_FLOW_ATTN 0x3C48 1174166676Sjkim#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1175166676Sjkim#define BGE_HCC_STD_BD_CONS 0x3C54 1176166676Sjkim#define BGE_HCC_MINI_BD_CONS 0x3C58 1177166676Sjkim#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1178166676Sjkim#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1179166676Sjkim#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1180166676Sjkim#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1181166676Sjkim#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1182166676Sjkim#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1183166676Sjkim#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1184166676Sjkim#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1185166676Sjkim#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1186166676Sjkim#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1187166676Sjkim#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1188166676Sjkim#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1189166676Sjkim#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1190166676Sjkim#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1191166676Sjkim#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1192166676Sjkim#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1193166676Sjkim#define BGE_HCC_TX_BD_CONS0 0x3CC0 1194166676Sjkim#define BGE_HCC_TX_BD_CONS1 0x3CC4 1195166676Sjkim#define BGE_HCC_TX_BD_CONS2 0x3CC8 1196166676Sjkim#define BGE_HCC_TX_BD_CONS3 0x3CCC 1197166676Sjkim#define BGE_HCC_TX_BD_CONS4 0x3CD0 1198166676Sjkim#define BGE_HCC_TX_BD_CONS5 0x3CD4 1199166676Sjkim#define BGE_HCC_TX_BD_CONS6 0x3CD8 1200166676Sjkim#define BGE_HCC_TX_BD_CONS7 0x3CDC 1201166676Sjkim#define BGE_HCC_TX_BD_CONS8 0x3CE0 1202166676Sjkim#define BGE_HCC_TX_BD_CONS9 0x3CE4 1203166676Sjkim#define BGE_HCC_TX_BD_CONS10 0x3CE8 1204166676Sjkim#define BGE_HCC_TX_BD_CONS11 0x3CEC 1205166676Sjkim#define BGE_HCC_TX_BD_CONS12 0x3CF0 1206166676Sjkim#define BGE_HCC_TX_BD_CONS13 0x3CF4 1207166676Sjkim#define BGE_HCC_TX_BD_CONS14 0x3CF8 1208166676Sjkim#define BGE_HCC_TX_BD_CONS15 0x3CFC 120984059Swpaul 121084059Swpaul 121184059Swpaul/* Host coalescing mode register */ 1212166676Sjkim#define BGE_HCCMODE_RESET 0x00000001 1213166676Sjkim#define BGE_HCCMODE_ENABLE 0x00000002 1214166676Sjkim#define BGE_HCCMODE_ATTN 0x00000004 1215166676Sjkim#define BGE_HCCMODE_COAL_NOW 0x00000008 1216166676Sjkim#define BGE_HCCMODE_MSI_BITS 0x00000070 1217166676Sjkim#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 121884059Swpaul 1219166676Sjkim#define BGE_STATBLKSZ_FULL 0x00000000 1220166676Sjkim#define BGE_STATBLKSZ_64BYTE 0x00000080 1221166676Sjkim#define BGE_STATBLKSZ_32BYTE 0x00000100 122284059Swpaul 122384059Swpaul/* Host coalescing status register */ 1224166676Sjkim#define BGE_HCCSTAT_ERROR 0x00000004 122584059Swpaul 122684059Swpaul/* Flow attention register */ 1227166676Sjkim#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1228166676Sjkim#define BGE_FLOWATTN_MEMARB 0x00000080 1229166676Sjkim#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1230166676Sjkim#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1231166676Sjkim#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1232166676Sjkim#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1233166676Sjkim#define BGE_FLOWATTN_RDBDI 0x00080000 1234166676Sjkim#define BGE_FLOWATTN_RXLS 0x00100000 1235166676Sjkim#define BGE_FLOWATTN_RXLP 0x00200000 1236166676Sjkim#define BGE_FLOWATTN_RBDC 0x00400000 1237166676Sjkim#define BGE_FLOWATTN_RBDI 0x00800000 1238166676Sjkim#define BGE_FLOWATTN_SDC 0x08000000 1239166676Sjkim#define BGE_FLOWATTN_SDI 0x10000000 1240166676Sjkim#define BGE_FLOWATTN_SRS 0x20000000 1241166676Sjkim#define BGE_FLOWATTN_SBDC 0x40000000 1242166676Sjkim#define BGE_FLOWATTN_SBDI 0x80000000 124384059Swpaul 124484059Swpaul/* 124584059Swpaul * Memory arbiter registers 124684059Swpaul */ 1247166676Sjkim#define BGE_MARB_MODE 0x4000 1248166676Sjkim#define BGE_MARB_STATUS 0x4004 1249166676Sjkim#define BGE_MARB_TRAPADDR_HI 0x4008 1250166676Sjkim#define BGE_MARB_TRAPADDR_LO 0x400C 125184059Swpaul 125284059Swpaul/* Memory arbiter mode register */ 1253166676Sjkim#define BGE_MARBMODE_RESET 0x00000001 1254166676Sjkim#define BGE_MARBMODE_ENABLE 0x00000002 1255166676Sjkim#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1256166676Sjkim#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1257166676Sjkim#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1258166676Sjkim#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1259166676Sjkim#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1260166676Sjkim#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1261166676Sjkim#define BGE_MARBMODE_PCI_TRAP 0x00000100 1262166676Sjkim#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1263166676Sjkim#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1264166676Sjkim#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1265166676Sjkim#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1266166676Sjkim#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1267166676Sjkim#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1268166676Sjkim#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1269166676Sjkim#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1270166676Sjkim#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1271166676Sjkim#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1272166676Sjkim#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1273166676Sjkim#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1274166676Sjkim#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1275166676Sjkim#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1276166676Sjkim#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1277166676Sjkim#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1278166676Sjkim#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 127984059Swpaul 128084059Swpaul/* Memory arbiter status register */ 1281166676Sjkim#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1282166676Sjkim#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1283166676Sjkim#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1284166676Sjkim#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1285166676Sjkim#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1286166676Sjkim#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1287166676Sjkim#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1288166676Sjkim#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1289166676Sjkim#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1290166676Sjkim#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1291166676Sjkim#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1292166676Sjkim#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1293166676Sjkim#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1294166676Sjkim#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1295166676Sjkim#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1296166676Sjkim#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1297166676Sjkim#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1298166676Sjkim#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1299166676Sjkim#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1300166676Sjkim#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1301166676Sjkim#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1302166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1303166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1304166676Sjkim#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 130584059Swpaul 130684059Swpaul/* 130784059Swpaul * Buffer manager control registers 130884059Swpaul */ 1309166676Sjkim#define BGE_BMAN_MODE 0x4400 1310166676Sjkim#define BGE_BMAN_STATUS 0x4404 1311166676Sjkim#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1312166676Sjkim#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1313166676Sjkim#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1314166676Sjkim#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1315166676Sjkim#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1316166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1317166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1318166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1319166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1320166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1321166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1322166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1323166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1324166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1325166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1326166676Sjkim#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1327166676Sjkim#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1328166676Sjkim#define BGE_BMAN_HWDIAG_1 0x444C 1329166676Sjkim#define BGE_BMAN_HWDIAG_2 0x4450 1330166676Sjkim#define BGE_BMAN_HWDIAG_3 0x4454 133184059Swpaul 133284059Swpaul/* Buffer manager mode register */ 1333166676Sjkim#define BGE_BMANMODE_RESET 0x00000001 1334166676Sjkim#define BGE_BMANMODE_ENABLE 0x00000002 1335166676Sjkim#define BGE_BMANMODE_ATTN 0x00000004 1336166676Sjkim#define BGE_BMANMODE_TESTMODE 0x00000008 1337166676Sjkim#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 133884059Swpaul 133984059Swpaul/* Buffer manager status register */ 1340166676Sjkim#define BGE_BMANSTAT_ERRO 0x00000004 1341166676Sjkim#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 134284059Swpaul 134384059Swpaul 134484059Swpaul/* 134584059Swpaul * Read DMA Control registers 134684059Swpaul */ 1347166676Sjkim#define BGE_RDMA_MODE 0x4800 1348166676Sjkim#define BGE_RDMA_STATUS 0x4804 134984059Swpaul 135084059Swpaul/* Read DMA mode register */ 1351166676Sjkim#define BGE_RDMAMODE_RESET 0x00000001 1352166676Sjkim#define BGE_RDMAMODE_ENABLE 0x00000002 1353166676Sjkim#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1354166676Sjkim#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1355166676Sjkim#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1356166676Sjkim#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1357166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1358166676Sjkim#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1359166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1360166676Sjkim#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1361166676Sjkim#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 136284059Swpaul 136384059Swpaul/* Read DMA status register */ 1364166676Sjkim#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1365166676Sjkim#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1366166676Sjkim#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1367166676Sjkim#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1368166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1369166676Sjkim#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1370166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1371166676Sjkim#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 137284059Swpaul 137384059Swpaul/* 137484059Swpaul * Write DMA control registers 137584059Swpaul */ 1376166676Sjkim#define BGE_WDMA_MODE 0x4C00 1377166676Sjkim#define BGE_WDMA_STATUS 0x4C04 137884059Swpaul 137984059Swpaul/* Write DMA mode register */ 1380166676Sjkim#define BGE_WDMAMODE_RESET 0x00000001 1381166676Sjkim#define BGE_WDMAMODE_ENABLE 0x00000002 1382166676Sjkim#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1383166676Sjkim#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1384166676Sjkim#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1385166676Sjkim#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1386166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1387166676Sjkim#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1388166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1389166676Sjkim#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1390166676Sjkim#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 139184059Swpaul 139284059Swpaul/* Write DMA status register */ 1393166676Sjkim#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1394166676Sjkim#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1395166676Sjkim#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1396166676Sjkim#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1397166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1398166676Sjkim#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1399166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1400166676Sjkim#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 140184059Swpaul 140284059Swpaul 140384059Swpaul/* 140484059Swpaul * RX CPU registers 140584059Swpaul */ 1406166676Sjkim#define BGE_RXCPU_MODE 0x5000 1407166676Sjkim#define BGE_RXCPU_STATUS 0x5004 1408166676Sjkim#define BGE_RXCPU_PC 0x501C 140984059Swpaul 141084059Swpaul/* RX CPU mode register */ 1411166676Sjkim#define BGE_RXCPUMODE_RESET 0x00000001 1412166676Sjkim#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1413166676Sjkim#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1414166676Sjkim#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1415166676Sjkim#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1416166676Sjkim#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1417166676Sjkim#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1418166676Sjkim#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1419166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1420166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1421166676Sjkim#define BGE_RXCPUMODE_HALTCPU 0x00000400 1422166676Sjkim#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1423166676Sjkim#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1424166676Sjkim#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 142584059Swpaul 142684059Swpaul/* RX CPU status register */ 1427166676Sjkim#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1428166676Sjkim#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1429166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1430166676Sjkim#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1431166676Sjkim#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1432166676Sjkim#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1433166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1434166676Sjkim#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1435166676Sjkim#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1436166676Sjkim#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1437166676Sjkim#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1438166676Sjkim#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1439166676Sjkim#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1440166676Sjkim#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1441166676Sjkim#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1442166676Sjkim#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1443166676Sjkim#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 144484059Swpaul 1445178667Sjhb/* 1446178667Sjhb * V? CPU registers 1447178667Sjhb */ 1448178667Sjhb#define BGE_VCPU_STATUS 0x5100 1449178667Sjhb#define BGE_VCPU_EXT_CTRL 0x6890 145084059Swpaul 1451178667Sjhb#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1452178667Sjhb#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1453178667Sjhb 1454178667Sjhb#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1455178667Sjhb#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1456178667Sjhb 145784059Swpaul/* 145884059Swpaul * TX CPU registers 145984059Swpaul */ 1460166676Sjkim#define BGE_TXCPU_MODE 0x5400 1461166676Sjkim#define BGE_TXCPU_STATUS 0x5404 1462166676Sjkim#define BGE_TXCPU_PC 0x541C 146384059Swpaul 146484059Swpaul/* TX CPU mode register */ 1465166676Sjkim#define BGE_TXCPUMODE_RESET 0x00000001 1466166676Sjkim#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1467166676Sjkim#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1468166676Sjkim#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1469166676Sjkim#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1470166676Sjkim#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1471166676Sjkim#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1472166676Sjkim#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1473166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1474166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1475166676Sjkim#define BGE_TXCPUMODE_HALTCPU 0x00000400 1476166676Sjkim#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1477166676Sjkim#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 147884059Swpaul 147984059Swpaul/* TX CPU status register */ 1480166676Sjkim#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1481166676Sjkim#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1482166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1483166676Sjkim#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1484166676Sjkim#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1485166676Sjkim#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1486166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1487166676Sjkim#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1488166676Sjkim#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1489166676Sjkim#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1490166676Sjkim#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1491166676Sjkim#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1492166676Sjkim#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1493166676Sjkim#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1494166676Sjkim#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1495166676Sjkim#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1496166676Sjkim#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 149784059Swpaul 149884059Swpaul 149984059Swpaul/* 150084059Swpaul * Low priority mailbox registers 150184059Swpaul */ 1502166676Sjkim#define BGE_LPMBX_IRQ0_HI 0x5800 1503166676Sjkim#define BGE_LPMBX_IRQ0_LO 0x5804 1504166676Sjkim#define BGE_LPMBX_IRQ1_HI 0x5808 1505166676Sjkim#define BGE_LPMBX_IRQ1_LO 0x580C 1506166676Sjkim#define BGE_LPMBX_IRQ2_HI 0x5810 1507166676Sjkim#define BGE_LPMBX_IRQ2_LO 0x5814 1508166676Sjkim#define BGE_LPMBX_IRQ3_HI 0x5818 1509166676Sjkim#define BGE_LPMBX_IRQ3_LO 0x581C 1510166676Sjkim#define BGE_LPMBX_GEN0_HI 0x5820 1511166676Sjkim#define BGE_LPMBX_GEN0_LO 0x5824 1512166676Sjkim#define BGE_LPMBX_GEN1_HI 0x5828 1513166676Sjkim#define BGE_LPMBX_GEN1_LO 0x582C 1514166676Sjkim#define BGE_LPMBX_GEN2_HI 0x5830 1515166676Sjkim#define BGE_LPMBX_GEN2_LO 0x5834 1516166676Sjkim#define BGE_LPMBX_GEN3_HI 0x5828 1517166676Sjkim#define BGE_LPMBX_GEN3_LO 0x582C 1518166676Sjkim#define BGE_LPMBX_GEN4_HI 0x5840 1519166676Sjkim#define BGE_LPMBX_GEN4_LO 0x5844 1520166676Sjkim#define BGE_LPMBX_GEN5_HI 0x5848 1521166676Sjkim#define BGE_LPMBX_GEN5_LO 0x584C 1522166676Sjkim#define BGE_LPMBX_GEN6_HI 0x5850 1523166676Sjkim#define BGE_LPMBX_GEN6_LO 0x5854 1524166676Sjkim#define BGE_LPMBX_GEN7_HI 0x5858 1525166676Sjkim#define BGE_LPMBX_GEN7_LO 0x585C 1526166676Sjkim#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1527166676Sjkim#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1528166676Sjkim#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1529166676Sjkim#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1530166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1531166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1532166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1533166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1534166676Sjkim#define BGE_LPMBX_RX_CONS0_HI 0x5880 1535166676Sjkim#define BGE_LPMBX_RX_CONS0_LO 0x5884 1536166676Sjkim#define BGE_LPMBX_RX_CONS1_HI 0x5888 1537166676Sjkim#define BGE_LPMBX_RX_CONS1_LO 0x588C 1538166676Sjkim#define BGE_LPMBX_RX_CONS2_HI 0x5890 1539166676Sjkim#define BGE_LPMBX_RX_CONS2_LO 0x5894 1540166676Sjkim#define BGE_LPMBX_RX_CONS3_HI 0x5898 1541166676Sjkim#define BGE_LPMBX_RX_CONS3_LO 0x589C 1542166676Sjkim#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1543166676Sjkim#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1544166676Sjkim#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1545166676Sjkim#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1546166676Sjkim#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1547166676Sjkim#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1548166676Sjkim#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1549166676Sjkim#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1550166676Sjkim#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1551166676Sjkim#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1552166676Sjkim#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1553166676Sjkim#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1554166676Sjkim#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1555166676Sjkim#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1556166676Sjkim#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1557166676Sjkim#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1558166676Sjkim#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1559166676Sjkim#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1560166676Sjkim#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1561166676Sjkim#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1562166676Sjkim#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1563166676Sjkim#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1564166676Sjkim#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1565166676Sjkim#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1566166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1567166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1568166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1569166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1570166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1571166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1572166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1573166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1574166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1575166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1576166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1577166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1578166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1579166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1580166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1581166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1582166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1583166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1584166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1585166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1586166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1587166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1588166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1589166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1590166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1591166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1592166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1593166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1594166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1595166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1596166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1597166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1598166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1599166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1600166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1601166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1602166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1603166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1604166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1605166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1606166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1607166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1608166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1609166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1610166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1611166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1612166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1613166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1614166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1615166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1616166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1617166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1618166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1619166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1620166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1621166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1622166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1623166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1624166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1625166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1626166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1627166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1628166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1629166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 163084059Swpaul 163184059Swpaul/* 163284059Swpaul * Flow throw Queue reset register 163384059Swpaul */ 1634166676Sjkim#define BGE_FTQ_RESET 0x5C00 163584059Swpaul 1636166676Sjkim#define BGE_FTQRESET_DMAREAD 0x00000002 1637166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1638166676Sjkim#define BGE_FTQRESET_DMADONE 0x00000010 1639166676Sjkim#define BGE_FTQRESET_SBDC 0x00000020 1640166676Sjkim#define BGE_FTQRESET_SDI 0x00000040 1641166676Sjkim#define BGE_FTQRESET_WDMA 0x00000080 1642166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1643166676Sjkim#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1644166676Sjkim#define BGE_FTQRESET_SDC 0x00000400 1645166676Sjkim#define BGE_FTQRESET_HCC 0x00000800 1646166676Sjkim#define BGE_FTQRESET_TXFIFO 0x00001000 1647166676Sjkim#define BGE_FTQRESET_MBC 0x00002000 1648166676Sjkim#define BGE_FTQRESET_RBDC 0x00004000 1649166676Sjkim#define BGE_FTQRESET_RXLP 0x00008000 1650166676Sjkim#define BGE_FTQRESET_RDBDI 0x00010000 1651166676Sjkim#define BGE_FTQRESET_RDC 0x00020000 1652166676Sjkim#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 165384059Swpaul 165484059Swpaul/* 165584059Swpaul * Message Signaled Interrupt registers 165684059Swpaul */ 1657166676Sjkim#define BGE_MSI_MODE 0x6000 1658166676Sjkim#define BGE_MSI_STATUS 0x6004 1659166676Sjkim#define BGE_MSI_FIFOACCESS 0x6008 166084059Swpaul 166184059Swpaul/* MSI mode register */ 1662166676Sjkim#define BGE_MSIMODE_RESET 0x00000001 1663166676Sjkim#define BGE_MSIMODE_ENABLE 0x00000002 1664166676Sjkim#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1665166676Sjkim#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1666166676Sjkim#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1667166676Sjkim#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1668166676Sjkim#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 166984059Swpaul 167084059Swpaul/* MSI status register */ 1671166676Sjkim#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1672166676Sjkim#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1673166676Sjkim#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1674166676Sjkim#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1675166676Sjkim#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 167684059Swpaul 167784059Swpaul 167884059Swpaul/* 167984059Swpaul * DMA Completion registers 168084059Swpaul */ 1681166676Sjkim#define BGE_DMAC_MODE 0x6400 168284059Swpaul 168384059Swpaul/* DMA Completion mode register */ 1684166676Sjkim#define BGE_DMACMODE_RESET 0x00000001 1685166676Sjkim#define BGE_DMACMODE_ENABLE 0x00000002 168684059Swpaul 168784059Swpaul 168884059Swpaul/* 168984059Swpaul * General control registers. 169084059Swpaul */ 1691166676Sjkim#define BGE_MODE_CTL 0x6800 1692166676Sjkim#define BGE_MISC_CFG 0x6804 1693166676Sjkim#define BGE_MISC_LOCAL_CTL 0x6808 1694166676Sjkim#define BGE_CPU_EVENT 0x6810 1695166676Sjkim#define BGE_EE_ADDR 0x6838 1696166676Sjkim#define BGE_EE_DATA 0x683C 1697166676Sjkim#define BGE_EE_CTL 0x6840 1698166676Sjkim#define BGE_MDI_CTL 0x6844 1699166676Sjkim#define BGE_EE_DELAY 0x6848 1700166676Sjkim#define BGE_FASTBOOT_PC 0x6894 170184059Swpaul 1702178667Sjhb/* 1703178667Sjhb * NVRAM Control registers 1704178667Sjhb */ 1705178667Sjhb#define BGE_NVRAM_CMD 0x7000 1706178667Sjhb#define BGE_NVRAM_STAT 0x7004 1707178667Sjhb#define BGE_NVRAM_WRDATA 0x7008 1708178667Sjhb#define BGE_NVRAM_ADDR 0x700c 1709178667Sjhb#define BGE_NVRAM_RDDATA 0x7010 1710178667Sjhb#define BGE_NVRAM_CFG1 0x7014 1711178667Sjhb#define BGE_NVRAM_CFG2 0x7018 1712178667Sjhb#define BGE_NVRAM_CFG3 0x701c 1713178667Sjhb#define BGE_NVRAM_SWARB 0x7020 1714178667Sjhb#define BGE_NVRAM_ACCESS 0x7024 1715178667Sjhb#define BGE_NVRAM_WRITE1 0x7028 1716178667Sjhb 1717178667Sjhb#define BGE_NVRAMCMD_RESET 0x00000001 1718178667Sjhb#define BGE_NVRAMCMD_DONE 0x00000008 1719178667Sjhb#define BGE_NVRAMCMD_START 0x00000010 1720178667Sjhb#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1721178667Sjhb#define BGE_NVRAMCMD_ERASE 0x00000040 1722178667Sjhb#define BGE_NVRAMCMD_FIRST 0x00000080 1723178667Sjhb#define BGE_NVRAMCMD_LAST 0x00000100 1724178667Sjhb 1725178667Sjhb#define BGE_NVRAM_READCMD \ 1726178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1727178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1728178667Sjhb#define BGE_NVRAM_WRITECMD \ 1729178667Sjhb (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1730178667Sjhb BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1731178667Sjhb 1732178667Sjhb#define BGE_NVRAMSWARB_SET0 0x00000001 1733178667Sjhb#define BGE_NVRAMSWARB_SET1 0x00000002 1734178667Sjhb#define BGE_NVRAMSWARB_SET2 0x00000003 1735178667Sjhb#define BGE_NVRAMSWARB_SET3 0x00000004 1736178667Sjhb#define BGE_NVRAMSWARB_CLR0 0x00000010 1737178667Sjhb#define BGE_NVRAMSWARB_CLR1 0x00000020 1738178667Sjhb#define BGE_NVRAMSWARB_CLR2 0x00000040 1739178667Sjhb#define BGE_NVRAMSWARB_CLR3 0x00000080 1740178667Sjhb#define BGE_NVRAMSWARB_GNT0 0x00000100 1741178667Sjhb#define BGE_NVRAMSWARB_GNT1 0x00000200 1742178667Sjhb#define BGE_NVRAMSWARB_GNT2 0x00000400 1743178667Sjhb#define BGE_NVRAMSWARB_GNT3 0x00000800 1744178667Sjhb#define BGE_NVRAMSWARB_REQ0 0x00001000 1745178667Sjhb#define BGE_NVRAMSWARB_REQ1 0x00002000 1746178667Sjhb#define BGE_NVRAMSWARB_REQ2 0x00004000 1747178667Sjhb#define BGE_NVRAMSWARB_REQ3 0x00008000 1748178667Sjhb 1749178667Sjhb#define BGE_NVRAMACC_ENABLE 0x00000001 1750178667Sjhb#define BGE_NVRAMACC_WRENABLE 0x00000002 1751178667Sjhb 175284059Swpaul/* Mode control register */ 1753166676Sjkim#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1754166676Sjkim#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1755166676Sjkim#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1756166676Sjkim#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1757166676Sjkim#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1758166676Sjkim#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1759166676Sjkim#define BGE_MODECTL_NO_RX_CRC 0x00000400 1760166676Sjkim#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1761166676Sjkim#define BGE_MODECTL_NO_TX_INTR 0x00002000 1762166676Sjkim#define BGE_MODECTL_NO_RX_INTR 0x00004000 1763166676Sjkim#define BGE_MODECTL_FORCE_PCI32 0x00008000 1764166676Sjkim#define BGE_MODECTL_STACKUP 0x00010000 1765166676Sjkim#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1766166676Sjkim#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1767166676Sjkim#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1768166676Sjkim#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1769166676Sjkim#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1770166676Sjkim#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1771166676Sjkim#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1772166676Sjkim#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1773166676Sjkim#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1774166676Sjkim#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 177584059Swpaul 177684059Swpaul/* Misc. config register */ 1777166676Sjkim#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1778166676Sjkim#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1779178785Sbz#define BGE_MISCCFG_BOARD_ID 0x0001E000 1780178785Sbz#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1781178785Sbz#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1782178667Sjhb#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 178384059Swpaul 1784166676Sjkim#define BGE_32BITTIME_66MHZ (0x41 << 1) 178584059Swpaul 178684059Swpaul/* Misc. Local Control */ 1787166676Sjkim#define BGE_MLC_INTR_STATE 0x00000001 1788166676Sjkim#define BGE_MLC_INTR_CLR 0x00000002 1789166676Sjkim#define BGE_MLC_INTR_SET 0x00000004 1790166676Sjkim#define BGE_MLC_INTR_ONATTN 0x00000008 1791166676Sjkim#define BGE_MLC_MISCIO_IN0 0x00000100 1792166676Sjkim#define BGE_MLC_MISCIO_IN1 0x00000200 1793166676Sjkim#define BGE_MLC_MISCIO_IN2 0x00000400 1794166676Sjkim#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1795166676Sjkim#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1796166676Sjkim#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1797166676Sjkim#define BGE_MLC_MISCIO_OUT0 0x00004000 1798166676Sjkim#define BGE_MLC_MISCIO_OUT1 0x00008000 1799166676Sjkim#define BGE_MLC_MISCIO_OUT2 0x00010000 1800166676Sjkim#define BGE_MLC_EXTRAM_ENB 0x00020000 1801166676Sjkim#define BGE_MLC_SRAM_SIZE 0x001C0000 1802166676Sjkim#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1803166676Sjkim#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1804166676Sjkim#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1805166676Sjkim#define BGE_MLC_AUTO_EEPROM 0x01000000 180684059Swpaul 1807166676Sjkim#define BGE_SSRAMSIZE_256KB 0x00000000 1808166676Sjkim#define BGE_SSRAMSIZE_512KB 0x00040000 1809166676Sjkim#define BGE_SSRAMSIZE_1MB 0x00080000 1810166676Sjkim#define BGE_SSRAMSIZE_2MB 0x000C0000 1811166676Sjkim#define BGE_SSRAMSIZE_4MB 0x00100000 1812166676Sjkim#define BGE_SSRAMSIZE_8MB 0x00140000 1813166676Sjkim#define BGE_SSRAMSIZE_16M 0x00180000 181484059Swpaul 181584059Swpaul/* EEPROM address register */ 1816166676Sjkim#define BGE_EEADDR_ADDRESS 0x0000FFFC 1817166676Sjkim#define BGE_EEADDR_HALFCLK 0x01FF0000 1818166676Sjkim#define BGE_EEADDR_START 0x02000000 1819166676Sjkim#define BGE_EEADDR_DEVID 0x1C000000 1820166676Sjkim#define BGE_EEADDR_RESET 0x20000000 1821166676Sjkim#define BGE_EEADDR_DONE 0x40000000 1822166676Sjkim#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 182384059Swpaul 1824166676Sjkim#define BGE_EEDEVID(x) ((x & 7) << 26) 1825166676Sjkim#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1826166676Sjkim#define BGE_HALFCLK_384SCL 0x60 1827166676Sjkim#define BGE_EE_READCMD \ 182884059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 182984059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1830166676Sjkim#define BGE_EE_WRCMD \ 183184059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 183284059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 183384059Swpaul 183484059Swpaul/* EEPROM Control register */ 1835166676Sjkim#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1836166676Sjkim#define BGE_EECTL_CLKOUT 0x00000002 1837166676Sjkim#define BGE_EECTL_CLKIN 0x00000004 1838166676Sjkim#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1839166676Sjkim#define BGE_EECTL_DATAOUT 0x00000010 1840166676Sjkim#define BGE_EECTL_DATAIN 0x00000020 184184059Swpaul 184284059Swpaul/* MDI (MII/GMII) access register */ 1843166676Sjkim#define BGE_MDI_DATA 0x00000001 1844166676Sjkim#define BGE_MDI_DIR 0x00000002 1845166676Sjkim#define BGE_MDI_SEL 0x00000004 1846166676Sjkim#define BGE_MDI_CLK 0x00000008 184784059Swpaul 1848166676Sjkim#define BGE_MEMWIN_START 0x00008000 1849166676Sjkim#define BGE_MEMWIN_END 0x0000FFFF 185084059Swpaul 185184059Swpaul 1852166676Sjkim#define BGE_MEMWIN_READ(sc, x, val) \ 185384059Swpaul do { \ 185484059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 185584059Swpaul (0xFFFF0000 & x), 4); \ 185684059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 185784059Swpaul } while(0) 185884059Swpaul 1859166676Sjkim#define BGE_MEMWIN_WRITE(sc, x, val) \ 186084059Swpaul do { \ 186184059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 186284059Swpaul (0xFFFF0000 & x), 4); \ 186384059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 186484059Swpaul } while(0) 186584059Swpaul 186684059Swpaul/* 1867161847Sdavidch * This magic number is written to the firmware mailbox at 0xb50 1868161847Sdavidch * before a software reset is issued. After the internal firmware 1869161847Sdavidch * has completed its initialization it will write the opposite of 1870161847Sdavidch * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1871161847Sdavidch * driver to synchronize with the firmware. 187284059Swpaul */ 1873166676Sjkim#define BGE_MAGIC_NUMBER 0x4B657654 187484059Swpaul 187584059Swpaultypedef struct { 1876159395Sglebius uint32_t bge_addr_hi; 1877159395Sglebius uint32_t bge_addr_lo; 187884059Swpaul} bge_hostaddr; 1879118026Swpaul 1880166676Sjkim#define BGE_HOSTADDR(x, y) \ 1881115200Sps do { \ 1882159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1883159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1884115200Sps } while(0) 188584059Swpaul 1886166676Sjkim#define BGE_ADDR_LO(y) \ 1887159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 1888166676Sjkim#define BGE_ADDR_HI(y) \ 1889159395Sglebius ((uint64_t) (y) >> 32) 1890118026Swpaul 189184059Swpaul/* Ring control block structure */ 189284059Swpaulstruct bge_rcb { 189384059Swpaul bge_hostaddr bge_hostaddr; 1894159395Sglebius uint32_t bge_maxlen_flags; 1895159395Sglebius uint32_t bge_nicaddr; 189684059Swpaul}; 1897153437Syongari 1898153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 1899183896Smarius bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 1900166676Sjkim#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 190184059Swpaul 1902166676Sjkim#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1903166676Sjkim#define BGE_RCB_FLAG_RING_DISABLED 0x0002 190484059Swpaul 190584059Swpaulstruct bge_tx_bd { 190684059Swpaul bge_hostaddr bge_addr; 1907153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1908159395Sglebius uint16_t bge_flags; 1909159395Sglebius uint16_t bge_len; 1910159395Sglebius uint16_t bge_vlan_tag; 1911159395Sglebius uint16_t bge_rsvd; 1912153437Syongari#else 1913159395Sglebius uint16_t bge_len; 1914159395Sglebius uint16_t bge_flags; 1915159395Sglebius uint16_t bge_rsvd; 1916159395Sglebius uint16_t bge_vlan_tag; 1917153437Syongari#endif 191884059Swpaul}; 191984059Swpaul 1920166676Sjkim#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1921166676Sjkim#define BGE_TXBDFLAG_IP_CSUM 0x0002 1922166676Sjkim#define BGE_TXBDFLAG_END 0x0004 1923166676Sjkim#define BGE_TXBDFLAG_IP_FRAG 0x0008 1924166676Sjkim#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1925166676Sjkim#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1926166676Sjkim#define BGE_TXBDFLAG_COAL_NOW 0x0080 1927166676Sjkim#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1928166676Sjkim#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1929166676Sjkim#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1930166676Sjkim#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1931166676Sjkim#define BGE_TXBDFLAG_NO_CRC 0x8000 193284059Swpaul 1933166676Sjkim#define BGE_NIC_TXRING_ADDR(ringno, size) \ 193484059Swpaul BGE_SEND_RING_1_TO_4 + \ 193584059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 193684059Swpaul 193784059Swpaulstruct bge_rx_bd { 193884059Swpaul bge_hostaddr bge_addr; 1939153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1940159395Sglebius uint16_t bge_len; 1941159395Sglebius uint16_t bge_idx; 1942159395Sglebius uint16_t bge_flags; 1943159395Sglebius uint16_t bge_type; 1944159395Sglebius uint16_t bge_tcp_udp_csum; 1945159395Sglebius uint16_t bge_ip_csum; 1946159395Sglebius uint16_t bge_vlan_tag; 1947159395Sglebius uint16_t bge_error_flag; 1948153437Syongari#else 1949159395Sglebius uint16_t bge_idx; 1950159395Sglebius uint16_t bge_len; 1951159395Sglebius uint16_t bge_type; 1952159395Sglebius uint16_t bge_flags; 1953159395Sglebius uint16_t bge_ip_csum; 1954159395Sglebius uint16_t bge_tcp_udp_csum; 1955159395Sglebius uint16_t bge_error_flag; 1956159395Sglebius uint16_t bge_vlan_tag; 1957153437Syongari#endif 1958159395Sglebius uint32_t bge_rsvd; 1959159395Sglebius uint32_t bge_opaque; 196084059Swpaul}; 196184059Swpaul 1962153239Sglebiusstruct bge_extrx_bd { 1963153239Sglebius bge_hostaddr bge_addr1; 1964153239Sglebius bge_hostaddr bge_addr2; 1965153239Sglebius bge_hostaddr bge_addr3; 1966153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1967159395Sglebius uint16_t bge_len2; 1968159395Sglebius uint16_t bge_len1; 1969159395Sglebius uint16_t bge_rsvd1; 1970159395Sglebius uint16_t bge_len3; 1971153437Syongari#else 1972159395Sglebius uint16_t bge_len1; 1973159395Sglebius uint16_t bge_len2; 1974159395Sglebius uint16_t bge_len3; 1975159395Sglebius uint16_t bge_rsvd1; 1976153437Syongari#endif 1977153239Sglebius bge_hostaddr bge_addr0; 1978153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1979159395Sglebius uint16_t bge_len0; 1980159395Sglebius uint16_t bge_idx; 1981159395Sglebius uint16_t bge_flags; 1982159395Sglebius uint16_t bge_type; 1983159395Sglebius uint16_t bge_tcp_udp_csum; 1984159395Sglebius uint16_t bge_ip_csum; 1985159395Sglebius uint16_t bge_vlan_tag; 1986159395Sglebius uint16_t bge_error_flag; 1987153437Syongari#else 1988159395Sglebius uint16_t bge_idx; 1989159395Sglebius uint16_t bge_len0; 1990159395Sglebius uint16_t bge_type; 1991159395Sglebius uint16_t bge_flags; 1992159395Sglebius uint16_t bge_ip_csum; 1993159395Sglebius uint16_t bge_tcp_udp_csum; 1994159395Sglebius uint16_t bge_error_flag; 1995159395Sglebius uint16_t bge_vlan_tag; 1996153437Syongari#endif 1997159395Sglebius uint32_t bge_rsvd0; 1998159395Sglebius uint32_t bge_opaque; 1999153239Sglebius}; 2000153239Sglebius 2001166676Sjkim#define BGE_RXBDFLAG_END 0x0004 2002166676Sjkim#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2003166676Sjkim#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2004166676Sjkim#define BGE_RXBDFLAG_ERROR 0x0400 2005166676Sjkim#define BGE_RXBDFLAG_MINI_RING 0x0800 2006166676Sjkim#define BGE_RXBDFLAG_IP_CSUM 0x1000 2007166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2008166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 200984059Swpaul 2010166676Sjkim#define BGE_RXERRFLAG_BAD_CRC 0x0001 2011166676Sjkim#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2012166676Sjkim#define BGE_RXERRFLAG_LINK_LOST 0x0004 2013166676Sjkim#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2014166676Sjkim#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2015166676Sjkim#define BGE_RXERRFLAG_RUNT 0x0020 2016166676Sjkim#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2017166676Sjkim#define BGE_RXERRFLAG_GIANT 0x0080 201884059Swpaul 201984059Swpaulstruct bge_sts_idx { 2020153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2021159395Sglebius uint16_t bge_rx_prod_idx; 2022159395Sglebius uint16_t bge_tx_cons_idx; 2023153437Syongari#else 2024159395Sglebius uint16_t bge_tx_cons_idx; 2025159395Sglebius uint16_t bge_rx_prod_idx; 2026153437Syongari#endif 202784059Swpaul}; 202884059Swpaul 202984059Swpaulstruct bge_status_block { 2030159395Sglebius uint32_t bge_status; 2031159395Sglebius uint32_t bge_rsvd0; 2032153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 2033159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2034159395Sglebius uint16_t bge_rx_std_cons_idx; 2035159395Sglebius uint16_t bge_rx_mini_cons_idx; 2036159395Sglebius uint16_t bge_rsvd1; 2037153437Syongari#else 2038159395Sglebius uint16_t bge_rx_std_cons_idx; 2039159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 2040159395Sglebius uint16_t bge_rsvd1; 2041159395Sglebius uint16_t bge_rx_mini_cons_idx; 2042153437Syongari#endif 204384059Swpaul struct bge_sts_idx bge_idx[16]; 204484059Swpaul}; 204584059Swpaul 2046166676Sjkim#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2047166676Sjkim#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 204884059Swpaul 2049166676Sjkim#define BGE_STATFLAG_UPDATED 0x00000001 2050166676Sjkim#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2051166676Sjkim#define BGE_STATFLAG_ERROR 0x00000004 205284059Swpaul 205384059Swpaul 205484059Swpaul/* 205584059Swpaul * Broadcom Vendor ID 205684059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 205784059Swpaul * even though they're now manufactured by Broadcom) 205884059Swpaul */ 2059166676Sjkim#define BCOM_VENDORID 0x14E4 2060166676Sjkim#define BCOM_DEVICEID_BCM5700 0x1644 2061166676Sjkim#define BCOM_DEVICEID_BCM5701 0x1645 2062166676Sjkim#define BCOM_DEVICEID_BCM5702 0x1646 2063166676Sjkim#define BCOM_DEVICEID_BCM5702X 0x16A6 2064166676Sjkim#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2065166676Sjkim#define BCOM_DEVICEID_BCM5703 0x1647 2066166676Sjkim#define BCOM_DEVICEID_BCM5703X 0x16A7 2067166676Sjkim#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2068166676Sjkim#define BCOM_DEVICEID_BCM5704C 0x1648 2069166676Sjkim#define BCOM_DEVICEID_BCM5704S 0x16A8 2070166676Sjkim#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2071166676Sjkim#define BCOM_DEVICEID_BCM5705 0x1653 2072166676Sjkim#define BCOM_DEVICEID_BCM5705K 0x1654 2073166676Sjkim#define BCOM_DEVICEID_BCM5705F 0x166E 2074166676Sjkim#define BCOM_DEVICEID_BCM5705M 0x165D 2075166676Sjkim#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2076166676Sjkim#define BCOM_DEVICEID_BCM5714C 0x1668 2077166676Sjkim#define BCOM_DEVICEID_BCM5714S 0x1669 2078166676Sjkim#define BCOM_DEVICEID_BCM5715 0x1678 2079166676Sjkim#define BCOM_DEVICEID_BCM5715S 0x1679 2080166676Sjkim#define BCOM_DEVICEID_BCM5720 0x1658 2081166676Sjkim#define BCOM_DEVICEID_BCM5721 0x1659 2082176883Sjhb#define BCOM_DEVICEID_BCM5722 0x165A 2083166676Sjkim#define BCOM_DEVICEID_BCM5750 0x1676 2084166676Sjkim#define BCOM_DEVICEID_BCM5750M 0x167C 2085166676Sjkim#define BCOM_DEVICEID_BCM5751 0x1677 2086166676Sjkim#define BCOM_DEVICEID_BCM5751F 0x167E 2087166676Sjkim#define BCOM_DEVICEID_BCM5751M 0x167D 2088166676Sjkim#define BCOM_DEVICEID_BCM5752 0x1600 2089166676Sjkim#define BCOM_DEVICEID_BCM5752M 0x1601 2090166676Sjkim#define BCOM_DEVICEID_BCM5753 0x16F7 2091166676Sjkim#define BCOM_DEVICEID_BCM5753F 0x16FE 2092166676Sjkim#define BCOM_DEVICEID_BCM5753M 0x16FD 2093166676Sjkim#define BCOM_DEVICEID_BCM5754 0x167A 2094166676Sjkim#define BCOM_DEVICEID_BCM5754M 0x1672 2095166676Sjkim#define BCOM_DEVICEID_BCM5755 0x167B 2096166676Sjkim#define BCOM_DEVICEID_BCM5755M 0x1673 2097166676Sjkim#define BCOM_DEVICEID_BCM5780 0x166A 2098166676Sjkim#define BCOM_DEVICEID_BCM5780S 0x166B 2099166676Sjkim#define BCOM_DEVICEID_BCM5781 0x16DD 2100166676Sjkim#define BCOM_DEVICEID_BCM5782 0x1696 2101166676Sjkim#define BCOM_DEVICEID_BCM5786 0x169A 2102166676Sjkim#define BCOM_DEVICEID_BCM5787 0x169B 2103166676Sjkim#define BCOM_DEVICEID_BCM5787M 0x1693 2104166676Sjkim#define BCOM_DEVICEID_BCM5788 0x169C 2105166676Sjkim#define BCOM_DEVICEID_BCM5789 0x169D 2106166676Sjkim#define BCOM_DEVICEID_BCM5901 0x170D 2107166676Sjkim#define BCOM_DEVICEID_BCM5901A2 0x170E 2108166676Sjkim#define BCOM_DEVICEID_BCM5903M 0x16FF 2109178667Sjhb#define BCOM_DEVICEID_BCM5906 0x1712 2110178667Sjhb#define BCOM_DEVICEID_BCM5906M 0x1713 211184059Swpaul 211284059Swpaul/* 211384059Swpaul * Alteon AceNIC PCI vendor/device ID. 211484059Swpaul */ 2115166676Sjkim#define ALTEON_VENDORID 0x12AE 2116166676Sjkim#define ALTEON_DEVICEID_ACENIC 0x0001 2117166676Sjkim#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2118166676Sjkim#define ALTEON_DEVICEID_BCM5700 0x0003 2119166676Sjkim#define ALTEON_DEVICEID_BCM5701 0x0004 212084059Swpaul 212184059Swpaul/* 2122162982Sglebius * 3Com 3c996 PCI vendor/device ID. 212384059Swpaul */ 2124166676Sjkim#define TC_VENDORID 0x10B7 2125166676Sjkim#define TC_DEVICEID_3C996 0x0003 212684059Swpaul 212784059Swpaul/* 212884059Swpaul * SysKonnect PCI vendor ID 212984059Swpaul */ 2130166676Sjkim#define SK_VENDORID 0x1148 2131166676Sjkim#define SK_DEVICEID_ALTIMA 0x4400 2132166676Sjkim#define SK_SUBSYSID_9D21 0x4421 2133166676Sjkim#define SK_SUBSYSID_9D41 0x4441 213484059Swpaul 213584059Swpaul/* 213689835Sjdp * Altima PCI vendor/device ID. 213789835Sjdp */ 2138166676Sjkim#define ALTIMA_VENDORID 0x173b 2139166676Sjkim#define ALTIMA_DEVICE_AC1000 0x03e8 2140166676Sjkim#define ALTIMA_DEVICE_AC1002 0x03e9 2141166676Sjkim#define ALTIMA_DEVICE_AC9100 0x03ea 214289835Sjdp 214389835Sjdp/* 2144119157Sambrisko * Dell PCI vendor ID 2145119157Sambrisko */ 2146119157Sambrisko 2147166676Sjkim#define DELL_VENDORID 0x1028 2148119157Sambrisko 2149119157Sambrisko/* 2150159637Sglebius * Apple PCI vendor ID. 2151159637Sglebius */ 2152166676Sjkim#define APPLE_VENDORID 0x106b 2153166676Sjkim#define APPLE_DEVICE_BCM5701 0x1645 2154159637Sglebius 2155159637Sglebius/* 2156169152Smarius * Sun PCI vendor ID 2157169152Smarius */ 2158169152Smarius#define SUN_VENDORID 0x108e 2159169152Smarius 2160169152Smarius/* 216184059Swpaul * Offset of MAC address inside EEPROM. 216284059Swpaul */ 2163166676Sjkim#define BGE_EE_MAC_OFFSET 0x7C 2164178667Sjhb#define BGE_EE_MAC_OFFSET_5906 0x10 2165166676Sjkim#define BGE_EE_HWCFG_OFFSET 0xC8 216684059Swpaul 2167166676Sjkim#define BGE_HWCFG_VOLTAGE 0x00000003 2168166676Sjkim#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2169166676Sjkim#define BGE_HWCFG_MEDIA 0x00000030 2170166676Sjkim#define BGE_HWCFG_ASF 0x00000080 217193751Swpaul 2172166676Sjkim#define BGE_VOLTAGE_1POINT3 0x00000000 2173166676Sjkim#define BGE_VOLTAGE_1POINT8 0x00000001 217493751Swpaul 2175166676Sjkim#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2176166676Sjkim#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2177166676Sjkim#define BGE_PHYLEDMODE_SINGLELED 0x00000008 217893751Swpaul 2179166676Sjkim#define BGE_MEDIA_UNSPEC 0x00000000 2180166676Sjkim#define BGE_MEDIA_COPPER 0x00000010 2181166676Sjkim#define BGE_MEDIA_FIBER 0x00000020 218293751Swpaul 2183166676Sjkim#define BGE_TICKS_PER_SEC 1000000 218484059Swpaul 218584059Swpaul/* 218684059Swpaul * Ring size constants. 218784059Swpaul */ 2188166676Sjkim#define BGE_EVENT_RING_CNT 256 2189166676Sjkim#define BGE_CMD_RING_CNT 64 2190166676Sjkim#define BGE_STD_RX_RING_CNT 512 2191166676Sjkim#define BGE_JUMBO_RX_RING_CNT 256 2192166676Sjkim#define BGE_MINI_RX_RING_CNT 1024 2193166676Sjkim#define BGE_RETURN_RING_CNT 1024 219484059Swpaul 2195117659Swpaul/* 5705 has smaller return ring size */ 2196117659Swpaul 2197166676Sjkim#define BGE_RETURN_RING_CNT_5705 512 2198117659Swpaul 219984059Swpaul/* 220084059Swpaul * Possible TX ring sizes. 220184059Swpaul */ 2202166676Sjkim#define BGE_TX_RING_CNT_128 128 2203166676Sjkim#define BGE_TX_RING_BASE_128 0x3800 220484059Swpaul 2205166676Sjkim#define BGE_TX_RING_CNT_256 256 2206166676Sjkim#define BGE_TX_RING_BASE_256 0x3000 220784059Swpaul 2208166676Sjkim#define BGE_TX_RING_CNT_512 512 2209166676Sjkim#define BGE_TX_RING_BASE_512 0x2000 221084059Swpaul 2211166676Sjkim#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2212166676Sjkim#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 221384059Swpaul 221484059Swpaul/* 221584059Swpaul * Tigon III statistics counters. 221684059Swpaul */ 2217117659Swpaul/* Statistics maintained MAC Receive block. */ 2218117659Swpaulstruct bge_rx_mac_stats { 221984059Swpaul bge_hostaddr ifHCInOctets; 222084059Swpaul bge_hostaddr Reserved1; 222184059Swpaul bge_hostaddr etherStatsFragments; 222284059Swpaul bge_hostaddr ifHCInUcastPkts; 222384059Swpaul bge_hostaddr ifHCInMulticastPkts; 222484059Swpaul bge_hostaddr ifHCInBroadcastPkts; 222584059Swpaul bge_hostaddr dot3StatsFCSErrors; 222684059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 222784059Swpaul bge_hostaddr xonPauseFramesReceived; 222884059Swpaul bge_hostaddr xoffPauseFramesReceived; 222984059Swpaul bge_hostaddr macControlFramesReceived; 223084059Swpaul bge_hostaddr xoffStateEntered; 223184059Swpaul bge_hostaddr dot3StatsFramesTooLong; 223284059Swpaul bge_hostaddr etherStatsJabbers; 223384059Swpaul bge_hostaddr etherStatsUndersizePkts; 223484059Swpaul bge_hostaddr inRangeLengthError; 223584059Swpaul bge_hostaddr outRangeLengthError; 223684059Swpaul bge_hostaddr etherStatsPkts64Octets; 223784059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 223884059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 223984059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 224084059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 224184059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 224284059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 224384059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 224484059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 224584059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2246117659Swpaul}; 224784059Swpaul 224884059Swpaul 2249117659Swpaul/* Statistics maintained MAC Transmit block. */ 2250117659Swpaulstruct bge_tx_mac_stats { 225184059Swpaul bge_hostaddr ifHCOutOctets; 225284059Swpaul bge_hostaddr Reserved2; 225384059Swpaul bge_hostaddr etherStatsCollisions; 225484059Swpaul bge_hostaddr outXonSent; 225584059Swpaul bge_hostaddr outXoffSent; 225684059Swpaul bge_hostaddr flowControlDone; 225784059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 225884059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 225984059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 226084059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 226184059Swpaul bge_hostaddr Reserved3; 226284059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 226384059Swpaul bge_hostaddr dot3StatsLateCollisions; 226484059Swpaul bge_hostaddr dot3Collided2Times; 226584059Swpaul bge_hostaddr dot3Collided3Times; 226684059Swpaul bge_hostaddr dot3Collided4Times; 226784059Swpaul bge_hostaddr dot3Collided5Times; 226884059Swpaul bge_hostaddr dot3Collided6Times; 226984059Swpaul bge_hostaddr dot3Collided7Times; 227084059Swpaul bge_hostaddr dot3Collided8Times; 227184059Swpaul bge_hostaddr dot3Collided9Times; 227284059Swpaul bge_hostaddr dot3Collided10Times; 227384059Swpaul bge_hostaddr dot3Collided11Times; 227484059Swpaul bge_hostaddr dot3Collided12Times; 227584059Swpaul bge_hostaddr dot3Collided13Times; 227684059Swpaul bge_hostaddr dot3Collided14Times; 227784059Swpaul bge_hostaddr dot3Collided15Times; 227884059Swpaul bge_hostaddr ifHCOutUcastPkts; 227984059Swpaul bge_hostaddr ifHCOutMulticastPkts; 228084059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 228184059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 228284059Swpaul bge_hostaddr ifOutDiscards; 228384059Swpaul bge_hostaddr ifOutErrors; 2284117659Swpaul}; 228584059Swpaul 2286117659Swpaul/* Stats counters access through registers */ 2287117659Swpaulstruct bge_mac_stats_regs { 2288159395Sglebius uint32_t ifHCOutOctets; 2289159395Sglebius uint32_t Reserved0; 2290159395Sglebius uint32_t etherStatsCollisions; 2291159395Sglebius uint32_t outXonSent; 2292159395Sglebius uint32_t outXoffSent; 2293159395Sglebius uint32_t Reserved1; 2294159395Sglebius uint32_t dot3StatsInternalMacTransmitErrors; 2295159395Sglebius uint32_t dot3StatsSingleCollisionFrames; 2296159395Sglebius uint32_t dot3StatsMultipleCollisionFrames; 2297159395Sglebius uint32_t dot3StatsDeferredTransmissions; 2298159395Sglebius uint32_t Reserved2; 2299159395Sglebius uint32_t dot3StatsExcessiveCollisions; 2300159395Sglebius uint32_t dot3StatsLateCollisions; 2301159395Sglebius uint32_t Reserved3[14]; 2302159395Sglebius uint32_t ifHCOutUcastPkts; 2303159395Sglebius uint32_t ifHCOutMulticastPkts; 2304159395Sglebius uint32_t ifHCOutBroadcastPkts; 2305159395Sglebius uint32_t Reserved4[2]; 2306159395Sglebius uint32_t ifHCInOctets; 2307159395Sglebius uint32_t Reserved5; 2308159395Sglebius uint32_t etherStatsFragments; 2309159395Sglebius uint32_t ifHCInUcastPkts; 2310159395Sglebius uint32_t ifHCInMulticastPkts; 2311159395Sglebius uint32_t ifHCInBroadcastPkts; 2312159395Sglebius uint32_t dot3StatsFCSErrors; 2313159395Sglebius uint32_t dot3StatsAlignmentErrors; 2314159395Sglebius uint32_t xonPauseFramesReceived; 2315159395Sglebius uint32_t xoffPauseFramesReceived; 2316159395Sglebius uint32_t macControlFramesReceived; 2317159395Sglebius uint32_t xoffStateEntered; 2318159395Sglebius uint32_t dot3StatsFramesTooLong; 2319159395Sglebius uint32_t etherStatsJabbers; 2320159395Sglebius uint32_t etherStatsUndersizePkts; 2321117659Swpaul}; 2322117659Swpaul 2323117659Swpaulstruct bge_stats { 2324159395Sglebius uint8_t Reserved0[256]; 2325117659Swpaul 2326117659Swpaul /* Statistics maintained by Receive MAC. */ 2327117659Swpaul struct bge_rx_mac_stats rxstats; 2328117659Swpaul 2329117659Swpaul bge_hostaddr Unused1[37]; 2330117659Swpaul 2331117659Swpaul /* Statistics maintained by Transmit MAC. */ 2332117659Swpaul struct bge_tx_mac_stats txstats; 2333117659Swpaul 233484059Swpaul bge_hostaddr Unused2[31]; 233584059Swpaul 233684059Swpaul /* Statistics maintained by Receive List Placement. */ 233784059Swpaul bge_hostaddr COSIfHCInPkts[16]; 233884059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 233984059Swpaul bge_hostaddr nicDmaWriteQueueFull; 234084059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 234184059Swpaul bge_hostaddr nicNoMoreRxBDs; 234284059Swpaul bge_hostaddr ifInDiscards; 234384059Swpaul bge_hostaddr ifInErrors; 234484059Swpaul bge_hostaddr nicRecvThresholdHit; 234584059Swpaul 234684059Swpaul bge_hostaddr Unused3[9]; 234784059Swpaul 234884059Swpaul /* Statistics maintained by Send Data Initiator. */ 234984059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 235084059Swpaul bge_hostaddr nicDmaReadQueueFull; 235184059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 235284059Swpaul bge_hostaddr nicSendDataCompQueueFull; 235384059Swpaul 235484059Swpaul /* Statistics maintained by Host Coalescing. */ 235584059Swpaul bge_hostaddr nicRingSetSendProdIndex; 235684059Swpaul bge_hostaddr nicRingStatusUpdate; 235784059Swpaul bge_hostaddr nicInterrupts; 235884059Swpaul bge_hostaddr nicAvoidedInterrupts; 235984059Swpaul bge_hostaddr nicSendThresholdHit; 236084059Swpaul 2361159395Sglebius uint8_t Reserved4[320]; 236284059Swpaul}; 236384059Swpaul 236484059Swpaul/* 236584059Swpaul * Tigon general information block. This resides in host memory 236684059Swpaul * and contains the status counters, ring control blocks and 236784059Swpaul * producer pointers. 236884059Swpaul */ 236984059Swpaul 237084059Swpaulstruct bge_gib { 237184059Swpaul struct bge_stats bge_stats; 237284059Swpaul struct bge_rcb bge_tx_rcb[16]; 237384059Swpaul struct bge_rcb bge_std_rx_rcb; 237484059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 237584059Swpaul struct bge_rcb bge_mini_rx_rcb; 237684059Swpaul struct bge_rcb bge_return_rcb; 237784059Swpaul}; 237884059Swpaul 2379166676Sjkim#define BGE_FRAMELEN 1518 2380166676Sjkim#define BGE_MAX_FRAMELEN 1536 2381166676Sjkim#define BGE_JUMBO_FRAMELEN 9018 2382166676Sjkim#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2383166676Sjkim#define BGE_MIN_FRAMELEN 60 238484059Swpaul 238584059Swpaul/* 238684059Swpaul * Other utility macros. 238784059Swpaul */ 2388166676Sjkim#define BGE_INC(x, y) (x) = (x + 1) % y 238984059Swpaul 239084059Swpaul/* 239184059Swpaul * Register access macros. The Tigon always uses memory mapped register 239284059Swpaul * accesses and all registers must be accessed with 32 bit operations. 239384059Swpaul */ 239484059Swpaul 2395166676Sjkim#define CSR_WRITE_4(sc, reg, val) \ 2396183896Smarius bus_write_4(sc->bge_res, reg, val) 239784059Swpaul 2398166676Sjkim#define CSR_READ_4(sc, reg) \ 2399183896Smarius bus_read_4(sc->bge_res, reg) 240084059Swpaul 2401166676Sjkim#define BGE_SETBIT(sc, reg, x) \ 2402106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2403166676Sjkim#define BGE_CLRBIT(sc, reg, x) \ 2404106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 240584059Swpaul 2406166676Sjkim#define PCI_SETBIT(dev, reg, x, s) \ 2407106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2408166676Sjkim#define PCI_CLRBIT(dev, reg, x, s) \ 2409106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 241084059Swpaul 241184059Swpaul/* 241284059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 241384059Swpaul * values are tuneable. They control the actual amount of buffers 241484059Swpaul * allocated for the standard, mini and jumbo receive rings. 241584059Swpaul */ 241684059Swpaul 2417166676Sjkim#define BGE_SSLOTS 256 2418166676Sjkim#define BGE_MSLOTS 256 2419166676Sjkim#define BGE_JSLOTS 384 242084059Swpaul 2421166676Sjkim#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2422166676Sjkim#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2423159395Sglebius (BGE_JRAWLEN % sizeof(uint64_t)))) 2424166676Sjkim#define BGE_JPAGESZ PAGE_SIZE 2425166676Sjkim#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2426166676Sjkim#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 242784059Swpaul 2428166676Sjkim#define BGE_NSEG_JUMBO 4 2429166676Sjkim#define BGE_NSEG_NEW 32 2430153239Sglebius 243184059Swpaul/* 243284059Swpaul * Ring structures. Most of these reside in host memory and we tell 243384059Swpaul * the NIC where they are via the ring control blocks. The exceptions 243484059Swpaul * are the tx and command rings, which live in NIC memory and which 243584059Swpaul * we access via the shared memory window. 243684059Swpaul */ 2437118026Swpaul 243884059Swpaulstruct bge_ring_data { 2439118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2440118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2441153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2442118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2443118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2444118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2445118026Swpaul struct bge_tx_bd *bge_tx_ring; 2446118026Swpaul bus_addr_t bge_tx_ring_paddr; 2447118026Swpaul struct bge_status_block *bge_status_block; 2448118026Swpaul bus_addr_t bge_status_block_paddr; 2449118026Swpaul struct bge_stats *bge_stats; 2450118026Swpaul bus_addr_t bge_stats_paddr; 245184059Swpaul struct bge_gib bge_info; 245284059Swpaul}; 245384059Swpaul 2454166676Sjkim#define BGE_STD_RX_RING_SZ \ 2455118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2456166676Sjkim#define BGE_JUMBO_RX_RING_SZ \ 2457153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2458166676Sjkim#define BGE_TX_RING_SZ \ 2459118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2460166676Sjkim#define BGE_RX_RTN_RING_SZ(x) \ 2461118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2462118026Swpaul 2463166676Sjkim#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2464118026Swpaul 2465166676Sjkim#define BGE_STATS_SZ sizeof (struct bge_stats) 2466118026Swpaul 246784059Swpaul/* 246884059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 246984059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 247084059Swpaul * not the other way around. 247184059Swpaul */ 247284059Swpaulstruct bge_chain_data { 2473118026Swpaul bus_dma_tag_t bge_parent_tag; 2474118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2475118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2476118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2477118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2478118026Swpaul bus_dma_tag_t bge_status_tag; 2479118026Swpaul bus_dma_tag_t bge_stats_tag; 2480118026Swpaul bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2481118026Swpaul bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2482118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2483118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2484118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2485118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2486118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2487118026Swpaul bus_dmamap_t bge_tx_ring_map; 2488118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2489118026Swpaul bus_dmamap_t bge_status_map; 2490118026Swpaul bus_dmamap_t bge_stats_map; 249184059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 249284059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 249384059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 249484059Swpaul}; 249584059Swpaul 2496118026Swpaulstruct bge_dmamap_arg { 2497118026Swpaul struct bge_softc *sc; 2498118026Swpaul bus_addr_t bge_busaddr; 2499159395Sglebius uint16_t bge_flags; 2500118026Swpaul int bge_idx; 2501118026Swpaul int bge_maxsegs; 2502118026Swpaul struct bge_tx_bd *bge_ring; 2503118026Swpaul}; 2504118026Swpaul 2505166676Sjkim#define BGE_HWREV_TIGON 0x01 2506166676Sjkim#define BGE_HWREV_TIGON_II 0x02 2507166676Sjkim#define BGE_TIMEOUT 100000 2508166676Sjkim#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 250984059Swpaul 251084059Swpaulstruct bge_bcom_hack { 251184059Swpaul int reg; 251284059Swpaul int val; 251384059Swpaul}; 251484059Swpaul 2515166676Sjkim#define ASF_ENABLE 1 2516166676Sjkim#define ASF_NEW_HANDSHAKE 2 2517166676Sjkim#define ASF_STACKUP 4 2518162169Sambrisko 251984059Swpaulstruct bge_softc { 2520147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 252184059Swpaul device_t bge_dev; 2522122497Ssam struct mtx bge_mtx; 252384059Swpaul device_t bge_miibus; 252484059Swpaul void *bge_intrhand; 252584059Swpaul struct resource *bge_irq; 252684059Swpaul struct resource *bge_res; 252784059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2528161546Sglebius uint32_t bge_flags; 2529166676Sjkim#define BGE_FLAG_TBI 0x00000001 2530166676Sjkim#define BGE_FLAG_JUMBO 0x00000002 2531175466Sjkim#define BGE_FLAG_WIRESPEED 0x00000004 2532178996Smarius#define BGE_FLAG_EADDR 0x00000008 2533166676Sjkim#define BGE_FLAG_MSI 0x00000100 2534166676Sjkim#define BGE_FLAG_PCIX 0x00000200 2535166676Sjkim#define BGE_FLAG_PCIE 0x00000400 2536166676Sjkim#define BGE_FLAG_5700_FAMILY 0x00001000 2537166676Sjkim#define BGE_FLAG_5705_PLUS 0x00002000 2538166676Sjkim#define BGE_FLAG_5714_FAMILY 0x00004000 2539166676Sjkim#define BGE_FLAG_575X_PLUS 0x00008000 2540166676Sjkim#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2541166676Sjkim#define BGE_FLAG_NO_3LED 0x00200000 2542166676Sjkim#define BGE_FLAG_ADC_BUG 0x00400000 2543166676Sjkim#define BGE_FLAG_5704_A0_BUG 0x00800000 2544166676Sjkim#define BGE_FLAG_JITTER_BUG 0x01000000 2545166676Sjkim#define BGE_FLAG_BER_BUG 0x02000000 2546166676Sjkim#define BGE_FLAG_ADJUST_TRIM 0x04000000 2547166677Sjkim#define BGE_FLAG_CRC_BUG 0x08000000 2548178785Sbz#define BGE_FLAG_5788 0x20000000 2549159395Sglebius uint32_t bge_chipid; 2550162169Sambrisko uint8_t bge_asicrev; 2551162169Sambrisko uint8_t bge_chiprev; 2552162169Sambrisko uint8_t bge_asf_mode; 2553162169Sambrisko uint8_t bge_asf_count; 2554118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 255584059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 2556159395Sglebius uint16_t bge_tx_saved_considx; 2557159395Sglebius uint16_t bge_rx_saved_considx; 2558159395Sglebius uint16_t bge_ev_saved_considx; 2559159395Sglebius uint16_t bge_return_ring_cnt; 2560159395Sglebius uint16_t bge_std; /* current std ring head */ 2561159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 2562159395Sglebius uint32_t bge_stat_ticks; 2563159395Sglebius uint32_t bge_rx_coal_ticks; 2564159395Sglebius uint32_t bge_tx_coal_ticks; 2565159395Sglebius uint32_t bge_tx_prodidx; 2566159395Sglebius uint32_t bge_rx_max_coal_bds; 2567159395Sglebius uint32_t bge_tx_max_coal_bds; 2568159395Sglebius uint32_t bge_tx_buf_ratio; 256984059Swpaul int bge_if_flags; 257084059Swpaul int bge_txcnt; 2571155180Soleg int bge_link; /* link state */ 2572155180Soleg int bge_link_evt; /* pending link event */ 2573164769Sglebius int bge_timer; 2574122497Ssam struct callout bge_stat_ch; 2575164780Sjkim uint32_t bge_rx_discards; 2576164780Sjkim uint32_t bge_tx_discards; 2577164780Sjkim uint32_t bge_tx_collisions; 2578151553Sglebius#ifdef DEVICE_POLLING 2579151553Sglebius int rxcycles; 2580151553Sglebius#endif /* DEVICE_POLLING */ 258184059Swpaul}; 2582122497Ssam 2583122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2584122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2585122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2586122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2587122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2588122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2589