if_bgereg.h revision 169880
1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 169880 2007-05-22 19:22:58Z jkim $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 64166676Sjkim#define BGE_PAGE_ZERO 0x00000000 65166676Sjkim#define BGE_PAGE_ZERO_END 0x000000FF 66166676Sjkim#define BGE_SEND_RING_RCB 0x00000100 67166676Sjkim#define BGE_SEND_RING_RCB_END 0x000001FF 68166676Sjkim#define BGE_RX_RETURN_RING_RCB 0x00000200 69166676Sjkim#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70166676Sjkim#define BGE_STATS_BLOCK 0x00000300 71166676Sjkim#define BGE_STATS_BLOCK_END 0x00000AFF 72166676Sjkim#define BGE_STATUS_BLOCK 0x00000B00 73166676Sjkim#define BGE_STATUS_BLOCK_END 0x00000B4F 74166676Sjkim#define BGE_SOFTWARE_GENCOMM 0x00000B50 75166676Sjkim#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76166676Sjkim#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77166676Sjkim#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78166676Sjkim#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79166676Sjkim#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80166676Sjkim#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81166676Sjkim#define BGE_UNMAPPED 0x00001000 82166676Sjkim#define BGE_UNMAPPED_END 0x00001FFF 83166676Sjkim#define BGE_DMA_DESCRIPTORS 0x00002000 84166676Sjkim#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85166676Sjkim#define BGE_SEND_RING_1_TO_4 0x00004000 86166676Sjkim#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8784059Swpaul 88166676Sjkim/* Firmware interface */ 89166676Sjkim#define BGE_FW_DRV_ALIVE 0x00000001 90166676Sjkim#define BGE_FW_PAUSE 0x00000002 91166676Sjkim 9284059Swpaul/* Mappings for internal memory configuration */ 93166676Sjkim#define BGE_STD_RX_RINGS 0x00006000 94166676Sjkim#define BGE_STD_RX_RINGS_END 0x00006FFF 95166676Sjkim#define BGE_JUMBO_RX_RINGS 0x00007000 96166676Sjkim#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97166676Sjkim#define BGE_BUFFPOOL_1 0x00008000 98166676Sjkim#define BGE_BUFFPOOL_1_END 0x0000FFFF 99166676Sjkim#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 100166676Sjkim#define BGE_BUFFPOOL_2_END 0x00017FFF 101166676Sjkim#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 102166676Sjkim#define BGE_BUFFPOOL_3_END 0x0001FFFF 10384059Swpaul 10484059Swpaul/* Mappings for external SSRAM configurations */ 105166676Sjkim#define BGE_SEND_RING_5_TO_6 0x00006000 106166676Sjkim#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107166676Sjkim#define BGE_SEND_RING_7_TO_8 0x00007000 108166676Sjkim#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109166676Sjkim#define BGE_SEND_RING_9_TO_16 0x00008000 110166676Sjkim#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111166676Sjkim#define BGE_EXT_STD_RX_RINGS 0x0000C000 112166676Sjkim#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114166676Sjkim#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115166676Sjkim#define BGE_MINI_RX_RINGS 0x0000E000 116166676Sjkim#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117166676Sjkim#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 118166676Sjkim#define BGE_AVAIL_REGION1_END 0x00017FFF 119166676Sjkim#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 120166676Sjkim#define BGE_AVAIL_REGION2_END 0x0001FFFF 121166676Sjkim#define BGE_EXT_SSRAM 0x00020000 122166676Sjkim#define BGE_EXT_SSRAM_END 0x000FFFFF 12384059Swpaul 12484059Swpaul 12584059Swpaul/* 12684059Swpaul * BCM570x register offsets. These are memory mapped registers 12784059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12884059Swpaul * Each register must be accessed using 32 bit operations. 12984059Swpaul * 13084059Swpaul * All registers are accessed through a 32K shared memory block. 13184059Swpaul * The first group of registers are actually copies of the PCI 13284059Swpaul * configuration space registers. 13384059Swpaul */ 13484059Swpaul 13584059Swpaul/* 13684059Swpaul * PCI registers defined in the PCI 2.2 spec. 13784059Swpaul */ 138166676Sjkim#define BGE_PCI_VID 0x00 139166676Sjkim#define BGE_PCI_DID 0x02 140166676Sjkim#define BGE_PCI_CMD 0x04 141166676Sjkim#define BGE_PCI_STS 0x06 142166676Sjkim#define BGE_PCI_REV 0x08 143166676Sjkim#define BGE_PCI_CLASS 0x09 144166676Sjkim#define BGE_PCI_CACHESZ 0x0C 145166676Sjkim#define BGE_PCI_LATTIMER 0x0D 146166676Sjkim#define BGE_PCI_HDRTYPE 0x0E 147166676Sjkim#define BGE_PCI_BIST 0x0F 148166676Sjkim#define BGE_PCI_BAR0 0x10 149166676Sjkim#define BGE_PCI_BAR1 0x14 150166676Sjkim#define BGE_PCI_SUBSYS 0x2C 151166676Sjkim#define BGE_PCI_SUBVID 0x2E 152166676Sjkim#define BGE_PCI_ROMBASE 0x30 153166676Sjkim#define BGE_PCI_CAPPTR 0x34 154166676Sjkim#define BGE_PCI_INTLINE 0x3C 155166676Sjkim#define BGE_PCI_INTPIN 0x3D 156166676Sjkim#define BGE_PCI_MINGNT 0x3E 157166676Sjkim#define BGE_PCI_MAXLAT 0x3F 158166676Sjkim#define BGE_PCI_PCIXCAP 0x40 159166676Sjkim#define BGE_PCI_NEXTPTR_PM 0x41 160166676Sjkim#define BGE_PCI_PCIX_CMD 0x42 161166676Sjkim#define BGE_PCI_PCIX_STS 0x44 162166676Sjkim#define BGE_PCI_PWRMGMT_CAPID 0x48 163166676Sjkim#define BGE_PCI_NEXTPTR_VPD 0x49 164166676Sjkim#define BGE_PCI_PWRMGMT_CAPS 0x4A 165166676Sjkim#define BGE_PCI_PWRMGMT_CMD 0x4C 166166676Sjkim#define BGE_PCI_PWRMGMT_STS 0x4D 167166676Sjkim#define BGE_PCI_PWRMGMT_DATA 0x4F 168166676Sjkim#define BGE_PCI_VPD_CAPID 0x50 169166676Sjkim#define BGE_PCI_NEXTPTR_MSI 0x51 170166676Sjkim#define BGE_PCI_VPD_ADDR 0x52 171166676Sjkim#define BGE_PCI_VPD_DATA 0x54 172166676Sjkim#define BGE_PCI_MSI_CAPID 0x58 173166676Sjkim#define BGE_PCI_NEXTPTR_NONE 0x59 174166676Sjkim#define BGE_PCI_MSI_CTL 0x5A 175166676Sjkim#define BGE_PCI_MSI_ADDR_HI 0x5C 176166676Sjkim#define BGE_PCI_MSI_ADDR_LO 0x60 177166676Sjkim#define BGE_PCI_MSI_DATA 0x64 17884059Swpaul 179135772Sps/* PCI MSI. ??? */ 180166676Sjkim#define BGE_PCIE_CAPID_REG 0xD0 181166676Sjkim#define BGE_PCIE_CAPID 0x10 182135772Sps 18384059Swpaul/* 18484059Swpaul * PCI registers specific to the BCM570x family. 18584059Swpaul */ 186166676Sjkim#define BGE_PCI_MISC_CTL 0x68 187166676Sjkim#define BGE_PCI_DMA_RW_CTL 0x6C 188166676Sjkim#define BGE_PCI_PCISTATE 0x70 189166676Sjkim#define BGE_PCI_CLKCTL 0x74 190166676Sjkim#define BGE_PCI_REG_BASEADDR 0x78 191166676Sjkim#define BGE_PCI_MEMWIN_BASEADDR 0x7C 192166676Sjkim#define BGE_PCI_REG_DATA 0x80 193166676Sjkim#define BGE_PCI_MEMWIN_DATA 0x84 194166676Sjkim#define BGE_PCI_MODECTL 0x88 195166676Sjkim#define BGE_PCI_MISC_CFG 0x8C 196166676Sjkim#define BGE_PCI_MISC_LOCALCTL 0x90 197166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 198166676Sjkim#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 199166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 200166676Sjkim#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 201166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 202166676Sjkim#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 203166676Sjkim#define BGE_PCI_ISR_MBX_HI 0xB0 204166676Sjkim#define BGE_PCI_ISR_MBX_LO 0xB4 20584059Swpaul 20684059Swpaul/* PCI Misc. Host control register */ 207166676Sjkim#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 208166676Sjkim#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 209166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 210166676Sjkim#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 211166676Sjkim#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 212166676Sjkim#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 213166676Sjkim#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 214166676Sjkim#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 215166676Sjkim#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 21684059Swpaul 217166676Sjkim#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 218153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 219166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 220153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME| \ 221153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 222153437Syongari#else 223166676Sjkim#define BGE_DMA_SWAP_OPTIONS \ 224153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 225153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 226153437Syongari#endif 22784059Swpaul 228166676Sjkim#define BGE_INIT \ 229153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 230153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 23184059Swpaul 232166676Sjkim#define BGE_CHIPID_TIGON_I 0x40000000 233166676Sjkim#define BGE_CHIPID_TIGON_II 0x60000000 234166676Sjkim#define BGE_CHIPID_BCM5700_A0 0x70000000 235166676Sjkim#define BGE_CHIPID_BCM5700_A1 0x70010000 236166676Sjkim#define BGE_CHIPID_BCM5700_B0 0x71000000 237166676Sjkim#define BGE_CHIPID_BCM5700_B1 0x71010000 238166676Sjkim#define BGE_CHIPID_BCM5700_B2 0x71020000 239166676Sjkim#define BGE_CHIPID_BCM5700_B3 0x71030000 240166676Sjkim#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 241166676Sjkim#define BGE_CHIPID_BCM5700_C0 0x72000000 242166676Sjkim#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 243166676Sjkim#define BGE_CHIPID_BCM5701_B0 0x01000000 244166676Sjkim#define BGE_CHIPID_BCM5701_B2 0x01020000 245166676Sjkim#define BGE_CHIPID_BCM5701_B5 0x01050000 246166676Sjkim#define BGE_CHIPID_BCM5703_A0 0x10000000 247166676Sjkim#define BGE_CHIPID_BCM5703_A1 0x10010000 248166676Sjkim#define BGE_CHIPID_BCM5703_A2 0x10020000 249166676Sjkim#define BGE_CHIPID_BCM5703_A3 0x10030000 250166676Sjkim#define BGE_CHIPID_BCM5703_B0 0x11000000 251166676Sjkim#define BGE_CHIPID_BCM5704_A0 0x20000000 252166676Sjkim#define BGE_CHIPID_BCM5704_A1 0x20010000 253166676Sjkim#define BGE_CHIPID_BCM5704_A2 0x20020000 254166676Sjkim#define BGE_CHIPID_BCM5704_A3 0x20030000 255166676Sjkim#define BGE_CHIPID_BCM5704_B0 0x21000000 256166676Sjkim#define BGE_CHIPID_BCM5705_A0 0x30000000 257166676Sjkim#define BGE_CHIPID_BCM5705_A1 0x30010000 258166676Sjkim#define BGE_CHIPID_BCM5705_A2 0x30020000 259166676Sjkim#define BGE_CHIPID_BCM5705_A3 0x30030000 260166676Sjkim#define BGE_CHIPID_BCM5750_A0 0x40000000 261166676Sjkim#define BGE_CHIPID_BCM5750_A1 0x40010000 262166676Sjkim#define BGE_CHIPID_BCM5750_A3 0x40030000 263166676Sjkim#define BGE_CHIPID_BCM5750_B0 0x41000000 264166676Sjkim#define BGE_CHIPID_BCM5750_B1 0x41010000 265166676Sjkim#define BGE_CHIPID_BCM5750_C0 0x42000000 266166676Sjkim#define BGE_CHIPID_BCM5750_C1 0x42010000 267166676Sjkim#define BGE_CHIPID_BCM5750_C2 0x42020000 268166676Sjkim#define BGE_CHIPID_BCM5714_A0 0x50000000 269166676Sjkim#define BGE_CHIPID_BCM5752_A0 0x60000000 270166676Sjkim#define BGE_CHIPID_BCM5752_A1 0x60010000 271166676Sjkim#define BGE_CHIPID_BCM5752_A2 0x60020000 272166676Sjkim#define BGE_CHIPID_BCM5714_B0 0x80000000 273166676Sjkim#define BGE_CHIPID_BCM5714_B3 0x80030000 274166676Sjkim#define BGE_CHIPID_BCM5715_A0 0x90000000 275166676Sjkim#define BGE_CHIPID_BCM5715_A1 0x90010000 276167351Sjkim#define BGE_CHIPID_BCM5715_A3 0x90030000 277166676Sjkim#define BGE_CHIPID_BCM5755_A0 0xa0000000 278166676Sjkim#define BGE_CHIPID_BCM5755_A1 0xa0010000 279166676Sjkim#define BGE_CHIPID_BCM5755_A2 0xa0020000 280166676Sjkim#define BGE_CHIPID_BCM5754_A0 0xb0000000 281166676Sjkim#define BGE_CHIPID_BCM5754_A1 0xb0010000 282166676Sjkim#define BGE_CHIPID_BCM5754_A2 0xb0020000 283166676Sjkim#define BGE_CHIPID_BCM5787_A0 0xb0000000 284166676Sjkim#define BGE_CHIPID_BCM5787_A1 0xb0010000 285166676Sjkim#define BGE_CHIPID_BCM5787_A2 0xb0020000 28684059Swpaul 28793751Swpaul/* shorthand one */ 288166676Sjkim#define BGE_ASICREV(x) ((x) >> 28) 289166676Sjkim#define BGE_ASICREV_BCM5701 0x00 290166676Sjkim#define BGE_ASICREV_BCM5703 0x01 291166676Sjkim#define BGE_ASICREV_BCM5704 0x02 292166676Sjkim#define BGE_ASICREV_BCM5705 0x03 293166676Sjkim#define BGE_ASICREV_BCM5750 0x04 294166676Sjkim#define BGE_ASICREV_BCM5714_A0 0x05 295166676Sjkim#define BGE_ASICREV_BCM5752 0x06 296166676Sjkim#define BGE_ASICREV_BCM5700 0x07 297166676Sjkim#define BGE_ASICREV_BCM5780 0x08 298166676Sjkim#define BGE_ASICREV_BCM5714 0x09 299166676Sjkim#define BGE_ASICREV_BCM5755 0x0a 300166676Sjkim#define BGE_ASICREV_BCM5754 0x0b 301166676Sjkim#define BGE_ASICREV_BCM5787 0x0b 30293751Swpaul 303114813Sps/* chip revisions */ 304166676Sjkim#define BGE_CHIPREV(x) ((x) >> 24) 305166676Sjkim#define BGE_CHIPREV_5700_AX 0x70 306166676Sjkim#define BGE_CHIPREV_5700_BX 0x71 307166676Sjkim#define BGE_CHIPREV_5700_CX 0x72 308166676Sjkim#define BGE_CHIPREV_5701_AX 0x00 309166676Sjkim#define BGE_CHIPREV_5703_AX 0x10 310166676Sjkim#define BGE_CHIPREV_5704_AX 0x20 311166676Sjkim#define BGE_CHIPREV_5704_BX 0x21 312166676Sjkim#define BGE_CHIPREV_5750_AX 0x40 313166676Sjkim#define BGE_CHIPREV_5750_BX 0x41 314114813Sps 31584059Swpaul/* PCI DMA Read/Write Control register */ 316166676Sjkim#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 317166676Sjkim#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 318166676Sjkim#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 319169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 320169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 321169880Sjkim#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 322166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 323166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 324166676Sjkim#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 325166676Sjkim#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 326166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 327166676Sjkim#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 32884059Swpaul 329166676Sjkim#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 330166676Sjkim#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 331166676Sjkim#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 332166676Sjkim#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 33384059Swpaul 334166676Sjkim#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 335166676Sjkim#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 336166676Sjkim#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 337166676Sjkim#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 338166676Sjkim#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 339166676Sjkim#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 340166676Sjkim#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 341166676Sjkim#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 34284059Swpaul 343166676Sjkim#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 344166676Sjkim#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 345166676Sjkim#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 346166676Sjkim#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 347166676Sjkim#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 348166676Sjkim#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 349166676Sjkim#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 350166676Sjkim#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 351166676Sjkim 35284059Swpaul/* 35384059Swpaul * PCI state register -- note, this register is read only 35484059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 35584059Swpaul * register is set. 35684059Swpaul */ 357166676Sjkim#define BGE_PCISTATE_FORCE_RESET 0x00000001 358166676Sjkim#define BGE_PCISTATE_INTR_STATE 0x00000002 359166676Sjkim#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 360166676Sjkim#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 361166676Sjkim#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 362166676Sjkim#define BGE_PCISTATE_WANT_EXPROM 0x00000020 363166676Sjkim#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 364166676Sjkim#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 365166676Sjkim#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 36684059Swpaul 36784059Swpaul/* 36884059Swpaul * PCI Clock Control register -- note, this register is read only 36984059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 37084059Swpaul * register is set. 37184059Swpaul */ 372166676Sjkim#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 373166676Sjkim#define BGE_PCICLOCKCTL_M66EN 0x00000080 374166676Sjkim#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 375166676Sjkim#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 376166676Sjkim#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 377166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 378166676Sjkim#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 379166676Sjkim#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 380166676Sjkim#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 381166676Sjkim#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 38284059Swpaul 38384059Swpaul 38484059Swpaul#ifndef PCIM_CMD_MWIEN 385166676Sjkim#define PCIM_CMD_MWIEN 0x0010 38684059Swpaul#endif 38784059Swpaul 38884059Swpaul/* 38984059Swpaul * High priority mailbox registers 39084059Swpaul * Each mailbox is 64-bits wide, though we only use the 39184059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 39284059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 39384059Swpaul * has been updated. 39484059Swpaul */ 395166676Sjkim#define BGE_MBX_IRQ0_HI 0x0200 396166676Sjkim#define BGE_MBX_IRQ0_LO 0x0204 397166676Sjkim#define BGE_MBX_IRQ1_HI 0x0208 398166676Sjkim#define BGE_MBX_IRQ1_LO 0x020C 399166676Sjkim#define BGE_MBX_IRQ2_HI 0x0210 400166676Sjkim#define BGE_MBX_IRQ2_LO 0x0214 401166676Sjkim#define BGE_MBX_IRQ3_HI 0x0218 402166676Sjkim#define BGE_MBX_IRQ3_LO 0x021C 403166676Sjkim#define BGE_MBX_GEN0_HI 0x0220 404166676Sjkim#define BGE_MBX_GEN0_LO 0x0224 405166676Sjkim#define BGE_MBX_GEN1_HI 0x0228 406166676Sjkim#define BGE_MBX_GEN1_LO 0x022C 407166676Sjkim#define BGE_MBX_GEN2_HI 0x0230 408166676Sjkim#define BGE_MBX_GEN2_LO 0x0234 409166676Sjkim#define BGE_MBX_GEN3_HI 0x0228 410166676Sjkim#define BGE_MBX_GEN3_LO 0x022C 411166676Sjkim#define BGE_MBX_GEN4_HI 0x0240 412166676Sjkim#define BGE_MBX_GEN4_LO 0x0244 413166676Sjkim#define BGE_MBX_GEN5_HI 0x0248 414166676Sjkim#define BGE_MBX_GEN5_LO 0x024C 415166676Sjkim#define BGE_MBX_GEN6_HI 0x0250 416166676Sjkim#define BGE_MBX_GEN6_LO 0x0254 417166676Sjkim#define BGE_MBX_GEN7_HI 0x0258 418166676Sjkim#define BGE_MBX_GEN7_LO 0x025C 419166676Sjkim#define BGE_MBX_RELOAD_STATS_HI 0x0260 420166676Sjkim#define BGE_MBX_RELOAD_STATS_LO 0x0264 421166676Sjkim#define BGE_MBX_RX_STD_PROD_HI 0x0268 422166676Sjkim#define BGE_MBX_RX_STD_PROD_LO 0x026C 423166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 424166676Sjkim#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 425166676Sjkim#define BGE_MBX_RX_MINI_PROD_HI 0x0278 426166676Sjkim#define BGE_MBX_RX_MINI_PROD_LO 0x027C 427166676Sjkim#define BGE_MBX_RX_CONS0_HI 0x0280 428166676Sjkim#define BGE_MBX_RX_CONS0_LO 0x0284 429166676Sjkim#define BGE_MBX_RX_CONS1_HI 0x0288 430166676Sjkim#define BGE_MBX_RX_CONS1_LO 0x028C 431166676Sjkim#define BGE_MBX_RX_CONS2_HI 0x0290 432166676Sjkim#define BGE_MBX_RX_CONS2_LO 0x0294 433166676Sjkim#define BGE_MBX_RX_CONS3_HI 0x0298 434166676Sjkim#define BGE_MBX_RX_CONS3_LO 0x029C 435166676Sjkim#define BGE_MBX_RX_CONS4_HI 0x02A0 436166676Sjkim#define BGE_MBX_RX_CONS4_LO 0x02A4 437166676Sjkim#define BGE_MBX_RX_CONS5_HI 0x02A8 438166676Sjkim#define BGE_MBX_RX_CONS5_LO 0x02AC 439166676Sjkim#define BGE_MBX_RX_CONS6_HI 0x02B0 440166676Sjkim#define BGE_MBX_RX_CONS6_LO 0x02B4 441166676Sjkim#define BGE_MBX_RX_CONS7_HI 0x02B8 442166676Sjkim#define BGE_MBX_RX_CONS7_LO 0x02BC 443166676Sjkim#define BGE_MBX_RX_CONS8_HI 0x02C0 444166676Sjkim#define BGE_MBX_RX_CONS8_LO 0x02C4 445166676Sjkim#define BGE_MBX_RX_CONS9_HI 0x02C8 446166676Sjkim#define BGE_MBX_RX_CONS9_LO 0x02CC 447166676Sjkim#define BGE_MBX_RX_CONS10_HI 0x02D0 448166676Sjkim#define BGE_MBX_RX_CONS10_LO 0x02D4 449166676Sjkim#define BGE_MBX_RX_CONS11_HI 0x02D8 450166676Sjkim#define BGE_MBX_RX_CONS11_LO 0x02DC 451166676Sjkim#define BGE_MBX_RX_CONS12_HI 0x02E0 452166676Sjkim#define BGE_MBX_RX_CONS12_LO 0x02E4 453166676Sjkim#define BGE_MBX_RX_CONS13_HI 0x02E8 454166676Sjkim#define BGE_MBX_RX_CONS13_LO 0x02EC 455166676Sjkim#define BGE_MBX_RX_CONS14_HI 0x02F0 456166676Sjkim#define BGE_MBX_RX_CONS14_LO 0x02F4 457166676Sjkim#define BGE_MBX_RX_CONS15_HI 0x02F8 458166676Sjkim#define BGE_MBX_RX_CONS15_LO 0x02FC 459166676Sjkim#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 460166676Sjkim#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 461166676Sjkim#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 462166676Sjkim#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 463166676Sjkim#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 464166676Sjkim#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 465166676Sjkim#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 466166676Sjkim#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 467166676Sjkim#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 468166676Sjkim#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 469166676Sjkim#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 470166676Sjkim#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 471166676Sjkim#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 472166676Sjkim#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 473166676Sjkim#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 474166676Sjkim#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 475166676Sjkim#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 476166676Sjkim#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 477166676Sjkim#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 478166676Sjkim#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 479166676Sjkim#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 480166676Sjkim#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 481166676Sjkim#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 482166676Sjkim#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 483166676Sjkim#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 484166676Sjkim#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 485166676Sjkim#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 486166676Sjkim#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 487166676Sjkim#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 488166676Sjkim#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 489166676Sjkim#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 490166676Sjkim#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 491166676Sjkim#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 492166676Sjkim#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 493166676Sjkim#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 494166676Sjkim#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 495166676Sjkim#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 496166676Sjkim#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 497166676Sjkim#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 498166676Sjkim#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 499166676Sjkim#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 500166676Sjkim#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 501166676Sjkim#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 502166676Sjkim#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 503166676Sjkim#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 504166676Sjkim#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 505166676Sjkim#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 506166676Sjkim#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 507166676Sjkim#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 508166676Sjkim#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 509166676Sjkim#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 510166676Sjkim#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 511166676Sjkim#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 512166676Sjkim#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 513166676Sjkim#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 514166676Sjkim#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 515166676Sjkim#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 516166676Sjkim#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 517166676Sjkim#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 518166676Sjkim#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 519166676Sjkim#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 520166676Sjkim#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 521166676Sjkim#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 522166676Sjkim#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 52384059Swpaul 524166676Sjkim#define BGE_TX_RINGS_MAX 4 525166676Sjkim#define BGE_TX_RINGS_EXTSSRAM_MAX 16 526166676Sjkim#define BGE_RX_RINGS_MAX 16 52784059Swpaul 52884059Swpaul/* Ethernet MAC control registers */ 529166676Sjkim#define BGE_MAC_MODE 0x0400 530166676Sjkim#define BGE_MAC_STS 0x0404 531166676Sjkim#define BGE_MAC_EVT_ENB 0x0408 532166676Sjkim#define BGE_MAC_LED_CTL 0x040C 533166676Sjkim#define BGE_MAC_ADDR1_LO 0x0410 534166676Sjkim#define BGE_MAC_ADDR1_HI 0x0414 535166676Sjkim#define BGE_MAC_ADDR2_LO 0x0418 536166676Sjkim#define BGE_MAC_ADDR2_HI 0x041C 537166676Sjkim#define BGE_MAC_ADDR3_LO 0x0420 538166676Sjkim#define BGE_MAC_ADDR3_HI 0x0424 539166676Sjkim#define BGE_MAC_ADDR4_LO 0x0428 540166676Sjkim#define BGE_MAC_ADDR4_HI 0x042C 541166676Sjkim#define BGE_WOL_PATPTR 0x0430 542166676Sjkim#define BGE_WOL_PATCFG 0x0434 543166676Sjkim#define BGE_TX_RANDOM_BACKOFF 0x0438 544166676Sjkim#define BGE_RX_MTU 0x043C 545166676Sjkim#define BGE_GBIT_PCS_TEST 0x0440 546166676Sjkim#define BGE_TX_TBI_AUTONEG 0x0444 547166676Sjkim#define BGE_RX_TBI_AUTONEG 0x0448 548166676Sjkim#define BGE_MI_COMM 0x044C 549166676Sjkim#define BGE_MI_STS 0x0450 550166676Sjkim#define BGE_MI_MODE 0x0454 551166676Sjkim#define BGE_AUTOPOLL_STS 0x0458 552166676Sjkim#define BGE_TX_MODE 0x045C 553166676Sjkim#define BGE_TX_STS 0x0460 554166676Sjkim#define BGE_TX_LENGTHS 0x0464 555166676Sjkim#define BGE_RX_MODE 0x0468 556166676Sjkim#define BGE_RX_STS 0x046C 557166676Sjkim#define BGE_MAR0 0x0470 558166676Sjkim#define BGE_MAR1 0x0474 559166676Sjkim#define BGE_MAR2 0x0478 560166676Sjkim#define BGE_MAR3 0x047C 561166676Sjkim#define BGE_RX_BD_RULES_CTL0 0x0480 562166676Sjkim#define BGE_RX_BD_RULES_MASKVAL0 0x0484 563166676Sjkim#define BGE_RX_BD_RULES_CTL1 0x0488 564166676Sjkim#define BGE_RX_BD_RULES_MASKVAL1 0x048C 565166676Sjkim#define BGE_RX_BD_RULES_CTL2 0x0490 566166676Sjkim#define BGE_RX_BD_RULES_MASKVAL2 0x0494 567166676Sjkim#define BGE_RX_BD_RULES_CTL3 0x0498 568166676Sjkim#define BGE_RX_BD_RULES_MASKVAL3 0x049C 569166676Sjkim#define BGE_RX_BD_RULES_CTL4 0x04A0 570166676Sjkim#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 571166676Sjkim#define BGE_RX_BD_RULES_CTL5 0x04A8 572166676Sjkim#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 573166676Sjkim#define BGE_RX_BD_RULES_CTL6 0x04B0 574166676Sjkim#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 575166676Sjkim#define BGE_RX_BD_RULES_CTL7 0x04B8 576166676Sjkim#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 577166676Sjkim#define BGE_RX_BD_RULES_CTL8 0x04C0 578166676Sjkim#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 579166676Sjkim#define BGE_RX_BD_RULES_CTL9 0x04C8 580166676Sjkim#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 581166676Sjkim#define BGE_RX_BD_RULES_CTL10 0x04D0 582166676Sjkim#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 583166676Sjkim#define BGE_RX_BD_RULES_CTL11 0x04D8 584166676Sjkim#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 585166676Sjkim#define BGE_RX_BD_RULES_CTL12 0x04E0 586166676Sjkim#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 587166676Sjkim#define BGE_RX_BD_RULES_CTL13 0x04E8 588166676Sjkim#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 589166676Sjkim#define BGE_RX_BD_RULES_CTL14 0x04F0 590166676Sjkim#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 591166676Sjkim#define BGE_RX_BD_RULES_CTL15 0x04F8 592166676Sjkim#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 593166676Sjkim#define BGE_RX_RULES_CFG 0x0500 594166676Sjkim#define BGE_SERDES_CFG 0x0590 595166676Sjkim#define BGE_SERDES_STS 0x0594 596166676Sjkim#define BGE_SGDIG_CFG 0x05B0 597166676Sjkim#define BGE_SGDIG_STS 0x05B4 598166676Sjkim#define BGE_MAC_STATS 0x0800 59984059Swpaul 60084059Swpaul/* Ethernet MAC Mode register */ 601166676Sjkim#define BGE_MACMODE_RESET 0x00000001 602166676Sjkim#define BGE_MACMODE_HALF_DUPLEX 0x00000002 603166676Sjkim#define BGE_MACMODE_PORTMODE 0x0000000C 604166676Sjkim#define BGE_MACMODE_LOOPBACK 0x00000010 605166676Sjkim#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 606166676Sjkim#define BGE_MACMODE_TX_BURST_ENB 0x00000100 607166676Sjkim#define BGE_MACMODE_MAX_DEFER 0x00000200 608166676Sjkim#define BGE_MACMODE_LINK_POLARITY 0x00000400 609166676Sjkim#define BGE_MACMODE_RX_STATS_ENB 0x00000800 610166676Sjkim#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 611166676Sjkim#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 612166676Sjkim#define BGE_MACMODE_TX_STATS_ENB 0x00004000 613166676Sjkim#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 614166676Sjkim#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 615166676Sjkim#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 616166676Sjkim#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 617166676Sjkim#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 618166676Sjkim#define BGE_MACMODE_MIP_ENB 0x00100000 619166676Sjkim#define BGE_MACMODE_TXDMA_ENB 0x00200000 620166676Sjkim#define BGE_MACMODE_RXDMA_ENB 0x00400000 621166676Sjkim#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 62284059Swpaul 623166676Sjkim#define BGE_PORTMODE_NONE 0x00000000 624166676Sjkim#define BGE_PORTMODE_MII 0x00000004 625166676Sjkim#define BGE_PORTMODE_GMII 0x00000008 626166676Sjkim#define BGE_PORTMODE_TBI 0x0000000C 62784059Swpaul 62884059Swpaul/* MAC Status register */ 629166676Sjkim#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 630166676Sjkim#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 631166676Sjkim#define BGE_MACSTAT_RX_CFG 0x00000004 632166676Sjkim#define BGE_MACSTAT_CFG_CHANGED 0x00000008 633166676Sjkim#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 634166676Sjkim#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 635166676Sjkim#define BGE_MACSTAT_LINK_CHANGED 0x00001000 636166676Sjkim#define BGE_MACSTAT_MI_COMPLETE 0x00400000 637166676Sjkim#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 638166676Sjkim#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 639166676Sjkim#define BGE_MACSTAT_ODI_ERROR 0x02000000 640166676Sjkim#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 641166676Sjkim#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 64284059Swpaul 64384059Swpaul/* MAC Event Enable Register */ 644166676Sjkim#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 645166676Sjkim#define BGE_EVTENB_LINK_CHANGED 0x00001000 646166676Sjkim#define BGE_EVTENB_MI_COMPLETE 0x00400000 647166676Sjkim#define BGE_EVTENB_MI_INTERRUPT 0x00800000 648166676Sjkim#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 649166676Sjkim#define BGE_EVTENB_ODI_ERROR 0x02000000 650166676Sjkim#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 651166676Sjkim#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 65284059Swpaul 65384059Swpaul/* LED Control Register */ 654166676Sjkim#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 655166676Sjkim#define BGE_LEDCTL_1000MBPS_LED 0x00000002 656166676Sjkim#define BGE_LEDCTL_100MBPS_LED 0x00000004 657166676Sjkim#define BGE_LEDCTL_10MBPS_LED 0x00000008 658166676Sjkim#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 659166676Sjkim#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 660166676Sjkim#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 661166676Sjkim#define BGE_LEDCTL_1000MBPS_STS 0x00000080 662166676Sjkim#define BGE_LEDCTL_100MBPS_STS 0x00000100 663166676Sjkim#define BGE_LEDCTL_10MBPS_STS 0x00000200 664166676Sjkim#define BGE_LEDCTL_TRADLED_STS 0x00000400 665166676Sjkim#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 666166676Sjkim#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 66784059Swpaul 66884059Swpaul/* TX backoff seed register */ 669166676Sjkim#define BGE_TX_BACKOFF_SEED_MASK 0x3F 67084059Swpaul 67184059Swpaul/* Autopoll status register */ 672166676Sjkim#define BGE_AUTOPOLLSTS_ERROR 0x00000001 67384059Swpaul 67484059Swpaul/* Transmit MAC mode register */ 675166676Sjkim#define BGE_TXMODE_RESET 0x00000001 676166676Sjkim#define BGE_TXMODE_ENABLE 0x00000002 677166676Sjkim#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 678166676Sjkim#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 679166676Sjkim#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 68084059Swpaul 68184059Swpaul/* Transmit MAC status register */ 682166676Sjkim#define BGE_TXSTAT_RX_XOFFED 0x00000001 683166676Sjkim#define BGE_TXSTAT_SENT_XOFF 0x00000002 684166676Sjkim#define BGE_TXSTAT_SENT_XON 0x00000004 685166676Sjkim#define BGE_TXSTAT_LINK_UP 0x00000008 686166676Sjkim#define BGE_TXSTAT_ODI_UFLOW 0x00000010 687166676Sjkim#define BGE_TXSTAT_ODI_OFLOW 0x00000020 68884059Swpaul 68984059Swpaul/* Transmit MAC lengths register */ 690166676Sjkim#define BGE_TXLEN_SLOTTIME 0x000000FF 691166676Sjkim#define BGE_TXLEN_IPG 0x00000F00 692166676Sjkim#define BGE_TXLEN_CRS 0x00003000 69384059Swpaul 69484059Swpaul/* Receive MAC mode register */ 695166676Sjkim#define BGE_RXMODE_RESET 0x00000001 696166676Sjkim#define BGE_RXMODE_ENABLE 0x00000002 697166676Sjkim#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 698166676Sjkim#define BGE_RXMODE_RX_GIANTS 0x00000020 699166676Sjkim#define BGE_RXMODE_RX_RUNTS 0x00000040 700166676Sjkim#define BGE_RXMODE_8022_LENCHECK 0x00000080 701166676Sjkim#define BGE_RXMODE_RX_PROMISC 0x00000100 702166676Sjkim#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 703166676Sjkim#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 70484059Swpaul 70584059Swpaul/* Receive MAC status register */ 706166676Sjkim#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 707166676Sjkim#define BGE_RXSTAT_RCVD_XOFF 0x00000002 708166676Sjkim#define BGE_RXSTAT_RCVD_XON 0x00000004 70984059Swpaul 71084059Swpaul/* Receive Rules Control register */ 711166676Sjkim#define BGE_RXRULECTL_OFFSET 0x000000FF 712166676Sjkim#define BGE_RXRULECTL_CLASS 0x00001F00 713166676Sjkim#define BGE_RXRULECTL_HDRTYPE 0x0000E000 714166676Sjkim#define BGE_RXRULECTL_COMPARE_OP 0x00030000 715166676Sjkim#define BGE_RXRULECTL_MAP 0x01000000 716166676Sjkim#define BGE_RXRULECTL_DISCARD 0x02000000 717166676Sjkim#define BGE_RXRULECTL_MASK 0x04000000 718166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 719166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 720166676Sjkim#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 721166676Sjkim#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 72284059Swpaul 72384059Swpaul/* Receive Rules Mask register */ 724166676Sjkim#define BGE_RXRULEMASK_VALUE 0x0000FFFF 725166676Sjkim#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 72684059Swpaul 727130273Swpaul/* SERDES configuration register */ 728166676Sjkim#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 729166676Sjkim#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 730166676Sjkim#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 731166676Sjkim#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 732166676Sjkim#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 733166676Sjkim#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 734166676Sjkim#define BGE_SERDESCFG_TXMODE 0x00001000 735166676Sjkim#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 736166676Sjkim#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 737166676Sjkim#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 738166676Sjkim#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 739166676Sjkim#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 740166676Sjkim#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 741166676Sjkim#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 742166676Sjkim#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 743166676Sjkim#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 744130273Swpaul 745130273Swpaul/* SERDES status register */ 746166676Sjkim#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 747166676Sjkim#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 748130273Swpaul 749130273Swpaul/* SGDIG config (not documented) */ 750166676Sjkim#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 751166676Sjkim#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 752166676Sjkim#define BGE_SGDIGCFG_SEND 0x40000000 753166676Sjkim#define BGE_SGDIGCFG_AUTO 0x80000000 754130273Swpaul 755130273Swpaul/* SGDIG status (not documented) */ 756166676Sjkim#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 757166676Sjkim#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 758166676Sjkim#define BGE_SGDIGSTS_DONE 0x00000002 759130273Swpaul 760130273Swpaul 76184059Swpaul/* MI communication register */ 762166676Sjkim#define BGE_MICOMM_DATA 0x0000FFFF 763166676Sjkim#define BGE_MICOMM_REG 0x001F0000 764166676Sjkim#define BGE_MICOMM_PHY 0x03E00000 765166676Sjkim#define BGE_MICOMM_CMD 0x0C000000 766166676Sjkim#define BGE_MICOMM_READFAIL 0x10000000 767166676Sjkim#define BGE_MICOMM_BUSY 0x20000000 76884059Swpaul 769166676Sjkim#define BGE_MIREG(x) ((x & 0x1F) << 16) 770166676Sjkim#define BGE_MIPHY(x) ((x & 0x1F) << 21) 771166676Sjkim#define BGE_MICMD_WRITE 0x04000000 772166676Sjkim#define BGE_MICMD_READ 0x08000000 77384059Swpaul 77484059Swpaul/* MI status register */ 775166676Sjkim#define BGE_MISTS_LINK 0x00000001 776166676Sjkim#define BGE_MISTS_10MBPS 0x00000002 77784059Swpaul 778166676Sjkim#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 779166676Sjkim#define BGE_MIMODE_AUTOPOLL 0x00000010 780166676Sjkim#define BGE_MIMODE_CLKCNT 0x001F0000 78184059Swpaul 78284059Swpaul 78384059Swpaul/* 78484059Swpaul * Send data initiator control registers. 78584059Swpaul */ 786166676Sjkim#define BGE_SDI_MODE 0x0C00 787166676Sjkim#define BGE_SDI_STATUS 0x0C04 788166676Sjkim#define BGE_SDI_STATS_CTL 0x0C08 789166676Sjkim#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 790166676Sjkim#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 791166676Sjkim#define BGE_LOCSTATS_COS0 0x0C80 792166676Sjkim#define BGE_LOCSTATS_COS1 0x0C84 793166676Sjkim#define BGE_LOCSTATS_COS2 0x0C88 794166676Sjkim#define BGE_LOCSTATS_COS3 0x0C8C 795166676Sjkim#define BGE_LOCSTATS_COS4 0x0C90 796166676Sjkim#define BGE_LOCSTATS_COS5 0x0C84 797166676Sjkim#define BGE_LOCSTATS_COS6 0x0C98 798166676Sjkim#define BGE_LOCSTATS_COS7 0x0C9C 799166676Sjkim#define BGE_LOCSTATS_COS8 0x0CA0 800166676Sjkim#define BGE_LOCSTATS_COS9 0x0CA4 801166676Sjkim#define BGE_LOCSTATS_COS10 0x0CA8 802166676Sjkim#define BGE_LOCSTATS_COS11 0x0CAC 803166676Sjkim#define BGE_LOCSTATS_COS12 0x0CB0 804166676Sjkim#define BGE_LOCSTATS_COS13 0x0CB4 805166676Sjkim#define BGE_LOCSTATS_COS14 0x0CB8 806166676Sjkim#define BGE_LOCSTATS_COS15 0x0CBC 807166676Sjkim#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 808166676Sjkim#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 809166676Sjkim#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 810166676Sjkim#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 811166676Sjkim#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 812166676Sjkim#define BGE_LOCSTATS_IRQS 0x0CD4 813166676Sjkim#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 814166676Sjkim#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 81584059Swpaul 81684059Swpaul/* Send Data Initiator mode register */ 817166676Sjkim#define BGE_SDIMODE_RESET 0x00000001 818166676Sjkim#define BGE_SDIMODE_ENABLE 0x00000002 819166676Sjkim#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 82084059Swpaul 82184059Swpaul/* Send Data Initiator stats register */ 822166676Sjkim#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 82384059Swpaul 82484059Swpaul/* Send Data Initiator stats control register */ 825166676Sjkim#define BGE_SDISTATSCTL_ENABLE 0x00000001 826166676Sjkim#define BGE_SDISTATSCTL_FASTER 0x00000002 827166676Sjkim#define BGE_SDISTATSCTL_CLEAR 0x00000004 828166676Sjkim#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 829166676Sjkim#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 83084059Swpaul 83184059Swpaul/* 83284059Swpaul * Send Data Completion Control registers 83384059Swpaul */ 834166676Sjkim#define BGE_SDC_MODE 0x1000 835166676Sjkim#define BGE_SDC_STATUS 0x1004 83684059Swpaul 83784059Swpaul/* Send Data completion mode register */ 838166676Sjkim#define BGE_SDCMODE_RESET 0x00000001 839166676Sjkim#define BGE_SDCMODE_ENABLE 0x00000002 840166676Sjkim#define BGE_SDCMODE_ATTN 0x00000004 84184059Swpaul 84284059Swpaul/* Send Data completion status register */ 843166676Sjkim#define BGE_SDCSTAT_ATTN 0x00000004 84484059Swpaul 84584059Swpaul/* 84684059Swpaul * Send BD Ring Selector Control registers 84784059Swpaul */ 848166676Sjkim#define BGE_SRS_MODE 0x1400 849166676Sjkim#define BGE_SRS_STATUS 0x1404 850166676Sjkim#define BGE_SRS_HWDIAG 0x1408 851166676Sjkim#define BGE_SRS_LOC_NIC_CONS0 0x1440 852166676Sjkim#define BGE_SRS_LOC_NIC_CONS1 0x1444 853166676Sjkim#define BGE_SRS_LOC_NIC_CONS2 0x1448 854166676Sjkim#define BGE_SRS_LOC_NIC_CONS3 0x144C 855166676Sjkim#define BGE_SRS_LOC_NIC_CONS4 0x1450 856166676Sjkim#define BGE_SRS_LOC_NIC_CONS5 0x1454 857166676Sjkim#define BGE_SRS_LOC_NIC_CONS6 0x1458 858166676Sjkim#define BGE_SRS_LOC_NIC_CONS7 0x145C 859166676Sjkim#define BGE_SRS_LOC_NIC_CONS8 0x1460 860166676Sjkim#define BGE_SRS_LOC_NIC_CONS9 0x1464 861166676Sjkim#define BGE_SRS_LOC_NIC_CONS10 0x1468 862166676Sjkim#define BGE_SRS_LOC_NIC_CONS11 0x146C 863166676Sjkim#define BGE_SRS_LOC_NIC_CONS12 0x1470 864166676Sjkim#define BGE_SRS_LOC_NIC_CONS13 0x1474 865166676Sjkim#define BGE_SRS_LOC_NIC_CONS14 0x1478 866166676Sjkim#define BGE_SRS_LOC_NIC_CONS15 0x147C 86784059Swpaul 86884059Swpaul/* Send BD Ring Selector Mode register */ 869166676Sjkim#define BGE_SRSMODE_RESET 0x00000001 870166676Sjkim#define BGE_SRSMODE_ENABLE 0x00000002 871166676Sjkim#define BGE_SRSMODE_ATTN 0x00000004 87284059Swpaul 87384059Swpaul/* Send BD Ring Selector Status register */ 874166676Sjkim#define BGE_SRSSTAT_ERROR 0x00000004 87584059Swpaul 87684059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 877166676Sjkim#define BGE_SRSHWDIAG_STATE 0x0000000F 878166676Sjkim#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 879166676Sjkim#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 880166676Sjkim#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 88184059Swpaul 88284059Swpaul/* 88384059Swpaul * Send BD Initiator Selector Control registers 88484059Swpaul */ 885166676Sjkim#define BGE_SBDI_MODE 0x1800 886166676Sjkim#define BGE_SBDI_STATUS 0x1804 887166676Sjkim#define BGE_SBDI_LOC_NIC_PROD0 0x1808 888166676Sjkim#define BGE_SBDI_LOC_NIC_PROD1 0x180C 889166676Sjkim#define BGE_SBDI_LOC_NIC_PROD2 0x1810 890166676Sjkim#define BGE_SBDI_LOC_NIC_PROD3 0x1814 891166676Sjkim#define BGE_SBDI_LOC_NIC_PROD4 0x1818 892166676Sjkim#define BGE_SBDI_LOC_NIC_PROD5 0x181C 893166676Sjkim#define BGE_SBDI_LOC_NIC_PROD6 0x1820 894166676Sjkim#define BGE_SBDI_LOC_NIC_PROD7 0x1824 895166676Sjkim#define BGE_SBDI_LOC_NIC_PROD8 0x1828 896166676Sjkim#define BGE_SBDI_LOC_NIC_PROD9 0x182C 897166676Sjkim#define BGE_SBDI_LOC_NIC_PROD10 0x1830 898166676Sjkim#define BGE_SBDI_LOC_NIC_PROD11 0x1834 899166676Sjkim#define BGE_SBDI_LOC_NIC_PROD12 0x1838 900166676Sjkim#define BGE_SBDI_LOC_NIC_PROD13 0x183C 901166676Sjkim#define BGE_SBDI_LOC_NIC_PROD14 0x1840 902166676Sjkim#define BGE_SBDI_LOC_NIC_PROD15 0x1844 90384059Swpaul 90484059Swpaul/* Send BD Initiator Mode register */ 905166676Sjkim#define BGE_SBDIMODE_RESET 0x00000001 906166676Sjkim#define BGE_SBDIMODE_ENABLE 0x00000002 907166676Sjkim#define BGE_SBDIMODE_ATTN 0x00000004 90884059Swpaul 90984059Swpaul/* Send BD Initiator Status register */ 910166676Sjkim#define BGE_SBDISTAT_ERROR 0x00000004 91184059Swpaul 91284059Swpaul/* 91384059Swpaul * Send BD Completion Control registers 91484059Swpaul */ 915166676Sjkim#define BGE_SBDC_MODE 0x1C00 916166676Sjkim#define BGE_SBDC_STATUS 0x1C04 91784059Swpaul 91884059Swpaul/* Send BD Completion Control Mode register */ 919166676Sjkim#define BGE_SBDCMODE_RESET 0x00000001 920166676Sjkim#define BGE_SBDCMODE_ENABLE 0x00000002 921166676Sjkim#define BGE_SBDCMODE_ATTN 0x00000004 92284059Swpaul 92384059Swpaul/* Send BD Completion Control Status register */ 924166676Sjkim#define BGE_SBDCSTAT_ATTN 0x00000004 92584059Swpaul 92684059Swpaul/* 92784059Swpaul * Receive List Placement Control registers 92884059Swpaul */ 929166676Sjkim#define BGE_RXLP_MODE 0x2000 930166676Sjkim#define BGE_RXLP_STATUS 0x2004 931166676Sjkim#define BGE_RXLP_SEL_LIST_LOCK 0x2008 932166676Sjkim#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 933166676Sjkim#define BGE_RXLP_CFG 0x2010 934166676Sjkim#define BGE_RXLP_STATS_CTL 0x2014 935166676Sjkim#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 936166676Sjkim#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 937166676Sjkim#define BGE_RXLP_HEAD0 0x2100 938166676Sjkim#define BGE_RXLP_TAIL0 0x2104 939166676Sjkim#define BGE_RXLP_COUNT0 0x2108 940166676Sjkim#define BGE_RXLP_HEAD1 0x2110 941166676Sjkim#define BGE_RXLP_TAIL1 0x2114 942166676Sjkim#define BGE_RXLP_COUNT1 0x2118 943166676Sjkim#define BGE_RXLP_HEAD2 0x2120 944166676Sjkim#define BGE_RXLP_TAIL2 0x2124 945166676Sjkim#define BGE_RXLP_COUNT2 0x2128 946166676Sjkim#define BGE_RXLP_HEAD3 0x2130 947166676Sjkim#define BGE_RXLP_TAIL3 0x2134 948166676Sjkim#define BGE_RXLP_COUNT3 0x2138 949166676Sjkim#define BGE_RXLP_HEAD4 0x2140 950166676Sjkim#define BGE_RXLP_TAIL4 0x2144 951166676Sjkim#define BGE_RXLP_COUNT4 0x2148 952166676Sjkim#define BGE_RXLP_HEAD5 0x2150 953166676Sjkim#define BGE_RXLP_TAIL5 0x2154 954166676Sjkim#define BGE_RXLP_COUNT5 0x2158 955166676Sjkim#define BGE_RXLP_HEAD6 0x2160 956166676Sjkim#define BGE_RXLP_TAIL6 0x2164 957166676Sjkim#define BGE_RXLP_COUNT6 0x2168 958166676Sjkim#define BGE_RXLP_HEAD7 0x2170 959166676Sjkim#define BGE_RXLP_TAIL7 0x2174 960166676Sjkim#define BGE_RXLP_COUNT7 0x2178 961166676Sjkim#define BGE_RXLP_HEAD8 0x2180 962166676Sjkim#define BGE_RXLP_TAIL8 0x2184 963166676Sjkim#define BGE_RXLP_COUNT8 0x2188 964166676Sjkim#define BGE_RXLP_HEAD9 0x2190 965166676Sjkim#define BGE_RXLP_TAIL9 0x2194 966166676Sjkim#define BGE_RXLP_COUNT9 0x2198 967166676Sjkim#define BGE_RXLP_HEAD10 0x21A0 968166676Sjkim#define BGE_RXLP_TAIL10 0x21A4 969166676Sjkim#define BGE_RXLP_COUNT10 0x21A8 970166676Sjkim#define BGE_RXLP_HEAD11 0x21B0 971166676Sjkim#define BGE_RXLP_TAIL11 0x21B4 972166676Sjkim#define BGE_RXLP_COUNT11 0x21B8 973166676Sjkim#define BGE_RXLP_HEAD12 0x21C0 974166676Sjkim#define BGE_RXLP_TAIL12 0x21C4 975166676Sjkim#define BGE_RXLP_COUNT12 0x21C8 976166676Sjkim#define BGE_RXLP_HEAD13 0x21D0 977166676Sjkim#define BGE_RXLP_TAIL13 0x21D4 978166676Sjkim#define BGE_RXLP_COUNT13 0x21D8 979166676Sjkim#define BGE_RXLP_HEAD14 0x21E0 980166676Sjkim#define BGE_RXLP_TAIL14 0x21E4 981166676Sjkim#define BGE_RXLP_COUNT14 0x21E8 982166676Sjkim#define BGE_RXLP_HEAD15 0x21F0 983166676Sjkim#define BGE_RXLP_TAIL15 0x21F4 984166676Sjkim#define BGE_RXLP_COUNT15 0x21F8 985166676Sjkim#define BGE_RXLP_LOCSTAT_COS0 0x2200 986166676Sjkim#define BGE_RXLP_LOCSTAT_COS1 0x2204 987166676Sjkim#define BGE_RXLP_LOCSTAT_COS2 0x2208 988166676Sjkim#define BGE_RXLP_LOCSTAT_COS3 0x220C 989166676Sjkim#define BGE_RXLP_LOCSTAT_COS4 0x2210 990166676Sjkim#define BGE_RXLP_LOCSTAT_COS5 0x2214 991166676Sjkim#define BGE_RXLP_LOCSTAT_COS6 0x2218 992166676Sjkim#define BGE_RXLP_LOCSTAT_COS7 0x221C 993166676Sjkim#define BGE_RXLP_LOCSTAT_COS8 0x2220 994166676Sjkim#define BGE_RXLP_LOCSTAT_COS9 0x2224 995166676Sjkim#define BGE_RXLP_LOCSTAT_COS10 0x2228 996166676Sjkim#define BGE_RXLP_LOCSTAT_COS11 0x222C 997166676Sjkim#define BGE_RXLP_LOCSTAT_COS12 0x2230 998166676Sjkim#define BGE_RXLP_LOCSTAT_COS13 0x2234 999166676Sjkim#define BGE_RXLP_LOCSTAT_COS14 0x2238 1000166676Sjkim#define BGE_RXLP_LOCSTAT_COS15 0x223C 1001166676Sjkim#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1002166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1003166676Sjkim#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1004166676Sjkim#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1005166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1006166676Sjkim#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1007166676Sjkim#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 100884059Swpaul 100984059Swpaul 101084059Swpaul/* Receive List Placement mode register */ 1011166676Sjkim#define BGE_RXLPMODE_RESET 0x00000001 1012166676Sjkim#define BGE_RXLPMODE_ENABLE 0x00000002 1013166676Sjkim#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1014166676Sjkim#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1015166676Sjkim#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 101684059Swpaul 101784059Swpaul/* Receive List Placement Status register */ 1018166676Sjkim#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1019166676Sjkim#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1020166676Sjkim#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 102184059Swpaul 102284059Swpaul/* 102384059Swpaul * Receive Data and Receive BD Initiator Control Registers 102484059Swpaul */ 1025166676Sjkim#define BGE_RDBDI_MODE 0x2400 1026166676Sjkim#define BGE_RDBDI_STATUS 0x2404 1027166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1028166676Sjkim#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1029166676Sjkim#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1030166676Sjkim#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1031166676Sjkim#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1032166676Sjkim#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1033166676Sjkim#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1034166676Sjkim#define BGE_RX_STD_RCB_NICADDR 0x245C 1035166676Sjkim#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1036166676Sjkim#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1037166676Sjkim#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1038166676Sjkim#define BGE_RX_MINI_RCB_NICADDR 0x246C 1039166676Sjkim#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1040166676Sjkim#define BGE_RDBDI_STD_RX_CONS 0x2474 1041166676Sjkim#define BGE_RDBDI_MINI_RX_CONS 0x2478 1042166676Sjkim#define BGE_RDBDI_RETURN_PROD0 0x2480 1043166676Sjkim#define BGE_RDBDI_RETURN_PROD1 0x2484 1044166676Sjkim#define BGE_RDBDI_RETURN_PROD2 0x2488 1045166676Sjkim#define BGE_RDBDI_RETURN_PROD3 0x248C 1046166676Sjkim#define BGE_RDBDI_RETURN_PROD4 0x2490 1047166676Sjkim#define BGE_RDBDI_RETURN_PROD5 0x2494 1048166676Sjkim#define BGE_RDBDI_RETURN_PROD6 0x2498 1049166676Sjkim#define BGE_RDBDI_RETURN_PROD7 0x249C 1050166676Sjkim#define BGE_RDBDI_RETURN_PROD8 0x24A0 1051166676Sjkim#define BGE_RDBDI_RETURN_PROD9 0x24A4 1052166676Sjkim#define BGE_RDBDI_RETURN_PROD10 0x24A8 1053166676Sjkim#define BGE_RDBDI_RETURN_PROD11 0x24AC 1054166676Sjkim#define BGE_RDBDI_RETURN_PROD12 0x24B0 1055166676Sjkim#define BGE_RDBDI_RETURN_PROD13 0x24B4 1056166676Sjkim#define BGE_RDBDI_RETURN_PROD14 0x24B8 1057166676Sjkim#define BGE_RDBDI_RETURN_PROD15 0x24BC 1058166676Sjkim#define BGE_RDBDI_HWDIAG 0x24C0 105984059Swpaul 106084059Swpaul 106184059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 1062166676Sjkim#define BGE_RDBDIMODE_RESET 0x00000001 1063166676Sjkim#define BGE_RDBDIMODE_ENABLE 0x00000002 1064166676Sjkim#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1065166676Sjkim#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1066166676Sjkim#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 106784059Swpaul 106884059Swpaul/* Receive Data and Receive BD Initiator Status register */ 1069166676Sjkim#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1070166676Sjkim#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1071166676Sjkim#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 107284059Swpaul 107384059Swpaul 107484059Swpaul/* 107584059Swpaul * Receive Data Completion Control registers 107684059Swpaul */ 1077166676Sjkim#define BGE_RDC_MODE 0x2800 107884059Swpaul 107984059Swpaul/* Receive Data Completion Mode register */ 1080166676Sjkim#define BGE_RDCMODE_RESET 0x00000001 1081166676Sjkim#define BGE_RDCMODE_ENABLE 0x00000002 1082166676Sjkim#define BGE_RDCMODE_ATTN 0x00000004 108384059Swpaul 108484059Swpaul/* 108584059Swpaul * Receive BD Initiator Control registers 108684059Swpaul */ 1087166676Sjkim#define BGE_RBDI_MODE 0x2C00 1088166676Sjkim#define BGE_RBDI_STATUS 0x2C04 1089166676Sjkim#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1090166676Sjkim#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1091166676Sjkim#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1092166676Sjkim#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1093166676Sjkim#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1094166676Sjkim#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 109584059Swpaul 109684059Swpaul/* Receive BD Initiator Mode register */ 1097166676Sjkim#define BGE_RBDIMODE_RESET 0x00000001 1098166676Sjkim#define BGE_RBDIMODE_ENABLE 0x00000002 1099166676Sjkim#define BGE_RBDIMODE_ATTN 0x00000004 110084059Swpaul 110184059Swpaul/* Receive BD Initiator Status register */ 1102166676Sjkim#define BGE_RBDISTAT_ATTN 0x00000004 110384059Swpaul 110484059Swpaul/* 110584059Swpaul * Receive BD Completion Control registers 110684059Swpaul */ 1107166676Sjkim#define BGE_RBDC_MODE 0x3000 1108166676Sjkim#define BGE_RBDC_STATUS 0x3004 1109166676Sjkim#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1110166676Sjkim#define BGE_RBDC_STD_BD_PROD 0x300C 1111166676Sjkim#define BGE_RBDC_MINI_BD_PROD 0x3010 111284059Swpaul 111384059Swpaul/* Receive BD completion mode register */ 1114166676Sjkim#define BGE_RBDCMODE_RESET 0x00000001 1115166676Sjkim#define BGE_RBDCMODE_ENABLE 0x00000002 1116166676Sjkim#define BGE_RBDCMODE_ATTN 0x00000004 111784059Swpaul 111884059Swpaul/* Receive BD completion status register */ 1119166676Sjkim#define BGE_RBDCSTAT_ERROR 0x00000004 112084059Swpaul 112184059Swpaul/* 112284059Swpaul * Receive List Selector Control registers 112384059Swpaul */ 1124166676Sjkim#define BGE_RXLS_MODE 0x3400 1125166676Sjkim#define BGE_RXLS_STATUS 0x3404 112684059Swpaul 112784059Swpaul/* Receive List Selector Mode register */ 1128166676Sjkim#define BGE_RXLSMODE_RESET 0x00000001 1129166676Sjkim#define BGE_RXLSMODE_ENABLE 0x00000002 1130166676Sjkim#define BGE_RXLSMODE_ATTN 0x00000004 113184059Swpaul 113284059Swpaul/* Receive List Selector Status register */ 1133166676Sjkim#define BGE_RXLSSTAT_ERROR 0x00000004 113484059Swpaul 113584059Swpaul/* 113684059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 113784059Swpaul */ 1138166676Sjkim#define BGE_MBCF_MODE 0x3800 1139166676Sjkim#define BGE_MBCF_STATUS 0x3804 114084059Swpaul 114184059Swpaul/* Mbuf Cluster Free mode register */ 1142166676Sjkim#define BGE_MBCFMODE_RESET 0x00000001 1143166676Sjkim#define BGE_MBCFMODE_ENABLE 0x00000002 1144166676Sjkim#define BGE_MBCFMODE_ATTN 0x00000004 114584059Swpaul 114684059Swpaul/* Mbuf Cluster Free status register */ 1147166676Sjkim#define BGE_MBCFSTAT_ERROR 0x00000004 114884059Swpaul 114984059Swpaul/* 115084059Swpaul * Host Coalescing Control registers 115184059Swpaul */ 1152166676Sjkim#define BGE_HCC_MODE 0x3C00 1153166676Sjkim#define BGE_HCC_STATUS 0x3C04 1154166676Sjkim#define BGE_HCC_RX_COAL_TICKS 0x3C08 1155166676Sjkim#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1156166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1157166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1158166676Sjkim#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1159166676Sjkim#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1160166676Sjkim#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1161166676Sjkim#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1162166676Sjkim#define BGE_HCC_STATS_TICKS 0x3C28 1163166676Sjkim#define BGE_HCC_STATS_ADDR_HI 0x3C30 1164166676Sjkim#define BGE_HCC_STATS_ADDR_LO 0x3C34 1165166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1166166676Sjkim#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1167166676Sjkim#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1168166676Sjkim#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1169166676Sjkim#define BGE_FLOW_ATTN 0x3C48 1170166676Sjkim#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1171166676Sjkim#define BGE_HCC_STD_BD_CONS 0x3C54 1172166676Sjkim#define BGE_HCC_MINI_BD_CONS 0x3C58 1173166676Sjkim#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1174166676Sjkim#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1175166676Sjkim#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1176166676Sjkim#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1177166676Sjkim#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1178166676Sjkim#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1179166676Sjkim#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1180166676Sjkim#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1181166676Sjkim#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1182166676Sjkim#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1183166676Sjkim#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1184166676Sjkim#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1185166676Sjkim#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1186166676Sjkim#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1187166676Sjkim#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1188166676Sjkim#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1189166676Sjkim#define BGE_HCC_TX_BD_CONS0 0x3CC0 1190166676Sjkim#define BGE_HCC_TX_BD_CONS1 0x3CC4 1191166676Sjkim#define BGE_HCC_TX_BD_CONS2 0x3CC8 1192166676Sjkim#define BGE_HCC_TX_BD_CONS3 0x3CCC 1193166676Sjkim#define BGE_HCC_TX_BD_CONS4 0x3CD0 1194166676Sjkim#define BGE_HCC_TX_BD_CONS5 0x3CD4 1195166676Sjkim#define BGE_HCC_TX_BD_CONS6 0x3CD8 1196166676Sjkim#define BGE_HCC_TX_BD_CONS7 0x3CDC 1197166676Sjkim#define BGE_HCC_TX_BD_CONS8 0x3CE0 1198166676Sjkim#define BGE_HCC_TX_BD_CONS9 0x3CE4 1199166676Sjkim#define BGE_HCC_TX_BD_CONS10 0x3CE8 1200166676Sjkim#define BGE_HCC_TX_BD_CONS11 0x3CEC 1201166676Sjkim#define BGE_HCC_TX_BD_CONS12 0x3CF0 1202166676Sjkim#define BGE_HCC_TX_BD_CONS13 0x3CF4 1203166676Sjkim#define BGE_HCC_TX_BD_CONS14 0x3CF8 1204166676Sjkim#define BGE_HCC_TX_BD_CONS15 0x3CFC 120584059Swpaul 120684059Swpaul 120784059Swpaul/* Host coalescing mode register */ 1208166676Sjkim#define BGE_HCCMODE_RESET 0x00000001 1209166676Sjkim#define BGE_HCCMODE_ENABLE 0x00000002 1210166676Sjkim#define BGE_HCCMODE_ATTN 0x00000004 1211166676Sjkim#define BGE_HCCMODE_COAL_NOW 0x00000008 1212166676Sjkim#define BGE_HCCMODE_MSI_BITS 0x00000070 1213166676Sjkim#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 121484059Swpaul 1215166676Sjkim#define BGE_STATBLKSZ_FULL 0x00000000 1216166676Sjkim#define BGE_STATBLKSZ_64BYTE 0x00000080 1217166676Sjkim#define BGE_STATBLKSZ_32BYTE 0x00000100 121884059Swpaul 121984059Swpaul/* Host coalescing status register */ 1220166676Sjkim#define BGE_HCCSTAT_ERROR 0x00000004 122184059Swpaul 122284059Swpaul/* Flow attention register */ 1223166676Sjkim#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1224166676Sjkim#define BGE_FLOWATTN_MEMARB 0x00000080 1225166676Sjkim#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1226166676Sjkim#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1227166676Sjkim#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1228166676Sjkim#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1229166676Sjkim#define BGE_FLOWATTN_RDBDI 0x00080000 1230166676Sjkim#define BGE_FLOWATTN_RXLS 0x00100000 1231166676Sjkim#define BGE_FLOWATTN_RXLP 0x00200000 1232166676Sjkim#define BGE_FLOWATTN_RBDC 0x00400000 1233166676Sjkim#define BGE_FLOWATTN_RBDI 0x00800000 1234166676Sjkim#define BGE_FLOWATTN_SDC 0x08000000 1235166676Sjkim#define BGE_FLOWATTN_SDI 0x10000000 1236166676Sjkim#define BGE_FLOWATTN_SRS 0x20000000 1237166676Sjkim#define BGE_FLOWATTN_SBDC 0x40000000 1238166676Sjkim#define BGE_FLOWATTN_SBDI 0x80000000 123984059Swpaul 124084059Swpaul/* 124184059Swpaul * Memory arbiter registers 124284059Swpaul */ 1243166676Sjkim#define BGE_MARB_MODE 0x4000 1244166676Sjkim#define BGE_MARB_STATUS 0x4004 1245166676Sjkim#define BGE_MARB_TRAPADDR_HI 0x4008 1246166676Sjkim#define BGE_MARB_TRAPADDR_LO 0x400C 124784059Swpaul 124884059Swpaul/* Memory arbiter mode register */ 1249166676Sjkim#define BGE_MARBMODE_RESET 0x00000001 1250166676Sjkim#define BGE_MARBMODE_ENABLE 0x00000002 1251166676Sjkim#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1252166676Sjkim#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1253166676Sjkim#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1254166676Sjkim#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1255166676Sjkim#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1256166676Sjkim#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1257166676Sjkim#define BGE_MARBMODE_PCI_TRAP 0x00000100 1258166676Sjkim#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1259166676Sjkim#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1260166676Sjkim#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1261166676Sjkim#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1262166676Sjkim#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1263166676Sjkim#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1264166676Sjkim#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1265166676Sjkim#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1266166676Sjkim#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1267166676Sjkim#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1268166676Sjkim#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1269166676Sjkim#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1270166676Sjkim#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1271166676Sjkim#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1272166676Sjkim#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1273166676Sjkim#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1274166676Sjkim#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 127584059Swpaul 127684059Swpaul/* Memory arbiter status register */ 1277166676Sjkim#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1278166676Sjkim#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1279166676Sjkim#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1280166676Sjkim#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1281166676Sjkim#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1282166676Sjkim#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1283166676Sjkim#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1284166676Sjkim#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1285166676Sjkim#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1286166676Sjkim#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1287166676Sjkim#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1288166676Sjkim#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1289166676Sjkim#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1290166676Sjkim#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1291166676Sjkim#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1292166676Sjkim#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1293166676Sjkim#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1294166676Sjkim#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1295166676Sjkim#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1296166676Sjkim#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1297166676Sjkim#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1298166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1299166676Sjkim#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1300166676Sjkim#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 130184059Swpaul 130284059Swpaul/* 130384059Swpaul * Buffer manager control registers 130484059Swpaul */ 1305166676Sjkim#define BGE_BMAN_MODE 0x4400 1306166676Sjkim#define BGE_BMAN_STATUS 0x4404 1307166676Sjkim#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1308166676Sjkim#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1309166676Sjkim#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1310166676Sjkim#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1311166676Sjkim#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1312166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1313166676Sjkim#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1314166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1315166676Sjkim#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1316166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1317166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1318166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1319166676Sjkim#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1320166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1321166676Sjkim#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1322166676Sjkim#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1323166676Sjkim#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1324166676Sjkim#define BGE_BMAN_HWDIAG_1 0x444C 1325166676Sjkim#define BGE_BMAN_HWDIAG_2 0x4450 1326166676Sjkim#define BGE_BMAN_HWDIAG_3 0x4454 132784059Swpaul 132884059Swpaul/* Buffer manager mode register */ 1329166676Sjkim#define BGE_BMANMODE_RESET 0x00000001 1330166676Sjkim#define BGE_BMANMODE_ENABLE 0x00000002 1331166676Sjkim#define BGE_BMANMODE_ATTN 0x00000004 1332166676Sjkim#define BGE_BMANMODE_TESTMODE 0x00000008 1333166676Sjkim#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 133484059Swpaul 133584059Swpaul/* Buffer manager status register */ 1336166676Sjkim#define BGE_BMANSTAT_ERRO 0x00000004 1337166676Sjkim#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 133884059Swpaul 133984059Swpaul 134084059Swpaul/* 134184059Swpaul * Read DMA Control registers 134284059Swpaul */ 1343166676Sjkim#define BGE_RDMA_MODE 0x4800 1344166676Sjkim#define BGE_RDMA_STATUS 0x4804 134584059Swpaul 134684059Swpaul/* Read DMA mode register */ 1347166676Sjkim#define BGE_RDMAMODE_RESET 0x00000001 1348166676Sjkim#define BGE_RDMAMODE_ENABLE 0x00000002 1349166676Sjkim#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1350166676Sjkim#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1351166676Sjkim#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1352166676Sjkim#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1353166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1354166676Sjkim#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1355166676Sjkim#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1356166676Sjkim#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1357166676Sjkim#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 135884059Swpaul 135984059Swpaul/* Read DMA status register */ 1360166676Sjkim#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1361166676Sjkim#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1362166676Sjkim#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1363166676Sjkim#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1364166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1365166676Sjkim#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1366166676Sjkim#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1367166676Sjkim#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 136884059Swpaul 136984059Swpaul/* 137084059Swpaul * Write DMA control registers 137184059Swpaul */ 1372166676Sjkim#define BGE_WDMA_MODE 0x4C00 1373166676Sjkim#define BGE_WDMA_STATUS 0x4C04 137484059Swpaul 137584059Swpaul/* Write DMA mode register */ 1376166676Sjkim#define BGE_WDMAMODE_RESET 0x00000001 1377166676Sjkim#define BGE_WDMAMODE_ENABLE 0x00000002 1378166676Sjkim#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1379166676Sjkim#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1380166676Sjkim#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1381166676Sjkim#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1382166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1383166676Sjkim#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1384166676Sjkim#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1385166676Sjkim#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1386166676Sjkim#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 138784059Swpaul 138884059Swpaul/* Write DMA status register */ 1389166676Sjkim#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1390166676Sjkim#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1391166676Sjkim#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1392166676Sjkim#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1393166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1394166676Sjkim#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1395166676Sjkim#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1396166676Sjkim#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 139784059Swpaul 139884059Swpaul 139984059Swpaul/* 140084059Swpaul * RX CPU registers 140184059Swpaul */ 1402166676Sjkim#define BGE_RXCPU_MODE 0x5000 1403166676Sjkim#define BGE_RXCPU_STATUS 0x5004 1404166676Sjkim#define BGE_RXCPU_PC 0x501C 140584059Swpaul 140684059Swpaul/* RX CPU mode register */ 1407166676Sjkim#define BGE_RXCPUMODE_RESET 0x00000001 1408166676Sjkim#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1409166676Sjkim#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1410166676Sjkim#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1411166676Sjkim#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1412166676Sjkim#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1413166676Sjkim#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1414166676Sjkim#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1415166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1416166676Sjkim#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1417166676Sjkim#define BGE_RXCPUMODE_HALTCPU 0x00000400 1418166676Sjkim#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1419166676Sjkim#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1420166676Sjkim#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 142184059Swpaul 142284059Swpaul/* RX CPU status register */ 1423166676Sjkim#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1424166676Sjkim#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1425166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1426166676Sjkim#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1427166676Sjkim#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1428166676Sjkim#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1429166676Sjkim#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1430166676Sjkim#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1431166676Sjkim#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1432166676Sjkim#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1433166676Sjkim#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1434166676Sjkim#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1435166676Sjkim#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1436166676Sjkim#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1437166676Sjkim#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1438166676Sjkim#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1439166676Sjkim#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 144084059Swpaul 144184059Swpaul 144284059Swpaul/* 144384059Swpaul * TX CPU registers 144484059Swpaul */ 1445166676Sjkim#define BGE_TXCPU_MODE 0x5400 1446166676Sjkim#define BGE_TXCPU_STATUS 0x5404 1447166676Sjkim#define BGE_TXCPU_PC 0x541C 144884059Swpaul 144984059Swpaul/* TX CPU mode register */ 1450166676Sjkim#define BGE_TXCPUMODE_RESET 0x00000001 1451166676Sjkim#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1452166676Sjkim#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1453166676Sjkim#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1454166676Sjkim#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1455166676Sjkim#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1456166676Sjkim#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1457166676Sjkim#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1458166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1459166676Sjkim#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1460166676Sjkim#define BGE_TXCPUMODE_HALTCPU 0x00000400 1461166676Sjkim#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1462166676Sjkim#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 146384059Swpaul 146484059Swpaul/* TX CPU status register */ 1465166676Sjkim#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1466166676Sjkim#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1467166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1468166676Sjkim#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1469166676Sjkim#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1470166676Sjkim#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1471166676Sjkim#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1472166676Sjkim#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1473166676Sjkim#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1474166676Sjkim#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1475166676Sjkim#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1476166676Sjkim#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1477166676Sjkim#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1478166676Sjkim#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1479166676Sjkim#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1480166676Sjkim#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1481166676Sjkim#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 148284059Swpaul 148384059Swpaul 148484059Swpaul/* 148584059Swpaul * Low priority mailbox registers 148684059Swpaul */ 1487166676Sjkim#define BGE_LPMBX_IRQ0_HI 0x5800 1488166676Sjkim#define BGE_LPMBX_IRQ0_LO 0x5804 1489166676Sjkim#define BGE_LPMBX_IRQ1_HI 0x5808 1490166676Sjkim#define BGE_LPMBX_IRQ1_LO 0x580C 1491166676Sjkim#define BGE_LPMBX_IRQ2_HI 0x5810 1492166676Sjkim#define BGE_LPMBX_IRQ2_LO 0x5814 1493166676Sjkim#define BGE_LPMBX_IRQ3_HI 0x5818 1494166676Sjkim#define BGE_LPMBX_IRQ3_LO 0x581C 1495166676Sjkim#define BGE_LPMBX_GEN0_HI 0x5820 1496166676Sjkim#define BGE_LPMBX_GEN0_LO 0x5824 1497166676Sjkim#define BGE_LPMBX_GEN1_HI 0x5828 1498166676Sjkim#define BGE_LPMBX_GEN1_LO 0x582C 1499166676Sjkim#define BGE_LPMBX_GEN2_HI 0x5830 1500166676Sjkim#define BGE_LPMBX_GEN2_LO 0x5834 1501166676Sjkim#define BGE_LPMBX_GEN3_HI 0x5828 1502166676Sjkim#define BGE_LPMBX_GEN3_LO 0x582C 1503166676Sjkim#define BGE_LPMBX_GEN4_HI 0x5840 1504166676Sjkim#define BGE_LPMBX_GEN4_LO 0x5844 1505166676Sjkim#define BGE_LPMBX_GEN5_HI 0x5848 1506166676Sjkim#define BGE_LPMBX_GEN5_LO 0x584C 1507166676Sjkim#define BGE_LPMBX_GEN6_HI 0x5850 1508166676Sjkim#define BGE_LPMBX_GEN6_LO 0x5854 1509166676Sjkim#define BGE_LPMBX_GEN7_HI 0x5858 1510166676Sjkim#define BGE_LPMBX_GEN7_LO 0x585C 1511166676Sjkim#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1512166676Sjkim#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1513166676Sjkim#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1514166676Sjkim#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1515166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1516166676Sjkim#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1517166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1518166676Sjkim#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1519166676Sjkim#define BGE_LPMBX_RX_CONS0_HI 0x5880 1520166676Sjkim#define BGE_LPMBX_RX_CONS0_LO 0x5884 1521166676Sjkim#define BGE_LPMBX_RX_CONS1_HI 0x5888 1522166676Sjkim#define BGE_LPMBX_RX_CONS1_LO 0x588C 1523166676Sjkim#define BGE_LPMBX_RX_CONS2_HI 0x5890 1524166676Sjkim#define BGE_LPMBX_RX_CONS2_LO 0x5894 1525166676Sjkim#define BGE_LPMBX_RX_CONS3_HI 0x5898 1526166676Sjkim#define BGE_LPMBX_RX_CONS3_LO 0x589C 1527166676Sjkim#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1528166676Sjkim#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1529166676Sjkim#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1530166676Sjkim#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1531166676Sjkim#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1532166676Sjkim#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1533166676Sjkim#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1534166676Sjkim#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1535166676Sjkim#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1536166676Sjkim#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1537166676Sjkim#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1538166676Sjkim#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1539166676Sjkim#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1540166676Sjkim#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1541166676Sjkim#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1542166676Sjkim#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1543166676Sjkim#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1544166676Sjkim#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1545166676Sjkim#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1546166676Sjkim#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1547166676Sjkim#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1548166676Sjkim#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1549166676Sjkim#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1550166676Sjkim#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1551166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1552166676Sjkim#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1553166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1554166676Sjkim#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1555166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1556166676Sjkim#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1557166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1558166676Sjkim#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1559166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1560166676Sjkim#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1561166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1562166676Sjkim#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1563166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1564166676Sjkim#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1565166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1566166676Sjkim#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1567166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1568166676Sjkim#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1569166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1570166676Sjkim#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1571166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1572166676Sjkim#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1573166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1574166676Sjkim#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1575166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1576166676Sjkim#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1577166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1578166676Sjkim#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1579166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1580166676Sjkim#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1581166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1582166676Sjkim#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1583166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1584166676Sjkim#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1585166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1586166676Sjkim#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1587166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1588166676Sjkim#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1589166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1590166676Sjkim#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1591166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1592166676Sjkim#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1593166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1594166676Sjkim#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1595166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1596166676Sjkim#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1597166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1598166676Sjkim#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1599166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1600166676Sjkim#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1601166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1602166676Sjkim#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1603166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1604166676Sjkim#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1605166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1606166676Sjkim#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1607166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1608166676Sjkim#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1609166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1610166676Sjkim#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1611166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1612166676Sjkim#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1613166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1614166676Sjkim#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 161584059Swpaul 161684059Swpaul/* 161784059Swpaul * Flow throw Queue reset register 161884059Swpaul */ 1619166676Sjkim#define BGE_FTQ_RESET 0x5C00 162084059Swpaul 1621166676Sjkim#define BGE_FTQRESET_DMAREAD 0x00000002 1622166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1623166676Sjkim#define BGE_FTQRESET_DMADONE 0x00000010 1624166676Sjkim#define BGE_FTQRESET_SBDC 0x00000020 1625166676Sjkim#define BGE_FTQRESET_SDI 0x00000040 1626166676Sjkim#define BGE_FTQRESET_WDMA 0x00000080 1627166676Sjkim#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1628166676Sjkim#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1629166676Sjkim#define BGE_FTQRESET_SDC 0x00000400 1630166676Sjkim#define BGE_FTQRESET_HCC 0x00000800 1631166676Sjkim#define BGE_FTQRESET_TXFIFO 0x00001000 1632166676Sjkim#define BGE_FTQRESET_MBC 0x00002000 1633166676Sjkim#define BGE_FTQRESET_RBDC 0x00004000 1634166676Sjkim#define BGE_FTQRESET_RXLP 0x00008000 1635166676Sjkim#define BGE_FTQRESET_RDBDI 0x00010000 1636166676Sjkim#define BGE_FTQRESET_RDC 0x00020000 1637166676Sjkim#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 163884059Swpaul 163984059Swpaul/* 164084059Swpaul * Message Signaled Interrupt registers 164184059Swpaul */ 1642166676Sjkim#define BGE_MSI_MODE 0x6000 1643166676Sjkim#define BGE_MSI_STATUS 0x6004 1644166676Sjkim#define BGE_MSI_FIFOACCESS 0x6008 164584059Swpaul 164684059Swpaul/* MSI mode register */ 1647166676Sjkim#define BGE_MSIMODE_RESET 0x00000001 1648166676Sjkim#define BGE_MSIMODE_ENABLE 0x00000002 1649166676Sjkim#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1650166676Sjkim#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1651166676Sjkim#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1652166676Sjkim#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1653166676Sjkim#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 165484059Swpaul 165584059Swpaul/* MSI status register */ 1656166676Sjkim#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1657166676Sjkim#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1658166676Sjkim#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1659166676Sjkim#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1660166676Sjkim#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 166184059Swpaul 166284059Swpaul 166384059Swpaul/* 166484059Swpaul * DMA Completion registers 166584059Swpaul */ 1666166676Sjkim#define BGE_DMAC_MODE 0x6400 166784059Swpaul 166884059Swpaul/* DMA Completion mode register */ 1669166676Sjkim#define BGE_DMACMODE_RESET 0x00000001 1670166676Sjkim#define BGE_DMACMODE_ENABLE 0x00000002 167184059Swpaul 167284059Swpaul 167384059Swpaul/* 167484059Swpaul * General control registers. 167584059Swpaul */ 1676166676Sjkim#define BGE_MODE_CTL 0x6800 1677166676Sjkim#define BGE_MISC_CFG 0x6804 1678166676Sjkim#define BGE_MISC_LOCAL_CTL 0x6808 1679166676Sjkim#define BGE_CPU_EVENT 0x6810 1680166676Sjkim#define BGE_EE_ADDR 0x6838 1681166676Sjkim#define BGE_EE_DATA 0x683C 1682166676Sjkim#define BGE_EE_CTL 0x6840 1683166676Sjkim#define BGE_MDI_CTL 0x6844 1684166676Sjkim#define BGE_EE_DELAY 0x6848 1685166676Sjkim#define BGE_FASTBOOT_PC 0x6894 168684059Swpaul 168784059Swpaul/* Mode control register */ 1688166676Sjkim#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1689166676Sjkim#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1690166676Sjkim#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1691166676Sjkim#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1692166676Sjkim#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1693166676Sjkim#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1694166676Sjkim#define BGE_MODECTL_NO_RX_CRC 0x00000400 1695166676Sjkim#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1696166676Sjkim#define BGE_MODECTL_NO_TX_INTR 0x00002000 1697166676Sjkim#define BGE_MODECTL_NO_RX_INTR 0x00004000 1698166676Sjkim#define BGE_MODECTL_FORCE_PCI32 0x00008000 1699166676Sjkim#define BGE_MODECTL_STACKUP 0x00010000 1700166676Sjkim#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1701166676Sjkim#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1702166676Sjkim#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1703166676Sjkim#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1704166676Sjkim#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1705166676Sjkim#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1706166676Sjkim#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1707166676Sjkim#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1708166676Sjkim#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1709166676Sjkim#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 171084059Swpaul 171184059Swpaul/* Misc. config register */ 1712166676Sjkim#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1713166676Sjkim#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 171484059Swpaul 1715166676Sjkim#define BGE_32BITTIME_66MHZ (0x41 << 1) 171684059Swpaul 171784059Swpaul/* Misc. Local Control */ 1718166676Sjkim#define BGE_MLC_INTR_STATE 0x00000001 1719166676Sjkim#define BGE_MLC_INTR_CLR 0x00000002 1720166676Sjkim#define BGE_MLC_INTR_SET 0x00000004 1721166676Sjkim#define BGE_MLC_INTR_ONATTN 0x00000008 1722166676Sjkim#define BGE_MLC_MISCIO_IN0 0x00000100 1723166676Sjkim#define BGE_MLC_MISCIO_IN1 0x00000200 1724166676Sjkim#define BGE_MLC_MISCIO_IN2 0x00000400 1725166676Sjkim#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1726166676Sjkim#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1727166676Sjkim#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1728166676Sjkim#define BGE_MLC_MISCIO_OUT0 0x00004000 1729166676Sjkim#define BGE_MLC_MISCIO_OUT1 0x00008000 1730166676Sjkim#define BGE_MLC_MISCIO_OUT2 0x00010000 1731166676Sjkim#define BGE_MLC_EXTRAM_ENB 0x00020000 1732166676Sjkim#define BGE_MLC_SRAM_SIZE 0x001C0000 1733166676Sjkim#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1734166676Sjkim#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1735166676Sjkim#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1736166676Sjkim#define BGE_MLC_AUTO_EEPROM 0x01000000 173784059Swpaul 1738166676Sjkim#define BGE_SSRAMSIZE_256KB 0x00000000 1739166676Sjkim#define BGE_SSRAMSIZE_512KB 0x00040000 1740166676Sjkim#define BGE_SSRAMSIZE_1MB 0x00080000 1741166676Sjkim#define BGE_SSRAMSIZE_2MB 0x000C0000 1742166676Sjkim#define BGE_SSRAMSIZE_4MB 0x00100000 1743166676Sjkim#define BGE_SSRAMSIZE_8MB 0x00140000 1744166676Sjkim#define BGE_SSRAMSIZE_16M 0x00180000 174584059Swpaul 174684059Swpaul/* EEPROM address register */ 1747166676Sjkim#define BGE_EEADDR_ADDRESS 0x0000FFFC 1748166676Sjkim#define BGE_EEADDR_HALFCLK 0x01FF0000 1749166676Sjkim#define BGE_EEADDR_START 0x02000000 1750166676Sjkim#define BGE_EEADDR_DEVID 0x1C000000 1751166676Sjkim#define BGE_EEADDR_RESET 0x20000000 1752166676Sjkim#define BGE_EEADDR_DONE 0x40000000 1753166676Sjkim#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 175484059Swpaul 1755166676Sjkim#define BGE_EEDEVID(x) ((x & 7) << 26) 1756166676Sjkim#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1757166676Sjkim#define BGE_HALFCLK_384SCL 0x60 1758166676Sjkim#define BGE_EE_READCMD \ 175984059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 176084059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1761166676Sjkim#define BGE_EE_WRCMD \ 176284059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 176384059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 176484059Swpaul 176584059Swpaul/* EEPROM Control register */ 1766166676Sjkim#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1767166676Sjkim#define BGE_EECTL_CLKOUT 0x00000002 1768166676Sjkim#define BGE_EECTL_CLKIN 0x00000004 1769166676Sjkim#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1770166676Sjkim#define BGE_EECTL_DATAOUT 0x00000010 1771166676Sjkim#define BGE_EECTL_DATAIN 0x00000020 177284059Swpaul 177384059Swpaul/* MDI (MII/GMII) access register */ 1774166676Sjkim#define BGE_MDI_DATA 0x00000001 1775166676Sjkim#define BGE_MDI_DIR 0x00000002 1776166676Sjkim#define BGE_MDI_SEL 0x00000004 1777166676Sjkim#define BGE_MDI_CLK 0x00000008 177884059Swpaul 1779166676Sjkim#define BGE_MEMWIN_START 0x00008000 1780166676Sjkim#define BGE_MEMWIN_END 0x0000FFFF 178184059Swpaul 178284059Swpaul 1783166676Sjkim#define BGE_MEMWIN_READ(sc, x, val) \ 178484059Swpaul do { \ 178584059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 178684059Swpaul (0xFFFF0000 & x), 4); \ 178784059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 178884059Swpaul } while(0) 178984059Swpaul 1790166676Sjkim#define BGE_MEMWIN_WRITE(sc, x, val) \ 179184059Swpaul do { \ 179284059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 179384059Swpaul (0xFFFF0000 & x), 4); \ 179484059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 179584059Swpaul } while(0) 179684059Swpaul 179784059Swpaul/* 1798161847Sdavidch * This magic number is written to the firmware mailbox at 0xb50 1799161847Sdavidch * before a software reset is issued. After the internal firmware 1800161847Sdavidch * has completed its initialization it will write the opposite of 1801161847Sdavidch * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1802161847Sdavidch * driver to synchronize with the firmware. 180384059Swpaul */ 1804166676Sjkim#define BGE_MAGIC_NUMBER 0x4B657654 180584059Swpaul 180684059Swpaultypedef struct { 1807159395Sglebius uint32_t bge_addr_hi; 1808159395Sglebius uint32_t bge_addr_lo; 180984059Swpaul} bge_hostaddr; 1810118026Swpaul 1811166676Sjkim#define BGE_HOSTADDR(x, y) \ 1812115200Sps do { \ 1813159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1814159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1815115200Sps } while(0) 181684059Swpaul 1817166676Sjkim#define BGE_ADDR_LO(y) \ 1818159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 1819166676Sjkim#define BGE_ADDR_HI(y) \ 1820159395Sglebius ((uint64_t) (y) >> 32) 1821118026Swpaul 182284059Swpaul/* Ring control block structure */ 182384059Swpaulstruct bge_rcb { 182484059Swpaul bge_hostaddr bge_hostaddr; 1825159395Sglebius uint32_t bge_maxlen_flags; 1826159395Sglebius uint32_t bge_nicaddr; 182784059Swpaul}; 1828153437Syongari 1829153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 1830153437Syongari bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1831153437Syongari rcb + offsetof(struct bge_rcb, offset), val) 1832166676Sjkim#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 183384059Swpaul 1834166676Sjkim#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1835166676Sjkim#define BGE_RCB_FLAG_RING_DISABLED 0x0002 183684059Swpaul 183784059Swpaulstruct bge_tx_bd { 183884059Swpaul bge_hostaddr bge_addr; 1839153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1840159395Sglebius uint16_t bge_flags; 1841159395Sglebius uint16_t bge_len; 1842159395Sglebius uint16_t bge_vlan_tag; 1843159395Sglebius uint16_t bge_rsvd; 1844153437Syongari#else 1845159395Sglebius uint16_t bge_len; 1846159395Sglebius uint16_t bge_flags; 1847159395Sglebius uint16_t bge_rsvd; 1848159395Sglebius uint16_t bge_vlan_tag; 1849153437Syongari#endif 185084059Swpaul}; 185184059Swpaul 1852166676Sjkim#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1853166676Sjkim#define BGE_TXBDFLAG_IP_CSUM 0x0002 1854166676Sjkim#define BGE_TXBDFLAG_END 0x0004 1855166676Sjkim#define BGE_TXBDFLAG_IP_FRAG 0x0008 1856166676Sjkim#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1857166676Sjkim#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1858166676Sjkim#define BGE_TXBDFLAG_COAL_NOW 0x0080 1859166676Sjkim#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1860166676Sjkim#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1861166676Sjkim#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1862166676Sjkim#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1863166676Sjkim#define BGE_TXBDFLAG_NO_CRC 0x8000 186484059Swpaul 1865166676Sjkim#define BGE_NIC_TXRING_ADDR(ringno, size) \ 186684059Swpaul BGE_SEND_RING_1_TO_4 + \ 186784059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 186884059Swpaul 186984059Swpaulstruct bge_rx_bd { 187084059Swpaul bge_hostaddr bge_addr; 1871153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1872159395Sglebius uint16_t bge_len; 1873159395Sglebius uint16_t bge_idx; 1874159395Sglebius uint16_t bge_flags; 1875159395Sglebius uint16_t bge_type; 1876159395Sglebius uint16_t bge_tcp_udp_csum; 1877159395Sglebius uint16_t bge_ip_csum; 1878159395Sglebius uint16_t bge_vlan_tag; 1879159395Sglebius uint16_t bge_error_flag; 1880153437Syongari#else 1881159395Sglebius uint16_t bge_idx; 1882159395Sglebius uint16_t bge_len; 1883159395Sglebius uint16_t bge_type; 1884159395Sglebius uint16_t bge_flags; 1885159395Sglebius uint16_t bge_ip_csum; 1886159395Sglebius uint16_t bge_tcp_udp_csum; 1887159395Sglebius uint16_t bge_error_flag; 1888159395Sglebius uint16_t bge_vlan_tag; 1889153437Syongari#endif 1890159395Sglebius uint32_t bge_rsvd; 1891159395Sglebius uint32_t bge_opaque; 189284059Swpaul}; 189384059Swpaul 1894153239Sglebiusstruct bge_extrx_bd { 1895153239Sglebius bge_hostaddr bge_addr1; 1896153239Sglebius bge_hostaddr bge_addr2; 1897153239Sglebius bge_hostaddr bge_addr3; 1898153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1899159395Sglebius uint16_t bge_len2; 1900159395Sglebius uint16_t bge_len1; 1901159395Sglebius uint16_t bge_rsvd1; 1902159395Sglebius uint16_t bge_len3; 1903153437Syongari#else 1904159395Sglebius uint16_t bge_len1; 1905159395Sglebius uint16_t bge_len2; 1906159395Sglebius uint16_t bge_len3; 1907159395Sglebius uint16_t bge_rsvd1; 1908153437Syongari#endif 1909153239Sglebius bge_hostaddr bge_addr0; 1910153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1911159395Sglebius uint16_t bge_len0; 1912159395Sglebius uint16_t bge_idx; 1913159395Sglebius uint16_t bge_flags; 1914159395Sglebius uint16_t bge_type; 1915159395Sglebius uint16_t bge_tcp_udp_csum; 1916159395Sglebius uint16_t bge_ip_csum; 1917159395Sglebius uint16_t bge_vlan_tag; 1918159395Sglebius uint16_t bge_error_flag; 1919153437Syongari#else 1920159395Sglebius uint16_t bge_idx; 1921159395Sglebius uint16_t bge_len0; 1922159395Sglebius uint16_t bge_type; 1923159395Sglebius uint16_t bge_flags; 1924159395Sglebius uint16_t bge_ip_csum; 1925159395Sglebius uint16_t bge_tcp_udp_csum; 1926159395Sglebius uint16_t bge_error_flag; 1927159395Sglebius uint16_t bge_vlan_tag; 1928153437Syongari#endif 1929159395Sglebius uint32_t bge_rsvd0; 1930159395Sglebius uint32_t bge_opaque; 1931153239Sglebius}; 1932153239Sglebius 1933166676Sjkim#define BGE_RXBDFLAG_END 0x0004 1934166676Sjkim#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1935166676Sjkim#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1936166676Sjkim#define BGE_RXBDFLAG_ERROR 0x0400 1937166676Sjkim#define BGE_RXBDFLAG_MINI_RING 0x0800 1938166676Sjkim#define BGE_RXBDFLAG_IP_CSUM 0x1000 1939166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1940166676Sjkim#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 194184059Swpaul 1942166676Sjkim#define BGE_RXERRFLAG_BAD_CRC 0x0001 1943166676Sjkim#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1944166676Sjkim#define BGE_RXERRFLAG_LINK_LOST 0x0004 1945166676Sjkim#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1946166676Sjkim#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1947166676Sjkim#define BGE_RXERRFLAG_RUNT 0x0020 1948166676Sjkim#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1949166676Sjkim#define BGE_RXERRFLAG_GIANT 0x0080 195084059Swpaul 195184059Swpaulstruct bge_sts_idx { 1952153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1953159395Sglebius uint16_t bge_rx_prod_idx; 1954159395Sglebius uint16_t bge_tx_cons_idx; 1955153437Syongari#else 1956159395Sglebius uint16_t bge_tx_cons_idx; 1957159395Sglebius uint16_t bge_rx_prod_idx; 1958153437Syongari#endif 195984059Swpaul}; 196084059Swpaul 196184059Swpaulstruct bge_status_block { 1962159395Sglebius uint32_t bge_status; 1963159395Sglebius uint32_t bge_rsvd0; 1964153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1965159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 1966159395Sglebius uint16_t bge_rx_std_cons_idx; 1967159395Sglebius uint16_t bge_rx_mini_cons_idx; 1968159395Sglebius uint16_t bge_rsvd1; 1969153437Syongari#else 1970159395Sglebius uint16_t bge_rx_std_cons_idx; 1971159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 1972159395Sglebius uint16_t bge_rsvd1; 1973159395Sglebius uint16_t bge_rx_mini_cons_idx; 1974153437Syongari#endif 197584059Swpaul struct bge_sts_idx bge_idx[16]; 197684059Swpaul}; 197784059Swpaul 1978166676Sjkim#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1979166676Sjkim#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 198084059Swpaul 1981166676Sjkim#define BGE_STATFLAG_UPDATED 0x00000001 1982166676Sjkim#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1983166676Sjkim#define BGE_STATFLAG_ERROR 0x00000004 198484059Swpaul 198584059Swpaul 198684059Swpaul/* 198784059Swpaul * Broadcom Vendor ID 198884059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 198984059Swpaul * even though they're now manufactured by Broadcom) 199084059Swpaul */ 1991166676Sjkim#define BCOM_VENDORID 0x14E4 1992166676Sjkim#define BCOM_DEVICEID_BCM5700 0x1644 1993166676Sjkim#define BCOM_DEVICEID_BCM5701 0x1645 1994166676Sjkim#define BCOM_DEVICEID_BCM5702 0x1646 1995166676Sjkim#define BCOM_DEVICEID_BCM5702X 0x16A6 1996166676Sjkim#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 1997166676Sjkim#define BCOM_DEVICEID_BCM5703 0x1647 1998166676Sjkim#define BCOM_DEVICEID_BCM5703X 0x16A7 1999166676Sjkim#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2000166676Sjkim#define BCOM_DEVICEID_BCM5704C 0x1648 2001166676Sjkim#define BCOM_DEVICEID_BCM5704S 0x16A8 2002166676Sjkim#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2003166676Sjkim#define BCOM_DEVICEID_BCM5705 0x1653 2004166676Sjkim#define BCOM_DEVICEID_BCM5705K 0x1654 2005166676Sjkim#define BCOM_DEVICEID_BCM5705F 0x166E 2006166676Sjkim#define BCOM_DEVICEID_BCM5705M 0x165D 2007166676Sjkim#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2008166676Sjkim#define BCOM_DEVICEID_BCM5714C 0x1668 2009166676Sjkim#define BCOM_DEVICEID_BCM5714S 0x1669 2010166676Sjkim#define BCOM_DEVICEID_BCM5715 0x1678 2011166676Sjkim#define BCOM_DEVICEID_BCM5715S 0x1679 2012166676Sjkim#define BCOM_DEVICEID_BCM5720 0x1658 2013166676Sjkim#define BCOM_DEVICEID_BCM5721 0x1659 2014166676Sjkim#define BCOM_DEVICEID_BCM5750 0x1676 2015166676Sjkim#define BCOM_DEVICEID_BCM5750M 0x167C 2016166676Sjkim#define BCOM_DEVICEID_BCM5751 0x1677 2017166676Sjkim#define BCOM_DEVICEID_BCM5751F 0x167E 2018166676Sjkim#define BCOM_DEVICEID_BCM5751M 0x167D 2019166676Sjkim#define BCOM_DEVICEID_BCM5752 0x1600 2020166676Sjkim#define BCOM_DEVICEID_BCM5752M 0x1601 2021166676Sjkim#define BCOM_DEVICEID_BCM5753 0x16F7 2022166676Sjkim#define BCOM_DEVICEID_BCM5753F 0x16FE 2023166676Sjkim#define BCOM_DEVICEID_BCM5753M 0x16FD 2024166676Sjkim#define BCOM_DEVICEID_BCM5754 0x167A 2025166676Sjkim#define BCOM_DEVICEID_BCM5754M 0x1672 2026166676Sjkim#define BCOM_DEVICEID_BCM5755 0x167B 2027166676Sjkim#define BCOM_DEVICEID_BCM5755M 0x1673 2028166676Sjkim#define BCOM_DEVICEID_BCM5780 0x166A 2029166676Sjkim#define BCOM_DEVICEID_BCM5780S 0x166B 2030166676Sjkim#define BCOM_DEVICEID_BCM5781 0x16DD 2031166676Sjkim#define BCOM_DEVICEID_BCM5782 0x1696 2032166676Sjkim#define BCOM_DEVICEID_BCM5786 0x169A 2033166676Sjkim#define BCOM_DEVICEID_BCM5787 0x169B 2034166676Sjkim#define BCOM_DEVICEID_BCM5787M 0x1693 2035166676Sjkim#define BCOM_DEVICEID_BCM5788 0x169C 2036166676Sjkim#define BCOM_DEVICEID_BCM5789 0x169D 2037166676Sjkim#define BCOM_DEVICEID_BCM5901 0x170D 2038166676Sjkim#define BCOM_DEVICEID_BCM5901A2 0x170E 2039166676Sjkim#define BCOM_DEVICEID_BCM5903M 0x16FF 204084059Swpaul 204184059Swpaul/* 204284059Swpaul * Alteon AceNIC PCI vendor/device ID. 204384059Swpaul */ 2044166676Sjkim#define ALTEON_VENDORID 0x12AE 2045166676Sjkim#define ALTEON_DEVICEID_ACENIC 0x0001 2046166676Sjkim#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2047166676Sjkim#define ALTEON_DEVICEID_BCM5700 0x0003 2048166676Sjkim#define ALTEON_DEVICEID_BCM5701 0x0004 204984059Swpaul 205084059Swpaul/* 2051162982Sglebius * 3Com 3c996 PCI vendor/device ID. 205284059Swpaul */ 2053166676Sjkim#define TC_VENDORID 0x10B7 2054166676Sjkim#define TC_DEVICEID_3C996 0x0003 205584059Swpaul 205684059Swpaul/* 205784059Swpaul * SysKonnect PCI vendor ID 205884059Swpaul */ 2059166676Sjkim#define SK_VENDORID 0x1148 2060166676Sjkim#define SK_DEVICEID_ALTIMA 0x4400 2061166676Sjkim#define SK_SUBSYSID_9D21 0x4421 2062166676Sjkim#define SK_SUBSYSID_9D41 0x4441 206384059Swpaul 206484059Swpaul/* 206589835Sjdp * Altima PCI vendor/device ID. 206689835Sjdp */ 2067166676Sjkim#define ALTIMA_VENDORID 0x173b 2068166676Sjkim#define ALTIMA_DEVICE_AC1000 0x03e8 2069166676Sjkim#define ALTIMA_DEVICE_AC1002 0x03e9 2070166676Sjkim#define ALTIMA_DEVICE_AC9100 0x03ea 207189835Sjdp 207289835Sjdp/* 2073119157Sambrisko * Dell PCI vendor ID 2074119157Sambrisko */ 2075119157Sambrisko 2076166676Sjkim#define DELL_VENDORID 0x1028 2077119157Sambrisko 2078119157Sambrisko/* 2079159637Sglebius * Apple PCI vendor ID. 2080159637Sglebius */ 2081166676Sjkim#define APPLE_VENDORID 0x106b 2082166676Sjkim#define APPLE_DEVICE_BCM5701 0x1645 2083159637Sglebius 2084159637Sglebius/* 2085169152Smarius * Sun PCI vendor ID 2086169152Smarius */ 2087169152Smarius#define SUN_VENDORID 0x108e 2088169152Smarius 2089169152Smarius/* 209084059Swpaul * Offset of MAC address inside EEPROM. 209184059Swpaul */ 2092166676Sjkim#define BGE_EE_MAC_OFFSET 0x7C 2093166676Sjkim#define BGE_EE_HWCFG_OFFSET 0xC8 209484059Swpaul 2095166676Sjkim#define BGE_HWCFG_VOLTAGE 0x00000003 2096166676Sjkim#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2097166676Sjkim#define BGE_HWCFG_MEDIA 0x00000030 2098166676Sjkim#define BGE_HWCFG_ASF 0x00000080 209993751Swpaul 2100166676Sjkim#define BGE_VOLTAGE_1POINT3 0x00000000 2101166676Sjkim#define BGE_VOLTAGE_1POINT8 0x00000001 210293751Swpaul 2103166676Sjkim#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2104166676Sjkim#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2105166676Sjkim#define BGE_PHYLEDMODE_SINGLELED 0x00000008 210693751Swpaul 2107166676Sjkim#define BGE_MEDIA_UNSPEC 0x00000000 2108166676Sjkim#define BGE_MEDIA_COPPER 0x00000010 2109166676Sjkim#define BGE_MEDIA_FIBER 0x00000020 211093751Swpaul 2111166676Sjkim#define BGE_TICKS_PER_SEC 1000000 211284059Swpaul 211384059Swpaul/* 211484059Swpaul * Ring size constants. 211584059Swpaul */ 2116166676Sjkim#define BGE_EVENT_RING_CNT 256 2117166676Sjkim#define BGE_CMD_RING_CNT 64 2118166676Sjkim#define BGE_STD_RX_RING_CNT 512 2119166676Sjkim#define BGE_JUMBO_RX_RING_CNT 256 2120166676Sjkim#define BGE_MINI_RX_RING_CNT 1024 2121166676Sjkim#define BGE_RETURN_RING_CNT 1024 212284059Swpaul 2123117659Swpaul/* 5705 has smaller return ring size */ 2124117659Swpaul 2125166676Sjkim#define BGE_RETURN_RING_CNT_5705 512 2126117659Swpaul 212784059Swpaul/* 212884059Swpaul * Possible TX ring sizes. 212984059Swpaul */ 2130166676Sjkim#define BGE_TX_RING_CNT_128 128 2131166676Sjkim#define BGE_TX_RING_BASE_128 0x3800 213284059Swpaul 2133166676Sjkim#define BGE_TX_RING_CNT_256 256 2134166676Sjkim#define BGE_TX_RING_BASE_256 0x3000 213584059Swpaul 2136166676Sjkim#define BGE_TX_RING_CNT_512 512 2137166676Sjkim#define BGE_TX_RING_BASE_512 0x2000 213884059Swpaul 2139166676Sjkim#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2140166676Sjkim#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 214184059Swpaul 214284059Swpaul/* 214384059Swpaul * Tigon III statistics counters. 214484059Swpaul */ 2145117659Swpaul/* Statistics maintained MAC Receive block. */ 2146117659Swpaulstruct bge_rx_mac_stats { 214784059Swpaul bge_hostaddr ifHCInOctets; 214884059Swpaul bge_hostaddr Reserved1; 214984059Swpaul bge_hostaddr etherStatsFragments; 215084059Swpaul bge_hostaddr ifHCInUcastPkts; 215184059Swpaul bge_hostaddr ifHCInMulticastPkts; 215284059Swpaul bge_hostaddr ifHCInBroadcastPkts; 215384059Swpaul bge_hostaddr dot3StatsFCSErrors; 215484059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 215584059Swpaul bge_hostaddr xonPauseFramesReceived; 215684059Swpaul bge_hostaddr xoffPauseFramesReceived; 215784059Swpaul bge_hostaddr macControlFramesReceived; 215884059Swpaul bge_hostaddr xoffStateEntered; 215984059Swpaul bge_hostaddr dot3StatsFramesTooLong; 216084059Swpaul bge_hostaddr etherStatsJabbers; 216184059Swpaul bge_hostaddr etherStatsUndersizePkts; 216284059Swpaul bge_hostaddr inRangeLengthError; 216384059Swpaul bge_hostaddr outRangeLengthError; 216484059Swpaul bge_hostaddr etherStatsPkts64Octets; 216584059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 216684059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 216784059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 216884059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 216984059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 217084059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 217184059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 217284059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 217384059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2174117659Swpaul}; 217584059Swpaul 217684059Swpaul 2177117659Swpaul/* Statistics maintained MAC Transmit block. */ 2178117659Swpaulstruct bge_tx_mac_stats { 217984059Swpaul bge_hostaddr ifHCOutOctets; 218084059Swpaul bge_hostaddr Reserved2; 218184059Swpaul bge_hostaddr etherStatsCollisions; 218284059Swpaul bge_hostaddr outXonSent; 218384059Swpaul bge_hostaddr outXoffSent; 218484059Swpaul bge_hostaddr flowControlDone; 218584059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 218684059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 218784059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 218884059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 218984059Swpaul bge_hostaddr Reserved3; 219084059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 219184059Swpaul bge_hostaddr dot3StatsLateCollisions; 219284059Swpaul bge_hostaddr dot3Collided2Times; 219384059Swpaul bge_hostaddr dot3Collided3Times; 219484059Swpaul bge_hostaddr dot3Collided4Times; 219584059Swpaul bge_hostaddr dot3Collided5Times; 219684059Swpaul bge_hostaddr dot3Collided6Times; 219784059Swpaul bge_hostaddr dot3Collided7Times; 219884059Swpaul bge_hostaddr dot3Collided8Times; 219984059Swpaul bge_hostaddr dot3Collided9Times; 220084059Swpaul bge_hostaddr dot3Collided10Times; 220184059Swpaul bge_hostaddr dot3Collided11Times; 220284059Swpaul bge_hostaddr dot3Collided12Times; 220384059Swpaul bge_hostaddr dot3Collided13Times; 220484059Swpaul bge_hostaddr dot3Collided14Times; 220584059Swpaul bge_hostaddr dot3Collided15Times; 220684059Swpaul bge_hostaddr ifHCOutUcastPkts; 220784059Swpaul bge_hostaddr ifHCOutMulticastPkts; 220884059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 220984059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 221084059Swpaul bge_hostaddr ifOutDiscards; 221184059Swpaul bge_hostaddr ifOutErrors; 2212117659Swpaul}; 221384059Swpaul 2214117659Swpaul/* Stats counters access through registers */ 2215117659Swpaulstruct bge_mac_stats_regs { 2216159395Sglebius uint32_t ifHCOutOctets; 2217159395Sglebius uint32_t Reserved0; 2218159395Sglebius uint32_t etherStatsCollisions; 2219159395Sglebius uint32_t outXonSent; 2220159395Sglebius uint32_t outXoffSent; 2221159395Sglebius uint32_t Reserved1; 2222159395Sglebius uint32_t dot3StatsInternalMacTransmitErrors; 2223159395Sglebius uint32_t dot3StatsSingleCollisionFrames; 2224159395Sglebius uint32_t dot3StatsMultipleCollisionFrames; 2225159395Sglebius uint32_t dot3StatsDeferredTransmissions; 2226159395Sglebius uint32_t Reserved2; 2227159395Sglebius uint32_t dot3StatsExcessiveCollisions; 2228159395Sglebius uint32_t dot3StatsLateCollisions; 2229159395Sglebius uint32_t Reserved3[14]; 2230159395Sglebius uint32_t ifHCOutUcastPkts; 2231159395Sglebius uint32_t ifHCOutMulticastPkts; 2232159395Sglebius uint32_t ifHCOutBroadcastPkts; 2233159395Sglebius uint32_t Reserved4[2]; 2234159395Sglebius uint32_t ifHCInOctets; 2235159395Sglebius uint32_t Reserved5; 2236159395Sglebius uint32_t etherStatsFragments; 2237159395Sglebius uint32_t ifHCInUcastPkts; 2238159395Sglebius uint32_t ifHCInMulticastPkts; 2239159395Sglebius uint32_t ifHCInBroadcastPkts; 2240159395Sglebius uint32_t dot3StatsFCSErrors; 2241159395Sglebius uint32_t dot3StatsAlignmentErrors; 2242159395Sglebius uint32_t xonPauseFramesReceived; 2243159395Sglebius uint32_t xoffPauseFramesReceived; 2244159395Sglebius uint32_t macControlFramesReceived; 2245159395Sglebius uint32_t xoffStateEntered; 2246159395Sglebius uint32_t dot3StatsFramesTooLong; 2247159395Sglebius uint32_t etherStatsJabbers; 2248159395Sglebius uint32_t etherStatsUndersizePkts; 2249117659Swpaul}; 2250117659Swpaul 2251117659Swpaulstruct bge_stats { 2252159395Sglebius uint8_t Reserved0[256]; 2253117659Swpaul 2254117659Swpaul /* Statistics maintained by Receive MAC. */ 2255117659Swpaul struct bge_rx_mac_stats rxstats; 2256117659Swpaul 2257117659Swpaul bge_hostaddr Unused1[37]; 2258117659Swpaul 2259117659Swpaul /* Statistics maintained by Transmit MAC. */ 2260117659Swpaul struct bge_tx_mac_stats txstats; 2261117659Swpaul 226284059Swpaul bge_hostaddr Unused2[31]; 226384059Swpaul 226484059Swpaul /* Statistics maintained by Receive List Placement. */ 226584059Swpaul bge_hostaddr COSIfHCInPkts[16]; 226684059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 226784059Swpaul bge_hostaddr nicDmaWriteQueueFull; 226884059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 226984059Swpaul bge_hostaddr nicNoMoreRxBDs; 227084059Swpaul bge_hostaddr ifInDiscards; 227184059Swpaul bge_hostaddr ifInErrors; 227284059Swpaul bge_hostaddr nicRecvThresholdHit; 227384059Swpaul 227484059Swpaul bge_hostaddr Unused3[9]; 227584059Swpaul 227684059Swpaul /* Statistics maintained by Send Data Initiator. */ 227784059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 227884059Swpaul bge_hostaddr nicDmaReadQueueFull; 227984059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 228084059Swpaul bge_hostaddr nicSendDataCompQueueFull; 228184059Swpaul 228284059Swpaul /* Statistics maintained by Host Coalescing. */ 228384059Swpaul bge_hostaddr nicRingSetSendProdIndex; 228484059Swpaul bge_hostaddr nicRingStatusUpdate; 228584059Swpaul bge_hostaddr nicInterrupts; 228684059Swpaul bge_hostaddr nicAvoidedInterrupts; 228784059Swpaul bge_hostaddr nicSendThresholdHit; 228884059Swpaul 2289159395Sglebius uint8_t Reserved4[320]; 229084059Swpaul}; 229184059Swpaul 229284059Swpaul/* 229384059Swpaul * Tigon general information block. This resides in host memory 229484059Swpaul * and contains the status counters, ring control blocks and 229584059Swpaul * producer pointers. 229684059Swpaul */ 229784059Swpaul 229884059Swpaulstruct bge_gib { 229984059Swpaul struct bge_stats bge_stats; 230084059Swpaul struct bge_rcb bge_tx_rcb[16]; 230184059Swpaul struct bge_rcb bge_std_rx_rcb; 230284059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 230384059Swpaul struct bge_rcb bge_mini_rx_rcb; 230484059Swpaul struct bge_rcb bge_return_rcb; 230584059Swpaul}; 230684059Swpaul 2307166676Sjkim#define BGE_FRAMELEN 1518 2308166676Sjkim#define BGE_MAX_FRAMELEN 1536 2309166676Sjkim#define BGE_JUMBO_FRAMELEN 9018 2310166676Sjkim#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2311166676Sjkim#define BGE_MIN_FRAMELEN 60 231284059Swpaul 231384059Swpaul/* 231484059Swpaul * Other utility macros. 231584059Swpaul */ 2316166676Sjkim#define BGE_INC(x, y) (x) = (x + 1) % y 231784059Swpaul 231884059Swpaul/* 231984059Swpaul * Register access macros. The Tigon always uses memory mapped register 232084059Swpaul * accesses and all registers must be accessed with 32 bit operations. 232184059Swpaul */ 232284059Swpaul 2323166676Sjkim#define CSR_WRITE_4(sc, reg, val) \ 232484059Swpaul bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 232584059Swpaul 2326166676Sjkim#define CSR_READ_4(sc, reg) \ 232784059Swpaul bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 232884059Swpaul 2329166676Sjkim#define BGE_SETBIT(sc, reg, x) \ 2330106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2331166676Sjkim#define BGE_CLRBIT(sc, reg, x) \ 2332106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 233384059Swpaul 2334166676Sjkim#define PCI_SETBIT(dev, reg, x, s) \ 2335106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2336166676Sjkim#define PCI_CLRBIT(dev, reg, x, s) \ 2337106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 233884059Swpaul 233984059Swpaul/* 234084059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 234184059Swpaul * values are tuneable. They control the actual amount of buffers 234284059Swpaul * allocated for the standard, mini and jumbo receive rings. 234384059Swpaul */ 234484059Swpaul 2345166676Sjkim#define BGE_SSLOTS 256 2346166676Sjkim#define BGE_MSLOTS 256 2347166676Sjkim#define BGE_JSLOTS 384 234884059Swpaul 2349166676Sjkim#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2350166676Sjkim#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2351159395Sglebius (BGE_JRAWLEN % sizeof(uint64_t)))) 2352166676Sjkim#define BGE_JPAGESZ PAGE_SIZE 2353166676Sjkim#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2354166676Sjkim#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 235584059Swpaul 2356166676Sjkim#define BGE_NSEG_JUMBO 4 2357166676Sjkim#define BGE_NSEG_NEW 32 2358153239Sglebius 235984059Swpaul/* 236084059Swpaul * Ring structures. Most of these reside in host memory and we tell 236184059Swpaul * the NIC where they are via the ring control blocks. The exceptions 236284059Swpaul * are the tx and command rings, which live in NIC memory and which 236384059Swpaul * we access via the shared memory window. 236484059Swpaul */ 2365118026Swpaul 236684059Swpaulstruct bge_ring_data { 2367118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2368118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2369153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2370118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2371118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2372118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2373118026Swpaul struct bge_tx_bd *bge_tx_ring; 2374118026Swpaul bus_addr_t bge_tx_ring_paddr; 2375118026Swpaul struct bge_status_block *bge_status_block; 2376118026Swpaul bus_addr_t bge_status_block_paddr; 2377118026Swpaul struct bge_stats *bge_stats; 2378118026Swpaul bus_addr_t bge_stats_paddr; 237984059Swpaul struct bge_gib bge_info; 238084059Swpaul}; 238184059Swpaul 2382166676Sjkim#define BGE_STD_RX_RING_SZ \ 2383118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2384166676Sjkim#define BGE_JUMBO_RX_RING_SZ \ 2385153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2386166676Sjkim#define BGE_TX_RING_SZ \ 2387118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2388166676Sjkim#define BGE_RX_RTN_RING_SZ(x) \ 2389118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2390118026Swpaul 2391166676Sjkim#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2392118026Swpaul 2393166676Sjkim#define BGE_STATS_SZ sizeof (struct bge_stats) 2394118026Swpaul 239584059Swpaul/* 239684059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 239784059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 239884059Swpaul * not the other way around. 239984059Swpaul */ 240084059Swpaulstruct bge_chain_data { 2401118026Swpaul bus_dma_tag_t bge_parent_tag; 2402118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2403118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2404118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2405118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2406118026Swpaul bus_dma_tag_t bge_status_tag; 2407118026Swpaul bus_dma_tag_t bge_stats_tag; 2408118026Swpaul bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2409118026Swpaul bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2410118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2411118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2412118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2413118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2414118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2415118026Swpaul bus_dmamap_t bge_tx_ring_map; 2416118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2417118026Swpaul bus_dmamap_t bge_status_map; 2418118026Swpaul bus_dmamap_t bge_stats_map; 241984059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 242084059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 242184059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 242284059Swpaul}; 242384059Swpaul 2424118026Swpaulstruct bge_dmamap_arg { 2425118026Swpaul struct bge_softc *sc; 2426118026Swpaul bus_addr_t bge_busaddr; 2427159395Sglebius uint16_t bge_flags; 2428118026Swpaul int bge_idx; 2429118026Swpaul int bge_maxsegs; 2430118026Swpaul struct bge_tx_bd *bge_ring; 2431118026Swpaul}; 2432118026Swpaul 2433166676Sjkim#define BGE_HWREV_TIGON 0x01 2434166676Sjkim#define BGE_HWREV_TIGON_II 0x02 2435166676Sjkim#define BGE_TIMEOUT 100000 2436166676Sjkim#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 243784059Swpaul 243884059Swpaulstruct bge_bcom_hack { 243984059Swpaul int reg; 244084059Swpaul int val; 244184059Swpaul}; 244284059Swpaul 2443166676Sjkim#define ASF_ENABLE 1 2444166676Sjkim#define ASF_NEW_HANDSHAKE 2 2445166676Sjkim#define ASF_STACKUP 4 2446162169Sambrisko 244784059Swpaulstruct bge_softc { 2448147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 244984059Swpaul device_t bge_dev; 2450122497Ssam struct mtx bge_mtx; 245184059Swpaul device_t bge_miibus; 245284059Swpaul bus_space_handle_t bge_bhandle; 245384059Swpaul bus_space_tag_t bge_btag; 245484059Swpaul void *bge_intrhand; 245584059Swpaul struct resource *bge_irq; 245684059Swpaul struct resource *bge_res; 245784059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2458161546Sglebius uint32_t bge_flags; 2459166676Sjkim#define BGE_FLAG_TBI 0x00000001 2460166676Sjkim#define BGE_FLAG_JUMBO 0x00000002 2461169152Smarius#define BGE_FLAG_EEPROM 0x00000004 2462166676Sjkim#define BGE_FLAG_MSI 0x00000100 2463166676Sjkim#define BGE_FLAG_PCIX 0x00000200 2464166676Sjkim#define BGE_FLAG_PCIE 0x00000400 2465166676Sjkim#define BGE_FLAG_5700_FAMILY 0x00001000 2466166676Sjkim#define BGE_FLAG_5705_PLUS 0x00002000 2467166676Sjkim#define BGE_FLAG_5714_FAMILY 0x00004000 2468166676Sjkim#define BGE_FLAG_575X_PLUS 0x00008000 2469166676Sjkim#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2470166676Sjkim#define BGE_FLAG_NO_3LED 0x00200000 2471166676Sjkim#define BGE_FLAG_ADC_BUG 0x00400000 2472166676Sjkim#define BGE_FLAG_5704_A0_BUG 0x00800000 2473166676Sjkim#define BGE_FLAG_JITTER_BUG 0x01000000 2474166676Sjkim#define BGE_FLAG_BER_BUG 0x02000000 2475166676Sjkim#define BGE_FLAG_ADJUST_TRIM 0x04000000 2476166677Sjkim#define BGE_FLAG_CRC_BUG 0x08000000 2477159395Sglebius uint32_t bge_chipid; 2478162169Sambrisko uint8_t bge_asicrev; 2479162169Sambrisko uint8_t bge_chiprev; 2480162169Sambrisko uint8_t bge_asf_mode; 2481162169Sambrisko uint8_t bge_asf_count; 2482118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 248384059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 2484159395Sglebius uint16_t bge_tx_saved_considx; 2485159395Sglebius uint16_t bge_rx_saved_considx; 2486159395Sglebius uint16_t bge_ev_saved_considx; 2487159395Sglebius uint16_t bge_return_ring_cnt; 2488159395Sglebius uint16_t bge_std; /* current std ring head */ 2489159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 2490159395Sglebius uint32_t bge_stat_ticks; 2491159395Sglebius uint32_t bge_rx_coal_ticks; 2492159395Sglebius uint32_t bge_tx_coal_ticks; 2493159395Sglebius uint32_t bge_tx_prodidx; 2494159395Sglebius uint32_t bge_rx_max_coal_bds; 2495159395Sglebius uint32_t bge_tx_max_coal_bds; 2496159395Sglebius uint32_t bge_tx_buf_ratio; 249784059Swpaul int bge_if_flags; 249884059Swpaul int bge_txcnt; 2499155180Soleg int bge_link; /* link state */ 2500155180Soleg int bge_link_evt; /* pending link event */ 2501164769Sglebius int bge_timer; 2502122497Ssam struct callout bge_stat_ch; 2503164780Sjkim uint32_t bge_rx_discards; 2504164780Sjkim uint32_t bge_tx_discards; 2505164780Sjkim uint32_t bge_tx_collisions; 2506151553Sglebius#ifdef DEVICE_POLLING 2507151553Sglebius int rxcycles; 2508151553Sglebius#endif /* DEVICE_POLLING */ 250984059Swpaul}; 2510122497Ssam 2511122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2512122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2513122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2514122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2515122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2516122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2517