if_bgereg.h revision 166677
1139749Simp/*-
284059Swpaul * Copyright (c) 2001 Wind River Systems
384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001
484059Swpaul *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
584059Swpaul *
684059Swpaul * Redistribution and use in source and binary forms, with or without
784059Swpaul * modification, are permitted provided that the following conditions
884059Swpaul * are met:
984059Swpaul * 1. Redistributions of source code must retain the above copyright
1084059Swpaul *    notice, this list of conditions and the following disclaimer.
1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright
1284059Swpaul *    notice, this list of conditions and the following disclaimer in the
1384059Swpaul *    documentation and/or other materials provided with the distribution.
1484059Swpaul * 3. All advertising materials mentioning features or use of this software
1584059Swpaul *    must display the following acknowledgement:
1684059Swpaul *	This product includes software developed by Bill Paul.
1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors
1884059Swpaul *    may be used to endorse or promote products derived from this software
1984059Swpaul *    without specific prior written permission.
2084059Swpaul *
2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2484059Swpaul * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE.
3284059Swpaul *
3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 166677 2007-02-12 23:58:52Z jkim $
3484059Swpaul */
3584059Swpaul
3684059Swpaul/*
3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat
3884059Swpaul * depending on whether or not we have external SSRAM attached.
3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701
4084059Swpaul * is apparently not designed to use external SSRAM. The mappings
4184059Swpaul * up to the first 4 send rings are the same for both internal and
4284059Swpaul * external memory configurations. Note that mini RX ring space is
4384059Swpaul * only available with external SSRAM configurations, which means
4484059Swpaul * the mini RX ring is not supported on the BCM5701.
4584059Swpaul *
4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways:
4784059Swpaul *
4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
4984059Swpaul *    registers in PCI config space can be used to read any 32-bit
5084059Swpaul *    address within the NIC's memory.
5184059Swpaul *
5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
5384059Swpaul *    space can be used in conjunction with the memory window in the
5484059Swpaul *    device register space at offset 0x8000 to read any 32K chunk
5584059Swpaul *    of NIC memory.
5684059Swpaul *
5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
5884059Swpaul *    set, the device I/O mapping consumes 32MB of host address space,
5984059Swpaul *    allowing all of the registers and internal NIC memory to be
6084059Swpaul *    accessed directly. NIC memory addresses are offset by 0x01000000.
6184059Swpaul *    Flat mode consumes so much host address space that it is not
6284059Swpaul *    recommended.
6384059Swpaul */
64166676Sjkim#define	BGE_PAGE_ZERO			0x00000000
65166676Sjkim#define	BGE_PAGE_ZERO_END		0x000000FF
66166676Sjkim#define	BGE_SEND_RING_RCB		0x00000100
67166676Sjkim#define	BGE_SEND_RING_RCB_END		0x000001FF
68166676Sjkim#define	BGE_RX_RETURN_RING_RCB		0x00000200
69166676Sjkim#define	BGE_RX_RETURN_RING_RCB_END	0x000002FF
70166676Sjkim#define	BGE_STATS_BLOCK			0x00000300
71166676Sjkim#define	BGE_STATS_BLOCK_END		0x00000AFF
72166676Sjkim#define	BGE_STATUS_BLOCK		0x00000B00
73166676Sjkim#define	BGE_STATUS_BLOCK_END		0x00000B4F
74166676Sjkim#define	BGE_SOFTWARE_GENCOMM		0x00000B50
75166676Sjkim#define	BGE_SOFTWARE_GENCOMM_SIG	0x00000B54
76166676Sjkim#define	BGE_SOFTWARE_GENCOMM_NICCFG	0x00000B58
77166676Sjkim#define	BGE_SOFTWARE_GENCOMM_FW		0x00000B78
78166676Sjkim#define	BGE_SOFTWARE_GENNCOMM_FW_LEN	0x00000B7C
79166676Sjkim#define	BGE_SOFTWARE_GENNCOMM_FW_DATA	0x00000B80
80166676Sjkim#define	BGE_SOFTWARE_GENCOMM_END	0x00000FFF
81166676Sjkim#define	BGE_UNMAPPED			0x00001000
82166676Sjkim#define	BGE_UNMAPPED_END		0x00001FFF
83166676Sjkim#define	BGE_DMA_DESCRIPTORS		0x00002000
84166676Sjkim#define	BGE_DMA_DESCRIPTORS_END		0x00003FFF
85166676Sjkim#define	BGE_SEND_RING_1_TO_4		0x00004000
86166676Sjkim#define	BGE_SEND_RING_1_TO_4_END	0x00005FFF
8784059Swpaul
88166676Sjkim/* Firmware interface */
89166676Sjkim#define	BGE_FW_DRV_ALIVE		0x00000001
90166676Sjkim#define	BGE_FW_PAUSE			0x00000002
91166676Sjkim
9284059Swpaul/* Mappings for internal memory configuration */
93166676Sjkim#define	BGE_STD_RX_RINGS		0x00006000
94166676Sjkim#define	BGE_STD_RX_RINGS_END		0x00006FFF
95166676Sjkim#define	BGE_JUMBO_RX_RINGS		0x00007000
96166676Sjkim#define	BGE_JUMBO_RX_RINGS_END		0x00007FFF
97166676Sjkim#define	BGE_BUFFPOOL_1			0x00008000
98166676Sjkim#define	BGE_BUFFPOOL_1_END		0x0000FFFF
99166676Sjkim#define	BGE_BUFFPOOL_2			0x00010000 /* or expansion ROM */
100166676Sjkim#define	BGE_BUFFPOOL_2_END		0x00017FFF
101166676Sjkim#define	BGE_BUFFPOOL_3			0x00018000 /* or expansion ROM */
102166676Sjkim#define	BGE_BUFFPOOL_3_END		0x0001FFFF
10384059Swpaul
10484059Swpaul/* Mappings for external SSRAM configurations */
105166676Sjkim#define	BGE_SEND_RING_5_TO_6		0x00006000
106166676Sjkim#define	BGE_SEND_RING_5_TO_6_END	0x00006FFF
107166676Sjkim#define	BGE_SEND_RING_7_TO_8		0x00007000
108166676Sjkim#define	BGE_SEND_RING_7_TO_8_END	0x00007FFF
109166676Sjkim#define	BGE_SEND_RING_9_TO_16		0x00008000
110166676Sjkim#define	BGE_SEND_RING_9_TO_16_END	0x0000BFFF
111166676Sjkim#define	BGE_EXT_STD_RX_RINGS		0x0000C000
112166676Sjkim#define	BGE_EXT_STD_RX_RINGS_END	0x0000CFFF
113166676Sjkim#define	BGE_EXT_JUMBO_RX_RINGS		0x0000D000
114166676Sjkim#define	BGE_EXT_JUMBO_RX_RINGS_END	0x0000DFFF
115166676Sjkim#define	BGE_MINI_RX_RINGS		0x0000E000
116166676Sjkim#define	BGE_MINI_RX_RINGS_END		0x0000FFFF
117166676Sjkim#define	BGE_AVAIL_REGION1		0x00010000 /* or expansion ROM */
118166676Sjkim#define	BGE_AVAIL_REGION1_END		0x00017FFF
119166676Sjkim#define	BGE_AVAIL_REGION2		0x00018000 /* or expansion ROM */
120166676Sjkim#define	BGE_AVAIL_REGION2_END		0x0001FFFF
121166676Sjkim#define	BGE_EXT_SSRAM			0x00020000
122166676Sjkim#define	BGE_EXT_SSRAM_END		0x000FFFFF
12384059Swpaul
12484059Swpaul
12584059Swpaul/*
12684059Swpaul * BCM570x register offsets. These are memory mapped registers
12784059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
12884059Swpaul * Each register must be accessed using 32 bit operations.
12984059Swpaul *
13084059Swpaul * All registers are accessed through a 32K shared memory block.
13184059Swpaul * The first group of registers are actually copies of the PCI
13284059Swpaul * configuration space registers.
13384059Swpaul */
13484059Swpaul
13584059Swpaul/*
13684059Swpaul * PCI registers defined in the PCI 2.2 spec.
13784059Swpaul */
138166676Sjkim#define	BGE_PCI_VID			0x00
139166676Sjkim#define	BGE_PCI_DID			0x02
140166676Sjkim#define	BGE_PCI_CMD			0x04
141166676Sjkim#define	BGE_PCI_STS			0x06
142166676Sjkim#define	BGE_PCI_REV			0x08
143166676Sjkim#define	BGE_PCI_CLASS			0x09
144166676Sjkim#define	BGE_PCI_CACHESZ			0x0C
145166676Sjkim#define	BGE_PCI_LATTIMER		0x0D
146166676Sjkim#define	BGE_PCI_HDRTYPE			0x0E
147166676Sjkim#define	BGE_PCI_BIST			0x0F
148166676Sjkim#define	BGE_PCI_BAR0			0x10
149166676Sjkim#define	BGE_PCI_BAR1			0x14
150166676Sjkim#define	BGE_PCI_SUBSYS			0x2C
151166676Sjkim#define	BGE_PCI_SUBVID			0x2E
152166676Sjkim#define	BGE_PCI_ROMBASE			0x30
153166676Sjkim#define	BGE_PCI_CAPPTR			0x34
154166676Sjkim#define	BGE_PCI_INTLINE			0x3C
155166676Sjkim#define	BGE_PCI_INTPIN			0x3D
156166676Sjkim#define	BGE_PCI_MINGNT			0x3E
157166676Sjkim#define	BGE_PCI_MAXLAT			0x3F
158166676Sjkim#define	BGE_PCI_PCIXCAP			0x40
159166676Sjkim#define	BGE_PCI_NEXTPTR_PM		0x41
160166676Sjkim#define	BGE_PCI_PCIX_CMD		0x42
161166676Sjkim#define	BGE_PCI_PCIX_STS		0x44
162166676Sjkim#define	BGE_PCI_PWRMGMT_CAPID		0x48
163166676Sjkim#define	BGE_PCI_NEXTPTR_VPD		0x49
164166676Sjkim#define	BGE_PCI_PWRMGMT_CAPS		0x4A
165166676Sjkim#define	BGE_PCI_PWRMGMT_CMD		0x4C
166166676Sjkim#define	BGE_PCI_PWRMGMT_STS		0x4D
167166676Sjkim#define	BGE_PCI_PWRMGMT_DATA		0x4F
168166676Sjkim#define	BGE_PCI_VPD_CAPID		0x50
169166676Sjkim#define	BGE_PCI_NEXTPTR_MSI		0x51
170166676Sjkim#define	BGE_PCI_VPD_ADDR		0x52
171166676Sjkim#define	BGE_PCI_VPD_DATA		0x54
172166676Sjkim#define	BGE_PCI_MSI_CAPID		0x58
173166676Sjkim#define	BGE_PCI_NEXTPTR_NONE		0x59
174166676Sjkim#define	BGE_PCI_MSI_CTL			0x5A
175166676Sjkim#define	BGE_PCI_MSI_ADDR_HI		0x5C
176166676Sjkim#define	BGE_PCI_MSI_ADDR_LO		0x60
177166676Sjkim#define	BGE_PCI_MSI_DATA		0x64
17884059Swpaul
179135772Sps/* PCI MSI. ??? */
180166676Sjkim#define	BGE_PCIE_CAPID_REG		0xD0
181166676Sjkim#define	BGE_PCIE_CAPID			0x10
182135772Sps
18384059Swpaul/*
18484059Swpaul * PCI registers specific to the BCM570x family.
18584059Swpaul */
186166676Sjkim#define	BGE_PCI_MISC_CTL		0x68
187166676Sjkim#define	BGE_PCI_DMA_RW_CTL		0x6C
188166676Sjkim#define	BGE_PCI_PCISTATE		0x70
189166676Sjkim#define	BGE_PCI_CLKCTL			0x74
190166676Sjkim#define	BGE_PCI_REG_BASEADDR		0x78
191166676Sjkim#define	BGE_PCI_MEMWIN_BASEADDR		0x7C
192166676Sjkim#define	BGE_PCI_REG_DATA		0x80
193166676Sjkim#define	BGE_PCI_MEMWIN_DATA		0x84
194166676Sjkim#define	BGE_PCI_MODECTL			0x88
195166676Sjkim#define	BGE_PCI_MISC_CFG		0x8C
196166676Sjkim#define	BGE_PCI_MISC_LOCALCTL		0x90
197166676Sjkim#define	BGE_PCI_UNDI_RX_STD_PRODIDX_HI	0x98
198166676Sjkim#define	BGE_PCI_UNDI_RX_STD_PRODIDX_LO	0x9C
199166676Sjkim#define	BGE_PCI_UNDI_RX_RTN_CONSIDX_HI	0xA0
200166676Sjkim#define	BGE_PCI_UNDI_RX_RTN_CONSIDX_LO	0xA4
201166676Sjkim#define	BGE_PCI_UNDI_TX_BD_PRODIDX_HI	0xA8
202166676Sjkim#define	BGE_PCI_UNDI_TX_BD_PRODIDX_LO	0xAC
203166676Sjkim#define	BGE_PCI_ISR_MBX_HI		0xB0
204166676Sjkim#define	BGE_PCI_ISR_MBX_LO		0xB4
20584059Swpaul
20684059Swpaul/* PCI Misc. Host control register */
207166676Sjkim#define	BGE_PCIMISCCTL_CLEAR_INTA	0x00000001
208166676Sjkim#define	BGE_PCIMISCCTL_MASK_PCI_INTR	0x00000002
209166676Sjkim#define	BGE_PCIMISCCTL_ENDIAN_BYTESWAP	0x00000004
210166676Sjkim#define	BGE_PCIMISCCTL_ENDIAN_WORDSWAP	0x00000008
211166676Sjkim#define	BGE_PCIMISCCTL_PCISTATE_RW	0x00000010
212166676Sjkim#define	BGE_PCIMISCCTL_CLOCKCTL_RW	0x00000020
213166676Sjkim#define	BGE_PCIMISCCTL_REG_WORDSWAP	0x00000040
214166676Sjkim#define	BGE_PCIMISCCTL_INDIRECT_ACCESS	0x00000080
215166676Sjkim#define	BGE_PCIMISCCTL_ASICREV		0xFFFF0000
21684059Swpaul
217166676Sjkim#define	BGE_HIF_SWAP_OPTIONS	(BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
218153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN
219166676Sjkim#define	BGE_DMA_SWAP_OPTIONS \
220153437Syongari	BGE_MODECTL_WORDSWAP_NONFRAME| \
221153437Syongari	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
222153437Syongari#else
223166676Sjkim#define	BGE_DMA_SWAP_OPTIONS \
224153437Syongari	BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \
225153437Syongari	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
226153437Syongari#endif
22784059Swpaul
228166676Sjkim#define	BGE_INIT \
229153437Syongari	(BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
230153437Syongari	 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
23184059Swpaul
232166676Sjkim#define	BGE_CHIPID_TIGON_I		0x40000000
233166676Sjkim#define	BGE_CHIPID_TIGON_II		0x60000000
234166676Sjkim#define	BGE_CHIPID_BCM5700_A0		0x70000000
235166676Sjkim#define	BGE_CHIPID_BCM5700_A1		0x70010000
236166676Sjkim#define	BGE_CHIPID_BCM5700_B0		0x71000000
237166676Sjkim#define	BGE_CHIPID_BCM5700_B1		0x71010000
238166676Sjkim#define	BGE_CHIPID_BCM5700_B2		0x71020000
239166676Sjkim#define	BGE_CHIPID_BCM5700_B3		0x71030000
240166676Sjkim#define	BGE_CHIPID_BCM5700_ALTIMA	0x71040000
241166676Sjkim#define	BGE_CHIPID_BCM5700_C0		0x72000000
242166676Sjkim#define	BGE_CHIPID_BCM5701_A0		0x00000000	/* grrrr */
243166676Sjkim#define	BGE_CHIPID_BCM5701_B0		0x01000000
244166676Sjkim#define	BGE_CHIPID_BCM5701_B2		0x01020000
245166676Sjkim#define	BGE_CHIPID_BCM5701_B5		0x01050000
246166676Sjkim#define	BGE_CHIPID_BCM5703_A0		0x10000000
247166676Sjkim#define	BGE_CHIPID_BCM5703_A1		0x10010000
248166676Sjkim#define	BGE_CHIPID_BCM5703_A2		0x10020000
249166676Sjkim#define	BGE_CHIPID_BCM5703_A3		0x10030000
250166676Sjkim#define	BGE_CHIPID_BCM5703_B0		0x11000000
251166676Sjkim#define	BGE_CHIPID_BCM5704_A0		0x20000000
252166676Sjkim#define	BGE_CHIPID_BCM5704_A1		0x20010000
253166676Sjkim#define	BGE_CHIPID_BCM5704_A2		0x20020000
254166676Sjkim#define	BGE_CHIPID_BCM5704_A3		0x20030000
255166676Sjkim#define	BGE_CHIPID_BCM5704_B0		0x21000000
256166676Sjkim#define	BGE_CHIPID_BCM5705_A0		0x30000000
257166676Sjkim#define	BGE_CHIPID_BCM5705_A1		0x30010000
258166676Sjkim#define	BGE_CHIPID_BCM5705_A2		0x30020000
259166676Sjkim#define	BGE_CHIPID_BCM5705_A3		0x30030000
260166676Sjkim#define	BGE_CHIPID_BCM5750_A0		0x40000000
261166676Sjkim#define	BGE_CHIPID_BCM5750_A1		0x40010000
262166676Sjkim#define	BGE_CHIPID_BCM5750_A3		0x40030000
263166676Sjkim#define	BGE_CHIPID_BCM5750_B0		0x41000000
264166676Sjkim#define	BGE_CHIPID_BCM5750_B1		0x41010000
265166676Sjkim#define	BGE_CHIPID_BCM5750_C0		0x42000000
266166676Sjkim#define	BGE_CHIPID_BCM5750_C1		0x42010000
267166676Sjkim#define	BGE_CHIPID_BCM5750_C2		0x42020000
268166676Sjkim#define	BGE_CHIPID_BCM5714_A0		0x50000000
269166676Sjkim#define	BGE_CHIPID_BCM5752_A0		0x60000000
270166676Sjkim#define	BGE_CHIPID_BCM5752_A1		0x60010000
271166676Sjkim#define	BGE_CHIPID_BCM5752_A2		0x60020000
272166676Sjkim#define	BGE_CHIPID_BCM5714_B0		0x80000000
273166676Sjkim#define	BGE_CHIPID_BCM5714_B3		0x80030000
274166676Sjkim#define	BGE_CHIPID_BCM5715_A0		0x90000000
275166676Sjkim#define	BGE_CHIPID_BCM5715_A1		0x90010000
276166676Sjkim#define	BGE_CHIPID_BCM5755_A0		0xa0000000
277166676Sjkim#define	BGE_CHIPID_BCM5755_A1		0xa0010000
278166676Sjkim#define	BGE_CHIPID_BCM5755_A2		0xa0020000
279166676Sjkim#define	BGE_CHIPID_BCM5754_A0		0xb0000000
280166676Sjkim#define	BGE_CHIPID_BCM5754_A1		0xb0010000
281166676Sjkim#define	BGE_CHIPID_BCM5754_A2		0xb0020000
282166676Sjkim#define	BGE_CHIPID_BCM5787_A0		0xb0000000
283166676Sjkim#define	BGE_CHIPID_BCM5787_A1		0xb0010000
284166676Sjkim#define	BGE_CHIPID_BCM5787_A2		0xb0020000
28584059Swpaul
28693751Swpaul/* shorthand one */
287166676Sjkim#define	BGE_ASICREV(x)			((x) >> 28)
288166676Sjkim#define	BGE_ASICREV_BCM5701		0x00
289166676Sjkim#define	BGE_ASICREV_BCM5703		0x01
290166676Sjkim#define	BGE_ASICREV_BCM5704		0x02
291166676Sjkim#define	BGE_ASICREV_BCM5705		0x03
292166676Sjkim#define	BGE_ASICREV_BCM5750		0x04
293166676Sjkim#define	BGE_ASICREV_BCM5714_A0		0x05
294166676Sjkim#define	BGE_ASICREV_BCM5752		0x06
295166676Sjkim#define	BGE_ASICREV_BCM5700		0x07
296166676Sjkim#define	BGE_ASICREV_BCM5780		0x08
297166676Sjkim#define	BGE_ASICREV_BCM5714		0x09
298166676Sjkim#define	BGE_ASICREV_BCM5755		0x0a
299166676Sjkim#define	BGE_ASICREV_BCM5754		0x0b
300166676Sjkim#define	BGE_ASICREV_BCM5787		0x0b
30193751Swpaul
302114813Sps/* chip revisions */
303166676Sjkim#define	BGE_CHIPREV(x)			((x) >> 24)
304166676Sjkim#define	BGE_CHIPREV_5700_AX		0x70
305166676Sjkim#define	BGE_CHIPREV_5700_BX		0x71
306166676Sjkim#define	BGE_CHIPREV_5700_CX		0x72
307166676Sjkim#define	BGE_CHIPREV_5701_AX		0x00
308166676Sjkim#define	BGE_CHIPREV_5703_AX		0x10
309166676Sjkim#define	BGE_CHIPREV_5704_AX		0x20
310166676Sjkim#define	BGE_CHIPREV_5704_BX		0x21
311166676Sjkim#define	BGE_CHIPREV_5750_AX		0x40
312166676Sjkim#define	BGE_CHIPREV_5750_BX		0x41
313114813Sps
31484059Swpaul/* PCI DMA Read/Write Control register */
315166676Sjkim#define	BGE_PCIDMARWCTL_MINDMA		0x000000FF
316166676Sjkim#define	BGE_PCIDMARWCTL_RDADRR_BNDRY	0x00000700
317166676Sjkim#define	BGE_PCIDMARWCTL_WRADDR_BNDRY	0x00003800
318166676Sjkim#define	BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x00004000
319166676Sjkim#define	BGE_PCIDMARWCTL_RD_WAT		0x00070000
320166676Sjkim#define	BGE_PCIDMARWCTL_WR_WAT		0x00380000
321166676Sjkim#define	BGE_PCIDMARWCTL_USE_MRM		0x00400000
322166676Sjkim#define	BGE_PCIDMARWCTL_ASRT_ALL_BE	0x00800000
323166676Sjkim#define	BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD	0x0F000000
324166676Sjkim#define	BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD	0xF0000000
32584059Swpaul
326166676Sjkim#define	BGE_PCIDMARWCTL_RD_WAT_SHIFT(x)	((x) << 16)
327166676Sjkim#define	BGE_PCIDMARWCTL_WR_WAT_SHIFT(x)	((x) << 19)
328166676Sjkim#define	BGE_PCIDMARWCTL_RD_CMD_SHIFT(x)	((x) << 24)
329166676Sjkim#define	BGE_PCIDMARWCTL_WR_CMD_SHIFT(x)	((x) << 28)
33084059Swpaul
331166676Sjkim#define	BGE_PCI_READ_BNDRY_DISABLE	0x00000000
332166676Sjkim#define	BGE_PCI_READ_BNDRY_16BYTES	0x00000100
333166676Sjkim#define	BGE_PCI_READ_BNDRY_32BYTES	0x00000200
334166676Sjkim#define	BGE_PCI_READ_BNDRY_64BYTES	0x00000300
335166676Sjkim#define	BGE_PCI_READ_BNDRY_128BYTES	0x00000400
336166676Sjkim#define	BGE_PCI_READ_BNDRY_256BYTES	0x00000500
337166676Sjkim#define	BGE_PCI_READ_BNDRY_512BYTES	0x00000600
338166676Sjkim#define	BGE_PCI_READ_BNDRY_1024BYTES	0x00000700
33984059Swpaul
340166676Sjkim#define	BGE_PCI_WRITE_BNDRY_DISABLE	0x00000000
341166676Sjkim#define	BGE_PCI_WRITE_BNDRY_16BYTES	0x00000800
342166676Sjkim#define	BGE_PCI_WRITE_BNDRY_32BYTES	0x00001000
343166676Sjkim#define	BGE_PCI_WRITE_BNDRY_64BYTES	0x00001800
344166676Sjkim#define	BGE_PCI_WRITE_BNDRY_128BYTES	0x00002000
345166676Sjkim#define	BGE_PCI_WRITE_BNDRY_256BYTES	0x00002800
346166676Sjkim#define	BGE_PCI_WRITE_BNDRY_512BYTES	0x00003000
347166676Sjkim#define	BGE_PCI_WRITE_BNDRY_1024BYTES	0x00003800
348166676Sjkim
34984059Swpaul/*
35084059Swpaul * PCI state register -- note, this register is read only
35184059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control
35284059Swpaul * register is set.
35384059Swpaul */
354166676Sjkim#define	BGE_PCISTATE_FORCE_RESET	0x00000001
355166676Sjkim#define	BGE_PCISTATE_INTR_STATE		0x00000002
356166676Sjkim#define	BGE_PCISTATE_PCI_BUSMODE	0x00000004 /* 1 = PCI, 0 = PCI-X */
357166676Sjkim#define	BGE_PCISTATE_PCI_BUSSPEED	0x00000008 /* 1 = 66/133, 0 = 33/66 */
358166676Sjkim#define	BGE_PCISTATE_32BIT_BUS		0x00000010 /* 1 = 32bit, 0 = 64bit */
359166676Sjkim#define	BGE_PCISTATE_WANT_EXPROM	0x00000020
360166676Sjkim#define	BGE_PCISTATE_EXPROM_RETRY	0x00000040
361166676Sjkim#define	BGE_PCISTATE_FLATVIEW_MODE	0x00000100
362166676Sjkim#define	BGE_PCISTATE_PCI_TGT_RETRY_MAX	0x00000E00
36384059Swpaul
36484059Swpaul/*
36584059Swpaul * PCI Clock Control register -- note, this register is read only
36684059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
36784059Swpaul * register is set.
36884059Swpaul */
369166676Sjkim#define	BGE_PCICLOCKCTL_DETECTED_SPEED	0x0000000F
370166676Sjkim#define	BGE_PCICLOCKCTL_M66EN		0x00000080
371166676Sjkim#define	BGE_PCICLOCKCTL_LOWPWR_CLKMODE	0x00000200
372166676Sjkim#define	BGE_PCICLOCKCTL_RXCPU_CLK_DIS	0x00000400
373166676Sjkim#define	BGE_PCICLOCKCTL_TXCPU_CLK_DIS	0x00000800
374166676Sjkim#define	BGE_PCICLOCKCTL_ALTCLK		0x00001000
375166676Sjkim#define	BGE_PCICLOCKCTL_ALTCLK_SRC	0x00002000
376166676Sjkim#define	BGE_PCICLOCKCTL_PCIPLL_DISABLE	0x00004000
377166676Sjkim#define	BGE_PCICLOCKCTL_SYSPLL_DISABLE	0x00008000
378166676Sjkim#define	BGE_PCICLOCKCTL_BIST_ENABLE	0x00010000
37984059Swpaul
38084059Swpaul
38184059Swpaul#ifndef PCIM_CMD_MWIEN
382166676Sjkim#define	PCIM_CMD_MWIEN			0x0010
38384059Swpaul#endif
38484059Swpaul
38584059Swpaul/*
38684059Swpaul * High priority mailbox registers
38784059Swpaul * Each mailbox is 64-bits wide, though we only use the
38884059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits
38984059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word
39084059Swpaul * has been updated.
39184059Swpaul */
392166676Sjkim#define	BGE_MBX_IRQ0_HI			0x0200
393166676Sjkim#define	BGE_MBX_IRQ0_LO			0x0204
394166676Sjkim#define	BGE_MBX_IRQ1_HI			0x0208
395166676Sjkim#define	BGE_MBX_IRQ1_LO			0x020C
396166676Sjkim#define	BGE_MBX_IRQ2_HI			0x0210
397166676Sjkim#define	BGE_MBX_IRQ2_LO			0x0214
398166676Sjkim#define	BGE_MBX_IRQ3_HI			0x0218
399166676Sjkim#define	BGE_MBX_IRQ3_LO			0x021C
400166676Sjkim#define	BGE_MBX_GEN0_HI			0x0220
401166676Sjkim#define	BGE_MBX_GEN0_LO			0x0224
402166676Sjkim#define	BGE_MBX_GEN1_HI			0x0228
403166676Sjkim#define	BGE_MBX_GEN1_LO			0x022C
404166676Sjkim#define	BGE_MBX_GEN2_HI			0x0230
405166676Sjkim#define	BGE_MBX_GEN2_LO			0x0234
406166676Sjkim#define	BGE_MBX_GEN3_HI			0x0228
407166676Sjkim#define	BGE_MBX_GEN3_LO			0x022C
408166676Sjkim#define	BGE_MBX_GEN4_HI			0x0240
409166676Sjkim#define	BGE_MBX_GEN4_LO			0x0244
410166676Sjkim#define	BGE_MBX_GEN5_HI			0x0248
411166676Sjkim#define	BGE_MBX_GEN5_LO			0x024C
412166676Sjkim#define	BGE_MBX_GEN6_HI			0x0250
413166676Sjkim#define	BGE_MBX_GEN6_LO			0x0254
414166676Sjkim#define	BGE_MBX_GEN7_HI			0x0258
415166676Sjkim#define	BGE_MBX_GEN7_LO			0x025C
416166676Sjkim#define	BGE_MBX_RELOAD_STATS_HI		0x0260
417166676Sjkim#define	BGE_MBX_RELOAD_STATS_LO		0x0264
418166676Sjkim#define	BGE_MBX_RX_STD_PROD_HI		0x0268
419166676Sjkim#define	BGE_MBX_RX_STD_PROD_LO		0x026C
420166676Sjkim#define	BGE_MBX_RX_JUMBO_PROD_HI	0x0270
421166676Sjkim#define	BGE_MBX_RX_JUMBO_PROD_LO	0x0274
422166676Sjkim#define	BGE_MBX_RX_MINI_PROD_HI		0x0278
423166676Sjkim#define	BGE_MBX_RX_MINI_PROD_LO		0x027C
424166676Sjkim#define	BGE_MBX_RX_CONS0_HI		0x0280
425166676Sjkim#define	BGE_MBX_RX_CONS0_LO		0x0284
426166676Sjkim#define	BGE_MBX_RX_CONS1_HI		0x0288
427166676Sjkim#define	BGE_MBX_RX_CONS1_LO		0x028C
428166676Sjkim#define	BGE_MBX_RX_CONS2_HI		0x0290
429166676Sjkim#define	BGE_MBX_RX_CONS2_LO		0x0294
430166676Sjkim#define	BGE_MBX_RX_CONS3_HI		0x0298
431166676Sjkim#define	BGE_MBX_RX_CONS3_LO		0x029C
432166676Sjkim#define	BGE_MBX_RX_CONS4_HI		0x02A0
433166676Sjkim#define	BGE_MBX_RX_CONS4_LO		0x02A4
434166676Sjkim#define	BGE_MBX_RX_CONS5_HI		0x02A8
435166676Sjkim#define	BGE_MBX_RX_CONS5_LO		0x02AC
436166676Sjkim#define	BGE_MBX_RX_CONS6_HI		0x02B0
437166676Sjkim#define	BGE_MBX_RX_CONS6_LO		0x02B4
438166676Sjkim#define	BGE_MBX_RX_CONS7_HI		0x02B8
439166676Sjkim#define	BGE_MBX_RX_CONS7_LO		0x02BC
440166676Sjkim#define	BGE_MBX_RX_CONS8_HI		0x02C0
441166676Sjkim#define	BGE_MBX_RX_CONS8_LO		0x02C4
442166676Sjkim#define	BGE_MBX_RX_CONS9_HI		0x02C8
443166676Sjkim#define	BGE_MBX_RX_CONS9_LO		0x02CC
444166676Sjkim#define	BGE_MBX_RX_CONS10_HI		0x02D0
445166676Sjkim#define	BGE_MBX_RX_CONS10_LO		0x02D4
446166676Sjkim#define	BGE_MBX_RX_CONS11_HI		0x02D8
447166676Sjkim#define	BGE_MBX_RX_CONS11_LO		0x02DC
448166676Sjkim#define	BGE_MBX_RX_CONS12_HI		0x02E0
449166676Sjkim#define	BGE_MBX_RX_CONS12_LO		0x02E4
450166676Sjkim#define	BGE_MBX_RX_CONS13_HI		0x02E8
451166676Sjkim#define	BGE_MBX_RX_CONS13_LO		0x02EC
452166676Sjkim#define	BGE_MBX_RX_CONS14_HI		0x02F0
453166676Sjkim#define	BGE_MBX_RX_CONS14_LO		0x02F4
454166676Sjkim#define	BGE_MBX_RX_CONS15_HI		0x02F8
455166676Sjkim#define	BGE_MBX_RX_CONS15_LO		0x02FC
456166676Sjkim#define	BGE_MBX_TX_HOST_PROD0_HI	0x0300
457166676Sjkim#define	BGE_MBX_TX_HOST_PROD0_LO	0x0304
458166676Sjkim#define	BGE_MBX_TX_HOST_PROD1_HI	0x0308
459166676Sjkim#define	BGE_MBX_TX_HOST_PROD1_LO	0x030C
460166676Sjkim#define	BGE_MBX_TX_HOST_PROD2_HI	0x0310
461166676Sjkim#define	BGE_MBX_TX_HOST_PROD2_LO	0x0314
462166676Sjkim#define	BGE_MBX_TX_HOST_PROD3_HI	0x0318
463166676Sjkim#define	BGE_MBX_TX_HOST_PROD3_LO	0x031C
464166676Sjkim#define	BGE_MBX_TX_HOST_PROD4_HI	0x0320
465166676Sjkim#define	BGE_MBX_TX_HOST_PROD4_LO	0x0324
466166676Sjkim#define	BGE_MBX_TX_HOST_PROD5_HI	0x0328
467166676Sjkim#define	BGE_MBX_TX_HOST_PROD5_LO	0x032C
468166676Sjkim#define	BGE_MBX_TX_HOST_PROD6_HI	0x0330
469166676Sjkim#define	BGE_MBX_TX_HOST_PROD6_LO	0x0334
470166676Sjkim#define	BGE_MBX_TX_HOST_PROD7_HI	0x0338
471166676Sjkim#define	BGE_MBX_TX_HOST_PROD7_LO	0x033C
472166676Sjkim#define	BGE_MBX_TX_HOST_PROD8_HI	0x0340
473166676Sjkim#define	BGE_MBX_TX_HOST_PROD8_LO	0x0344
474166676Sjkim#define	BGE_MBX_TX_HOST_PROD9_HI	0x0348
475166676Sjkim#define	BGE_MBX_TX_HOST_PROD9_LO	0x034C
476166676Sjkim#define	BGE_MBX_TX_HOST_PROD10_HI	0x0350
477166676Sjkim#define	BGE_MBX_TX_HOST_PROD10_LO	0x0354
478166676Sjkim#define	BGE_MBX_TX_HOST_PROD11_HI	0x0358
479166676Sjkim#define	BGE_MBX_TX_HOST_PROD11_LO	0x035C
480166676Sjkim#define	BGE_MBX_TX_HOST_PROD12_HI	0x0360
481166676Sjkim#define	BGE_MBX_TX_HOST_PROD12_LO	0x0364
482166676Sjkim#define	BGE_MBX_TX_HOST_PROD13_HI	0x0368
483166676Sjkim#define	BGE_MBX_TX_HOST_PROD13_LO	0x036C
484166676Sjkim#define	BGE_MBX_TX_HOST_PROD14_HI	0x0370
485166676Sjkim#define	BGE_MBX_TX_HOST_PROD14_LO	0x0374
486166676Sjkim#define	BGE_MBX_TX_HOST_PROD15_HI	0x0378
487166676Sjkim#define	BGE_MBX_TX_HOST_PROD15_LO	0x037C
488166676Sjkim#define	BGE_MBX_TX_NIC_PROD0_HI		0x0380
489166676Sjkim#define	BGE_MBX_TX_NIC_PROD0_LO		0x0384
490166676Sjkim#define	BGE_MBX_TX_NIC_PROD1_HI		0x0388
491166676Sjkim#define	BGE_MBX_TX_NIC_PROD1_LO		0x038C
492166676Sjkim#define	BGE_MBX_TX_NIC_PROD2_HI		0x0390
493166676Sjkim#define	BGE_MBX_TX_NIC_PROD2_LO		0x0394
494166676Sjkim#define	BGE_MBX_TX_NIC_PROD3_HI		0x0398
495166676Sjkim#define	BGE_MBX_TX_NIC_PROD3_LO		0x039C
496166676Sjkim#define	BGE_MBX_TX_NIC_PROD4_HI		0x03A0
497166676Sjkim#define	BGE_MBX_TX_NIC_PROD4_LO		0x03A4
498166676Sjkim#define	BGE_MBX_TX_NIC_PROD5_HI		0x03A8
499166676Sjkim#define	BGE_MBX_TX_NIC_PROD5_LO		0x03AC
500166676Sjkim#define	BGE_MBX_TX_NIC_PROD6_HI		0x03B0
501166676Sjkim#define	BGE_MBX_TX_NIC_PROD6_LO		0x03B4
502166676Sjkim#define	BGE_MBX_TX_NIC_PROD7_HI		0x03B8
503166676Sjkim#define	BGE_MBX_TX_NIC_PROD7_LO		0x03BC
504166676Sjkim#define	BGE_MBX_TX_NIC_PROD8_HI		0x03C0
505166676Sjkim#define	BGE_MBX_TX_NIC_PROD8_LO		0x03C4
506166676Sjkim#define	BGE_MBX_TX_NIC_PROD9_HI		0x03C8
507166676Sjkim#define	BGE_MBX_TX_NIC_PROD9_LO		0x03CC
508166676Sjkim#define	BGE_MBX_TX_NIC_PROD10_HI	0x03D0
509166676Sjkim#define	BGE_MBX_TX_NIC_PROD10_LO	0x03D4
510166676Sjkim#define	BGE_MBX_TX_NIC_PROD11_HI	0x03D8
511166676Sjkim#define	BGE_MBX_TX_NIC_PROD11_LO	0x03DC
512166676Sjkim#define	BGE_MBX_TX_NIC_PROD12_HI	0x03E0
513166676Sjkim#define	BGE_MBX_TX_NIC_PROD12_LO	0x03E4
514166676Sjkim#define	BGE_MBX_TX_NIC_PROD13_HI	0x03E8
515166676Sjkim#define	BGE_MBX_TX_NIC_PROD13_LO	0x03EC
516166676Sjkim#define	BGE_MBX_TX_NIC_PROD14_HI	0x03F0
517166676Sjkim#define	BGE_MBX_TX_NIC_PROD14_LO	0x03F4
518166676Sjkim#define	BGE_MBX_TX_NIC_PROD15_HI	0x03F8
519166676Sjkim#define	BGE_MBX_TX_NIC_PROD15_LO	0x03FC
52084059Swpaul
521166676Sjkim#define	BGE_TX_RINGS_MAX		4
522166676Sjkim#define	BGE_TX_RINGS_EXTSSRAM_MAX	16
523166676Sjkim#define	BGE_RX_RINGS_MAX		16
52484059Swpaul
52584059Swpaul/* Ethernet MAC control registers */
526166676Sjkim#define	BGE_MAC_MODE			0x0400
527166676Sjkim#define	BGE_MAC_STS			0x0404
528166676Sjkim#define	BGE_MAC_EVT_ENB			0x0408
529166676Sjkim#define	BGE_MAC_LED_CTL			0x040C
530166676Sjkim#define	BGE_MAC_ADDR1_LO		0x0410
531166676Sjkim#define	BGE_MAC_ADDR1_HI		0x0414
532166676Sjkim#define	BGE_MAC_ADDR2_LO		0x0418
533166676Sjkim#define	BGE_MAC_ADDR2_HI		0x041C
534166676Sjkim#define	BGE_MAC_ADDR3_LO		0x0420
535166676Sjkim#define	BGE_MAC_ADDR3_HI		0x0424
536166676Sjkim#define	BGE_MAC_ADDR4_LO		0x0428
537166676Sjkim#define	BGE_MAC_ADDR4_HI		0x042C
538166676Sjkim#define	BGE_WOL_PATPTR			0x0430
539166676Sjkim#define	BGE_WOL_PATCFG			0x0434
540166676Sjkim#define	BGE_TX_RANDOM_BACKOFF		0x0438
541166676Sjkim#define	BGE_RX_MTU			0x043C
542166676Sjkim#define	BGE_GBIT_PCS_TEST		0x0440
543166676Sjkim#define	BGE_TX_TBI_AUTONEG		0x0444
544166676Sjkim#define	BGE_RX_TBI_AUTONEG		0x0448
545166676Sjkim#define	BGE_MI_COMM			0x044C
546166676Sjkim#define	BGE_MI_STS			0x0450
547166676Sjkim#define	BGE_MI_MODE			0x0454
548166676Sjkim#define	BGE_AUTOPOLL_STS		0x0458
549166676Sjkim#define	BGE_TX_MODE			0x045C
550166676Sjkim#define	BGE_TX_STS			0x0460
551166676Sjkim#define	BGE_TX_LENGTHS			0x0464
552166676Sjkim#define	BGE_RX_MODE			0x0468
553166676Sjkim#define	BGE_RX_STS			0x046C
554166676Sjkim#define	BGE_MAR0			0x0470
555166676Sjkim#define	BGE_MAR1			0x0474
556166676Sjkim#define	BGE_MAR2			0x0478
557166676Sjkim#define	BGE_MAR3			0x047C
558166676Sjkim#define	BGE_RX_BD_RULES_CTL0		0x0480
559166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL0	0x0484
560166676Sjkim#define	BGE_RX_BD_RULES_CTL1		0x0488
561166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL1	0x048C
562166676Sjkim#define	BGE_RX_BD_RULES_CTL2		0x0490
563166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL2	0x0494
564166676Sjkim#define	BGE_RX_BD_RULES_CTL3		0x0498
565166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL3	0x049C
566166676Sjkim#define	BGE_RX_BD_RULES_CTL4		0x04A0
567166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL4	0x04A4
568166676Sjkim#define	BGE_RX_BD_RULES_CTL5		0x04A8
569166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL5	0x04AC
570166676Sjkim#define	BGE_RX_BD_RULES_CTL6		0x04B0
571166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL6	0x04B4
572166676Sjkim#define	BGE_RX_BD_RULES_CTL7		0x04B8
573166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL7	0x04BC
574166676Sjkim#define	BGE_RX_BD_RULES_CTL8		0x04C0
575166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL8	0x04C4
576166676Sjkim#define	BGE_RX_BD_RULES_CTL9		0x04C8
577166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL9	0x04CC
578166676Sjkim#define	BGE_RX_BD_RULES_CTL10		0x04D0
579166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL10	0x04D4
580166676Sjkim#define	BGE_RX_BD_RULES_CTL11		0x04D8
581166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL11	0x04DC
582166676Sjkim#define	BGE_RX_BD_RULES_CTL12		0x04E0
583166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL12	0x04E4
584166676Sjkim#define	BGE_RX_BD_RULES_CTL13		0x04E8
585166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL13	0x04EC
586166676Sjkim#define	BGE_RX_BD_RULES_CTL14		0x04F0
587166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL14	0x04F4
588166676Sjkim#define	BGE_RX_BD_RULES_CTL15		0x04F8
589166676Sjkim#define	BGE_RX_BD_RULES_MASKVAL15	0x04FC
590166676Sjkim#define	BGE_RX_RULES_CFG		0x0500
591166676Sjkim#define	BGE_SERDES_CFG			0x0590
592166676Sjkim#define	BGE_SERDES_STS			0x0594
593166676Sjkim#define	BGE_SGDIG_CFG			0x05B0
594166676Sjkim#define	BGE_SGDIG_STS			0x05B4
595166676Sjkim#define	BGE_MAC_STATS			0x0800
59684059Swpaul
59784059Swpaul/* Ethernet MAC Mode register */
598166676Sjkim#define	BGE_MACMODE_RESET		0x00000001
599166676Sjkim#define	BGE_MACMODE_HALF_DUPLEX		0x00000002
600166676Sjkim#define	BGE_MACMODE_PORTMODE		0x0000000C
601166676Sjkim#define	BGE_MACMODE_LOOPBACK		0x00000010
602166676Sjkim#define	BGE_MACMODE_RX_TAGGEDPKT	0x00000080
603166676Sjkim#define	BGE_MACMODE_TX_BURST_ENB	0x00000100
604166676Sjkim#define	BGE_MACMODE_MAX_DEFER		0x00000200
605166676Sjkim#define	BGE_MACMODE_LINK_POLARITY	0x00000400
606166676Sjkim#define	BGE_MACMODE_RX_STATS_ENB	0x00000800
607166676Sjkim#define	BGE_MACMODE_RX_STATS_CLEAR	0x00001000
608166676Sjkim#define	BGE_MACMODE_RX_STATS_FLUSH	0x00002000
609166676Sjkim#define	BGE_MACMODE_TX_STATS_ENB	0x00004000
610166676Sjkim#define	BGE_MACMODE_TX_STATS_CLEAR	0x00008000
611166676Sjkim#define	BGE_MACMODE_TX_STATS_FLUSH	0x00010000
612166676Sjkim#define	BGE_MACMODE_TBI_SEND_CFGS	0x00020000
613166676Sjkim#define	BGE_MACMODE_MAGIC_PKT_ENB	0x00040000
614166676Sjkim#define	BGE_MACMODE_ACPI_PWRON_ENB	0x00080000
615166676Sjkim#define	BGE_MACMODE_MIP_ENB		0x00100000
616166676Sjkim#define	BGE_MACMODE_TXDMA_ENB		0x00200000
617166676Sjkim#define	BGE_MACMODE_RXDMA_ENB		0x00400000
618166676Sjkim#define	BGE_MACMODE_FRMHDR_DMA_ENB	0x00800000
61984059Swpaul
620166676Sjkim#define	BGE_PORTMODE_NONE		0x00000000
621166676Sjkim#define	BGE_PORTMODE_MII		0x00000004
622166676Sjkim#define	BGE_PORTMODE_GMII		0x00000008
623166676Sjkim#define	BGE_PORTMODE_TBI		0x0000000C
62484059Swpaul
62584059Swpaul/* MAC Status register */
626166676Sjkim#define	BGE_MACSTAT_TBI_PCS_SYNCHED	0x00000001
627166676Sjkim#define	BGE_MACSTAT_TBI_SIGNAL_DETECT	0x00000002
628166676Sjkim#define	BGE_MACSTAT_RX_CFG		0x00000004
629166676Sjkim#define	BGE_MACSTAT_CFG_CHANGED		0x00000008
630166676Sjkim#define	BGE_MACSTAT_SYNC_CHANGED	0x00000010
631166676Sjkim#define	BGE_MACSTAT_PORT_DECODE_ERROR	0x00000400
632166676Sjkim#define	BGE_MACSTAT_LINK_CHANGED	0x00001000
633166676Sjkim#define	BGE_MACSTAT_MI_COMPLETE		0x00400000
634166676Sjkim#define	BGE_MACSTAT_MI_INTERRUPT	0x00800000
635166676Sjkim#define	BGE_MACSTAT_AUTOPOLL_ERROR	0x01000000
636166676Sjkim#define	BGE_MACSTAT_ODI_ERROR		0x02000000
637166676Sjkim#define	BGE_MACSTAT_RXSTAT_OFLOW	0x04000000
638166676Sjkim#define	BGE_MACSTAT_TXSTAT_OFLOW	0x08000000
63984059Swpaul
64084059Swpaul/* MAC Event Enable Register */
641166676Sjkim#define	BGE_EVTENB_PORT_DECODE_ERROR	0x00000400
642166676Sjkim#define	BGE_EVTENB_LINK_CHANGED		0x00001000
643166676Sjkim#define	BGE_EVTENB_MI_COMPLETE		0x00400000
644166676Sjkim#define	BGE_EVTENB_MI_INTERRUPT		0x00800000
645166676Sjkim#define	BGE_EVTENB_AUTOPOLL_ERROR	0x01000000
646166676Sjkim#define	BGE_EVTENB_ODI_ERROR		0x02000000
647166676Sjkim#define	BGE_EVTENB_RXSTAT_OFLOW		0x04000000
648166676Sjkim#define	BGE_EVTENB_TXSTAT_OFLOW		0x08000000
64984059Swpaul
65084059Swpaul/* LED Control Register */
651166676Sjkim#define	BGE_LEDCTL_LINKLED_OVERRIDE	0x00000001
652166676Sjkim#define	BGE_LEDCTL_1000MBPS_LED		0x00000002
653166676Sjkim#define	BGE_LEDCTL_100MBPS_LED		0x00000004
654166676Sjkim#define	BGE_LEDCTL_10MBPS_LED		0x00000008
655166676Sjkim#define	BGE_LEDCTL_TRAFLED_OVERRIDE	0x00000010
656166676Sjkim#define	BGE_LEDCTL_TRAFLED_BLINK	0x00000020
657166676Sjkim#define	BGE_LEDCTL_TREFLED_BLINK_2	0x00000040
658166676Sjkim#define	BGE_LEDCTL_1000MBPS_STS		0x00000080
659166676Sjkim#define	BGE_LEDCTL_100MBPS_STS		0x00000100
660166676Sjkim#define	BGE_LEDCTL_10MBPS_STS		0x00000200
661166676Sjkim#define	BGE_LEDCTL_TRADLED_STS		0x00000400
662166676Sjkim#define	BGE_LEDCTL_BLINKPERIOD		0x7FF80000
663166676Sjkim#define	BGE_LEDCTL_BLINKPERIOD_OVERRIDE	0x80000000
66484059Swpaul
66584059Swpaul/* TX backoff seed register */
666166676Sjkim#define	BGE_TX_BACKOFF_SEED_MASK	0x3F
66784059Swpaul
66884059Swpaul/* Autopoll status register */
669166676Sjkim#define	BGE_AUTOPOLLSTS_ERROR		0x00000001
67084059Swpaul
67184059Swpaul/* Transmit MAC mode register */
672166676Sjkim#define	BGE_TXMODE_RESET		0x00000001
673166676Sjkim#define	BGE_TXMODE_ENABLE		0x00000002
674166676Sjkim#define	BGE_TXMODE_FLOWCTL_ENABLE	0x00000010
675166676Sjkim#define	BGE_TXMODE_BIGBACKOFF_ENABLE	0x00000020
676166676Sjkim#define	BGE_TXMODE_LONGPAUSE_ENABLE	0x00000040
67784059Swpaul
67884059Swpaul/* Transmit MAC status register */
679166676Sjkim#define	BGE_TXSTAT_RX_XOFFED		0x00000001
680166676Sjkim#define	BGE_TXSTAT_SENT_XOFF		0x00000002
681166676Sjkim#define	BGE_TXSTAT_SENT_XON		0x00000004
682166676Sjkim#define	BGE_TXSTAT_LINK_UP		0x00000008
683166676Sjkim#define	BGE_TXSTAT_ODI_UFLOW		0x00000010
684166676Sjkim#define	BGE_TXSTAT_ODI_OFLOW		0x00000020
68584059Swpaul
68684059Swpaul/* Transmit MAC lengths register */
687166676Sjkim#define	BGE_TXLEN_SLOTTIME		0x000000FF
688166676Sjkim#define	BGE_TXLEN_IPG			0x00000F00
689166676Sjkim#define	BGE_TXLEN_CRS			0x00003000
69084059Swpaul
69184059Swpaul/* Receive MAC mode register */
692166676Sjkim#define	BGE_RXMODE_RESET		0x00000001
693166676Sjkim#define	BGE_RXMODE_ENABLE		0x00000002
694166676Sjkim#define	BGE_RXMODE_FLOWCTL_ENABLE	0x00000004
695166676Sjkim#define	BGE_RXMODE_RX_GIANTS		0x00000020
696166676Sjkim#define	BGE_RXMODE_RX_RUNTS		0x00000040
697166676Sjkim#define	BGE_RXMODE_8022_LENCHECK	0x00000080
698166676Sjkim#define	BGE_RXMODE_RX_PROMISC		0x00000100
699166676Sjkim#define	BGE_RXMODE_RX_NO_CRC_CHECK	0x00000200
700166676Sjkim#define	BGE_RXMODE_RX_KEEP_VLAN_DIAG	0x00000400
70184059Swpaul
70284059Swpaul/* Receive MAC status register */
703166676Sjkim#define	BGE_RXSTAT_REMOTE_XOFFED	0x00000001
704166676Sjkim#define	BGE_RXSTAT_RCVD_XOFF		0x00000002
705166676Sjkim#define	BGE_RXSTAT_RCVD_XON		0x00000004
70684059Swpaul
70784059Swpaul/* Receive Rules Control register */
708166676Sjkim#define	BGE_RXRULECTL_OFFSET		0x000000FF
709166676Sjkim#define	BGE_RXRULECTL_CLASS		0x00001F00
710166676Sjkim#define	BGE_RXRULECTL_HDRTYPE		0x0000E000
711166676Sjkim#define	BGE_RXRULECTL_COMPARE_OP	0x00030000
712166676Sjkim#define	BGE_RXRULECTL_MAP		0x01000000
713166676Sjkim#define	BGE_RXRULECTL_DISCARD		0x02000000
714166676Sjkim#define	BGE_RXRULECTL_MASK		0x04000000
715166676Sjkim#define	BGE_RXRULECTL_ACTIVATE_PROC3	0x08000000
716166676Sjkim#define	BGE_RXRULECTL_ACTIVATE_PROC2	0x10000000
717166676Sjkim#define	BGE_RXRULECTL_ACTIVATE_PROC1	0x20000000
718166676Sjkim#define	BGE_RXRULECTL_ANDWITHNEXT	0x40000000
71984059Swpaul
72084059Swpaul/* Receive Rules Mask register */
721166676Sjkim#define	BGE_RXRULEMASK_VALUE		0x0000FFFF
722166676Sjkim#define	BGE_RXRULEMASK_MASKVAL		0xFFFF0000
72384059Swpaul
724130273Swpaul/* SERDES configuration register */
725166676Sjkim#define	BGE_SERDESCFG_RXR		0x00000007 /* phase interpolator */
726166676Sjkim#define	BGE_SERDESCFG_RXG		0x00000018 /* rx gain setting */
727166676Sjkim#define	BGE_SERDESCFG_RXEDGESEL		0x00000040 /* rising/falling egde */
728166676Sjkim#define	BGE_SERDESCFG_TX_BIAS		0x00000380 /* TXDAC bias setting */
729166676Sjkim#define	BGE_SERDESCFG_IBMAX		0x00000400 /* bias current +25% */
730166676Sjkim#define	BGE_SERDESCFG_IBMIN		0x00000800 /* bias current -25% */
731166676Sjkim#define	BGE_SERDESCFG_TXMODE		0x00001000
732166676Sjkim#define	BGE_SERDESCFG_TXEDGESEL		0x00002000 /* rising/falling edge */
733166676Sjkim#define	BGE_SERDESCFG_MODE		0x00004000 /* TXCP/TXCN disabled */
734166676Sjkim#define	BGE_SERDESCFG_PLLTEST		0x00008000 /* PLL test mode */
735166676Sjkim#define	BGE_SERDESCFG_CDET		0x00010000 /* comma detect enable */
736166676Sjkim#define	BGE_SERDESCFG_TBILOOP		0x00020000 /* local loopback */
737166676Sjkim#define	BGE_SERDESCFG_REMLOOP		0x00040000 /* remote loopback */
738166676Sjkim#define	BGE_SERDESCFG_INVPHASE		0x00080000 /* Reverse 125Mhz clock */
739166676Sjkim#define	BGE_SERDESCFG_12REGCTL		0x00300000 /* 1.2v regulator ctl */
740166676Sjkim#define	BGE_SERDESCFG_REGCTL		0x00C00000 /* regulator ctl (2.5v) */
741130273Swpaul
742130273Swpaul/* SERDES status register */
743166676Sjkim#define	BGE_SERDESSTS_RXSTAT		0x0000000F /* receive status bits */
744166676Sjkim#define	BGE_SERDESSTS_CDET		0x00000010 /* comma code detected */
745130273Swpaul
746130273Swpaul/* SGDIG config (not documented) */
747166676Sjkim#define	BGE_SGDIGCFG_PAUSE_CAP		0x00000800
748166676Sjkim#define	BGE_SGDIGCFG_ASYM_PAUSE		0x00001000
749166676Sjkim#define	BGE_SGDIGCFG_SEND		0x40000000
750166676Sjkim#define	BGE_SGDIGCFG_AUTO		0x80000000
751130273Swpaul
752130273Swpaul/* SGDIG status (not documented) */
753166676Sjkim#define	BGE_SGDIGSTS_PAUSE_CAP		0x00080000
754166676Sjkim#define	BGE_SGDIGSTS_ASYM_PAUSE		0x00100000
755166676Sjkim#define	BGE_SGDIGSTS_DONE		0x00000002
756130273Swpaul
757130273Swpaul
75884059Swpaul/* MI communication register */
759166676Sjkim#define	BGE_MICOMM_DATA			0x0000FFFF
760166676Sjkim#define	BGE_MICOMM_REG			0x001F0000
761166676Sjkim#define	BGE_MICOMM_PHY			0x03E00000
762166676Sjkim#define	BGE_MICOMM_CMD			0x0C000000
763166676Sjkim#define	BGE_MICOMM_READFAIL		0x10000000
764166676Sjkim#define	BGE_MICOMM_BUSY			0x20000000
76584059Swpaul
766166676Sjkim#define	BGE_MIREG(x)	((x & 0x1F) << 16)
767166676Sjkim#define	BGE_MIPHY(x)	((x & 0x1F) << 21)
768166676Sjkim#define	BGE_MICMD_WRITE			0x04000000
769166676Sjkim#define	BGE_MICMD_READ			0x08000000
77084059Swpaul
77184059Swpaul/* MI status register */
772166676Sjkim#define	BGE_MISTS_LINK			0x00000001
773166676Sjkim#define	BGE_MISTS_10MBPS		0x00000002
77484059Swpaul
775166676Sjkim#define	BGE_MIMODE_SHORTPREAMBLE	0x00000002
776166676Sjkim#define	BGE_MIMODE_AUTOPOLL		0x00000010
777166676Sjkim#define	BGE_MIMODE_CLKCNT		0x001F0000
77884059Swpaul
77984059Swpaul
78084059Swpaul/*
78184059Swpaul * Send data initiator control registers.
78284059Swpaul */
783166676Sjkim#define	BGE_SDI_MODE			0x0C00
784166676Sjkim#define	BGE_SDI_STATUS			0x0C04
785166676Sjkim#define	BGE_SDI_STATS_CTL		0x0C08
786166676Sjkim#define	BGE_SDI_STATS_ENABLE_MASK	0x0C0C
787166676Sjkim#define	BGE_SDI_STATS_INCREMENT_MASK	0x0C10
788166676Sjkim#define	BGE_LOCSTATS_COS0		0x0C80
789166676Sjkim#define	BGE_LOCSTATS_COS1		0x0C84
790166676Sjkim#define	BGE_LOCSTATS_COS2		0x0C88
791166676Sjkim#define	BGE_LOCSTATS_COS3		0x0C8C
792166676Sjkim#define	BGE_LOCSTATS_COS4		0x0C90
793166676Sjkim#define	BGE_LOCSTATS_COS5		0x0C84
794166676Sjkim#define	BGE_LOCSTATS_COS6		0x0C98
795166676Sjkim#define	BGE_LOCSTATS_COS7		0x0C9C
796166676Sjkim#define	BGE_LOCSTATS_COS8		0x0CA0
797166676Sjkim#define	BGE_LOCSTATS_COS9		0x0CA4
798166676Sjkim#define	BGE_LOCSTATS_COS10		0x0CA8
799166676Sjkim#define	BGE_LOCSTATS_COS11		0x0CAC
800166676Sjkim#define	BGE_LOCSTATS_COS12		0x0CB0
801166676Sjkim#define	BGE_LOCSTATS_COS13		0x0CB4
802166676Sjkim#define	BGE_LOCSTATS_COS14		0x0CB8
803166676Sjkim#define	BGE_LOCSTATS_COS15		0x0CBC
804166676Sjkim#define	BGE_LOCSTATS_DMA_RQ_FULL	0x0CC0
805166676Sjkim#define	BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL	0x0CC4
806166676Sjkim#define	BGE_LOCSTATS_SDC_QUEUE_FULL	0x0CC8
807166676Sjkim#define	BGE_LOCSTATS_NIC_SENDPROD_SET	0x0CCC
808166676Sjkim#define	BGE_LOCSTATS_STATS_UPDATED	0x0CD0
809166676Sjkim#define	BGE_LOCSTATS_IRQS		0x0CD4
810166676Sjkim#define	BGE_LOCSTATS_AVOIDED_IRQS	0x0CD8
811166676Sjkim#define	BGE_LOCSTATS_TX_THRESH_HIT	0x0CDC
81284059Swpaul
81384059Swpaul/* Send Data Initiator mode register */
814166676Sjkim#define	BGE_SDIMODE_RESET		0x00000001
815166676Sjkim#define	BGE_SDIMODE_ENABLE		0x00000002
816166676Sjkim#define	BGE_SDIMODE_STATS_OFLOW_ATTN	0x00000004
81784059Swpaul
81884059Swpaul/* Send Data Initiator stats register */
819166676Sjkim#define	BGE_SDISTAT_STATS_OFLOW_ATTN	0x00000004
82084059Swpaul
82184059Swpaul/* Send Data Initiator stats control register */
822166676Sjkim#define	BGE_SDISTATSCTL_ENABLE		0x00000001
823166676Sjkim#define	BGE_SDISTATSCTL_FASTER		0x00000002
824166676Sjkim#define	BGE_SDISTATSCTL_CLEAR		0x00000004
825166676Sjkim#define	BGE_SDISTATSCTL_FORCEFLUSH	0x00000008
826166676Sjkim#define	BGE_SDISTATSCTL_FORCEZERO	0x00000010
82784059Swpaul
82884059Swpaul/*
82984059Swpaul * Send Data Completion Control registers
83084059Swpaul */
831166676Sjkim#define	BGE_SDC_MODE			0x1000
832166676Sjkim#define	BGE_SDC_STATUS			0x1004
83384059Swpaul
83484059Swpaul/* Send Data completion mode register */
835166676Sjkim#define	BGE_SDCMODE_RESET		0x00000001
836166676Sjkim#define	BGE_SDCMODE_ENABLE		0x00000002
837166676Sjkim#define	BGE_SDCMODE_ATTN		0x00000004
83884059Swpaul
83984059Swpaul/* Send Data completion status register */
840166676Sjkim#define	BGE_SDCSTAT_ATTN		0x00000004
84184059Swpaul
84284059Swpaul/*
84384059Swpaul * Send BD Ring Selector Control registers
84484059Swpaul */
845166676Sjkim#define	BGE_SRS_MODE			0x1400
846166676Sjkim#define	BGE_SRS_STATUS			0x1404
847166676Sjkim#define	BGE_SRS_HWDIAG			0x1408
848166676Sjkim#define	BGE_SRS_LOC_NIC_CONS0		0x1440
849166676Sjkim#define	BGE_SRS_LOC_NIC_CONS1		0x1444
850166676Sjkim#define	BGE_SRS_LOC_NIC_CONS2		0x1448
851166676Sjkim#define	BGE_SRS_LOC_NIC_CONS3		0x144C
852166676Sjkim#define	BGE_SRS_LOC_NIC_CONS4		0x1450
853166676Sjkim#define	BGE_SRS_LOC_NIC_CONS5		0x1454
854166676Sjkim#define	BGE_SRS_LOC_NIC_CONS6		0x1458
855166676Sjkim#define	BGE_SRS_LOC_NIC_CONS7		0x145C
856166676Sjkim#define	BGE_SRS_LOC_NIC_CONS8		0x1460
857166676Sjkim#define	BGE_SRS_LOC_NIC_CONS9		0x1464
858166676Sjkim#define	BGE_SRS_LOC_NIC_CONS10		0x1468
859166676Sjkim#define	BGE_SRS_LOC_NIC_CONS11		0x146C
860166676Sjkim#define	BGE_SRS_LOC_NIC_CONS12		0x1470
861166676Sjkim#define	BGE_SRS_LOC_NIC_CONS13		0x1474
862166676Sjkim#define	BGE_SRS_LOC_NIC_CONS14		0x1478
863166676Sjkim#define	BGE_SRS_LOC_NIC_CONS15		0x147C
86484059Swpaul
86584059Swpaul/* Send BD Ring Selector Mode register */
866166676Sjkim#define	BGE_SRSMODE_RESET		0x00000001
867166676Sjkim#define	BGE_SRSMODE_ENABLE		0x00000002
868166676Sjkim#define	BGE_SRSMODE_ATTN		0x00000004
86984059Swpaul
87084059Swpaul/* Send BD Ring Selector Status register */
871166676Sjkim#define	BGE_SRSSTAT_ERROR		0x00000004
87284059Swpaul
87384059Swpaul/* Send BD Ring Selector HW Diagnostics register */
874166676Sjkim#define	BGE_SRSHWDIAG_STATE		0x0000000F
875166676Sjkim#define	BGE_SRSHWDIAG_CURRINGNUM	0x000000F0
876166676Sjkim#define	BGE_SRSHWDIAG_STAGEDRINGNUM	0x00000F00
877166676Sjkim#define	BGE_SRSHWDIAG_RINGNUM_IN_MBX	0x0000F000
87884059Swpaul
87984059Swpaul/*
88084059Swpaul * Send BD Initiator Selector Control registers
88184059Swpaul */
882166676Sjkim#define	BGE_SBDI_MODE			0x1800
883166676Sjkim#define	BGE_SBDI_STATUS			0x1804
884166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD0		0x1808
885166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD1		0x180C
886166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD2		0x1810
887166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD3		0x1814
888166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD4		0x1818
889166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD5		0x181C
890166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD6		0x1820
891166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD7		0x1824
892166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD8		0x1828
893166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD9		0x182C
894166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD10		0x1830
895166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD11		0x1834
896166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD12		0x1838
897166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD13		0x183C
898166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD14		0x1840
899166676Sjkim#define	BGE_SBDI_LOC_NIC_PROD15		0x1844
90084059Swpaul
90184059Swpaul/* Send BD Initiator Mode register */
902166676Sjkim#define	BGE_SBDIMODE_RESET		0x00000001
903166676Sjkim#define	BGE_SBDIMODE_ENABLE		0x00000002
904166676Sjkim#define	BGE_SBDIMODE_ATTN		0x00000004
90584059Swpaul
90684059Swpaul/* Send BD Initiator Status register */
907166676Sjkim#define	BGE_SBDISTAT_ERROR		0x00000004
90884059Swpaul
90984059Swpaul/*
91084059Swpaul * Send BD Completion Control registers
91184059Swpaul */
912166676Sjkim#define	BGE_SBDC_MODE			0x1C00
913166676Sjkim#define	BGE_SBDC_STATUS			0x1C04
91484059Swpaul
91584059Swpaul/* Send BD Completion Control Mode register */
916166676Sjkim#define	BGE_SBDCMODE_RESET		0x00000001
917166676Sjkim#define	BGE_SBDCMODE_ENABLE		0x00000002
918166676Sjkim#define	BGE_SBDCMODE_ATTN		0x00000004
91984059Swpaul
92084059Swpaul/* Send BD Completion Control Status register */
921166676Sjkim#define	BGE_SBDCSTAT_ATTN		0x00000004
92284059Swpaul
92384059Swpaul/*
92484059Swpaul * Receive List Placement Control registers
92584059Swpaul */
926166676Sjkim#define	BGE_RXLP_MODE			0x2000
927166676Sjkim#define	BGE_RXLP_STATUS			0x2004
928166676Sjkim#define	BGE_RXLP_SEL_LIST_LOCK		0x2008
929166676Sjkim#define	BGE_RXLP_SEL_NON_EMPTY_BITS	0x200C
930166676Sjkim#define	BGE_RXLP_CFG			0x2010
931166676Sjkim#define	BGE_RXLP_STATS_CTL		0x2014
932166676Sjkim#define	BGE_RXLP_STATS_ENABLE_MASK	0x2018
933166676Sjkim#define	BGE_RXLP_STATS_INCREMENT_MASK	0x201C
934166676Sjkim#define	BGE_RXLP_HEAD0			0x2100
935166676Sjkim#define	BGE_RXLP_TAIL0			0x2104
936166676Sjkim#define	BGE_RXLP_COUNT0			0x2108
937166676Sjkim#define	BGE_RXLP_HEAD1			0x2110
938166676Sjkim#define	BGE_RXLP_TAIL1			0x2114
939166676Sjkim#define	BGE_RXLP_COUNT1			0x2118
940166676Sjkim#define	BGE_RXLP_HEAD2			0x2120
941166676Sjkim#define	BGE_RXLP_TAIL2			0x2124
942166676Sjkim#define	BGE_RXLP_COUNT2			0x2128
943166676Sjkim#define	BGE_RXLP_HEAD3			0x2130
944166676Sjkim#define	BGE_RXLP_TAIL3			0x2134
945166676Sjkim#define	BGE_RXLP_COUNT3			0x2138
946166676Sjkim#define	BGE_RXLP_HEAD4			0x2140
947166676Sjkim#define	BGE_RXLP_TAIL4			0x2144
948166676Sjkim#define	BGE_RXLP_COUNT4			0x2148
949166676Sjkim#define	BGE_RXLP_HEAD5			0x2150
950166676Sjkim#define	BGE_RXLP_TAIL5			0x2154
951166676Sjkim#define	BGE_RXLP_COUNT5			0x2158
952166676Sjkim#define	BGE_RXLP_HEAD6			0x2160
953166676Sjkim#define	BGE_RXLP_TAIL6			0x2164
954166676Sjkim#define	BGE_RXLP_COUNT6			0x2168
955166676Sjkim#define	BGE_RXLP_HEAD7			0x2170
956166676Sjkim#define	BGE_RXLP_TAIL7			0x2174
957166676Sjkim#define	BGE_RXLP_COUNT7			0x2178
958166676Sjkim#define	BGE_RXLP_HEAD8			0x2180
959166676Sjkim#define	BGE_RXLP_TAIL8			0x2184
960166676Sjkim#define	BGE_RXLP_COUNT8			0x2188
961166676Sjkim#define	BGE_RXLP_HEAD9			0x2190
962166676Sjkim#define	BGE_RXLP_TAIL9			0x2194
963166676Sjkim#define	BGE_RXLP_COUNT9			0x2198
964166676Sjkim#define	BGE_RXLP_HEAD10			0x21A0
965166676Sjkim#define	BGE_RXLP_TAIL10			0x21A4
966166676Sjkim#define	BGE_RXLP_COUNT10		0x21A8
967166676Sjkim#define	BGE_RXLP_HEAD11			0x21B0
968166676Sjkim#define	BGE_RXLP_TAIL11			0x21B4
969166676Sjkim#define	BGE_RXLP_COUNT11		0x21B8
970166676Sjkim#define	BGE_RXLP_HEAD12			0x21C0
971166676Sjkim#define	BGE_RXLP_TAIL12			0x21C4
972166676Sjkim#define	BGE_RXLP_COUNT12		0x21C8
973166676Sjkim#define	BGE_RXLP_HEAD13			0x21D0
974166676Sjkim#define	BGE_RXLP_TAIL13			0x21D4
975166676Sjkim#define	BGE_RXLP_COUNT13		0x21D8
976166676Sjkim#define	BGE_RXLP_HEAD14			0x21E0
977166676Sjkim#define	BGE_RXLP_TAIL14			0x21E4
978166676Sjkim#define	BGE_RXLP_COUNT14		0x21E8
979166676Sjkim#define	BGE_RXLP_HEAD15			0x21F0
980166676Sjkim#define	BGE_RXLP_TAIL15			0x21F4
981166676Sjkim#define	BGE_RXLP_COUNT15		0x21F8
982166676Sjkim#define	BGE_RXLP_LOCSTAT_COS0		0x2200
983166676Sjkim#define	BGE_RXLP_LOCSTAT_COS1		0x2204
984166676Sjkim#define	BGE_RXLP_LOCSTAT_COS2		0x2208
985166676Sjkim#define	BGE_RXLP_LOCSTAT_COS3		0x220C
986166676Sjkim#define	BGE_RXLP_LOCSTAT_COS4		0x2210
987166676Sjkim#define	BGE_RXLP_LOCSTAT_COS5		0x2214
988166676Sjkim#define	BGE_RXLP_LOCSTAT_COS6		0x2218
989166676Sjkim#define	BGE_RXLP_LOCSTAT_COS7		0x221C
990166676Sjkim#define	BGE_RXLP_LOCSTAT_COS8		0x2220
991166676Sjkim#define	BGE_RXLP_LOCSTAT_COS9		0x2224
992166676Sjkim#define	BGE_RXLP_LOCSTAT_COS10		0x2228
993166676Sjkim#define	BGE_RXLP_LOCSTAT_COS11		0x222C
994166676Sjkim#define	BGE_RXLP_LOCSTAT_COS12		0x2230
995166676Sjkim#define	BGE_RXLP_LOCSTAT_COS13		0x2234
996166676Sjkim#define	BGE_RXLP_LOCSTAT_COS14		0x2238
997166676Sjkim#define	BGE_RXLP_LOCSTAT_COS15		0x223C
998166676Sjkim#define	BGE_RXLP_LOCSTAT_FILTDROP	0x2240
999166676Sjkim#define	BGE_RXLP_LOCSTAT_DMA_WRQ_FULL	0x2244
1000166676Sjkim#define	BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL	0x2248
1001166676Sjkim#define	BGE_RXLP_LOCSTAT_OUT_OF_BDS	0x224C
1002166676Sjkim#define	BGE_RXLP_LOCSTAT_IFIN_DROPS	0x2250
1003166676Sjkim#define	BGE_RXLP_LOCSTAT_IFIN_ERRORS	0x2254
1004166676Sjkim#define	BGE_RXLP_LOCSTAT_RXTHRESH_HIT	0x2258
100584059Swpaul
100684059Swpaul
100784059Swpaul/* Receive List Placement mode register */
1008166676Sjkim#define	BGE_RXLPMODE_RESET		0x00000001
1009166676Sjkim#define	BGE_RXLPMODE_ENABLE		0x00000002
1010166676Sjkim#define	BGE_RXLPMODE_CLASS0_ATTN	0x00000004
1011166676Sjkim#define	BGE_RXLPMODE_MAPOUTRANGE_ATTN	0x00000008
1012166676Sjkim#define	BGE_RXLPMODE_STATSOFLOW_ATTN	0x00000010
101384059Swpaul
101484059Swpaul/* Receive List Placement Status register */
1015166676Sjkim#define	BGE_RXLPSTAT_CLASS0_ATTN	0x00000004
1016166676Sjkim#define	BGE_RXLPSTAT_MAPOUTRANGE_ATTN	0x00000008
1017166676Sjkim#define	BGE_RXLPSTAT_STATSOFLOW_ATTN	0x00000010
101884059Swpaul
101984059Swpaul/*
102084059Swpaul * Receive Data and Receive BD Initiator Control Registers
102184059Swpaul */
1022166676Sjkim#define	BGE_RDBDI_MODE			0x2400
1023166676Sjkim#define	BGE_RDBDI_STATUS		0x2404
1024166676Sjkim#define	BGE_RX_JUMBO_RCB_HADDR_HI	0x2440
1025166676Sjkim#define	BGE_RX_JUMBO_RCB_HADDR_LO	0x2444
1026166676Sjkim#define	BGE_RX_JUMBO_RCB_MAXLEN_FLAGS	0x2448
1027166676Sjkim#define	BGE_RX_JUMBO_RCB_NICADDR	0x244C
1028166676Sjkim#define	BGE_RX_STD_RCB_HADDR_HI		0x2450
1029166676Sjkim#define	BGE_RX_STD_RCB_HADDR_LO		0x2454
1030166676Sjkim#define	BGE_RX_STD_RCB_MAXLEN_FLAGS	0x2458
1031166676Sjkim#define	BGE_RX_STD_RCB_NICADDR		0x245C
1032166676Sjkim#define	BGE_RX_MINI_RCB_HADDR_HI	0x2460
1033166676Sjkim#define	BGE_RX_MINI_RCB_HADDR_LO	0x2464
1034166676Sjkim#define	BGE_RX_MINI_RCB_MAXLEN_FLAGS	0x2468
1035166676Sjkim#define	BGE_RX_MINI_RCB_NICADDR		0x246C
1036166676Sjkim#define	BGE_RDBDI_JUMBO_RX_CONS		0x2470
1037166676Sjkim#define	BGE_RDBDI_STD_RX_CONS		0x2474
1038166676Sjkim#define	BGE_RDBDI_MINI_RX_CONS		0x2478
1039166676Sjkim#define	BGE_RDBDI_RETURN_PROD0		0x2480
1040166676Sjkim#define	BGE_RDBDI_RETURN_PROD1		0x2484
1041166676Sjkim#define	BGE_RDBDI_RETURN_PROD2		0x2488
1042166676Sjkim#define	BGE_RDBDI_RETURN_PROD3		0x248C
1043166676Sjkim#define	BGE_RDBDI_RETURN_PROD4		0x2490
1044166676Sjkim#define	BGE_RDBDI_RETURN_PROD5		0x2494
1045166676Sjkim#define	BGE_RDBDI_RETURN_PROD6		0x2498
1046166676Sjkim#define	BGE_RDBDI_RETURN_PROD7		0x249C
1047166676Sjkim#define	BGE_RDBDI_RETURN_PROD8		0x24A0
1048166676Sjkim#define	BGE_RDBDI_RETURN_PROD9		0x24A4
1049166676Sjkim#define	BGE_RDBDI_RETURN_PROD10		0x24A8
1050166676Sjkim#define	BGE_RDBDI_RETURN_PROD11		0x24AC
1051166676Sjkim#define	BGE_RDBDI_RETURN_PROD12		0x24B0
1052166676Sjkim#define	BGE_RDBDI_RETURN_PROD13		0x24B4
1053166676Sjkim#define	BGE_RDBDI_RETURN_PROD14		0x24B8
1054166676Sjkim#define	BGE_RDBDI_RETURN_PROD15		0x24BC
1055166676Sjkim#define	BGE_RDBDI_HWDIAG		0x24C0
105684059Swpaul
105784059Swpaul
105884059Swpaul/* Receive Data and Receive BD Initiator Mode register */
1059166676Sjkim#define	BGE_RDBDIMODE_RESET		0x00000001
1060166676Sjkim#define	BGE_RDBDIMODE_ENABLE		0x00000002
1061166676Sjkim#define	BGE_RDBDIMODE_JUMBO_ATTN	0x00000004
1062166676Sjkim#define	BGE_RDBDIMODE_GIANT_ATTN	0x00000008
1063166676Sjkim#define	BGE_RDBDIMODE_BADRINGSZ_ATTN	0x00000010
106484059Swpaul
106584059Swpaul/* Receive Data and Receive BD Initiator Status register */
1066166676Sjkim#define	BGE_RDBDISTAT_JUMBO_ATTN	0x00000004
1067166676Sjkim#define	BGE_RDBDISTAT_GIANT_ATTN	0x00000008
1068166676Sjkim#define	BGE_RDBDISTAT_BADRINGSZ_ATTN	0x00000010
106984059Swpaul
107084059Swpaul
107184059Swpaul/*
107284059Swpaul * Receive Data Completion Control registers
107384059Swpaul */
1074166676Sjkim#define	BGE_RDC_MODE			0x2800
107584059Swpaul
107684059Swpaul/* Receive Data Completion Mode register */
1077166676Sjkim#define	BGE_RDCMODE_RESET		0x00000001
1078166676Sjkim#define	BGE_RDCMODE_ENABLE		0x00000002
1079166676Sjkim#define	BGE_RDCMODE_ATTN		0x00000004
108084059Swpaul
108184059Swpaul/*
108284059Swpaul * Receive BD Initiator Control registers
108384059Swpaul */
1084166676Sjkim#define	BGE_RBDI_MODE			0x2C00
1085166676Sjkim#define	BGE_RBDI_STATUS			0x2C04
1086166676Sjkim#define	BGE_RBDI_NIC_JUMBO_BD_PROD	0x2C08
1087166676Sjkim#define	BGE_RBDI_NIC_STD_BD_PROD	0x2C0C
1088166676Sjkim#define	BGE_RBDI_NIC_MINI_BD_PROD	0x2C10
1089166676Sjkim#define	BGE_RBDI_MINI_REPL_THRESH	0x2C14
1090166676Sjkim#define	BGE_RBDI_STD_REPL_THRESH	0x2C18
1091166676Sjkim#define	BGE_RBDI_JUMBO_REPL_THRESH	0x2C1C
109284059Swpaul
109384059Swpaul/* Receive BD Initiator Mode register */
1094166676Sjkim#define	BGE_RBDIMODE_RESET		0x00000001
1095166676Sjkim#define	BGE_RBDIMODE_ENABLE		0x00000002
1096166676Sjkim#define	BGE_RBDIMODE_ATTN		0x00000004
109784059Swpaul
109884059Swpaul/* Receive BD Initiator Status register */
1099166676Sjkim#define	BGE_RBDISTAT_ATTN		0x00000004
110084059Swpaul
110184059Swpaul/*
110284059Swpaul * Receive BD Completion Control registers
110384059Swpaul */
1104166676Sjkim#define	BGE_RBDC_MODE			0x3000
1105166676Sjkim#define	BGE_RBDC_STATUS			0x3004
1106166676Sjkim#define	BGE_RBDC_JUMBO_BD_PROD		0x3008
1107166676Sjkim#define	BGE_RBDC_STD_BD_PROD		0x300C
1108166676Sjkim#define	BGE_RBDC_MINI_BD_PROD		0x3010
110984059Swpaul
111084059Swpaul/* Receive BD completion mode register */
1111166676Sjkim#define	BGE_RBDCMODE_RESET		0x00000001
1112166676Sjkim#define	BGE_RBDCMODE_ENABLE		0x00000002
1113166676Sjkim#define	BGE_RBDCMODE_ATTN		0x00000004
111484059Swpaul
111584059Swpaul/* Receive BD completion status register */
1116166676Sjkim#define	BGE_RBDCSTAT_ERROR		0x00000004
111784059Swpaul
111884059Swpaul/*
111984059Swpaul * Receive List Selector Control registers
112084059Swpaul */
1121166676Sjkim#define	BGE_RXLS_MODE			0x3400
1122166676Sjkim#define	BGE_RXLS_STATUS			0x3404
112384059Swpaul
112484059Swpaul/* Receive List Selector Mode register */
1125166676Sjkim#define	BGE_RXLSMODE_RESET		0x00000001
1126166676Sjkim#define	BGE_RXLSMODE_ENABLE		0x00000002
1127166676Sjkim#define	BGE_RXLSMODE_ATTN		0x00000004
112884059Swpaul
112984059Swpaul/* Receive List Selector Status register */
1130166676Sjkim#define	BGE_RXLSSTAT_ERROR		0x00000004
113184059Swpaul
113284059Swpaul/*
113384059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
113484059Swpaul */
1135166676Sjkim#define	BGE_MBCF_MODE			0x3800
1136166676Sjkim#define	BGE_MBCF_STATUS			0x3804
113784059Swpaul
113884059Swpaul/* Mbuf Cluster Free mode register */
1139166676Sjkim#define	BGE_MBCFMODE_RESET		0x00000001
1140166676Sjkim#define	BGE_MBCFMODE_ENABLE		0x00000002
1141166676Sjkim#define	BGE_MBCFMODE_ATTN		0x00000004
114284059Swpaul
114384059Swpaul/* Mbuf Cluster Free status register */
1144166676Sjkim#define	BGE_MBCFSTAT_ERROR		0x00000004
114584059Swpaul
114684059Swpaul/*
114784059Swpaul * Host Coalescing Control registers
114884059Swpaul */
1149166676Sjkim#define	BGE_HCC_MODE			0x3C00
1150166676Sjkim#define	BGE_HCC_STATUS			0x3C04
1151166676Sjkim#define	BGE_HCC_RX_COAL_TICKS		0x3C08
1152166676Sjkim#define	BGE_HCC_TX_COAL_TICKS		0x3C0C
1153166676Sjkim#define	BGE_HCC_RX_MAX_COAL_BDS		0x3C10
1154166676Sjkim#define	BGE_HCC_TX_MAX_COAL_BDS		0x3C14
1155166676Sjkim#define	BGE_HCC_RX_COAL_TICKS_INT	0x3C18 /* ticks during interrupt */
1156166676Sjkim#define	BGE_HCC_TX_COAL_TICKS_INT	0x3C1C /* ticks during interrupt */
1157166676Sjkim#define	BGE_HCC_RX_MAX_COAL_BDS_INT	0x3C20 /* BDs during interrupt */
1158166676Sjkim#define	BGE_HCC_TX_MAX_COAL_BDS_INT	0x3C24 /* BDs during interrupt */
1159166676Sjkim#define	BGE_HCC_STATS_TICKS		0x3C28
1160166676Sjkim#define	BGE_HCC_STATS_ADDR_HI		0x3C30
1161166676Sjkim#define	BGE_HCC_STATS_ADDR_LO		0x3C34
1162166676Sjkim#define	BGE_HCC_STATUSBLK_ADDR_HI	0x3C38
1163166676Sjkim#define	BGE_HCC_STATUSBLK_ADDR_LO	0x3C3C
1164166676Sjkim#define	BGE_HCC_STATS_BASEADDR		0x3C40 /* address in NIC memory */
1165166676Sjkim#define	BGE_HCC_STATUSBLK_BASEADDR	0x3C44 /* address in NIC memory */
1166166676Sjkim#define	BGE_FLOW_ATTN			0x3C48
1167166676Sjkim#define	BGE_HCC_JUMBO_BD_CONS		0x3C50
1168166676Sjkim#define	BGE_HCC_STD_BD_CONS		0x3C54
1169166676Sjkim#define	BGE_HCC_MINI_BD_CONS		0x3C58
1170166676Sjkim#define	BGE_HCC_RX_RETURN_PROD0		0x3C80
1171166676Sjkim#define	BGE_HCC_RX_RETURN_PROD1		0x3C84
1172166676Sjkim#define	BGE_HCC_RX_RETURN_PROD2		0x3C88
1173166676Sjkim#define	BGE_HCC_RX_RETURN_PROD3		0x3C8C
1174166676Sjkim#define	BGE_HCC_RX_RETURN_PROD4		0x3C90
1175166676Sjkim#define	BGE_HCC_RX_RETURN_PROD5		0x3C94
1176166676Sjkim#define	BGE_HCC_RX_RETURN_PROD6		0x3C98
1177166676Sjkim#define	BGE_HCC_RX_RETURN_PROD7		0x3C9C
1178166676Sjkim#define	BGE_HCC_RX_RETURN_PROD8		0x3CA0
1179166676Sjkim#define	BGE_HCC_RX_RETURN_PROD9		0x3CA4
1180166676Sjkim#define	BGE_HCC_RX_RETURN_PROD10	0x3CA8
1181166676Sjkim#define	BGE_HCC_RX_RETURN_PROD11	0x3CAC
1182166676Sjkim#define	BGE_HCC_RX_RETURN_PROD12	0x3CB0
1183166676Sjkim#define	BGE_HCC_RX_RETURN_PROD13	0x3CB4
1184166676Sjkim#define	BGE_HCC_RX_RETURN_PROD14	0x3CB8
1185166676Sjkim#define	BGE_HCC_RX_RETURN_PROD15	0x3CBC
1186166676Sjkim#define	BGE_HCC_TX_BD_CONS0		0x3CC0
1187166676Sjkim#define	BGE_HCC_TX_BD_CONS1		0x3CC4
1188166676Sjkim#define	BGE_HCC_TX_BD_CONS2		0x3CC8
1189166676Sjkim#define	BGE_HCC_TX_BD_CONS3		0x3CCC
1190166676Sjkim#define	BGE_HCC_TX_BD_CONS4		0x3CD0
1191166676Sjkim#define	BGE_HCC_TX_BD_CONS5		0x3CD4
1192166676Sjkim#define	BGE_HCC_TX_BD_CONS6		0x3CD8
1193166676Sjkim#define	BGE_HCC_TX_BD_CONS7		0x3CDC
1194166676Sjkim#define	BGE_HCC_TX_BD_CONS8		0x3CE0
1195166676Sjkim#define	BGE_HCC_TX_BD_CONS9		0x3CE4
1196166676Sjkim#define	BGE_HCC_TX_BD_CONS10		0x3CE8
1197166676Sjkim#define	BGE_HCC_TX_BD_CONS11		0x3CEC
1198166676Sjkim#define	BGE_HCC_TX_BD_CONS12		0x3CF0
1199166676Sjkim#define	BGE_HCC_TX_BD_CONS13		0x3CF4
1200166676Sjkim#define	BGE_HCC_TX_BD_CONS14		0x3CF8
1201166676Sjkim#define	BGE_HCC_TX_BD_CONS15		0x3CFC
120284059Swpaul
120384059Swpaul
120484059Swpaul/* Host coalescing mode register */
1205166676Sjkim#define	BGE_HCCMODE_RESET		0x00000001
1206166676Sjkim#define	BGE_HCCMODE_ENABLE		0x00000002
1207166676Sjkim#define	BGE_HCCMODE_ATTN		0x00000004
1208166676Sjkim#define	BGE_HCCMODE_COAL_NOW		0x00000008
1209166676Sjkim#define	BGE_HCCMODE_MSI_BITS		0x00000070
1210166676Sjkim#define	BGE_HCCMODE_STATBLK_SIZE	0x00000180
121184059Swpaul
1212166676Sjkim#define	BGE_STATBLKSZ_FULL		0x00000000
1213166676Sjkim#define	BGE_STATBLKSZ_64BYTE		0x00000080
1214166676Sjkim#define	BGE_STATBLKSZ_32BYTE		0x00000100
121584059Swpaul
121684059Swpaul/* Host coalescing status register */
1217166676Sjkim#define	BGE_HCCSTAT_ERROR		0x00000004
121884059Swpaul
121984059Swpaul/* Flow attention register */
1220166676Sjkim#define	BGE_FLOWATTN_MB_LOWAT		0x00000040
1221166676Sjkim#define	BGE_FLOWATTN_MEMARB		0x00000080
1222166676Sjkim#define	BGE_FLOWATTN_HOSTCOAL		0x00008000
1223166676Sjkim#define	BGE_FLOWATTN_DMADONE_DISCARD	0x00010000
1224166676Sjkim#define	BGE_FLOWATTN_RCB_INVAL		0x00020000
1225166676Sjkim#define	BGE_FLOWATTN_RXDATA_CORRUPT	0x00040000
1226166676Sjkim#define	BGE_FLOWATTN_RDBDI		0x00080000
1227166676Sjkim#define	BGE_FLOWATTN_RXLS		0x00100000
1228166676Sjkim#define	BGE_FLOWATTN_RXLP		0x00200000
1229166676Sjkim#define	BGE_FLOWATTN_RBDC		0x00400000
1230166676Sjkim#define	BGE_FLOWATTN_RBDI		0x00800000
1231166676Sjkim#define	BGE_FLOWATTN_SDC		0x08000000
1232166676Sjkim#define	BGE_FLOWATTN_SDI		0x10000000
1233166676Sjkim#define	BGE_FLOWATTN_SRS		0x20000000
1234166676Sjkim#define	BGE_FLOWATTN_SBDC		0x40000000
1235166676Sjkim#define	BGE_FLOWATTN_SBDI		0x80000000
123684059Swpaul
123784059Swpaul/*
123884059Swpaul * Memory arbiter registers
123984059Swpaul */
1240166676Sjkim#define	BGE_MARB_MODE			0x4000
1241166676Sjkim#define	BGE_MARB_STATUS			0x4004
1242166676Sjkim#define	BGE_MARB_TRAPADDR_HI		0x4008
1243166676Sjkim#define	BGE_MARB_TRAPADDR_LO		0x400C
124484059Swpaul
124584059Swpaul/* Memory arbiter mode register */
1246166676Sjkim#define	BGE_MARBMODE_RESET		0x00000001
1247166676Sjkim#define	BGE_MARBMODE_ENABLE		0x00000002
1248166676Sjkim#define	BGE_MARBMODE_TX_ADDR_TRAP	0x00000004
1249166676Sjkim#define	BGE_MARBMODE_RX_ADDR_TRAP	0x00000008
1250166676Sjkim#define	BGE_MARBMODE_DMAW1_TRAP		0x00000010
1251166676Sjkim#define	BGE_MARBMODE_DMAR1_TRAP		0x00000020
1252166676Sjkim#define	BGE_MARBMODE_RXRISC_TRAP	0x00000040
1253166676Sjkim#define	BGE_MARBMODE_TXRISC_TRAP	0x00000080
1254166676Sjkim#define	BGE_MARBMODE_PCI_TRAP		0x00000100
1255166676Sjkim#define	BGE_MARBMODE_DMAR2_TRAP		0x00000200
1256166676Sjkim#define	BGE_MARBMODE_RXQ_TRAP		0x00000400
1257166676Sjkim#define	BGE_MARBMODE_RXDI1_TRAP		0x00000800
1258166676Sjkim#define	BGE_MARBMODE_RXDI2_TRAP		0x00001000
1259166676Sjkim#define	BGE_MARBMODE_DC_GRPMEM_TRAP	0x00002000
1260166676Sjkim#define	BGE_MARBMODE_HCOAL_TRAP		0x00004000
1261166676Sjkim#define	BGE_MARBMODE_MBUF_TRAP		0x00008000
1262166676Sjkim#define	BGE_MARBMODE_TXDI_TRAP		0x00010000
1263166676Sjkim#define	BGE_MARBMODE_SDC_DMAC_TRAP	0x00020000
1264166676Sjkim#define	BGE_MARBMODE_TXBD_TRAP		0x00040000
1265166676Sjkim#define	BGE_MARBMODE_BUFFMAN_TRAP	0x00080000
1266166676Sjkim#define	BGE_MARBMODE_DMAW2_TRAP		0x00100000
1267166676Sjkim#define	BGE_MARBMODE_XTSSRAM_ROFLO_TRAP	0x00200000
1268166676Sjkim#define	BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1269166676Sjkim#define	BGE_MARBMODE_XTSSRAM_WOFLO_TRAP	0x00800000
1270166676Sjkim#define	BGE_MARBMODE_XTSSRAM_WUFLO_TRAP	0x01000000
1271166676Sjkim#define	BGE_MARBMODE_XTSSRAM_PERR_TRAP	0x02000000
127284059Swpaul
127384059Swpaul/* Memory arbiter status register */
1274166676Sjkim#define	BGE_MARBSTAT_TX_ADDR_TRAP	0x00000004
1275166676Sjkim#define	BGE_MARBSTAT_RX_ADDR_TRAP	0x00000008
1276166676Sjkim#define	BGE_MARBSTAT_DMAW1_TRAP		0x00000010
1277166676Sjkim#define	BGE_MARBSTAT_DMAR1_TRAP		0x00000020
1278166676Sjkim#define	BGE_MARBSTAT_RXRISC_TRAP	0x00000040
1279166676Sjkim#define	BGE_MARBSTAT_TXRISC_TRAP	0x00000080
1280166676Sjkim#define	BGE_MARBSTAT_PCI_TRAP		0x00000100
1281166676Sjkim#define	BGE_MARBSTAT_DMAR2_TRAP		0x00000200
1282166676Sjkim#define	BGE_MARBSTAT_RXQ_TRAP		0x00000400
1283166676Sjkim#define	BGE_MARBSTAT_RXDI1_TRAP		0x00000800
1284166676Sjkim#define	BGE_MARBSTAT_RXDI2_TRAP		0x00001000
1285166676Sjkim#define	BGE_MARBSTAT_DC_GRPMEM_TRAP	0x00002000
1286166676Sjkim#define	BGE_MARBSTAT_HCOAL_TRAP		0x00004000
1287166676Sjkim#define	BGE_MARBSTAT_MBUF_TRAP		0x00008000
1288166676Sjkim#define	BGE_MARBSTAT_TXDI_TRAP		0x00010000
1289166676Sjkim#define	BGE_MARBSTAT_SDC_DMAC_TRAP	0x00020000
1290166676Sjkim#define	BGE_MARBSTAT_TXBD_TRAP		0x00040000
1291166676Sjkim#define	BGE_MARBSTAT_BUFFMAN_TRAP	0x00080000
1292166676Sjkim#define	BGE_MARBSTAT_DMAW2_TRAP		0x00100000
1293166676Sjkim#define	BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP	0x00200000
1294166676Sjkim#define	BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1295166676Sjkim#define	BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP	0x00800000
1296166676Sjkim#define	BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP	0x01000000
1297166676Sjkim#define	BGE_MARBSTAT_XTSSRAM_PERR_TRAP	0x02000000
129884059Swpaul
129984059Swpaul/*
130084059Swpaul * Buffer manager control registers
130184059Swpaul */
1302166676Sjkim#define	BGE_BMAN_MODE			0x4400
1303166676Sjkim#define	BGE_BMAN_STATUS			0x4404
1304166676Sjkim#define	BGE_BMAN_MBUFPOOL_BASEADDR	0x4408
1305166676Sjkim#define	BGE_BMAN_MBUFPOOL_LEN		0x440C
1306166676Sjkim#define	BGE_BMAN_MBUFPOOL_READDMA_LOWAT	0x4410
1307166676Sjkim#define	BGE_BMAN_MBUFPOOL_MACRX_LOWAT	0x4414
1308166676Sjkim#define	BGE_BMAN_MBUFPOOL_HIWAT		0x4418
1309166676Sjkim#define	BGE_BMAN_RXCPU_MBALLOC_REQ	0x441C
1310166676Sjkim#define	BGE_BMAN_RXCPU_MBALLOC_RESP	0x4420
1311166676Sjkim#define	BGE_BMAN_TXCPU_MBALLOC_REQ	0x4424
1312166676Sjkim#define	BGE_BMAN_TXCPU_MBALLOC_RESP	0x4428
1313166676Sjkim#define	BGE_BMAN_DMA_DESCPOOL_BASEADDR	0x442C
1314166676Sjkim#define	BGE_BMAN_DMA_DESCPOOL_LEN	0x4430
1315166676Sjkim#define	BGE_BMAN_DMA_DESCPOOL_LOWAT	0x4434
1316166676Sjkim#define	BGE_BMAN_DMA_DESCPOOL_HIWAT	0x4438
1317166676Sjkim#define	BGE_BMAN_RXCPU_DMAALLOC_REQ	0x443C
1318166676Sjkim#define	BGE_BMAN_RXCPU_DMAALLOC_RESP	0x4440
1319166676Sjkim#define	BGE_BMAN_TXCPU_DMAALLOC_REQ	0x4444
1320166676Sjkim#define	BGE_BMAN_TXCPU_DMALLLOC_RESP	0x4448
1321166676Sjkim#define	BGE_BMAN_HWDIAG_1		0x444C
1322166676Sjkim#define	BGE_BMAN_HWDIAG_2		0x4450
1323166676Sjkim#define	BGE_BMAN_HWDIAG_3		0x4454
132484059Swpaul
132584059Swpaul/* Buffer manager mode register */
1326166676Sjkim#define	BGE_BMANMODE_RESET		0x00000001
1327166676Sjkim#define	BGE_BMANMODE_ENABLE		0x00000002
1328166676Sjkim#define	BGE_BMANMODE_ATTN		0x00000004
1329166676Sjkim#define	BGE_BMANMODE_TESTMODE		0x00000008
1330166676Sjkim#define	BGE_BMANMODE_LOMBUF_ATTN	0x00000010
133184059Swpaul
133284059Swpaul/* Buffer manager status register */
1333166676Sjkim#define	BGE_BMANSTAT_ERRO		0x00000004
1334166676Sjkim#define	BGE_BMANSTAT_LOWMBUF_ERROR	0x00000010
133584059Swpaul
133684059Swpaul
133784059Swpaul/*
133884059Swpaul * Read DMA Control registers
133984059Swpaul */
1340166676Sjkim#define	BGE_RDMA_MODE			0x4800
1341166676Sjkim#define	BGE_RDMA_STATUS			0x4804
134284059Swpaul
134384059Swpaul/* Read DMA mode register */
1344166676Sjkim#define	BGE_RDMAMODE_RESET		0x00000001
1345166676Sjkim#define	BGE_RDMAMODE_ENABLE		0x00000002
1346166676Sjkim#define	BGE_RDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
1347166676Sjkim#define	BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
1348166676Sjkim#define	BGE_RDMAMODE_PCI_PERR_ATTN	0x00000010
1349166676Sjkim#define	BGE_RDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
1350166676Sjkim#define	BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
1351166676Sjkim#define	BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
1352166676Sjkim#define	BGE_RDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
1353166676Sjkim#define	BGE_RDMAMODE_LOCWRITE_TOOBIG	0x00000200
1354166676Sjkim#define	BGE_RDMAMODE_ALL_ATTNS		0x000003FC
135584059Swpaul
135684059Swpaul/* Read DMA status register */
1357166676Sjkim#define	BGE_RDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
1358166676Sjkim#define	BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
1359166676Sjkim#define	BGE_RDMASTAT_PCI_PERR_ATTN	0x00000010
1360166676Sjkim#define	BGE_RDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
1361166676Sjkim#define	BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
1362166676Sjkim#define	BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
1363166676Sjkim#define	BGE_RDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
1364166676Sjkim#define	BGE_RDMASTAT_LOCWRITE_TOOBIG	0x00000200
136584059Swpaul
136684059Swpaul/*
136784059Swpaul * Write DMA control registers
136884059Swpaul */
1369166676Sjkim#define	BGE_WDMA_MODE			0x4C00
1370166676Sjkim#define	BGE_WDMA_STATUS			0x4C04
137184059Swpaul
137284059Swpaul/* Write DMA mode register */
1373166676Sjkim#define	BGE_WDMAMODE_RESET		0x00000001
1374166676Sjkim#define	BGE_WDMAMODE_ENABLE		0x00000002
1375166676Sjkim#define	BGE_WDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
1376166676Sjkim#define	BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
1377166676Sjkim#define	BGE_WDMAMODE_PCI_PERR_ATTN	0x00000010
1378166676Sjkim#define	BGE_WDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
1379166676Sjkim#define	BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
1380166676Sjkim#define	BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
1381166676Sjkim#define	BGE_WDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
1382166676Sjkim#define	BGE_WDMAMODE_LOCREAD_TOOBIG	0x00000200
1383166676Sjkim#define	BGE_WDMAMODE_ALL_ATTNS		0x000003FC
138484059Swpaul
138584059Swpaul/* Write DMA status register */
1386166676Sjkim#define	BGE_WDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
1387166676Sjkim#define	BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
1388166676Sjkim#define	BGE_WDMASTAT_PCI_PERR_ATTN	0x00000010
1389166676Sjkim#define	BGE_WDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
1390166676Sjkim#define	BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
1391166676Sjkim#define	BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
1392166676Sjkim#define	BGE_WDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
1393166676Sjkim#define	BGE_WDMASTAT_LOCREAD_TOOBIG	0x00000200
139484059Swpaul
139584059Swpaul
139684059Swpaul/*
139784059Swpaul * RX CPU registers
139884059Swpaul */
1399166676Sjkim#define	BGE_RXCPU_MODE			0x5000
1400166676Sjkim#define	BGE_RXCPU_STATUS		0x5004
1401166676Sjkim#define	BGE_RXCPU_PC			0x501C
140284059Swpaul
140384059Swpaul/* RX CPU mode register */
1404166676Sjkim#define	BGE_RXCPUMODE_RESET		0x00000001
1405166676Sjkim#define	BGE_RXCPUMODE_SINGLESTEP	0x00000002
1406166676Sjkim#define	BGE_RXCPUMODE_P0_DATAHLT_ENB	0x00000004
1407166676Sjkim#define	BGE_RXCPUMODE_P0_INSTRHLT_ENB	0x00000008
1408166676Sjkim#define	BGE_RXCPUMODE_WR_POSTBUF_ENB	0x00000010
1409166676Sjkim#define	BGE_RXCPUMODE_DATACACHE_ENB	0x00000020
1410166676Sjkim#define	BGE_RXCPUMODE_ROMFAIL		0x00000040
1411166676Sjkim#define	BGE_RXCPUMODE_WATCHDOG_ENB	0x00000080
1412166676Sjkim#define	BGE_RXCPUMODE_INSTRCACHE_PRF	0x00000100
1413166676Sjkim#define	BGE_RXCPUMODE_INSTRCACHE_FLUSH	0x00000200
1414166676Sjkim#define	BGE_RXCPUMODE_HALTCPU		0x00000400
1415166676Sjkim#define	BGE_RXCPUMODE_INVDATAHLT_ENB	0x00000800
1416166676Sjkim#define	BGE_RXCPUMODE_MADDRTRAPHLT_ENB	0x00001000
1417166676Sjkim#define	BGE_RXCPUMODE_RADDRTRAPHLT_ENB	0x00002000
141884059Swpaul
141984059Swpaul/* RX CPU status register */
1420166676Sjkim#define	BGE_RXCPUSTAT_HW_BREAKPOINT	0x00000001
1421166676Sjkim#define	BGE_RXCPUSTAT_HLTINSTR_EXECUTED	0x00000002
1422166676Sjkim#define	BGE_RXCPUSTAT_INVALID_INSTR	0x00000004
1423166676Sjkim#define	BGE_RXCPUSTAT_P0_DATAREF	0x00000008
1424166676Sjkim#define	BGE_RXCPUSTAT_P0_INSTRREF	0x00000010
1425166676Sjkim#define	BGE_RXCPUSTAT_INVALID_DATAACC	0x00000020
1426166676Sjkim#define	BGE_RXCPUSTAT_INVALID_INSTRFTCH	0x00000040
1427166676Sjkim#define	BGE_RXCPUSTAT_BAD_MEMALIGN	0x00000080
1428166676Sjkim#define	BGE_RXCPUSTAT_MADDR_TRAP	0x00000100
1429166676Sjkim#define	BGE_RXCPUSTAT_REGADDR_TRAP	0x00000200
1430166676Sjkim#define	BGE_RXCPUSTAT_DATAACC_STALL	0x00001000
1431166676Sjkim#define	BGE_RXCPUSTAT_INSTRFETCH_STALL	0x00002000
1432166676Sjkim#define	BGE_RXCPUSTAT_MA_WR_FIFOOFLOW	0x08000000
1433166676Sjkim#define	BGE_RXCPUSTAT_MA_RD_FIFOOFLOW	0x10000000
1434166676Sjkim#define	BGE_RXCPUSTAT_MA_DATAMASK_OFLOW	0x20000000
1435166676Sjkim#define	BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW	0x40000000
1436166676Sjkim#define	BGE_RXCPUSTAT_BLOCKING_READ	0x80000000
143784059Swpaul
143884059Swpaul
143984059Swpaul/*
144084059Swpaul * TX CPU registers
144184059Swpaul */
1442166676Sjkim#define	BGE_TXCPU_MODE			0x5400
1443166676Sjkim#define	BGE_TXCPU_STATUS		0x5404
1444166676Sjkim#define	BGE_TXCPU_PC			0x541C
144584059Swpaul
144684059Swpaul/* TX CPU mode register */
1447166676Sjkim#define	BGE_TXCPUMODE_RESET		0x00000001
1448166676Sjkim#define	BGE_TXCPUMODE_SINGLESTEP	0x00000002
1449166676Sjkim#define	BGE_TXCPUMODE_P0_DATAHLT_ENB	0x00000004
1450166676Sjkim#define	BGE_TXCPUMODE_P0_INSTRHLT_ENB	0x00000008
1451166676Sjkim#define	BGE_TXCPUMODE_WR_POSTBUF_ENB	0x00000010
1452166676Sjkim#define	BGE_TXCPUMODE_DATACACHE_ENB	0x00000020
1453166676Sjkim#define	BGE_TXCPUMODE_ROMFAIL		0x00000040
1454166676Sjkim#define	BGE_TXCPUMODE_WATCHDOG_ENB	0x00000080
1455166676Sjkim#define	BGE_TXCPUMODE_INSTRCACHE_PRF	0x00000100
1456166676Sjkim#define	BGE_TXCPUMODE_INSTRCACHE_FLUSH	0x00000200
1457166676Sjkim#define	BGE_TXCPUMODE_HALTCPU		0x00000400
1458166676Sjkim#define	BGE_TXCPUMODE_INVDATAHLT_ENB	0x00000800
1459166676Sjkim#define	BGE_TXCPUMODE_MADDRTRAPHLT_ENB	0x00001000
146084059Swpaul
146184059Swpaul/* TX CPU status register */
1462166676Sjkim#define	BGE_TXCPUSTAT_HW_BREAKPOINT	0x00000001
1463166676Sjkim#define	BGE_TXCPUSTAT_HLTINSTR_EXECUTED	0x00000002
1464166676Sjkim#define	BGE_TXCPUSTAT_INVALID_INSTR	0x00000004
1465166676Sjkim#define	BGE_TXCPUSTAT_P0_DATAREF	0x00000008
1466166676Sjkim#define	BGE_TXCPUSTAT_P0_INSTRREF	0x00000010
1467166676Sjkim#define	BGE_TXCPUSTAT_INVALID_DATAACC	0x00000020
1468166676Sjkim#define	BGE_TXCPUSTAT_INVALID_INSTRFTCH	0x00000040
1469166676Sjkim#define	BGE_TXCPUSTAT_BAD_MEMALIGN	0x00000080
1470166676Sjkim#define	BGE_TXCPUSTAT_MADDR_TRAP	0x00000100
1471166676Sjkim#define	BGE_TXCPUSTAT_REGADDR_TRAP	0x00000200
1472166676Sjkim#define	BGE_TXCPUSTAT_DATAACC_STALL	0x00001000
1473166676Sjkim#define	BGE_TXCPUSTAT_INSTRFETCH_STALL	0x00002000
1474166676Sjkim#define	BGE_TXCPUSTAT_MA_WR_FIFOOFLOW	0x08000000
1475166676Sjkim#define	BGE_TXCPUSTAT_MA_RD_FIFOOFLOW	0x10000000
1476166676Sjkim#define	BGE_TXCPUSTAT_MA_DATAMASK_OFLOW	0x20000000
1477166676Sjkim#define	BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW	0x40000000
1478166676Sjkim#define	BGE_TXCPUSTAT_BLOCKING_READ	0x80000000
147984059Swpaul
148084059Swpaul
148184059Swpaul/*
148284059Swpaul * Low priority mailbox registers
148384059Swpaul */
1484166676Sjkim#define	BGE_LPMBX_IRQ0_HI		0x5800
1485166676Sjkim#define	BGE_LPMBX_IRQ0_LO		0x5804
1486166676Sjkim#define	BGE_LPMBX_IRQ1_HI		0x5808
1487166676Sjkim#define	BGE_LPMBX_IRQ1_LO		0x580C
1488166676Sjkim#define	BGE_LPMBX_IRQ2_HI		0x5810
1489166676Sjkim#define	BGE_LPMBX_IRQ2_LO		0x5814
1490166676Sjkim#define	BGE_LPMBX_IRQ3_HI		0x5818
1491166676Sjkim#define	BGE_LPMBX_IRQ3_LO		0x581C
1492166676Sjkim#define	BGE_LPMBX_GEN0_HI		0x5820
1493166676Sjkim#define	BGE_LPMBX_GEN0_LO		0x5824
1494166676Sjkim#define	BGE_LPMBX_GEN1_HI		0x5828
1495166676Sjkim#define	BGE_LPMBX_GEN1_LO		0x582C
1496166676Sjkim#define	BGE_LPMBX_GEN2_HI		0x5830
1497166676Sjkim#define	BGE_LPMBX_GEN2_LO		0x5834
1498166676Sjkim#define	BGE_LPMBX_GEN3_HI		0x5828
1499166676Sjkim#define	BGE_LPMBX_GEN3_LO		0x582C
1500166676Sjkim#define	BGE_LPMBX_GEN4_HI		0x5840
1501166676Sjkim#define	BGE_LPMBX_GEN4_LO		0x5844
1502166676Sjkim#define	BGE_LPMBX_GEN5_HI		0x5848
1503166676Sjkim#define	BGE_LPMBX_GEN5_LO		0x584C
1504166676Sjkim#define	BGE_LPMBX_GEN6_HI		0x5850
1505166676Sjkim#define	BGE_LPMBX_GEN6_LO		0x5854
1506166676Sjkim#define	BGE_LPMBX_GEN7_HI		0x5858
1507166676Sjkim#define	BGE_LPMBX_GEN7_LO		0x585C
1508166676Sjkim#define	BGE_LPMBX_RELOAD_STATS_HI	0x5860
1509166676Sjkim#define	BGE_LPMBX_RELOAD_STATS_LO	0x5864
1510166676Sjkim#define	BGE_LPMBX_RX_STD_PROD_HI	0x5868
1511166676Sjkim#define	BGE_LPMBX_RX_STD_PROD_LO	0x586C
1512166676Sjkim#define	BGE_LPMBX_RX_JUMBO_PROD_HI	0x5870
1513166676Sjkim#define	BGE_LPMBX_RX_JUMBO_PROD_LO	0x5874
1514166676Sjkim#define	BGE_LPMBX_RX_MINI_PROD_HI	0x5878
1515166676Sjkim#define	BGE_LPMBX_RX_MINI_PROD_LO	0x587C
1516166676Sjkim#define	BGE_LPMBX_RX_CONS0_HI		0x5880
1517166676Sjkim#define	BGE_LPMBX_RX_CONS0_LO		0x5884
1518166676Sjkim#define	BGE_LPMBX_RX_CONS1_HI		0x5888
1519166676Sjkim#define	BGE_LPMBX_RX_CONS1_LO		0x588C
1520166676Sjkim#define	BGE_LPMBX_RX_CONS2_HI		0x5890
1521166676Sjkim#define	BGE_LPMBX_RX_CONS2_LO		0x5894
1522166676Sjkim#define	BGE_LPMBX_RX_CONS3_HI		0x5898
1523166676Sjkim#define	BGE_LPMBX_RX_CONS3_LO		0x589C
1524166676Sjkim#define	BGE_LPMBX_RX_CONS4_HI		0x58A0
1525166676Sjkim#define	BGE_LPMBX_RX_CONS4_LO		0x58A4
1526166676Sjkim#define	BGE_LPMBX_RX_CONS5_HI		0x58A8
1527166676Sjkim#define	BGE_LPMBX_RX_CONS5_LO		0x58AC
1528166676Sjkim#define	BGE_LPMBX_RX_CONS6_HI		0x58B0
1529166676Sjkim#define	BGE_LPMBX_RX_CONS6_LO		0x58B4
1530166676Sjkim#define	BGE_LPMBX_RX_CONS7_HI		0x58B8
1531166676Sjkim#define	BGE_LPMBX_RX_CONS7_LO		0x58BC
1532166676Sjkim#define	BGE_LPMBX_RX_CONS8_HI		0x58C0
1533166676Sjkim#define	BGE_LPMBX_RX_CONS8_LO		0x58C4
1534166676Sjkim#define	BGE_LPMBX_RX_CONS9_HI		0x58C8
1535166676Sjkim#define	BGE_LPMBX_RX_CONS9_LO		0x58CC
1536166676Sjkim#define	BGE_LPMBX_RX_CONS10_HI		0x58D0
1537166676Sjkim#define	BGE_LPMBX_RX_CONS10_LO		0x58D4
1538166676Sjkim#define	BGE_LPMBX_RX_CONS11_HI		0x58D8
1539166676Sjkim#define	BGE_LPMBX_RX_CONS11_LO		0x58DC
1540166676Sjkim#define	BGE_LPMBX_RX_CONS12_HI		0x58E0
1541166676Sjkim#define	BGE_LPMBX_RX_CONS12_LO		0x58E4
1542166676Sjkim#define	BGE_LPMBX_RX_CONS13_HI		0x58E8
1543166676Sjkim#define	BGE_LPMBX_RX_CONS13_LO		0x58EC
1544166676Sjkim#define	BGE_LPMBX_RX_CONS14_HI		0x58F0
1545166676Sjkim#define	BGE_LPMBX_RX_CONS14_LO		0x58F4
1546166676Sjkim#define	BGE_LPMBX_RX_CONS15_HI		0x58F8
1547166676Sjkim#define	BGE_LPMBX_RX_CONS15_LO		0x58FC
1548166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD0_HI	0x5900
1549166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD0_LO	0x5904
1550166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD1_HI	0x5908
1551166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD1_LO	0x590C
1552166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD2_HI	0x5910
1553166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD2_LO	0x5914
1554166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD3_HI	0x5918
1555166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD3_LO	0x591C
1556166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD4_HI	0x5920
1557166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD4_LO	0x5924
1558166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD5_HI	0x5928
1559166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD5_LO	0x592C
1560166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD6_HI	0x5930
1561166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD6_LO	0x5934
1562166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD7_HI	0x5938
1563166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD7_LO	0x593C
1564166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD8_HI	0x5940
1565166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD8_LO	0x5944
1566166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD9_HI	0x5948
1567166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD9_LO	0x594C
1568166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD10_HI	0x5950
1569166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD10_LO	0x5954
1570166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD11_HI	0x5958
1571166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD11_LO	0x595C
1572166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD12_HI	0x5960
1573166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD12_LO	0x5964
1574166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD13_HI	0x5968
1575166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD13_LO	0x596C
1576166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD14_HI	0x5970
1577166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD14_LO	0x5974
1578166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD15_HI	0x5978
1579166676Sjkim#define	BGE_LPMBX_TX_HOST_PROD15_LO	0x597C
1580166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD0_HI	0x5980
1581166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD0_LO	0x5984
1582166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD1_HI	0x5988
1583166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD1_LO	0x598C
1584166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD2_HI	0x5990
1585166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD2_LO	0x5994
1586166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD3_HI	0x5998
1587166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD3_LO	0x599C
1588166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD4_HI	0x59A0
1589166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD4_LO	0x59A4
1590166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD5_HI	0x59A8
1591166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD5_LO	0x59AC
1592166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD6_HI	0x59B0
1593166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD6_LO	0x59B4
1594166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD7_HI	0x59B8
1595166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD7_LO	0x59BC
1596166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD8_HI	0x59C0
1597166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD8_LO	0x59C4
1598166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD9_HI	0x59C8
1599166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD9_LO	0x59CC
1600166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD10_HI	0x59D0
1601166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD10_LO	0x59D4
1602166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD11_HI	0x59D8
1603166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD11_LO	0x59DC
1604166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD12_HI	0x59E0
1605166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD12_LO	0x59E4
1606166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD13_HI	0x59E8
1607166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD13_LO	0x59EC
1608166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD14_HI	0x59F0
1609166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD14_LO	0x59F4
1610166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD15_HI	0x59F8
1611166676Sjkim#define	BGE_LPMBX_TX_NIC_PROD15_LO	0x59FC
161284059Swpaul
161384059Swpaul/*
161484059Swpaul * Flow throw Queue reset register
161584059Swpaul */
1616166676Sjkim#define	BGE_FTQ_RESET			0x5C00
161784059Swpaul
1618166676Sjkim#define	BGE_FTQRESET_DMAREAD		0x00000002
1619166676Sjkim#define	BGE_FTQRESET_DMAHIPRIO_RD	0x00000004
1620166676Sjkim#define	BGE_FTQRESET_DMADONE		0x00000010
1621166676Sjkim#define	BGE_FTQRESET_SBDC		0x00000020
1622166676Sjkim#define	BGE_FTQRESET_SDI		0x00000040
1623166676Sjkim#define	BGE_FTQRESET_WDMA		0x00000080
1624166676Sjkim#define	BGE_FTQRESET_DMAHIPRIO_WR	0x00000100
1625166676Sjkim#define	BGE_FTQRESET_TYPE1_SOFTWARE	0x00000200
1626166676Sjkim#define	BGE_FTQRESET_SDC		0x00000400
1627166676Sjkim#define	BGE_FTQRESET_HCC		0x00000800
1628166676Sjkim#define	BGE_FTQRESET_TXFIFO		0x00001000
1629166676Sjkim#define	BGE_FTQRESET_MBC		0x00002000
1630166676Sjkim#define	BGE_FTQRESET_RBDC		0x00004000
1631166676Sjkim#define	BGE_FTQRESET_RXLP		0x00008000
1632166676Sjkim#define	BGE_FTQRESET_RDBDI		0x00010000
1633166676Sjkim#define	BGE_FTQRESET_RDC		0x00020000
1634166676Sjkim#define	BGE_FTQRESET_TYPE2_SOFTWARE	0x00040000
163584059Swpaul
163684059Swpaul/*
163784059Swpaul * Message Signaled Interrupt registers
163884059Swpaul */
1639166676Sjkim#define	BGE_MSI_MODE			0x6000
1640166676Sjkim#define	BGE_MSI_STATUS			0x6004
1641166676Sjkim#define	BGE_MSI_FIFOACCESS		0x6008
164284059Swpaul
164384059Swpaul/* MSI mode register */
1644166676Sjkim#define	BGE_MSIMODE_RESET		0x00000001
1645166676Sjkim#define	BGE_MSIMODE_ENABLE		0x00000002
1646166676Sjkim#define	BGE_MSIMODE_PCI_TGT_ABRT_ATTN	0x00000004
1647166676Sjkim#define	BGE_MSIMODE_PCI_MSTR_ABRT_ATTN	0x00000008
1648166676Sjkim#define	BGE_MSIMODE_PCI_PERR_ATTN	0x00000010
1649166676Sjkim#define	BGE_MSIMODE_MSI_FIFOUFLOW_ATTN	0x00000020
1650166676Sjkim#define	BGE_MSIMODE_MSI_FIFOOFLOW_ATTN	0x00000040
165184059Swpaul
165284059Swpaul/* MSI status register */
1653166676Sjkim#define	BGE_MSISTAT_PCI_TGT_ABRT_ATTN	0x00000004
1654166676Sjkim#define	BGE_MSISTAT_PCI_MSTR_ABRT_ATTN	0x00000008
1655166676Sjkim#define	BGE_MSISTAT_PCI_PERR_ATTN	0x00000010
1656166676Sjkim#define	BGE_MSISTAT_MSI_FIFOUFLOW_ATTN	0x00000020
1657166676Sjkim#define	BGE_MSISTAT_MSI_FIFOOFLOW_ATTN	0x00000040
165884059Swpaul
165984059Swpaul
166084059Swpaul/*
166184059Swpaul * DMA Completion registers
166284059Swpaul */
1663166676Sjkim#define	BGE_DMAC_MODE			0x6400
166484059Swpaul
166584059Swpaul/* DMA Completion mode register */
1666166676Sjkim#define	BGE_DMACMODE_RESET		0x00000001
1667166676Sjkim#define	BGE_DMACMODE_ENABLE		0x00000002
166884059Swpaul
166984059Swpaul
167084059Swpaul/*
167184059Swpaul * General control registers.
167284059Swpaul */
1673166676Sjkim#define	BGE_MODE_CTL			0x6800
1674166676Sjkim#define	BGE_MISC_CFG			0x6804
1675166676Sjkim#define	BGE_MISC_LOCAL_CTL		0x6808
1676166676Sjkim#define	BGE_CPU_EVENT			0x6810
1677166676Sjkim#define	BGE_EE_ADDR			0x6838
1678166676Sjkim#define	BGE_EE_DATA			0x683C
1679166676Sjkim#define	BGE_EE_CTL			0x6840
1680166676Sjkim#define	BGE_MDI_CTL			0x6844
1681166676Sjkim#define	BGE_EE_DELAY			0x6848
1682166676Sjkim#define	BGE_FASTBOOT_PC			0x6894
168384059Swpaul
168484059Swpaul/* Mode control register */
1685166676Sjkim#define	BGE_MODECTL_INT_SNDCOAL_ONLY	0x00000001
1686166676Sjkim#define	BGE_MODECTL_BYTESWAP_NONFRAME	0x00000002
1687166676Sjkim#define	BGE_MODECTL_WORDSWAP_NONFRAME	0x00000004
1688166676Sjkim#define	BGE_MODECTL_BYTESWAP_DATA	0x00000010
1689166676Sjkim#define	BGE_MODECTL_WORDSWAP_DATA	0x00000020
1690166676Sjkim#define	BGE_MODECTL_NO_FRAME_CRACKING	0x00000200
1691166676Sjkim#define	BGE_MODECTL_NO_RX_CRC		0x00000400
1692166676Sjkim#define	BGE_MODECTL_RX_BADFRAMES	0x00000800
1693166676Sjkim#define	BGE_MODECTL_NO_TX_INTR		0x00002000
1694166676Sjkim#define	BGE_MODECTL_NO_RX_INTR		0x00004000
1695166676Sjkim#define	BGE_MODECTL_FORCE_PCI32		0x00008000
1696166676Sjkim#define	BGE_MODECTL_STACKUP		0x00010000
1697166676Sjkim#define	BGE_MODECTL_HOST_SEND_BDS	0x00020000
1698166676Sjkim#define	BGE_MODECTL_TX_NO_PHDR_CSUM	0x00100000
1699166676Sjkim#define	BGE_MODECTL_RX_NO_PHDR_CSUM	0x00800000
1700166676Sjkim#define	BGE_MODECTL_TX_ATTN_INTR	0x01000000
1701166676Sjkim#define	BGE_MODECTL_RX_ATTN_INTR	0x02000000
1702166676Sjkim#define	BGE_MODECTL_MAC_ATTN_INTR	0x04000000
1703166676Sjkim#define	BGE_MODECTL_DMA_ATTN_INTR	0x08000000
1704166676Sjkim#define	BGE_MODECTL_FLOWCTL_ATTN_INTR	0x10000000
1705166676Sjkim#define	BGE_MODECTL_4X_SENDRING_SZ	0x20000000
1706166676Sjkim#define	BGE_MODECTL_FW_PROCESS_MCASTS	0x40000000
170784059Swpaul
170884059Swpaul/* Misc. config register */
1709166676Sjkim#define	BGE_MISCCFG_RESET_CORE_CLOCKS	0x00000001
1710166676Sjkim#define	BGE_MISCCFG_TIMER_PRESCALER	0x000000FE
171184059Swpaul
1712166676Sjkim#define	BGE_32BITTIME_66MHZ		(0x41 << 1)
171384059Swpaul
171484059Swpaul/* Misc. Local Control */
1715166676Sjkim#define	BGE_MLC_INTR_STATE		0x00000001
1716166676Sjkim#define	BGE_MLC_INTR_CLR		0x00000002
1717166676Sjkim#define	BGE_MLC_INTR_SET		0x00000004
1718166676Sjkim#define	BGE_MLC_INTR_ONATTN		0x00000008
1719166676Sjkim#define	BGE_MLC_MISCIO_IN0		0x00000100
1720166676Sjkim#define	BGE_MLC_MISCIO_IN1		0x00000200
1721166676Sjkim#define	BGE_MLC_MISCIO_IN2		0x00000400
1722166676Sjkim#define	BGE_MLC_MISCIO_OUTEN0		0x00000800
1723166676Sjkim#define	BGE_MLC_MISCIO_OUTEN1		0x00001000
1724166676Sjkim#define	BGE_MLC_MISCIO_OUTEN2		0x00002000
1725166676Sjkim#define	BGE_MLC_MISCIO_OUT0		0x00004000
1726166676Sjkim#define	BGE_MLC_MISCIO_OUT1		0x00008000
1727166676Sjkim#define	BGE_MLC_MISCIO_OUT2		0x00010000
1728166676Sjkim#define	BGE_MLC_EXTRAM_ENB		0x00020000
1729166676Sjkim#define	BGE_MLC_SRAM_SIZE		0x001C0000
1730166676Sjkim#define	BGE_MLC_BANK_SEL		0x00200000 /* 0 = 2 banks, 1 == 1 */
1731166676Sjkim#define	BGE_MLC_SSRAM_TYPE		0x00400000 /* 1 = ZBT, 0 = standard */
1732166676Sjkim#define	BGE_MLC_SSRAM_CYC_DESEL		0x00800000
1733166676Sjkim#define	BGE_MLC_AUTO_EEPROM		0x01000000
173484059Swpaul
1735166676Sjkim#define	BGE_SSRAMSIZE_256KB		0x00000000
1736166676Sjkim#define	BGE_SSRAMSIZE_512KB		0x00040000
1737166676Sjkim#define	BGE_SSRAMSIZE_1MB		0x00080000
1738166676Sjkim#define	BGE_SSRAMSIZE_2MB		0x000C0000
1739166676Sjkim#define	BGE_SSRAMSIZE_4MB		0x00100000
1740166676Sjkim#define	BGE_SSRAMSIZE_8MB		0x00140000
1741166676Sjkim#define	BGE_SSRAMSIZE_16M		0x00180000
174284059Swpaul
174384059Swpaul/* EEPROM address register */
1744166676Sjkim#define	BGE_EEADDR_ADDRESS		0x0000FFFC
1745166676Sjkim#define	BGE_EEADDR_HALFCLK		0x01FF0000
1746166676Sjkim#define	BGE_EEADDR_START		0x02000000
1747166676Sjkim#define	BGE_EEADDR_DEVID		0x1C000000
1748166676Sjkim#define	BGE_EEADDR_RESET		0x20000000
1749166676Sjkim#define	BGE_EEADDR_DONE			0x40000000
1750166676Sjkim#define	BGE_EEADDR_RW			0x80000000 /* 1 = rd, 0 = wr */
175184059Swpaul
1752166676Sjkim#define	BGE_EEDEVID(x)			((x & 7) << 26)
1753166676Sjkim#define	BGE_EEHALFCLK(x)		((x & 0x1FF) << 16)
1754166676Sjkim#define	BGE_HALFCLK_384SCL		0x60
1755166676Sjkim#define	BGE_EE_READCMD \
175684059Swpaul	(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)|	\
175784059Swpaul	BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1758166676Sjkim#define	BGE_EE_WRCMD \
175984059Swpaul	(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)|	\
176084059Swpaul	BGE_EEADDR_START|BGE_EEADDR_DONE)
176184059Swpaul
176284059Swpaul/* EEPROM Control register */
1763166676Sjkim#define	BGE_EECTL_CLKOUT_TRISTATE	0x00000001
1764166676Sjkim#define	BGE_EECTL_CLKOUT		0x00000002
1765166676Sjkim#define	BGE_EECTL_CLKIN			0x00000004
1766166676Sjkim#define	BGE_EECTL_DATAOUT_TRISTATE	0x00000008
1767166676Sjkim#define	BGE_EECTL_DATAOUT		0x00000010
1768166676Sjkim#define	BGE_EECTL_DATAIN		0x00000020
176984059Swpaul
177084059Swpaul/* MDI (MII/GMII) access register */
1771166676Sjkim#define	BGE_MDI_DATA			0x00000001
1772166676Sjkim#define	BGE_MDI_DIR			0x00000002
1773166676Sjkim#define	BGE_MDI_SEL			0x00000004
1774166676Sjkim#define	BGE_MDI_CLK			0x00000008
177584059Swpaul
1776166676Sjkim#define	BGE_MEMWIN_START		0x00008000
1777166676Sjkim#define	BGE_MEMWIN_END			0x0000FFFF
177884059Swpaul
177984059Swpaul
1780166676Sjkim#define	BGE_MEMWIN_READ(sc, x, val)					\
178184059Swpaul	do {								\
178284059Swpaul		pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
178384059Swpaul		    (0xFFFF0000 & x), 4);				\
178484059Swpaul		val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF));	\
178584059Swpaul	} while(0)
178684059Swpaul
1787166676Sjkim#define	BGE_MEMWIN_WRITE(sc, x, val)					\
178884059Swpaul	do {								\
178984059Swpaul		pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
179084059Swpaul		    (0xFFFF0000 & x), 4);				\
179184059Swpaul		CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val);	\
179284059Swpaul	} while(0)
179384059Swpaul
179484059Swpaul/*
1795161847Sdavidch * This magic number is written to the firmware mailbox at 0xb50
1796161847Sdavidch * before a software reset is issued.  After the internal firmware
1797161847Sdavidch * has completed its initialization it will write the opposite of
1798161847Sdavidch * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
1799161847Sdavidch * driver to synchronize with the firmware.
180084059Swpaul */
1801166676Sjkim#define	BGE_MAGIC_NUMBER                0x4B657654
180284059Swpaul
180384059Swpaultypedef struct {
1804159395Sglebius	uint32_t		bge_addr_hi;
1805159395Sglebius	uint32_t		bge_addr_lo;
180684059Swpaul} bge_hostaddr;
1807118026Swpaul
1808166676Sjkim#define	BGE_HOSTADDR(x, y)						\
1809115200Sps	do {								\
1810159395Sglebius		(x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff);	\
1811159395Sglebius		(x).bge_addr_hi = ((uint64_t) (y) >> 32);		\
1812115200Sps	} while(0)
181384059Swpaul
1814166676Sjkim#define	BGE_ADDR_LO(y)	\
1815159395Sglebius	((uint64_t) (y) & 0xFFFFFFFF)
1816166676Sjkim#define	BGE_ADDR_HI(y)	\
1817159395Sglebius	((uint64_t) (y) >> 32)
1818118026Swpaul
181984059Swpaul/* Ring control block structure */
182084059Swpaulstruct bge_rcb {
182184059Swpaul	bge_hostaddr		bge_hostaddr;
1822159395Sglebius	uint32_t		bge_maxlen_flags;
1823159395Sglebius	uint32_t		bge_nicaddr;
182484059Swpaul};
1825153437Syongari
1826153437Syongari#define	RCB_WRITE_4(sc, rcb, offset, val) \
1827153437Syongari	bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
1828153437Syongari			  rcb + offsetof(struct bge_rcb, offset), val)
1829166676Sjkim#define	BGE_RCB_MAXLEN_FLAGS(maxlen, flags)	((maxlen) << 16 | (flags))
183084059Swpaul
1831166676Sjkim#define	BGE_RCB_FLAG_USE_EXT_RX_BD	0x0001
1832166676Sjkim#define	BGE_RCB_FLAG_RING_DISABLED	0x0002
183384059Swpaul
183484059Swpaulstruct bge_tx_bd {
183584059Swpaul	bge_hostaddr		bge_addr;
1836153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN
1837159395Sglebius	uint16_t		bge_flags;
1838159395Sglebius	uint16_t		bge_len;
1839159395Sglebius	uint16_t		bge_vlan_tag;
1840159395Sglebius	uint16_t		bge_rsvd;
1841153437Syongari#else
1842159395Sglebius	uint16_t		bge_len;
1843159395Sglebius	uint16_t		bge_flags;
1844159395Sglebius	uint16_t		bge_rsvd;
1845159395Sglebius	uint16_t		bge_vlan_tag;
1846153437Syongari#endif
184784059Swpaul};
184884059Swpaul
1849166676Sjkim#define	BGE_TXBDFLAG_TCP_UDP_CSUM	0x0001
1850166676Sjkim#define	BGE_TXBDFLAG_IP_CSUM		0x0002
1851166676Sjkim#define	BGE_TXBDFLAG_END		0x0004
1852166676Sjkim#define	BGE_TXBDFLAG_IP_FRAG		0x0008
1853166676Sjkim#define	BGE_TXBDFLAG_IP_FRAG_END	0x0010
1854166676Sjkim#define	BGE_TXBDFLAG_VLAN_TAG		0x0040
1855166676Sjkim#define	BGE_TXBDFLAG_COAL_NOW		0x0080
1856166676Sjkim#define	BGE_TXBDFLAG_CPU_PRE_DMA	0x0100
1857166676Sjkim#define	BGE_TXBDFLAG_CPU_POST_DMA	0x0200
1858166676Sjkim#define	BGE_TXBDFLAG_INSERT_SRC_ADDR	0x1000
1859166676Sjkim#define	BGE_TXBDFLAG_CHOOSE_SRC_ADDR	0x6000
1860166676Sjkim#define	BGE_TXBDFLAG_NO_CRC		0x8000
186184059Swpaul
1862166676Sjkim#define	BGE_NIC_TXRING_ADDR(ringno, size)	\
186384059Swpaul	BGE_SEND_RING_1_TO_4 +			\
186484059Swpaul	((ringno * sizeof(struct bge_tx_bd) * size) / 4)
186584059Swpaul
186684059Swpaulstruct bge_rx_bd {
186784059Swpaul	bge_hostaddr		bge_addr;
1868153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN
1869159395Sglebius	uint16_t		bge_len;
1870159395Sglebius	uint16_t		bge_idx;
1871159395Sglebius	uint16_t		bge_flags;
1872159395Sglebius	uint16_t		bge_type;
1873159395Sglebius	uint16_t		bge_tcp_udp_csum;
1874159395Sglebius	uint16_t		bge_ip_csum;
1875159395Sglebius	uint16_t		bge_vlan_tag;
1876159395Sglebius	uint16_t		bge_error_flag;
1877153437Syongari#else
1878159395Sglebius	uint16_t		bge_idx;
1879159395Sglebius	uint16_t		bge_len;
1880159395Sglebius	uint16_t		bge_type;
1881159395Sglebius	uint16_t		bge_flags;
1882159395Sglebius	uint16_t		bge_ip_csum;
1883159395Sglebius	uint16_t		bge_tcp_udp_csum;
1884159395Sglebius	uint16_t		bge_error_flag;
1885159395Sglebius	uint16_t		bge_vlan_tag;
1886153437Syongari#endif
1887159395Sglebius	uint32_t		bge_rsvd;
1888159395Sglebius	uint32_t		bge_opaque;
188984059Swpaul};
189084059Swpaul
1891153239Sglebiusstruct bge_extrx_bd {
1892153239Sglebius	bge_hostaddr		bge_addr1;
1893153239Sglebius	bge_hostaddr		bge_addr2;
1894153239Sglebius	bge_hostaddr		bge_addr3;
1895153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN
1896159395Sglebius	uint16_t		bge_len2;
1897159395Sglebius	uint16_t		bge_len1;
1898159395Sglebius	uint16_t		bge_rsvd1;
1899159395Sglebius	uint16_t		bge_len3;
1900153437Syongari#else
1901159395Sglebius	uint16_t		bge_len1;
1902159395Sglebius	uint16_t		bge_len2;
1903159395Sglebius	uint16_t		bge_len3;
1904159395Sglebius	uint16_t		bge_rsvd1;
1905153437Syongari#endif
1906153239Sglebius	bge_hostaddr		bge_addr0;
1907153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN
1908159395Sglebius	uint16_t		bge_len0;
1909159395Sglebius	uint16_t		bge_idx;
1910159395Sglebius	uint16_t		bge_flags;
1911159395Sglebius	uint16_t		bge_type;
1912159395Sglebius	uint16_t		bge_tcp_udp_csum;
1913159395Sglebius	uint16_t		bge_ip_csum;
1914159395Sglebius	uint16_t		bge_vlan_tag;
1915159395Sglebius	uint16_t		bge_error_flag;
1916153437Syongari#else
1917159395Sglebius	uint16_t		bge_idx;
1918159395Sglebius	uint16_t		bge_len0;
1919159395Sglebius	uint16_t		bge_type;
1920159395Sglebius	uint16_t		bge_flags;
1921159395Sglebius	uint16_t		bge_ip_csum;
1922159395Sglebius	uint16_t		bge_tcp_udp_csum;
1923159395Sglebius	uint16_t		bge_error_flag;
1924159395Sglebius	uint16_t		bge_vlan_tag;
1925153437Syongari#endif
1926159395Sglebius	uint32_t		bge_rsvd0;
1927159395Sglebius	uint32_t		bge_opaque;
1928153239Sglebius};
1929153239Sglebius
1930166676Sjkim#define	BGE_RXBDFLAG_END		0x0004
1931166676Sjkim#define	BGE_RXBDFLAG_JUMBO_RING		0x0020
1932166676Sjkim#define	BGE_RXBDFLAG_VLAN_TAG		0x0040
1933166676Sjkim#define	BGE_RXBDFLAG_ERROR		0x0400
1934166676Sjkim#define	BGE_RXBDFLAG_MINI_RING		0x0800
1935166676Sjkim#define	BGE_RXBDFLAG_IP_CSUM		0x1000
1936166676Sjkim#define	BGE_RXBDFLAG_TCP_UDP_CSUM	0x2000
1937166676Sjkim#define	BGE_RXBDFLAG_TCP_UDP_IS_TCP	0x4000
193884059Swpaul
1939166676Sjkim#define	BGE_RXERRFLAG_BAD_CRC		0x0001
1940166676Sjkim#define	BGE_RXERRFLAG_COLL_DETECT	0x0002
1941166676Sjkim#define	BGE_RXERRFLAG_LINK_LOST		0x0004
1942166676Sjkim#define	BGE_RXERRFLAG_PHY_DECODE_ERR	0x0008
1943166676Sjkim#define	BGE_RXERRFLAG_MAC_ABORT		0x0010
1944166676Sjkim#define	BGE_RXERRFLAG_RUNT		0x0020
1945166676Sjkim#define	BGE_RXERRFLAG_TRUNC_NO_RSRCS	0x0040
1946166676Sjkim#define	BGE_RXERRFLAG_GIANT		0x0080
194784059Swpaul
194884059Swpaulstruct bge_sts_idx {
1949153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN
1950159395Sglebius	uint16_t		bge_rx_prod_idx;
1951159395Sglebius	uint16_t		bge_tx_cons_idx;
1952153437Syongari#else
1953159395Sglebius	uint16_t		bge_tx_cons_idx;
1954159395Sglebius	uint16_t		bge_rx_prod_idx;
1955153437Syongari#endif
195684059Swpaul};
195784059Swpaul
195884059Swpaulstruct bge_status_block {
1959159395Sglebius	uint32_t		bge_status;
1960159395Sglebius	uint32_t		bge_rsvd0;
1961153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN
1962159395Sglebius	uint16_t		bge_rx_jumbo_cons_idx;
1963159395Sglebius	uint16_t		bge_rx_std_cons_idx;
1964159395Sglebius	uint16_t		bge_rx_mini_cons_idx;
1965159395Sglebius	uint16_t		bge_rsvd1;
1966153437Syongari#else
1967159395Sglebius	uint16_t		bge_rx_std_cons_idx;
1968159395Sglebius	uint16_t		bge_rx_jumbo_cons_idx;
1969159395Sglebius	uint16_t		bge_rsvd1;
1970159395Sglebius	uint16_t		bge_rx_mini_cons_idx;
1971153437Syongari#endif
197284059Swpaul	struct bge_sts_idx	bge_idx[16];
197384059Swpaul};
197484059Swpaul
1975166676Sjkim#define	BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
1976166676Sjkim#define	BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
197784059Swpaul
1978166676Sjkim#define	BGE_STATFLAG_UPDATED		0x00000001
1979166676Sjkim#define	BGE_STATFLAG_LINKSTATE_CHANGED	0x00000002
1980166676Sjkim#define	BGE_STATFLAG_ERROR		0x00000004
198184059Swpaul
198284059Swpaul
198384059Swpaul/*
198484059Swpaul * Broadcom Vendor ID
198584059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
198684059Swpaul * even though they're now manufactured by Broadcom)
198784059Swpaul */
1988166676Sjkim#define	BCOM_VENDORID			0x14E4
1989166676Sjkim#define	BCOM_DEVICEID_BCM5700		0x1644
1990166676Sjkim#define	BCOM_DEVICEID_BCM5701		0x1645
1991166676Sjkim#define	BCOM_DEVICEID_BCM5702		0x1646
1992166676Sjkim#define	BCOM_DEVICEID_BCM5702X		0x16A6
1993166676Sjkim#define	BCOM_DEVICEID_BCM5702_ALT	0x16C6
1994166676Sjkim#define	BCOM_DEVICEID_BCM5703		0x1647
1995166676Sjkim#define	BCOM_DEVICEID_BCM5703X		0x16A7
1996166676Sjkim#define	BCOM_DEVICEID_BCM5703_ALT	0x16C7
1997166676Sjkim#define	BCOM_DEVICEID_BCM5704C		0x1648
1998166676Sjkim#define	BCOM_DEVICEID_BCM5704S		0x16A8
1999166676Sjkim#define	BCOM_DEVICEID_BCM5704S_ALT	0x1649
2000166676Sjkim#define	BCOM_DEVICEID_BCM5705		0x1653
2001166676Sjkim#define	BCOM_DEVICEID_BCM5705K		0x1654
2002166676Sjkim#define	BCOM_DEVICEID_BCM5705F		0x166E
2003166676Sjkim#define	BCOM_DEVICEID_BCM5705M		0x165D
2004166676Sjkim#define	BCOM_DEVICEID_BCM5705M_ALT	0x165E
2005166676Sjkim#define	BCOM_DEVICEID_BCM5714C		0x1668
2006166676Sjkim#define	BCOM_DEVICEID_BCM5714S		0x1669
2007166676Sjkim#define	BCOM_DEVICEID_BCM5715		0x1678
2008166676Sjkim#define	BCOM_DEVICEID_BCM5715S		0x1679
2009166676Sjkim#define	BCOM_DEVICEID_BCM5720		0x1658
2010166676Sjkim#define	BCOM_DEVICEID_BCM5721		0x1659
2011166676Sjkim#define	BCOM_DEVICEID_BCM5750		0x1676
2012166676Sjkim#define	BCOM_DEVICEID_BCM5750M		0x167C
2013166676Sjkim#define	BCOM_DEVICEID_BCM5751		0x1677
2014166676Sjkim#define	BCOM_DEVICEID_BCM5751F		0x167E
2015166676Sjkim#define	BCOM_DEVICEID_BCM5751M		0x167D
2016166676Sjkim#define	BCOM_DEVICEID_BCM5752		0x1600
2017166676Sjkim#define	BCOM_DEVICEID_BCM5752M		0x1601
2018166676Sjkim#define	BCOM_DEVICEID_BCM5753		0x16F7
2019166676Sjkim#define	BCOM_DEVICEID_BCM5753F		0x16FE
2020166676Sjkim#define	BCOM_DEVICEID_BCM5753M		0x16FD
2021166676Sjkim#define	BCOM_DEVICEID_BCM5754		0x167A
2022166676Sjkim#define	BCOM_DEVICEID_BCM5754M		0x1672
2023166676Sjkim#define	BCOM_DEVICEID_BCM5755		0x167B
2024166676Sjkim#define	BCOM_DEVICEID_BCM5755M		0x1673
2025166676Sjkim#define	BCOM_DEVICEID_BCM5780		0x166A
2026166676Sjkim#define	BCOM_DEVICEID_BCM5780S		0x166B
2027166676Sjkim#define	BCOM_DEVICEID_BCM5781		0x16DD
2028166676Sjkim#define	BCOM_DEVICEID_BCM5782		0x1696
2029166676Sjkim#define	BCOM_DEVICEID_BCM5786		0x169A
2030166676Sjkim#define	BCOM_DEVICEID_BCM5787		0x169B
2031166676Sjkim#define	BCOM_DEVICEID_BCM5787M		0x1693
2032166676Sjkim#define	BCOM_DEVICEID_BCM5788		0x169C
2033166676Sjkim#define	BCOM_DEVICEID_BCM5789		0x169D
2034166676Sjkim#define	BCOM_DEVICEID_BCM5901		0x170D
2035166676Sjkim#define	BCOM_DEVICEID_BCM5901A2		0x170E
2036166676Sjkim#define	BCOM_DEVICEID_BCM5903M		0x16FF
203784059Swpaul
203884059Swpaul/*
203984059Swpaul * Alteon AceNIC PCI vendor/device ID.
204084059Swpaul */
2041166676Sjkim#define	ALTEON_VENDORID			0x12AE
2042166676Sjkim#define	ALTEON_DEVICEID_ACENIC		0x0001
2043166676Sjkim#define	ALTEON_DEVICEID_ACENIC_COPPER	0x0002
2044166676Sjkim#define	ALTEON_DEVICEID_BCM5700		0x0003
2045166676Sjkim#define	ALTEON_DEVICEID_BCM5701		0x0004
204684059Swpaul
204784059Swpaul/*
2048162982Sglebius * 3Com 3c996 PCI vendor/device ID.
204984059Swpaul */
2050166676Sjkim#define	TC_VENDORID			0x10B7
2051166676Sjkim#define	TC_DEVICEID_3C996		0x0003
205284059Swpaul
205384059Swpaul/*
205484059Swpaul * SysKonnect PCI vendor ID
205584059Swpaul */
2056166676Sjkim#define	SK_VENDORID			0x1148
2057166676Sjkim#define	SK_DEVICEID_ALTIMA		0x4400
2058166676Sjkim#define	SK_SUBSYSID_9D21		0x4421
2059166676Sjkim#define	SK_SUBSYSID_9D41		0x4441
206084059Swpaul
206184059Swpaul/*
206289835Sjdp * Altima PCI vendor/device ID.
206389835Sjdp */
2064166676Sjkim#define	ALTIMA_VENDORID			0x173b
2065166676Sjkim#define	ALTIMA_DEVICE_AC1000		0x03e8
2066166676Sjkim#define	ALTIMA_DEVICE_AC1002		0x03e9
2067166676Sjkim#define	ALTIMA_DEVICE_AC9100		0x03ea
206889835Sjdp
206989835Sjdp/*
2070119157Sambrisko * Dell PCI vendor ID
2071119157Sambrisko */
2072119157Sambrisko
2073166676Sjkim#define	DELL_VENDORID			0x1028
2074119157Sambrisko
2075119157Sambrisko/*
2076159637Sglebius * Apple PCI vendor ID.
2077159637Sglebius */
2078166676Sjkim#define	APPLE_VENDORID			0x106b
2079166676Sjkim#define	APPLE_DEVICE_BCM5701		0x1645
2080159637Sglebius
2081159637Sglebius/*
208284059Swpaul * Offset of MAC address inside EEPROM.
208384059Swpaul */
2084166676Sjkim#define	BGE_EE_MAC_OFFSET		0x7C
2085166676Sjkim#define	BGE_EE_HWCFG_OFFSET		0xC8
208684059Swpaul
2087166676Sjkim#define	BGE_HWCFG_VOLTAGE		0x00000003
2088166676Sjkim#define	BGE_HWCFG_PHYLED_MODE		0x0000000C
2089166676Sjkim#define	BGE_HWCFG_MEDIA			0x00000030
2090166676Sjkim#define	BGE_HWCFG_ASF			0x00000080
209193751Swpaul
2092166676Sjkim#define	BGE_VOLTAGE_1POINT3		0x00000000
2093166676Sjkim#define	BGE_VOLTAGE_1POINT8		0x00000001
209493751Swpaul
2095166676Sjkim#define	BGE_PHYLEDMODE_UNSPEC		0x00000000
2096166676Sjkim#define	BGE_PHYLEDMODE_TRIPLELED	0x00000004
2097166676Sjkim#define	BGE_PHYLEDMODE_SINGLELED	0x00000008
209893751Swpaul
2099166676Sjkim#define	BGE_MEDIA_UNSPEC		0x00000000
2100166676Sjkim#define	BGE_MEDIA_COPPER		0x00000010
2101166676Sjkim#define	BGE_MEDIA_FIBER			0x00000020
210293751Swpaul
2103166676Sjkim#define	BGE_PCI_READ_CMD		0x06000000
2104166676Sjkim#define	BGE_PCI_WRITE_CMD		0x70000000
210584059Swpaul
2106166676Sjkim#define	BGE_TICKS_PER_SEC		1000000
210784059Swpaul
210884059Swpaul/*
210984059Swpaul * Ring size constants.
211084059Swpaul */
2111166676Sjkim#define	BGE_EVENT_RING_CNT	256
2112166676Sjkim#define	BGE_CMD_RING_CNT	64
2113166676Sjkim#define	BGE_STD_RX_RING_CNT	512
2114166676Sjkim#define	BGE_JUMBO_RX_RING_CNT	256
2115166676Sjkim#define	BGE_MINI_RX_RING_CNT	1024
2116166676Sjkim#define	BGE_RETURN_RING_CNT	1024
211784059Swpaul
2118117659Swpaul/* 5705 has smaller return ring size */
2119117659Swpaul
2120166676Sjkim#define	BGE_RETURN_RING_CNT_5705	512
2121117659Swpaul
212284059Swpaul/*
212384059Swpaul * Possible TX ring sizes.
212484059Swpaul */
2125166676Sjkim#define	BGE_TX_RING_CNT_128	128
2126166676Sjkim#define	BGE_TX_RING_BASE_128	0x3800
212784059Swpaul
2128166676Sjkim#define	BGE_TX_RING_CNT_256	256
2129166676Sjkim#define	BGE_TX_RING_BASE_256	0x3000
213084059Swpaul
2131166676Sjkim#define	BGE_TX_RING_CNT_512	512
2132166676Sjkim#define	BGE_TX_RING_BASE_512	0x2000
213384059Swpaul
2134166676Sjkim#define	BGE_TX_RING_CNT		BGE_TX_RING_CNT_512
2135166676Sjkim#define	BGE_TX_RING_BASE	BGE_TX_RING_BASE_512
213684059Swpaul
213784059Swpaul/*
213884059Swpaul * Tigon III statistics counters.
213984059Swpaul */
2140117659Swpaul/* Statistics maintained MAC Receive block. */
2141117659Swpaulstruct bge_rx_mac_stats {
214284059Swpaul	bge_hostaddr		ifHCInOctets;
214384059Swpaul	bge_hostaddr		Reserved1;
214484059Swpaul	bge_hostaddr		etherStatsFragments;
214584059Swpaul	bge_hostaddr		ifHCInUcastPkts;
214684059Swpaul	bge_hostaddr		ifHCInMulticastPkts;
214784059Swpaul	bge_hostaddr		ifHCInBroadcastPkts;
214884059Swpaul	bge_hostaddr		dot3StatsFCSErrors;
214984059Swpaul	bge_hostaddr		dot3StatsAlignmentErrors;
215084059Swpaul	bge_hostaddr		xonPauseFramesReceived;
215184059Swpaul	bge_hostaddr		xoffPauseFramesReceived;
215284059Swpaul	bge_hostaddr		macControlFramesReceived;
215384059Swpaul	bge_hostaddr		xoffStateEntered;
215484059Swpaul	bge_hostaddr		dot3StatsFramesTooLong;
215584059Swpaul	bge_hostaddr		etherStatsJabbers;
215684059Swpaul	bge_hostaddr		etherStatsUndersizePkts;
215784059Swpaul	bge_hostaddr		inRangeLengthError;
215884059Swpaul	bge_hostaddr		outRangeLengthError;
215984059Swpaul	bge_hostaddr		etherStatsPkts64Octets;
216084059Swpaul	bge_hostaddr		etherStatsPkts65Octetsto127Octets;
216184059Swpaul	bge_hostaddr		etherStatsPkts128Octetsto255Octets;
216284059Swpaul	bge_hostaddr		etherStatsPkts256Octetsto511Octets;
216384059Swpaul	bge_hostaddr		etherStatsPkts512Octetsto1023Octets;
216484059Swpaul	bge_hostaddr		etherStatsPkts1024Octetsto1522Octets;
216584059Swpaul	bge_hostaddr		etherStatsPkts1523Octetsto2047Octets;
216684059Swpaul	bge_hostaddr		etherStatsPkts2048Octetsto4095Octets;
216784059Swpaul	bge_hostaddr		etherStatsPkts4096Octetsto8191Octets;
216884059Swpaul	bge_hostaddr		etherStatsPkts8192Octetsto9022Octets;
2169117659Swpaul};
217084059Swpaul
217184059Swpaul
2172117659Swpaul/* Statistics maintained MAC Transmit block. */
2173117659Swpaulstruct bge_tx_mac_stats {
217484059Swpaul	bge_hostaddr		ifHCOutOctets;
217584059Swpaul	bge_hostaddr		Reserved2;
217684059Swpaul	bge_hostaddr		etherStatsCollisions;
217784059Swpaul	bge_hostaddr		outXonSent;
217884059Swpaul	bge_hostaddr		outXoffSent;
217984059Swpaul	bge_hostaddr		flowControlDone;
218084059Swpaul	bge_hostaddr		dot3StatsInternalMacTransmitErrors;
218184059Swpaul	bge_hostaddr		dot3StatsSingleCollisionFrames;
218284059Swpaul	bge_hostaddr		dot3StatsMultipleCollisionFrames;
218384059Swpaul	bge_hostaddr		dot3StatsDeferredTransmissions;
218484059Swpaul	bge_hostaddr		Reserved3;
218584059Swpaul	bge_hostaddr		dot3StatsExcessiveCollisions;
218684059Swpaul	bge_hostaddr		dot3StatsLateCollisions;
218784059Swpaul	bge_hostaddr		dot3Collided2Times;
218884059Swpaul	bge_hostaddr		dot3Collided3Times;
218984059Swpaul	bge_hostaddr		dot3Collided4Times;
219084059Swpaul	bge_hostaddr		dot3Collided5Times;
219184059Swpaul	bge_hostaddr		dot3Collided6Times;
219284059Swpaul	bge_hostaddr		dot3Collided7Times;
219384059Swpaul	bge_hostaddr		dot3Collided8Times;
219484059Swpaul	bge_hostaddr		dot3Collided9Times;
219584059Swpaul	bge_hostaddr		dot3Collided10Times;
219684059Swpaul	bge_hostaddr		dot3Collided11Times;
219784059Swpaul	bge_hostaddr		dot3Collided12Times;
219884059Swpaul	bge_hostaddr		dot3Collided13Times;
219984059Swpaul	bge_hostaddr		dot3Collided14Times;
220084059Swpaul	bge_hostaddr		dot3Collided15Times;
220184059Swpaul	bge_hostaddr		ifHCOutUcastPkts;
220284059Swpaul	bge_hostaddr		ifHCOutMulticastPkts;
220384059Swpaul	bge_hostaddr		ifHCOutBroadcastPkts;
220484059Swpaul	bge_hostaddr		dot3StatsCarrierSenseErrors;
220584059Swpaul	bge_hostaddr		ifOutDiscards;
220684059Swpaul	bge_hostaddr		ifOutErrors;
2207117659Swpaul};
220884059Swpaul
2209117659Swpaul/* Stats counters access through registers */
2210117659Swpaulstruct bge_mac_stats_regs {
2211159395Sglebius	uint32_t		ifHCOutOctets;
2212159395Sglebius	uint32_t		Reserved0;
2213159395Sglebius	uint32_t		etherStatsCollisions;
2214159395Sglebius	uint32_t		outXonSent;
2215159395Sglebius	uint32_t		outXoffSent;
2216159395Sglebius	uint32_t		Reserved1;
2217159395Sglebius	uint32_t		dot3StatsInternalMacTransmitErrors;
2218159395Sglebius	uint32_t		dot3StatsSingleCollisionFrames;
2219159395Sglebius	uint32_t		dot3StatsMultipleCollisionFrames;
2220159395Sglebius	uint32_t		dot3StatsDeferredTransmissions;
2221159395Sglebius	uint32_t		Reserved2;
2222159395Sglebius	uint32_t		dot3StatsExcessiveCollisions;
2223159395Sglebius	uint32_t		dot3StatsLateCollisions;
2224159395Sglebius	uint32_t		Reserved3[14];
2225159395Sglebius	uint32_t		ifHCOutUcastPkts;
2226159395Sglebius	uint32_t		ifHCOutMulticastPkts;
2227159395Sglebius	uint32_t		ifHCOutBroadcastPkts;
2228159395Sglebius	uint32_t		Reserved4[2];
2229159395Sglebius	uint32_t		ifHCInOctets;
2230159395Sglebius	uint32_t		Reserved5;
2231159395Sglebius	uint32_t		etherStatsFragments;
2232159395Sglebius	uint32_t		ifHCInUcastPkts;
2233159395Sglebius	uint32_t		ifHCInMulticastPkts;
2234159395Sglebius	uint32_t		ifHCInBroadcastPkts;
2235159395Sglebius	uint32_t		dot3StatsFCSErrors;
2236159395Sglebius	uint32_t		dot3StatsAlignmentErrors;
2237159395Sglebius	uint32_t		xonPauseFramesReceived;
2238159395Sglebius	uint32_t		xoffPauseFramesReceived;
2239159395Sglebius	uint32_t		macControlFramesReceived;
2240159395Sglebius	uint32_t		xoffStateEntered;
2241159395Sglebius	uint32_t		dot3StatsFramesTooLong;
2242159395Sglebius	uint32_t		etherStatsJabbers;
2243159395Sglebius	uint32_t		etherStatsUndersizePkts;
2244117659Swpaul};
2245117659Swpaul
2246117659Swpaulstruct bge_stats {
2247159395Sglebius	uint8_t		Reserved0[256];
2248117659Swpaul
2249117659Swpaul	/* Statistics maintained by Receive MAC. */
2250117659Swpaul	struct bge_rx_mac_stats rxstats;
2251117659Swpaul
2252117659Swpaul	bge_hostaddr		Unused1[37];
2253117659Swpaul
2254117659Swpaul	/* Statistics maintained by Transmit MAC. */
2255117659Swpaul	struct bge_tx_mac_stats txstats;
2256117659Swpaul
225784059Swpaul	bge_hostaddr		Unused2[31];
225884059Swpaul
225984059Swpaul	/* Statistics maintained by Receive List Placement. */
226084059Swpaul	bge_hostaddr		COSIfHCInPkts[16];
226184059Swpaul	bge_hostaddr		COSFramesDroppedDueToFilters;
226284059Swpaul	bge_hostaddr		nicDmaWriteQueueFull;
226384059Swpaul	bge_hostaddr		nicDmaWriteHighPriQueueFull;
226484059Swpaul	bge_hostaddr		nicNoMoreRxBDs;
226584059Swpaul	bge_hostaddr		ifInDiscards;
226684059Swpaul	bge_hostaddr		ifInErrors;
226784059Swpaul	bge_hostaddr		nicRecvThresholdHit;
226884059Swpaul
226984059Swpaul	bge_hostaddr		Unused3[9];
227084059Swpaul
227184059Swpaul	/* Statistics maintained by Send Data Initiator. */
227284059Swpaul	bge_hostaddr		COSIfHCOutPkts[16];
227384059Swpaul	bge_hostaddr		nicDmaReadQueueFull;
227484059Swpaul	bge_hostaddr		nicDmaReadHighPriQueueFull;
227584059Swpaul	bge_hostaddr		nicSendDataCompQueueFull;
227684059Swpaul
227784059Swpaul	/* Statistics maintained by Host Coalescing. */
227884059Swpaul	bge_hostaddr		nicRingSetSendProdIndex;
227984059Swpaul	bge_hostaddr		nicRingStatusUpdate;
228084059Swpaul	bge_hostaddr		nicInterrupts;
228184059Swpaul	bge_hostaddr		nicAvoidedInterrupts;
228284059Swpaul	bge_hostaddr		nicSendThresholdHit;
228384059Swpaul
2284159395Sglebius	uint8_t		Reserved4[320];
228584059Swpaul};
228684059Swpaul
228784059Swpaul/*
228884059Swpaul * Tigon general information block. This resides in host memory
228984059Swpaul * and contains the status counters, ring control blocks and
229084059Swpaul * producer pointers.
229184059Swpaul */
229284059Swpaul
229384059Swpaulstruct bge_gib {
229484059Swpaul	struct bge_stats	bge_stats;
229584059Swpaul	struct bge_rcb		bge_tx_rcb[16];
229684059Swpaul	struct bge_rcb		bge_std_rx_rcb;
229784059Swpaul	struct bge_rcb		bge_jumbo_rx_rcb;
229884059Swpaul	struct bge_rcb		bge_mini_rx_rcb;
229984059Swpaul	struct bge_rcb		bge_return_rcb;
230084059Swpaul};
230184059Swpaul
2302166676Sjkim#define	BGE_FRAMELEN		1518
2303166676Sjkim#define	BGE_MAX_FRAMELEN	1536
2304166676Sjkim#define	BGE_JUMBO_FRAMELEN	9018
2305166676Sjkim#define	BGE_JUMBO_MTU		(BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2306166676Sjkim#define	BGE_MIN_FRAMELEN		60
230784059Swpaul
230884059Swpaul/*
230984059Swpaul * Other utility macros.
231084059Swpaul */
2311166676Sjkim#define	BGE_INC(x, y)	(x) = (x + 1) % y
231284059Swpaul
231384059Swpaul/*
231484059Swpaul * Register access macros. The Tigon always uses memory mapped register
231584059Swpaul * accesses and all registers must be accessed with 32 bit operations.
231684059Swpaul */
231784059Swpaul
2318166676Sjkim#define	CSR_WRITE_4(sc, reg, val)	\
231984059Swpaul	bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
232084059Swpaul
2321166676Sjkim#define	CSR_READ_4(sc, reg)		\
232284059Swpaul	bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
232384059Swpaul
2324166676Sjkim#define	BGE_SETBIT(sc, reg, x)	\
2325106696Salfred	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2326166676Sjkim#define	BGE_CLRBIT(sc, reg, x)	\
2327106696Salfred	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
232884059Swpaul
2329166676Sjkim#define	PCI_SETBIT(dev, reg, x, s)	\
2330106696Salfred	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2331166676Sjkim#define	PCI_CLRBIT(dev, reg, x, s)	\
2332106696Salfred	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
233384059Swpaul
233484059Swpaul/*
233584059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
233684059Swpaul * values are tuneable. They control the actual amount of buffers
233784059Swpaul * allocated for the standard, mini and jumbo receive rings.
233884059Swpaul */
233984059Swpaul
2340166676Sjkim#define	BGE_SSLOTS	256
2341166676Sjkim#define	BGE_MSLOTS	256
2342166676Sjkim#define	BGE_JSLOTS	384
234384059Swpaul
2344166676Sjkim#define	BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
2345166676Sjkim#define	BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \
2346159395Sglebius	(BGE_JRAWLEN % sizeof(uint64_t))))
2347166676Sjkim#define	BGE_JPAGESZ PAGE_SIZE
2348166676Sjkim#define	BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
2349166676Sjkim#define	BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
235084059Swpaul
2351166676Sjkim#define	BGE_NSEG_JUMBO	4
2352166676Sjkim#define	BGE_NSEG_NEW 32
2353153239Sglebius
235484059Swpaul/*
235584059Swpaul * Ring structures. Most of these reside in host memory and we tell
235684059Swpaul * the NIC where they are via the ring control blocks. The exceptions
235784059Swpaul * are the tx and command rings, which live in NIC memory and which
235884059Swpaul * we access via the shared memory window.
235984059Swpaul */
2360118026Swpaul
236184059Swpaulstruct bge_ring_data {
2362118026Swpaul	struct bge_rx_bd	*bge_rx_std_ring;
2363118026Swpaul	bus_addr_t		bge_rx_std_ring_paddr;
2364153239Sglebius	struct bge_extrx_bd	*bge_rx_jumbo_ring;
2365118026Swpaul	bus_addr_t		bge_rx_jumbo_ring_paddr;
2366118026Swpaul	struct bge_rx_bd	*bge_rx_return_ring;
2367118026Swpaul	bus_addr_t		bge_rx_return_ring_paddr;
2368118026Swpaul	struct bge_tx_bd	*bge_tx_ring;
2369118026Swpaul	bus_addr_t		bge_tx_ring_paddr;
2370118026Swpaul	struct bge_status_block	*bge_status_block;
2371118026Swpaul	bus_addr_t		bge_status_block_paddr;
2372118026Swpaul	struct bge_stats	*bge_stats;
2373118026Swpaul	bus_addr_t		bge_stats_paddr;
237484059Swpaul	struct bge_gib		bge_info;
237584059Swpaul};
237684059Swpaul
2377166676Sjkim#define	BGE_STD_RX_RING_SZ	\
2378118026Swpaul	(sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2379166676Sjkim#define	BGE_JUMBO_RX_RING_SZ	\
2380153239Sglebius	(sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2381166676Sjkim#define	BGE_TX_RING_SZ		\
2382118026Swpaul	(sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2383166676Sjkim#define	BGE_RX_RTN_RING_SZ(x)	\
2384118026Swpaul	(sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2385118026Swpaul
2386166676Sjkim#define	BGE_STATUS_BLK_SZ	sizeof (struct bge_status_block)
2387118026Swpaul
2388166676Sjkim#define	BGE_STATS_SZ		sizeof (struct bge_stats)
2389118026Swpaul
239084059Swpaul/*
239184059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses
239284059Swpaul * of our mbuf chains since we can only convert from physical to virtual,
239384059Swpaul * not the other way around.
239484059Swpaul */
239584059Swpaulstruct bge_chain_data {
2396118026Swpaul	bus_dma_tag_t		bge_parent_tag;
2397118026Swpaul	bus_dma_tag_t		bge_rx_std_ring_tag;
2398118026Swpaul	bus_dma_tag_t		bge_rx_jumbo_ring_tag;
2399118026Swpaul	bus_dma_tag_t		bge_rx_return_ring_tag;
2400118026Swpaul	bus_dma_tag_t		bge_tx_ring_tag;
2401118026Swpaul	bus_dma_tag_t		bge_status_tag;
2402118026Swpaul	bus_dma_tag_t		bge_stats_tag;
2403118026Swpaul	bus_dma_tag_t		bge_mtag;	/* mbuf mapping tag */
2404118026Swpaul	bus_dma_tag_t		bge_mtag_jumbo;	/* mbuf mapping tag */
2405118026Swpaul	bus_dmamap_t		bge_tx_dmamap[BGE_TX_RING_CNT];
2406118026Swpaul	bus_dmamap_t		bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2407118026Swpaul	bus_dmamap_t		bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2408118026Swpaul	bus_dmamap_t		bge_rx_std_ring_map;
2409118026Swpaul	bus_dmamap_t		bge_rx_jumbo_ring_map;
2410118026Swpaul	bus_dmamap_t		bge_tx_ring_map;
2411118026Swpaul	bus_dmamap_t		bge_rx_return_ring_map;
2412118026Swpaul	bus_dmamap_t		bge_status_map;
2413118026Swpaul	bus_dmamap_t		bge_stats_map;
241484059Swpaul	struct mbuf		*bge_tx_chain[BGE_TX_RING_CNT];
241584059Swpaul	struct mbuf		*bge_rx_std_chain[BGE_STD_RX_RING_CNT];
241684059Swpaul	struct mbuf		*bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
241784059Swpaul};
241884059Swpaul
2419118026Swpaulstruct bge_dmamap_arg {
2420118026Swpaul	struct bge_softc	*sc;
2421118026Swpaul	bus_addr_t		bge_busaddr;
2422159395Sglebius	uint16_t		bge_flags;
2423118026Swpaul	int			bge_idx;
2424118026Swpaul	int			bge_maxsegs;
2425118026Swpaul	struct bge_tx_bd	*bge_ring;
2426118026Swpaul};
2427118026Swpaul
2428166676Sjkim#define	BGE_HWREV_TIGON		0x01
2429166676Sjkim#define	BGE_HWREV_TIGON_II	0x02
2430166676Sjkim#define	BGE_TIMEOUT		100000
2431166676Sjkim#define	BGE_TXCONS_UNSET		0xFFFF	/* impossible value */
243284059Swpaul
243384059Swpaulstruct bge_bcom_hack {
243484059Swpaul	int			reg;
243584059Swpaul	int			val;
243684059Swpaul};
243784059Swpaul
2438166676Sjkim#define	ASF_ENABLE		1
2439166676Sjkim#define	ASF_NEW_HANDSHAKE	2
2440166676Sjkim#define	ASF_STACKUP		4
2441162169Sambrisko
244284059Swpaulstruct bge_softc {
2443147256Sbrooks	struct ifnet		*bge_ifp;	/* interface info */
244484059Swpaul	device_t		bge_dev;
2445122497Ssam	struct mtx		bge_mtx;
244684059Swpaul	device_t		bge_miibus;
244784059Swpaul	bus_space_handle_t	bge_bhandle;
244884059Swpaul	bus_space_tag_t		bge_btag;
244984059Swpaul	void			*bge_intrhand;
245084059Swpaul	struct resource		*bge_irq;
245184059Swpaul	struct resource		*bge_res;
245284059Swpaul	struct ifmedia		bge_ifmedia;	/* TBI media info */
2453161546Sglebius	uint32_t		bge_flags;
2454166676Sjkim#define	BGE_FLAG_TBI		0x00000001
2455166676Sjkim#define	BGE_FLAG_JUMBO		0x00000002
2456166676Sjkim#define	BGE_FLAG_MSI		0x00000100
2457166676Sjkim#define	BGE_FLAG_PCIX		0x00000200
2458166676Sjkim#define	BGE_FLAG_PCIE		0x00000400
2459166676Sjkim#define	BGE_FLAG_5700_FAMILY	0x00001000
2460166676Sjkim#define	BGE_FLAG_5705_PLUS	0x00002000
2461166676Sjkim#define	BGE_FLAG_5714_FAMILY	0x00004000
2462166676Sjkim#define	BGE_FLAG_575X_PLUS	0x00008000
2463166676Sjkim#define	BGE_FLAG_RX_ALIGNBUG	0x00100000
2464166676Sjkim#define	BGE_FLAG_NO_3LED	0x00200000
2465166676Sjkim#define	BGE_FLAG_ADC_BUG	0x00400000
2466166676Sjkim#define	BGE_FLAG_5704_A0_BUG	0x00800000
2467166676Sjkim#define	BGE_FLAG_JITTER_BUG	0x01000000
2468166676Sjkim#define	BGE_FLAG_BER_BUG	0x02000000
2469166676Sjkim#define	BGE_FLAG_ADJUST_TRIM	0x04000000
2470166677Sjkim#define	BGE_FLAG_CRC_BUG	0x08000000
2471159395Sglebius	uint32_t		bge_chipid;
2472162169Sambrisko	uint8_t			bge_asicrev;
2473162169Sambrisko	uint8_t			bge_chiprev;
2474162169Sambrisko	uint8_t			bge_asf_mode;
2475162169Sambrisko	uint8_t			bge_asf_count;
2476118026Swpaul	struct bge_ring_data	bge_ldata;	/* rings */
247784059Swpaul	struct bge_chain_data	bge_cdata;	/* mbufs */
2478159395Sglebius	uint16_t		bge_tx_saved_considx;
2479159395Sglebius	uint16_t		bge_rx_saved_considx;
2480159395Sglebius	uint16_t		bge_ev_saved_considx;
2481159395Sglebius	uint16_t		bge_return_ring_cnt;
2482159395Sglebius	uint16_t		bge_std;	/* current std ring head */
2483159395Sglebius	uint16_t		bge_jumbo;	/* current jumo ring head */
2484159395Sglebius	uint32_t		bge_stat_ticks;
2485159395Sglebius	uint32_t		bge_rx_coal_ticks;
2486159395Sglebius	uint32_t		bge_tx_coal_ticks;
2487159395Sglebius	uint32_t		bge_tx_prodidx;
2488159395Sglebius	uint32_t		bge_rx_max_coal_bds;
2489159395Sglebius	uint32_t		bge_tx_max_coal_bds;
2490159395Sglebius	uint32_t		bge_tx_buf_ratio;
249184059Swpaul	int			bge_if_flags;
249284059Swpaul	int			bge_txcnt;
2493155180Soleg	int			bge_link;	/* link state */
2494155180Soleg	int			bge_link_evt;	/* pending link event */
2495164769Sglebius	int			bge_timer;
2496122497Ssam	struct callout		bge_stat_ch;
2497164780Sjkim	uint32_t		bge_rx_discards;
2498164780Sjkim	uint32_t		bge_tx_discards;
2499164780Sjkim	uint32_t		bge_tx_collisions;
2500151553Sglebius#ifdef DEVICE_POLLING
2501151553Sglebius	int			rxcycles;
2502151553Sglebius#endif /* DEVICE_POLLING */
250384059Swpaul};
2504122497Ssam
2505122497Ssam#define	BGE_LOCK_INIT(_sc, _name) \
2506122497Ssam	mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
2507122497Ssam#define	BGE_LOCK(_sc)		mtx_lock(&(_sc)->bge_mtx)
2508122497Ssam#define	BGE_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
2509122497Ssam#define	BGE_UNLOCK(_sc)		mtx_unlock(&(_sc)->bge_mtx)
2510122497Ssam#define	BGE_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->bge_mtx)
2511