if_bgereg.h revision 159637
1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 159637 2006-06-15 14:31:49Z glebius $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 6484059Swpaul#define BGE_PAGE_ZERO 0x00000000 6584059Swpaul#define BGE_PAGE_ZERO_END 0x000000FF 6684059Swpaul#define BGE_SEND_RING_RCB 0x00000100 6784059Swpaul#define BGE_SEND_RING_RCB_END 0x000001FF 6884059Swpaul#define BGE_RX_RETURN_RING_RCB 0x00000200 6984059Swpaul#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 7084059Swpaul#define BGE_STATS_BLOCK 0x00000300 7184059Swpaul#define BGE_STATS_BLOCK_END 0x00000AFF 7284059Swpaul#define BGE_STATUS_BLOCK 0x00000B00 7384059Swpaul#define BGE_STATUS_BLOCK_END 0x00000B4F 7484059Swpaul#define BGE_SOFTWARE_GENCOMM 0x00000B50 75110367Sps#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76110367Sps#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 7784059Swpaul#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 7884059Swpaul#define BGE_UNMAPPED 0x00001000 7984059Swpaul#define BGE_UNMAPPED_END 0x00001FFF 8084059Swpaul#define BGE_DMA_DESCRIPTORS 0x00002000 8184059Swpaul#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 8284059Swpaul#define BGE_SEND_RING_1_TO_4 0x00004000 8384059Swpaul#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8484059Swpaul 8584059Swpaul/* Mappings for internal memory configuration */ 8684059Swpaul#define BGE_STD_RX_RINGS 0x00006000 8784059Swpaul#define BGE_STD_RX_RINGS_END 0x00006FFF 8884059Swpaul#define BGE_JUMBO_RX_RINGS 0x00007000 8984059Swpaul#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 9084059Swpaul#define BGE_BUFFPOOL_1 0x00008000 9184059Swpaul#define BGE_BUFFPOOL_1_END 0x0000FFFF 9284059Swpaul#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 9384059Swpaul#define BGE_BUFFPOOL_2_END 0x00017FFF 9484059Swpaul#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 9584059Swpaul#define BGE_BUFFPOOL_3_END 0x0001FFFF 9684059Swpaul 9784059Swpaul/* Mappings for external SSRAM configurations */ 9884059Swpaul#define BGE_SEND_RING_5_TO_6 0x00006000 9984059Swpaul#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 10084059Swpaul#define BGE_SEND_RING_7_TO_8 0x00007000 10184059Swpaul#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 10284059Swpaul#define BGE_SEND_RING_9_TO_16 0x00008000 10384059Swpaul#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 10484059Swpaul#define BGE_EXT_STD_RX_RINGS 0x0000C000 10584059Swpaul#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 10684059Swpaul#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 10784059Swpaul#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 10884059Swpaul#define BGE_MINI_RX_RINGS 0x0000E000 10984059Swpaul#define BGE_MINI_RX_RINGS_END 0x0000FFFF 11084059Swpaul#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 11184059Swpaul#define BGE_AVAIL_REGION1_END 0x00017FFF 11284059Swpaul#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 11384059Swpaul#define BGE_AVAIL_REGION2_END 0x0001FFFF 11484059Swpaul#define BGE_EXT_SSRAM 0x00020000 11584059Swpaul#define BGE_EXT_SSRAM_END 0x000FFFFF 11684059Swpaul 11784059Swpaul 11884059Swpaul/* 11984059Swpaul * BCM570x register offsets. These are memory mapped registers 12084059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12184059Swpaul * Each register must be accessed using 32 bit operations. 12284059Swpaul * 12384059Swpaul * All registers are accessed through a 32K shared memory block. 12484059Swpaul * The first group of registers are actually copies of the PCI 12584059Swpaul * configuration space registers. 12684059Swpaul */ 12784059Swpaul 12884059Swpaul/* 12984059Swpaul * PCI registers defined in the PCI 2.2 spec. 13084059Swpaul */ 13184059Swpaul#define BGE_PCI_VID 0x00 13284059Swpaul#define BGE_PCI_DID 0x02 13384059Swpaul#define BGE_PCI_CMD 0x04 13484059Swpaul#define BGE_PCI_STS 0x06 13584059Swpaul#define BGE_PCI_REV 0x08 13684059Swpaul#define BGE_PCI_CLASS 0x09 13784059Swpaul#define BGE_PCI_CACHESZ 0x0C 13884059Swpaul#define BGE_PCI_LATTIMER 0x0D 13984059Swpaul#define BGE_PCI_HDRTYPE 0x0E 14084059Swpaul#define BGE_PCI_BIST 0x0F 14184059Swpaul#define BGE_PCI_BAR0 0x10 14284059Swpaul#define BGE_PCI_BAR1 0x14 14384059Swpaul#define BGE_PCI_SUBSYS 0x2C 14484059Swpaul#define BGE_PCI_SUBVID 0x2E 14584059Swpaul#define BGE_PCI_ROMBASE 0x30 14684059Swpaul#define BGE_PCI_CAPPTR 0x34 14784059Swpaul#define BGE_PCI_INTLINE 0x3C 14884059Swpaul#define BGE_PCI_INTPIN 0x3D 14984059Swpaul#define BGE_PCI_MINGNT 0x3E 15084059Swpaul#define BGE_PCI_MAXLAT 0x3F 15184059Swpaul#define BGE_PCI_PCIXCAP 0x40 15284059Swpaul#define BGE_PCI_NEXTPTR_PM 0x41 15384059Swpaul#define BGE_PCI_PCIX_CMD 0x42 15484059Swpaul#define BGE_PCI_PCIX_STS 0x44 15584059Swpaul#define BGE_PCI_PWRMGMT_CAPID 0x48 15684059Swpaul#define BGE_PCI_NEXTPTR_VPD 0x49 15784059Swpaul#define BGE_PCI_PWRMGMT_CAPS 0x4A 15884059Swpaul#define BGE_PCI_PWRMGMT_CMD 0x4C 15984059Swpaul#define BGE_PCI_PWRMGMT_STS 0x4D 16084059Swpaul#define BGE_PCI_PWRMGMT_DATA 0x4F 16184059Swpaul#define BGE_PCI_VPD_CAPID 0x50 16284059Swpaul#define BGE_PCI_NEXTPTR_MSI 0x51 16384059Swpaul#define BGE_PCI_VPD_ADDR 0x52 16484059Swpaul#define BGE_PCI_VPD_DATA 0x54 16584059Swpaul#define BGE_PCI_MSI_CAPID 0x58 16684059Swpaul#define BGE_PCI_NEXTPTR_NONE 0x59 16784059Swpaul#define BGE_PCI_MSI_CTL 0x5A 16884059Swpaul#define BGE_PCI_MSI_ADDR_HI 0x5C 16984059Swpaul#define BGE_PCI_MSI_ADDR_LO 0x60 17084059Swpaul#define BGE_PCI_MSI_DATA 0x64 17184059Swpaul 172135772Sps/* PCI MSI. ??? */ 173135772Sps#define BGE_PCIE_CAPID_REG 0xD0 174135772Sps#define BGE_PCIE_CAPID 0x10 175135772Sps 17684059Swpaul/* 17784059Swpaul * PCI registers specific to the BCM570x family. 17884059Swpaul */ 17984059Swpaul#define BGE_PCI_MISC_CTL 0x68 18084059Swpaul#define BGE_PCI_DMA_RW_CTL 0x6C 18184059Swpaul#define BGE_PCI_PCISTATE 0x70 18284059Swpaul#define BGE_PCI_CLKCTL 0x74 18384059Swpaul#define BGE_PCI_REG_BASEADDR 0x78 18484059Swpaul#define BGE_PCI_MEMWIN_BASEADDR 0x7C 18584059Swpaul#define BGE_PCI_REG_DATA 0x80 18684059Swpaul#define BGE_PCI_MEMWIN_DATA 0x84 18784059Swpaul#define BGE_PCI_MODECTL 0x88 18884059Swpaul#define BGE_PCI_MISC_CFG 0x8C 18984059Swpaul#define BGE_PCI_MISC_LOCALCTL 0x90 19084059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 19184059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 19284059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 19384059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 19484059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 19584059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 19684059Swpaul#define BGE_PCI_ISR_MBX_HI 0xB0 19784059Swpaul#define BGE_PCI_ISR_MBX_LO 0xB4 19884059Swpaul 19984059Swpaul/* PCI Misc. Host control register */ 20084059Swpaul#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 20184059Swpaul#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 20284059Swpaul#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 20384059Swpaul#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 20484059Swpaul#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 20584059Swpaul#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 20684059Swpaul#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 20784059Swpaul#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 20884059Swpaul#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 20984059Swpaul 210153437Syongari#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 211153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 212153437Syongari#define BGE_DMA_SWAP_OPTIONS \ 213153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME| \ 214153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 215153437Syongari#else 216153437Syongari#define BGE_DMA_SWAP_OPTIONS \ 217153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 218153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 219153437Syongari#endif 22084059Swpaul 221153437Syongari#define BGE_INIT \ 222153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 223153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 22484059Swpaul 225114813Sps#define BGE_CHIPID_TIGON_I 0x40000000 226114813Sps#define BGE_CHIPID_TIGON_II 0x60000000 227159637Sglebius#define BGE_CHIPID_BCM5700_A0 0x70000000 228159637Sglebius#define BGE_CHIPID_BCM5700_A1 0x70010000 229114813Sps#define BGE_CHIPID_BCM5700_B0 0x71000000 230159637Sglebius#define BGE_CHIPID_BCM5700_B1 0x71010000 231159637Sglebius#define BGE_CHIPID_BCM5700_B2 0x71020000 232159637Sglebius#define BGE_CHIPID_BCM5700_B3 0x71030000 233114813Sps#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 234114813Sps#define BGE_CHIPID_BCM5700_C0 0x72000000 235114813Sps#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 236114813Sps#define BGE_CHIPID_BCM5701_B0 0x01000000 237114813Sps#define BGE_CHIPID_BCM5701_B2 0x01020000 238114813Sps#define BGE_CHIPID_BCM5701_B5 0x01050000 239114813Sps#define BGE_CHIPID_BCM5703_A0 0x10000000 240114813Sps#define BGE_CHIPID_BCM5703_A1 0x10010000 241114813Sps#define BGE_CHIPID_BCM5703_A2 0x10020000 242159637Sglebius#define BGE_CHIPID_BCM5703_A3 0x10030000 243114813Sps#define BGE_CHIPID_BCM5704_A0 0x20000000 244114813Sps#define BGE_CHIPID_BCM5704_A1 0x20010000 245114813Sps#define BGE_CHIPID_BCM5704_A2 0x20020000 246159637Sglebius#define BGE_CHIPID_BCM5704_A3 0x20030000 247159637Sglebius#define BGE_CHIPID_BCM5704_B0 0x21000000 248117659Swpaul#define BGE_CHIPID_BCM5705_A0 0x30000000 249117659Swpaul#define BGE_CHIPID_BCM5705_A1 0x30010000 250117659Swpaul#define BGE_CHIPID_BCM5705_A2 0x30020000 251117659Swpaul#define BGE_CHIPID_BCM5705_A3 0x30030000 252135772Sps#define BGE_CHIPID_BCM5750_A0 0x40000000 253135772Sps#define BGE_CHIPID_BCM5750_A1 0x40010000 254159637Sglebius#define BGE_CHIPID_BCM5750_A3 0x40030000 255159637Sglebius#define BGE_CHIPID_BCM5750_B0 0x40100000 256159637Sglebius#define BGE_CHIPID_BCM5750_B1 0x41010000 257159637Sglebius#define BGE_CHIPID_BCM5750_C0 0x42000000 258159637Sglebius#define BGE_CHIPID_BCM5750_C1 0x42010000 259146413Sps#define BGE_CHIPID_BCM5714_A0 0x50000000 260159637Sglebius#define BGE_CHIPID_BCM5752_A0 0x60000000 261159637Sglebius#define BGE_CHIPID_BCM5752_A1 0x60010000 262159637Sglebius#define BGE_CHIPID_BCM5752_A2 0x60020000 263159637Sglebius#define BGE_CHIPID_BCM5714_B0 0x80000000 264159637Sglebius#define BGE_CHIPID_BCM5714_B3 0x80030000 265159637Sglebius#define BGE_CHIPID_BCM5715_A0 0x90000000 266159637Sglebius#define BGE_CHIPID_BCM5715_A1 0x90010000 26784059Swpaul 26893751Swpaul/* shorthand one */ 269114615Sps#define BGE_ASICREV(x) ((x) >> 28) 270114615Sps#define BGE_ASICREV_BCM5701 0x00 271114615Sps#define BGE_ASICREV_BCM5703 0x01 272114615Sps#define BGE_ASICREV_BCM5704 0x02 273117659Swpaul#define BGE_ASICREV_BCM5705 0x03 274135772Sps#define BGE_ASICREV_BCM5750 0x04 275159637Sglebius#define BGE_ASICREV_BCM5714_A0 0x05 276152452Sglebius#define BGE_ASICREV_BCM5752 0x06 277159637Sglebius#define BGE_ASICREV_BCM5700 0x07 278159637Sglebius#define BGE_ASICREV_BCM5780 0x08 279159637Sglebius#define BGE_ASICREV_BCM5714 0x09 28093751Swpaul 281114813Sps/* chip revisions */ 282114813Sps#define BGE_CHIPREV(x) ((x) >> 24) 283114813Sps#define BGE_CHIPREV_5700_AX 0x70 284114813Sps#define BGE_CHIPREV_5700_BX 0x71 285114813Sps#define BGE_CHIPREV_5700_CX 0x72 286114813Sps#define BGE_CHIPREV_5701_AX 0x00 287114813Sps 28884059Swpaul/* PCI DMA Read/Write Control register */ 28984059Swpaul#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 29084059Swpaul#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 29184059Swpaul#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 29284059Swpaul#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 29384059Swpaul#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 294114615Sps# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 29584059Swpaul#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 296114615Sps# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 29784059Swpaul#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 29884059Swpaul#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 29984059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 300114615Sps# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 30184059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 302114615Sps# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 30384059Swpaul 30484059Swpaul#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 30584059Swpaul#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 30684059Swpaul#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 30784059Swpaul#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 30884059Swpaul#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 30984059Swpaul#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 31084059Swpaul#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 31184059Swpaul#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 31284059Swpaul 31384059Swpaul#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 31484059Swpaul#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 31584059Swpaul#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 31684059Swpaul#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 31784059Swpaul#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 31884059Swpaul#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 31984059Swpaul#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 32084059Swpaul#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 32184059Swpaul 32284059Swpaul/* 32384059Swpaul * PCI state register -- note, this register is read only 32484059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 32584059Swpaul * register is set. 32684059Swpaul */ 32784059Swpaul#define BGE_PCISTATE_FORCE_RESET 0x00000001 32884059Swpaul#define BGE_PCISTATE_INTR_STATE 0x00000002 32984059Swpaul#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 33084059Swpaul#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 33184059Swpaul#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 33284059Swpaul#define BGE_PCISTATE_WANT_EXPROM 0x00000020 33384059Swpaul#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 33484059Swpaul#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 33584059Swpaul#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 33684059Swpaul 33784059Swpaul/* 33884059Swpaul * PCI Clock Control register -- note, this register is read only 33984059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 34084059Swpaul * register is set. 34184059Swpaul */ 34284059Swpaul#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 34384059Swpaul#define BGE_PCICLOCKCTL_M66EN 0x00000080 34484059Swpaul#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 34584059Swpaul#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 34684059Swpaul#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 34784059Swpaul#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 34884059Swpaul#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 34984059Swpaul#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 35084059Swpaul#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 35184059Swpaul#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 35284059Swpaul 35384059Swpaul 35484059Swpaul#ifndef PCIM_CMD_MWIEN 35584059Swpaul#define PCIM_CMD_MWIEN 0x0010 35684059Swpaul#endif 35784059Swpaul 35884059Swpaul/* 35984059Swpaul * High priority mailbox registers 36084059Swpaul * Each mailbox is 64-bits wide, though we only use the 36184059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 36284059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 36384059Swpaul * has been updated. 36484059Swpaul */ 36584059Swpaul#define BGE_MBX_IRQ0_HI 0x0200 36684059Swpaul#define BGE_MBX_IRQ0_LO 0x0204 36784059Swpaul#define BGE_MBX_IRQ1_HI 0x0208 36884059Swpaul#define BGE_MBX_IRQ1_LO 0x020C 36984059Swpaul#define BGE_MBX_IRQ2_HI 0x0210 37084059Swpaul#define BGE_MBX_IRQ2_LO 0x0214 37184059Swpaul#define BGE_MBX_IRQ3_HI 0x0218 37284059Swpaul#define BGE_MBX_IRQ3_LO 0x021C 37384059Swpaul#define BGE_MBX_GEN0_HI 0x0220 37484059Swpaul#define BGE_MBX_GEN0_LO 0x0224 37584059Swpaul#define BGE_MBX_GEN1_HI 0x0228 37684059Swpaul#define BGE_MBX_GEN1_LO 0x022C 37784059Swpaul#define BGE_MBX_GEN2_HI 0x0230 37884059Swpaul#define BGE_MBX_GEN2_LO 0x0234 37984059Swpaul#define BGE_MBX_GEN3_HI 0x0228 38084059Swpaul#define BGE_MBX_GEN3_LO 0x022C 38184059Swpaul#define BGE_MBX_GEN4_HI 0x0240 38284059Swpaul#define BGE_MBX_GEN4_LO 0x0244 38384059Swpaul#define BGE_MBX_GEN5_HI 0x0248 38484059Swpaul#define BGE_MBX_GEN5_LO 0x024C 38584059Swpaul#define BGE_MBX_GEN6_HI 0x0250 38684059Swpaul#define BGE_MBX_GEN6_LO 0x0254 38784059Swpaul#define BGE_MBX_GEN7_HI 0x0258 38884059Swpaul#define BGE_MBX_GEN7_LO 0x025C 38984059Swpaul#define BGE_MBX_RELOAD_STATS_HI 0x0260 39084059Swpaul#define BGE_MBX_RELOAD_STATS_LO 0x0264 39184059Swpaul#define BGE_MBX_RX_STD_PROD_HI 0x0268 39284059Swpaul#define BGE_MBX_RX_STD_PROD_LO 0x026C 39384059Swpaul#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 39484059Swpaul#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 39584059Swpaul#define BGE_MBX_RX_MINI_PROD_HI 0x0278 39684059Swpaul#define BGE_MBX_RX_MINI_PROD_LO 0x027C 39784059Swpaul#define BGE_MBX_RX_CONS0_HI 0x0280 39884059Swpaul#define BGE_MBX_RX_CONS0_LO 0x0284 39984059Swpaul#define BGE_MBX_RX_CONS1_HI 0x0288 40084059Swpaul#define BGE_MBX_RX_CONS1_LO 0x028C 40184059Swpaul#define BGE_MBX_RX_CONS2_HI 0x0290 40284059Swpaul#define BGE_MBX_RX_CONS2_LO 0x0294 40384059Swpaul#define BGE_MBX_RX_CONS3_HI 0x0298 40484059Swpaul#define BGE_MBX_RX_CONS3_LO 0x029C 40584059Swpaul#define BGE_MBX_RX_CONS4_HI 0x02A0 40684059Swpaul#define BGE_MBX_RX_CONS4_LO 0x02A4 40784059Swpaul#define BGE_MBX_RX_CONS5_HI 0x02A8 40884059Swpaul#define BGE_MBX_RX_CONS5_LO 0x02AC 40984059Swpaul#define BGE_MBX_RX_CONS6_HI 0x02B0 41084059Swpaul#define BGE_MBX_RX_CONS6_LO 0x02B4 41184059Swpaul#define BGE_MBX_RX_CONS7_HI 0x02B8 41284059Swpaul#define BGE_MBX_RX_CONS7_LO 0x02BC 41384059Swpaul#define BGE_MBX_RX_CONS8_HI 0x02C0 41484059Swpaul#define BGE_MBX_RX_CONS8_LO 0x02C4 41584059Swpaul#define BGE_MBX_RX_CONS9_HI 0x02C8 41684059Swpaul#define BGE_MBX_RX_CONS9_LO 0x02CC 41784059Swpaul#define BGE_MBX_RX_CONS10_HI 0x02D0 41884059Swpaul#define BGE_MBX_RX_CONS10_LO 0x02D4 41984059Swpaul#define BGE_MBX_RX_CONS11_HI 0x02D8 42084059Swpaul#define BGE_MBX_RX_CONS11_LO 0x02DC 42184059Swpaul#define BGE_MBX_RX_CONS12_HI 0x02E0 42284059Swpaul#define BGE_MBX_RX_CONS12_LO 0x02E4 42384059Swpaul#define BGE_MBX_RX_CONS13_HI 0x02E8 42484059Swpaul#define BGE_MBX_RX_CONS13_LO 0x02EC 42584059Swpaul#define BGE_MBX_RX_CONS14_HI 0x02F0 42684059Swpaul#define BGE_MBX_RX_CONS14_LO 0x02F4 42784059Swpaul#define BGE_MBX_RX_CONS15_HI 0x02F8 42884059Swpaul#define BGE_MBX_RX_CONS15_LO 0x02FC 42984059Swpaul#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 43084059Swpaul#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 43184059Swpaul#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 43284059Swpaul#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 43384059Swpaul#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 43484059Swpaul#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 43584059Swpaul#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 43684059Swpaul#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 43784059Swpaul#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 43884059Swpaul#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 43984059Swpaul#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 44084059Swpaul#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 44184059Swpaul#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 44284059Swpaul#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 44384059Swpaul#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 44484059Swpaul#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 44584059Swpaul#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 44684059Swpaul#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 44784059Swpaul#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 44884059Swpaul#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 44984059Swpaul#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 45084059Swpaul#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 45184059Swpaul#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 45284059Swpaul#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 45384059Swpaul#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 45484059Swpaul#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 45584059Swpaul#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 45684059Swpaul#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 45784059Swpaul#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 45884059Swpaul#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 45984059Swpaul#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 46084059Swpaul#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 46184059Swpaul#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 46284059Swpaul#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 46384059Swpaul#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 46484059Swpaul#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 46584059Swpaul#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 46684059Swpaul#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 46784059Swpaul#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 46884059Swpaul#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 46984059Swpaul#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 47084059Swpaul#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 47184059Swpaul#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 47284059Swpaul#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 47384059Swpaul#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 47484059Swpaul#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 47584059Swpaul#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 47684059Swpaul#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 47784059Swpaul#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 47884059Swpaul#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 47984059Swpaul#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 48084059Swpaul#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 48184059Swpaul#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 48284059Swpaul#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 48384059Swpaul#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 48484059Swpaul#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 48584059Swpaul#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 48684059Swpaul#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 48784059Swpaul#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 48884059Swpaul#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 48984059Swpaul#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 49084059Swpaul#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 49184059Swpaul#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 49284059Swpaul#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 49384059Swpaul 49484059Swpaul#define BGE_TX_RINGS_MAX 4 49584059Swpaul#define BGE_TX_RINGS_EXTSSRAM_MAX 16 49684059Swpaul#define BGE_RX_RINGS_MAX 16 49784059Swpaul 49884059Swpaul/* Ethernet MAC control registers */ 49984059Swpaul#define BGE_MAC_MODE 0x0400 50084059Swpaul#define BGE_MAC_STS 0x0404 50184059Swpaul#define BGE_MAC_EVT_ENB 0x0408 50284059Swpaul#define BGE_MAC_LED_CTL 0x040C 50384059Swpaul#define BGE_MAC_ADDR1_LO 0x0410 50484059Swpaul#define BGE_MAC_ADDR1_HI 0x0414 50584059Swpaul#define BGE_MAC_ADDR2_LO 0x0418 50684059Swpaul#define BGE_MAC_ADDR2_HI 0x041C 50784059Swpaul#define BGE_MAC_ADDR3_LO 0x0420 50884059Swpaul#define BGE_MAC_ADDR3_HI 0x0424 50984059Swpaul#define BGE_MAC_ADDR4_LO 0x0428 51084059Swpaul#define BGE_MAC_ADDR4_HI 0x042C 51184059Swpaul#define BGE_WOL_PATPTR 0x0430 51284059Swpaul#define BGE_WOL_PATCFG 0x0434 51384059Swpaul#define BGE_TX_RANDOM_BACKOFF 0x0438 51484059Swpaul#define BGE_RX_MTU 0x043C 51584059Swpaul#define BGE_GBIT_PCS_TEST 0x0440 51684059Swpaul#define BGE_TX_TBI_AUTONEG 0x0444 51784059Swpaul#define BGE_RX_TBI_AUTONEG 0x0448 51884059Swpaul#define BGE_MI_COMM 0x044C 51984059Swpaul#define BGE_MI_STS 0x0450 52084059Swpaul#define BGE_MI_MODE 0x0454 52184059Swpaul#define BGE_AUTOPOLL_STS 0x0458 52284059Swpaul#define BGE_TX_MODE 0x045C 52384059Swpaul#define BGE_TX_STS 0x0460 52484059Swpaul#define BGE_TX_LENGTHS 0x0464 52584059Swpaul#define BGE_RX_MODE 0x0468 52684059Swpaul#define BGE_RX_STS 0x046C 52784059Swpaul#define BGE_MAR0 0x0470 52884059Swpaul#define BGE_MAR1 0x0474 52984059Swpaul#define BGE_MAR2 0x0478 53084059Swpaul#define BGE_MAR3 0x047C 53184059Swpaul#define BGE_RX_BD_RULES_CTL0 0x0480 53284059Swpaul#define BGE_RX_BD_RULES_MASKVAL0 0x0484 53384059Swpaul#define BGE_RX_BD_RULES_CTL1 0x0488 53484059Swpaul#define BGE_RX_BD_RULES_MASKVAL1 0x048C 53584059Swpaul#define BGE_RX_BD_RULES_CTL2 0x0490 53684059Swpaul#define BGE_RX_BD_RULES_MASKVAL2 0x0494 53784059Swpaul#define BGE_RX_BD_RULES_CTL3 0x0498 53884059Swpaul#define BGE_RX_BD_RULES_MASKVAL3 0x049C 53984059Swpaul#define BGE_RX_BD_RULES_CTL4 0x04A0 54084059Swpaul#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 54184059Swpaul#define BGE_RX_BD_RULES_CTL5 0x04A8 54284059Swpaul#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 54384059Swpaul#define BGE_RX_BD_RULES_CTL6 0x04B0 54484059Swpaul#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 54584059Swpaul#define BGE_RX_BD_RULES_CTL7 0x04B8 54684059Swpaul#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 54784059Swpaul#define BGE_RX_BD_RULES_CTL8 0x04C0 54884059Swpaul#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 54984059Swpaul#define BGE_RX_BD_RULES_CTL9 0x04C8 55084059Swpaul#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 55184059Swpaul#define BGE_RX_BD_RULES_CTL10 0x04D0 55284059Swpaul#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 55384059Swpaul#define BGE_RX_BD_RULES_CTL11 0x04D8 55484059Swpaul#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 55584059Swpaul#define BGE_RX_BD_RULES_CTL12 0x04E0 55684059Swpaul#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 55784059Swpaul#define BGE_RX_BD_RULES_CTL13 0x04E8 55884059Swpaul#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 55984059Swpaul#define BGE_RX_BD_RULES_CTL14 0x04F0 56084059Swpaul#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 56184059Swpaul#define BGE_RX_BD_RULES_CTL15 0x04F8 56284059Swpaul#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 56384059Swpaul#define BGE_RX_RULES_CFG 0x0500 564130273Swpaul#define BGE_SERDES_CFG 0x0590 565130273Swpaul#define BGE_SERDES_STS 0x0594 566130273Swpaul#define BGE_SGDIG_CFG 0x05B0 567130273Swpaul#define BGE_SGDIG_STS 0x05B4 56884059Swpaul#define BGE_RX_STATS 0x0800 56984059Swpaul#define BGE_TX_STATS 0x0880 57084059Swpaul 57184059Swpaul/* Ethernet MAC Mode register */ 57284059Swpaul#define BGE_MACMODE_RESET 0x00000001 57384059Swpaul#define BGE_MACMODE_HALF_DUPLEX 0x00000002 57484059Swpaul#define BGE_MACMODE_PORTMODE 0x0000000C 57584059Swpaul#define BGE_MACMODE_LOOPBACK 0x00000010 57684059Swpaul#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 57784059Swpaul#define BGE_MACMODE_TX_BURST_ENB 0x00000100 57884059Swpaul#define BGE_MACMODE_MAX_DEFER 0x00000200 57984059Swpaul#define BGE_MACMODE_LINK_POLARITY 0x00000400 58084059Swpaul#define BGE_MACMODE_RX_STATS_ENB 0x00000800 58184059Swpaul#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 58284059Swpaul#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 58384059Swpaul#define BGE_MACMODE_TX_STATS_ENB 0x00004000 58484059Swpaul#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 58584059Swpaul#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 58684059Swpaul#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 58784059Swpaul#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 58884059Swpaul#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 58984059Swpaul#define BGE_MACMODE_MIP_ENB 0x00100000 59084059Swpaul#define BGE_MACMODE_TXDMA_ENB 0x00200000 59184059Swpaul#define BGE_MACMODE_RXDMA_ENB 0x00400000 59284059Swpaul#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 59384059Swpaul 59484059Swpaul#define BGE_PORTMODE_NONE 0x00000000 59584059Swpaul#define BGE_PORTMODE_MII 0x00000004 59684059Swpaul#define BGE_PORTMODE_GMII 0x00000008 59784059Swpaul#define BGE_PORTMODE_TBI 0x0000000C 59884059Swpaul 59984059Swpaul/* MAC Status register */ 60084059Swpaul#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 60184059Swpaul#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 60284059Swpaul#define BGE_MACSTAT_RX_CFG 0x00000004 60384059Swpaul#define BGE_MACSTAT_CFG_CHANGED 0x00000008 60484059Swpaul#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 60584059Swpaul#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 60684059Swpaul#define BGE_MACSTAT_LINK_CHANGED 0x00001000 60784059Swpaul#define BGE_MACSTAT_MI_COMPLETE 0x00400000 60884059Swpaul#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 60984059Swpaul#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 61084059Swpaul#define BGE_MACSTAT_ODI_ERROR 0x02000000 61184059Swpaul#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 61284059Swpaul#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 61384059Swpaul 61484059Swpaul/* MAC Event Enable Register */ 61584059Swpaul#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 61684059Swpaul#define BGE_EVTENB_LINK_CHANGED 0x00001000 61784059Swpaul#define BGE_EVTENB_MI_COMPLETE 0x00400000 61884059Swpaul#define BGE_EVTENB_MI_INTERRUPT 0x00800000 61984059Swpaul#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 62084059Swpaul#define BGE_EVTENB_ODI_ERROR 0x02000000 62184059Swpaul#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 62284059Swpaul#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 62384059Swpaul 62484059Swpaul/* LED Control Register */ 62584059Swpaul#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 62684059Swpaul#define BGE_LEDCTL_1000MBPS_LED 0x00000002 62784059Swpaul#define BGE_LEDCTL_100MBPS_LED 0x00000004 62884059Swpaul#define BGE_LEDCTL_10MBPS_LED 0x00000008 62984059Swpaul#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 63084059Swpaul#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 63184059Swpaul#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 63284059Swpaul#define BGE_LEDCTL_1000MBPS_STS 0x00000080 63384059Swpaul#define BGE_LEDCTL_100MBPS_STS 0x00000100 63484059Swpaul#define BGE_LEDCTL_10MBPS_STS 0x00000200 63584059Swpaul#define BGE_LEDCTL_TRADLED_STS 0x00000400 63684059Swpaul#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 63784059Swpaul#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 63884059Swpaul 63984059Swpaul/* TX backoff seed register */ 64084059Swpaul#define BGE_TX_BACKOFF_SEED_MASK 0x3F 64184059Swpaul 64284059Swpaul/* Autopoll status register */ 64384059Swpaul#define BGE_AUTOPOLLSTS_ERROR 0x00000001 64484059Swpaul 64584059Swpaul/* Transmit MAC mode register */ 64684059Swpaul#define BGE_TXMODE_RESET 0x00000001 64784059Swpaul#define BGE_TXMODE_ENABLE 0x00000002 64884059Swpaul#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 64984059Swpaul#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 65084059Swpaul#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 65184059Swpaul 65284059Swpaul/* Transmit MAC status register */ 65384059Swpaul#define BGE_TXSTAT_RX_XOFFED 0x00000001 65484059Swpaul#define BGE_TXSTAT_SENT_XOFF 0x00000002 65584059Swpaul#define BGE_TXSTAT_SENT_XON 0x00000004 65684059Swpaul#define BGE_TXSTAT_LINK_UP 0x00000008 65784059Swpaul#define BGE_TXSTAT_ODI_UFLOW 0x00000010 65884059Swpaul#define BGE_TXSTAT_ODI_OFLOW 0x00000020 65984059Swpaul 66084059Swpaul/* Transmit MAC lengths register */ 66184059Swpaul#define BGE_TXLEN_SLOTTIME 0x000000FF 66284059Swpaul#define BGE_TXLEN_IPG 0x00000F00 66384059Swpaul#define BGE_TXLEN_CRS 0x00003000 66484059Swpaul 66584059Swpaul/* Receive MAC mode register */ 66684059Swpaul#define BGE_RXMODE_RESET 0x00000001 66784059Swpaul#define BGE_RXMODE_ENABLE 0x00000002 66884059Swpaul#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 66984059Swpaul#define BGE_RXMODE_RX_GIANTS 0x00000020 67084059Swpaul#define BGE_RXMODE_RX_RUNTS 0x00000040 67184059Swpaul#define BGE_RXMODE_8022_LENCHECK 0x00000080 67284059Swpaul#define BGE_RXMODE_RX_PROMISC 0x00000100 67384059Swpaul#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 67484059Swpaul#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 67584059Swpaul 67684059Swpaul/* Receive MAC status register */ 67784059Swpaul#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 67884059Swpaul#define BGE_RXSTAT_RCVD_XOFF 0x00000002 67984059Swpaul#define BGE_RXSTAT_RCVD_XON 0x00000004 68084059Swpaul 68184059Swpaul/* Receive Rules Control register */ 68284059Swpaul#define BGE_RXRULECTL_OFFSET 0x000000FF 68384059Swpaul#define BGE_RXRULECTL_CLASS 0x00001F00 68484059Swpaul#define BGE_RXRULECTL_HDRTYPE 0x0000E000 68584059Swpaul#define BGE_RXRULECTL_COMPARE_OP 0x00030000 68684059Swpaul#define BGE_RXRULECTL_MAP 0x01000000 68784059Swpaul#define BGE_RXRULECTL_DISCARD 0x02000000 68884059Swpaul#define BGE_RXRULECTL_MASK 0x04000000 68984059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 69084059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 69184059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 69284059Swpaul#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 69384059Swpaul 69484059Swpaul/* Receive Rules Mask register */ 69584059Swpaul#define BGE_RXRULEMASK_VALUE 0x0000FFFF 69684059Swpaul#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 69784059Swpaul 698130273Swpaul/* SERDES configuration register */ 699130273Swpaul#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 700130273Swpaul#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 701130273Swpaul#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 702130273Swpaul#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 703130273Swpaul#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 704130273Swpaul#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 705130273Swpaul#define BGE_SERDESCFG_TXMODE 0x00001000 706130273Swpaul#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 707130273Swpaul#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 708130273Swpaul#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 709130273Swpaul#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 710130273Swpaul#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 711130273Swpaul#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 712130273Swpaul#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 713130273Swpaul#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 714130273Swpaul#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 715130273Swpaul 716130273Swpaul/* SERDES status register */ 717130273Swpaul#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 718130273Swpaul#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 719130273Swpaul 720130273Swpaul/* SGDIG config (not documented) */ 721130273Swpaul#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 722130273Swpaul#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 723130273Swpaul#define BGE_SGDIGCFG_SEND 0x40000000 724130273Swpaul#define BGE_SGDIGCFG_AUTO 0x80000000 725130273Swpaul 726130273Swpaul/* SGDIG status (not documented) */ 727130273Swpaul#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 728130273Swpaul#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 729130273Swpaul#define BGE_SGDIGSTS_DONE 0x00000002 730130273Swpaul 731130273Swpaul 73284059Swpaul/* MI communication register */ 73384059Swpaul#define BGE_MICOMM_DATA 0x0000FFFF 73484059Swpaul#define BGE_MICOMM_REG 0x001F0000 73584059Swpaul#define BGE_MICOMM_PHY 0x03E00000 73684059Swpaul#define BGE_MICOMM_CMD 0x0C000000 73784059Swpaul#define BGE_MICOMM_READFAIL 0x10000000 73884059Swpaul#define BGE_MICOMM_BUSY 0x20000000 73984059Swpaul 74084059Swpaul#define BGE_MIREG(x) ((x & 0x1F) << 16) 74184059Swpaul#define BGE_MIPHY(x) ((x & 0x1F) << 21) 74284059Swpaul#define BGE_MICMD_WRITE 0x04000000 74384059Swpaul#define BGE_MICMD_READ 0x08000000 74484059Swpaul 74584059Swpaul/* MI status register */ 74684059Swpaul#define BGE_MISTS_LINK 0x00000001 74784059Swpaul#define BGE_MISTS_10MBPS 0x00000002 74884059Swpaul 74984059Swpaul#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 75084059Swpaul#define BGE_MIMODE_AUTOPOLL 0x00000010 75184059Swpaul#define BGE_MIMODE_CLKCNT 0x001F0000 75284059Swpaul 75384059Swpaul 75484059Swpaul/* 75584059Swpaul * Send data initiator control registers. 75684059Swpaul */ 75784059Swpaul#define BGE_SDI_MODE 0x0C00 75884059Swpaul#define BGE_SDI_STATUS 0x0C04 75984059Swpaul#define BGE_SDI_STATS_CTL 0x0C08 76084059Swpaul#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 76184059Swpaul#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 76284059Swpaul#define BGE_LOCSTATS_COS0 0x0C80 76384059Swpaul#define BGE_LOCSTATS_COS1 0x0C84 76484059Swpaul#define BGE_LOCSTATS_COS2 0x0C88 76584059Swpaul#define BGE_LOCSTATS_COS3 0x0C8C 76684059Swpaul#define BGE_LOCSTATS_COS4 0x0C90 76784059Swpaul#define BGE_LOCSTATS_COS5 0x0C84 76884059Swpaul#define BGE_LOCSTATS_COS6 0x0C98 76984059Swpaul#define BGE_LOCSTATS_COS7 0x0C9C 77084059Swpaul#define BGE_LOCSTATS_COS8 0x0CA0 77184059Swpaul#define BGE_LOCSTATS_COS9 0x0CA4 77284059Swpaul#define BGE_LOCSTATS_COS10 0x0CA8 77384059Swpaul#define BGE_LOCSTATS_COS11 0x0CAC 77484059Swpaul#define BGE_LOCSTATS_COS12 0x0CB0 77584059Swpaul#define BGE_LOCSTATS_COS13 0x0CB4 77684059Swpaul#define BGE_LOCSTATS_COS14 0x0CB8 77784059Swpaul#define BGE_LOCSTATS_COS15 0x0CBC 77884059Swpaul#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 77984059Swpaul#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 78084059Swpaul#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 78184059Swpaul#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 78284059Swpaul#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 78384059Swpaul#define BGE_LOCSTATS_IRQS 0x0CD4 78484059Swpaul#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 78584059Swpaul#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 78684059Swpaul 78784059Swpaul/* Send Data Initiator mode register */ 78884059Swpaul#define BGE_SDIMODE_RESET 0x00000001 78984059Swpaul#define BGE_SDIMODE_ENABLE 0x00000002 79084059Swpaul#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 79184059Swpaul 79284059Swpaul/* Send Data Initiator stats register */ 79384059Swpaul#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 79484059Swpaul 79584059Swpaul/* Send Data Initiator stats control register */ 79684059Swpaul#define BGE_SDISTATSCTL_ENABLE 0x00000001 79784059Swpaul#define BGE_SDISTATSCTL_FASTER 0x00000002 79884059Swpaul#define BGE_SDISTATSCTL_CLEAR 0x00000004 79984059Swpaul#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 80084059Swpaul#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 80184059Swpaul 80284059Swpaul/* 80384059Swpaul * Send Data Completion Control registers 80484059Swpaul */ 80584059Swpaul#define BGE_SDC_MODE 0x1000 80684059Swpaul#define BGE_SDC_STATUS 0x1004 80784059Swpaul 80884059Swpaul/* Send Data completion mode register */ 80984059Swpaul#define BGE_SDCMODE_RESET 0x00000001 81084059Swpaul#define BGE_SDCMODE_ENABLE 0x00000002 81184059Swpaul#define BGE_SDCMODE_ATTN 0x00000004 81284059Swpaul 81384059Swpaul/* Send Data completion status register */ 81484059Swpaul#define BGE_SDCSTAT_ATTN 0x00000004 81584059Swpaul 81684059Swpaul/* 81784059Swpaul * Send BD Ring Selector Control registers 81884059Swpaul */ 81984059Swpaul#define BGE_SRS_MODE 0x1400 82084059Swpaul#define BGE_SRS_STATUS 0x1404 82184059Swpaul#define BGE_SRS_HWDIAG 0x1408 82284059Swpaul#define BGE_SRS_LOC_NIC_CONS0 0x1440 82384059Swpaul#define BGE_SRS_LOC_NIC_CONS1 0x1444 82484059Swpaul#define BGE_SRS_LOC_NIC_CONS2 0x1448 82584059Swpaul#define BGE_SRS_LOC_NIC_CONS3 0x144C 82684059Swpaul#define BGE_SRS_LOC_NIC_CONS4 0x1450 82784059Swpaul#define BGE_SRS_LOC_NIC_CONS5 0x1454 82884059Swpaul#define BGE_SRS_LOC_NIC_CONS6 0x1458 82984059Swpaul#define BGE_SRS_LOC_NIC_CONS7 0x145C 83084059Swpaul#define BGE_SRS_LOC_NIC_CONS8 0x1460 83184059Swpaul#define BGE_SRS_LOC_NIC_CONS9 0x1464 83284059Swpaul#define BGE_SRS_LOC_NIC_CONS10 0x1468 83384059Swpaul#define BGE_SRS_LOC_NIC_CONS11 0x146C 83484059Swpaul#define BGE_SRS_LOC_NIC_CONS12 0x1470 83584059Swpaul#define BGE_SRS_LOC_NIC_CONS13 0x1474 83684059Swpaul#define BGE_SRS_LOC_NIC_CONS14 0x1478 83784059Swpaul#define BGE_SRS_LOC_NIC_CONS15 0x147C 83884059Swpaul 83984059Swpaul/* Send BD Ring Selector Mode register */ 84084059Swpaul#define BGE_SRSMODE_RESET 0x00000001 84184059Swpaul#define BGE_SRSMODE_ENABLE 0x00000002 84284059Swpaul#define BGE_SRSMODE_ATTN 0x00000004 84384059Swpaul 84484059Swpaul/* Send BD Ring Selector Status register */ 84584059Swpaul#define BGE_SRSSTAT_ERROR 0x00000004 84684059Swpaul 84784059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 84884059Swpaul#define BGE_SRSHWDIAG_STATE 0x0000000F 84984059Swpaul#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 85084059Swpaul#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 85184059Swpaul#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 85284059Swpaul 85384059Swpaul/* 85484059Swpaul * Send BD Initiator Selector Control registers 85584059Swpaul */ 85684059Swpaul#define BGE_SBDI_MODE 0x1800 85784059Swpaul#define BGE_SBDI_STATUS 0x1804 85884059Swpaul#define BGE_SBDI_LOC_NIC_PROD0 0x1808 85984059Swpaul#define BGE_SBDI_LOC_NIC_PROD1 0x180C 86084059Swpaul#define BGE_SBDI_LOC_NIC_PROD2 0x1810 86184059Swpaul#define BGE_SBDI_LOC_NIC_PROD3 0x1814 86284059Swpaul#define BGE_SBDI_LOC_NIC_PROD4 0x1818 86384059Swpaul#define BGE_SBDI_LOC_NIC_PROD5 0x181C 86484059Swpaul#define BGE_SBDI_LOC_NIC_PROD6 0x1820 86584059Swpaul#define BGE_SBDI_LOC_NIC_PROD7 0x1824 86684059Swpaul#define BGE_SBDI_LOC_NIC_PROD8 0x1828 86784059Swpaul#define BGE_SBDI_LOC_NIC_PROD9 0x182C 86884059Swpaul#define BGE_SBDI_LOC_NIC_PROD10 0x1830 86984059Swpaul#define BGE_SBDI_LOC_NIC_PROD11 0x1834 87084059Swpaul#define BGE_SBDI_LOC_NIC_PROD12 0x1838 87184059Swpaul#define BGE_SBDI_LOC_NIC_PROD13 0x183C 87284059Swpaul#define BGE_SBDI_LOC_NIC_PROD14 0x1840 87384059Swpaul#define BGE_SBDI_LOC_NIC_PROD15 0x1844 87484059Swpaul 87584059Swpaul/* Send BD Initiator Mode register */ 87684059Swpaul#define BGE_SBDIMODE_RESET 0x00000001 87784059Swpaul#define BGE_SBDIMODE_ENABLE 0x00000002 87884059Swpaul#define BGE_SBDIMODE_ATTN 0x00000004 87984059Swpaul 88084059Swpaul/* Send BD Initiator Status register */ 88184059Swpaul#define BGE_SBDISTAT_ERROR 0x00000004 88284059Swpaul 88384059Swpaul/* 88484059Swpaul * Send BD Completion Control registers 88584059Swpaul */ 88684059Swpaul#define BGE_SBDC_MODE 0x1C00 88784059Swpaul#define BGE_SBDC_STATUS 0x1C04 88884059Swpaul 88984059Swpaul/* Send BD Completion Control Mode register */ 89084059Swpaul#define BGE_SBDCMODE_RESET 0x00000001 89184059Swpaul#define BGE_SBDCMODE_ENABLE 0x00000002 89284059Swpaul#define BGE_SBDCMODE_ATTN 0x00000004 89384059Swpaul 89484059Swpaul/* Send BD Completion Control Status register */ 89584059Swpaul#define BGE_SBDCSTAT_ATTN 0x00000004 89684059Swpaul 89784059Swpaul/* 89884059Swpaul * Receive List Placement Control registers 89984059Swpaul */ 90084059Swpaul#define BGE_RXLP_MODE 0x2000 90184059Swpaul#define BGE_RXLP_STATUS 0x2004 90284059Swpaul#define BGE_RXLP_SEL_LIST_LOCK 0x2008 90384059Swpaul#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 90484059Swpaul#define BGE_RXLP_CFG 0x2010 90584059Swpaul#define BGE_RXLP_STATS_CTL 0x2014 90684059Swpaul#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 90784059Swpaul#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 90884059Swpaul#define BGE_RXLP_HEAD0 0x2100 90984059Swpaul#define BGE_RXLP_TAIL0 0x2104 91084059Swpaul#define BGE_RXLP_COUNT0 0x2108 91184059Swpaul#define BGE_RXLP_HEAD1 0x2110 91284059Swpaul#define BGE_RXLP_TAIL1 0x2114 91384059Swpaul#define BGE_RXLP_COUNT1 0x2118 91484059Swpaul#define BGE_RXLP_HEAD2 0x2120 91584059Swpaul#define BGE_RXLP_TAIL2 0x2124 91684059Swpaul#define BGE_RXLP_COUNT2 0x2128 91784059Swpaul#define BGE_RXLP_HEAD3 0x2130 91884059Swpaul#define BGE_RXLP_TAIL3 0x2134 91984059Swpaul#define BGE_RXLP_COUNT3 0x2138 92084059Swpaul#define BGE_RXLP_HEAD4 0x2140 92184059Swpaul#define BGE_RXLP_TAIL4 0x2144 92284059Swpaul#define BGE_RXLP_COUNT4 0x2148 92384059Swpaul#define BGE_RXLP_HEAD5 0x2150 92484059Swpaul#define BGE_RXLP_TAIL5 0x2154 92584059Swpaul#define BGE_RXLP_COUNT5 0x2158 92684059Swpaul#define BGE_RXLP_HEAD6 0x2160 92784059Swpaul#define BGE_RXLP_TAIL6 0x2164 92884059Swpaul#define BGE_RXLP_COUNT6 0x2168 92984059Swpaul#define BGE_RXLP_HEAD7 0x2170 93084059Swpaul#define BGE_RXLP_TAIL7 0x2174 93184059Swpaul#define BGE_RXLP_COUNT7 0x2178 93284059Swpaul#define BGE_RXLP_HEAD8 0x2180 93384059Swpaul#define BGE_RXLP_TAIL8 0x2184 93484059Swpaul#define BGE_RXLP_COUNT8 0x2188 93584059Swpaul#define BGE_RXLP_HEAD9 0x2190 93684059Swpaul#define BGE_RXLP_TAIL9 0x2194 93784059Swpaul#define BGE_RXLP_COUNT9 0x2198 93884059Swpaul#define BGE_RXLP_HEAD10 0x21A0 93984059Swpaul#define BGE_RXLP_TAIL10 0x21A4 94084059Swpaul#define BGE_RXLP_COUNT10 0x21A8 94184059Swpaul#define BGE_RXLP_HEAD11 0x21B0 94284059Swpaul#define BGE_RXLP_TAIL11 0x21B4 94384059Swpaul#define BGE_RXLP_COUNT11 0x21B8 94484059Swpaul#define BGE_RXLP_HEAD12 0x21C0 94584059Swpaul#define BGE_RXLP_TAIL12 0x21C4 94684059Swpaul#define BGE_RXLP_COUNT12 0x21C8 94784059Swpaul#define BGE_RXLP_HEAD13 0x21D0 94884059Swpaul#define BGE_RXLP_TAIL13 0x21D4 94984059Swpaul#define BGE_RXLP_COUNT13 0x21D8 95084059Swpaul#define BGE_RXLP_HEAD14 0x21E0 95184059Swpaul#define BGE_RXLP_TAIL14 0x21E4 95284059Swpaul#define BGE_RXLP_COUNT14 0x21E8 95384059Swpaul#define BGE_RXLP_HEAD15 0x21F0 95484059Swpaul#define BGE_RXLP_TAIL15 0x21F4 95584059Swpaul#define BGE_RXLP_COUNT15 0x21F8 95684059Swpaul#define BGE_RXLP_LOCSTAT_COS0 0x2200 95784059Swpaul#define BGE_RXLP_LOCSTAT_COS1 0x2204 95884059Swpaul#define BGE_RXLP_LOCSTAT_COS2 0x2208 95984059Swpaul#define BGE_RXLP_LOCSTAT_COS3 0x220C 96084059Swpaul#define BGE_RXLP_LOCSTAT_COS4 0x2210 96184059Swpaul#define BGE_RXLP_LOCSTAT_COS5 0x2214 96284059Swpaul#define BGE_RXLP_LOCSTAT_COS6 0x2218 96384059Swpaul#define BGE_RXLP_LOCSTAT_COS7 0x221C 96484059Swpaul#define BGE_RXLP_LOCSTAT_COS8 0x2220 96584059Swpaul#define BGE_RXLP_LOCSTAT_COS9 0x2224 96684059Swpaul#define BGE_RXLP_LOCSTAT_COS10 0x2228 96784059Swpaul#define BGE_RXLP_LOCSTAT_COS11 0x222C 96884059Swpaul#define BGE_RXLP_LOCSTAT_COS12 0x2230 96984059Swpaul#define BGE_RXLP_LOCSTAT_COS13 0x2234 97084059Swpaul#define BGE_RXLP_LOCSTAT_COS14 0x2238 97184059Swpaul#define BGE_RXLP_LOCSTAT_COS15 0x223C 97284059Swpaul#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 97384059Swpaul#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 97484059Swpaul#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 97584059Swpaul#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 97684059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 97784059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 97884059Swpaul#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 97984059Swpaul 98084059Swpaul 98184059Swpaul/* Receive List Placement mode register */ 98284059Swpaul#define BGE_RXLPMODE_RESET 0x00000001 98384059Swpaul#define BGE_RXLPMODE_ENABLE 0x00000002 98484059Swpaul#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 98584059Swpaul#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 98684059Swpaul#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 98784059Swpaul 98884059Swpaul/* Receive List Placement Status register */ 98984059Swpaul#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 99084059Swpaul#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 99184059Swpaul#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 99284059Swpaul 99384059Swpaul/* 99484059Swpaul * Receive Data and Receive BD Initiator Control Registers 99584059Swpaul */ 99684059Swpaul#define BGE_RDBDI_MODE 0x2400 99784059Swpaul#define BGE_RDBDI_STATUS 0x2404 99884059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 99984059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 100084059Swpaul#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 100184059Swpaul#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 100284059Swpaul#define BGE_RX_STD_RCB_HADDR_HI 0x2450 100384059Swpaul#define BGE_RX_STD_RCB_HADDR_LO 0x2454 100484059Swpaul#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 100584059Swpaul#define BGE_RX_STD_RCB_NICADDR 0x245C 100684059Swpaul#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 100784059Swpaul#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 100884059Swpaul#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 100984059Swpaul#define BGE_RX_MINI_RCB_NICADDR 0x246C 101084059Swpaul#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 101184059Swpaul#define BGE_RDBDI_STD_RX_CONS 0x2474 101284059Swpaul#define BGE_RDBDI_MINI_RX_CONS 0x2478 101384059Swpaul#define BGE_RDBDI_RETURN_PROD0 0x2480 101484059Swpaul#define BGE_RDBDI_RETURN_PROD1 0x2484 101584059Swpaul#define BGE_RDBDI_RETURN_PROD2 0x2488 101684059Swpaul#define BGE_RDBDI_RETURN_PROD3 0x248C 101784059Swpaul#define BGE_RDBDI_RETURN_PROD4 0x2490 101884059Swpaul#define BGE_RDBDI_RETURN_PROD5 0x2494 101984059Swpaul#define BGE_RDBDI_RETURN_PROD6 0x2498 102084059Swpaul#define BGE_RDBDI_RETURN_PROD7 0x249C 102184059Swpaul#define BGE_RDBDI_RETURN_PROD8 0x24A0 102284059Swpaul#define BGE_RDBDI_RETURN_PROD9 0x24A4 102384059Swpaul#define BGE_RDBDI_RETURN_PROD10 0x24A8 102484059Swpaul#define BGE_RDBDI_RETURN_PROD11 0x24AC 102584059Swpaul#define BGE_RDBDI_RETURN_PROD12 0x24B0 102684059Swpaul#define BGE_RDBDI_RETURN_PROD13 0x24B4 102784059Swpaul#define BGE_RDBDI_RETURN_PROD14 0x24B8 102884059Swpaul#define BGE_RDBDI_RETURN_PROD15 0x24BC 102984059Swpaul#define BGE_RDBDI_HWDIAG 0x24C0 103084059Swpaul 103184059Swpaul 103284059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 103384059Swpaul#define BGE_RDBDIMODE_RESET 0x00000001 103484059Swpaul#define BGE_RDBDIMODE_ENABLE 0x00000002 103584059Swpaul#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 103684059Swpaul#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 103784059Swpaul#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 103884059Swpaul 103984059Swpaul/* Receive Data and Receive BD Initiator Status register */ 104084059Swpaul#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 104184059Swpaul#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 104284059Swpaul#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 104384059Swpaul 104484059Swpaul 104584059Swpaul/* 104684059Swpaul * Receive Data Completion Control registers 104784059Swpaul */ 104884059Swpaul#define BGE_RDC_MODE 0x2800 104984059Swpaul 105084059Swpaul/* Receive Data Completion Mode register */ 105184059Swpaul#define BGE_RDCMODE_RESET 0x00000001 105284059Swpaul#define BGE_RDCMODE_ENABLE 0x00000002 105384059Swpaul#define BGE_RDCMODE_ATTN 0x00000004 105484059Swpaul 105584059Swpaul/* 105684059Swpaul * Receive BD Initiator Control registers 105784059Swpaul */ 105884059Swpaul#define BGE_RBDI_MODE 0x2C00 105984059Swpaul#define BGE_RBDI_STATUS 0x2C04 106084059Swpaul#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 106184059Swpaul#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 106284059Swpaul#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 106384059Swpaul#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 106484059Swpaul#define BGE_RBDI_STD_REPL_THRESH 0x2C18 106584059Swpaul#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 106684059Swpaul 106784059Swpaul/* Receive BD Initiator Mode register */ 106884059Swpaul#define BGE_RBDIMODE_RESET 0x00000001 106984059Swpaul#define BGE_RBDIMODE_ENABLE 0x00000002 107084059Swpaul#define BGE_RBDIMODE_ATTN 0x00000004 107184059Swpaul 107284059Swpaul/* Receive BD Initiator Status register */ 107384059Swpaul#define BGE_RBDISTAT_ATTN 0x00000004 107484059Swpaul 107584059Swpaul/* 107684059Swpaul * Receive BD Completion Control registers 107784059Swpaul */ 107884059Swpaul#define BGE_RBDC_MODE 0x3000 107984059Swpaul#define BGE_RBDC_STATUS 0x3004 108084059Swpaul#define BGE_RBDC_JUMBO_BD_PROD 0x3008 108184059Swpaul#define BGE_RBDC_STD_BD_PROD 0x300C 108284059Swpaul#define BGE_RBDC_MINI_BD_PROD 0x3010 108384059Swpaul 108484059Swpaul/* Receive BD completion mode register */ 108584059Swpaul#define BGE_RBDCMODE_RESET 0x00000001 108684059Swpaul#define BGE_RBDCMODE_ENABLE 0x00000002 108784059Swpaul#define BGE_RBDCMODE_ATTN 0x00000004 108884059Swpaul 108984059Swpaul/* Receive BD completion status register */ 109084059Swpaul#define BGE_RBDCSTAT_ERROR 0x00000004 109184059Swpaul 109284059Swpaul/* 109384059Swpaul * Receive List Selector Control registers 109484059Swpaul */ 109584059Swpaul#define BGE_RXLS_MODE 0x3400 109684059Swpaul#define BGE_RXLS_STATUS 0x3404 109784059Swpaul 109884059Swpaul/* Receive List Selector Mode register */ 109984059Swpaul#define BGE_RXLSMODE_RESET 0x00000001 110084059Swpaul#define BGE_RXLSMODE_ENABLE 0x00000002 110184059Swpaul#define BGE_RXLSMODE_ATTN 0x00000004 110284059Swpaul 110384059Swpaul/* Receive List Selector Status register */ 110484059Swpaul#define BGE_RXLSSTAT_ERROR 0x00000004 110584059Swpaul 110684059Swpaul/* 110784059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 110884059Swpaul */ 110984059Swpaul#define BGE_MBCF_MODE 0x3800 111084059Swpaul#define BGE_MBCF_STATUS 0x3804 111184059Swpaul 111284059Swpaul/* Mbuf Cluster Free mode register */ 111384059Swpaul#define BGE_MBCFMODE_RESET 0x00000001 111484059Swpaul#define BGE_MBCFMODE_ENABLE 0x00000002 111584059Swpaul#define BGE_MBCFMODE_ATTN 0x00000004 111684059Swpaul 111784059Swpaul/* Mbuf Cluster Free status register */ 111884059Swpaul#define BGE_MBCFSTAT_ERROR 0x00000004 111984059Swpaul 112084059Swpaul/* 112184059Swpaul * Host Coalescing Control registers 112284059Swpaul */ 112384059Swpaul#define BGE_HCC_MODE 0x3C00 112484059Swpaul#define BGE_HCC_STATUS 0x3C04 112584059Swpaul#define BGE_HCC_RX_COAL_TICKS 0x3C08 112684059Swpaul#define BGE_HCC_TX_COAL_TICKS 0x3C0C 112784059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 112884059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 112984059Swpaul#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 113084059Swpaul#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 113184059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1132119047Sps#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 113384059Swpaul#define BGE_HCC_STATS_TICKS 0x3C28 113484059Swpaul#define BGE_HCC_STATS_ADDR_HI 0x3C30 113584059Swpaul#define BGE_HCC_STATS_ADDR_LO 0x3C34 113684059Swpaul#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 113784059Swpaul#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 113884059Swpaul#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 113984059Swpaul#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 114084059Swpaul#define BGE_FLOW_ATTN 0x3C48 114184059Swpaul#define BGE_HCC_JUMBO_BD_CONS 0x3C50 114284059Swpaul#define BGE_HCC_STD_BD_CONS 0x3C54 114384059Swpaul#define BGE_HCC_MINI_BD_CONS 0x3C58 114484059Swpaul#define BGE_HCC_RX_RETURN_PROD0 0x3C80 114584059Swpaul#define BGE_HCC_RX_RETURN_PROD1 0x3C84 114684059Swpaul#define BGE_HCC_RX_RETURN_PROD2 0x3C88 114784059Swpaul#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 114884059Swpaul#define BGE_HCC_RX_RETURN_PROD4 0x3C90 114984059Swpaul#define BGE_HCC_RX_RETURN_PROD5 0x3C94 115084059Swpaul#define BGE_HCC_RX_RETURN_PROD6 0x3C98 115184059Swpaul#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 115284059Swpaul#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 115384059Swpaul#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 115484059Swpaul#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 115584059Swpaul#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 115684059Swpaul#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 115784059Swpaul#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 115884059Swpaul#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 115984059Swpaul#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 116084059Swpaul#define BGE_HCC_TX_BD_CONS0 0x3CC0 116184059Swpaul#define BGE_HCC_TX_BD_CONS1 0x3CC4 116284059Swpaul#define BGE_HCC_TX_BD_CONS2 0x3CC8 116384059Swpaul#define BGE_HCC_TX_BD_CONS3 0x3CCC 116484059Swpaul#define BGE_HCC_TX_BD_CONS4 0x3CD0 116584059Swpaul#define BGE_HCC_TX_BD_CONS5 0x3CD4 116684059Swpaul#define BGE_HCC_TX_BD_CONS6 0x3CD8 116784059Swpaul#define BGE_HCC_TX_BD_CONS7 0x3CDC 116884059Swpaul#define BGE_HCC_TX_BD_CONS8 0x3CE0 116984059Swpaul#define BGE_HCC_TX_BD_CONS9 0x3CE4 117084059Swpaul#define BGE_HCC_TX_BD_CONS10 0x3CE8 117184059Swpaul#define BGE_HCC_TX_BD_CONS11 0x3CEC 117284059Swpaul#define BGE_HCC_TX_BD_CONS12 0x3CF0 117384059Swpaul#define BGE_HCC_TX_BD_CONS13 0x3CF4 117484059Swpaul#define BGE_HCC_TX_BD_CONS14 0x3CF8 117584059Swpaul#define BGE_HCC_TX_BD_CONS15 0x3CFC 117684059Swpaul 117784059Swpaul 117884059Swpaul/* Host coalescing mode register */ 117984059Swpaul#define BGE_HCCMODE_RESET 0x00000001 118084059Swpaul#define BGE_HCCMODE_ENABLE 0x00000002 118184059Swpaul#define BGE_HCCMODE_ATTN 0x00000004 118284059Swpaul#define BGE_HCCMODE_COAL_NOW 0x00000008 1183157683Spjd#define BGE_HCCMODE_MSI_BITS 0x00000070 118484059Swpaul#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 118584059Swpaul 118684059Swpaul#define BGE_STATBLKSZ_FULL 0x00000000 118784059Swpaul#define BGE_STATBLKSZ_64BYTE 0x00000080 118884059Swpaul#define BGE_STATBLKSZ_32BYTE 0x00000100 118984059Swpaul 119084059Swpaul/* Host coalescing status register */ 119184059Swpaul#define BGE_HCCSTAT_ERROR 0x00000004 119284059Swpaul 119384059Swpaul/* Flow attention register */ 119484059Swpaul#define BGE_FLOWATTN_MB_LOWAT 0x00000040 119584059Swpaul#define BGE_FLOWATTN_MEMARB 0x00000080 119684059Swpaul#define BGE_FLOWATTN_HOSTCOAL 0x00008000 119784059Swpaul#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 119884059Swpaul#define BGE_FLOWATTN_RCB_INVAL 0x00020000 119984059Swpaul#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 120084059Swpaul#define BGE_FLOWATTN_RDBDI 0x00080000 120184059Swpaul#define BGE_FLOWATTN_RXLS 0x00100000 120284059Swpaul#define BGE_FLOWATTN_RXLP 0x00200000 120384059Swpaul#define BGE_FLOWATTN_RBDC 0x00400000 120484059Swpaul#define BGE_FLOWATTN_RBDI 0x00800000 120584059Swpaul#define BGE_FLOWATTN_SDC 0x08000000 120684059Swpaul#define BGE_FLOWATTN_SDI 0x10000000 120784059Swpaul#define BGE_FLOWATTN_SRS 0x20000000 120884059Swpaul#define BGE_FLOWATTN_SBDC 0x40000000 120984059Swpaul#define BGE_FLOWATTN_SBDI 0x80000000 121084059Swpaul 121184059Swpaul/* 121284059Swpaul * Memory arbiter registers 121384059Swpaul */ 121484059Swpaul#define BGE_MARB_MODE 0x4000 121584059Swpaul#define BGE_MARB_STATUS 0x4004 121684059Swpaul#define BGE_MARB_TRAPADDR_HI 0x4008 121784059Swpaul#define BGE_MARB_TRAPADDR_LO 0x400C 121884059Swpaul 121984059Swpaul/* Memory arbiter mode register */ 122084059Swpaul#define BGE_MARBMODE_RESET 0x00000001 122184059Swpaul#define BGE_MARBMODE_ENABLE 0x00000002 122284059Swpaul#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 122384059Swpaul#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 122484059Swpaul#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 122584059Swpaul#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 122684059Swpaul#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 122784059Swpaul#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 122884059Swpaul#define BGE_MARBMODE_PCI_TRAP 0x00000100 122984059Swpaul#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 123084059Swpaul#define BGE_MARBMODE_RXQ_TRAP 0x00000400 123184059Swpaul#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 123284059Swpaul#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 123384059Swpaul#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 123484059Swpaul#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 123584059Swpaul#define BGE_MARBMODE_MBUF_TRAP 0x00008000 123684059Swpaul#define BGE_MARBMODE_TXDI_TRAP 0x00010000 123784059Swpaul#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 123884059Swpaul#define BGE_MARBMODE_TXBD_TRAP 0x00040000 123984059Swpaul#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 124084059Swpaul#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 124184059Swpaul#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 124284059Swpaul#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 124384059Swpaul#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 124484059Swpaul#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 124584059Swpaul#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 124684059Swpaul 124784059Swpaul/* Memory arbiter status register */ 124884059Swpaul#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 124984059Swpaul#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 125084059Swpaul#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 125184059Swpaul#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 125284059Swpaul#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 125384059Swpaul#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 125484059Swpaul#define BGE_MARBSTAT_PCI_TRAP 0x00000100 125584059Swpaul#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 125684059Swpaul#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 125784059Swpaul#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 125884059Swpaul#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 125984059Swpaul#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 126084059Swpaul#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 126184059Swpaul#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 126284059Swpaul#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 126384059Swpaul#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 126484059Swpaul#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 126584059Swpaul#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 126684059Swpaul#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 126784059Swpaul#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 126884059Swpaul#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 126984059Swpaul#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 127084059Swpaul#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 127184059Swpaul#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 127284059Swpaul 127384059Swpaul/* 127484059Swpaul * Buffer manager control registers 127584059Swpaul */ 127684059Swpaul#define BGE_BMAN_MODE 0x4400 127784059Swpaul#define BGE_BMAN_STATUS 0x4404 127884059Swpaul#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 127984059Swpaul#define BGE_BMAN_MBUFPOOL_LEN 0x440C 128084059Swpaul#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 128184059Swpaul#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 128284059Swpaul#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 128384059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 128484059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 128584059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 128684059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 128784059Swpaul#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 128884059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 128984059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 129084059Swpaul#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 129184059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 129284059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 129384059Swpaul#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 129484059Swpaul#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 129584059Swpaul#define BGE_BMAN_HWDIAG_1 0x444C 129684059Swpaul#define BGE_BMAN_HWDIAG_2 0x4450 129784059Swpaul#define BGE_BMAN_HWDIAG_3 0x4454 129884059Swpaul 129984059Swpaul/* Buffer manager mode register */ 130084059Swpaul#define BGE_BMANMODE_RESET 0x00000001 130184059Swpaul#define BGE_BMANMODE_ENABLE 0x00000002 130284059Swpaul#define BGE_BMANMODE_ATTN 0x00000004 130384059Swpaul#define BGE_BMANMODE_TESTMODE 0x00000008 130484059Swpaul#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 130584059Swpaul 130684059Swpaul/* Buffer manager status register */ 130784059Swpaul#define BGE_BMANSTAT_ERRO 0x00000004 130884059Swpaul#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 130984059Swpaul 131084059Swpaul 131184059Swpaul/* 131284059Swpaul * Read DMA Control registers 131384059Swpaul */ 131484059Swpaul#define BGE_RDMA_MODE 0x4800 131584059Swpaul#define BGE_RDMA_STATUS 0x4804 131684059Swpaul 131784059Swpaul/* Read DMA mode register */ 131884059Swpaul#define BGE_RDMAMODE_RESET 0x00000001 131984059Swpaul#define BGE_RDMAMODE_ENABLE 0x00000002 132084059Swpaul#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 132184059Swpaul#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 132284059Swpaul#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 132384059Swpaul#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 132484059Swpaul#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 132584059Swpaul#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 132684059Swpaul#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 132784059Swpaul#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 132884059Swpaul#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 132984059Swpaul 133084059Swpaul/* Read DMA status register */ 133184059Swpaul#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 133284059Swpaul#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 133384059Swpaul#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 133484059Swpaul#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 133584059Swpaul#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 133684059Swpaul#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 133784059Swpaul#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 133884059Swpaul#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 133984059Swpaul 134084059Swpaul/* 134184059Swpaul * Write DMA control registers 134284059Swpaul */ 134384059Swpaul#define BGE_WDMA_MODE 0x4C00 134484059Swpaul#define BGE_WDMA_STATUS 0x4C04 134584059Swpaul 134684059Swpaul/* Write DMA mode register */ 134784059Swpaul#define BGE_WDMAMODE_RESET 0x00000001 134884059Swpaul#define BGE_WDMAMODE_ENABLE 0x00000002 134984059Swpaul#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 135084059Swpaul#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 135184059Swpaul#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 135284059Swpaul#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 135384059Swpaul#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 135484059Swpaul#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 135584059Swpaul#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 135684059Swpaul#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 135784059Swpaul#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 135884059Swpaul 135984059Swpaul/* Write DMA status register */ 136084059Swpaul#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 136184059Swpaul#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 136284059Swpaul#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 136384059Swpaul#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 136484059Swpaul#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 136584059Swpaul#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 136684059Swpaul#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 136784059Swpaul#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 136884059Swpaul 136984059Swpaul 137084059Swpaul/* 137184059Swpaul * RX CPU registers 137284059Swpaul */ 137384059Swpaul#define BGE_RXCPU_MODE 0x5000 137484059Swpaul#define BGE_RXCPU_STATUS 0x5004 137584059Swpaul#define BGE_RXCPU_PC 0x501C 137684059Swpaul 137784059Swpaul/* RX CPU mode register */ 137884059Swpaul#define BGE_RXCPUMODE_RESET 0x00000001 137984059Swpaul#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 138084059Swpaul#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 138184059Swpaul#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 138284059Swpaul#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 138384059Swpaul#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 138484059Swpaul#define BGE_RXCPUMODE_ROMFAIL 0x00000040 138584059Swpaul#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 138684059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 138784059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 138884059Swpaul#define BGE_RXCPUMODE_HALTCPU 0x00000400 138984059Swpaul#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 139084059Swpaul#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 139184059Swpaul#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 139284059Swpaul 139384059Swpaul/* RX CPU status register */ 139484059Swpaul#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 139584059Swpaul#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 139684059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 139784059Swpaul#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 139884059Swpaul#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 139984059Swpaul#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 140084059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 140184059Swpaul#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 140284059Swpaul#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 140384059Swpaul#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 140484059Swpaul#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 140584059Swpaul#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 140684059Swpaul#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 140784059Swpaul#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 140884059Swpaul#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 140984059Swpaul#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 141084059Swpaul#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 141184059Swpaul 141284059Swpaul 141384059Swpaul/* 141484059Swpaul * TX CPU registers 141584059Swpaul */ 141684059Swpaul#define BGE_TXCPU_MODE 0x5400 141784059Swpaul#define BGE_TXCPU_STATUS 0x5404 141884059Swpaul#define BGE_TXCPU_PC 0x541C 141984059Swpaul 142084059Swpaul/* TX CPU mode register */ 142184059Swpaul#define BGE_TXCPUMODE_RESET 0x00000001 142284059Swpaul#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 142384059Swpaul#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 142484059Swpaul#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 142584059Swpaul#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 142684059Swpaul#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 142784059Swpaul#define BGE_TXCPUMODE_ROMFAIL 0x00000040 142884059Swpaul#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 142984059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 143084059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 143184059Swpaul#define BGE_TXCPUMODE_HALTCPU 0x00000400 143284059Swpaul#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 143384059Swpaul#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 143484059Swpaul 143584059Swpaul/* TX CPU status register */ 143684059Swpaul#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 143784059Swpaul#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 143884059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 143984059Swpaul#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 144084059Swpaul#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 144184059Swpaul#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 144284059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 144384059Swpaul#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 144484059Swpaul#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 144584059Swpaul#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 144684059Swpaul#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 144784059Swpaul#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 144884059Swpaul#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 144984059Swpaul#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 145084059Swpaul#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 145184059Swpaul#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 145284059Swpaul#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 145384059Swpaul 145484059Swpaul 145584059Swpaul/* 145684059Swpaul * Low priority mailbox registers 145784059Swpaul */ 145884059Swpaul#define BGE_LPMBX_IRQ0_HI 0x5800 145984059Swpaul#define BGE_LPMBX_IRQ0_LO 0x5804 146084059Swpaul#define BGE_LPMBX_IRQ1_HI 0x5808 146184059Swpaul#define BGE_LPMBX_IRQ1_LO 0x580C 146284059Swpaul#define BGE_LPMBX_IRQ2_HI 0x5810 146384059Swpaul#define BGE_LPMBX_IRQ2_LO 0x5814 146484059Swpaul#define BGE_LPMBX_IRQ3_HI 0x5818 146584059Swpaul#define BGE_LPMBX_IRQ3_LO 0x581C 146684059Swpaul#define BGE_LPMBX_GEN0_HI 0x5820 146784059Swpaul#define BGE_LPMBX_GEN0_LO 0x5824 146884059Swpaul#define BGE_LPMBX_GEN1_HI 0x5828 146984059Swpaul#define BGE_LPMBX_GEN1_LO 0x582C 147084059Swpaul#define BGE_LPMBX_GEN2_HI 0x5830 147184059Swpaul#define BGE_LPMBX_GEN2_LO 0x5834 147284059Swpaul#define BGE_LPMBX_GEN3_HI 0x5828 147384059Swpaul#define BGE_LPMBX_GEN3_LO 0x582C 147484059Swpaul#define BGE_LPMBX_GEN4_HI 0x5840 147584059Swpaul#define BGE_LPMBX_GEN4_LO 0x5844 147684059Swpaul#define BGE_LPMBX_GEN5_HI 0x5848 147784059Swpaul#define BGE_LPMBX_GEN5_LO 0x584C 147884059Swpaul#define BGE_LPMBX_GEN6_HI 0x5850 147984059Swpaul#define BGE_LPMBX_GEN6_LO 0x5854 148084059Swpaul#define BGE_LPMBX_GEN7_HI 0x5858 148184059Swpaul#define BGE_LPMBX_GEN7_LO 0x585C 148284059Swpaul#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 148384059Swpaul#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 148484059Swpaul#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 148584059Swpaul#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 148684059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 148784059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 148884059Swpaul#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 148984059Swpaul#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 149084059Swpaul#define BGE_LPMBX_RX_CONS0_HI 0x5880 149184059Swpaul#define BGE_LPMBX_RX_CONS0_LO 0x5884 149284059Swpaul#define BGE_LPMBX_RX_CONS1_HI 0x5888 149384059Swpaul#define BGE_LPMBX_RX_CONS1_LO 0x588C 149484059Swpaul#define BGE_LPMBX_RX_CONS2_HI 0x5890 149584059Swpaul#define BGE_LPMBX_RX_CONS2_LO 0x5894 149684059Swpaul#define BGE_LPMBX_RX_CONS3_HI 0x5898 149784059Swpaul#define BGE_LPMBX_RX_CONS3_LO 0x589C 149884059Swpaul#define BGE_LPMBX_RX_CONS4_HI 0x58A0 149984059Swpaul#define BGE_LPMBX_RX_CONS4_LO 0x58A4 150084059Swpaul#define BGE_LPMBX_RX_CONS5_HI 0x58A8 150184059Swpaul#define BGE_LPMBX_RX_CONS5_LO 0x58AC 150284059Swpaul#define BGE_LPMBX_RX_CONS6_HI 0x58B0 150384059Swpaul#define BGE_LPMBX_RX_CONS6_LO 0x58B4 150484059Swpaul#define BGE_LPMBX_RX_CONS7_HI 0x58B8 150584059Swpaul#define BGE_LPMBX_RX_CONS7_LO 0x58BC 150684059Swpaul#define BGE_LPMBX_RX_CONS8_HI 0x58C0 150784059Swpaul#define BGE_LPMBX_RX_CONS8_LO 0x58C4 150884059Swpaul#define BGE_LPMBX_RX_CONS9_HI 0x58C8 150984059Swpaul#define BGE_LPMBX_RX_CONS9_LO 0x58CC 151084059Swpaul#define BGE_LPMBX_RX_CONS10_HI 0x58D0 151184059Swpaul#define BGE_LPMBX_RX_CONS10_LO 0x58D4 151284059Swpaul#define BGE_LPMBX_RX_CONS11_HI 0x58D8 151384059Swpaul#define BGE_LPMBX_RX_CONS11_LO 0x58DC 151484059Swpaul#define BGE_LPMBX_RX_CONS12_HI 0x58E0 151584059Swpaul#define BGE_LPMBX_RX_CONS12_LO 0x58E4 151684059Swpaul#define BGE_LPMBX_RX_CONS13_HI 0x58E8 151784059Swpaul#define BGE_LPMBX_RX_CONS13_LO 0x58EC 151884059Swpaul#define BGE_LPMBX_RX_CONS14_HI 0x58F0 151984059Swpaul#define BGE_LPMBX_RX_CONS14_LO 0x58F4 152084059Swpaul#define BGE_LPMBX_RX_CONS15_HI 0x58F8 152184059Swpaul#define BGE_LPMBX_RX_CONS15_LO 0x58FC 152284059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 152384059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 152484059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 152584059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 152684059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 152784059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 152884059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 152984059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 153084059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 153184059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 153284059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 153384059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 153484059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 153584059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 153684059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 153784059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 153884059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 153984059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 154084059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 154184059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 154284059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 154384059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 154484059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 154584059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 154684059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 154784059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 154884059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 154984059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 155084059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 155184059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 155284059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 155384059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 155484059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 155584059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 155684059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 155784059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 155884059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 155984059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 156084059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 156184059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 156284059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 156384059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 156484059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 156584059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 156684059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 156784059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 156884059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 156984059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 157084059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 157184059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 157284059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 157384059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 157484059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 157584059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 157684059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 157784059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 157884059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 157984059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 158084059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 158184059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 158284059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 158384059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 158484059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 158584059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 158684059Swpaul 158784059Swpaul/* 158884059Swpaul * Flow throw Queue reset register 158984059Swpaul */ 159084059Swpaul#define BGE_FTQ_RESET 0x5C00 159184059Swpaul 159284059Swpaul#define BGE_FTQRESET_DMAREAD 0x00000002 159384059Swpaul#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 159484059Swpaul#define BGE_FTQRESET_DMADONE 0x00000010 159584059Swpaul#define BGE_FTQRESET_SBDC 0x00000020 159684059Swpaul#define BGE_FTQRESET_SDI 0x00000040 159784059Swpaul#define BGE_FTQRESET_WDMA 0x00000080 159884059Swpaul#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 159984059Swpaul#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 160084059Swpaul#define BGE_FTQRESET_SDC 0x00000400 160184059Swpaul#define BGE_FTQRESET_HCC 0x00000800 160284059Swpaul#define BGE_FTQRESET_TXFIFO 0x00001000 160384059Swpaul#define BGE_FTQRESET_MBC 0x00002000 160484059Swpaul#define BGE_FTQRESET_RBDC 0x00004000 160584059Swpaul#define BGE_FTQRESET_RXLP 0x00008000 160684059Swpaul#define BGE_FTQRESET_RDBDI 0x00010000 160784059Swpaul#define BGE_FTQRESET_RDC 0x00020000 160884059Swpaul#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 160984059Swpaul 161084059Swpaul/* 161184059Swpaul * Message Signaled Interrupt registers 161284059Swpaul */ 161384059Swpaul#define BGE_MSI_MODE 0x6000 161484059Swpaul#define BGE_MSI_STATUS 0x6004 161584059Swpaul#define BGE_MSI_FIFOACCESS 0x6008 161684059Swpaul 161784059Swpaul/* MSI mode register */ 161884059Swpaul#define BGE_MSIMODE_RESET 0x00000001 161984059Swpaul#define BGE_MSIMODE_ENABLE 0x00000002 162084059Swpaul#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 162184059Swpaul#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 162284059Swpaul#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 162384059Swpaul#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 162484059Swpaul#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 162584059Swpaul 162684059Swpaul/* MSI status register */ 162784059Swpaul#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 162884059Swpaul#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 162984059Swpaul#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 163084059Swpaul#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 163184059Swpaul#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 163284059Swpaul 163384059Swpaul 163484059Swpaul/* 163584059Swpaul * DMA Completion registers 163684059Swpaul */ 163784059Swpaul#define BGE_DMAC_MODE 0x6400 163884059Swpaul 163984059Swpaul/* DMA Completion mode register */ 164084059Swpaul#define BGE_DMACMODE_RESET 0x00000001 164184059Swpaul#define BGE_DMACMODE_ENABLE 0x00000002 164284059Swpaul 164384059Swpaul 164484059Swpaul/* 164584059Swpaul * General control registers. 164684059Swpaul */ 164784059Swpaul#define BGE_MODE_CTL 0x6800 164884059Swpaul#define BGE_MISC_CFG 0x6804 164984059Swpaul#define BGE_MISC_LOCAL_CTL 0x6808 165084059Swpaul#define BGE_EE_ADDR 0x6838 165184059Swpaul#define BGE_EE_DATA 0x683C 165284059Swpaul#define BGE_EE_CTL 0x6840 165384059Swpaul#define BGE_MDI_CTL 0x6844 165484059Swpaul#define BGE_EE_DELAY 0x6848 165584059Swpaul 165684059Swpaul/* Mode control register */ 165784059Swpaul#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 165884059Swpaul#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 165984059Swpaul#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 166084059Swpaul#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 166184059Swpaul#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 166284059Swpaul#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 166384059Swpaul#define BGE_MODECTL_NO_RX_CRC 0x00000400 166484059Swpaul#define BGE_MODECTL_RX_BADFRAMES 0x00000800 166584059Swpaul#define BGE_MODECTL_NO_TX_INTR 0x00002000 166684059Swpaul#define BGE_MODECTL_NO_RX_INTR 0x00004000 166784059Swpaul#define BGE_MODECTL_FORCE_PCI32 0x00008000 166884059Swpaul#define BGE_MODECTL_STACKUP 0x00010000 166984059Swpaul#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 167084059Swpaul#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 167184059Swpaul#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 167284059Swpaul#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 167384059Swpaul#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 167484059Swpaul#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 167584059Swpaul#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 167684059Swpaul#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 167784059Swpaul#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 167884059Swpaul#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 167984059Swpaul 168084059Swpaul/* Misc. config register */ 168184059Swpaul#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 168284059Swpaul#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 168384059Swpaul 168484059Swpaul#define BGE_32BITTIME_66MHZ (0x41 << 1) 168584059Swpaul 168684059Swpaul/* Misc. Local Control */ 168784059Swpaul#define BGE_MLC_INTR_STATE 0x00000001 168884059Swpaul#define BGE_MLC_INTR_CLR 0x00000002 168984059Swpaul#define BGE_MLC_INTR_SET 0x00000004 169084059Swpaul#define BGE_MLC_INTR_ONATTN 0x00000008 169184059Swpaul#define BGE_MLC_MISCIO_IN0 0x00000100 169284059Swpaul#define BGE_MLC_MISCIO_IN1 0x00000200 169384059Swpaul#define BGE_MLC_MISCIO_IN2 0x00000400 169484059Swpaul#define BGE_MLC_MISCIO_OUTEN0 0x00000800 169584059Swpaul#define BGE_MLC_MISCIO_OUTEN1 0x00001000 169684059Swpaul#define BGE_MLC_MISCIO_OUTEN2 0x00002000 169784059Swpaul#define BGE_MLC_MISCIO_OUT0 0x00004000 169884059Swpaul#define BGE_MLC_MISCIO_OUT1 0x00008000 169984059Swpaul#define BGE_MLC_MISCIO_OUT2 0x00010000 170084059Swpaul#define BGE_MLC_EXTRAM_ENB 0x00020000 170184059Swpaul#define BGE_MLC_SRAM_SIZE 0x001C0000 170284059Swpaul#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 170384059Swpaul#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 170484059Swpaul#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 170584059Swpaul#define BGE_MLC_AUTO_EEPROM 0x01000000 170684059Swpaul 170784059Swpaul#define BGE_SSRAMSIZE_256KB 0x00000000 170884059Swpaul#define BGE_SSRAMSIZE_512KB 0x00040000 170984059Swpaul#define BGE_SSRAMSIZE_1MB 0x00080000 171084059Swpaul#define BGE_SSRAMSIZE_2MB 0x000C0000 171184059Swpaul#define BGE_SSRAMSIZE_4MB 0x00100000 171284059Swpaul#define BGE_SSRAMSIZE_8MB 0x00140000 171384059Swpaul#define BGE_SSRAMSIZE_16M 0x00180000 171484059Swpaul 171584059Swpaul/* EEPROM address register */ 171684059Swpaul#define BGE_EEADDR_ADDRESS 0x0000FFFC 171784059Swpaul#define BGE_EEADDR_HALFCLK 0x01FF0000 171884059Swpaul#define BGE_EEADDR_START 0x02000000 171984059Swpaul#define BGE_EEADDR_DEVID 0x1C000000 172084059Swpaul#define BGE_EEADDR_RESET 0x20000000 172184059Swpaul#define BGE_EEADDR_DONE 0x40000000 172284059Swpaul#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 172384059Swpaul 172484059Swpaul#define BGE_EEDEVID(x) ((x & 7) << 26) 172584059Swpaul#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 172684059Swpaul#define BGE_HALFCLK_384SCL 0x60 172784059Swpaul#define BGE_EE_READCMD \ 172884059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 172984059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 173084059Swpaul#define BGE_EE_WRCMD \ 173184059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 173284059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 173384059Swpaul 173484059Swpaul/* EEPROM Control register */ 173584059Swpaul#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 173684059Swpaul#define BGE_EECTL_CLKOUT 0x00000002 173784059Swpaul#define BGE_EECTL_CLKIN 0x00000004 173884059Swpaul#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 173984059Swpaul#define BGE_EECTL_DATAOUT 0x00000010 174084059Swpaul#define BGE_EECTL_DATAIN 0x00000020 174184059Swpaul 174284059Swpaul/* MDI (MII/GMII) access register */ 174384059Swpaul#define BGE_MDI_DATA 0x00000001 174484059Swpaul#define BGE_MDI_DIR 0x00000002 174584059Swpaul#define BGE_MDI_SEL 0x00000004 174684059Swpaul#define BGE_MDI_CLK 0x00000008 174784059Swpaul 174884059Swpaul#define BGE_MEMWIN_START 0x00008000 174984059Swpaul#define BGE_MEMWIN_END 0x0000FFFF 175084059Swpaul 175184059Swpaul 175284059Swpaul#define BGE_MEMWIN_READ(sc, x, val) \ 175384059Swpaul do { \ 175484059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 175584059Swpaul (0xFFFF0000 & x), 4); \ 175684059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 175784059Swpaul } while(0) 175884059Swpaul 175984059Swpaul#define BGE_MEMWIN_WRITE(sc, x, val) \ 176084059Swpaul do { \ 176184059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 176284059Swpaul (0xFFFF0000 & x), 4); \ 176384059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 176484059Swpaul } while(0) 176584059Swpaul 176684059Swpaul/* 176784059Swpaul * This magic number is used to prevent PXE restart when we 176884059Swpaul * issue a software reset. We write this magic number to the 176984059Swpaul * firmware mailbox at 0xB50 in order to prevent the PXE boot 177084059Swpaul * code from running. 177184059Swpaul */ 177284059Swpaul#define BGE_MAGIC_NUMBER 0x4B657654 177384059Swpaul 177484059Swpaultypedef struct { 1775159395Sglebius uint32_t bge_addr_hi; 1776159395Sglebius uint32_t bge_addr_lo; 177784059Swpaul} bge_hostaddr; 1778118026Swpaul 1779115200Sps#define BGE_HOSTADDR(x, y) \ 1780115200Sps do { \ 1781159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1782159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1783115200Sps } while(0) 178484059Swpaul 1785118026Swpaul#define BGE_ADDR_LO(y) \ 1786159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 1787118026Swpaul#define BGE_ADDR_HI(y) \ 1788159395Sglebius ((uint64_t) (y) >> 32) 1789118026Swpaul 179084059Swpaul/* Ring control block structure */ 179184059Swpaulstruct bge_rcb { 179284059Swpaul bge_hostaddr bge_hostaddr; 1793159395Sglebius uint32_t bge_maxlen_flags; 1794159395Sglebius uint32_t bge_nicaddr; 179584059Swpaul}; 1796153437Syongari 1797153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 1798153437Syongari bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1799153437Syongari rcb + offsetof(struct bge_rcb, offset), val) 1800108847Sjdp#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 180184059Swpaul 180284059Swpaul#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 180384059Swpaul#define BGE_RCB_FLAG_RING_DISABLED 0x0002 180484059Swpaul 180584059Swpaulstruct bge_tx_bd { 180684059Swpaul bge_hostaddr bge_addr; 1807153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1808159395Sglebius uint16_t bge_flags; 1809159395Sglebius uint16_t bge_len; 1810159395Sglebius uint16_t bge_vlan_tag; 1811159395Sglebius uint16_t bge_rsvd; 1812153437Syongari#else 1813159395Sglebius uint16_t bge_len; 1814159395Sglebius uint16_t bge_flags; 1815159395Sglebius uint16_t bge_rsvd; 1816159395Sglebius uint16_t bge_vlan_tag; 1817153437Syongari#endif 181884059Swpaul}; 181984059Swpaul 182084059Swpaul#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 182184059Swpaul#define BGE_TXBDFLAG_IP_CSUM 0x0002 182284059Swpaul#define BGE_TXBDFLAG_END 0x0004 182384059Swpaul#define BGE_TXBDFLAG_IP_FRAG 0x0008 182484059Swpaul#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 182584059Swpaul#define BGE_TXBDFLAG_VLAN_TAG 0x0040 182684059Swpaul#define BGE_TXBDFLAG_COAL_NOW 0x0080 182784059Swpaul#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 182884059Swpaul#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 182984059Swpaul#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 183084059Swpaul#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 183184059Swpaul#define BGE_TXBDFLAG_NO_CRC 0x8000 183284059Swpaul 183384059Swpaul#define BGE_NIC_TXRING_ADDR(ringno, size) \ 183484059Swpaul BGE_SEND_RING_1_TO_4 + \ 183584059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 183684059Swpaul 183784059Swpaulstruct bge_rx_bd { 183884059Swpaul bge_hostaddr bge_addr; 1839153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1840159395Sglebius uint16_t bge_len; 1841159395Sglebius uint16_t bge_idx; 1842159395Sglebius uint16_t bge_flags; 1843159395Sglebius uint16_t bge_type; 1844159395Sglebius uint16_t bge_tcp_udp_csum; 1845159395Sglebius uint16_t bge_ip_csum; 1846159395Sglebius uint16_t bge_vlan_tag; 1847159395Sglebius uint16_t bge_error_flag; 1848153437Syongari#else 1849159395Sglebius uint16_t bge_idx; 1850159395Sglebius uint16_t bge_len; 1851159395Sglebius uint16_t bge_type; 1852159395Sglebius uint16_t bge_flags; 1853159395Sglebius uint16_t bge_ip_csum; 1854159395Sglebius uint16_t bge_tcp_udp_csum; 1855159395Sglebius uint16_t bge_error_flag; 1856159395Sglebius uint16_t bge_vlan_tag; 1857153437Syongari#endif 1858159395Sglebius uint32_t bge_rsvd; 1859159395Sglebius uint32_t bge_opaque; 186084059Swpaul}; 186184059Swpaul 1862153239Sglebiusstruct bge_extrx_bd { 1863153239Sglebius bge_hostaddr bge_addr1; 1864153239Sglebius bge_hostaddr bge_addr2; 1865153239Sglebius bge_hostaddr bge_addr3; 1866153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1867159395Sglebius uint16_t bge_len2; 1868159395Sglebius uint16_t bge_len1; 1869159395Sglebius uint16_t bge_rsvd1; 1870159395Sglebius uint16_t bge_len3; 1871153437Syongari#else 1872159395Sglebius uint16_t bge_len1; 1873159395Sglebius uint16_t bge_len2; 1874159395Sglebius uint16_t bge_len3; 1875159395Sglebius uint16_t bge_rsvd1; 1876153437Syongari#endif 1877153239Sglebius bge_hostaddr bge_addr0; 1878153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1879159395Sglebius uint16_t bge_len0; 1880159395Sglebius uint16_t bge_idx; 1881159395Sglebius uint16_t bge_flags; 1882159395Sglebius uint16_t bge_type; 1883159395Sglebius uint16_t bge_tcp_udp_csum; 1884159395Sglebius uint16_t bge_ip_csum; 1885159395Sglebius uint16_t bge_vlan_tag; 1886159395Sglebius uint16_t bge_error_flag; 1887153437Syongari#else 1888159395Sglebius uint16_t bge_idx; 1889159395Sglebius uint16_t bge_len0; 1890159395Sglebius uint16_t bge_type; 1891159395Sglebius uint16_t bge_flags; 1892159395Sglebius uint16_t bge_ip_csum; 1893159395Sglebius uint16_t bge_tcp_udp_csum; 1894159395Sglebius uint16_t bge_error_flag; 1895159395Sglebius uint16_t bge_vlan_tag; 1896153437Syongari#endif 1897159395Sglebius uint32_t bge_rsvd0; 1898159395Sglebius uint32_t bge_opaque; 1899153239Sglebius}; 1900153239Sglebius 190184059Swpaul#define BGE_RXBDFLAG_END 0x0004 190284059Swpaul#define BGE_RXBDFLAG_JUMBO_RING 0x0020 190384059Swpaul#define BGE_RXBDFLAG_VLAN_TAG 0x0040 190484059Swpaul#define BGE_RXBDFLAG_ERROR 0x0400 190584059Swpaul#define BGE_RXBDFLAG_MINI_RING 0x0800 190684059Swpaul#define BGE_RXBDFLAG_IP_CSUM 0x1000 190784059Swpaul#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 190884059Swpaul#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 190984059Swpaul 191084059Swpaul#define BGE_RXERRFLAG_BAD_CRC 0x0001 191184059Swpaul#define BGE_RXERRFLAG_COLL_DETECT 0x0002 191284059Swpaul#define BGE_RXERRFLAG_LINK_LOST 0x0004 191384059Swpaul#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 191484059Swpaul#define BGE_RXERRFLAG_MAC_ABORT 0x0010 191584059Swpaul#define BGE_RXERRFLAG_RUNT 0x0020 191684059Swpaul#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 191784059Swpaul#define BGE_RXERRFLAG_GIANT 0x0080 191884059Swpaul 191984059Swpaulstruct bge_sts_idx { 1920153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1921159395Sglebius uint16_t bge_rx_prod_idx; 1922159395Sglebius uint16_t bge_tx_cons_idx; 1923153437Syongari#else 1924159395Sglebius uint16_t bge_tx_cons_idx; 1925159395Sglebius uint16_t bge_rx_prod_idx; 1926153437Syongari#endif 192784059Swpaul}; 192884059Swpaul 192984059Swpaulstruct bge_status_block { 1930159395Sglebius uint32_t bge_status; 1931159395Sglebius uint32_t bge_rsvd0; 1932153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1933159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 1934159395Sglebius uint16_t bge_rx_std_cons_idx; 1935159395Sglebius uint16_t bge_rx_mini_cons_idx; 1936159395Sglebius uint16_t bge_rsvd1; 1937153437Syongari#else 1938159395Sglebius uint16_t bge_rx_std_cons_idx; 1939159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 1940159395Sglebius uint16_t bge_rsvd1; 1941159395Sglebius uint16_t bge_rx_mini_cons_idx; 1942153437Syongari#endif 194384059Swpaul struct bge_sts_idx bge_idx[16]; 194484059Swpaul}; 194584059Swpaul 194684059Swpaul#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 194784059Swpaul#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 194884059Swpaul 194984059Swpaul#define BGE_STATFLAG_UPDATED 0x00000001 195084059Swpaul#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 195184059Swpaul#define BGE_STATFLAG_ERROR 0x00000004 195284059Swpaul 195384059Swpaul 195484059Swpaul/* 195584059Swpaul * Broadcom Vendor ID 195684059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 195784059Swpaul * even though they're now manufactured by Broadcom) 195884059Swpaul */ 195984059Swpaul#define BCOM_VENDORID 0x14E4 196084059Swpaul#define BCOM_DEVICEID_BCM5700 0x1644 196184059Swpaul#define BCOM_DEVICEID_BCM5701 0x1645 1962159637Sglebius#define BCOM_DEVICEID_BCM5702 0x1646 1963159637Sglebius#define BCOM_DEVICEID_BCM5702X 0x16A6 1964159637Sglebius#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 1965159637Sglebius#define BCOM_DEVICEID_BCM5703 0x1647 1966159637Sglebius#define BCOM_DEVICEID_BCM5703X 0x16A7 1967159637Sglebius#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 1968114547Sps#define BCOM_DEVICEID_BCM5704C 0x1648 1969114547Sps#define BCOM_DEVICEID_BCM5704S 0x16A8 1970159637Sglebius#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 1971117659Swpaul#define BCOM_DEVICEID_BCM5705 0x1653 1972129640Sps#define BCOM_DEVICEID_BCM5705K 0x1654 1973159637Sglebius#define BCOM_DEVICEID_BCM5705F 0x166E 1974117659Swpaul#define BCOM_DEVICEID_BCM5705M 0x165D 1975117659Swpaul#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1976146413Sps#define BCOM_DEVICEID_BCM5714C 0x1668 1977159637Sglebius#define BCOM_DEVICEID_BCM5714S 0x1669 1978159637Sglebius#define BCOM_DEVICEID_BCM5715 0x1678 1979159637Sglebius#define BCOM_DEVICEID_BCM5715S 0x1679 1980159637Sglebius#define BCOM_DEVICEID_BCM5720 0x1658 1981159637Sglebius#define BCOM_DEVICEID_BCM5721 0x1659 1982135772Sps#define BCOM_DEVICEID_BCM5750 0x1676 1983135772Sps#define BCOM_DEVICEID_BCM5750M 0x167C 1984135772Sps#define BCOM_DEVICEID_BCM5751 0x1677 1985159637Sglebius#define BCOM_DEVICEID_BCM5751F 0x167E 1986143448Savatar#define BCOM_DEVICEID_BCM5751M 0x167D 1987152452Sglebius#define BCOM_DEVICEID_BCM5752 0x1600 1988159637Sglebius#define BCOM_DEVICEID_BCM5752M 0x1601 1989159637Sglebius#define BCOM_DEVICEID_BCM5753 0x16F7 1990159637Sglebius#define BCOM_DEVICEID_BCM5753F 0x16FE 1991159637Sglebius#define BCOM_DEVICEID_BCM5753M 0x16FD 1992159637Sglebius#define BCOM_DEVICEID_BCM5780 0x166A 1993159637Sglebius#define BCOM_DEVICEID_BCM5780S 0x166B 1994159637Sglebius#define BCOM_DEVICEID_BCM5781 0x16DD 1995117659Swpaul#define BCOM_DEVICEID_BCM5782 0x1696 1996121810Swpaul#define BCOM_DEVICEID_BCM5788 0x169C 1997146485Ssilby#define BCOM_DEVICEID_BCM5789 0x169D 1998118814Swpaul#define BCOM_DEVICEID_BCM5901 0x170D 1999118814Swpaul#define BCOM_DEVICEID_BCM5901A2 0x170E 2000159637Sglebius#define BCOM_DEVICEID_BCM5903M 0x16FF 200184059Swpaul 200284059Swpaul/* 200384059Swpaul * Alteon AceNIC PCI vendor/device ID. 200484059Swpaul */ 2005159637Sglebius#define ALTEON_VENDORID 0x12AE 2006159637Sglebius#define ALTEON_DEVICEID_ACENIC 0x0001 2007159637Sglebius#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2008159637Sglebius#define ALTEON_DEVICEID_BCM5700 0x0003 2009159637Sglebius#define ALTEON_DEVICEID_BCM5701 0x0004 201084059Swpaul 201184059Swpaul/* 201284059Swpaul * 3Com 3c985 PCI vendor/device ID. 201384059Swpaul */ 201484059Swpaul#define TC_VENDORID 0x10B7 201584059Swpaul#define TC_DEVICEID_3C985 0x0001 201684059Swpaul#define TC_DEVICEID_3C996 0x0003 201784059Swpaul 201884059Swpaul/* 201984059Swpaul * SysKonnect PCI vendor ID 202084059Swpaul */ 202184059Swpaul#define SK_VENDORID 0x1148 202284059Swpaul#define SK_DEVICEID_ALTIMA 0x4400 202384059Swpaul#define SK_SUBSYSID_9D21 0x4421 202484059Swpaul#define SK_SUBSYSID_9D41 0x4441 202584059Swpaul 202684059Swpaul/* 202789835Sjdp * Altima PCI vendor/device ID. 202889835Sjdp */ 202989835Sjdp#define ALTIMA_VENDORID 0x173b 203089835Sjdp#define ALTIMA_DEVICE_AC1000 0x03e8 2031124257Swpaul#define ALTIMA_DEVICE_AC1002 0x03e9 2032137073Sdes#define ALTIMA_DEVICE_AC9100 0x03ea 203389835Sjdp 203489835Sjdp/* 2035119157Sambrisko * Dell PCI vendor ID 2036119157Sambrisko */ 2037119157Sambrisko 2038119157Sambrisko#define DELL_VENDORID 0x1028 2039119157Sambrisko 2040119157Sambrisko/* 2041159637Sglebius * Apple PCI vendor ID. 2042159637Sglebius */ 2043159637Sglebius#define APPLE_VENDORID 0x106b 2044159637Sglebius#define APPLE_DEVICE_BCM5701 0x1645 2045159637Sglebius 2046159637Sglebius/* 204784059Swpaul * Offset of MAC address inside EEPROM. 204884059Swpaul */ 204984059Swpaul#define BGE_EE_MAC_OFFSET 0x7C 205084059Swpaul#define BGE_EE_HWCFG_OFFSET 0xC8 205184059Swpaul 205293751Swpaul#define BGE_HWCFG_VOLTAGE 0x00000003 205393751Swpaul#define BGE_HWCFG_PHYLED_MODE 0x0000000C 205493751Swpaul#define BGE_HWCFG_MEDIA 0x00000030 205593751Swpaul 205693751Swpaul#define BGE_VOLTAGE_1POINT3 0x00000000 205793751Swpaul#define BGE_VOLTAGE_1POINT8 0x00000001 205893751Swpaul 205993751Swpaul#define BGE_PHYLEDMODE_UNSPEC 0x00000000 206093751Swpaul#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 206193751Swpaul#define BGE_PHYLEDMODE_SINGLELED 0x00000008 206293751Swpaul 206393751Swpaul#define BGE_MEDIA_UNSPEC 0x00000000 206493751Swpaul#define BGE_MEDIA_COPPER 0x00000010 206593751Swpaul#define BGE_MEDIA_FIBER 0x00000020 206693751Swpaul 206784059Swpaul#define BGE_PCI_READ_CMD 0x06000000 206884059Swpaul#define BGE_PCI_WRITE_CMD 0x70000000 206984059Swpaul 207084059Swpaul#define BGE_TICKS_PER_SEC 1000000 207184059Swpaul 207284059Swpaul/* 207384059Swpaul * Ring size constants. 207484059Swpaul */ 207584059Swpaul#define BGE_EVENT_RING_CNT 256 207684059Swpaul#define BGE_CMD_RING_CNT 64 207784059Swpaul#define BGE_STD_RX_RING_CNT 512 207884059Swpaul#define BGE_JUMBO_RX_RING_CNT 256 207984059Swpaul#define BGE_MINI_RX_RING_CNT 1024 208084059Swpaul#define BGE_RETURN_RING_CNT 1024 208184059Swpaul 2082117659Swpaul/* 5705 has smaller return ring size */ 2083117659Swpaul 2084117659Swpaul#define BGE_RETURN_RING_CNT_5705 512 2085117659Swpaul 208684059Swpaul/* 208784059Swpaul * Possible TX ring sizes. 208884059Swpaul */ 208984059Swpaul#define BGE_TX_RING_CNT_128 128 209084059Swpaul#define BGE_TX_RING_BASE_128 0x3800 209184059Swpaul 209284059Swpaul#define BGE_TX_RING_CNT_256 256 209384059Swpaul#define BGE_TX_RING_BASE_256 0x3000 209484059Swpaul 209584059Swpaul#define BGE_TX_RING_CNT_512 512 209684059Swpaul#define BGE_TX_RING_BASE_512 0x2000 209784059Swpaul 209884059Swpaul#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 209984059Swpaul#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 210084059Swpaul 210184059Swpaul/* 210284059Swpaul * Tigon III statistics counters. 210384059Swpaul */ 2104117659Swpaul/* Statistics maintained MAC Receive block. */ 2105117659Swpaulstruct bge_rx_mac_stats { 210684059Swpaul bge_hostaddr ifHCInOctets; 210784059Swpaul bge_hostaddr Reserved1; 210884059Swpaul bge_hostaddr etherStatsFragments; 210984059Swpaul bge_hostaddr ifHCInUcastPkts; 211084059Swpaul bge_hostaddr ifHCInMulticastPkts; 211184059Swpaul bge_hostaddr ifHCInBroadcastPkts; 211284059Swpaul bge_hostaddr dot3StatsFCSErrors; 211384059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 211484059Swpaul bge_hostaddr xonPauseFramesReceived; 211584059Swpaul bge_hostaddr xoffPauseFramesReceived; 211684059Swpaul bge_hostaddr macControlFramesReceived; 211784059Swpaul bge_hostaddr xoffStateEntered; 211884059Swpaul bge_hostaddr dot3StatsFramesTooLong; 211984059Swpaul bge_hostaddr etherStatsJabbers; 212084059Swpaul bge_hostaddr etherStatsUndersizePkts; 212184059Swpaul bge_hostaddr inRangeLengthError; 212284059Swpaul bge_hostaddr outRangeLengthError; 212384059Swpaul bge_hostaddr etherStatsPkts64Octets; 212484059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 212584059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 212684059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 212784059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 212884059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 212984059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 213084059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 213184059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 213284059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2133117659Swpaul}; 213484059Swpaul 213584059Swpaul 2136117659Swpaul/* Statistics maintained MAC Transmit block. */ 2137117659Swpaulstruct bge_tx_mac_stats { 213884059Swpaul bge_hostaddr ifHCOutOctets; 213984059Swpaul bge_hostaddr Reserved2; 214084059Swpaul bge_hostaddr etherStatsCollisions; 214184059Swpaul bge_hostaddr outXonSent; 214284059Swpaul bge_hostaddr outXoffSent; 214384059Swpaul bge_hostaddr flowControlDone; 214484059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 214584059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 214684059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 214784059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 214884059Swpaul bge_hostaddr Reserved3; 214984059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 215084059Swpaul bge_hostaddr dot3StatsLateCollisions; 215184059Swpaul bge_hostaddr dot3Collided2Times; 215284059Swpaul bge_hostaddr dot3Collided3Times; 215384059Swpaul bge_hostaddr dot3Collided4Times; 215484059Swpaul bge_hostaddr dot3Collided5Times; 215584059Swpaul bge_hostaddr dot3Collided6Times; 215684059Swpaul bge_hostaddr dot3Collided7Times; 215784059Swpaul bge_hostaddr dot3Collided8Times; 215884059Swpaul bge_hostaddr dot3Collided9Times; 215984059Swpaul bge_hostaddr dot3Collided10Times; 216084059Swpaul bge_hostaddr dot3Collided11Times; 216184059Swpaul bge_hostaddr dot3Collided12Times; 216284059Swpaul bge_hostaddr dot3Collided13Times; 216384059Swpaul bge_hostaddr dot3Collided14Times; 216484059Swpaul bge_hostaddr dot3Collided15Times; 216584059Swpaul bge_hostaddr ifHCOutUcastPkts; 216684059Swpaul bge_hostaddr ifHCOutMulticastPkts; 216784059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 216884059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 216984059Swpaul bge_hostaddr ifOutDiscards; 217084059Swpaul bge_hostaddr ifOutErrors; 2171117659Swpaul}; 217284059Swpaul 2173117659Swpaul/* Stats counters access through registers */ 2174117659Swpaulstruct bge_mac_stats_regs { 2175159395Sglebius uint32_t ifHCOutOctets; 2176159395Sglebius uint32_t Reserved0; 2177159395Sglebius uint32_t etherStatsCollisions; 2178159395Sglebius uint32_t outXonSent; 2179159395Sglebius uint32_t outXoffSent; 2180159395Sglebius uint32_t Reserved1; 2181159395Sglebius uint32_t dot3StatsInternalMacTransmitErrors; 2182159395Sglebius uint32_t dot3StatsSingleCollisionFrames; 2183159395Sglebius uint32_t dot3StatsMultipleCollisionFrames; 2184159395Sglebius uint32_t dot3StatsDeferredTransmissions; 2185159395Sglebius uint32_t Reserved2; 2186159395Sglebius uint32_t dot3StatsExcessiveCollisions; 2187159395Sglebius uint32_t dot3StatsLateCollisions; 2188159395Sglebius uint32_t Reserved3[14]; 2189159395Sglebius uint32_t ifHCOutUcastPkts; 2190159395Sglebius uint32_t ifHCOutMulticastPkts; 2191159395Sglebius uint32_t ifHCOutBroadcastPkts; 2192159395Sglebius uint32_t Reserved4[2]; 2193159395Sglebius uint32_t ifHCInOctets; 2194159395Sglebius uint32_t Reserved5; 2195159395Sglebius uint32_t etherStatsFragments; 2196159395Sglebius uint32_t ifHCInUcastPkts; 2197159395Sglebius uint32_t ifHCInMulticastPkts; 2198159395Sglebius uint32_t ifHCInBroadcastPkts; 2199159395Sglebius uint32_t dot3StatsFCSErrors; 2200159395Sglebius uint32_t dot3StatsAlignmentErrors; 2201159395Sglebius uint32_t xonPauseFramesReceived; 2202159395Sglebius uint32_t xoffPauseFramesReceived; 2203159395Sglebius uint32_t macControlFramesReceived; 2204159395Sglebius uint32_t xoffStateEntered; 2205159395Sglebius uint32_t dot3StatsFramesTooLong; 2206159395Sglebius uint32_t etherStatsJabbers; 2207159395Sglebius uint32_t etherStatsUndersizePkts; 2208117659Swpaul}; 2209117659Swpaul 2210117659Swpaulstruct bge_stats { 2211159395Sglebius uint8_t Reserved0[256]; 2212117659Swpaul 2213117659Swpaul /* Statistics maintained by Receive MAC. */ 2214117659Swpaul struct bge_rx_mac_stats rxstats; 2215117659Swpaul 2216117659Swpaul bge_hostaddr Unused1[37]; 2217117659Swpaul 2218117659Swpaul /* Statistics maintained by Transmit MAC. */ 2219117659Swpaul struct bge_tx_mac_stats txstats; 2220117659Swpaul 222184059Swpaul bge_hostaddr Unused2[31]; 222284059Swpaul 222384059Swpaul /* Statistics maintained by Receive List Placement. */ 222484059Swpaul bge_hostaddr COSIfHCInPkts[16]; 222584059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 222684059Swpaul bge_hostaddr nicDmaWriteQueueFull; 222784059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 222884059Swpaul bge_hostaddr nicNoMoreRxBDs; 222984059Swpaul bge_hostaddr ifInDiscards; 223084059Swpaul bge_hostaddr ifInErrors; 223184059Swpaul bge_hostaddr nicRecvThresholdHit; 223284059Swpaul 223384059Swpaul bge_hostaddr Unused3[9]; 223484059Swpaul 223584059Swpaul /* Statistics maintained by Send Data Initiator. */ 223684059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 223784059Swpaul bge_hostaddr nicDmaReadQueueFull; 223884059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 223984059Swpaul bge_hostaddr nicSendDataCompQueueFull; 224084059Swpaul 224184059Swpaul /* Statistics maintained by Host Coalescing. */ 224284059Swpaul bge_hostaddr nicRingSetSendProdIndex; 224384059Swpaul bge_hostaddr nicRingStatusUpdate; 224484059Swpaul bge_hostaddr nicInterrupts; 224584059Swpaul bge_hostaddr nicAvoidedInterrupts; 224684059Swpaul bge_hostaddr nicSendThresholdHit; 224784059Swpaul 2248159395Sglebius uint8_t Reserved4[320]; 224984059Swpaul}; 225084059Swpaul 225184059Swpaul/* 225284059Swpaul * Tigon general information block. This resides in host memory 225384059Swpaul * and contains the status counters, ring control blocks and 225484059Swpaul * producer pointers. 225584059Swpaul */ 225684059Swpaul 225784059Swpaulstruct bge_gib { 225884059Swpaul struct bge_stats bge_stats; 225984059Swpaul struct bge_rcb bge_tx_rcb[16]; 226084059Swpaul struct bge_rcb bge_std_rx_rcb; 226184059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 226284059Swpaul struct bge_rcb bge_mini_rx_rcb; 226384059Swpaul struct bge_rcb bge_return_rcb; 226484059Swpaul}; 226584059Swpaul 226684059Swpaul#define BGE_FRAMELEN 1518 226784059Swpaul#define BGE_MAX_FRAMELEN 1536 226884059Swpaul#define BGE_JUMBO_FRAMELEN 9018 226984059Swpaul#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 227084059Swpaul#define BGE_MIN_FRAMELEN 60 227184059Swpaul 227284059Swpaul/* 227384059Swpaul * Other utility macros. 227484059Swpaul */ 227584059Swpaul#define BGE_INC(x, y) (x) = (x + 1) % y 227684059Swpaul 227784059Swpaul/* 227884059Swpaul * Vital product data and structures. 227984059Swpaul */ 228084059Swpaul#define BGE_VPD_FLAG 0x8000 2281137073Sdes 228284059Swpaul/* VPD structures */ 228384059Swpaulstruct vpd_res { 2284159395Sglebius uint8_t vr_id; 2285159395Sglebius uint8_t vr_len; 2286159395Sglebius uint8_t vr_pad; 228784059Swpaul}; 2288137073Sdes 228984059Swpaulstruct vpd_key { 229084059Swpaul char vk_key[2]; 2291159395Sglebius uint8_t vk_len; 229284059Swpaul}; 2293137073Sdes 229484059Swpaul#define VPD_RES_ID 0x82 /* ID string */ 229584059Swpaul#define VPD_RES_READ 0x90 /* start of read only area */ 229684059Swpaul#define VPD_RES_WRITE 0x81 /* start of read/write area */ 229784059Swpaul#define VPD_RES_END 0x78 /* end tag */ 229884059Swpaul 229984059Swpaul 230084059Swpaul/* 230184059Swpaul * Register access macros. The Tigon always uses memory mapped register 230284059Swpaul * accesses and all registers must be accessed with 32 bit operations. 230384059Swpaul */ 230484059Swpaul 230584059Swpaul#define CSR_WRITE_4(sc, reg, val) \ 230684059Swpaul bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 230784059Swpaul 230884059Swpaul#define CSR_READ_4(sc, reg) \ 230984059Swpaul bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 231084059Swpaul 231184059Swpaul#define BGE_SETBIT(sc, reg, x) \ 2312106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 231384059Swpaul#define BGE_CLRBIT(sc, reg, x) \ 2314106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 231584059Swpaul 231684059Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 2317106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 231884059Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 2319106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 232084059Swpaul 232184059Swpaul/* 232284059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 232384059Swpaul * values are tuneable. They control the actual amount of buffers 232484059Swpaul * allocated for the standard, mini and jumbo receive rings. 232584059Swpaul */ 232684059Swpaul 232784059Swpaul#define BGE_SSLOTS 256 232884059Swpaul#define BGE_MSLOTS 256 232984059Swpaul#define BGE_JSLOTS 384 233084059Swpaul 233184059Swpaul#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2332159395Sglebius#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2333159395Sglebius (BGE_JRAWLEN % sizeof(uint64_t)))) 233484059Swpaul#define BGE_JPAGESZ PAGE_SIZE 233584059Swpaul#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 233684059Swpaul#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 233784059Swpaul 2338154519Sglebius#define BGE_NSEG_JUMBO 4 2339153239Sglebius#define BGE_NSEG_NEW 32 2340153239Sglebius 234184059Swpaul/* 234284059Swpaul * Ring structures. Most of these reside in host memory and we tell 234384059Swpaul * the NIC where they are via the ring control blocks. The exceptions 234484059Swpaul * are the tx and command rings, which live in NIC memory and which 234584059Swpaul * we access via the shared memory window. 234684059Swpaul */ 2347118026Swpaul 234884059Swpaulstruct bge_ring_data { 2349118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2350118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2351153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2352118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2353118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2354118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2355118026Swpaul struct bge_tx_bd *bge_tx_ring; 2356118026Swpaul bus_addr_t bge_tx_ring_paddr; 2357118026Swpaul struct bge_status_block *bge_status_block; 2358118026Swpaul bus_addr_t bge_status_block_paddr; 2359118026Swpaul struct bge_stats *bge_stats; 2360118026Swpaul bus_addr_t bge_stats_paddr; 236184059Swpaul struct bge_gib bge_info; 236284059Swpaul}; 236384059Swpaul 2364118026Swpaul#define BGE_STD_RX_RING_SZ \ 2365118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2366118026Swpaul#define BGE_JUMBO_RX_RING_SZ \ 2367153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2368118026Swpaul#define BGE_TX_RING_SZ \ 2369118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2370118026Swpaul#define BGE_RX_RTN_RING_SZ(x) \ 2371118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2372118026Swpaul 2373118026Swpaul#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2374118026Swpaul 2375118026Swpaul#define BGE_STATS_SZ sizeof (struct bge_stats) 2376118026Swpaul 237784059Swpaul/* 237884059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 237984059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 238084059Swpaul * not the other way around. 238184059Swpaul */ 238284059Swpaulstruct bge_chain_data { 2383118026Swpaul bus_dma_tag_t bge_parent_tag; 2384118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2385118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2386118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2387118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2388118026Swpaul bus_dma_tag_t bge_status_tag; 2389118026Swpaul bus_dma_tag_t bge_stats_tag; 2390118026Swpaul bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2391118026Swpaul bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2392118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2393118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2394118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2395118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2396118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2397118026Swpaul bus_dmamap_t bge_tx_ring_map; 2398118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2399118026Swpaul bus_dmamap_t bge_status_map; 2400118026Swpaul bus_dmamap_t bge_stats_map; 240184059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 240284059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 240384059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 240484059Swpaul}; 240584059Swpaul 2406118026Swpaulstruct bge_dmamap_arg { 2407118026Swpaul struct bge_softc *sc; 2408118026Swpaul bus_addr_t bge_busaddr; 2409159395Sglebius uint16_t bge_flags; 2410118026Swpaul int bge_idx; 2411118026Swpaul int bge_maxsegs; 2412118026Swpaul struct bge_tx_bd *bge_ring; 2413118026Swpaul}; 2414118026Swpaul 241584059Swpaul#define BGE_HWREV_TIGON 0x01 241684059Swpaul#define BGE_HWREV_TIGON_II 0x02 2417117659Swpaul#define BGE_TIMEOUT 100000 241884059Swpaul#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 241984059Swpaul 242084059Swpaulstruct bge_bcom_hack { 242184059Swpaul int reg; 242284059Swpaul int val; 242384059Swpaul}; 242484059Swpaul 242584059Swpaulstruct bge_softc { 2426147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 242784059Swpaul device_t bge_dev; 2428122497Ssam struct mtx bge_mtx; 242984059Swpaul device_t bge_miibus; 243084059Swpaul bus_space_handle_t bge_bhandle; 243184059Swpaul bus_space_tag_t bge_btag; 243284059Swpaul void *bge_intrhand; 243384059Swpaul struct resource *bge_irq; 243484059Swpaul struct resource *bge_res; 243584059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2436159395Sglebius uint8_t bge_extram; /* has external SSRAM */ 2437159395Sglebius uint8_t bge_tbi; 2438159395Sglebius uint8_t bge_rx_alignment_bug; 2439159395Sglebius uint32_t bge_chipid; 2440159395Sglebius uint8_t bge_asicrev; 2441159395Sglebius uint8_t bge_chiprev; 2442159395Sglebius uint8_t bge_no_3_led; 2443159395Sglebius uint8_t bge_pcie; 2444159637Sglebius uint8_t bge_pcix; 2445118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 244684059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 2447159395Sglebius uint16_t bge_tx_saved_considx; 2448159395Sglebius uint16_t bge_rx_saved_considx; 2449159395Sglebius uint16_t bge_ev_saved_considx; 2450159395Sglebius uint16_t bge_return_ring_cnt; 2451159395Sglebius uint16_t bge_std; /* current std ring head */ 2452159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 2453159395Sglebius uint32_t bge_stat_ticks; 2454159395Sglebius uint32_t bge_rx_coal_ticks; 2455159395Sglebius uint32_t bge_tx_coal_ticks; 2456159395Sglebius uint32_t bge_tx_prodidx; 2457159395Sglebius uint32_t bge_rx_max_coal_bds; 2458159395Sglebius uint32_t bge_tx_max_coal_bds; 2459159395Sglebius uint32_t bge_tx_buf_ratio; 246084059Swpaul int bge_if_flags; 246184059Swpaul int bge_txcnt; 2462155180Soleg int bge_link; /* link state */ 2463155180Soleg int bge_link_evt; /* pending link event */ 2464122497Ssam struct callout bge_stat_ch; 246584059Swpaul char *bge_vpd_prodname; 246684059Swpaul char *bge_vpd_readonly; 2467154492Soleg u_long bge_rx_discards; 2468154492Soleg u_long bge_tx_discards; 2469154492Soleg u_long bge_tx_collisions; 2470151553Sglebius#ifdef DEVICE_POLLING 2471151553Sglebius int rxcycles; 2472151553Sglebius#endif /* DEVICE_POLLING */ 247384059Swpaul}; 2474122497Ssam 2475122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2476122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2477122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2478122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2479122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2480122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2481