if_bgereg.h revision 159395
1139749Simp/*- 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 159395 2006-06-08 09:35:02Z glebius $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 6484059Swpaul#define BGE_PAGE_ZERO 0x00000000 6584059Swpaul#define BGE_PAGE_ZERO_END 0x000000FF 6684059Swpaul#define BGE_SEND_RING_RCB 0x00000100 6784059Swpaul#define BGE_SEND_RING_RCB_END 0x000001FF 6884059Swpaul#define BGE_RX_RETURN_RING_RCB 0x00000200 6984059Swpaul#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 7084059Swpaul#define BGE_STATS_BLOCK 0x00000300 7184059Swpaul#define BGE_STATS_BLOCK_END 0x00000AFF 7284059Swpaul#define BGE_STATUS_BLOCK 0x00000B00 7384059Swpaul#define BGE_STATUS_BLOCK_END 0x00000B4F 7484059Swpaul#define BGE_SOFTWARE_GENCOMM 0x00000B50 75110367Sps#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76110367Sps#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 7784059Swpaul#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 7884059Swpaul#define BGE_UNMAPPED 0x00001000 7984059Swpaul#define BGE_UNMAPPED_END 0x00001FFF 8084059Swpaul#define BGE_DMA_DESCRIPTORS 0x00002000 8184059Swpaul#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 8284059Swpaul#define BGE_SEND_RING_1_TO_4 0x00004000 8384059Swpaul#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8484059Swpaul 8584059Swpaul/* Mappings for internal memory configuration */ 8684059Swpaul#define BGE_STD_RX_RINGS 0x00006000 8784059Swpaul#define BGE_STD_RX_RINGS_END 0x00006FFF 8884059Swpaul#define BGE_JUMBO_RX_RINGS 0x00007000 8984059Swpaul#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 9084059Swpaul#define BGE_BUFFPOOL_1 0x00008000 9184059Swpaul#define BGE_BUFFPOOL_1_END 0x0000FFFF 9284059Swpaul#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 9384059Swpaul#define BGE_BUFFPOOL_2_END 0x00017FFF 9484059Swpaul#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 9584059Swpaul#define BGE_BUFFPOOL_3_END 0x0001FFFF 9684059Swpaul 9784059Swpaul/* Mappings for external SSRAM configurations */ 9884059Swpaul#define BGE_SEND_RING_5_TO_6 0x00006000 9984059Swpaul#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 10084059Swpaul#define BGE_SEND_RING_7_TO_8 0x00007000 10184059Swpaul#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 10284059Swpaul#define BGE_SEND_RING_9_TO_16 0x00008000 10384059Swpaul#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 10484059Swpaul#define BGE_EXT_STD_RX_RINGS 0x0000C000 10584059Swpaul#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 10684059Swpaul#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 10784059Swpaul#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 10884059Swpaul#define BGE_MINI_RX_RINGS 0x0000E000 10984059Swpaul#define BGE_MINI_RX_RINGS_END 0x0000FFFF 11084059Swpaul#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 11184059Swpaul#define BGE_AVAIL_REGION1_END 0x00017FFF 11284059Swpaul#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 11384059Swpaul#define BGE_AVAIL_REGION2_END 0x0001FFFF 11484059Swpaul#define BGE_EXT_SSRAM 0x00020000 11584059Swpaul#define BGE_EXT_SSRAM_END 0x000FFFFF 11684059Swpaul 11784059Swpaul 11884059Swpaul/* 11984059Swpaul * BCM570x register offsets. These are memory mapped registers 12084059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12184059Swpaul * Each register must be accessed using 32 bit operations. 12284059Swpaul * 12384059Swpaul * All registers are accessed through a 32K shared memory block. 12484059Swpaul * The first group of registers are actually copies of the PCI 12584059Swpaul * configuration space registers. 12684059Swpaul */ 12784059Swpaul 12884059Swpaul/* 12984059Swpaul * PCI registers defined in the PCI 2.2 spec. 13084059Swpaul */ 13184059Swpaul#define BGE_PCI_VID 0x00 13284059Swpaul#define BGE_PCI_DID 0x02 13384059Swpaul#define BGE_PCI_CMD 0x04 13484059Swpaul#define BGE_PCI_STS 0x06 13584059Swpaul#define BGE_PCI_REV 0x08 13684059Swpaul#define BGE_PCI_CLASS 0x09 13784059Swpaul#define BGE_PCI_CACHESZ 0x0C 13884059Swpaul#define BGE_PCI_LATTIMER 0x0D 13984059Swpaul#define BGE_PCI_HDRTYPE 0x0E 14084059Swpaul#define BGE_PCI_BIST 0x0F 14184059Swpaul#define BGE_PCI_BAR0 0x10 14284059Swpaul#define BGE_PCI_BAR1 0x14 14384059Swpaul#define BGE_PCI_SUBSYS 0x2C 14484059Swpaul#define BGE_PCI_SUBVID 0x2E 14584059Swpaul#define BGE_PCI_ROMBASE 0x30 14684059Swpaul#define BGE_PCI_CAPPTR 0x34 14784059Swpaul#define BGE_PCI_INTLINE 0x3C 14884059Swpaul#define BGE_PCI_INTPIN 0x3D 14984059Swpaul#define BGE_PCI_MINGNT 0x3E 15084059Swpaul#define BGE_PCI_MAXLAT 0x3F 15184059Swpaul#define BGE_PCI_PCIXCAP 0x40 15284059Swpaul#define BGE_PCI_NEXTPTR_PM 0x41 15384059Swpaul#define BGE_PCI_PCIX_CMD 0x42 15484059Swpaul#define BGE_PCI_PCIX_STS 0x44 15584059Swpaul#define BGE_PCI_PWRMGMT_CAPID 0x48 15684059Swpaul#define BGE_PCI_NEXTPTR_VPD 0x49 15784059Swpaul#define BGE_PCI_PWRMGMT_CAPS 0x4A 15884059Swpaul#define BGE_PCI_PWRMGMT_CMD 0x4C 15984059Swpaul#define BGE_PCI_PWRMGMT_STS 0x4D 16084059Swpaul#define BGE_PCI_PWRMGMT_DATA 0x4F 16184059Swpaul#define BGE_PCI_VPD_CAPID 0x50 16284059Swpaul#define BGE_PCI_NEXTPTR_MSI 0x51 16384059Swpaul#define BGE_PCI_VPD_ADDR 0x52 16484059Swpaul#define BGE_PCI_VPD_DATA 0x54 16584059Swpaul#define BGE_PCI_MSI_CAPID 0x58 16684059Swpaul#define BGE_PCI_NEXTPTR_NONE 0x59 16784059Swpaul#define BGE_PCI_MSI_CTL 0x5A 16884059Swpaul#define BGE_PCI_MSI_ADDR_HI 0x5C 16984059Swpaul#define BGE_PCI_MSI_ADDR_LO 0x60 17084059Swpaul#define BGE_PCI_MSI_DATA 0x64 17184059Swpaul 172135772Sps/* PCI MSI. ??? */ 173135772Sps#define BGE_PCIE_CAPID_REG 0xD0 174135772Sps#define BGE_PCIE_CAPID 0x10 175135772Sps 17684059Swpaul/* 17784059Swpaul * PCI registers specific to the BCM570x family. 17884059Swpaul */ 17984059Swpaul#define BGE_PCI_MISC_CTL 0x68 18084059Swpaul#define BGE_PCI_DMA_RW_CTL 0x6C 18184059Swpaul#define BGE_PCI_PCISTATE 0x70 18284059Swpaul#define BGE_PCI_CLKCTL 0x74 18384059Swpaul#define BGE_PCI_REG_BASEADDR 0x78 18484059Swpaul#define BGE_PCI_MEMWIN_BASEADDR 0x7C 18584059Swpaul#define BGE_PCI_REG_DATA 0x80 18684059Swpaul#define BGE_PCI_MEMWIN_DATA 0x84 18784059Swpaul#define BGE_PCI_MODECTL 0x88 18884059Swpaul#define BGE_PCI_MISC_CFG 0x8C 18984059Swpaul#define BGE_PCI_MISC_LOCALCTL 0x90 19084059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 19184059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 19284059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 19384059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 19484059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 19584059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 19684059Swpaul#define BGE_PCI_ISR_MBX_HI 0xB0 19784059Swpaul#define BGE_PCI_ISR_MBX_LO 0xB4 19884059Swpaul 19984059Swpaul/* PCI Misc. Host control register */ 20084059Swpaul#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 20184059Swpaul#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 20284059Swpaul#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 20384059Swpaul#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 20484059Swpaul#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 20584059Swpaul#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 20684059Swpaul#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 20784059Swpaul#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 20884059Swpaul#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 20984059Swpaul 210153437Syongari#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 211153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 212153437Syongari#define BGE_DMA_SWAP_OPTIONS \ 213153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME| \ 214153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 215153437Syongari#else 216153437Syongari#define BGE_DMA_SWAP_OPTIONS \ 217153437Syongari BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 218153437Syongari BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 219153437Syongari#endif 22084059Swpaul 221153437Syongari#define BGE_INIT \ 222153437Syongari (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 223153437Syongari BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 22484059Swpaul 225114813Sps#define BGE_CHIPID_TIGON_I 0x40000000 226114813Sps#define BGE_CHIPID_TIGON_II 0x60000000 227114813Sps#define BGE_CHIPID_BCM5700_B0 0x71000000 228114813Sps#define BGE_CHIPID_BCM5700_B1 0x71020000 229114813Sps#define BGE_CHIPID_BCM5700_B2 0x71030000 230114813Sps#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 231114813Sps#define BGE_CHIPID_BCM5700_C0 0x72000000 232114813Sps#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 233114813Sps#define BGE_CHIPID_BCM5701_B0 0x01000000 234114813Sps#define BGE_CHIPID_BCM5701_B2 0x01020000 235114813Sps#define BGE_CHIPID_BCM5701_B5 0x01050000 236114813Sps#define BGE_CHIPID_BCM5703_A0 0x10000000 237114813Sps#define BGE_CHIPID_BCM5703_A1 0x10010000 238114813Sps#define BGE_CHIPID_BCM5703_A2 0x10020000 239114813Sps#define BGE_CHIPID_BCM5704_A0 0x20000000 240114813Sps#define BGE_CHIPID_BCM5704_A1 0x20010000 241114813Sps#define BGE_CHIPID_BCM5704_A2 0x20020000 242117659Swpaul#define BGE_CHIPID_BCM5705_A0 0x30000000 243117659Swpaul#define BGE_CHIPID_BCM5705_A1 0x30010000 244117659Swpaul#define BGE_CHIPID_BCM5705_A2 0x30020000 245117659Swpaul#define BGE_CHIPID_BCM5705_A3 0x30030000 246135772Sps#define BGE_CHIPID_BCM5750_A0 0x40000000 247135772Sps#define BGE_CHIPID_BCM5750_A1 0x40010000 248146413Sps#define BGE_CHIPID_BCM5714_A0 0x50000000 24984059Swpaul 25093751Swpaul/* shorthand one */ 251114615Sps#define BGE_ASICREV(x) ((x) >> 28) 252114615Sps#define BGE_ASICREV_BCM5700 0x07 253114615Sps#define BGE_ASICREV_BCM5701 0x00 254114615Sps#define BGE_ASICREV_BCM5703 0x01 255114615Sps#define BGE_ASICREV_BCM5704 0x02 256117659Swpaul#define BGE_ASICREV_BCM5705 0x03 257135772Sps#define BGE_ASICREV_BCM5750 0x04 258146413Sps#define BGE_ASICREV_BCM5714 0x05 259152452Sglebius#define BGE_ASICREV_BCM5752 0x06 26093751Swpaul 261114813Sps/* chip revisions */ 262114813Sps#define BGE_CHIPREV(x) ((x) >> 24) 263114813Sps#define BGE_CHIPREV_5700_AX 0x70 264114813Sps#define BGE_CHIPREV_5700_BX 0x71 265114813Sps#define BGE_CHIPREV_5700_CX 0x72 266114813Sps#define BGE_CHIPREV_5701_AX 0x00 267114813Sps 26884059Swpaul/* PCI DMA Read/Write Control register */ 26984059Swpaul#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 27084059Swpaul#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 27184059Swpaul#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 27284059Swpaul#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 27384059Swpaul#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 274114615Sps# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 27584059Swpaul#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 276114615Sps# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 27784059Swpaul#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 27884059Swpaul#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 27984059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 280114615Sps# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 28184059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 282114615Sps# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 28384059Swpaul 28484059Swpaul#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 28584059Swpaul#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 28684059Swpaul#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 28784059Swpaul#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 28884059Swpaul#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 28984059Swpaul#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 29084059Swpaul#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 29184059Swpaul#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 29284059Swpaul 29384059Swpaul#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 29484059Swpaul#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 29584059Swpaul#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 29684059Swpaul#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 29784059Swpaul#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 29884059Swpaul#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 29984059Swpaul#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 30084059Swpaul#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 30184059Swpaul 30284059Swpaul/* 30384059Swpaul * PCI state register -- note, this register is read only 30484059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 30584059Swpaul * register is set. 30684059Swpaul */ 30784059Swpaul#define BGE_PCISTATE_FORCE_RESET 0x00000001 30884059Swpaul#define BGE_PCISTATE_INTR_STATE 0x00000002 30984059Swpaul#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 31084059Swpaul#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 31184059Swpaul#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 31284059Swpaul#define BGE_PCISTATE_WANT_EXPROM 0x00000020 31384059Swpaul#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 31484059Swpaul#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 31584059Swpaul#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 31684059Swpaul 31784059Swpaul/* 31884059Swpaul * PCI Clock Control register -- note, this register is read only 31984059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 32084059Swpaul * register is set. 32184059Swpaul */ 32284059Swpaul#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 32384059Swpaul#define BGE_PCICLOCKCTL_M66EN 0x00000080 32484059Swpaul#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 32584059Swpaul#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 32684059Swpaul#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 32784059Swpaul#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 32884059Swpaul#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 32984059Swpaul#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 33084059Swpaul#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 33184059Swpaul#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 33284059Swpaul 33384059Swpaul 33484059Swpaul#ifndef PCIM_CMD_MWIEN 33584059Swpaul#define PCIM_CMD_MWIEN 0x0010 33684059Swpaul#endif 33784059Swpaul 33884059Swpaul/* 33984059Swpaul * High priority mailbox registers 34084059Swpaul * Each mailbox is 64-bits wide, though we only use the 34184059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 34284059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 34384059Swpaul * has been updated. 34484059Swpaul */ 34584059Swpaul#define BGE_MBX_IRQ0_HI 0x0200 34684059Swpaul#define BGE_MBX_IRQ0_LO 0x0204 34784059Swpaul#define BGE_MBX_IRQ1_HI 0x0208 34884059Swpaul#define BGE_MBX_IRQ1_LO 0x020C 34984059Swpaul#define BGE_MBX_IRQ2_HI 0x0210 35084059Swpaul#define BGE_MBX_IRQ2_LO 0x0214 35184059Swpaul#define BGE_MBX_IRQ3_HI 0x0218 35284059Swpaul#define BGE_MBX_IRQ3_LO 0x021C 35384059Swpaul#define BGE_MBX_GEN0_HI 0x0220 35484059Swpaul#define BGE_MBX_GEN0_LO 0x0224 35584059Swpaul#define BGE_MBX_GEN1_HI 0x0228 35684059Swpaul#define BGE_MBX_GEN1_LO 0x022C 35784059Swpaul#define BGE_MBX_GEN2_HI 0x0230 35884059Swpaul#define BGE_MBX_GEN2_LO 0x0234 35984059Swpaul#define BGE_MBX_GEN3_HI 0x0228 36084059Swpaul#define BGE_MBX_GEN3_LO 0x022C 36184059Swpaul#define BGE_MBX_GEN4_HI 0x0240 36284059Swpaul#define BGE_MBX_GEN4_LO 0x0244 36384059Swpaul#define BGE_MBX_GEN5_HI 0x0248 36484059Swpaul#define BGE_MBX_GEN5_LO 0x024C 36584059Swpaul#define BGE_MBX_GEN6_HI 0x0250 36684059Swpaul#define BGE_MBX_GEN6_LO 0x0254 36784059Swpaul#define BGE_MBX_GEN7_HI 0x0258 36884059Swpaul#define BGE_MBX_GEN7_LO 0x025C 36984059Swpaul#define BGE_MBX_RELOAD_STATS_HI 0x0260 37084059Swpaul#define BGE_MBX_RELOAD_STATS_LO 0x0264 37184059Swpaul#define BGE_MBX_RX_STD_PROD_HI 0x0268 37284059Swpaul#define BGE_MBX_RX_STD_PROD_LO 0x026C 37384059Swpaul#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 37484059Swpaul#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 37584059Swpaul#define BGE_MBX_RX_MINI_PROD_HI 0x0278 37684059Swpaul#define BGE_MBX_RX_MINI_PROD_LO 0x027C 37784059Swpaul#define BGE_MBX_RX_CONS0_HI 0x0280 37884059Swpaul#define BGE_MBX_RX_CONS0_LO 0x0284 37984059Swpaul#define BGE_MBX_RX_CONS1_HI 0x0288 38084059Swpaul#define BGE_MBX_RX_CONS1_LO 0x028C 38184059Swpaul#define BGE_MBX_RX_CONS2_HI 0x0290 38284059Swpaul#define BGE_MBX_RX_CONS2_LO 0x0294 38384059Swpaul#define BGE_MBX_RX_CONS3_HI 0x0298 38484059Swpaul#define BGE_MBX_RX_CONS3_LO 0x029C 38584059Swpaul#define BGE_MBX_RX_CONS4_HI 0x02A0 38684059Swpaul#define BGE_MBX_RX_CONS4_LO 0x02A4 38784059Swpaul#define BGE_MBX_RX_CONS5_HI 0x02A8 38884059Swpaul#define BGE_MBX_RX_CONS5_LO 0x02AC 38984059Swpaul#define BGE_MBX_RX_CONS6_HI 0x02B0 39084059Swpaul#define BGE_MBX_RX_CONS6_LO 0x02B4 39184059Swpaul#define BGE_MBX_RX_CONS7_HI 0x02B8 39284059Swpaul#define BGE_MBX_RX_CONS7_LO 0x02BC 39384059Swpaul#define BGE_MBX_RX_CONS8_HI 0x02C0 39484059Swpaul#define BGE_MBX_RX_CONS8_LO 0x02C4 39584059Swpaul#define BGE_MBX_RX_CONS9_HI 0x02C8 39684059Swpaul#define BGE_MBX_RX_CONS9_LO 0x02CC 39784059Swpaul#define BGE_MBX_RX_CONS10_HI 0x02D0 39884059Swpaul#define BGE_MBX_RX_CONS10_LO 0x02D4 39984059Swpaul#define BGE_MBX_RX_CONS11_HI 0x02D8 40084059Swpaul#define BGE_MBX_RX_CONS11_LO 0x02DC 40184059Swpaul#define BGE_MBX_RX_CONS12_HI 0x02E0 40284059Swpaul#define BGE_MBX_RX_CONS12_LO 0x02E4 40384059Swpaul#define BGE_MBX_RX_CONS13_HI 0x02E8 40484059Swpaul#define BGE_MBX_RX_CONS13_LO 0x02EC 40584059Swpaul#define BGE_MBX_RX_CONS14_HI 0x02F0 40684059Swpaul#define BGE_MBX_RX_CONS14_LO 0x02F4 40784059Swpaul#define BGE_MBX_RX_CONS15_HI 0x02F8 40884059Swpaul#define BGE_MBX_RX_CONS15_LO 0x02FC 40984059Swpaul#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 41084059Swpaul#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 41184059Swpaul#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 41284059Swpaul#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 41384059Swpaul#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 41484059Swpaul#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 41584059Swpaul#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 41684059Swpaul#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 41784059Swpaul#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 41884059Swpaul#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 41984059Swpaul#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 42084059Swpaul#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 42184059Swpaul#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 42284059Swpaul#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 42384059Swpaul#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 42484059Swpaul#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 42584059Swpaul#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 42684059Swpaul#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 42784059Swpaul#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 42884059Swpaul#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 42984059Swpaul#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 43084059Swpaul#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 43184059Swpaul#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 43284059Swpaul#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 43384059Swpaul#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 43484059Swpaul#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 43584059Swpaul#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 43684059Swpaul#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 43784059Swpaul#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 43884059Swpaul#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 43984059Swpaul#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 44084059Swpaul#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 44184059Swpaul#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 44284059Swpaul#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 44384059Swpaul#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 44484059Swpaul#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 44584059Swpaul#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 44684059Swpaul#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 44784059Swpaul#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 44884059Swpaul#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 44984059Swpaul#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 45084059Swpaul#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 45184059Swpaul#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 45284059Swpaul#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 45384059Swpaul#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 45484059Swpaul#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 45584059Swpaul#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 45684059Swpaul#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 45784059Swpaul#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 45884059Swpaul#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 45984059Swpaul#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 46084059Swpaul#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 46184059Swpaul#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 46284059Swpaul#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 46384059Swpaul#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 46484059Swpaul#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 46584059Swpaul#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 46684059Swpaul#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 46784059Swpaul#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 46884059Swpaul#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 46984059Swpaul#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 47084059Swpaul#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 47184059Swpaul#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 47284059Swpaul#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 47384059Swpaul 47484059Swpaul#define BGE_TX_RINGS_MAX 4 47584059Swpaul#define BGE_TX_RINGS_EXTSSRAM_MAX 16 47684059Swpaul#define BGE_RX_RINGS_MAX 16 47784059Swpaul 47884059Swpaul/* Ethernet MAC control registers */ 47984059Swpaul#define BGE_MAC_MODE 0x0400 48084059Swpaul#define BGE_MAC_STS 0x0404 48184059Swpaul#define BGE_MAC_EVT_ENB 0x0408 48284059Swpaul#define BGE_MAC_LED_CTL 0x040C 48384059Swpaul#define BGE_MAC_ADDR1_LO 0x0410 48484059Swpaul#define BGE_MAC_ADDR1_HI 0x0414 48584059Swpaul#define BGE_MAC_ADDR2_LO 0x0418 48684059Swpaul#define BGE_MAC_ADDR2_HI 0x041C 48784059Swpaul#define BGE_MAC_ADDR3_LO 0x0420 48884059Swpaul#define BGE_MAC_ADDR3_HI 0x0424 48984059Swpaul#define BGE_MAC_ADDR4_LO 0x0428 49084059Swpaul#define BGE_MAC_ADDR4_HI 0x042C 49184059Swpaul#define BGE_WOL_PATPTR 0x0430 49284059Swpaul#define BGE_WOL_PATCFG 0x0434 49384059Swpaul#define BGE_TX_RANDOM_BACKOFF 0x0438 49484059Swpaul#define BGE_RX_MTU 0x043C 49584059Swpaul#define BGE_GBIT_PCS_TEST 0x0440 49684059Swpaul#define BGE_TX_TBI_AUTONEG 0x0444 49784059Swpaul#define BGE_RX_TBI_AUTONEG 0x0448 49884059Swpaul#define BGE_MI_COMM 0x044C 49984059Swpaul#define BGE_MI_STS 0x0450 50084059Swpaul#define BGE_MI_MODE 0x0454 50184059Swpaul#define BGE_AUTOPOLL_STS 0x0458 50284059Swpaul#define BGE_TX_MODE 0x045C 50384059Swpaul#define BGE_TX_STS 0x0460 50484059Swpaul#define BGE_TX_LENGTHS 0x0464 50584059Swpaul#define BGE_RX_MODE 0x0468 50684059Swpaul#define BGE_RX_STS 0x046C 50784059Swpaul#define BGE_MAR0 0x0470 50884059Swpaul#define BGE_MAR1 0x0474 50984059Swpaul#define BGE_MAR2 0x0478 51084059Swpaul#define BGE_MAR3 0x047C 51184059Swpaul#define BGE_RX_BD_RULES_CTL0 0x0480 51284059Swpaul#define BGE_RX_BD_RULES_MASKVAL0 0x0484 51384059Swpaul#define BGE_RX_BD_RULES_CTL1 0x0488 51484059Swpaul#define BGE_RX_BD_RULES_MASKVAL1 0x048C 51584059Swpaul#define BGE_RX_BD_RULES_CTL2 0x0490 51684059Swpaul#define BGE_RX_BD_RULES_MASKVAL2 0x0494 51784059Swpaul#define BGE_RX_BD_RULES_CTL3 0x0498 51884059Swpaul#define BGE_RX_BD_RULES_MASKVAL3 0x049C 51984059Swpaul#define BGE_RX_BD_RULES_CTL4 0x04A0 52084059Swpaul#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 52184059Swpaul#define BGE_RX_BD_RULES_CTL5 0x04A8 52284059Swpaul#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 52384059Swpaul#define BGE_RX_BD_RULES_CTL6 0x04B0 52484059Swpaul#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 52584059Swpaul#define BGE_RX_BD_RULES_CTL7 0x04B8 52684059Swpaul#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 52784059Swpaul#define BGE_RX_BD_RULES_CTL8 0x04C0 52884059Swpaul#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 52984059Swpaul#define BGE_RX_BD_RULES_CTL9 0x04C8 53084059Swpaul#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 53184059Swpaul#define BGE_RX_BD_RULES_CTL10 0x04D0 53284059Swpaul#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 53384059Swpaul#define BGE_RX_BD_RULES_CTL11 0x04D8 53484059Swpaul#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 53584059Swpaul#define BGE_RX_BD_RULES_CTL12 0x04E0 53684059Swpaul#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 53784059Swpaul#define BGE_RX_BD_RULES_CTL13 0x04E8 53884059Swpaul#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 53984059Swpaul#define BGE_RX_BD_RULES_CTL14 0x04F0 54084059Swpaul#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 54184059Swpaul#define BGE_RX_BD_RULES_CTL15 0x04F8 54284059Swpaul#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 54384059Swpaul#define BGE_RX_RULES_CFG 0x0500 544130273Swpaul#define BGE_SERDES_CFG 0x0590 545130273Swpaul#define BGE_SERDES_STS 0x0594 546130273Swpaul#define BGE_SGDIG_CFG 0x05B0 547130273Swpaul#define BGE_SGDIG_STS 0x05B4 54884059Swpaul#define BGE_RX_STATS 0x0800 54984059Swpaul#define BGE_TX_STATS 0x0880 55084059Swpaul 55184059Swpaul/* Ethernet MAC Mode register */ 55284059Swpaul#define BGE_MACMODE_RESET 0x00000001 55384059Swpaul#define BGE_MACMODE_HALF_DUPLEX 0x00000002 55484059Swpaul#define BGE_MACMODE_PORTMODE 0x0000000C 55584059Swpaul#define BGE_MACMODE_LOOPBACK 0x00000010 55684059Swpaul#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 55784059Swpaul#define BGE_MACMODE_TX_BURST_ENB 0x00000100 55884059Swpaul#define BGE_MACMODE_MAX_DEFER 0x00000200 55984059Swpaul#define BGE_MACMODE_LINK_POLARITY 0x00000400 56084059Swpaul#define BGE_MACMODE_RX_STATS_ENB 0x00000800 56184059Swpaul#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 56284059Swpaul#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 56384059Swpaul#define BGE_MACMODE_TX_STATS_ENB 0x00004000 56484059Swpaul#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 56584059Swpaul#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 56684059Swpaul#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 56784059Swpaul#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 56884059Swpaul#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 56984059Swpaul#define BGE_MACMODE_MIP_ENB 0x00100000 57084059Swpaul#define BGE_MACMODE_TXDMA_ENB 0x00200000 57184059Swpaul#define BGE_MACMODE_RXDMA_ENB 0x00400000 57284059Swpaul#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 57384059Swpaul 57484059Swpaul#define BGE_PORTMODE_NONE 0x00000000 57584059Swpaul#define BGE_PORTMODE_MII 0x00000004 57684059Swpaul#define BGE_PORTMODE_GMII 0x00000008 57784059Swpaul#define BGE_PORTMODE_TBI 0x0000000C 57884059Swpaul 57984059Swpaul/* MAC Status register */ 58084059Swpaul#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 58184059Swpaul#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 58284059Swpaul#define BGE_MACSTAT_RX_CFG 0x00000004 58384059Swpaul#define BGE_MACSTAT_CFG_CHANGED 0x00000008 58484059Swpaul#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 58584059Swpaul#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 58684059Swpaul#define BGE_MACSTAT_LINK_CHANGED 0x00001000 58784059Swpaul#define BGE_MACSTAT_MI_COMPLETE 0x00400000 58884059Swpaul#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 58984059Swpaul#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 59084059Swpaul#define BGE_MACSTAT_ODI_ERROR 0x02000000 59184059Swpaul#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 59284059Swpaul#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 59384059Swpaul 59484059Swpaul/* MAC Event Enable Register */ 59584059Swpaul#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 59684059Swpaul#define BGE_EVTENB_LINK_CHANGED 0x00001000 59784059Swpaul#define BGE_EVTENB_MI_COMPLETE 0x00400000 59884059Swpaul#define BGE_EVTENB_MI_INTERRUPT 0x00800000 59984059Swpaul#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 60084059Swpaul#define BGE_EVTENB_ODI_ERROR 0x02000000 60184059Swpaul#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 60284059Swpaul#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 60384059Swpaul 60484059Swpaul/* LED Control Register */ 60584059Swpaul#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 60684059Swpaul#define BGE_LEDCTL_1000MBPS_LED 0x00000002 60784059Swpaul#define BGE_LEDCTL_100MBPS_LED 0x00000004 60884059Swpaul#define BGE_LEDCTL_10MBPS_LED 0x00000008 60984059Swpaul#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 61084059Swpaul#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 61184059Swpaul#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 61284059Swpaul#define BGE_LEDCTL_1000MBPS_STS 0x00000080 61384059Swpaul#define BGE_LEDCTL_100MBPS_STS 0x00000100 61484059Swpaul#define BGE_LEDCTL_10MBPS_STS 0x00000200 61584059Swpaul#define BGE_LEDCTL_TRADLED_STS 0x00000400 61684059Swpaul#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 61784059Swpaul#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 61884059Swpaul 61984059Swpaul/* TX backoff seed register */ 62084059Swpaul#define BGE_TX_BACKOFF_SEED_MASK 0x3F 62184059Swpaul 62284059Swpaul/* Autopoll status register */ 62384059Swpaul#define BGE_AUTOPOLLSTS_ERROR 0x00000001 62484059Swpaul 62584059Swpaul/* Transmit MAC mode register */ 62684059Swpaul#define BGE_TXMODE_RESET 0x00000001 62784059Swpaul#define BGE_TXMODE_ENABLE 0x00000002 62884059Swpaul#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 62984059Swpaul#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 63084059Swpaul#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 63184059Swpaul 63284059Swpaul/* Transmit MAC status register */ 63384059Swpaul#define BGE_TXSTAT_RX_XOFFED 0x00000001 63484059Swpaul#define BGE_TXSTAT_SENT_XOFF 0x00000002 63584059Swpaul#define BGE_TXSTAT_SENT_XON 0x00000004 63684059Swpaul#define BGE_TXSTAT_LINK_UP 0x00000008 63784059Swpaul#define BGE_TXSTAT_ODI_UFLOW 0x00000010 63884059Swpaul#define BGE_TXSTAT_ODI_OFLOW 0x00000020 63984059Swpaul 64084059Swpaul/* Transmit MAC lengths register */ 64184059Swpaul#define BGE_TXLEN_SLOTTIME 0x000000FF 64284059Swpaul#define BGE_TXLEN_IPG 0x00000F00 64384059Swpaul#define BGE_TXLEN_CRS 0x00003000 64484059Swpaul 64584059Swpaul/* Receive MAC mode register */ 64684059Swpaul#define BGE_RXMODE_RESET 0x00000001 64784059Swpaul#define BGE_RXMODE_ENABLE 0x00000002 64884059Swpaul#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 64984059Swpaul#define BGE_RXMODE_RX_GIANTS 0x00000020 65084059Swpaul#define BGE_RXMODE_RX_RUNTS 0x00000040 65184059Swpaul#define BGE_RXMODE_8022_LENCHECK 0x00000080 65284059Swpaul#define BGE_RXMODE_RX_PROMISC 0x00000100 65384059Swpaul#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 65484059Swpaul#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 65584059Swpaul 65684059Swpaul/* Receive MAC status register */ 65784059Swpaul#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 65884059Swpaul#define BGE_RXSTAT_RCVD_XOFF 0x00000002 65984059Swpaul#define BGE_RXSTAT_RCVD_XON 0x00000004 66084059Swpaul 66184059Swpaul/* Receive Rules Control register */ 66284059Swpaul#define BGE_RXRULECTL_OFFSET 0x000000FF 66384059Swpaul#define BGE_RXRULECTL_CLASS 0x00001F00 66484059Swpaul#define BGE_RXRULECTL_HDRTYPE 0x0000E000 66584059Swpaul#define BGE_RXRULECTL_COMPARE_OP 0x00030000 66684059Swpaul#define BGE_RXRULECTL_MAP 0x01000000 66784059Swpaul#define BGE_RXRULECTL_DISCARD 0x02000000 66884059Swpaul#define BGE_RXRULECTL_MASK 0x04000000 66984059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 67084059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 67184059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 67284059Swpaul#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 67384059Swpaul 67484059Swpaul/* Receive Rules Mask register */ 67584059Swpaul#define BGE_RXRULEMASK_VALUE 0x0000FFFF 67684059Swpaul#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 67784059Swpaul 678130273Swpaul/* SERDES configuration register */ 679130273Swpaul#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 680130273Swpaul#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 681130273Swpaul#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 682130273Swpaul#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 683130273Swpaul#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 684130273Swpaul#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 685130273Swpaul#define BGE_SERDESCFG_TXMODE 0x00001000 686130273Swpaul#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 687130273Swpaul#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 688130273Swpaul#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 689130273Swpaul#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 690130273Swpaul#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 691130273Swpaul#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 692130273Swpaul#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 693130273Swpaul#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 694130273Swpaul#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 695130273Swpaul 696130273Swpaul/* SERDES status register */ 697130273Swpaul#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 698130273Swpaul#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 699130273Swpaul 700130273Swpaul/* SGDIG config (not documented) */ 701130273Swpaul#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 702130273Swpaul#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 703130273Swpaul#define BGE_SGDIGCFG_SEND 0x40000000 704130273Swpaul#define BGE_SGDIGCFG_AUTO 0x80000000 705130273Swpaul 706130273Swpaul/* SGDIG status (not documented) */ 707130273Swpaul#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 708130273Swpaul#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 709130273Swpaul#define BGE_SGDIGSTS_DONE 0x00000002 710130273Swpaul 711130273Swpaul 71284059Swpaul/* MI communication register */ 71384059Swpaul#define BGE_MICOMM_DATA 0x0000FFFF 71484059Swpaul#define BGE_MICOMM_REG 0x001F0000 71584059Swpaul#define BGE_MICOMM_PHY 0x03E00000 71684059Swpaul#define BGE_MICOMM_CMD 0x0C000000 71784059Swpaul#define BGE_MICOMM_READFAIL 0x10000000 71884059Swpaul#define BGE_MICOMM_BUSY 0x20000000 71984059Swpaul 72084059Swpaul#define BGE_MIREG(x) ((x & 0x1F) << 16) 72184059Swpaul#define BGE_MIPHY(x) ((x & 0x1F) << 21) 72284059Swpaul#define BGE_MICMD_WRITE 0x04000000 72384059Swpaul#define BGE_MICMD_READ 0x08000000 72484059Swpaul 72584059Swpaul/* MI status register */ 72684059Swpaul#define BGE_MISTS_LINK 0x00000001 72784059Swpaul#define BGE_MISTS_10MBPS 0x00000002 72884059Swpaul 72984059Swpaul#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 73084059Swpaul#define BGE_MIMODE_AUTOPOLL 0x00000010 73184059Swpaul#define BGE_MIMODE_CLKCNT 0x001F0000 73284059Swpaul 73384059Swpaul 73484059Swpaul/* 73584059Swpaul * Send data initiator control registers. 73684059Swpaul */ 73784059Swpaul#define BGE_SDI_MODE 0x0C00 73884059Swpaul#define BGE_SDI_STATUS 0x0C04 73984059Swpaul#define BGE_SDI_STATS_CTL 0x0C08 74084059Swpaul#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 74184059Swpaul#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 74284059Swpaul#define BGE_LOCSTATS_COS0 0x0C80 74384059Swpaul#define BGE_LOCSTATS_COS1 0x0C84 74484059Swpaul#define BGE_LOCSTATS_COS2 0x0C88 74584059Swpaul#define BGE_LOCSTATS_COS3 0x0C8C 74684059Swpaul#define BGE_LOCSTATS_COS4 0x0C90 74784059Swpaul#define BGE_LOCSTATS_COS5 0x0C84 74884059Swpaul#define BGE_LOCSTATS_COS6 0x0C98 74984059Swpaul#define BGE_LOCSTATS_COS7 0x0C9C 75084059Swpaul#define BGE_LOCSTATS_COS8 0x0CA0 75184059Swpaul#define BGE_LOCSTATS_COS9 0x0CA4 75284059Swpaul#define BGE_LOCSTATS_COS10 0x0CA8 75384059Swpaul#define BGE_LOCSTATS_COS11 0x0CAC 75484059Swpaul#define BGE_LOCSTATS_COS12 0x0CB0 75584059Swpaul#define BGE_LOCSTATS_COS13 0x0CB4 75684059Swpaul#define BGE_LOCSTATS_COS14 0x0CB8 75784059Swpaul#define BGE_LOCSTATS_COS15 0x0CBC 75884059Swpaul#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 75984059Swpaul#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 76084059Swpaul#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 76184059Swpaul#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 76284059Swpaul#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 76384059Swpaul#define BGE_LOCSTATS_IRQS 0x0CD4 76484059Swpaul#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 76584059Swpaul#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 76684059Swpaul 76784059Swpaul/* Send Data Initiator mode register */ 76884059Swpaul#define BGE_SDIMODE_RESET 0x00000001 76984059Swpaul#define BGE_SDIMODE_ENABLE 0x00000002 77084059Swpaul#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 77184059Swpaul 77284059Swpaul/* Send Data Initiator stats register */ 77384059Swpaul#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 77484059Swpaul 77584059Swpaul/* Send Data Initiator stats control register */ 77684059Swpaul#define BGE_SDISTATSCTL_ENABLE 0x00000001 77784059Swpaul#define BGE_SDISTATSCTL_FASTER 0x00000002 77884059Swpaul#define BGE_SDISTATSCTL_CLEAR 0x00000004 77984059Swpaul#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 78084059Swpaul#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 78184059Swpaul 78284059Swpaul/* 78384059Swpaul * Send Data Completion Control registers 78484059Swpaul */ 78584059Swpaul#define BGE_SDC_MODE 0x1000 78684059Swpaul#define BGE_SDC_STATUS 0x1004 78784059Swpaul 78884059Swpaul/* Send Data completion mode register */ 78984059Swpaul#define BGE_SDCMODE_RESET 0x00000001 79084059Swpaul#define BGE_SDCMODE_ENABLE 0x00000002 79184059Swpaul#define BGE_SDCMODE_ATTN 0x00000004 79284059Swpaul 79384059Swpaul/* Send Data completion status register */ 79484059Swpaul#define BGE_SDCSTAT_ATTN 0x00000004 79584059Swpaul 79684059Swpaul/* 79784059Swpaul * Send BD Ring Selector Control registers 79884059Swpaul */ 79984059Swpaul#define BGE_SRS_MODE 0x1400 80084059Swpaul#define BGE_SRS_STATUS 0x1404 80184059Swpaul#define BGE_SRS_HWDIAG 0x1408 80284059Swpaul#define BGE_SRS_LOC_NIC_CONS0 0x1440 80384059Swpaul#define BGE_SRS_LOC_NIC_CONS1 0x1444 80484059Swpaul#define BGE_SRS_LOC_NIC_CONS2 0x1448 80584059Swpaul#define BGE_SRS_LOC_NIC_CONS3 0x144C 80684059Swpaul#define BGE_SRS_LOC_NIC_CONS4 0x1450 80784059Swpaul#define BGE_SRS_LOC_NIC_CONS5 0x1454 80884059Swpaul#define BGE_SRS_LOC_NIC_CONS6 0x1458 80984059Swpaul#define BGE_SRS_LOC_NIC_CONS7 0x145C 81084059Swpaul#define BGE_SRS_LOC_NIC_CONS8 0x1460 81184059Swpaul#define BGE_SRS_LOC_NIC_CONS9 0x1464 81284059Swpaul#define BGE_SRS_LOC_NIC_CONS10 0x1468 81384059Swpaul#define BGE_SRS_LOC_NIC_CONS11 0x146C 81484059Swpaul#define BGE_SRS_LOC_NIC_CONS12 0x1470 81584059Swpaul#define BGE_SRS_LOC_NIC_CONS13 0x1474 81684059Swpaul#define BGE_SRS_LOC_NIC_CONS14 0x1478 81784059Swpaul#define BGE_SRS_LOC_NIC_CONS15 0x147C 81884059Swpaul 81984059Swpaul/* Send BD Ring Selector Mode register */ 82084059Swpaul#define BGE_SRSMODE_RESET 0x00000001 82184059Swpaul#define BGE_SRSMODE_ENABLE 0x00000002 82284059Swpaul#define BGE_SRSMODE_ATTN 0x00000004 82384059Swpaul 82484059Swpaul/* Send BD Ring Selector Status register */ 82584059Swpaul#define BGE_SRSSTAT_ERROR 0x00000004 82684059Swpaul 82784059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 82884059Swpaul#define BGE_SRSHWDIAG_STATE 0x0000000F 82984059Swpaul#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 83084059Swpaul#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 83184059Swpaul#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 83284059Swpaul 83384059Swpaul/* 83484059Swpaul * Send BD Initiator Selector Control registers 83584059Swpaul */ 83684059Swpaul#define BGE_SBDI_MODE 0x1800 83784059Swpaul#define BGE_SBDI_STATUS 0x1804 83884059Swpaul#define BGE_SBDI_LOC_NIC_PROD0 0x1808 83984059Swpaul#define BGE_SBDI_LOC_NIC_PROD1 0x180C 84084059Swpaul#define BGE_SBDI_LOC_NIC_PROD2 0x1810 84184059Swpaul#define BGE_SBDI_LOC_NIC_PROD3 0x1814 84284059Swpaul#define BGE_SBDI_LOC_NIC_PROD4 0x1818 84384059Swpaul#define BGE_SBDI_LOC_NIC_PROD5 0x181C 84484059Swpaul#define BGE_SBDI_LOC_NIC_PROD6 0x1820 84584059Swpaul#define BGE_SBDI_LOC_NIC_PROD7 0x1824 84684059Swpaul#define BGE_SBDI_LOC_NIC_PROD8 0x1828 84784059Swpaul#define BGE_SBDI_LOC_NIC_PROD9 0x182C 84884059Swpaul#define BGE_SBDI_LOC_NIC_PROD10 0x1830 84984059Swpaul#define BGE_SBDI_LOC_NIC_PROD11 0x1834 85084059Swpaul#define BGE_SBDI_LOC_NIC_PROD12 0x1838 85184059Swpaul#define BGE_SBDI_LOC_NIC_PROD13 0x183C 85284059Swpaul#define BGE_SBDI_LOC_NIC_PROD14 0x1840 85384059Swpaul#define BGE_SBDI_LOC_NIC_PROD15 0x1844 85484059Swpaul 85584059Swpaul/* Send BD Initiator Mode register */ 85684059Swpaul#define BGE_SBDIMODE_RESET 0x00000001 85784059Swpaul#define BGE_SBDIMODE_ENABLE 0x00000002 85884059Swpaul#define BGE_SBDIMODE_ATTN 0x00000004 85984059Swpaul 86084059Swpaul/* Send BD Initiator Status register */ 86184059Swpaul#define BGE_SBDISTAT_ERROR 0x00000004 86284059Swpaul 86384059Swpaul/* 86484059Swpaul * Send BD Completion Control registers 86584059Swpaul */ 86684059Swpaul#define BGE_SBDC_MODE 0x1C00 86784059Swpaul#define BGE_SBDC_STATUS 0x1C04 86884059Swpaul 86984059Swpaul/* Send BD Completion Control Mode register */ 87084059Swpaul#define BGE_SBDCMODE_RESET 0x00000001 87184059Swpaul#define BGE_SBDCMODE_ENABLE 0x00000002 87284059Swpaul#define BGE_SBDCMODE_ATTN 0x00000004 87384059Swpaul 87484059Swpaul/* Send BD Completion Control Status register */ 87584059Swpaul#define BGE_SBDCSTAT_ATTN 0x00000004 87684059Swpaul 87784059Swpaul/* 87884059Swpaul * Receive List Placement Control registers 87984059Swpaul */ 88084059Swpaul#define BGE_RXLP_MODE 0x2000 88184059Swpaul#define BGE_RXLP_STATUS 0x2004 88284059Swpaul#define BGE_RXLP_SEL_LIST_LOCK 0x2008 88384059Swpaul#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 88484059Swpaul#define BGE_RXLP_CFG 0x2010 88584059Swpaul#define BGE_RXLP_STATS_CTL 0x2014 88684059Swpaul#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 88784059Swpaul#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 88884059Swpaul#define BGE_RXLP_HEAD0 0x2100 88984059Swpaul#define BGE_RXLP_TAIL0 0x2104 89084059Swpaul#define BGE_RXLP_COUNT0 0x2108 89184059Swpaul#define BGE_RXLP_HEAD1 0x2110 89284059Swpaul#define BGE_RXLP_TAIL1 0x2114 89384059Swpaul#define BGE_RXLP_COUNT1 0x2118 89484059Swpaul#define BGE_RXLP_HEAD2 0x2120 89584059Swpaul#define BGE_RXLP_TAIL2 0x2124 89684059Swpaul#define BGE_RXLP_COUNT2 0x2128 89784059Swpaul#define BGE_RXLP_HEAD3 0x2130 89884059Swpaul#define BGE_RXLP_TAIL3 0x2134 89984059Swpaul#define BGE_RXLP_COUNT3 0x2138 90084059Swpaul#define BGE_RXLP_HEAD4 0x2140 90184059Swpaul#define BGE_RXLP_TAIL4 0x2144 90284059Swpaul#define BGE_RXLP_COUNT4 0x2148 90384059Swpaul#define BGE_RXLP_HEAD5 0x2150 90484059Swpaul#define BGE_RXLP_TAIL5 0x2154 90584059Swpaul#define BGE_RXLP_COUNT5 0x2158 90684059Swpaul#define BGE_RXLP_HEAD6 0x2160 90784059Swpaul#define BGE_RXLP_TAIL6 0x2164 90884059Swpaul#define BGE_RXLP_COUNT6 0x2168 90984059Swpaul#define BGE_RXLP_HEAD7 0x2170 91084059Swpaul#define BGE_RXLP_TAIL7 0x2174 91184059Swpaul#define BGE_RXLP_COUNT7 0x2178 91284059Swpaul#define BGE_RXLP_HEAD8 0x2180 91384059Swpaul#define BGE_RXLP_TAIL8 0x2184 91484059Swpaul#define BGE_RXLP_COUNT8 0x2188 91584059Swpaul#define BGE_RXLP_HEAD9 0x2190 91684059Swpaul#define BGE_RXLP_TAIL9 0x2194 91784059Swpaul#define BGE_RXLP_COUNT9 0x2198 91884059Swpaul#define BGE_RXLP_HEAD10 0x21A0 91984059Swpaul#define BGE_RXLP_TAIL10 0x21A4 92084059Swpaul#define BGE_RXLP_COUNT10 0x21A8 92184059Swpaul#define BGE_RXLP_HEAD11 0x21B0 92284059Swpaul#define BGE_RXLP_TAIL11 0x21B4 92384059Swpaul#define BGE_RXLP_COUNT11 0x21B8 92484059Swpaul#define BGE_RXLP_HEAD12 0x21C0 92584059Swpaul#define BGE_RXLP_TAIL12 0x21C4 92684059Swpaul#define BGE_RXLP_COUNT12 0x21C8 92784059Swpaul#define BGE_RXLP_HEAD13 0x21D0 92884059Swpaul#define BGE_RXLP_TAIL13 0x21D4 92984059Swpaul#define BGE_RXLP_COUNT13 0x21D8 93084059Swpaul#define BGE_RXLP_HEAD14 0x21E0 93184059Swpaul#define BGE_RXLP_TAIL14 0x21E4 93284059Swpaul#define BGE_RXLP_COUNT14 0x21E8 93384059Swpaul#define BGE_RXLP_HEAD15 0x21F0 93484059Swpaul#define BGE_RXLP_TAIL15 0x21F4 93584059Swpaul#define BGE_RXLP_COUNT15 0x21F8 93684059Swpaul#define BGE_RXLP_LOCSTAT_COS0 0x2200 93784059Swpaul#define BGE_RXLP_LOCSTAT_COS1 0x2204 93884059Swpaul#define BGE_RXLP_LOCSTAT_COS2 0x2208 93984059Swpaul#define BGE_RXLP_LOCSTAT_COS3 0x220C 94084059Swpaul#define BGE_RXLP_LOCSTAT_COS4 0x2210 94184059Swpaul#define BGE_RXLP_LOCSTAT_COS5 0x2214 94284059Swpaul#define BGE_RXLP_LOCSTAT_COS6 0x2218 94384059Swpaul#define BGE_RXLP_LOCSTAT_COS7 0x221C 94484059Swpaul#define BGE_RXLP_LOCSTAT_COS8 0x2220 94584059Swpaul#define BGE_RXLP_LOCSTAT_COS9 0x2224 94684059Swpaul#define BGE_RXLP_LOCSTAT_COS10 0x2228 94784059Swpaul#define BGE_RXLP_LOCSTAT_COS11 0x222C 94884059Swpaul#define BGE_RXLP_LOCSTAT_COS12 0x2230 94984059Swpaul#define BGE_RXLP_LOCSTAT_COS13 0x2234 95084059Swpaul#define BGE_RXLP_LOCSTAT_COS14 0x2238 95184059Swpaul#define BGE_RXLP_LOCSTAT_COS15 0x223C 95284059Swpaul#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 95384059Swpaul#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 95484059Swpaul#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 95584059Swpaul#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 95684059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 95784059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 95884059Swpaul#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 95984059Swpaul 96084059Swpaul 96184059Swpaul/* Receive List Placement mode register */ 96284059Swpaul#define BGE_RXLPMODE_RESET 0x00000001 96384059Swpaul#define BGE_RXLPMODE_ENABLE 0x00000002 96484059Swpaul#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 96584059Swpaul#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 96684059Swpaul#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 96784059Swpaul 96884059Swpaul/* Receive List Placement Status register */ 96984059Swpaul#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 97084059Swpaul#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 97184059Swpaul#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 97284059Swpaul 97384059Swpaul/* 97484059Swpaul * Receive Data and Receive BD Initiator Control Registers 97584059Swpaul */ 97684059Swpaul#define BGE_RDBDI_MODE 0x2400 97784059Swpaul#define BGE_RDBDI_STATUS 0x2404 97884059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 97984059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 98084059Swpaul#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 98184059Swpaul#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 98284059Swpaul#define BGE_RX_STD_RCB_HADDR_HI 0x2450 98384059Swpaul#define BGE_RX_STD_RCB_HADDR_LO 0x2454 98484059Swpaul#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 98584059Swpaul#define BGE_RX_STD_RCB_NICADDR 0x245C 98684059Swpaul#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 98784059Swpaul#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 98884059Swpaul#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 98984059Swpaul#define BGE_RX_MINI_RCB_NICADDR 0x246C 99084059Swpaul#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 99184059Swpaul#define BGE_RDBDI_STD_RX_CONS 0x2474 99284059Swpaul#define BGE_RDBDI_MINI_RX_CONS 0x2478 99384059Swpaul#define BGE_RDBDI_RETURN_PROD0 0x2480 99484059Swpaul#define BGE_RDBDI_RETURN_PROD1 0x2484 99584059Swpaul#define BGE_RDBDI_RETURN_PROD2 0x2488 99684059Swpaul#define BGE_RDBDI_RETURN_PROD3 0x248C 99784059Swpaul#define BGE_RDBDI_RETURN_PROD4 0x2490 99884059Swpaul#define BGE_RDBDI_RETURN_PROD5 0x2494 99984059Swpaul#define BGE_RDBDI_RETURN_PROD6 0x2498 100084059Swpaul#define BGE_RDBDI_RETURN_PROD7 0x249C 100184059Swpaul#define BGE_RDBDI_RETURN_PROD8 0x24A0 100284059Swpaul#define BGE_RDBDI_RETURN_PROD9 0x24A4 100384059Swpaul#define BGE_RDBDI_RETURN_PROD10 0x24A8 100484059Swpaul#define BGE_RDBDI_RETURN_PROD11 0x24AC 100584059Swpaul#define BGE_RDBDI_RETURN_PROD12 0x24B0 100684059Swpaul#define BGE_RDBDI_RETURN_PROD13 0x24B4 100784059Swpaul#define BGE_RDBDI_RETURN_PROD14 0x24B8 100884059Swpaul#define BGE_RDBDI_RETURN_PROD15 0x24BC 100984059Swpaul#define BGE_RDBDI_HWDIAG 0x24C0 101084059Swpaul 101184059Swpaul 101284059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 101384059Swpaul#define BGE_RDBDIMODE_RESET 0x00000001 101484059Swpaul#define BGE_RDBDIMODE_ENABLE 0x00000002 101584059Swpaul#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 101684059Swpaul#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 101784059Swpaul#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 101884059Swpaul 101984059Swpaul/* Receive Data and Receive BD Initiator Status register */ 102084059Swpaul#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 102184059Swpaul#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 102284059Swpaul#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 102384059Swpaul 102484059Swpaul 102584059Swpaul/* 102684059Swpaul * Receive Data Completion Control registers 102784059Swpaul */ 102884059Swpaul#define BGE_RDC_MODE 0x2800 102984059Swpaul 103084059Swpaul/* Receive Data Completion Mode register */ 103184059Swpaul#define BGE_RDCMODE_RESET 0x00000001 103284059Swpaul#define BGE_RDCMODE_ENABLE 0x00000002 103384059Swpaul#define BGE_RDCMODE_ATTN 0x00000004 103484059Swpaul 103584059Swpaul/* 103684059Swpaul * Receive BD Initiator Control registers 103784059Swpaul */ 103884059Swpaul#define BGE_RBDI_MODE 0x2C00 103984059Swpaul#define BGE_RBDI_STATUS 0x2C04 104084059Swpaul#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 104184059Swpaul#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 104284059Swpaul#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 104384059Swpaul#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 104484059Swpaul#define BGE_RBDI_STD_REPL_THRESH 0x2C18 104584059Swpaul#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 104684059Swpaul 104784059Swpaul/* Receive BD Initiator Mode register */ 104884059Swpaul#define BGE_RBDIMODE_RESET 0x00000001 104984059Swpaul#define BGE_RBDIMODE_ENABLE 0x00000002 105084059Swpaul#define BGE_RBDIMODE_ATTN 0x00000004 105184059Swpaul 105284059Swpaul/* Receive BD Initiator Status register */ 105384059Swpaul#define BGE_RBDISTAT_ATTN 0x00000004 105484059Swpaul 105584059Swpaul/* 105684059Swpaul * Receive BD Completion Control registers 105784059Swpaul */ 105884059Swpaul#define BGE_RBDC_MODE 0x3000 105984059Swpaul#define BGE_RBDC_STATUS 0x3004 106084059Swpaul#define BGE_RBDC_JUMBO_BD_PROD 0x3008 106184059Swpaul#define BGE_RBDC_STD_BD_PROD 0x300C 106284059Swpaul#define BGE_RBDC_MINI_BD_PROD 0x3010 106384059Swpaul 106484059Swpaul/* Receive BD completion mode register */ 106584059Swpaul#define BGE_RBDCMODE_RESET 0x00000001 106684059Swpaul#define BGE_RBDCMODE_ENABLE 0x00000002 106784059Swpaul#define BGE_RBDCMODE_ATTN 0x00000004 106884059Swpaul 106984059Swpaul/* Receive BD completion status register */ 107084059Swpaul#define BGE_RBDCSTAT_ERROR 0x00000004 107184059Swpaul 107284059Swpaul/* 107384059Swpaul * Receive List Selector Control registers 107484059Swpaul */ 107584059Swpaul#define BGE_RXLS_MODE 0x3400 107684059Swpaul#define BGE_RXLS_STATUS 0x3404 107784059Swpaul 107884059Swpaul/* Receive List Selector Mode register */ 107984059Swpaul#define BGE_RXLSMODE_RESET 0x00000001 108084059Swpaul#define BGE_RXLSMODE_ENABLE 0x00000002 108184059Swpaul#define BGE_RXLSMODE_ATTN 0x00000004 108284059Swpaul 108384059Swpaul/* Receive List Selector Status register */ 108484059Swpaul#define BGE_RXLSSTAT_ERROR 0x00000004 108584059Swpaul 108684059Swpaul/* 108784059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 108884059Swpaul */ 108984059Swpaul#define BGE_MBCF_MODE 0x3800 109084059Swpaul#define BGE_MBCF_STATUS 0x3804 109184059Swpaul 109284059Swpaul/* Mbuf Cluster Free mode register */ 109384059Swpaul#define BGE_MBCFMODE_RESET 0x00000001 109484059Swpaul#define BGE_MBCFMODE_ENABLE 0x00000002 109584059Swpaul#define BGE_MBCFMODE_ATTN 0x00000004 109684059Swpaul 109784059Swpaul/* Mbuf Cluster Free status register */ 109884059Swpaul#define BGE_MBCFSTAT_ERROR 0x00000004 109984059Swpaul 110084059Swpaul/* 110184059Swpaul * Host Coalescing Control registers 110284059Swpaul */ 110384059Swpaul#define BGE_HCC_MODE 0x3C00 110484059Swpaul#define BGE_HCC_STATUS 0x3C04 110584059Swpaul#define BGE_HCC_RX_COAL_TICKS 0x3C08 110684059Swpaul#define BGE_HCC_TX_COAL_TICKS 0x3C0C 110784059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 110884059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 110984059Swpaul#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 111084059Swpaul#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 111184059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1112119047Sps#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 111384059Swpaul#define BGE_HCC_STATS_TICKS 0x3C28 111484059Swpaul#define BGE_HCC_STATS_ADDR_HI 0x3C30 111584059Swpaul#define BGE_HCC_STATS_ADDR_LO 0x3C34 111684059Swpaul#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 111784059Swpaul#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 111884059Swpaul#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 111984059Swpaul#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 112084059Swpaul#define BGE_FLOW_ATTN 0x3C48 112184059Swpaul#define BGE_HCC_JUMBO_BD_CONS 0x3C50 112284059Swpaul#define BGE_HCC_STD_BD_CONS 0x3C54 112384059Swpaul#define BGE_HCC_MINI_BD_CONS 0x3C58 112484059Swpaul#define BGE_HCC_RX_RETURN_PROD0 0x3C80 112584059Swpaul#define BGE_HCC_RX_RETURN_PROD1 0x3C84 112684059Swpaul#define BGE_HCC_RX_RETURN_PROD2 0x3C88 112784059Swpaul#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 112884059Swpaul#define BGE_HCC_RX_RETURN_PROD4 0x3C90 112984059Swpaul#define BGE_HCC_RX_RETURN_PROD5 0x3C94 113084059Swpaul#define BGE_HCC_RX_RETURN_PROD6 0x3C98 113184059Swpaul#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 113284059Swpaul#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 113384059Swpaul#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 113484059Swpaul#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 113584059Swpaul#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 113684059Swpaul#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 113784059Swpaul#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 113884059Swpaul#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 113984059Swpaul#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 114084059Swpaul#define BGE_HCC_TX_BD_CONS0 0x3CC0 114184059Swpaul#define BGE_HCC_TX_BD_CONS1 0x3CC4 114284059Swpaul#define BGE_HCC_TX_BD_CONS2 0x3CC8 114384059Swpaul#define BGE_HCC_TX_BD_CONS3 0x3CCC 114484059Swpaul#define BGE_HCC_TX_BD_CONS4 0x3CD0 114584059Swpaul#define BGE_HCC_TX_BD_CONS5 0x3CD4 114684059Swpaul#define BGE_HCC_TX_BD_CONS6 0x3CD8 114784059Swpaul#define BGE_HCC_TX_BD_CONS7 0x3CDC 114884059Swpaul#define BGE_HCC_TX_BD_CONS8 0x3CE0 114984059Swpaul#define BGE_HCC_TX_BD_CONS9 0x3CE4 115084059Swpaul#define BGE_HCC_TX_BD_CONS10 0x3CE8 115184059Swpaul#define BGE_HCC_TX_BD_CONS11 0x3CEC 115284059Swpaul#define BGE_HCC_TX_BD_CONS12 0x3CF0 115384059Swpaul#define BGE_HCC_TX_BD_CONS13 0x3CF4 115484059Swpaul#define BGE_HCC_TX_BD_CONS14 0x3CF8 115584059Swpaul#define BGE_HCC_TX_BD_CONS15 0x3CFC 115684059Swpaul 115784059Swpaul 115884059Swpaul/* Host coalescing mode register */ 115984059Swpaul#define BGE_HCCMODE_RESET 0x00000001 116084059Swpaul#define BGE_HCCMODE_ENABLE 0x00000002 116184059Swpaul#define BGE_HCCMODE_ATTN 0x00000004 116284059Swpaul#define BGE_HCCMODE_COAL_NOW 0x00000008 1163157683Spjd#define BGE_HCCMODE_MSI_BITS 0x00000070 116484059Swpaul#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 116584059Swpaul 116684059Swpaul#define BGE_STATBLKSZ_FULL 0x00000000 116784059Swpaul#define BGE_STATBLKSZ_64BYTE 0x00000080 116884059Swpaul#define BGE_STATBLKSZ_32BYTE 0x00000100 116984059Swpaul 117084059Swpaul/* Host coalescing status register */ 117184059Swpaul#define BGE_HCCSTAT_ERROR 0x00000004 117284059Swpaul 117384059Swpaul/* Flow attention register */ 117484059Swpaul#define BGE_FLOWATTN_MB_LOWAT 0x00000040 117584059Swpaul#define BGE_FLOWATTN_MEMARB 0x00000080 117684059Swpaul#define BGE_FLOWATTN_HOSTCOAL 0x00008000 117784059Swpaul#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 117884059Swpaul#define BGE_FLOWATTN_RCB_INVAL 0x00020000 117984059Swpaul#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 118084059Swpaul#define BGE_FLOWATTN_RDBDI 0x00080000 118184059Swpaul#define BGE_FLOWATTN_RXLS 0x00100000 118284059Swpaul#define BGE_FLOWATTN_RXLP 0x00200000 118384059Swpaul#define BGE_FLOWATTN_RBDC 0x00400000 118484059Swpaul#define BGE_FLOWATTN_RBDI 0x00800000 118584059Swpaul#define BGE_FLOWATTN_SDC 0x08000000 118684059Swpaul#define BGE_FLOWATTN_SDI 0x10000000 118784059Swpaul#define BGE_FLOWATTN_SRS 0x20000000 118884059Swpaul#define BGE_FLOWATTN_SBDC 0x40000000 118984059Swpaul#define BGE_FLOWATTN_SBDI 0x80000000 119084059Swpaul 119184059Swpaul/* 119284059Swpaul * Memory arbiter registers 119384059Swpaul */ 119484059Swpaul#define BGE_MARB_MODE 0x4000 119584059Swpaul#define BGE_MARB_STATUS 0x4004 119684059Swpaul#define BGE_MARB_TRAPADDR_HI 0x4008 119784059Swpaul#define BGE_MARB_TRAPADDR_LO 0x400C 119884059Swpaul 119984059Swpaul/* Memory arbiter mode register */ 120084059Swpaul#define BGE_MARBMODE_RESET 0x00000001 120184059Swpaul#define BGE_MARBMODE_ENABLE 0x00000002 120284059Swpaul#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 120384059Swpaul#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 120484059Swpaul#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 120584059Swpaul#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 120684059Swpaul#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 120784059Swpaul#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 120884059Swpaul#define BGE_MARBMODE_PCI_TRAP 0x00000100 120984059Swpaul#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 121084059Swpaul#define BGE_MARBMODE_RXQ_TRAP 0x00000400 121184059Swpaul#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 121284059Swpaul#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 121384059Swpaul#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 121484059Swpaul#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 121584059Swpaul#define BGE_MARBMODE_MBUF_TRAP 0x00008000 121684059Swpaul#define BGE_MARBMODE_TXDI_TRAP 0x00010000 121784059Swpaul#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 121884059Swpaul#define BGE_MARBMODE_TXBD_TRAP 0x00040000 121984059Swpaul#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 122084059Swpaul#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 122184059Swpaul#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 122284059Swpaul#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 122384059Swpaul#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 122484059Swpaul#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 122584059Swpaul#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 122684059Swpaul 122784059Swpaul/* Memory arbiter status register */ 122884059Swpaul#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 122984059Swpaul#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 123084059Swpaul#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 123184059Swpaul#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 123284059Swpaul#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 123384059Swpaul#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 123484059Swpaul#define BGE_MARBSTAT_PCI_TRAP 0x00000100 123584059Swpaul#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 123684059Swpaul#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 123784059Swpaul#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 123884059Swpaul#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 123984059Swpaul#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 124084059Swpaul#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 124184059Swpaul#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 124284059Swpaul#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 124384059Swpaul#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 124484059Swpaul#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 124584059Swpaul#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 124684059Swpaul#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 124784059Swpaul#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 124884059Swpaul#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 124984059Swpaul#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 125084059Swpaul#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 125184059Swpaul#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 125284059Swpaul 125384059Swpaul/* 125484059Swpaul * Buffer manager control registers 125584059Swpaul */ 125684059Swpaul#define BGE_BMAN_MODE 0x4400 125784059Swpaul#define BGE_BMAN_STATUS 0x4404 125884059Swpaul#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 125984059Swpaul#define BGE_BMAN_MBUFPOOL_LEN 0x440C 126084059Swpaul#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 126184059Swpaul#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 126284059Swpaul#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 126384059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 126484059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 126584059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 126684059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 126784059Swpaul#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 126884059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 126984059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 127084059Swpaul#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 127184059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 127284059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 127384059Swpaul#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 127484059Swpaul#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 127584059Swpaul#define BGE_BMAN_HWDIAG_1 0x444C 127684059Swpaul#define BGE_BMAN_HWDIAG_2 0x4450 127784059Swpaul#define BGE_BMAN_HWDIAG_3 0x4454 127884059Swpaul 127984059Swpaul/* Buffer manager mode register */ 128084059Swpaul#define BGE_BMANMODE_RESET 0x00000001 128184059Swpaul#define BGE_BMANMODE_ENABLE 0x00000002 128284059Swpaul#define BGE_BMANMODE_ATTN 0x00000004 128384059Swpaul#define BGE_BMANMODE_TESTMODE 0x00000008 128484059Swpaul#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 128584059Swpaul 128684059Swpaul/* Buffer manager status register */ 128784059Swpaul#define BGE_BMANSTAT_ERRO 0x00000004 128884059Swpaul#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 128984059Swpaul 129084059Swpaul 129184059Swpaul/* 129284059Swpaul * Read DMA Control registers 129384059Swpaul */ 129484059Swpaul#define BGE_RDMA_MODE 0x4800 129584059Swpaul#define BGE_RDMA_STATUS 0x4804 129684059Swpaul 129784059Swpaul/* Read DMA mode register */ 129884059Swpaul#define BGE_RDMAMODE_RESET 0x00000001 129984059Swpaul#define BGE_RDMAMODE_ENABLE 0x00000002 130084059Swpaul#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 130184059Swpaul#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 130284059Swpaul#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 130384059Swpaul#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 130484059Swpaul#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 130584059Swpaul#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 130684059Swpaul#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 130784059Swpaul#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 130884059Swpaul#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 130984059Swpaul 131084059Swpaul/* Read DMA status register */ 131184059Swpaul#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 131284059Swpaul#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 131384059Swpaul#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 131484059Swpaul#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 131584059Swpaul#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 131684059Swpaul#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 131784059Swpaul#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 131884059Swpaul#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 131984059Swpaul 132084059Swpaul/* 132184059Swpaul * Write DMA control registers 132284059Swpaul */ 132384059Swpaul#define BGE_WDMA_MODE 0x4C00 132484059Swpaul#define BGE_WDMA_STATUS 0x4C04 132584059Swpaul 132684059Swpaul/* Write DMA mode register */ 132784059Swpaul#define BGE_WDMAMODE_RESET 0x00000001 132884059Swpaul#define BGE_WDMAMODE_ENABLE 0x00000002 132984059Swpaul#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 133084059Swpaul#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 133184059Swpaul#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 133284059Swpaul#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 133384059Swpaul#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 133484059Swpaul#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 133584059Swpaul#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 133684059Swpaul#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 133784059Swpaul#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 133884059Swpaul 133984059Swpaul/* Write DMA status register */ 134084059Swpaul#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 134184059Swpaul#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 134284059Swpaul#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 134384059Swpaul#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 134484059Swpaul#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 134584059Swpaul#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 134684059Swpaul#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 134784059Swpaul#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 134884059Swpaul 134984059Swpaul 135084059Swpaul/* 135184059Swpaul * RX CPU registers 135284059Swpaul */ 135384059Swpaul#define BGE_RXCPU_MODE 0x5000 135484059Swpaul#define BGE_RXCPU_STATUS 0x5004 135584059Swpaul#define BGE_RXCPU_PC 0x501C 135684059Swpaul 135784059Swpaul/* RX CPU mode register */ 135884059Swpaul#define BGE_RXCPUMODE_RESET 0x00000001 135984059Swpaul#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 136084059Swpaul#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 136184059Swpaul#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 136284059Swpaul#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 136384059Swpaul#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 136484059Swpaul#define BGE_RXCPUMODE_ROMFAIL 0x00000040 136584059Swpaul#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 136684059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 136784059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 136884059Swpaul#define BGE_RXCPUMODE_HALTCPU 0x00000400 136984059Swpaul#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 137084059Swpaul#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 137184059Swpaul#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 137284059Swpaul 137384059Swpaul/* RX CPU status register */ 137484059Swpaul#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 137584059Swpaul#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 137684059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 137784059Swpaul#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 137884059Swpaul#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 137984059Swpaul#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 138084059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 138184059Swpaul#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 138284059Swpaul#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 138384059Swpaul#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 138484059Swpaul#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 138584059Swpaul#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 138684059Swpaul#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 138784059Swpaul#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 138884059Swpaul#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 138984059Swpaul#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 139084059Swpaul#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 139184059Swpaul 139284059Swpaul 139384059Swpaul/* 139484059Swpaul * TX CPU registers 139584059Swpaul */ 139684059Swpaul#define BGE_TXCPU_MODE 0x5400 139784059Swpaul#define BGE_TXCPU_STATUS 0x5404 139884059Swpaul#define BGE_TXCPU_PC 0x541C 139984059Swpaul 140084059Swpaul/* TX CPU mode register */ 140184059Swpaul#define BGE_TXCPUMODE_RESET 0x00000001 140284059Swpaul#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 140384059Swpaul#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 140484059Swpaul#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 140584059Swpaul#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 140684059Swpaul#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 140784059Swpaul#define BGE_TXCPUMODE_ROMFAIL 0x00000040 140884059Swpaul#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 140984059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 141084059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 141184059Swpaul#define BGE_TXCPUMODE_HALTCPU 0x00000400 141284059Swpaul#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 141384059Swpaul#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 141484059Swpaul 141584059Swpaul/* TX CPU status register */ 141684059Swpaul#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 141784059Swpaul#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 141884059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 141984059Swpaul#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 142084059Swpaul#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 142184059Swpaul#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 142284059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 142384059Swpaul#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 142484059Swpaul#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 142584059Swpaul#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 142684059Swpaul#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 142784059Swpaul#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 142884059Swpaul#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 142984059Swpaul#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 143084059Swpaul#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 143184059Swpaul#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 143284059Swpaul#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 143384059Swpaul 143484059Swpaul 143584059Swpaul/* 143684059Swpaul * Low priority mailbox registers 143784059Swpaul */ 143884059Swpaul#define BGE_LPMBX_IRQ0_HI 0x5800 143984059Swpaul#define BGE_LPMBX_IRQ0_LO 0x5804 144084059Swpaul#define BGE_LPMBX_IRQ1_HI 0x5808 144184059Swpaul#define BGE_LPMBX_IRQ1_LO 0x580C 144284059Swpaul#define BGE_LPMBX_IRQ2_HI 0x5810 144384059Swpaul#define BGE_LPMBX_IRQ2_LO 0x5814 144484059Swpaul#define BGE_LPMBX_IRQ3_HI 0x5818 144584059Swpaul#define BGE_LPMBX_IRQ3_LO 0x581C 144684059Swpaul#define BGE_LPMBX_GEN0_HI 0x5820 144784059Swpaul#define BGE_LPMBX_GEN0_LO 0x5824 144884059Swpaul#define BGE_LPMBX_GEN1_HI 0x5828 144984059Swpaul#define BGE_LPMBX_GEN1_LO 0x582C 145084059Swpaul#define BGE_LPMBX_GEN2_HI 0x5830 145184059Swpaul#define BGE_LPMBX_GEN2_LO 0x5834 145284059Swpaul#define BGE_LPMBX_GEN3_HI 0x5828 145384059Swpaul#define BGE_LPMBX_GEN3_LO 0x582C 145484059Swpaul#define BGE_LPMBX_GEN4_HI 0x5840 145584059Swpaul#define BGE_LPMBX_GEN4_LO 0x5844 145684059Swpaul#define BGE_LPMBX_GEN5_HI 0x5848 145784059Swpaul#define BGE_LPMBX_GEN5_LO 0x584C 145884059Swpaul#define BGE_LPMBX_GEN6_HI 0x5850 145984059Swpaul#define BGE_LPMBX_GEN6_LO 0x5854 146084059Swpaul#define BGE_LPMBX_GEN7_HI 0x5858 146184059Swpaul#define BGE_LPMBX_GEN7_LO 0x585C 146284059Swpaul#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 146384059Swpaul#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 146484059Swpaul#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 146584059Swpaul#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 146684059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 146784059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 146884059Swpaul#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 146984059Swpaul#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 147084059Swpaul#define BGE_LPMBX_RX_CONS0_HI 0x5880 147184059Swpaul#define BGE_LPMBX_RX_CONS0_LO 0x5884 147284059Swpaul#define BGE_LPMBX_RX_CONS1_HI 0x5888 147384059Swpaul#define BGE_LPMBX_RX_CONS1_LO 0x588C 147484059Swpaul#define BGE_LPMBX_RX_CONS2_HI 0x5890 147584059Swpaul#define BGE_LPMBX_RX_CONS2_LO 0x5894 147684059Swpaul#define BGE_LPMBX_RX_CONS3_HI 0x5898 147784059Swpaul#define BGE_LPMBX_RX_CONS3_LO 0x589C 147884059Swpaul#define BGE_LPMBX_RX_CONS4_HI 0x58A0 147984059Swpaul#define BGE_LPMBX_RX_CONS4_LO 0x58A4 148084059Swpaul#define BGE_LPMBX_RX_CONS5_HI 0x58A8 148184059Swpaul#define BGE_LPMBX_RX_CONS5_LO 0x58AC 148284059Swpaul#define BGE_LPMBX_RX_CONS6_HI 0x58B0 148384059Swpaul#define BGE_LPMBX_RX_CONS6_LO 0x58B4 148484059Swpaul#define BGE_LPMBX_RX_CONS7_HI 0x58B8 148584059Swpaul#define BGE_LPMBX_RX_CONS7_LO 0x58BC 148684059Swpaul#define BGE_LPMBX_RX_CONS8_HI 0x58C0 148784059Swpaul#define BGE_LPMBX_RX_CONS8_LO 0x58C4 148884059Swpaul#define BGE_LPMBX_RX_CONS9_HI 0x58C8 148984059Swpaul#define BGE_LPMBX_RX_CONS9_LO 0x58CC 149084059Swpaul#define BGE_LPMBX_RX_CONS10_HI 0x58D0 149184059Swpaul#define BGE_LPMBX_RX_CONS10_LO 0x58D4 149284059Swpaul#define BGE_LPMBX_RX_CONS11_HI 0x58D8 149384059Swpaul#define BGE_LPMBX_RX_CONS11_LO 0x58DC 149484059Swpaul#define BGE_LPMBX_RX_CONS12_HI 0x58E0 149584059Swpaul#define BGE_LPMBX_RX_CONS12_LO 0x58E4 149684059Swpaul#define BGE_LPMBX_RX_CONS13_HI 0x58E8 149784059Swpaul#define BGE_LPMBX_RX_CONS13_LO 0x58EC 149884059Swpaul#define BGE_LPMBX_RX_CONS14_HI 0x58F0 149984059Swpaul#define BGE_LPMBX_RX_CONS14_LO 0x58F4 150084059Swpaul#define BGE_LPMBX_RX_CONS15_HI 0x58F8 150184059Swpaul#define BGE_LPMBX_RX_CONS15_LO 0x58FC 150284059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 150384059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 150484059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 150584059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 150684059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 150784059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 150884059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 150984059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 151084059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 151184059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 151284059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 151384059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 151484059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 151584059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 151684059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 151784059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 151884059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 151984059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 152084059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 152184059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 152284059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 152384059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 152484059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 152584059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 152684059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 152784059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 152884059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 152984059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 153084059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 153184059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 153284059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 153384059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 153484059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 153584059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 153684059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 153784059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 153884059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 153984059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 154084059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 154184059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 154284059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 154384059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 154484059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 154584059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 154684059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 154784059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 154884059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 154984059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 155084059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 155184059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 155284059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 155384059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 155484059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 155584059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 155684059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 155784059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 155884059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 155984059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 156084059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 156184059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 156284059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 156384059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 156484059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 156584059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 156684059Swpaul 156784059Swpaul/* 156884059Swpaul * Flow throw Queue reset register 156984059Swpaul */ 157084059Swpaul#define BGE_FTQ_RESET 0x5C00 157184059Swpaul 157284059Swpaul#define BGE_FTQRESET_DMAREAD 0x00000002 157384059Swpaul#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 157484059Swpaul#define BGE_FTQRESET_DMADONE 0x00000010 157584059Swpaul#define BGE_FTQRESET_SBDC 0x00000020 157684059Swpaul#define BGE_FTQRESET_SDI 0x00000040 157784059Swpaul#define BGE_FTQRESET_WDMA 0x00000080 157884059Swpaul#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 157984059Swpaul#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 158084059Swpaul#define BGE_FTQRESET_SDC 0x00000400 158184059Swpaul#define BGE_FTQRESET_HCC 0x00000800 158284059Swpaul#define BGE_FTQRESET_TXFIFO 0x00001000 158384059Swpaul#define BGE_FTQRESET_MBC 0x00002000 158484059Swpaul#define BGE_FTQRESET_RBDC 0x00004000 158584059Swpaul#define BGE_FTQRESET_RXLP 0x00008000 158684059Swpaul#define BGE_FTQRESET_RDBDI 0x00010000 158784059Swpaul#define BGE_FTQRESET_RDC 0x00020000 158884059Swpaul#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 158984059Swpaul 159084059Swpaul/* 159184059Swpaul * Message Signaled Interrupt registers 159284059Swpaul */ 159384059Swpaul#define BGE_MSI_MODE 0x6000 159484059Swpaul#define BGE_MSI_STATUS 0x6004 159584059Swpaul#define BGE_MSI_FIFOACCESS 0x6008 159684059Swpaul 159784059Swpaul/* MSI mode register */ 159884059Swpaul#define BGE_MSIMODE_RESET 0x00000001 159984059Swpaul#define BGE_MSIMODE_ENABLE 0x00000002 160084059Swpaul#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 160184059Swpaul#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 160284059Swpaul#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 160384059Swpaul#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 160484059Swpaul#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 160584059Swpaul 160684059Swpaul/* MSI status register */ 160784059Swpaul#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 160884059Swpaul#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 160984059Swpaul#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 161084059Swpaul#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 161184059Swpaul#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 161284059Swpaul 161384059Swpaul 161484059Swpaul/* 161584059Swpaul * DMA Completion registers 161684059Swpaul */ 161784059Swpaul#define BGE_DMAC_MODE 0x6400 161884059Swpaul 161984059Swpaul/* DMA Completion mode register */ 162084059Swpaul#define BGE_DMACMODE_RESET 0x00000001 162184059Swpaul#define BGE_DMACMODE_ENABLE 0x00000002 162284059Swpaul 162384059Swpaul 162484059Swpaul/* 162584059Swpaul * General control registers. 162684059Swpaul */ 162784059Swpaul#define BGE_MODE_CTL 0x6800 162884059Swpaul#define BGE_MISC_CFG 0x6804 162984059Swpaul#define BGE_MISC_LOCAL_CTL 0x6808 163084059Swpaul#define BGE_EE_ADDR 0x6838 163184059Swpaul#define BGE_EE_DATA 0x683C 163284059Swpaul#define BGE_EE_CTL 0x6840 163384059Swpaul#define BGE_MDI_CTL 0x6844 163484059Swpaul#define BGE_EE_DELAY 0x6848 163584059Swpaul 163684059Swpaul/* Mode control register */ 163784059Swpaul#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 163884059Swpaul#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 163984059Swpaul#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 164084059Swpaul#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 164184059Swpaul#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 164284059Swpaul#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 164384059Swpaul#define BGE_MODECTL_NO_RX_CRC 0x00000400 164484059Swpaul#define BGE_MODECTL_RX_BADFRAMES 0x00000800 164584059Swpaul#define BGE_MODECTL_NO_TX_INTR 0x00002000 164684059Swpaul#define BGE_MODECTL_NO_RX_INTR 0x00004000 164784059Swpaul#define BGE_MODECTL_FORCE_PCI32 0x00008000 164884059Swpaul#define BGE_MODECTL_STACKUP 0x00010000 164984059Swpaul#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 165084059Swpaul#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 165184059Swpaul#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 165284059Swpaul#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 165384059Swpaul#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 165484059Swpaul#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 165584059Swpaul#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 165684059Swpaul#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 165784059Swpaul#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 165884059Swpaul#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 165984059Swpaul 166084059Swpaul/* Misc. config register */ 166184059Swpaul#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 166284059Swpaul#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 166384059Swpaul 166484059Swpaul#define BGE_32BITTIME_66MHZ (0x41 << 1) 166584059Swpaul 166684059Swpaul/* Misc. Local Control */ 166784059Swpaul#define BGE_MLC_INTR_STATE 0x00000001 166884059Swpaul#define BGE_MLC_INTR_CLR 0x00000002 166984059Swpaul#define BGE_MLC_INTR_SET 0x00000004 167084059Swpaul#define BGE_MLC_INTR_ONATTN 0x00000008 167184059Swpaul#define BGE_MLC_MISCIO_IN0 0x00000100 167284059Swpaul#define BGE_MLC_MISCIO_IN1 0x00000200 167384059Swpaul#define BGE_MLC_MISCIO_IN2 0x00000400 167484059Swpaul#define BGE_MLC_MISCIO_OUTEN0 0x00000800 167584059Swpaul#define BGE_MLC_MISCIO_OUTEN1 0x00001000 167684059Swpaul#define BGE_MLC_MISCIO_OUTEN2 0x00002000 167784059Swpaul#define BGE_MLC_MISCIO_OUT0 0x00004000 167884059Swpaul#define BGE_MLC_MISCIO_OUT1 0x00008000 167984059Swpaul#define BGE_MLC_MISCIO_OUT2 0x00010000 168084059Swpaul#define BGE_MLC_EXTRAM_ENB 0x00020000 168184059Swpaul#define BGE_MLC_SRAM_SIZE 0x001C0000 168284059Swpaul#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 168384059Swpaul#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 168484059Swpaul#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 168584059Swpaul#define BGE_MLC_AUTO_EEPROM 0x01000000 168684059Swpaul 168784059Swpaul#define BGE_SSRAMSIZE_256KB 0x00000000 168884059Swpaul#define BGE_SSRAMSIZE_512KB 0x00040000 168984059Swpaul#define BGE_SSRAMSIZE_1MB 0x00080000 169084059Swpaul#define BGE_SSRAMSIZE_2MB 0x000C0000 169184059Swpaul#define BGE_SSRAMSIZE_4MB 0x00100000 169284059Swpaul#define BGE_SSRAMSIZE_8MB 0x00140000 169384059Swpaul#define BGE_SSRAMSIZE_16M 0x00180000 169484059Swpaul 169584059Swpaul/* EEPROM address register */ 169684059Swpaul#define BGE_EEADDR_ADDRESS 0x0000FFFC 169784059Swpaul#define BGE_EEADDR_HALFCLK 0x01FF0000 169884059Swpaul#define BGE_EEADDR_START 0x02000000 169984059Swpaul#define BGE_EEADDR_DEVID 0x1C000000 170084059Swpaul#define BGE_EEADDR_RESET 0x20000000 170184059Swpaul#define BGE_EEADDR_DONE 0x40000000 170284059Swpaul#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 170384059Swpaul 170484059Swpaul#define BGE_EEDEVID(x) ((x & 7) << 26) 170584059Swpaul#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 170684059Swpaul#define BGE_HALFCLK_384SCL 0x60 170784059Swpaul#define BGE_EE_READCMD \ 170884059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 170984059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 171084059Swpaul#define BGE_EE_WRCMD \ 171184059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 171284059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 171384059Swpaul 171484059Swpaul/* EEPROM Control register */ 171584059Swpaul#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 171684059Swpaul#define BGE_EECTL_CLKOUT 0x00000002 171784059Swpaul#define BGE_EECTL_CLKIN 0x00000004 171884059Swpaul#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 171984059Swpaul#define BGE_EECTL_DATAOUT 0x00000010 172084059Swpaul#define BGE_EECTL_DATAIN 0x00000020 172184059Swpaul 172284059Swpaul/* MDI (MII/GMII) access register */ 172384059Swpaul#define BGE_MDI_DATA 0x00000001 172484059Swpaul#define BGE_MDI_DIR 0x00000002 172584059Swpaul#define BGE_MDI_SEL 0x00000004 172684059Swpaul#define BGE_MDI_CLK 0x00000008 172784059Swpaul 172884059Swpaul#define BGE_MEMWIN_START 0x00008000 172984059Swpaul#define BGE_MEMWIN_END 0x0000FFFF 173084059Swpaul 173184059Swpaul 173284059Swpaul#define BGE_MEMWIN_READ(sc, x, val) \ 173384059Swpaul do { \ 173484059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 173584059Swpaul (0xFFFF0000 & x), 4); \ 173684059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 173784059Swpaul } while(0) 173884059Swpaul 173984059Swpaul#define BGE_MEMWIN_WRITE(sc, x, val) \ 174084059Swpaul do { \ 174184059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 174284059Swpaul (0xFFFF0000 & x), 4); \ 174384059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 174484059Swpaul } while(0) 174584059Swpaul 174684059Swpaul/* 174784059Swpaul * This magic number is used to prevent PXE restart when we 174884059Swpaul * issue a software reset. We write this magic number to the 174984059Swpaul * firmware mailbox at 0xB50 in order to prevent the PXE boot 175084059Swpaul * code from running. 175184059Swpaul */ 175284059Swpaul#define BGE_MAGIC_NUMBER 0x4B657654 175384059Swpaul 175484059Swpaultypedef struct { 1755159395Sglebius uint32_t bge_addr_hi; 1756159395Sglebius uint32_t bge_addr_lo; 175784059Swpaul} bge_hostaddr; 1758118026Swpaul 1759115200Sps#define BGE_HOSTADDR(x, y) \ 1760115200Sps do { \ 1761159395Sglebius (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1762159395Sglebius (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1763115200Sps } while(0) 176484059Swpaul 1765118026Swpaul#define BGE_ADDR_LO(y) \ 1766159395Sglebius ((uint64_t) (y) & 0xFFFFFFFF) 1767118026Swpaul#define BGE_ADDR_HI(y) \ 1768159395Sglebius ((uint64_t) (y) >> 32) 1769118026Swpaul 177084059Swpaul/* Ring control block structure */ 177184059Swpaulstruct bge_rcb { 177284059Swpaul bge_hostaddr bge_hostaddr; 1773159395Sglebius uint32_t bge_maxlen_flags; 1774159395Sglebius uint32_t bge_nicaddr; 177584059Swpaul}; 1776153437Syongari 1777153437Syongari#define RCB_WRITE_4(sc, rcb, offset, val) \ 1778153437Syongari bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1779153437Syongari rcb + offsetof(struct bge_rcb, offset), val) 1780108847Sjdp#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 178184059Swpaul 178284059Swpaul#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 178384059Swpaul#define BGE_RCB_FLAG_RING_DISABLED 0x0002 178484059Swpaul 178584059Swpaulstruct bge_tx_bd { 178684059Swpaul bge_hostaddr bge_addr; 1787153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1788159395Sglebius uint16_t bge_flags; 1789159395Sglebius uint16_t bge_len; 1790159395Sglebius uint16_t bge_vlan_tag; 1791159395Sglebius uint16_t bge_rsvd; 1792153437Syongari#else 1793159395Sglebius uint16_t bge_len; 1794159395Sglebius uint16_t bge_flags; 1795159395Sglebius uint16_t bge_rsvd; 1796159395Sglebius uint16_t bge_vlan_tag; 1797153437Syongari#endif 179884059Swpaul}; 179984059Swpaul 180084059Swpaul#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 180184059Swpaul#define BGE_TXBDFLAG_IP_CSUM 0x0002 180284059Swpaul#define BGE_TXBDFLAG_END 0x0004 180384059Swpaul#define BGE_TXBDFLAG_IP_FRAG 0x0008 180484059Swpaul#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 180584059Swpaul#define BGE_TXBDFLAG_VLAN_TAG 0x0040 180684059Swpaul#define BGE_TXBDFLAG_COAL_NOW 0x0080 180784059Swpaul#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 180884059Swpaul#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 180984059Swpaul#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 181084059Swpaul#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 181184059Swpaul#define BGE_TXBDFLAG_NO_CRC 0x8000 181284059Swpaul 181384059Swpaul#define BGE_NIC_TXRING_ADDR(ringno, size) \ 181484059Swpaul BGE_SEND_RING_1_TO_4 + \ 181584059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 181684059Swpaul 181784059Swpaulstruct bge_rx_bd { 181884059Swpaul bge_hostaddr bge_addr; 1819153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1820159395Sglebius uint16_t bge_len; 1821159395Sglebius uint16_t bge_idx; 1822159395Sglebius uint16_t bge_flags; 1823159395Sglebius uint16_t bge_type; 1824159395Sglebius uint16_t bge_tcp_udp_csum; 1825159395Sglebius uint16_t bge_ip_csum; 1826159395Sglebius uint16_t bge_vlan_tag; 1827159395Sglebius uint16_t bge_error_flag; 1828153437Syongari#else 1829159395Sglebius uint16_t bge_idx; 1830159395Sglebius uint16_t bge_len; 1831159395Sglebius uint16_t bge_type; 1832159395Sglebius uint16_t bge_flags; 1833159395Sglebius uint16_t bge_ip_csum; 1834159395Sglebius uint16_t bge_tcp_udp_csum; 1835159395Sglebius uint16_t bge_error_flag; 1836159395Sglebius uint16_t bge_vlan_tag; 1837153437Syongari#endif 1838159395Sglebius uint32_t bge_rsvd; 1839159395Sglebius uint32_t bge_opaque; 184084059Swpaul}; 184184059Swpaul 1842153239Sglebiusstruct bge_extrx_bd { 1843153239Sglebius bge_hostaddr bge_addr1; 1844153239Sglebius bge_hostaddr bge_addr2; 1845153239Sglebius bge_hostaddr bge_addr3; 1846153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1847159395Sglebius uint16_t bge_len2; 1848159395Sglebius uint16_t bge_len1; 1849159395Sglebius uint16_t bge_rsvd1; 1850159395Sglebius uint16_t bge_len3; 1851153437Syongari#else 1852159395Sglebius uint16_t bge_len1; 1853159395Sglebius uint16_t bge_len2; 1854159395Sglebius uint16_t bge_len3; 1855159395Sglebius uint16_t bge_rsvd1; 1856153437Syongari#endif 1857153239Sglebius bge_hostaddr bge_addr0; 1858153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1859159395Sglebius uint16_t bge_len0; 1860159395Sglebius uint16_t bge_idx; 1861159395Sglebius uint16_t bge_flags; 1862159395Sglebius uint16_t bge_type; 1863159395Sglebius uint16_t bge_tcp_udp_csum; 1864159395Sglebius uint16_t bge_ip_csum; 1865159395Sglebius uint16_t bge_vlan_tag; 1866159395Sglebius uint16_t bge_error_flag; 1867153437Syongari#else 1868159395Sglebius uint16_t bge_idx; 1869159395Sglebius uint16_t bge_len0; 1870159395Sglebius uint16_t bge_type; 1871159395Sglebius uint16_t bge_flags; 1872159395Sglebius uint16_t bge_ip_csum; 1873159395Sglebius uint16_t bge_tcp_udp_csum; 1874159395Sglebius uint16_t bge_error_flag; 1875159395Sglebius uint16_t bge_vlan_tag; 1876153437Syongari#endif 1877159395Sglebius uint32_t bge_rsvd0; 1878159395Sglebius uint32_t bge_opaque; 1879153239Sglebius}; 1880153239Sglebius 188184059Swpaul#define BGE_RXBDFLAG_END 0x0004 188284059Swpaul#define BGE_RXBDFLAG_JUMBO_RING 0x0020 188384059Swpaul#define BGE_RXBDFLAG_VLAN_TAG 0x0040 188484059Swpaul#define BGE_RXBDFLAG_ERROR 0x0400 188584059Swpaul#define BGE_RXBDFLAG_MINI_RING 0x0800 188684059Swpaul#define BGE_RXBDFLAG_IP_CSUM 0x1000 188784059Swpaul#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 188884059Swpaul#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 188984059Swpaul 189084059Swpaul#define BGE_RXERRFLAG_BAD_CRC 0x0001 189184059Swpaul#define BGE_RXERRFLAG_COLL_DETECT 0x0002 189284059Swpaul#define BGE_RXERRFLAG_LINK_LOST 0x0004 189384059Swpaul#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 189484059Swpaul#define BGE_RXERRFLAG_MAC_ABORT 0x0010 189584059Swpaul#define BGE_RXERRFLAG_RUNT 0x0020 189684059Swpaul#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 189784059Swpaul#define BGE_RXERRFLAG_GIANT 0x0080 189884059Swpaul 189984059Swpaulstruct bge_sts_idx { 1900153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1901159395Sglebius uint16_t bge_rx_prod_idx; 1902159395Sglebius uint16_t bge_tx_cons_idx; 1903153437Syongari#else 1904159395Sglebius uint16_t bge_tx_cons_idx; 1905159395Sglebius uint16_t bge_rx_prod_idx; 1906153437Syongari#endif 190784059Swpaul}; 190884059Swpaul 190984059Swpaulstruct bge_status_block { 1910159395Sglebius uint32_t bge_status; 1911159395Sglebius uint32_t bge_rsvd0; 1912153437Syongari#if BYTE_ORDER == LITTLE_ENDIAN 1913159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 1914159395Sglebius uint16_t bge_rx_std_cons_idx; 1915159395Sglebius uint16_t bge_rx_mini_cons_idx; 1916159395Sglebius uint16_t bge_rsvd1; 1917153437Syongari#else 1918159395Sglebius uint16_t bge_rx_std_cons_idx; 1919159395Sglebius uint16_t bge_rx_jumbo_cons_idx; 1920159395Sglebius uint16_t bge_rsvd1; 1921159395Sglebius uint16_t bge_rx_mini_cons_idx; 1922153437Syongari#endif 192384059Swpaul struct bge_sts_idx bge_idx[16]; 192484059Swpaul}; 192584059Swpaul 192684059Swpaul#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 192784059Swpaul#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 192884059Swpaul 192984059Swpaul#define BGE_STATFLAG_UPDATED 0x00000001 193084059Swpaul#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 193184059Swpaul#define BGE_STATFLAG_ERROR 0x00000004 193284059Swpaul 193384059Swpaul 193484059Swpaul/* 193584059Swpaul * Broadcom Vendor ID 193684059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 193784059Swpaul * even though they're now manufactured by Broadcom) 193884059Swpaul */ 193984059Swpaul#define BCOM_VENDORID 0x14E4 194084059Swpaul#define BCOM_DEVICEID_BCM5700 0x1644 194184059Swpaul#define BCOM_DEVICEID_BCM5701 0x1645 1942117659Swpaul#define BCOM_DEVICEID_BCM5702 0x16A6 1943117659Swpaul#define BCOM_DEVICEID_BCM5702X 0x16C6 1944117659Swpaul#define BCOM_DEVICEID_BCM5703 0x16A7 1945117659Swpaul#define BCOM_DEVICEID_BCM5703X 0x16C7 1946114547Sps#define BCOM_DEVICEID_BCM5704C 0x1648 1947114547Sps#define BCOM_DEVICEID_BCM5704S 0x16A8 1948117659Swpaul#define BCOM_DEVICEID_BCM5705 0x1653 1949129640Sps#define BCOM_DEVICEID_BCM5705K 0x1654 1950138990Sps#define BCOM_DEVICEID_BCM5721 0x1659 1951117659Swpaul#define BCOM_DEVICEID_BCM5705M 0x165D 1952117659Swpaul#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1953146413Sps#define BCOM_DEVICEID_BCM5714C 0x1668 1954135772Sps#define BCOM_DEVICEID_BCM5750 0x1676 1955135772Sps#define BCOM_DEVICEID_BCM5750M 0x167C 1956135772Sps#define BCOM_DEVICEID_BCM5751 0x1677 1957143448Savatar#define BCOM_DEVICEID_BCM5751M 0x167D 1958152452Sglebius#define BCOM_DEVICEID_BCM5752 0x1600 1959117659Swpaul#define BCOM_DEVICEID_BCM5782 0x1696 1960121810Swpaul#define BCOM_DEVICEID_BCM5788 0x169C 1961146485Ssilby#define BCOM_DEVICEID_BCM5789 0x169D 1962118814Swpaul#define BCOM_DEVICEID_BCM5901 0x170D 1963118814Swpaul#define BCOM_DEVICEID_BCM5901A2 0x170E 196484059Swpaul 196584059Swpaul/* 196684059Swpaul * Alteon AceNIC PCI vendor/device ID. 196784059Swpaul */ 196884059Swpaul#define ALT_VENDORID 0x12AE 196984059Swpaul#define ALT_DEVICEID_ACENIC 0x0001 197084059Swpaul#define ALT_DEVICEID_ACENIC_COPPER 0x0002 197184059Swpaul#define ALT_DEVICEID_BCM5700 0x0003 197284059Swpaul#define ALT_DEVICEID_BCM5701 0x0004 197384059Swpaul 197484059Swpaul/* 197584059Swpaul * 3Com 3c985 PCI vendor/device ID. 197684059Swpaul */ 197784059Swpaul#define TC_VENDORID 0x10B7 197884059Swpaul#define TC_DEVICEID_3C985 0x0001 197984059Swpaul#define TC_DEVICEID_3C996 0x0003 198084059Swpaul 198184059Swpaul/* 198284059Swpaul * SysKonnect PCI vendor ID 198384059Swpaul */ 198484059Swpaul#define SK_VENDORID 0x1148 198584059Swpaul#define SK_DEVICEID_ALTIMA 0x4400 198684059Swpaul#define SK_SUBSYSID_9D21 0x4421 198784059Swpaul#define SK_SUBSYSID_9D41 0x4441 198884059Swpaul 198984059Swpaul/* 199089835Sjdp * Altima PCI vendor/device ID. 199189835Sjdp */ 199289835Sjdp#define ALTIMA_VENDORID 0x173b 199389835Sjdp#define ALTIMA_DEVICE_AC1000 0x03e8 1994124257Swpaul#define ALTIMA_DEVICE_AC1002 0x03e9 1995137073Sdes#define ALTIMA_DEVICE_AC9100 0x03ea 199689835Sjdp 199789835Sjdp/* 1998119157Sambrisko * Dell PCI vendor ID 1999119157Sambrisko */ 2000119157Sambrisko 2001119157Sambrisko#define DELL_VENDORID 0x1028 2002119157Sambrisko 2003119157Sambrisko/* 200484059Swpaul * Offset of MAC address inside EEPROM. 200584059Swpaul */ 200684059Swpaul#define BGE_EE_MAC_OFFSET 0x7C 200784059Swpaul#define BGE_EE_HWCFG_OFFSET 0xC8 200884059Swpaul 200993751Swpaul#define BGE_HWCFG_VOLTAGE 0x00000003 201093751Swpaul#define BGE_HWCFG_PHYLED_MODE 0x0000000C 201193751Swpaul#define BGE_HWCFG_MEDIA 0x00000030 201293751Swpaul 201393751Swpaul#define BGE_VOLTAGE_1POINT3 0x00000000 201493751Swpaul#define BGE_VOLTAGE_1POINT8 0x00000001 201593751Swpaul 201693751Swpaul#define BGE_PHYLEDMODE_UNSPEC 0x00000000 201793751Swpaul#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 201893751Swpaul#define BGE_PHYLEDMODE_SINGLELED 0x00000008 201993751Swpaul 202093751Swpaul#define BGE_MEDIA_UNSPEC 0x00000000 202193751Swpaul#define BGE_MEDIA_COPPER 0x00000010 202293751Swpaul#define BGE_MEDIA_FIBER 0x00000020 202393751Swpaul 202484059Swpaul#define BGE_PCI_READ_CMD 0x06000000 202584059Swpaul#define BGE_PCI_WRITE_CMD 0x70000000 202684059Swpaul 202784059Swpaul#define BGE_TICKS_PER_SEC 1000000 202884059Swpaul 202984059Swpaul/* 203084059Swpaul * Ring size constants. 203184059Swpaul */ 203284059Swpaul#define BGE_EVENT_RING_CNT 256 203384059Swpaul#define BGE_CMD_RING_CNT 64 203484059Swpaul#define BGE_STD_RX_RING_CNT 512 203584059Swpaul#define BGE_JUMBO_RX_RING_CNT 256 203684059Swpaul#define BGE_MINI_RX_RING_CNT 1024 203784059Swpaul#define BGE_RETURN_RING_CNT 1024 203884059Swpaul 2039117659Swpaul/* 5705 has smaller return ring size */ 2040117659Swpaul 2041117659Swpaul#define BGE_RETURN_RING_CNT_5705 512 2042117659Swpaul 204384059Swpaul/* 204484059Swpaul * Possible TX ring sizes. 204584059Swpaul */ 204684059Swpaul#define BGE_TX_RING_CNT_128 128 204784059Swpaul#define BGE_TX_RING_BASE_128 0x3800 204884059Swpaul 204984059Swpaul#define BGE_TX_RING_CNT_256 256 205084059Swpaul#define BGE_TX_RING_BASE_256 0x3000 205184059Swpaul 205284059Swpaul#define BGE_TX_RING_CNT_512 512 205384059Swpaul#define BGE_TX_RING_BASE_512 0x2000 205484059Swpaul 205584059Swpaul#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 205684059Swpaul#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 205784059Swpaul 205884059Swpaul/* 205984059Swpaul * Tigon III statistics counters. 206084059Swpaul */ 2061117659Swpaul/* Statistics maintained MAC Receive block. */ 2062117659Swpaulstruct bge_rx_mac_stats { 206384059Swpaul bge_hostaddr ifHCInOctets; 206484059Swpaul bge_hostaddr Reserved1; 206584059Swpaul bge_hostaddr etherStatsFragments; 206684059Swpaul bge_hostaddr ifHCInUcastPkts; 206784059Swpaul bge_hostaddr ifHCInMulticastPkts; 206884059Swpaul bge_hostaddr ifHCInBroadcastPkts; 206984059Swpaul bge_hostaddr dot3StatsFCSErrors; 207084059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 207184059Swpaul bge_hostaddr xonPauseFramesReceived; 207284059Swpaul bge_hostaddr xoffPauseFramesReceived; 207384059Swpaul bge_hostaddr macControlFramesReceived; 207484059Swpaul bge_hostaddr xoffStateEntered; 207584059Swpaul bge_hostaddr dot3StatsFramesTooLong; 207684059Swpaul bge_hostaddr etherStatsJabbers; 207784059Swpaul bge_hostaddr etherStatsUndersizePkts; 207884059Swpaul bge_hostaddr inRangeLengthError; 207984059Swpaul bge_hostaddr outRangeLengthError; 208084059Swpaul bge_hostaddr etherStatsPkts64Octets; 208184059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 208284059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 208384059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 208484059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 208584059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 208684059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 208784059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 208884059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 208984059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2090117659Swpaul}; 209184059Swpaul 209284059Swpaul 2093117659Swpaul/* Statistics maintained MAC Transmit block. */ 2094117659Swpaulstruct bge_tx_mac_stats { 209584059Swpaul bge_hostaddr ifHCOutOctets; 209684059Swpaul bge_hostaddr Reserved2; 209784059Swpaul bge_hostaddr etherStatsCollisions; 209884059Swpaul bge_hostaddr outXonSent; 209984059Swpaul bge_hostaddr outXoffSent; 210084059Swpaul bge_hostaddr flowControlDone; 210184059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 210284059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 210384059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 210484059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 210584059Swpaul bge_hostaddr Reserved3; 210684059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 210784059Swpaul bge_hostaddr dot3StatsLateCollisions; 210884059Swpaul bge_hostaddr dot3Collided2Times; 210984059Swpaul bge_hostaddr dot3Collided3Times; 211084059Swpaul bge_hostaddr dot3Collided4Times; 211184059Swpaul bge_hostaddr dot3Collided5Times; 211284059Swpaul bge_hostaddr dot3Collided6Times; 211384059Swpaul bge_hostaddr dot3Collided7Times; 211484059Swpaul bge_hostaddr dot3Collided8Times; 211584059Swpaul bge_hostaddr dot3Collided9Times; 211684059Swpaul bge_hostaddr dot3Collided10Times; 211784059Swpaul bge_hostaddr dot3Collided11Times; 211884059Swpaul bge_hostaddr dot3Collided12Times; 211984059Swpaul bge_hostaddr dot3Collided13Times; 212084059Swpaul bge_hostaddr dot3Collided14Times; 212184059Swpaul bge_hostaddr dot3Collided15Times; 212284059Swpaul bge_hostaddr ifHCOutUcastPkts; 212384059Swpaul bge_hostaddr ifHCOutMulticastPkts; 212484059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 212584059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 212684059Swpaul bge_hostaddr ifOutDiscards; 212784059Swpaul bge_hostaddr ifOutErrors; 2128117659Swpaul}; 212984059Swpaul 2130117659Swpaul/* Stats counters access through registers */ 2131117659Swpaulstruct bge_mac_stats_regs { 2132159395Sglebius uint32_t ifHCOutOctets; 2133159395Sglebius uint32_t Reserved0; 2134159395Sglebius uint32_t etherStatsCollisions; 2135159395Sglebius uint32_t outXonSent; 2136159395Sglebius uint32_t outXoffSent; 2137159395Sglebius uint32_t Reserved1; 2138159395Sglebius uint32_t dot3StatsInternalMacTransmitErrors; 2139159395Sglebius uint32_t dot3StatsSingleCollisionFrames; 2140159395Sglebius uint32_t dot3StatsMultipleCollisionFrames; 2141159395Sglebius uint32_t dot3StatsDeferredTransmissions; 2142159395Sglebius uint32_t Reserved2; 2143159395Sglebius uint32_t dot3StatsExcessiveCollisions; 2144159395Sglebius uint32_t dot3StatsLateCollisions; 2145159395Sglebius uint32_t Reserved3[14]; 2146159395Sglebius uint32_t ifHCOutUcastPkts; 2147159395Sglebius uint32_t ifHCOutMulticastPkts; 2148159395Sglebius uint32_t ifHCOutBroadcastPkts; 2149159395Sglebius uint32_t Reserved4[2]; 2150159395Sglebius uint32_t ifHCInOctets; 2151159395Sglebius uint32_t Reserved5; 2152159395Sglebius uint32_t etherStatsFragments; 2153159395Sglebius uint32_t ifHCInUcastPkts; 2154159395Sglebius uint32_t ifHCInMulticastPkts; 2155159395Sglebius uint32_t ifHCInBroadcastPkts; 2156159395Sglebius uint32_t dot3StatsFCSErrors; 2157159395Sglebius uint32_t dot3StatsAlignmentErrors; 2158159395Sglebius uint32_t xonPauseFramesReceived; 2159159395Sglebius uint32_t xoffPauseFramesReceived; 2160159395Sglebius uint32_t macControlFramesReceived; 2161159395Sglebius uint32_t xoffStateEntered; 2162159395Sglebius uint32_t dot3StatsFramesTooLong; 2163159395Sglebius uint32_t etherStatsJabbers; 2164159395Sglebius uint32_t etherStatsUndersizePkts; 2165117659Swpaul}; 2166117659Swpaul 2167117659Swpaulstruct bge_stats { 2168159395Sglebius uint8_t Reserved0[256]; 2169117659Swpaul 2170117659Swpaul /* Statistics maintained by Receive MAC. */ 2171117659Swpaul struct bge_rx_mac_stats rxstats; 2172117659Swpaul 2173117659Swpaul bge_hostaddr Unused1[37]; 2174117659Swpaul 2175117659Swpaul /* Statistics maintained by Transmit MAC. */ 2176117659Swpaul struct bge_tx_mac_stats txstats; 2177117659Swpaul 217884059Swpaul bge_hostaddr Unused2[31]; 217984059Swpaul 218084059Swpaul /* Statistics maintained by Receive List Placement. */ 218184059Swpaul bge_hostaddr COSIfHCInPkts[16]; 218284059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 218384059Swpaul bge_hostaddr nicDmaWriteQueueFull; 218484059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 218584059Swpaul bge_hostaddr nicNoMoreRxBDs; 218684059Swpaul bge_hostaddr ifInDiscards; 218784059Swpaul bge_hostaddr ifInErrors; 218884059Swpaul bge_hostaddr nicRecvThresholdHit; 218984059Swpaul 219084059Swpaul bge_hostaddr Unused3[9]; 219184059Swpaul 219284059Swpaul /* Statistics maintained by Send Data Initiator. */ 219384059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 219484059Swpaul bge_hostaddr nicDmaReadQueueFull; 219584059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 219684059Swpaul bge_hostaddr nicSendDataCompQueueFull; 219784059Swpaul 219884059Swpaul /* Statistics maintained by Host Coalescing. */ 219984059Swpaul bge_hostaddr nicRingSetSendProdIndex; 220084059Swpaul bge_hostaddr nicRingStatusUpdate; 220184059Swpaul bge_hostaddr nicInterrupts; 220284059Swpaul bge_hostaddr nicAvoidedInterrupts; 220384059Swpaul bge_hostaddr nicSendThresholdHit; 220484059Swpaul 2205159395Sglebius uint8_t Reserved4[320]; 220684059Swpaul}; 220784059Swpaul 220884059Swpaul/* 220984059Swpaul * Tigon general information block. This resides in host memory 221084059Swpaul * and contains the status counters, ring control blocks and 221184059Swpaul * producer pointers. 221284059Swpaul */ 221384059Swpaul 221484059Swpaulstruct bge_gib { 221584059Swpaul struct bge_stats bge_stats; 221684059Swpaul struct bge_rcb bge_tx_rcb[16]; 221784059Swpaul struct bge_rcb bge_std_rx_rcb; 221884059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 221984059Swpaul struct bge_rcb bge_mini_rx_rcb; 222084059Swpaul struct bge_rcb bge_return_rcb; 222184059Swpaul}; 222284059Swpaul 222384059Swpaul#define BGE_FRAMELEN 1518 222484059Swpaul#define BGE_MAX_FRAMELEN 1536 222584059Swpaul#define BGE_JUMBO_FRAMELEN 9018 222684059Swpaul#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 222784059Swpaul#define BGE_MIN_FRAMELEN 60 222884059Swpaul 222984059Swpaul/* 223084059Swpaul * Other utility macros. 223184059Swpaul */ 223284059Swpaul#define BGE_INC(x, y) (x) = (x + 1) % y 223384059Swpaul 223484059Swpaul/* 223584059Swpaul * Vital product data and structures. 223684059Swpaul */ 223784059Swpaul#define BGE_VPD_FLAG 0x8000 2238137073Sdes 223984059Swpaul/* VPD structures */ 224084059Swpaulstruct vpd_res { 2241159395Sglebius uint8_t vr_id; 2242159395Sglebius uint8_t vr_len; 2243159395Sglebius uint8_t vr_pad; 224484059Swpaul}; 2245137073Sdes 224684059Swpaulstruct vpd_key { 224784059Swpaul char vk_key[2]; 2248159395Sglebius uint8_t vk_len; 224984059Swpaul}; 2250137073Sdes 225184059Swpaul#define VPD_RES_ID 0x82 /* ID string */ 225284059Swpaul#define VPD_RES_READ 0x90 /* start of read only area */ 225384059Swpaul#define VPD_RES_WRITE 0x81 /* start of read/write area */ 225484059Swpaul#define VPD_RES_END 0x78 /* end tag */ 225584059Swpaul 225684059Swpaul 225784059Swpaul/* 225884059Swpaul * Register access macros. The Tigon always uses memory mapped register 225984059Swpaul * accesses and all registers must be accessed with 32 bit operations. 226084059Swpaul */ 226184059Swpaul 226284059Swpaul#define CSR_WRITE_4(sc, reg, val) \ 226384059Swpaul bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 226484059Swpaul 226584059Swpaul#define CSR_READ_4(sc, reg) \ 226684059Swpaul bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 226784059Swpaul 226884059Swpaul#define BGE_SETBIT(sc, reg, x) \ 2269106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 227084059Swpaul#define BGE_CLRBIT(sc, reg, x) \ 2271106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 227284059Swpaul 227384059Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 2274106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 227584059Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 2276106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 227784059Swpaul 227884059Swpaul/* 227984059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 228084059Swpaul * values are tuneable. They control the actual amount of buffers 228184059Swpaul * allocated for the standard, mini and jumbo receive rings. 228284059Swpaul */ 228384059Swpaul 228484059Swpaul#define BGE_SSLOTS 256 228584059Swpaul#define BGE_MSLOTS 256 228684059Swpaul#define BGE_JSLOTS 384 228784059Swpaul 228884059Swpaul#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2289159395Sglebius#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2290159395Sglebius (BGE_JRAWLEN % sizeof(uint64_t)))) 229184059Swpaul#define BGE_JPAGESZ PAGE_SIZE 229284059Swpaul#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 229384059Swpaul#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 229484059Swpaul 2295154519Sglebius#define BGE_NSEG_JUMBO 4 2296153239Sglebius#define BGE_NSEG_NEW 32 2297153239Sglebius 229884059Swpaul/* 229984059Swpaul * Ring structures. Most of these reside in host memory and we tell 230084059Swpaul * the NIC where they are via the ring control blocks. The exceptions 230184059Swpaul * are the tx and command rings, which live in NIC memory and which 230284059Swpaul * we access via the shared memory window. 230384059Swpaul */ 2304118026Swpaul 230584059Swpaulstruct bge_ring_data { 2306118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2307118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2308153239Sglebius struct bge_extrx_bd *bge_rx_jumbo_ring; 2309118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2310118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2311118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2312118026Swpaul struct bge_tx_bd *bge_tx_ring; 2313118026Swpaul bus_addr_t bge_tx_ring_paddr; 2314118026Swpaul struct bge_status_block *bge_status_block; 2315118026Swpaul bus_addr_t bge_status_block_paddr; 2316118026Swpaul struct bge_stats *bge_stats; 2317118026Swpaul bus_addr_t bge_stats_paddr; 231884059Swpaul struct bge_gib bge_info; 231984059Swpaul}; 232084059Swpaul 2321118026Swpaul#define BGE_STD_RX_RING_SZ \ 2322118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2323118026Swpaul#define BGE_JUMBO_RX_RING_SZ \ 2324153239Sglebius (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2325118026Swpaul#define BGE_TX_RING_SZ \ 2326118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2327118026Swpaul#define BGE_RX_RTN_RING_SZ(x) \ 2328118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2329118026Swpaul 2330118026Swpaul#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2331118026Swpaul 2332118026Swpaul#define BGE_STATS_SZ sizeof (struct bge_stats) 2333118026Swpaul 233484059Swpaul/* 233584059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 233684059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 233784059Swpaul * not the other way around. 233884059Swpaul */ 233984059Swpaulstruct bge_chain_data { 2340118026Swpaul bus_dma_tag_t bge_parent_tag; 2341118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2342118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2343118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2344118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2345118026Swpaul bus_dma_tag_t bge_status_tag; 2346118026Swpaul bus_dma_tag_t bge_stats_tag; 2347118026Swpaul bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2348118026Swpaul bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2349118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2350118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2351118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2352118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2353118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2354118026Swpaul bus_dmamap_t bge_tx_ring_map; 2355118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2356118026Swpaul bus_dmamap_t bge_status_map; 2357118026Swpaul bus_dmamap_t bge_stats_map; 235884059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 235984059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 236084059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 236184059Swpaul}; 236284059Swpaul 2363118026Swpaulstruct bge_dmamap_arg { 2364118026Swpaul struct bge_softc *sc; 2365118026Swpaul bus_addr_t bge_busaddr; 2366159395Sglebius uint16_t bge_flags; 2367118026Swpaul int bge_idx; 2368118026Swpaul int bge_maxsegs; 2369118026Swpaul struct bge_tx_bd *bge_ring; 2370118026Swpaul}; 2371118026Swpaul 237284059Swpaulstruct bge_type { 2373159395Sglebius uint16_t bge_vid; 2374159395Sglebius uint16_t bge_did; 237584059Swpaul char *bge_name; 237684059Swpaul}; 237784059Swpaul 237884059Swpaul#define BGE_HWREV_TIGON 0x01 237984059Swpaul#define BGE_HWREV_TIGON_II 0x02 2380117659Swpaul#define BGE_TIMEOUT 100000 238184059Swpaul#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 238284059Swpaul 238384059Swpaulstruct bge_bcom_hack { 238484059Swpaul int reg; 238584059Swpaul int val; 238684059Swpaul}; 238784059Swpaul 238884059Swpaulstruct bge_softc { 2389147256Sbrooks struct ifnet *bge_ifp; /* interface info */ 239084059Swpaul device_t bge_dev; 2391122497Ssam struct mtx bge_mtx; 239284059Swpaul device_t bge_miibus; 239384059Swpaul bus_space_handle_t bge_bhandle; 239484059Swpaul bus_space_tag_t bge_btag; 239584059Swpaul void *bge_intrhand; 239684059Swpaul struct resource *bge_irq; 239784059Swpaul struct resource *bge_res; 239884059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 2399159395Sglebius uint8_t bge_extram; /* has external SSRAM */ 2400159395Sglebius uint8_t bge_tbi; 2401159395Sglebius uint8_t bge_rx_alignment_bug; 2402159395Sglebius uint32_t bge_chipid; 2403159395Sglebius uint8_t bge_asicrev; 2404159395Sglebius uint8_t bge_chiprev; 2405159395Sglebius uint8_t bge_no_3_led; 2406159395Sglebius uint8_t bge_pcie; 2407118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 240884059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 2409159395Sglebius uint16_t bge_tx_saved_considx; 2410159395Sglebius uint16_t bge_rx_saved_considx; 2411159395Sglebius uint16_t bge_ev_saved_considx; 2412159395Sglebius uint16_t bge_return_ring_cnt; 2413159395Sglebius uint16_t bge_std; /* current std ring head */ 2414159395Sglebius uint16_t bge_jumbo; /* current jumo ring head */ 2415159395Sglebius uint32_t bge_stat_ticks; 2416159395Sglebius uint32_t bge_rx_coal_ticks; 2417159395Sglebius uint32_t bge_tx_coal_ticks; 2418159395Sglebius uint32_t bge_tx_prodidx; 2419159395Sglebius uint32_t bge_rx_max_coal_bds; 2420159395Sglebius uint32_t bge_tx_max_coal_bds; 2421159395Sglebius uint32_t bge_tx_buf_ratio; 242284059Swpaul int bge_if_flags; 242384059Swpaul int bge_txcnt; 2424155180Soleg int bge_link; /* link state */ 2425155180Soleg int bge_link_evt; /* pending link event */ 2426122497Ssam struct callout bge_stat_ch; 242784059Swpaul char *bge_vpd_prodname; 242884059Swpaul char *bge_vpd_readonly; 2429154492Soleg u_long bge_rx_discards; 2430154492Soleg u_long bge_tx_discards; 2431154492Soleg u_long bge_tx_collisions; 2432151553Sglebius#ifdef DEVICE_POLLING 2433151553Sglebius int rxcycles; 2434151553Sglebius#endif /* DEVICE_POLLING */ 243584059Swpaul}; 2436122497Ssam 2437122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2438122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2439122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2440122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2441122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2442122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2443