if_bgereg.h revision 135772
184059Swpaul/* 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 135772 2004-09-24 22:24:33Z ps $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 6484059Swpaul#define BGE_PAGE_ZERO 0x00000000 6584059Swpaul#define BGE_PAGE_ZERO_END 0x000000FF 6684059Swpaul#define BGE_SEND_RING_RCB 0x00000100 6784059Swpaul#define BGE_SEND_RING_RCB_END 0x000001FF 6884059Swpaul#define BGE_RX_RETURN_RING_RCB 0x00000200 6984059Swpaul#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 7084059Swpaul#define BGE_STATS_BLOCK 0x00000300 7184059Swpaul#define BGE_STATS_BLOCK_END 0x00000AFF 7284059Swpaul#define BGE_STATUS_BLOCK 0x00000B00 7384059Swpaul#define BGE_STATUS_BLOCK_END 0x00000B4F 7484059Swpaul#define BGE_SOFTWARE_GENCOMM 0x00000B50 75110367Sps#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76110367Sps#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 7784059Swpaul#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 7884059Swpaul#define BGE_UNMAPPED 0x00001000 7984059Swpaul#define BGE_UNMAPPED_END 0x00001FFF 8084059Swpaul#define BGE_DMA_DESCRIPTORS 0x00002000 8184059Swpaul#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 8284059Swpaul#define BGE_SEND_RING_1_TO_4 0x00004000 8384059Swpaul#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8484059Swpaul 8584059Swpaul/* Mappings for internal memory configuration */ 8684059Swpaul#define BGE_STD_RX_RINGS 0x00006000 8784059Swpaul#define BGE_STD_RX_RINGS_END 0x00006FFF 8884059Swpaul#define BGE_JUMBO_RX_RINGS 0x00007000 8984059Swpaul#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 9084059Swpaul#define BGE_BUFFPOOL_1 0x00008000 9184059Swpaul#define BGE_BUFFPOOL_1_END 0x0000FFFF 9284059Swpaul#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 9384059Swpaul#define BGE_BUFFPOOL_2_END 0x00017FFF 9484059Swpaul#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 9584059Swpaul#define BGE_BUFFPOOL_3_END 0x0001FFFF 9684059Swpaul 9784059Swpaul/* Mappings for external SSRAM configurations */ 9884059Swpaul#define BGE_SEND_RING_5_TO_6 0x00006000 9984059Swpaul#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 10084059Swpaul#define BGE_SEND_RING_7_TO_8 0x00007000 10184059Swpaul#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 10284059Swpaul#define BGE_SEND_RING_9_TO_16 0x00008000 10384059Swpaul#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 10484059Swpaul#define BGE_EXT_STD_RX_RINGS 0x0000C000 10584059Swpaul#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 10684059Swpaul#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 10784059Swpaul#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 10884059Swpaul#define BGE_MINI_RX_RINGS 0x0000E000 10984059Swpaul#define BGE_MINI_RX_RINGS_END 0x0000FFFF 11084059Swpaul#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 11184059Swpaul#define BGE_AVAIL_REGION1_END 0x00017FFF 11284059Swpaul#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 11384059Swpaul#define BGE_AVAIL_REGION2_END 0x0001FFFF 11484059Swpaul#define BGE_EXT_SSRAM 0x00020000 11584059Swpaul#define BGE_EXT_SSRAM_END 0x000FFFFF 11684059Swpaul 11784059Swpaul 11884059Swpaul/* 11984059Swpaul * BCM570x register offsets. These are memory mapped registers 12084059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12184059Swpaul * Each register must be accessed using 32 bit operations. 12284059Swpaul * 12384059Swpaul * All registers are accessed through a 32K shared memory block. 12484059Swpaul * The first group of registers are actually copies of the PCI 12584059Swpaul * configuration space registers. 12684059Swpaul */ 12784059Swpaul 12884059Swpaul/* 12984059Swpaul * PCI registers defined in the PCI 2.2 spec. 13084059Swpaul */ 13184059Swpaul#define BGE_PCI_VID 0x00 13284059Swpaul#define BGE_PCI_DID 0x02 13384059Swpaul#define BGE_PCI_CMD 0x04 13484059Swpaul#define BGE_PCI_STS 0x06 13584059Swpaul#define BGE_PCI_REV 0x08 13684059Swpaul#define BGE_PCI_CLASS 0x09 13784059Swpaul#define BGE_PCI_CACHESZ 0x0C 13884059Swpaul#define BGE_PCI_LATTIMER 0x0D 13984059Swpaul#define BGE_PCI_HDRTYPE 0x0E 14084059Swpaul#define BGE_PCI_BIST 0x0F 14184059Swpaul#define BGE_PCI_BAR0 0x10 14284059Swpaul#define BGE_PCI_BAR1 0x14 14384059Swpaul#define BGE_PCI_SUBSYS 0x2C 14484059Swpaul#define BGE_PCI_SUBVID 0x2E 14584059Swpaul#define BGE_PCI_ROMBASE 0x30 14684059Swpaul#define BGE_PCI_CAPPTR 0x34 14784059Swpaul#define BGE_PCI_INTLINE 0x3C 14884059Swpaul#define BGE_PCI_INTPIN 0x3D 14984059Swpaul#define BGE_PCI_MINGNT 0x3E 15084059Swpaul#define BGE_PCI_MAXLAT 0x3F 15184059Swpaul#define BGE_PCI_PCIXCAP 0x40 15284059Swpaul#define BGE_PCI_NEXTPTR_PM 0x41 15384059Swpaul#define BGE_PCI_PCIX_CMD 0x42 15484059Swpaul#define BGE_PCI_PCIX_STS 0x44 15584059Swpaul#define BGE_PCI_PWRMGMT_CAPID 0x48 15684059Swpaul#define BGE_PCI_NEXTPTR_VPD 0x49 15784059Swpaul#define BGE_PCI_PWRMGMT_CAPS 0x4A 15884059Swpaul#define BGE_PCI_PWRMGMT_CMD 0x4C 15984059Swpaul#define BGE_PCI_PWRMGMT_STS 0x4D 16084059Swpaul#define BGE_PCI_PWRMGMT_DATA 0x4F 16184059Swpaul#define BGE_PCI_VPD_CAPID 0x50 16284059Swpaul#define BGE_PCI_NEXTPTR_MSI 0x51 16384059Swpaul#define BGE_PCI_VPD_ADDR 0x52 16484059Swpaul#define BGE_PCI_VPD_DATA 0x54 16584059Swpaul#define BGE_PCI_MSI_CAPID 0x58 16684059Swpaul#define BGE_PCI_NEXTPTR_NONE 0x59 16784059Swpaul#define BGE_PCI_MSI_CTL 0x5A 16884059Swpaul#define BGE_PCI_MSI_ADDR_HI 0x5C 16984059Swpaul#define BGE_PCI_MSI_ADDR_LO 0x60 17084059Swpaul#define BGE_PCI_MSI_DATA 0x64 17184059Swpaul 172135772Sps/* PCI MSI. ??? */ 173135772Sps#define BGE_PCIE_CAPID_REG 0xD0 174135772Sps#define BGE_PCIE_CAPID 0x10 175135772Sps 17684059Swpaul/* 17784059Swpaul * PCI registers specific to the BCM570x family. 17884059Swpaul */ 17984059Swpaul#define BGE_PCI_MISC_CTL 0x68 18084059Swpaul#define BGE_PCI_DMA_RW_CTL 0x6C 18184059Swpaul#define BGE_PCI_PCISTATE 0x70 18284059Swpaul#define BGE_PCI_CLKCTL 0x74 18384059Swpaul#define BGE_PCI_REG_BASEADDR 0x78 18484059Swpaul#define BGE_PCI_MEMWIN_BASEADDR 0x7C 18584059Swpaul#define BGE_PCI_REG_DATA 0x80 18684059Swpaul#define BGE_PCI_MEMWIN_DATA 0x84 18784059Swpaul#define BGE_PCI_MODECTL 0x88 18884059Swpaul#define BGE_PCI_MISC_CFG 0x8C 18984059Swpaul#define BGE_PCI_MISC_LOCALCTL 0x90 19084059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 19184059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 19284059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 19384059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 19484059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 19584059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 19684059Swpaul#define BGE_PCI_ISR_MBX_HI 0xB0 19784059Swpaul#define BGE_PCI_ISR_MBX_LO 0xB4 19884059Swpaul 19984059Swpaul/* PCI Misc. Host control register */ 20084059Swpaul#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 20184059Swpaul#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 20284059Swpaul#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 20384059Swpaul#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 20484059Swpaul#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 20584059Swpaul#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 20684059Swpaul#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 20784059Swpaul#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 20884059Swpaul#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 20984059Swpaul 21084059Swpaul#define BGE_BIGENDIAN_INIT \ 211104325Sjake (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 21284059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 213104325Sjake BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 21484059Swpaul 21584059Swpaul#define BGE_LITTLEENDIAN_INIT \ 21684059Swpaul (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 21784059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 21884059Swpaul 219114813Sps#define BGE_CHIPID_TIGON_I 0x40000000 220114813Sps#define BGE_CHIPID_TIGON_II 0x60000000 221114813Sps#define BGE_CHIPID_BCM5700_B0 0x71000000 222114813Sps#define BGE_CHIPID_BCM5700_B1 0x71020000 223114813Sps#define BGE_CHIPID_BCM5700_B2 0x71030000 224114813Sps#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 225114813Sps#define BGE_CHIPID_BCM5700_C0 0x72000000 226114813Sps#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 227114813Sps#define BGE_CHIPID_BCM5701_B0 0x01000000 228114813Sps#define BGE_CHIPID_BCM5701_B2 0x01020000 229114813Sps#define BGE_CHIPID_BCM5701_B5 0x01050000 230114813Sps#define BGE_CHIPID_BCM5703_A0 0x10000000 231114813Sps#define BGE_CHIPID_BCM5703_A1 0x10010000 232114813Sps#define BGE_CHIPID_BCM5703_A2 0x10020000 233114813Sps#define BGE_CHIPID_BCM5704_A0 0x20000000 234114813Sps#define BGE_CHIPID_BCM5704_A1 0x20010000 235114813Sps#define BGE_CHIPID_BCM5704_A2 0x20020000 236117659Swpaul#define BGE_CHIPID_BCM5705_A0 0x30000000 237117659Swpaul#define BGE_CHIPID_BCM5705_A1 0x30010000 238117659Swpaul#define BGE_CHIPID_BCM5705_A2 0x30020000 239117659Swpaul#define BGE_CHIPID_BCM5705_A3 0x30030000 240135772Sps#define BGE_CHIPID_BCM5750_A0 0x40000000 241135772Sps#define BGE_CHIPID_BCM5750_A1 0x40010000 24284059Swpaul 24393751Swpaul/* shorthand one */ 244114615Sps#define BGE_ASICREV(x) ((x) >> 28) 245114615Sps#define BGE_ASICREV_BCM5700 0x07 246114615Sps#define BGE_ASICREV_BCM5701 0x00 247114615Sps#define BGE_ASICREV_BCM5703 0x01 248114615Sps#define BGE_ASICREV_BCM5704 0x02 249117659Swpaul#define BGE_ASICREV_BCM5705 0x03 250135772Sps#define BGE_ASICREV_BCM5750 0x04 25193751Swpaul 252114813Sps/* chip revisions */ 253114813Sps#define BGE_CHIPREV(x) ((x) >> 24) 254114813Sps#define BGE_CHIPREV_5700_AX 0x70 255114813Sps#define BGE_CHIPREV_5700_BX 0x71 256114813Sps#define BGE_CHIPREV_5700_CX 0x72 257114813Sps#define BGE_CHIPREV_5701_AX 0x00 258114813Sps 25984059Swpaul/* PCI DMA Read/Write Control register */ 26084059Swpaul#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 26184059Swpaul#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 26284059Swpaul#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 26384059Swpaul#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 26484059Swpaul#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 265114615Sps# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 26684059Swpaul#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 267114615Sps# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 26884059Swpaul#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 26984059Swpaul#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 27084059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 271114615Sps# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 27284059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 273114615Sps# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 27484059Swpaul 27584059Swpaul#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 27684059Swpaul#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 27784059Swpaul#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 27884059Swpaul#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 27984059Swpaul#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 28084059Swpaul#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 28184059Swpaul#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 28284059Swpaul#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 28384059Swpaul 28484059Swpaul#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 28584059Swpaul#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 28684059Swpaul#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 28784059Swpaul#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 28884059Swpaul#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 28984059Swpaul#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 29084059Swpaul#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 29184059Swpaul#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 29284059Swpaul 29384059Swpaul/* 29484059Swpaul * PCI state register -- note, this register is read only 29584059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 29684059Swpaul * register is set. 29784059Swpaul */ 29884059Swpaul#define BGE_PCISTATE_FORCE_RESET 0x00000001 29984059Swpaul#define BGE_PCISTATE_INTR_STATE 0x00000002 30084059Swpaul#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 30184059Swpaul#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 30284059Swpaul#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 30384059Swpaul#define BGE_PCISTATE_WANT_EXPROM 0x00000020 30484059Swpaul#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 30584059Swpaul#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 30684059Swpaul#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 30784059Swpaul 30884059Swpaul/* 30984059Swpaul * PCI Clock Control register -- note, this register is read only 31084059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 31184059Swpaul * register is set. 31284059Swpaul */ 31384059Swpaul#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 31484059Swpaul#define BGE_PCICLOCKCTL_M66EN 0x00000080 31584059Swpaul#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 31684059Swpaul#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 31784059Swpaul#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 31884059Swpaul#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 31984059Swpaul#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 32084059Swpaul#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 32184059Swpaul#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 32284059Swpaul#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 32384059Swpaul 32484059Swpaul 32584059Swpaul#ifndef PCIM_CMD_MWIEN 32684059Swpaul#define PCIM_CMD_MWIEN 0x0010 32784059Swpaul#endif 32884059Swpaul 32984059Swpaul/* 33084059Swpaul * High priority mailbox registers 33184059Swpaul * Each mailbox is 64-bits wide, though we only use the 33284059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 33384059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 33484059Swpaul * has been updated. 33584059Swpaul */ 33684059Swpaul#define BGE_MBX_IRQ0_HI 0x0200 33784059Swpaul#define BGE_MBX_IRQ0_LO 0x0204 33884059Swpaul#define BGE_MBX_IRQ1_HI 0x0208 33984059Swpaul#define BGE_MBX_IRQ1_LO 0x020C 34084059Swpaul#define BGE_MBX_IRQ2_HI 0x0210 34184059Swpaul#define BGE_MBX_IRQ2_LO 0x0214 34284059Swpaul#define BGE_MBX_IRQ3_HI 0x0218 34384059Swpaul#define BGE_MBX_IRQ3_LO 0x021C 34484059Swpaul#define BGE_MBX_GEN0_HI 0x0220 34584059Swpaul#define BGE_MBX_GEN0_LO 0x0224 34684059Swpaul#define BGE_MBX_GEN1_HI 0x0228 34784059Swpaul#define BGE_MBX_GEN1_LO 0x022C 34884059Swpaul#define BGE_MBX_GEN2_HI 0x0230 34984059Swpaul#define BGE_MBX_GEN2_LO 0x0234 35084059Swpaul#define BGE_MBX_GEN3_HI 0x0228 35184059Swpaul#define BGE_MBX_GEN3_LO 0x022C 35284059Swpaul#define BGE_MBX_GEN4_HI 0x0240 35384059Swpaul#define BGE_MBX_GEN4_LO 0x0244 35484059Swpaul#define BGE_MBX_GEN5_HI 0x0248 35584059Swpaul#define BGE_MBX_GEN5_LO 0x024C 35684059Swpaul#define BGE_MBX_GEN6_HI 0x0250 35784059Swpaul#define BGE_MBX_GEN6_LO 0x0254 35884059Swpaul#define BGE_MBX_GEN7_HI 0x0258 35984059Swpaul#define BGE_MBX_GEN7_LO 0x025C 36084059Swpaul#define BGE_MBX_RELOAD_STATS_HI 0x0260 36184059Swpaul#define BGE_MBX_RELOAD_STATS_LO 0x0264 36284059Swpaul#define BGE_MBX_RX_STD_PROD_HI 0x0268 36384059Swpaul#define BGE_MBX_RX_STD_PROD_LO 0x026C 36484059Swpaul#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 36584059Swpaul#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 36684059Swpaul#define BGE_MBX_RX_MINI_PROD_HI 0x0278 36784059Swpaul#define BGE_MBX_RX_MINI_PROD_LO 0x027C 36884059Swpaul#define BGE_MBX_RX_CONS0_HI 0x0280 36984059Swpaul#define BGE_MBX_RX_CONS0_LO 0x0284 37084059Swpaul#define BGE_MBX_RX_CONS1_HI 0x0288 37184059Swpaul#define BGE_MBX_RX_CONS1_LO 0x028C 37284059Swpaul#define BGE_MBX_RX_CONS2_HI 0x0290 37384059Swpaul#define BGE_MBX_RX_CONS2_LO 0x0294 37484059Swpaul#define BGE_MBX_RX_CONS3_HI 0x0298 37584059Swpaul#define BGE_MBX_RX_CONS3_LO 0x029C 37684059Swpaul#define BGE_MBX_RX_CONS4_HI 0x02A0 37784059Swpaul#define BGE_MBX_RX_CONS4_LO 0x02A4 37884059Swpaul#define BGE_MBX_RX_CONS5_HI 0x02A8 37984059Swpaul#define BGE_MBX_RX_CONS5_LO 0x02AC 38084059Swpaul#define BGE_MBX_RX_CONS6_HI 0x02B0 38184059Swpaul#define BGE_MBX_RX_CONS6_LO 0x02B4 38284059Swpaul#define BGE_MBX_RX_CONS7_HI 0x02B8 38384059Swpaul#define BGE_MBX_RX_CONS7_LO 0x02BC 38484059Swpaul#define BGE_MBX_RX_CONS8_HI 0x02C0 38584059Swpaul#define BGE_MBX_RX_CONS8_LO 0x02C4 38684059Swpaul#define BGE_MBX_RX_CONS9_HI 0x02C8 38784059Swpaul#define BGE_MBX_RX_CONS9_LO 0x02CC 38884059Swpaul#define BGE_MBX_RX_CONS10_HI 0x02D0 38984059Swpaul#define BGE_MBX_RX_CONS10_LO 0x02D4 39084059Swpaul#define BGE_MBX_RX_CONS11_HI 0x02D8 39184059Swpaul#define BGE_MBX_RX_CONS11_LO 0x02DC 39284059Swpaul#define BGE_MBX_RX_CONS12_HI 0x02E0 39384059Swpaul#define BGE_MBX_RX_CONS12_LO 0x02E4 39484059Swpaul#define BGE_MBX_RX_CONS13_HI 0x02E8 39584059Swpaul#define BGE_MBX_RX_CONS13_LO 0x02EC 39684059Swpaul#define BGE_MBX_RX_CONS14_HI 0x02F0 39784059Swpaul#define BGE_MBX_RX_CONS14_LO 0x02F4 39884059Swpaul#define BGE_MBX_RX_CONS15_HI 0x02F8 39984059Swpaul#define BGE_MBX_RX_CONS15_LO 0x02FC 40084059Swpaul#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 40184059Swpaul#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 40284059Swpaul#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 40384059Swpaul#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 40484059Swpaul#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 40584059Swpaul#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 40684059Swpaul#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 40784059Swpaul#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 40884059Swpaul#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 40984059Swpaul#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 41084059Swpaul#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 41184059Swpaul#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 41284059Swpaul#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 41384059Swpaul#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 41484059Swpaul#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 41584059Swpaul#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 41684059Swpaul#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 41784059Swpaul#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 41884059Swpaul#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 41984059Swpaul#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 42084059Swpaul#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 42184059Swpaul#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 42284059Swpaul#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 42384059Swpaul#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 42484059Swpaul#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 42584059Swpaul#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 42684059Swpaul#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 42784059Swpaul#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 42884059Swpaul#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 42984059Swpaul#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 43084059Swpaul#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 43184059Swpaul#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 43284059Swpaul#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 43384059Swpaul#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 43484059Swpaul#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 43584059Swpaul#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 43684059Swpaul#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 43784059Swpaul#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 43884059Swpaul#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 43984059Swpaul#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 44084059Swpaul#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 44184059Swpaul#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 44284059Swpaul#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 44384059Swpaul#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 44484059Swpaul#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 44584059Swpaul#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 44684059Swpaul#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 44784059Swpaul#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 44884059Swpaul#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 44984059Swpaul#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 45084059Swpaul#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 45184059Swpaul#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 45284059Swpaul#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 45384059Swpaul#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 45484059Swpaul#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 45584059Swpaul#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 45684059Swpaul#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 45784059Swpaul#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 45884059Swpaul#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 45984059Swpaul#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 46084059Swpaul#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 46184059Swpaul#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 46284059Swpaul#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 46384059Swpaul#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 46484059Swpaul 46584059Swpaul#define BGE_TX_RINGS_MAX 4 46684059Swpaul#define BGE_TX_RINGS_EXTSSRAM_MAX 16 46784059Swpaul#define BGE_RX_RINGS_MAX 16 46884059Swpaul 46984059Swpaul/* Ethernet MAC control registers */ 47084059Swpaul#define BGE_MAC_MODE 0x0400 47184059Swpaul#define BGE_MAC_STS 0x0404 47284059Swpaul#define BGE_MAC_EVT_ENB 0x0408 47384059Swpaul#define BGE_MAC_LED_CTL 0x040C 47484059Swpaul#define BGE_MAC_ADDR1_LO 0x0410 47584059Swpaul#define BGE_MAC_ADDR1_HI 0x0414 47684059Swpaul#define BGE_MAC_ADDR2_LO 0x0418 47784059Swpaul#define BGE_MAC_ADDR2_HI 0x041C 47884059Swpaul#define BGE_MAC_ADDR3_LO 0x0420 47984059Swpaul#define BGE_MAC_ADDR3_HI 0x0424 48084059Swpaul#define BGE_MAC_ADDR4_LO 0x0428 48184059Swpaul#define BGE_MAC_ADDR4_HI 0x042C 48284059Swpaul#define BGE_WOL_PATPTR 0x0430 48384059Swpaul#define BGE_WOL_PATCFG 0x0434 48484059Swpaul#define BGE_TX_RANDOM_BACKOFF 0x0438 48584059Swpaul#define BGE_RX_MTU 0x043C 48684059Swpaul#define BGE_GBIT_PCS_TEST 0x0440 48784059Swpaul#define BGE_TX_TBI_AUTONEG 0x0444 48884059Swpaul#define BGE_RX_TBI_AUTONEG 0x0448 48984059Swpaul#define BGE_MI_COMM 0x044C 49084059Swpaul#define BGE_MI_STS 0x0450 49184059Swpaul#define BGE_MI_MODE 0x0454 49284059Swpaul#define BGE_AUTOPOLL_STS 0x0458 49384059Swpaul#define BGE_TX_MODE 0x045C 49484059Swpaul#define BGE_TX_STS 0x0460 49584059Swpaul#define BGE_TX_LENGTHS 0x0464 49684059Swpaul#define BGE_RX_MODE 0x0468 49784059Swpaul#define BGE_RX_STS 0x046C 49884059Swpaul#define BGE_MAR0 0x0470 49984059Swpaul#define BGE_MAR1 0x0474 50084059Swpaul#define BGE_MAR2 0x0478 50184059Swpaul#define BGE_MAR3 0x047C 50284059Swpaul#define BGE_RX_BD_RULES_CTL0 0x0480 50384059Swpaul#define BGE_RX_BD_RULES_MASKVAL0 0x0484 50484059Swpaul#define BGE_RX_BD_RULES_CTL1 0x0488 50584059Swpaul#define BGE_RX_BD_RULES_MASKVAL1 0x048C 50684059Swpaul#define BGE_RX_BD_RULES_CTL2 0x0490 50784059Swpaul#define BGE_RX_BD_RULES_MASKVAL2 0x0494 50884059Swpaul#define BGE_RX_BD_RULES_CTL3 0x0498 50984059Swpaul#define BGE_RX_BD_RULES_MASKVAL3 0x049C 51084059Swpaul#define BGE_RX_BD_RULES_CTL4 0x04A0 51184059Swpaul#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 51284059Swpaul#define BGE_RX_BD_RULES_CTL5 0x04A8 51384059Swpaul#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 51484059Swpaul#define BGE_RX_BD_RULES_CTL6 0x04B0 51584059Swpaul#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 51684059Swpaul#define BGE_RX_BD_RULES_CTL7 0x04B8 51784059Swpaul#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 51884059Swpaul#define BGE_RX_BD_RULES_CTL8 0x04C0 51984059Swpaul#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 52084059Swpaul#define BGE_RX_BD_RULES_CTL9 0x04C8 52184059Swpaul#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 52284059Swpaul#define BGE_RX_BD_RULES_CTL10 0x04D0 52384059Swpaul#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 52484059Swpaul#define BGE_RX_BD_RULES_CTL11 0x04D8 52584059Swpaul#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 52684059Swpaul#define BGE_RX_BD_RULES_CTL12 0x04E0 52784059Swpaul#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 52884059Swpaul#define BGE_RX_BD_RULES_CTL13 0x04E8 52984059Swpaul#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 53084059Swpaul#define BGE_RX_BD_RULES_CTL14 0x04F0 53184059Swpaul#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 53284059Swpaul#define BGE_RX_BD_RULES_CTL15 0x04F8 53384059Swpaul#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 53484059Swpaul#define BGE_RX_RULES_CFG 0x0500 535130273Swpaul#define BGE_SERDES_CFG 0x0590 536130273Swpaul#define BGE_SERDES_STS 0x0594 537130273Swpaul#define BGE_SGDIG_CFG 0x05B0 538130273Swpaul#define BGE_SGDIG_STS 0x05B4 53984059Swpaul#define BGE_RX_STATS 0x0800 54084059Swpaul#define BGE_TX_STATS 0x0880 54184059Swpaul 54284059Swpaul/* Ethernet MAC Mode register */ 54384059Swpaul#define BGE_MACMODE_RESET 0x00000001 54484059Swpaul#define BGE_MACMODE_HALF_DUPLEX 0x00000002 54584059Swpaul#define BGE_MACMODE_PORTMODE 0x0000000C 54684059Swpaul#define BGE_MACMODE_LOOPBACK 0x00000010 54784059Swpaul#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 54884059Swpaul#define BGE_MACMODE_TX_BURST_ENB 0x00000100 54984059Swpaul#define BGE_MACMODE_MAX_DEFER 0x00000200 55084059Swpaul#define BGE_MACMODE_LINK_POLARITY 0x00000400 55184059Swpaul#define BGE_MACMODE_RX_STATS_ENB 0x00000800 55284059Swpaul#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 55384059Swpaul#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 55484059Swpaul#define BGE_MACMODE_TX_STATS_ENB 0x00004000 55584059Swpaul#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 55684059Swpaul#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 55784059Swpaul#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 55884059Swpaul#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 55984059Swpaul#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 56084059Swpaul#define BGE_MACMODE_MIP_ENB 0x00100000 56184059Swpaul#define BGE_MACMODE_TXDMA_ENB 0x00200000 56284059Swpaul#define BGE_MACMODE_RXDMA_ENB 0x00400000 56384059Swpaul#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 56484059Swpaul 56584059Swpaul#define BGE_PORTMODE_NONE 0x00000000 56684059Swpaul#define BGE_PORTMODE_MII 0x00000004 56784059Swpaul#define BGE_PORTMODE_GMII 0x00000008 56884059Swpaul#define BGE_PORTMODE_TBI 0x0000000C 56984059Swpaul 57084059Swpaul/* MAC Status register */ 57184059Swpaul#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 57284059Swpaul#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 57384059Swpaul#define BGE_MACSTAT_RX_CFG 0x00000004 57484059Swpaul#define BGE_MACSTAT_CFG_CHANGED 0x00000008 57584059Swpaul#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 57684059Swpaul#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 57784059Swpaul#define BGE_MACSTAT_LINK_CHANGED 0x00001000 57884059Swpaul#define BGE_MACSTAT_MI_COMPLETE 0x00400000 57984059Swpaul#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 58084059Swpaul#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 58184059Swpaul#define BGE_MACSTAT_ODI_ERROR 0x02000000 58284059Swpaul#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 58384059Swpaul#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 58484059Swpaul 58584059Swpaul/* MAC Event Enable Register */ 58684059Swpaul#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 58784059Swpaul#define BGE_EVTENB_LINK_CHANGED 0x00001000 58884059Swpaul#define BGE_EVTENB_MI_COMPLETE 0x00400000 58984059Swpaul#define BGE_EVTENB_MI_INTERRUPT 0x00800000 59084059Swpaul#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 59184059Swpaul#define BGE_EVTENB_ODI_ERROR 0x02000000 59284059Swpaul#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 59384059Swpaul#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 59484059Swpaul 59584059Swpaul/* LED Control Register */ 59684059Swpaul#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 59784059Swpaul#define BGE_LEDCTL_1000MBPS_LED 0x00000002 59884059Swpaul#define BGE_LEDCTL_100MBPS_LED 0x00000004 59984059Swpaul#define BGE_LEDCTL_10MBPS_LED 0x00000008 60084059Swpaul#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 60184059Swpaul#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 60284059Swpaul#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 60384059Swpaul#define BGE_LEDCTL_1000MBPS_STS 0x00000080 60484059Swpaul#define BGE_LEDCTL_100MBPS_STS 0x00000100 60584059Swpaul#define BGE_LEDCTL_10MBPS_STS 0x00000200 60684059Swpaul#define BGE_LEDCTL_TRADLED_STS 0x00000400 60784059Swpaul#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 60884059Swpaul#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 60984059Swpaul 61084059Swpaul/* TX backoff seed register */ 61184059Swpaul#define BGE_TX_BACKOFF_SEED_MASK 0x3F 61284059Swpaul 61384059Swpaul/* Autopoll status register */ 61484059Swpaul#define BGE_AUTOPOLLSTS_ERROR 0x00000001 61584059Swpaul 61684059Swpaul/* Transmit MAC mode register */ 61784059Swpaul#define BGE_TXMODE_RESET 0x00000001 61884059Swpaul#define BGE_TXMODE_ENABLE 0x00000002 61984059Swpaul#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 62084059Swpaul#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 62184059Swpaul#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 62284059Swpaul 62384059Swpaul/* Transmit MAC status register */ 62484059Swpaul#define BGE_TXSTAT_RX_XOFFED 0x00000001 62584059Swpaul#define BGE_TXSTAT_SENT_XOFF 0x00000002 62684059Swpaul#define BGE_TXSTAT_SENT_XON 0x00000004 62784059Swpaul#define BGE_TXSTAT_LINK_UP 0x00000008 62884059Swpaul#define BGE_TXSTAT_ODI_UFLOW 0x00000010 62984059Swpaul#define BGE_TXSTAT_ODI_OFLOW 0x00000020 63084059Swpaul 63184059Swpaul/* Transmit MAC lengths register */ 63284059Swpaul#define BGE_TXLEN_SLOTTIME 0x000000FF 63384059Swpaul#define BGE_TXLEN_IPG 0x00000F00 63484059Swpaul#define BGE_TXLEN_CRS 0x00003000 63584059Swpaul 63684059Swpaul/* Receive MAC mode register */ 63784059Swpaul#define BGE_RXMODE_RESET 0x00000001 63884059Swpaul#define BGE_RXMODE_ENABLE 0x00000002 63984059Swpaul#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 64084059Swpaul#define BGE_RXMODE_RX_GIANTS 0x00000020 64184059Swpaul#define BGE_RXMODE_RX_RUNTS 0x00000040 64284059Swpaul#define BGE_RXMODE_8022_LENCHECK 0x00000080 64384059Swpaul#define BGE_RXMODE_RX_PROMISC 0x00000100 64484059Swpaul#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 64584059Swpaul#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 64684059Swpaul 64784059Swpaul/* Receive MAC status register */ 64884059Swpaul#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 64984059Swpaul#define BGE_RXSTAT_RCVD_XOFF 0x00000002 65084059Swpaul#define BGE_RXSTAT_RCVD_XON 0x00000004 65184059Swpaul 65284059Swpaul/* Receive Rules Control register */ 65384059Swpaul#define BGE_RXRULECTL_OFFSET 0x000000FF 65484059Swpaul#define BGE_RXRULECTL_CLASS 0x00001F00 65584059Swpaul#define BGE_RXRULECTL_HDRTYPE 0x0000E000 65684059Swpaul#define BGE_RXRULECTL_COMPARE_OP 0x00030000 65784059Swpaul#define BGE_RXRULECTL_MAP 0x01000000 65884059Swpaul#define BGE_RXRULECTL_DISCARD 0x02000000 65984059Swpaul#define BGE_RXRULECTL_MASK 0x04000000 66084059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 66184059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 66284059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 66384059Swpaul#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 66484059Swpaul 66584059Swpaul/* Receive Rules Mask register */ 66684059Swpaul#define BGE_RXRULEMASK_VALUE 0x0000FFFF 66784059Swpaul#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 66884059Swpaul 669130273Swpaul/* SERDES configuration register */ 670130273Swpaul#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 671130273Swpaul#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 672130273Swpaul#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 673130273Swpaul#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 674130273Swpaul#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 675130273Swpaul#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 676130273Swpaul#define BGE_SERDESCFG_TXMODE 0x00001000 677130273Swpaul#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 678130273Swpaul#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 679130273Swpaul#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 680130273Swpaul#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 681130273Swpaul#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 682130273Swpaul#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 683130273Swpaul#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 684130273Swpaul#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 685130273Swpaul#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 686130273Swpaul 687130273Swpaul/* SERDES status register */ 688130273Swpaul#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 689130273Swpaul#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 690130273Swpaul 691130273Swpaul/* SGDIG config (not documented) */ 692130273Swpaul#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 693130273Swpaul#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 694130273Swpaul#define BGE_SGDIGCFG_SEND 0x40000000 695130273Swpaul#define BGE_SGDIGCFG_AUTO 0x80000000 696130273Swpaul 697130273Swpaul/* SGDIG status (not documented) */ 698130273Swpaul#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 699130273Swpaul#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 700130273Swpaul#define BGE_SGDIGSTS_DONE 0x00000002 701130273Swpaul 702130273Swpaul 70384059Swpaul/* MI communication register */ 70484059Swpaul#define BGE_MICOMM_DATA 0x0000FFFF 70584059Swpaul#define BGE_MICOMM_REG 0x001F0000 70684059Swpaul#define BGE_MICOMM_PHY 0x03E00000 70784059Swpaul#define BGE_MICOMM_CMD 0x0C000000 70884059Swpaul#define BGE_MICOMM_READFAIL 0x10000000 70984059Swpaul#define BGE_MICOMM_BUSY 0x20000000 71084059Swpaul 71184059Swpaul#define BGE_MIREG(x) ((x & 0x1F) << 16) 71284059Swpaul#define BGE_MIPHY(x) ((x & 0x1F) << 21) 71384059Swpaul#define BGE_MICMD_WRITE 0x04000000 71484059Swpaul#define BGE_MICMD_READ 0x08000000 71584059Swpaul 71684059Swpaul/* MI status register */ 71784059Swpaul#define BGE_MISTS_LINK 0x00000001 71884059Swpaul#define BGE_MISTS_10MBPS 0x00000002 71984059Swpaul 72084059Swpaul#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 72184059Swpaul#define BGE_MIMODE_AUTOPOLL 0x00000010 72284059Swpaul#define BGE_MIMODE_CLKCNT 0x001F0000 72384059Swpaul 72484059Swpaul 72584059Swpaul/* 72684059Swpaul * Send data initiator control registers. 72784059Swpaul */ 72884059Swpaul#define BGE_SDI_MODE 0x0C00 72984059Swpaul#define BGE_SDI_STATUS 0x0C04 73084059Swpaul#define BGE_SDI_STATS_CTL 0x0C08 73184059Swpaul#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 73284059Swpaul#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 73384059Swpaul#define BGE_LOCSTATS_COS0 0x0C80 73484059Swpaul#define BGE_LOCSTATS_COS1 0x0C84 73584059Swpaul#define BGE_LOCSTATS_COS2 0x0C88 73684059Swpaul#define BGE_LOCSTATS_COS3 0x0C8C 73784059Swpaul#define BGE_LOCSTATS_COS4 0x0C90 73884059Swpaul#define BGE_LOCSTATS_COS5 0x0C84 73984059Swpaul#define BGE_LOCSTATS_COS6 0x0C98 74084059Swpaul#define BGE_LOCSTATS_COS7 0x0C9C 74184059Swpaul#define BGE_LOCSTATS_COS8 0x0CA0 74284059Swpaul#define BGE_LOCSTATS_COS9 0x0CA4 74384059Swpaul#define BGE_LOCSTATS_COS10 0x0CA8 74484059Swpaul#define BGE_LOCSTATS_COS11 0x0CAC 74584059Swpaul#define BGE_LOCSTATS_COS12 0x0CB0 74684059Swpaul#define BGE_LOCSTATS_COS13 0x0CB4 74784059Swpaul#define BGE_LOCSTATS_COS14 0x0CB8 74884059Swpaul#define BGE_LOCSTATS_COS15 0x0CBC 74984059Swpaul#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 75084059Swpaul#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 75184059Swpaul#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 75284059Swpaul#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 75384059Swpaul#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 75484059Swpaul#define BGE_LOCSTATS_IRQS 0x0CD4 75584059Swpaul#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 75684059Swpaul#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 75784059Swpaul 75884059Swpaul/* Send Data Initiator mode register */ 75984059Swpaul#define BGE_SDIMODE_RESET 0x00000001 76084059Swpaul#define BGE_SDIMODE_ENABLE 0x00000002 76184059Swpaul#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 76284059Swpaul 76384059Swpaul/* Send Data Initiator stats register */ 76484059Swpaul#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 76584059Swpaul 76684059Swpaul/* Send Data Initiator stats control register */ 76784059Swpaul#define BGE_SDISTATSCTL_ENABLE 0x00000001 76884059Swpaul#define BGE_SDISTATSCTL_FASTER 0x00000002 76984059Swpaul#define BGE_SDISTATSCTL_CLEAR 0x00000004 77084059Swpaul#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 77184059Swpaul#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 77284059Swpaul 77384059Swpaul/* 77484059Swpaul * Send Data Completion Control registers 77584059Swpaul */ 77684059Swpaul#define BGE_SDC_MODE 0x1000 77784059Swpaul#define BGE_SDC_STATUS 0x1004 77884059Swpaul 77984059Swpaul/* Send Data completion mode register */ 78084059Swpaul#define BGE_SDCMODE_RESET 0x00000001 78184059Swpaul#define BGE_SDCMODE_ENABLE 0x00000002 78284059Swpaul#define BGE_SDCMODE_ATTN 0x00000004 78384059Swpaul 78484059Swpaul/* Send Data completion status register */ 78584059Swpaul#define BGE_SDCSTAT_ATTN 0x00000004 78684059Swpaul 78784059Swpaul/* 78884059Swpaul * Send BD Ring Selector Control registers 78984059Swpaul */ 79084059Swpaul#define BGE_SRS_MODE 0x1400 79184059Swpaul#define BGE_SRS_STATUS 0x1404 79284059Swpaul#define BGE_SRS_HWDIAG 0x1408 79384059Swpaul#define BGE_SRS_LOC_NIC_CONS0 0x1440 79484059Swpaul#define BGE_SRS_LOC_NIC_CONS1 0x1444 79584059Swpaul#define BGE_SRS_LOC_NIC_CONS2 0x1448 79684059Swpaul#define BGE_SRS_LOC_NIC_CONS3 0x144C 79784059Swpaul#define BGE_SRS_LOC_NIC_CONS4 0x1450 79884059Swpaul#define BGE_SRS_LOC_NIC_CONS5 0x1454 79984059Swpaul#define BGE_SRS_LOC_NIC_CONS6 0x1458 80084059Swpaul#define BGE_SRS_LOC_NIC_CONS7 0x145C 80184059Swpaul#define BGE_SRS_LOC_NIC_CONS8 0x1460 80284059Swpaul#define BGE_SRS_LOC_NIC_CONS9 0x1464 80384059Swpaul#define BGE_SRS_LOC_NIC_CONS10 0x1468 80484059Swpaul#define BGE_SRS_LOC_NIC_CONS11 0x146C 80584059Swpaul#define BGE_SRS_LOC_NIC_CONS12 0x1470 80684059Swpaul#define BGE_SRS_LOC_NIC_CONS13 0x1474 80784059Swpaul#define BGE_SRS_LOC_NIC_CONS14 0x1478 80884059Swpaul#define BGE_SRS_LOC_NIC_CONS15 0x147C 80984059Swpaul 81084059Swpaul/* Send BD Ring Selector Mode register */ 81184059Swpaul#define BGE_SRSMODE_RESET 0x00000001 81284059Swpaul#define BGE_SRSMODE_ENABLE 0x00000002 81384059Swpaul#define BGE_SRSMODE_ATTN 0x00000004 81484059Swpaul 81584059Swpaul/* Send BD Ring Selector Status register */ 81684059Swpaul#define BGE_SRSSTAT_ERROR 0x00000004 81784059Swpaul 81884059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 81984059Swpaul#define BGE_SRSHWDIAG_STATE 0x0000000F 82084059Swpaul#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 82184059Swpaul#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 82284059Swpaul#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 82384059Swpaul 82484059Swpaul/* 82584059Swpaul * Send BD Initiator Selector Control registers 82684059Swpaul */ 82784059Swpaul#define BGE_SBDI_MODE 0x1800 82884059Swpaul#define BGE_SBDI_STATUS 0x1804 82984059Swpaul#define BGE_SBDI_LOC_NIC_PROD0 0x1808 83084059Swpaul#define BGE_SBDI_LOC_NIC_PROD1 0x180C 83184059Swpaul#define BGE_SBDI_LOC_NIC_PROD2 0x1810 83284059Swpaul#define BGE_SBDI_LOC_NIC_PROD3 0x1814 83384059Swpaul#define BGE_SBDI_LOC_NIC_PROD4 0x1818 83484059Swpaul#define BGE_SBDI_LOC_NIC_PROD5 0x181C 83584059Swpaul#define BGE_SBDI_LOC_NIC_PROD6 0x1820 83684059Swpaul#define BGE_SBDI_LOC_NIC_PROD7 0x1824 83784059Swpaul#define BGE_SBDI_LOC_NIC_PROD8 0x1828 83884059Swpaul#define BGE_SBDI_LOC_NIC_PROD9 0x182C 83984059Swpaul#define BGE_SBDI_LOC_NIC_PROD10 0x1830 84084059Swpaul#define BGE_SBDI_LOC_NIC_PROD11 0x1834 84184059Swpaul#define BGE_SBDI_LOC_NIC_PROD12 0x1838 84284059Swpaul#define BGE_SBDI_LOC_NIC_PROD13 0x183C 84384059Swpaul#define BGE_SBDI_LOC_NIC_PROD14 0x1840 84484059Swpaul#define BGE_SBDI_LOC_NIC_PROD15 0x1844 84584059Swpaul 84684059Swpaul/* Send BD Initiator Mode register */ 84784059Swpaul#define BGE_SBDIMODE_RESET 0x00000001 84884059Swpaul#define BGE_SBDIMODE_ENABLE 0x00000002 84984059Swpaul#define BGE_SBDIMODE_ATTN 0x00000004 85084059Swpaul 85184059Swpaul/* Send BD Initiator Status register */ 85284059Swpaul#define BGE_SBDISTAT_ERROR 0x00000004 85384059Swpaul 85484059Swpaul/* 85584059Swpaul * Send BD Completion Control registers 85684059Swpaul */ 85784059Swpaul#define BGE_SBDC_MODE 0x1C00 85884059Swpaul#define BGE_SBDC_STATUS 0x1C04 85984059Swpaul 86084059Swpaul/* Send BD Completion Control Mode register */ 86184059Swpaul#define BGE_SBDCMODE_RESET 0x00000001 86284059Swpaul#define BGE_SBDCMODE_ENABLE 0x00000002 86384059Swpaul#define BGE_SBDCMODE_ATTN 0x00000004 86484059Swpaul 86584059Swpaul/* Send BD Completion Control Status register */ 86684059Swpaul#define BGE_SBDCSTAT_ATTN 0x00000004 86784059Swpaul 86884059Swpaul/* 86984059Swpaul * Receive List Placement Control registers 87084059Swpaul */ 87184059Swpaul#define BGE_RXLP_MODE 0x2000 87284059Swpaul#define BGE_RXLP_STATUS 0x2004 87384059Swpaul#define BGE_RXLP_SEL_LIST_LOCK 0x2008 87484059Swpaul#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 87584059Swpaul#define BGE_RXLP_CFG 0x2010 87684059Swpaul#define BGE_RXLP_STATS_CTL 0x2014 87784059Swpaul#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 87884059Swpaul#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 87984059Swpaul#define BGE_RXLP_HEAD0 0x2100 88084059Swpaul#define BGE_RXLP_TAIL0 0x2104 88184059Swpaul#define BGE_RXLP_COUNT0 0x2108 88284059Swpaul#define BGE_RXLP_HEAD1 0x2110 88384059Swpaul#define BGE_RXLP_TAIL1 0x2114 88484059Swpaul#define BGE_RXLP_COUNT1 0x2118 88584059Swpaul#define BGE_RXLP_HEAD2 0x2120 88684059Swpaul#define BGE_RXLP_TAIL2 0x2124 88784059Swpaul#define BGE_RXLP_COUNT2 0x2128 88884059Swpaul#define BGE_RXLP_HEAD3 0x2130 88984059Swpaul#define BGE_RXLP_TAIL3 0x2134 89084059Swpaul#define BGE_RXLP_COUNT3 0x2138 89184059Swpaul#define BGE_RXLP_HEAD4 0x2140 89284059Swpaul#define BGE_RXLP_TAIL4 0x2144 89384059Swpaul#define BGE_RXLP_COUNT4 0x2148 89484059Swpaul#define BGE_RXLP_HEAD5 0x2150 89584059Swpaul#define BGE_RXLP_TAIL5 0x2154 89684059Swpaul#define BGE_RXLP_COUNT5 0x2158 89784059Swpaul#define BGE_RXLP_HEAD6 0x2160 89884059Swpaul#define BGE_RXLP_TAIL6 0x2164 89984059Swpaul#define BGE_RXLP_COUNT6 0x2168 90084059Swpaul#define BGE_RXLP_HEAD7 0x2170 90184059Swpaul#define BGE_RXLP_TAIL7 0x2174 90284059Swpaul#define BGE_RXLP_COUNT7 0x2178 90384059Swpaul#define BGE_RXLP_HEAD8 0x2180 90484059Swpaul#define BGE_RXLP_TAIL8 0x2184 90584059Swpaul#define BGE_RXLP_COUNT8 0x2188 90684059Swpaul#define BGE_RXLP_HEAD9 0x2190 90784059Swpaul#define BGE_RXLP_TAIL9 0x2194 90884059Swpaul#define BGE_RXLP_COUNT9 0x2198 90984059Swpaul#define BGE_RXLP_HEAD10 0x21A0 91084059Swpaul#define BGE_RXLP_TAIL10 0x21A4 91184059Swpaul#define BGE_RXLP_COUNT10 0x21A8 91284059Swpaul#define BGE_RXLP_HEAD11 0x21B0 91384059Swpaul#define BGE_RXLP_TAIL11 0x21B4 91484059Swpaul#define BGE_RXLP_COUNT11 0x21B8 91584059Swpaul#define BGE_RXLP_HEAD12 0x21C0 91684059Swpaul#define BGE_RXLP_TAIL12 0x21C4 91784059Swpaul#define BGE_RXLP_COUNT12 0x21C8 91884059Swpaul#define BGE_RXLP_HEAD13 0x21D0 91984059Swpaul#define BGE_RXLP_TAIL13 0x21D4 92084059Swpaul#define BGE_RXLP_COUNT13 0x21D8 92184059Swpaul#define BGE_RXLP_HEAD14 0x21E0 92284059Swpaul#define BGE_RXLP_TAIL14 0x21E4 92384059Swpaul#define BGE_RXLP_COUNT14 0x21E8 92484059Swpaul#define BGE_RXLP_HEAD15 0x21F0 92584059Swpaul#define BGE_RXLP_TAIL15 0x21F4 92684059Swpaul#define BGE_RXLP_COUNT15 0x21F8 92784059Swpaul#define BGE_RXLP_LOCSTAT_COS0 0x2200 92884059Swpaul#define BGE_RXLP_LOCSTAT_COS1 0x2204 92984059Swpaul#define BGE_RXLP_LOCSTAT_COS2 0x2208 93084059Swpaul#define BGE_RXLP_LOCSTAT_COS3 0x220C 93184059Swpaul#define BGE_RXLP_LOCSTAT_COS4 0x2210 93284059Swpaul#define BGE_RXLP_LOCSTAT_COS5 0x2214 93384059Swpaul#define BGE_RXLP_LOCSTAT_COS6 0x2218 93484059Swpaul#define BGE_RXLP_LOCSTAT_COS7 0x221C 93584059Swpaul#define BGE_RXLP_LOCSTAT_COS8 0x2220 93684059Swpaul#define BGE_RXLP_LOCSTAT_COS9 0x2224 93784059Swpaul#define BGE_RXLP_LOCSTAT_COS10 0x2228 93884059Swpaul#define BGE_RXLP_LOCSTAT_COS11 0x222C 93984059Swpaul#define BGE_RXLP_LOCSTAT_COS12 0x2230 94084059Swpaul#define BGE_RXLP_LOCSTAT_COS13 0x2234 94184059Swpaul#define BGE_RXLP_LOCSTAT_COS14 0x2238 94284059Swpaul#define BGE_RXLP_LOCSTAT_COS15 0x223C 94384059Swpaul#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 94484059Swpaul#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 94584059Swpaul#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 94684059Swpaul#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 94784059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 94884059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 94984059Swpaul#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 95084059Swpaul 95184059Swpaul 95284059Swpaul/* Receive List Placement mode register */ 95384059Swpaul#define BGE_RXLPMODE_RESET 0x00000001 95484059Swpaul#define BGE_RXLPMODE_ENABLE 0x00000002 95584059Swpaul#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 95684059Swpaul#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 95784059Swpaul#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 95884059Swpaul 95984059Swpaul/* Receive List Placement Status register */ 96084059Swpaul#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 96184059Swpaul#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 96284059Swpaul#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 96384059Swpaul 96484059Swpaul/* 96584059Swpaul * Receive Data and Receive BD Initiator Control Registers 96684059Swpaul */ 96784059Swpaul#define BGE_RDBDI_MODE 0x2400 96884059Swpaul#define BGE_RDBDI_STATUS 0x2404 96984059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 97084059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 97184059Swpaul#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 97284059Swpaul#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 97384059Swpaul#define BGE_RX_STD_RCB_HADDR_HI 0x2450 97484059Swpaul#define BGE_RX_STD_RCB_HADDR_LO 0x2454 97584059Swpaul#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 97684059Swpaul#define BGE_RX_STD_RCB_NICADDR 0x245C 97784059Swpaul#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 97884059Swpaul#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 97984059Swpaul#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 98084059Swpaul#define BGE_RX_MINI_RCB_NICADDR 0x246C 98184059Swpaul#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 98284059Swpaul#define BGE_RDBDI_STD_RX_CONS 0x2474 98384059Swpaul#define BGE_RDBDI_MINI_RX_CONS 0x2478 98484059Swpaul#define BGE_RDBDI_RETURN_PROD0 0x2480 98584059Swpaul#define BGE_RDBDI_RETURN_PROD1 0x2484 98684059Swpaul#define BGE_RDBDI_RETURN_PROD2 0x2488 98784059Swpaul#define BGE_RDBDI_RETURN_PROD3 0x248C 98884059Swpaul#define BGE_RDBDI_RETURN_PROD4 0x2490 98984059Swpaul#define BGE_RDBDI_RETURN_PROD5 0x2494 99084059Swpaul#define BGE_RDBDI_RETURN_PROD6 0x2498 99184059Swpaul#define BGE_RDBDI_RETURN_PROD7 0x249C 99284059Swpaul#define BGE_RDBDI_RETURN_PROD8 0x24A0 99384059Swpaul#define BGE_RDBDI_RETURN_PROD9 0x24A4 99484059Swpaul#define BGE_RDBDI_RETURN_PROD10 0x24A8 99584059Swpaul#define BGE_RDBDI_RETURN_PROD11 0x24AC 99684059Swpaul#define BGE_RDBDI_RETURN_PROD12 0x24B0 99784059Swpaul#define BGE_RDBDI_RETURN_PROD13 0x24B4 99884059Swpaul#define BGE_RDBDI_RETURN_PROD14 0x24B8 99984059Swpaul#define BGE_RDBDI_RETURN_PROD15 0x24BC 100084059Swpaul#define BGE_RDBDI_HWDIAG 0x24C0 100184059Swpaul 100284059Swpaul 100384059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 100484059Swpaul#define BGE_RDBDIMODE_RESET 0x00000001 100584059Swpaul#define BGE_RDBDIMODE_ENABLE 0x00000002 100684059Swpaul#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 100784059Swpaul#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 100884059Swpaul#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 100984059Swpaul 101084059Swpaul/* Receive Data and Receive BD Initiator Status register */ 101184059Swpaul#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 101284059Swpaul#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 101384059Swpaul#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 101484059Swpaul 101584059Swpaul 101684059Swpaul/* 101784059Swpaul * Receive Data Completion Control registers 101884059Swpaul */ 101984059Swpaul#define BGE_RDC_MODE 0x2800 102084059Swpaul 102184059Swpaul/* Receive Data Completion Mode register */ 102284059Swpaul#define BGE_RDCMODE_RESET 0x00000001 102384059Swpaul#define BGE_RDCMODE_ENABLE 0x00000002 102484059Swpaul#define BGE_RDCMODE_ATTN 0x00000004 102584059Swpaul 102684059Swpaul/* 102784059Swpaul * Receive BD Initiator Control registers 102884059Swpaul */ 102984059Swpaul#define BGE_RBDI_MODE 0x2C00 103084059Swpaul#define BGE_RBDI_STATUS 0x2C04 103184059Swpaul#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 103284059Swpaul#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 103384059Swpaul#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 103484059Swpaul#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 103584059Swpaul#define BGE_RBDI_STD_REPL_THRESH 0x2C18 103684059Swpaul#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 103784059Swpaul 103884059Swpaul/* Receive BD Initiator Mode register */ 103984059Swpaul#define BGE_RBDIMODE_RESET 0x00000001 104084059Swpaul#define BGE_RBDIMODE_ENABLE 0x00000002 104184059Swpaul#define BGE_RBDIMODE_ATTN 0x00000004 104284059Swpaul 104384059Swpaul/* Receive BD Initiator Status register */ 104484059Swpaul#define BGE_RBDISTAT_ATTN 0x00000004 104584059Swpaul 104684059Swpaul/* 104784059Swpaul * Receive BD Completion Control registers 104884059Swpaul */ 104984059Swpaul#define BGE_RBDC_MODE 0x3000 105084059Swpaul#define BGE_RBDC_STATUS 0x3004 105184059Swpaul#define BGE_RBDC_JUMBO_BD_PROD 0x3008 105284059Swpaul#define BGE_RBDC_STD_BD_PROD 0x300C 105384059Swpaul#define BGE_RBDC_MINI_BD_PROD 0x3010 105484059Swpaul 105584059Swpaul/* Receive BD completion mode register */ 105684059Swpaul#define BGE_RBDCMODE_RESET 0x00000001 105784059Swpaul#define BGE_RBDCMODE_ENABLE 0x00000002 105884059Swpaul#define BGE_RBDCMODE_ATTN 0x00000004 105984059Swpaul 106084059Swpaul/* Receive BD completion status register */ 106184059Swpaul#define BGE_RBDCSTAT_ERROR 0x00000004 106284059Swpaul 106384059Swpaul/* 106484059Swpaul * Receive List Selector Control registers 106584059Swpaul */ 106684059Swpaul#define BGE_RXLS_MODE 0x3400 106784059Swpaul#define BGE_RXLS_STATUS 0x3404 106884059Swpaul 106984059Swpaul/* Receive List Selector Mode register */ 107084059Swpaul#define BGE_RXLSMODE_RESET 0x00000001 107184059Swpaul#define BGE_RXLSMODE_ENABLE 0x00000002 107284059Swpaul#define BGE_RXLSMODE_ATTN 0x00000004 107384059Swpaul 107484059Swpaul/* Receive List Selector Status register */ 107584059Swpaul#define BGE_RXLSSTAT_ERROR 0x00000004 107684059Swpaul 107784059Swpaul/* 107884059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 107984059Swpaul */ 108084059Swpaul#define BGE_MBCF_MODE 0x3800 108184059Swpaul#define BGE_MBCF_STATUS 0x3804 108284059Swpaul 108384059Swpaul/* Mbuf Cluster Free mode register */ 108484059Swpaul#define BGE_MBCFMODE_RESET 0x00000001 108584059Swpaul#define BGE_MBCFMODE_ENABLE 0x00000002 108684059Swpaul#define BGE_MBCFMODE_ATTN 0x00000004 108784059Swpaul 108884059Swpaul/* Mbuf Cluster Free status register */ 108984059Swpaul#define BGE_MBCFSTAT_ERROR 0x00000004 109084059Swpaul 109184059Swpaul/* 109284059Swpaul * Host Coalescing Control registers 109384059Swpaul */ 109484059Swpaul#define BGE_HCC_MODE 0x3C00 109584059Swpaul#define BGE_HCC_STATUS 0x3C04 109684059Swpaul#define BGE_HCC_RX_COAL_TICKS 0x3C08 109784059Swpaul#define BGE_HCC_TX_COAL_TICKS 0x3C0C 109884059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 109984059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 110084059Swpaul#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 110184059Swpaul#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 110284059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1103119047Sps#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 110484059Swpaul#define BGE_HCC_STATS_TICKS 0x3C28 110584059Swpaul#define BGE_HCC_STATS_ADDR_HI 0x3C30 110684059Swpaul#define BGE_HCC_STATS_ADDR_LO 0x3C34 110784059Swpaul#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 110884059Swpaul#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 110984059Swpaul#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 111084059Swpaul#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 111184059Swpaul#define BGE_FLOW_ATTN 0x3C48 111284059Swpaul#define BGE_HCC_JUMBO_BD_CONS 0x3C50 111384059Swpaul#define BGE_HCC_STD_BD_CONS 0x3C54 111484059Swpaul#define BGE_HCC_MINI_BD_CONS 0x3C58 111584059Swpaul#define BGE_HCC_RX_RETURN_PROD0 0x3C80 111684059Swpaul#define BGE_HCC_RX_RETURN_PROD1 0x3C84 111784059Swpaul#define BGE_HCC_RX_RETURN_PROD2 0x3C88 111884059Swpaul#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 111984059Swpaul#define BGE_HCC_RX_RETURN_PROD4 0x3C90 112084059Swpaul#define BGE_HCC_RX_RETURN_PROD5 0x3C94 112184059Swpaul#define BGE_HCC_RX_RETURN_PROD6 0x3C98 112284059Swpaul#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 112384059Swpaul#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 112484059Swpaul#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 112584059Swpaul#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 112684059Swpaul#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 112784059Swpaul#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 112884059Swpaul#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 112984059Swpaul#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 113084059Swpaul#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 113184059Swpaul#define BGE_HCC_TX_BD_CONS0 0x3CC0 113284059Swpaul#define BGE_HCC_TX_BD_CONS1 0x3CC4 113384059Swpaul#define BGE_HCC_TX_BD_CONS2 0x3CC8 113484059Swpaul#define BGE_HCC_TX_BD_CONS3 0x3CCC 113584059Swpaul#define BGE_HCC_TX_BD_CONS4 0x3CD0 113684059Swpaul#define BGE_HCC_TX_BD_CONS5 0x3CD4 113784059Swpaul#define BGE_HCC_TX_BD_CONS6 0x3CD8 113884059Swpaul#define BGE_HCC_TX_BD_CONS7 0x3CDC 113984059Swpaul#define BGE_HCC_TX_BD_CONS8 0x3CE0 114084059Swpaul#define BGE_HCC_TX_BD_CONS9 0x3CE4 114184059Swpaul#define BGE_HCC_TX_BD_CONS10 0x3CE8 114284059Swpaul#define BGE_HCC_TX_BD_CONS11 0x3CEC 114384059Swpaul#define BGE_HCC_TX_BD_CONS12 0x3CF0 114484059Swpaul#define BGE_HCC_TX_BD_CONS13 0x3CF4 114584059Swpaul#define BGE_HCC_TX_BD_CONS14 0x3CF8 114684059Swpaul#define BGE_HCC_TX_BD_CONS15 0x3CFC 114784059Swpaul 114884059Swpaul 114984059Swpaul/* Host coalescing mode register */ 115084059Swpaul#define BGE_HCCMODE_RESET 0x00000001 115184059Swpaul#define BGE_HCCMODE_ENABLE 0x00000002 115284059Swpaul#define BGE_HCCMODE_ATTN 0x00000004 115384059Swpaul#define BGE_HCCMODE_COAL_NOW 0x00000008 115484059Swpaul#define BGE_HCCMODE_MSI_BITS 0x0x000070 115584059Swpaul#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 115684059Swpaul 115784059Swpaul#define BGE_STATBLKSZ_FULL 0x00000000 115884059Swpaul#define BGE_STATBLKSZ_64BYTE 0x00000080 115984059Swpaul#define BGE_STATBLKSZ_32BYTE 0x00000100 116084059Swpaul 116184059Swpaul/* Host coalescing status register */ 116284059Swpaul#define BGE_HCCSTAT_ERROR 0x00000004 116384059Swpaul 116484059Swpaul/* Flow attention register */ 116584059Swpaul#define BGE_FLOWATTN_MB_LOWAT 0x00000040 116684059Swpaul#define BGE_FLOWATTN_MEMARB 0x00000080 116784059Swpaul#define BGE_FLOWATTN_HOSTCOAL 0x00008000 116884059Swpaul#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 116984059Swpaul#define BGE_FLOWATTN_RCB_INVAL 0x00020000 117084059Swpaul#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 117184059Swpaul#define BGE_FLOWATTN_RDBDI 0x00080000 117284059Swpaul#define BGE_FLOWATTN_RXLS 0x00100000 117384059Swpaul#define BGE_FLOWATTN_RXLP 0x00200000 117484059Swpaul#define BGE_FLOWATTN_RBDC 0x00400000 117584059Swpaul#define BGE_FLOWATTN_RBDI 0x00800000 117684059Swpaul#define BGE_FLOWATTN_SDC 0x08000000 117784059Swpaul#define BGE_FLOWATTN_SDI 0x10000000 117884059Swpaul#define BGE_FLOWATTN_SRS 0x20000000 117984059Swpaul#define BGE_FLOWATTN_SBDC 0x40000000 118084059Swpaul#define BGE_FLOWATTN_SBDI 0x80000000 118184059Swpaul 118284059Swpaul/* 118384059Swpaul * Memory arbiter registers 118484059Swpaul */ 118584059Swpaul#define BGE_MARB_MODE 0x4000 118684059Swpaul#define BGE_MARB_STATUS 0x4004 118784059Swpaul#define BGE_MARB_TRAPADDR_HI 0x4008 118884059Swpaul#define BGE_MARB_TRAPADDR_LO 0x400C 118984059Swpaul 119084059Swpaul/* Memory arbiter mode register */ 119184059Swpaul#define BGE_MARBMODE_RESET 0x00000001 119284059Swpaul#define BGE_MARBMODE_ENABLE 0x00000002 119384059Swpaul#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 119484059Swpaul#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 119584059Swpaul#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 119684059Swpaul#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 119784059Swpaul#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 119884059Swpaul#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 119984059Swpaul#define BGE_MARBMODE_PCI_TRAP 0x00000100 120084059Swpaul#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 120184059Swpaul#define BGE_MARBMODE_RXQ_TRAP 0x00000400 120284059Swpaul#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 120384059Swpaul#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 120484059Swpaul#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 120584059Swpaul#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 120684059Swpaul#define BGE_MARBMODE_MBUF_TRAP 0x00008000 120784059Swpaul#define BGE_MARBMODE_TXDI_TRAP 0x00010000 120884059Swpaul#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 120984059Swpaul#define BGE_MARBMODE_TXBD_TRAP 0x00040000 121084059Swpaul#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 121184059Swpaul#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 121284059Swpaul#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 121384059Swpaul#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 121484059Swpaul#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 121584059Swpaul#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 121684059Swpaul#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 121784059Swpaul 121884059Swpaul/* Memory arbiter status register */ 121984059Swpaul#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 122084059Swpaul#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 122184059Swpaul#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 122284059Swpaul#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 122384059Swpaul#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 122484059Swpaul#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 122584059Swpaul#define BGE_MARBSTAT_PCI_TRAP 0x00000100 122684059Swpaul#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 122784059Swpaul#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 122884059Swpaul#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 122984059Swpaul#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 123084059Swpaul#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 123184059Swpaul#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 123284059Swpaul#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 123384059Swpaul#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 123484059Swpaul#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 123584059Swpaul#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 123684059Swpaul#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 123784059Swpaul#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 123884059Swpaul#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 123984059Swpaul#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 124084059Swpaul#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 124184059Swpaul#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 124284059Swpaul#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 124384059Swpaul 124484059Swpaul/* 124584059Swpaul * Buffer manager control registers 124684059Swpaul */ 124784059Swpaul#define BGE_BMAN_MODE 0x4400 124884059Swpaul#define BGE_BMAN_STATUS 0x4404 124984059Swpaul#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 125084059Swpaul#define BGE_BMAN_MBUFPOOL_LEN 0x440C 125184059Swpaul#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 125284059Swpaul#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 125384059Swpaul#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 125484059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 125584059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 125684059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 125784059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 125884059Swpaul#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 125984059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 126084059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 126184059Swpaul#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 126284059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 126384059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 126484059Swpaul#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 126584059Swpaul#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 126684059Swpaul#define BGE_BMAN_HWDIAG_1 0x444C 126784059Swpaul#define BGE_BMAN_HWDIAG_2 0x4450 126884059Swpaul#define BGE_BMAN_HWDIAG_3 0x4454 126984059Swpaul 127084059Swpaul/* Buffer manager mode register */ 127184059Swpaul#define BGE_BMANMODE_RESET 0x00000001 127284059Swpaul#define BGE_BMANMODE_ENABLE 0x00000002 127384059Swpaul#define BGE_BMANMODE_ATTN 0x00000004 127484059Swpaul#define BGE_BMANMODE_TESTMODE 0x00000008 127584059Swpaul#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 127684059Swpaul 127784059Swpaul/* Buffer manager status register */ 127884059Swpaul#define BGE_BMANSTAT_ERRO 0x00000004 127984059Swpaul#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 128084059Swpaul 128184059Swpaul 128284059Swpaul/* 128384059Swpaul * Read DMA Control registers 128484059Swpaul */ 128584059Swpaul#define BGE_RDMA_MODE 0x4800 128684059Swpaul#define BGE_RDMA_STATUS 0x4804 128784059Swpaul 128884059Swpaul/* Read DMA mode register */ 128984059Swpaul#define BGE_RDMAMODE_RESET 0x00000001 129084059Swpaul#define BGE_RDMAMODE_ENABLE 0x00000002 129184059Swpaul#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 129284059Swpaul#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 129384059Swpaul#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 129484059Swpaul#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 129584059Swpaul#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 129684059Swpaul#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 129784059Swpaul#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 129884059Swpaul#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 129984059Swpaul#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 130084059Swpaul 130184059Swpaul/* Read DMA status register */ 130284059Swpaul#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 130384059Swpaul#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 130484059Swpaul#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 130584059Swpaul#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 130684059Swpaul#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 130784059Swpaul#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 130884059Swpaul#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 130984059Swpaul#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 131084059Swpaul 131184059Swpaul/* 131284059Swpaul * Write DMA control registers 131384059Swpaul */ 131484059Swpaul#define BGE_WDMA_MODE 0x4C00 131584059Swpaul#define BGE_WDMA_STATUS 0x4C04 131684059Swpaul 131784059Swpaul/* Write DMA mode register */ 131884059Swpaul#define BGE_WDMAMODE_RESET 0x00000001 131984059Swpaul#define BGE_WDMAMODE_ENABLE 0x00000002 132084059Swpaul#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 132184059Swpaul#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 132284059Swpaul#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 132384059Swpaul#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 132484059Swpaul#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 132584059Swpaul#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 132684059Swpaul#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 132784059Swpaul#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 132884059Swpaul#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 132984059Swpaul 133084059Swpaul/* Write DMA status register */ 133184059Swpaul#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 133284059Swpaul#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 133384059Swpaul#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 133484059Swpaul#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 133584059Swpaul#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 133684059Swpaul#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 133784059Swpaul#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 133884059Swpaul#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 133984059Swpaul 134084059Swpaul 134184059Swpaul/* 134284059Swpaul * RX CPU registers 134384059Swpaul */ 134484059Swpaul#define BGE_RXCPU_MODE 0x5000 134584059Swpaul#define BGE_RXCPU_STATUS 0x5004 134684059Swpaul#define BGE_RXCPU_PC 0x501C 134784059Swpaul 134884059Swpaul/* RX CPU mode register */ 134984059Swpaul#define BGE_RXCPUMODE_RESET 0x00000001 135084059Swpaul#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 135184059Swpaul#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 135284059Swpaul#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 135384059Swpaul#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 135484059Swpaul#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 135584059Swpaul#define BGE_RXCPUMODE_ROMFAIL 0x00000040 135684059Swpaul#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 135784059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 135884059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 135984059Swpaul#define BGE_RXCPUMODE_HALTCPU 0x00000400 136084059Swpaul#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 136184059Swpaul#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 136284059Swpaul#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 136384059Swpaul 136484059Swpaul/* RX CPU status register */ 136584059Swpaul#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 136684059Swpaul#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 136784059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 136884059Swpaul#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 136984059Swpaul#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 137084059Swpaul#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 137184059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 137284059Swpaul#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 137384059Swpaul#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 137484059Swpaul#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 137584059Swpaul#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 137684059Swpaul#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 137784059Swpaul#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 137884059Swpaul#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 137984059Swpaul#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 138084059Swpaul#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 138184059Swpaul#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 138284059Swpaul 138384059Swpaul 138484059Swpaul/* 138584059Swpaul * TX CPU registers 138684059Swpaul */ 138784059Swpaul#define BGE_TXCPU_MODE 0x5400 138884059Swpaul#define BGE_TXCPU_STATUS 0x5404 138984059Swpaul#define BGE_TXCPU_PC 0x541C 139084059Swpaul 139184059Swpaul/* TX CPU mode register */ 139284059Swpaul#define BGE_TXCPUMODE_RESET 0x00000001 139384059Swpaul#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 139484059Swpaul#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 139584059Swpaul#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 139684059Swpaul#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 139784059Swpaul#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 139884059Swpaul#define BGE_TXCPUMODE_ROMFAIL 0x00000040 139984059Swpaul#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 140084059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 140184059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 140284059Swpaul#define BGE_TXCPUMODE_HALTCPU 0x00000400 140384059Swpaul#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 140484059Swpaul#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 140584059Swpaul 140684059Swpaul/* TX CPU status register */ 140784059Swpaul#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 140884059Swpaul#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 140984059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 141084059Swpaul#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 141184059Swpaul#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 141284059Swpaul#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 141384059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 141484059Swpaul#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 141584059Swpaul#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 141684059Swpaul#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 141784059Swpaul#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 141884059Swpaul#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 141984059Swpaul#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 142084059Swpaul#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 142184059Swpaul#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 142284059Swpaul#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 142384059Swpaul#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 142484059Swpaul 142584059Swpaul 142684059Swpaul/* 142784059Swpaul * Low priority mailbox registers 142884059Swpaul */ 142984059Swpaul#define BGE_LPMBX_IRQ0_HI 0x5800 143084059Swpaul#define BGE_LPMBX_IRQ0_LO 0x5804 143184059Swpaul#define BGE_LPMBX_IRQ1_HI 0x5808 143284059Swpaul#define BGE_LPMBX_IRQ1_LO 0x580C 143384059Swpaul#define BGE_LPMBX_IRQ2_HI 0x5810 143484059Swpaul#define BGE_LPMBX_IRQ2_LO 0x5814 143584059Swpaul#define BGE_LPMBX_IRQ3_HI 0x5818 143684059Swpaul#define BGE_LPMBX_IRQ3_LO 0x581C 143784059Swpaul#define BGE_LPMBX_GEN0_HI 0x5820 143884059Swpaul#define BGE_LPMBX_GEN0_LO 0x5824 143984059Swpaul#define BGE_LPMBX_GEN1_HI 0x5828 144084059Swpaul#define BGE_LPMBX_GEN1_LO 0x582C 144184059Swpaul#define BGE_LPMBX_GEN2_HI 0x5830 144284059Swpaul#define BGE_LPMBX_GEN2_LO 0x5834 144384059Swpaul#define BGE_LPMBX_GEN3_HI 0x5828 144484059Swpaul#define BGE_LPMBX_GEN3_LO 0x582C 144584059Swpaul#define BGE_LPMBX_GEN4_HI 0x5840 144684059Swpaul#define BGE_LPMBX_GEN4_LO 0x5844 144784059Swpaul#define BGE_LPMBX_GEN5_HI 0x5848 144884059Swpaul#define BGE_LPMBX_GEN5_LO 0x584C 144984059Swpaul#define BGE_LPMBX_GEN6_HI 0x5850 145084059Swpaul#define BGE_LPMBX_GEN6_LO 0x5854 145184059Swpaul#define BGE_LPMBX_GEN7_HI 0x5858 145284059Swpaul#define BGE_LPMBX_GEN7_LO 0x585C 145384059Swpaul#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 145484059Swpaul#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 145584059Swpaul#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 145684059Swpaul#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 145784059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 145884059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 145984059Swpaul#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 146084059Swpaul#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 146184059Swpaul#define BGE_LPMBX_RX_CONS0_HI 0x5880 146284059Swpaul#define BGE_LPMBX_RX_CONS0_LO 0x5884 146384059Swpaul#define BGE_LPMBX_RX_CONS1_HI 0x5888 146484059Swpaul#define BGE_LPMBX_RX_CONS1_LO 0x588C 146584059Swpaul#define BGE_LPMBX_RX_CONS2_HI 0x5890 146684059Swpaul#define BGE_LPMBX_RX_CONS2_LO 0x5894 146784059Swpaul#define BGE_LPMBX_RX_CONS3_HI 0x5898 146884059Swpaul#define BGE_LPMBX_RX_CONS3_LO 0x589C 146984059Swpaul#define BGE_LPMBX_RX_CONS4_HI 0x58A0 147084059Swpaul#define BGE_LPMBX_RX_CONS4_LO 0x58A4 147184059Swpaul#define BGE_LPMBX_RX_CONS5_HI 0x58A8 147284059Swpaul#define BGE_LPMBX_RX_CONS5_LO 0x58AC 147384059Swpaul#define BGE_LPMBX_RX_CONS6_HI 0x58B0 147484059Swpaul#define BGE_LPMBX_RX_CONS6_LO 0x58B4 147584059Swpaul#define BGE_LPMBX_RX_CONS7_HI 0x58B8 147684059Swpaul#define BGE_LPMBX_RX_CONS7_LO 0x58BC 147784059Swpaul#define BGE_LPMBX_RX_CONS8_HI 0x58C0 147884059Swpaul#define BGE_LPMBX_RX_CONS8_LO 0x58C4 147984059Swpaul#define BGE_LPMBX_RX_CONS9_HI 0x58C8 148084059Swpaul#define BGE_LPMBX_RX_CONS9_LO 0x58CC 148184059Swpaul#define BGE_LPMBX_RX_CONS10_HI 0x58D0 148284059Swpaul#define BGE_LPMBX_RX_CONS10_LO 0x58D4 148384059Swpaul#define BGE_LPMBX_RX_CONS11_HI 0x58D8 148484059Swpaul#define BGE_LPMBX_RX_CONS11_LO 0x58DC 148584059Swpaul#define BGE_LPMBX_RX_CONS12_HI 0x58E0 148684059Swpaul#define BGE_LPMBX_RX_CONS12_LO 0x58E4 148784059Swpaul#define BGE_LPMBX_RX_CONS13_HI 0x58E8 148884059Swpaul#define BGE_LPMBX_RX_CONS13_LO 0x58EC 148984059Swpaul#define BGE_LPMBX_RX_CONS14_HI 0x58F0 149084059Swpaul#define BGE_LPMBX_RX_CONS14_LO 0x58F4 149184059Swpaul#define BGE_LPMBX_RX_CONS15_HI 0x58F8 149284059Swpaul#define BGE_LPMBX_RX_CONS15_LO 0x58FC 149384059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 149484059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 149584059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 149684059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 149784059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 149884059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 149984059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 150084059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 150184059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 150284059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 150384059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 150484059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 150584059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 150684059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 150784059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 150884059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 150984059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 151084059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 151184059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 151284059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 151384059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 151484059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 151584059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 151684059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 151784059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 151884059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 151984059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 152084059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 152184059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 152284059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 152384059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 152484059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 152584059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 152684059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 152784059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 152884059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 152984059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 153084059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 153184059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 153284059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 153384059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 153484059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 153584059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 153684059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 153784059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 153884059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 153984059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 154084059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 154184059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 154284059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 154384059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 154484059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 154584059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 154684059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 154784059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 154884059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 154984059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 155084059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 155184059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 155284059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 155384059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 155484059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 155584059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 155684059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 155784059Swpaul 155884059Swpaul/* 155984059Swpaul * Flow throw Queue reset register 156084059Swpaul */ 156184059Swpaul#define BGE_FTQ_RESET 0x5C00 156284059Swpaul 156384059Swpaul#define BGE_FTQRESET_DMAREAD 0x00000002 156484059Swpaul#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 156584059Swpaul#define BGE_FTQRESET_DMADONE 0x00000010 156684059Swpaul#define BGE_FTQRESET_SBDC 0x00000020 156784059Swpaul#define BGE_FTQRESET_SDI 0x00000040 156884059Swpaul#define BGE_FTQRESET_WDMA 0x00000080 156984059Swpaul#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 157084059Swpaul#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 157184059Swpaul#define BGE_FTQRESET_SDC 0x00000400 157284059Swpaul#define BGE_FTQRESET_HCC 0x00000800 157384059Swpaul#define BGE_FTQRESET_TXFIFO 0x00001000 157484059Swpaul#define BGE_FTQRESET_MBC 0x00002000 157584059Swpaul#define BGE_FTQRESET_RBDC 0x00004000 157684059Swpaul#define BGE_FTQRESET_RXLP 0x00008000 157784059Swpaul#define BGE_FTQRESET_RDBDI 0x00010000 157884059Swpaul#define BGE_FTQRESET_RDC 0x00020000 157984059Swpaul#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 158084059Swpaul 158184059Swpaul/* 158284059Swpaul * Message Signaled Interrupt registers 158384059Swpaul */ 158484059Swpaul#define BGE_MSI_MODE 0x6000 158584059Swpaul#define BGE_MSI_STATUS 0x6004 158684059Swpaul#define BGE_MSI_FIFOACCESS 0x6008 158784059Swpaul 158884059Swpaul/* MSI mode register */ 158984059Swpaul#define BGE_MSIMODE_RESET 0x00000001 159084059Swpaul#define BGE_MSIMODE_ENABLE 0x00000002 159184059Swpaul#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 159284059Swpaul#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 159384059Swpaul#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 159484059Swpaul#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 159584059Swpaul#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 159684059Swpaul 159784059Swpaul/* MSI status register */ 159884059Swpaul#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 159984059Swpaul#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 160084059Swpaul#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 160184059Swpaul#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 160284059Swpaul#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 160384059Swpaul 160484059Swpaul 160584059Swpaul/* 160684059Swpaul * DMA Completion registers 160784059Swpaul */ 160884059Swpaul#define BGE_DMAC_MODE 0x6400 160984059Swpaul 161084059Swpaul/* DMA Completion mode register */ 161184059Swpaul#define BGE_DMACMODE_RESET 0x00000001 161284059Swpaul#define BGE_DMACMODE_ENABLE 0x00000002 161384059Swpaul 161484059Swpaul 161584059Swpaul/* 161684059Swpaul * General control registers. 161784059Swpaul */ 161884059Swpaul#define BGE_MODE_CTL 0x6800 161984059Swpaul#define BGE_MISC_CFG 0x6804 162084059Swpaul#define BGE_MISC_LOCAL_CTL 0x6808 162184059Swpaul#define BGE_EE_ADDR 0x6838 162284059Swpaul#define BGE_EE_DATA 0x683C 162384059Swpaul#define BGE_EE_CTL 0x6840 162484059Swpaul#define BGE_MDI_CTL 0x6844 162584059Swpaul#define BGE_EE_DELAY 0x6848 162684059Swpaul 162784059Swpaul/* Mode control register */ 162884059Swpaul#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 162984059Swpaul#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 163084059Swpaul#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 163184059Swpaul#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 163284059Swpaul#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 163384059Swpaul#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 163484059Swpaul#define BGE_MODECTL_NO_RX_CRC 0x00000400 163584059Swpaul#define BGE_MODECTL_RX_BADFRAMES 0x00000800 163684059Swpaul#define BGE_MODECTL_NO_TX_INTR 0x00002000 163784059Swpaul#define BGE_MODECTL_NO_RX_INTR 0x00004000 163884059Swpaul#define BGE_MODECTL_FORCE_PCI32 0x00008000 163984059Swpaul#define BGE_MODECTL_STACKUP 0x00010000 164084059Swpaul#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 164184059Swpaul#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 164284059Swpaul#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 164384059Swpaul#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 164484059Swpaul#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 164584059Swpaul#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 164684059Swpaul#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 164784059Swpaul#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 164884059Swpaul#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 164984059Swpaul#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 165084059Swpaul 165184059Swpaul/* Misc. config register */ 165284059Swpaul#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 165384059Swpaul#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 165484059Swpaul 165584059Swpaul#define BGE_32BITTIME_66MHZ (0x41 << 1) 165684059Swpaul 165784059Swpaul/* Misc. Local Control */ 165884059Swpaul#define BGE_MLC_INTR_STATE 0x00000001 165984059Swpaul#define BGE_MLC_INTR_CLR 0x00000002 166084059Swpaul#define BGE_MLC_INTR_SET 0x00000004 166184059Swpaul#define BGE_MLC_INTR_ONATTN 0x00000008 166284059Swpaul#define BGE_MLC_MISCIO_IN0 0x00000100 166384059Swpaul#define BGE_MLC_MISCIO_IN1 0x00000200 166484059Swpaul#define BGE_MLC_MISCIO_IN2 0x00000400 166584059Swpaul#define BGE_MLC_MISCIO_OUTEN0 0x00000800 166684059Swpaul#define BGE_MLC_MISCIO_OUTEN1 0x00001000 166784059Swpaul#define BGE_MLC_MISCIO_OUTEN2 0x00002000 166884059Swpaul#define BGE_MLC_MISCIO_OUT0 0x00004000 166984059Swpaul#define BGE_MLC_MISCIO_OUT1 0x00008000 167084059Swpaul#define BGE_MLC_MISCIO_OUT2 0x00010000 167184059Swpaul#define BGE_MLC_EXTRAM_ENB 0x00020000 167284059Swpaul#define BGE_MLC_SRAM_SIZE 0x001C0000 167384059Swpaul#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 167484059Swpaul#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 167584059Swpaul#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 167684059Swpaul#define BGE_MLC_AUTO_EEPROM 0x01000000 167784059Swpaul 167884059Swpaul#define BGE_SSRAMSIZE_256KB 0x00000000 167984059Swpaul#define BGE_SSRAMSIZE_512KB 0x00040000 168084059Swpaul#define BGE_SSRAMSIZE_1MB 0x00080000 168184059Swpaul#define BGE_SSRAMSIZE_2MB 0x000C0000 168284059Swpaul#define BGE_SSRAMSIZE_4MB 0x00100000 168384059Swpaul#define BGE_SSRAMSIZE_8MB 0x00140000 168484059Swpaul#define BGE_SSRAMSIZE_16M 0x00180000 168584059Swpaul 168684059Swpaul/* EEPROM address register */ 168784059Swpaul#define BGE_EEADDR_ADDRESS 0x0000FFFC 168884059Swpaul#define BGE_EEADDR_HALFCLK 0x01FF0000 168984059Swpaul#define BGE_EEADDR_START 0x02000000 169084059Swpaul#define BGE_EEADDR_DEVID 0x1C000000 169184059Swpaul#define BGE_EEADDR_RESET 0x20000000 169284059Swpaul#define BGE_EEADDR_DONE 0x40000000 169384059Swpaul#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 169484059Swpaul 169584059Swpaul#define BGE_EEDEVID(x) ((x & 7) << 26) 169684059Swpaul#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 169784059Swpaul#define BGE_HALFCLK_384SCL 0x60 169884059Swpaul#define BGE_EE_READCMD \ 169984059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 170084059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 170184059Swpaul#define BGE_EE_WRCMD \ 170284059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 170384059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 170484059Swpaul 170584059Swpaul/* EEPROM Control register */ 170684059Swpaul#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 170784059Swpaul#define BGE_EECTL_CLKOUT 0x00000002 170884059Swpaul#define BGE_EECTL_CLKIN 0x00000004 170984059Swpaul#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 171084059Swpaul#define BGE_EECTL_DATAOUT 0x00000010 171184059Swpaul#define BGE_EECTL_DATAIN 0x00000020 171284059Swpaul 171384059Swpaul/* MDI (MII/GMII) access register */ 171484059Swpaul#define BGE_MDI_DATA 0x00000001 171584059Swpaul#define BGE_MDI_DIR 0x00000002 171684059Swpaul#define BGE_MDI_SEL 0x00000004 171784059Swpaul#define BGE_MDI_CLK 0x00000008 171884059Swpaul 171984059Swpaul#define BGE_MEMWIN_START 0x00008000 172084059Swpaul#define BGE_MEMWIN_END 0x0000FFFF 172184059Swpaul 172284059Swpaul 172384059Swpaul#define BGE_MEMWIN_READ(sc, x, val) \ 172484059Swpaul do { \ 172584059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 172684059Swpaul (0xFFFF0000 & x), 4); \ 172784059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 172884059Swpaul } while(0) 172984059Swpaul 173084059Swpaul#define BGE_MEMWIN_WRITE(sc, x, val) \ 173184059Swpaul do { \ 173284059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 173384059Swpaul (0xFFFF0000 & x), 4); \ 173484059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 173584059Swpaul } while(0) 173684059Swpaul 173784059Swpaul/* 173884059Swpaul * This magic number is used to prevent PXE restart when we 173984059Swpaul * issue a software reset. We write this magic number to the 174084059Swpaul * firmware mailbox at 0xB50 in order to prevent the PXE boot 174184059Swpaul * code from running. 174284059Swpaul */ 174384059Swpaul#define BGE_MAGIC_NUMBER 0x4B657654 174484059Swpaul 174584059Swpaultypedef struct { 174684059Swpaul u_int32_t bge_addr_hi; 174784059Swpaul u_int32_t bge_addr_lo; 174884059Swpaul} bge_hostaddr; 1749118026Swpaul 1750115200Sps#define BGE_HOSTADDR(x, y) \ 1751115200Sps do { \ 1752115200Sps (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1753115200Sps (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1754115200Sps } while(0) 175584059Swpaul 1756118026Swpaul#define BGE_ADDR_LO(y) \ 1757118026Swpaul ((u_int64_t) (y) & 0xFFFFFFFF) 1758118026Swpaul#define BGE_ADDR_HI(y) \ 1759118026Swpaul ((u_int64_t) (y) >> 32) 1760118026Swpaul 176184059Swpaul/* Ring control block structure */ 176284059Swpaulstruct bge_rcb { 176384059Swpaul bge_hostaddr bge_hostaddr; 1764108847Sjdp u_int32_t bge_maxlen_flags; 176584059Swpaul u_int32_t bge_nicaddr; 176684059Swpaul}; 1767108847Sjdp#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 176884059Swpaul 176984059Swpaul#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 177084059Swpaul#define BGE_RCB_FLAG_RING_DISABLED 0x0002 177184059Swpaul 177284059Swpaulstruct bge_tx_bd { 177384059Swpaul bge_hostaddr bge_addr; 177484059Swpaul u_int16_t bge_flags; 177584059Swpaul u_int16_t bge_len; 177684059Swpaul u_int16_t bge_vlan_tag; 177784059Swpaul u_int16_t bge_rsvd; 177884059Swpaul}; 177984059Swpaul 178084059Swpaul#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 178184059Swpaul#define BGE_TXBDFLAG_IP_CSUM 0x0002 178284059Swpaul#define BGE_TXBDFLAG_END 0x0004 178384059Swpaul#define BGE_TXBDFLAG_IP_FRAG 0x0008 178484059Swpaul#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 178584059Swpaul#define BGE_TXBDFLAG_VLAN_TAG 0x0040 178684059Swpaul#define BGE_TXBDFLAG_COAL_NOW 0x0080 178784059Swpaul#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 178884059Swpaul#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 178984059Swpaul#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 179084059Swpaul#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 179184059Swpaul#define BGE_TXBDFLAG_NO_CRC 0x8000 179284059Swpaul 179384059Swpaul#define BGE_NIC_TXRING_ADDR(ringno, size) \ 179484059Swpaul BGE_SEND_RING_1_TO_4 + \ 179584059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 179684059Swpaul 179784059Swpaulstruct bge_rx_bd { 179884059Swpaul bge_hostaddr bge_addr; 179984059Swpaul u_int16_t bge_len; 180084059Swpaul u_int16_t bge_idx; 180184059Swpaul u_int16_t bge_flags; 180284059Swpaul u_int16_t bge_type; 180384059Swpaul u_int16_t bge_tcp_udp_csum; 180484059Swpaul u_int16_t bge_ip_csum; 180584059Swpaul u_int16_t bge_vlan_tag; 180684059Swpaul u_int16_t bge_error_flag; 180784059Swpaul u_int32_t bge_rsvd; 180884059Swpaul u_int32_t bge_opaque; 180984059Swpaul}; 181084059Swpaul 181184059Swpaul#define BGE_RXBDFLAG_END 0x0004 181284059Swpaul#define BGE_RXBDFLAG_JUMBO_RING 0x0020 181384059Swpaul#define BGE_RXBDFLAG_VLAN_TAG 0x0040 181484059Swpaul#define BGE_RXBDFLAG_ERROR 0x0400 181584059Swpaul#define BGE_RXBDFLAG_MINI_RING 0x0800 181684059Swpaul#define BGE_RXBDFLAG_IP_CSUM 0x1000 181784059Swpaul#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 181884059Swpaul#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 181984059Swpaul 182084059Swpaul#define BGE_RXERRFLAG_BAD_CRC 0x0001 182184059Swpaul#define BGE_RXERRFLAG_COLL_DETECT 0x0002 182284059Swpaul#define BGE_RXERRFLAG_LINK_LOST 0x0004 182384059Swpaul#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 182484059Swpaul#define BGE_RXERRFLAG_MAC_ABORT 0x0010 182584059Swpaul#define BGE_RXERRFLAG_RUNT 0x0020 182684059Swpaul#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 182784059Swpaul#define BGE_RXERRFLAG_GIANT 0x0080 182884059Swpaul 182984059Swpaulstruct bge_sts_idx { 183084059Swpaul u_int16_t bge_rx_prod_idx; 183184059Swpaul u_int16_t bge_tx_cons_idx; 183284059Swpaul}; 183384059Swpaul 183484059Swpaulstruct bge_status_block { 183584059Swpaul u_int32_t bge_status; 183684059Swpaul u_int32_t bge_rsvd0; 183784059Swpaul u_int16_t bge_rx_jumbo_cons_idx; 183884059Swpaul u_int16_t bge_rx_std_cons_idx; 183984059Swpaul u_int16_t bge_rx_mini_cons_idx; 184084059Swpaul u_int16_t bge_rsvd1; 184184059Swpaul struct bge_sts_idx bge_idx[16]; 184284059Swpaul}; 184384059Swpaul 184484059Swpaul#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 184584059Swpaul#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 184684059Swpaul 184784059Swpaul#define BGE_STATFLAG_UPDATED 0x00000001 184884059Swpaul#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 184984059Swpaul#define BGE_STATFLAG_ERROR 0x00000004 185084059Swpaul 185184059Swpaul 185284059Swpaul/* 185384059Swpaul * Broadcom Vendor ID 185484059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 185584059Swpaul * even though they're now manufactured by Broadcom) 185684059Swpaul */ 185784059Swpaul#define BCOM_VENDORID 0x14E4 185884059Swpaul#define BCOM_DEVICEID_BCM5700 0x1644 185984059Swpaul#define BCOM_DEVICEID_BCM5701 0x1645 1860117659Swpaul#define BCOM_DEVICEID_BCM5702 0x16A6 1861117659Swpaul#define BCOM_DEVICEID_BCM5702X 0x16C6 1862117659Swpaul#define BCOM_DEVICEID_BCM5703 0x16A7 1863117659Swpaul#define BCOM_DEVICEID_BCM5703X 0x16C7 1864114547Sps#define BCOM_DEVICEID_BCM5704C 0x1648 1865114547Sps#define BCOM_DEVICEID_BCM5704S 0x16A8 1866117659Swpaul#define BCOM_DEVICEID_BCM5705 0x1653 1867129640Sps#define BCOM_DEVICEID_BCM5705K 0x1654 1868117659Swpaul#define BCOM_DEVICEID_BCM5705M 0x165D 1869117659Swpaul#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1870135772Sps#define BCOM_DEVICEID_BCM5750 0x1676 1871135772Sps#define BCOM_DEVICEID_BCM5750M 0x167C 1872135772Sps#define BCOM_DEVICEID_BCM5751 0x1677 1873117659Swpaul#define BCOM_DEVICEID_BCM5782 0x1696 1874121810Swpaul#define BCOM_DEVICEID_BCM5788 0x169C 1875118814Swpaul#define BCOM_DEVICEID_BCM5901 0x170D 1876118814Swpaul#define BCOM_DEVICEID_BCM5901A2 0x170E 187784059Swpaul 187884059Swpaul/* 187984059Swpaul * Alteon AceNIC PCI vendor/device ID. 188084059Swpaul */ 188184059Swpaul#define ALT_VENDORID 0x12AE 188284059Swpaul#define ALT_DEVICEID_ACENIC 0x0001 188384059Swpaul#define ALT_DEVICEID_ACENIC_COPPER 0x0002 188484059Swpaul#define ALT_DEVICEID_BCM5700 0x0003 188584059Swpaul#define ALT_DEVICEID_BCM5701 0x0004 188684059Swpaul 188784059Swpaul/* 188884059Swpaul * 3Com 3c985 PCI vendor/device ID. 188984059Swpaul */ 189084059Swpaul#define TC_VENDORID 0x10B7 189184059Swpaul#define TC_DEVICEID_3C985 0x0001 189284059Swpaul#define TC_DEVICEID_3C996 0x0003 189384059Swpaul 189484059Swpaul/* 189584059Swpaul * SysKonnect PCI vendor ID 189684059Swpaul */ 189784059Swpaul#define SK_VENDORID 0x1148 189884059Swpaul#define SK_DEVICEID_ALTIMA 0x4400 189984059Swpaul#define SK_SUBSYSID_9D21 0x4421 190084059Swpaul#define SK_SUBSYSID_9D41 0x4441 190184059Swpaul 190284059Swpaul/* 190389835Sjdp * Altima PCI vendor/device ID. 190489835Sjdp */ 190589835Sjdp#define ALTIMA_VENDORID 0x173b 190689835Sjdp#define ALTIMA_DEVICE_AC1000 0x03e8 1907124257Swpaul#define ALTIMA_DEVICE_AC1002 0x03e9 1908100695Sjdp#define ALTIMA_DEVICE_AC9100 0x03ea 190989835Sjdp 191089835Sjdp/* 1911119157Sambrisko * Dell PCI vendor ID 1912119157Sambrisko */ 1913119157Sambrisko 1914119157Sambrisko#define DELL_VENDORID 0x1028 1915119157Sambrisko 1916119157Sambrisko/* 191784059Swpaul * Offset of MAC address inside EEPROM. 191884059Swpaul */ 191984059Swpaul#define BGE_EE_MAC_OFFSET 0x7C 192084059Swpaul#define BGE_EE_HWCFG_OFFSET 0xC8 192184059Swpaul 192293751Swpaul#define BGE_HWCFG_VOLTAGE 0x00000003 192393751Swpaul#define BGE_HWCFG_PHYLED_MODE 0x0000000C 192493751Swpaul#define BGE_HWCFG_MEDIA 0x00000030 192593751Swpaul 192693751Swpaul#define BGE_VOLTAGE_1POINT3 0x00000000 192793751Swpaul#define BGE_VOLTAGE_1POINT8 0x00000001 192893751Swpaul 192993751Swpaul#define BGE_PHYLEDMODE_UNSPEC 0x00000000 193093751Swpaul#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 193193751Swpaul#define BGE_PHYLEDMODE_SINGLELED 0x00000008 193293751Swpaul 193393751Swpaul#define BGE_MEDIA_UNSPEC 0x00000000 193493751Swpaul#define BGE_MEDIA_COPPER 0x00000010 193593751Swpaul#define BGE_MEDIA_FIBER 0x00000020 193693751Swpaul 193784059Swpaul#define BGE_PCI_READ_CMD 0x06000000 193884059Swpaul#define BGE_PCI_WRITE_CMD 0x70000000 193984059Swpaul 194084059Swpaul#define BGE_TICKS_PER_SEC 1000000 194184059Swpaul 194284059Swpaul/* 194384059Swpaul * Ring size constants. 194484059Swpaul */ 194584059Swpaul#define BGE_EVENT_RING_CNT 256 194684059Swpaul#define BGE_CMD_RING_CNT 64 194784059Swpaul#define BGE_STD_RX_RING_CNT 512 194884059Swpaul#define BGE_JUMBO_RX_RING_CNT 256 194984059Swpaul#define BGE_MINI_RX_RING_CNT 1024 195084059Swpaul#define BGE_RETURN_RING_CNT 1024 195184059Swpaul 1952117659Swpaul/* 5705 has smaller return ring size */ 1953117659Swpaul 1954117659Swpaul#define BGE_RETURN_RING_CNT_5705 512 1955117659Swpaul 195684059Swpaul/* 195784059Swpaul * Possible TX ring sizes. 195884059Swpaul */ 195984059Swpaul#define BGE_TX_RING_CNT_128 128 196084059Swpaul#define BGE_TX_RING_BASE_128 0x3800 196184059Swpaul 196284059Swpaul#define BGE_TX_RING_CNT_256 256 196384059Swpaul#define BGE_TX_RING_BASE_256 0x3000 196484059Swpaul 196584059Swpaul#define BGE_TX_RING_CNT_512 512 196684059Swpaul#define BGE_TX_RING_BASE_512 0x2000 196784059Swpaul 196884059Swpaul#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 196984059Swpaul#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 197084059Swpaul 197184059Swpaul/* 197284059Swpaul * Tigon III statistics counters. 197384059Swpaul */ 1974117659Swpaul/* Statistics maintained MAC Receive block. */ 1975117659Swpaulstruct bge_rx_mac_stats { 197684059Swpaul bge_hostaddr ifHCInOctets; 197784059Swpaul bge_hostaddr Reserved1; 197884059Swpaul bge_hostaddr etherStatsFragments; 197984059Swpaul bge_hostaddr ifHCInUcastPkts; 198084059Swpaul bge_hostaddr ifHCInMulticastPkts; 198184059Swpaul bge_hostaddr ifHCInBroadcastPkts; 198284059Swpaul bge_hostaddr dot3StatsFCSErrors; 198384059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 198484059Swpaul bge_hostaddr xonPauseFramesReceived; 198584059Swpaul bge_hostaddr xoffPauseFramesReceived; 198684059Swpaul bge_hostaddr macControlFramesReceived; 198784059Swpaul bge_hostaddr xoffStateEntered; 198884059Swpaul bge_hostaddr dot3StatsFramesTooLong; 198984059Swpaul bge_hostaddr etherStatsJabbers; 199084059Swpaul bge_hostaddr etherStatsUndersizePkts; 199184059Swpaul bge_hostaddr inRangeLengthError; 199284059Swpaul bge_hostaddr outRangeLengthError; 199384059Swpaul bge_hostaddr etherStatsPkts64Octets; 199484059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 199584059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 199684059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 199784059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 199884059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 199984059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 200084059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 200184059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 200284059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2003117659Swpaul}; 200484059Swpaul 200584059Swpaul 2006117659Swpaul/* Statistics maintained MAC Transmit block. */ 2007117659Swpaulstruct bge_tx_mac_stats { 200884059Swpaul bge_hostaddr ifHCOutOctets; 200984059Swpaul bge_hostaddr Reserved2; 201084059Swpaul bge_hostaddr etherStatsCollisions; 201184059Swpaul bge_hostaddr outXonSent; 201284059Swpaul bge_hostaddr outXoffSent; 201384059Swpaul bge_hostaddr flowControlDone; 201484059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 201584059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 201684059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 201784059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 201884059Swpaul bge_hostaddr Reserved3; 201984059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 202084059Swpaul bge_hostaddr dot3StatsLateCollisions; 202184059Swpaul bge_hostaddr dot3Collided2Times; 202284059Swpaul bge_hostaddr dot3Collided3Times; 202384059Swpaul bge_hostaddr dot3Collided4Times; 202484059Swpaul bge_hostaddr dot3Collided5Times; 202584059Swpaul bge_hostaddr dot3Collided6Times; 202684059Swpaul bge_hostaddr dot3Collided7Times; 202784059Swpaul bge_hostaddr dot3Collided8Times; 202884059Swpaul bge_hostaddr dot3Collided9Times; 202984059Swpaul bge_hostaddr dot3Collided10Times; 203084059Swpaul bge_hostaddr dot3Collided11Times; 203184059Swpaul bge_hostaddr dot3Collided12Times; 203284059Swpaul bge_hostaddr dot3Collided13Times; 203384059Swpaul bge_hostaddr dot3Collided14Times; 203484059Swpaul bge_hostaddr dot3Collided15Times; 203584059Swpaul bge_hostaddr ifHCOutUcastPkts; 203684059Swpaul bge_hostaddr ifHCOutMulticastPkts; 203784059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 203884059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 203984059Swpaul bge_hostaddr ifOutDiscards; 204084059Swpaul bge_hostaddr ifOutErrors; 2041117659Swpaul}; 204284059Swpaul 2043117659Swpaul/* Stats counters access through registers */ 2044117659Swpaulstruct bge_mac_stats_regs { 2045117659Swpaul u_int32_t ifHCOutOctets; 2046117659Swpaul u_int32_t Reserved0; 2047117659Swpaul u_int32_t etherStatsCollisions; 2048117659Swpaul u_int32_t outXonSent; 2049117659Swpaul u_int32_t outXoffSent; 2050117659Swpaul u_int32_t Reserved1; 2051117659Swpaul u_int32_t dot3StatsInternalMacTransmitErrors; 2052117659Swpaul u_int32_t dot3StatsSingleCollisionFrames; 2053117659Swpaul u_int32_t dot3StatsMultipleCollisionFrames; 2054117659Swpaul u_int32_t dot3StatsDeferredTransmissions; 2055117659Swpaul u_int32_t Reserved2; 2056117659Swpaul u_int32_t dot3StatsExcessiveCollisions; 2057117659Swpaul u_int32_t dot3StatsLateCollisions; 2058117659Swpaul u_int32_t Reserved3[14]; 2059117659Swpaul u_int32_t ifHCOutUcastPkts; 2060117659Swpaul u_int32_t ifHCOutMulticastPkts; 2061117659Swpaul u_int32_t ifHCOutBroadcastPkts; 2062117659Swpaul u_int32_t Reserved4[2]; 2063117659Swpaul u_int32_t ifHCInOctets; 2064117659Swpaul u_int32_t Reserved5; 2065117659Swpaul u_int32_t etherStatsFragments; 2066117659Swpaul u_int32_t ifHCInUcastPkts; 2067117659Swpaul u_int32_t ifHCInMulticastPkts; 2068117659Swpaul u_int32_t ifHCInBroadcastPkts; 2069117659Swpaul u_int32_t dot3StatsFCSErrors; 2070117659Swpaul u_int32_t dot3StatsAlignmentErrors; 2071117659Swpaul u_int32_t xonPauseFramesReceived; 2072117659Swpaul u_int32_t xoffPauseFramesReceived; 2073117659Swpaul u_int32_t macControlFramesReceived; 2074117659Swpaul u_int32_t xoffStateEntered; 2075117659Swpaul u_int32_t dot3StatsFramesTooLong; 2076117659Swpaul u_int32_t etherStatsJabbers; 2077117659Swpaul u_int32_t etherStatsUndersizePkts; 2078117659Swpaul}; 2079117659Swpaul 2080117659Swpaulstruct bge_stats { 2081117659Swpaul u_int8_t Reserved0[256]; 2082117659Swpaul 2083117659Swpaul /* Statistics maintained by Receive MAC. */ 2084117659Swpaul struct bge_rx_mac_stats rxstats; 2085117659Swpaul 2086117659Swpaul bge_hostaddr Unused1[37]; 2087117659Swpaul 2088117659Swpaul /* Statistics maintained by Transmit MAC. */ 2089117659Swpaul struct bge_tx_mac_stats txstats; 2090117659Swpaul 209184059Swpaul bge_hostaddr Unused2[31]; 209284059Swpaul 209384059Swpaul /* Statistics maintained by Receive List Placement. */ 209484059Swpaul bge_hostaddr COSIfHCInPkts[16]; 209584059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 209684059Swpaul bge_hostaddr nicDmaWriteQueueFull; 209784059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 209884059Swpaul bge_hostaddr nicNoMoreRxBDs; 209984059Swpaul bge_hostaddr ifInDiscards; 210084059Swpaul bge_hostaddr ifInErrors; 210184059Swpaul bge_hostaddr nicRecvThresholdHit; 210284059Swpaul 210384059Swpaul bge_hostaddr Unused3[9]; 210484059Swpaul 210584059Swpaul /* Statistics maintained by Send Data Initiator. */ 210684059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 210784059Swpaul bge_hostaddr nicDmaReadQueueFull; 210884059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 210984059Swpaul bge_hostaddr nicSendDataCompQueueFull; 211084059Swpaul 211184059Swpaul /* Statistics maintained by Host Coalescing. */ 211284059Swpaul bge_hostaddr nicRingSetSendProdIndex; 211384059Swpaul bge_hostaddr nicRingStatusUpdate; 211484059Swpaul bge_hostaddr nicInterrupts; 211584059Swpaul bge_hostaddr nicAvoidedInterrupts; 211684059Swpaul bge_hostaddr nicSendThresholdHit; 211784059Swpaul 211884059Swpaul u_int8_t Reserved4[320]; 211984059Swpaul}; 212084059Swpaul 212184059Swpaul/* 212284059Swpaul * Tigon general information block. This resides in host memory 212384059Swpaul * and contains the status counters, ring control blocks and 212484059Swpaul * producer pointers. 212584059Swpaul */ 212684059Swpaul 212784059Swpaulstruct bge_gib { 212884059Swpaul struct bge_stats bge_stats; 212984059Swpaul struct bge_rcb bge_tx_rcb[16]; 213084059Swpaul struct bge_rcb bge_std_rx_rcb; 213184059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 213284059Swpaul struct bge_rcb bge_mini_rx_rcb; 213384059Swpaul struct bge_rcb bge_return_rcb; 213484059Swpaul}; 213584059Swpaul 213684059Swpaul#define BGE_FRAMELEN 1518 213784059Swpaul#define BGE_MAX_FRAMELEN 1536 213884059Swpaul#define BGE_JUMBO_FRAMELEN 9018 213984059Swpaul#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 214084059Swpaul#define BGE_PAGE_SIZE PAGE_SIZE 214184059Swpaul#define BGE_MIN_FRAMELEN 60 214284059Swpaul 214384059Swpaul/* 214484059Swpaul * Other utility macros. 214584059Swpaul */ 214684059Swpaul#define BGE_INC(x, y) (x) = (x + 1) % y 214784059Swpaul 214884059Swpaul/* 214984059Swpaul * Vital product data and structures. 215084059Swpaul */ 215184059Swpaul#define BGE_VPD_FLAG 0x8000 215284059Swpaul 215384059Swpaul/* VPD structures */ 215484059Swpaulstruct vpd_res { 215584059Swpaul u_int8_t vr_id; 215684059Swpaul u_int8_t vr_len; 215784059Swpaul u_int8_t vr_pad; 215884059Swpaul}; 215984059Swpaul 216084059Swpaulstruct vpd_key { 216184059Swpaul char vk_key[2]; 216284059Swpaul u_int8_t vk_len; 216384059Swpaul}; 216484059Swpaul 216584059Swpaul#define VPD_RES_ID 0x82 /* ID string */ 216684059Swpaul#define VPD_RES_READ 0x90 /* start of read only area */ 216784059Swpaul#define VPD_RES_WRITE 0x81 /* start of read/write area */ 216884059Swpaul#define VPD_RES_END 0x78 /* end tag */ 216984059Swpaul 217084059Swpaul 217184059Swpaul/* 217284059Swpaul * Register access macros. The Tigon always uses memory mapped register 217384059Swpaul * accesses and all registers must be accessed with 32 bit operations. 217484059Swpaul */ 217584059Swpaul 217684059Swpaul#define CSR_WRITE_4(sc, reg, val) \ 217784059Swpaul bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 217884059Swpaul 217984059Swpaul#define CSR_READ_4(sc, reg) \ 218084059Swpaul bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 218184059Swpaul 218284059Swpaul#define BGE_SETBIT(sc, reg, x) \ 2183106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 218484059Swpaul#define BGE_CLRBIT(sc, reg, x) \ 2185106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 218684059Swpaul 218784059Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 2188106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 218984059Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 2190106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 219184059Swpaul 219284059Swpaul/* 219384059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 219484059Swpaul * values are tuneable. They control the actual amount of buffers 219584059Swpaul * allocated for the standard, mini and jumbo receive rings. 219684059Swpaul */ 219784059Swpaul 219884059Swpaul#define BGE_SSLOTS 256 219984059Swpaul#define BGE_MSLOTS 256 220084059Swpaul#define BGE_JSLOTS 384 220184059Swpaul 220284059Swpaul#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 220384059Swpaul#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 220484059Swpaul (BGE_JRAWLEN % sizeof(u_int64_t)))) 220584059Swpaul#define BGE_JPAGESZ PAGE_SIZE 220684059Swpaul#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 220784059Swpaul#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 220884059Swpaul 220984059Swpaul/* 221084059Swpaul * Ring structures. Most of these reside in host memory and we tell 221184059Swpaul * the NIC where they are via the ring control blocks. The exceptions 221284059Swpaul * are the tx and command rings, which live in NIC memory and which 221384059Swpaul * we access via the shared memory window. 221484059Swpaul */ 2215118026Swpaul 221684059Swpaulstruct bge_ring_data { 2217118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2218118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2219118026Swpaul struct bge_rx_bd *bge_rx_jumbo_ring; 2220118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2221118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2222118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2223118026Swpaul struct bge_tx_bd *bge_tx_ring; 2224118026Swpaul bus_addr_t bge_tx_ring_paddr; 2225118026Swpaul struct bge_status_block *bge_status_block; 2226118026Swpaul bus_addr_t bge_status_block_paddr; 2227118026Swpaul struct bge_stats *bge_stats; 2228118026Swpaul bus_addr_t bge_stats_paddr; 2229118026Swpaul void *bge_jumbo_buf; 223084059Swpaul struct bge_gib bge_info; 223184059Swpaul}; 223284059Swpaul 2233118026Swpaul#define BGE_STD_RX_RING_SZ \ 2234118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2235118026Swpaul#define BGE_JUMBO_RX_RING_SZ \ 2236118026Swpaul (sizeof(struct bge_rx_bd) * BGE_JUMBO_RX_RING_CNT) 2237118026Swpaul#define BGE_TX_RING_SZ \ 2238118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2239118026Swpaul#define BGE_RX_RTN_RING_SZ(x) \ 2240118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2241118026Swpaul 2242118026Swpaul#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2243118026Swpaul 2244118026Swpaul#define BGE_STATS_SZ sizeof (struct bge_stats) 2245118026Swpaul 224684059Swpaul/* 224784059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 224884059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 224984059Swpaul * not the other way around. 225084059Swpaul */ 225184059Swpaulstruct bge_chain_data { 2252118026Swpaul bus_dma_tag_t bge_parent_tag; 2253118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2254118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2255118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2256118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2257118026Swpaul bus_dma_tag_t bge_status_tag; 2258118026Swpaul bus_dma_tag_t bge_stats_tag; 2259118026Swpaul bus_dma_tag_t bge_jumbo_tag; 2260118026Swpaul bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2261118026Swpaul bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2262118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2263118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2264118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2265118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2266118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2267118026Swpaul bus_dmamap_t bge_tx_ring_map; 2268118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2269118026Swpaul bus_dmamap_t bge_status_map; 2270118026Swpaul bus_dmamap_t bge_stats_map; 2271118026Swpaul bus_dmamap_t bge_jumbo_map; 227284059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 227384059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 227484059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 227584059Swpaul /* Stick the jumbo mem management stuff here too. */ 227684059Swpaul caddr_t bge_jslots[BGE_JSLOTS]; 227784059Swpaul}; 227884059Swpaul 2279118026Swpaulstruct bge_dmamap_arg { 2280118026Swpaul struct bge_softc *sc; 2281118026Swpaul bus_addr_t bge_busaddr; 2282118026Swpaul u_int16_t bge_flags; 2283118026Swpaul int bge_idx; 2284118026Swpaul int bge_maxsegs; 2285118026Swpaul struct bge_tx_bd *bge_ring; 2286118026Swpaul}; 2287118026Swpaul 228884059Swpaulstruct bge_type { 228984059Swpaul u_int16_t bge_vid; 229084059Swpaul u_int16_t bge_did; 229184059Swpaul char *bge_name; 229284059Swpaul}; 229384059Swpaul 229484059Swpaul#define BGE_HWREV_TIGON 0x01 229584059Swpaul#define BGE_HWREV_TIGON_II 0x02 2296117659Swpaul#define BGE_TIMEOUT 100000 229784059Swpaul#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 229884059Swpaul 229984059Swpaulstruct bge_jpool_entry { 230084059Swpaul int slot; 230184059Swpaul SLIST_ENTRY(bge_jpool_entry) jpool_entries; 230284059Swpaul}; 230384059Swpaul 230484059Swpaulstruct bge_bcom_hack { 230584059Swpaul int reg; 230684059Swpaul int val; 230784059Swpaul}; 230884059Swpaul 230984059Swpaulstruct bge_softc { 231084059Swpaul struct arpcom arpcom; /* interface info */ 231184059Swpaul device_t bge_dev; 2312122497Ssam struct mtx bge_mtx; 231384059Swpaul device_t bge_miibus; 231484059Swpaul bus_space_handle_t bge_bhandle; 231584059Swpaul vm_offset_t bge_vhandle; 231684059Swpaul bus_space_tag_t bge_btag; 231784059Swpaul void *bge_intrhand; 231884059Swpaul struct resource *bge_irq; 231984059Swpaul struct resource *bge_res; 232084059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 232184059Swpaul u_int8_t bge_unit; /* interface number */ 232284059Swpaul u_int8_t bge_extram; /* has external SSRAM */ 232384059Swpaul u_int8_t bge_tbi; 232498779Sjdp u_int8_t bge_rx_alignment_bug; 2325114813Sps u_int32_t bge_chipid; 2326114813Sps u_int8_t bge_asicrev; 2327114813Sps u_int8_t bge_chiprev; 2328119157Sambrisko u_int8_t bge_no_3_led; 2329135772Sps u_int8_t bge_pcie; 2330118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 233184059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 233284059Swpaul u_int16_t bge_tx_saved_considx; 233384059Swpaul u_int16_t bge_rx_saved_considx; 233484059Swpaul u_int16_t bge_ev_saved_considx; 2335117659Swpaul u_int16_t bge_return_ring_cnt; 233684059Swpaul u_int16_t bge_std; /* current std ring head */ 233784059Swpaul u_int16_t bge_jumbo; /* current jumo ring head */ 233884059Swpaul SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 233984059Swpaul SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 234084059Swpaul u_int32_t bge_stat_ticks; 234184059Swpaul u_int32_t bge_rx_coal_ticks; 234284059Swpaul u_int32_t bge_tx_coal_ticks; 234384059Swpaul u_int32_t bge_rx_max_coal_bds; 234484059Swpaul u_int32_t bge_tx_max_coal_bds; 234584059Swpaul u_int32_t bge_tx_buf_ratio; 234684059Swpaul int bge_if_flags; 234784059Swpaul int bge_txcnt; 234884059Swpaul int bge_link; 2349122497Ssam struct callout bge_stat_ch; 235084059Swpaul char *bge_vpd_prodname; 235184059Swpaul char *bge_vpd_readonly; 235284059Swpaul}; 2353122497Ssam 2354122497Ssam#define BGE_LOCK_INIT(_sc, _name) \ 2355122497Ssam mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2356122497Ssam#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2357122497Ssam#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2358122497Ssam#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2359122497Ssam#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2360