if_bgereg.h revision 118026
184059Swpaul/* 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 118026 2003-07-25 19:42:44Z wpaul $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 6484059Swpaul#define BGE_PAGE_ZERO 0x00000000 6584059Swpaul#define BGE_PAGE_ZERO_END 0x000000FF 6684059Swpaul#define BGE_SEND_RING_RCB 0x00000100 6784059Swpaul#define BGE_SEND_RING_RCB_END 0x000001FF 6884059Swpaul#define BGE_RX_RETURN_RING_RCB 0x00000200 6984059Swpaul#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 7084059Swpaul#define BGE_STATS_BLOCK 0x00000300 7184059Swpaul#define BGE_STATS_BLOCK_END 0x00000AFF 7284059Swpaul#define BGE_STATUS_BLOCK 0x00000B00 7384059Swpaul#define BGE_STATUS_BLOCK_END 0x00000B4F 7484059Swpaul#define BGE_SOFTWARE_GENCOMM 0x00000B50 75110367Sps#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76110367Sps#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 7784059Swpaul#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 7884059Swpaul#define BGE_UNMAPPED 0x00001000 7984059Swpaul#define BGE_UNMAPPED_END 0x00001FFF 8084059Swpaul#define BGE_DMA_DESCRIPTORS 0x00002000 8184059Swpaul#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 8284059Swpaul#define BGE_SEND_RING_1_TO_4 0x00004000 8384059Swpaul#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8484059Swpaul 8584059Swpaul/* Mappings for internal memory configuration */ 8684059Swpaul#define BGE_STD_RX_RINGS 0x00006000 8784059Swpaul#define BGE_STD_RX_RINGS_END 0x00006FFF 8884059Swpaul#define BGE_JUMBO_RX_RINGS 0x00007000 8984059Swpaul#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 9084059Swpaul#define BGE_BUFFPOOL_1 0x00008000 9184059Swpaul#define BGE_BUFFPOOL_1_END 0x0000FFFF 9284059Swpaul#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 9384059Swpaul#define BGE_BUFFPOOL_2_END 0x00017FFF 9484059Swpaul#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 9584059Swpaul#define BGE_BUFFPOOL_3_END 0x0001FFFF 9684059Swpaul 9784059Swpaul/* Mappings for external SSRAM configurations */ 9884059Swpaul#define BGE_SEND_RING_5_TO_6 0x00006000 9984059Swpaul#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 10084059Swpaul#define BGE_SEND_RING_7_TO_8 0x00007000 10184059Swpaul#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 10284059Swpaul#define BGE_SEND_RING_9_TO_16 0x00008000 10384059Swpaul#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 10484059Swpaul#define BGE_EXT_STD_RX_RINGS 0x0000C000 10584059Swpaul#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 10684059Swpaul#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 10784059Swpaul#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 10884059Swpaul#define BGE_MINI_RX_RINGS 0x0000E000 10984059Swpaul#define BGE_MINI_RX_RINGS_END 0x0000FFFF 11084059Swpaul#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 11184059Swpaul#define BGE_AVAIL_REGION1_END 0x00017FFF 11284059Swpaul#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 11384059Swpaul#define BGE_AVAIL_REGION2_END 0x0001FFFF 11484059Swpaul#define BGE_EXT_SSRAM 0x00020000 11584059Swpaul#define BGE_EXT_SSRAM_END 0x000FFFFF 11684059Swpaul 11784059Swpaul 11884059Swpaul/* 11984059Swpaul * BCM570x register offsets. These are memory mapped registers 12084059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12184059Swpaul * Each register must be accessed using 32 bit operations. 12284059Swpaul * 12384059Swpaul * All registers are accessed through a 32K shared memory block. 12484059Swpaul * The first group of registers are actually copies of the PCI 12584059Swpaul * configuration space registers. 12684059Swpaul */ 12784059Swpaul 12884059Swpaul/* 12984059Swpaul * PCI registers defined in the PCI 2.2 spec. 13084059Swpaul */ 13184059Swpaul#define BGE_PCI_VID 0x00 13284059Swpaul#define BGE_PCI_DID 0x02 13384059Swpaul#define BGE_PCI_CMD 0x04 13484059Swpaul#define BGE_PCI_STS 0x06 13584059Swpaul#define BGE_PCI_REV 0x08 13684059Swpaul#define BGE_PCI_CLASS 0x09 13784059Swpaul#define BGE_PCI_CACHESZ 0x0C 13884059Swpaul#define BGE_PCI_LATTIMER 0x0D 13984059Swpaul#define BGE_PCI_HDRTYPE 0x0E 14084059Swpaul#define BGE_PCI_BIST 0x0F 14184059Swpaul#define BGE_PCI_BAR0 0x10 14284059Swpaul#define BGE_PCI_BAR1 0x14 14384059Swpaul#define BGE_PCI_SUBSYS 0x2C 14484059Swpaul#define BGE_PCI_SUBVID 0x2E 14584059Swpaul#define BGE_PCI_ROMBASE 0x30 14684059Swpaul#define BGE_PCI_CAPPTR 0x34 14784059Swpaul#define BGE_PCI_INTLINE 0x3C 14884059Swpaul#define BGE_PCI_INTPIN 0x3D 14984059Swpaul#define BGE_PCI_MINGNT 0x3E 15084059Swpaul#define BGE_PCI_MAXLAT 0x3F 15184059Swpaul#define BGE_PCI_PCIXCAP 0x40 15284059Swpaul#define BGE_PCI_NEXTPTR_PM 0x41 15384059Swpaul#define BGE_PCI_PCIX_CMD 0x42 15484059Swpaul#define BGE_PCI_PCIX_STS 0x44 15584059Swpaul#define BGE_PCI_PWRMGMT_CAPID 0x48 15684059Swpaul#define BGE_PCI_NEXTPTR_VPD 0x49 15784059Swpaul#define BGE_PCI_PWRMGMT_CAPS 0x4A 15884059Swpaul#define BGE_PCI_PWRMGMT_CMD 0x4C 15984059Swpaul#define BGE_PCI_PWRMGMT_STS 0x4D 16084059Swpaul#define BGE_PCI_PWRMGMT_DATA 0x4F 16184059Swpaul#define BGE_PCI_VPD_CAPID 0x50 16284059Swpaul#define BGE_PCI_NEXTPTR_MSI 0x51 16384059Swpaul#define BGE_PCI_VPD_ADDR 0x52 16484059Swpaul#define BGE_PCI_VPD_DATA 0x54 16584059Swpaul#define BGE_PCI_MSI_CAPID 0x58 16684059Swpaul#define BGE_PCI_NEXTPTR_NONE 0x59 16784059Swpaul#define BGE_PCI_MSI_CTL 0x5A 16884059Swpaul#define BGE_PCI_MSI_ADDR_HI 0x5C 16984059Swpaul#define BGE_PCI_MSI_ADDR_LO 0x60 17084059Swpaul#define BGE_PCI_MSI_DATA 0x64 17184059Swpaul 17284059Swpaul/* 17384059Swpaul * PCI registers specific to the BCM570x family. 17484059Swpaul */ 17584059Swpaul#define BGE_PCI_MISC_CTL 0x68 17684059Swpaul#define BGE_PCI_DMA_RW_CTL 0x6C 17784059Swpaul#define BGE_PCI_PCISTATE 0x70 17884059Swpaul#define BGE_PCI_CLKCTL 0x74 17984059Swpaul#define BGE_PCI_REG_BASEADDR 0x78 18084059Swpaul#define BGE_PCI_MEMWIN_BASEADDR 0x7C 18184059Swpaul#define BGE_PCI_REG_DATA 0x80 18284059Swpaul#define BGE_PCI_MEMWIN_DATA 0x84 18384059Swpaul#define BGE_PCI_MODECTL 0x88 18484059Swpaul#define BGE_PCI_MISC_CFG 0x8C 18584059Swpaul#define BGE_PCI_MISC_LOCALCTL 0x90 18684059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 18784059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 18884059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 18984059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 19084059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 19184059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 19284059Swpaul#define BGE_PCI_ISR_MBX_HI 0xB0 19384059Swpaul#define BGE_PCI_ISR_MBX_LO 0xB4 19484059Swpaul 19584059Swpaul/* PCI Misc. Host control register */ 19684059Swpaul#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 19784059Swpaul#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 19884059Swpaul#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 19984059Swpaul#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 20084059Swpaul#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 20184059Swpaul#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 20284059Swpaul#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 20384059Swpaul#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 20484059Swpaul#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 20584059Swpaul 20684059Swpaul#define BGE_BIGENDIAN_INIT \ 207104325Sjake (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 20884059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 209104325Sjake BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 21084059Swpaul 21184059Swpaul#define BGE_LITTLEENDIAN_INIT \ 21284059Swpaul (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 21384059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 21484059Swpaul 215114813Sps#define BGE_CHIPID_TIGON_I 0x40000000 216114813Sps#define BGE_CHIPID_TIGON_II 0x60000000 217114813Sps#define BGE_CHIPID_BCM5700_B0 0x71000000 218114813Sps#define BGE_CHIPID_BCM5700_B1 0x71020000 219114813Sps#define BGE_CHIPID_BCM5700_B2 0x71030000 220114813Sps#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 221114813Sps#define BGE_CHIPID_BCM5700_C0 0x72000000 222114813Sps#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 223114813Sps#define BGE_CHIPID_BCM5701_B0 0x01000000 224114813Sps#define BGE_CHIPID_BCM5701_B2 0x01020000 225114813Sps#define BGE_CHIPID_BCM5701_B5 0x01050000 226114813Sps#define BGE_CHIPID_BCM5703_A0 0x10000000 227114813Sps#define BGE_CHIPID_BCM5703_A1 0x10010000 228114813Sps#define BGE_CHIPID_BCM5703_A2 0x10020000 229114813Sps#define BGE_CHIPID_BCM5704_A0 0x20000000 230114813Sps#define BGE_CHIPID_BCM5704_A1 0x20010000 231114813Sps#define BGE_CHIPID_BCM5704_A2 0x20020000 232117659Swpaul#define BGE_CHIPID_BCM5705_A0 0x30000000 233117659Swpaul#define BGE_CHIPID_BCM5705_A1 0x30010000 234117659Swpaul#define BGE_CHIPID_BCM5705_A2 0x30020000 235117659Swpaul#define BGE_CHIPID_BCM5705_A3 0x30030000 23684059Swpaul 23793751Swpaul/* shorthand one */ 238114615Sps#define BGE_ASICREV(x) ((x) >> 28) 239114615Sps#define BGE_ASICREV_BCM5700 0x07 240114615Sps#define BGE_ASICREV_BCM5701 0x00 241114615Sps#define BGE_ASICREV_BCM5703 0x01 242114615Sps#define BGE_ASICREV_BCM5704 0x02 243117659Swpaul#define BGE_ASICREV_BCM5705 0x03 24493751Swpaul 245114813Sps/* chip revisions */ 246114813Sps#define BGE_CHIPREV(x) ((x) >> 24) 247114813Sps#define BGE_CHIPREV_5700_AX 0x70 248114813Sps#define BGE_CHIPREV_5700_BX 0x71 249114813Sps#define BGE_CHIPREV_5700_CX 0x72 250114813Sps#define BGE_CHIPREV_5701_AX 0x00 251114813Sps 25284059Swpaul/* PCI DMA Read/Write Control register */ 25384059Swpaul#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 25484059Swpaul#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 25584059Swpaul#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 25684059Swpaul#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 25784059Swpaul#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 258114615Sps# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 25984059Swpaul#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 260114615Sps# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 26184059Swpaul#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 26284059Swpaul#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 26384059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 264114615Sps# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 26584059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 266114615Sps# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 26784059Swpaul 26884059Swpaul#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 26984059Swpaul#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 27084059Swpaul#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 27184059Swpaul#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 27284059Swpaul#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 27384059Swpaul#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 27484059Swpaul#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 27584059Swpaul#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 27684059Swpaul 27784059Swpaul#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 27884059Swpaul#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 27984059Swpaul#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 28084059Swpaul#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 28184059Swpaul#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 28284059Swpaul#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 28384059Swpaul#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 28484059Swpaul#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 28584059Swpaul 28684059Swpaul/* 28784059Swpaul * PCI state register -- note, this register is read only 28884059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 28984059Swpaul * register is set. 29084059Swpaul */ 29184059Swpaul#define BGE_PCISTATE_FORCE_RESET 0x00000001 29284059Swpaul#define BGE_PCISTATE_INTR_STATE 0x00000002 29384059Swpaul#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 29484059Swpaul#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 29584059Swpaul#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 29684059Swpaul#define BGE_PCISTATE_WANT_EXPROM 0x00000020 29784059Swpaul#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 29884059Swpaul#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 29984059Swpaul#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 30084059Swpaul 30184059Swpaul/* 30284059Swpaul * PCI Clock Control register -- note, this register is read only 30384059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 30484059Swpaul * register is set. 30584059Swpaul */ 30684059Swpaul#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 30784059Swpaul#define BGE_PCICLOCKCTL_M66EN 0x00000080 30884059Swpaul#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 30984059Swpaul#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 31084059Swpaul#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 31184059Swpaul#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 31284059Swpaul#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 31384059Swpaul#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 31484059Swpaul#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 31584059Swpaul#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 31684059Swpaul 31784059Swpaul 31884059Swpaul#ifndef PCIM_CMD_MWIEN 31984059Swpaul#define PCIM_CMD_MWIEN 0x0010 32084059Swpaul#endif 32184059Swpaul 32284059Swpaul/* 32384059Swpaul * High priority mailbox registers 32484059Swpaul * Each mailbox is 64-bits wide, though we only use the 32584059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 32684059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 32784059Swpaul * has been updated. 32884059Swpaul */ 32984059Swpaul#define BGE_MBX_IRQ0_HI 0x0200 33084059Swpaul#define BGE_MBX_IRQ0_LO 0x0204 33184059Swpaul#define BGE_MBX_IRQ1_HI 0x0208 33284059Swpaul#define BGE_MBX_IRQ1_LO 0x020C 33384059Swpaul#define BGE_MBX_IRQ2_HI 0x0210 33484059Swpaul#define BGE_MBX_IRQ2_LO 0x0214 33584059Swpaul#define BGE_MBX_IRQ3_HI 0x0218 33684059Swpaul#define BGE_MBX_IRQ3_LO 0x021C 33784059Swpaul#define BGE_MBX_GEN0_HI 0x0220 33884059Swpaul#define BGE_MBX_GEN0_LO 0x0224 33984059Swpaul#define BGE_MBX_GEN1_HI 0x0228 34084059Swpaul#define BGE_MBX_GEN1_LO 0x022C 34184059Swpaul#define BGE_MBX_GEN2_HI 0x0230 34284059Swpaul#define BGE_MBX_GEN2_LO 0x0234 34384059Swpaul#define BGE_MBX_GEN3_HI 0x0228 34484059Swpaul#define BGE_MBX_GEN3_LO 0x022C 34584059Swpaul#define BGE_MBX_GEN4_HI 0x0240 34684059Swpaul#define BGE_MBX_GEN4_LO 0x0244 34784059Swpaul#define BGE_MBX_GEN5_HI 0x0248 34884059Swpaul#define BGE_MBX_GEN5_LO 0x024C 34984059Swpaul#define BGE_MBX_GEN6_HI 0x0250 35084059Swpaul#define BGE_MBX_GEN6_LO 0x0254 35184059Swpaul#define BGE_MBX_GEN7_HI 0x0258 35284059Swpaul#define BGE_MBX_GEN7_LO 0x025C 35384059Swpaul#define BGE_MBX_RELOAD_STATS_HI 0x0260 35484059Swpaul#define BGE_MBX_RELOAD_STATS_LO 0x0264 35584059Swpaul#define BGE_MBX_RX_STD_PROD_HI 0x0268 35684059Swpaul#define BGE_MBX_RX_STD_PROD_LO 0x026C 35784059Swpaul#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 35884059Swpaul#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 35984059Swpaul#define BGE_MBX_RX_MINI_PROD_HI 0x0278 36084059Swpaul#define BGE_MBX_RX_MINI_PROD_LO 0x027C 36184059Swpaul#define BGE_MBX_RX_CONS0_HI 0x0280 36284059Swpaul#define BGE_MBX_RX_CONS0_LO 0x0284 36384059Swpaul#define BGE_MBX_RX_CONS1_HI 0x0288 36484059Swpaul#define BGE_MBX_RX_CONS1_LO 0x028C 36584059Swpaul#define BGE_MBX_RX_CONS2_HI 0x0290 36684059Swpaul#define BGE_MBX_RX_CONS2_LO 0x0294 36784059Swpaul#define BGE_MBX_RX_CONS3_HI 0x0298 36884059Swpaul#define BGE_MBX_RX_CONS3_LO 0x029C 36984059Swpaul#define BGE_MBX_RX_CONS4_HI 0x02A0 37084059Swpaul#define BGE_MBX_RX_CONS4_LO 0x02A4 37184059Swpaul#define BGE_MBX_RX_CONS5_HI 0x02A8 37284059Swpaul#define BGE_MBX_RX_CONS5_LO 0x02AC 37384059Swpaul#define BGE_MBX_RX_CONS6_HI 0x02B0 37484059Swpaul#define BGE_MBX_RX_CONS6_LO 0x02B4 37584059Swpaul#define BGE_MBX_RX_CONS7_HI 0x02B8 37684059Swpaul#define BGE_MBX_RX_CONS7_LO 0x02BC 37784059Swpaul#define BGE_MBX_RX_CONS8_HI 0x02C0 37884059Swpaul#define BGE_MBX_RX_CONS8_LO 0x02C4 37984059Swpaul#define BGE_MBX_RX_CONS9_HI 0x02C8 38084059Swpaul#define BGE_MBX_RX_CONS9_LO 0x02CC 38184059Swpaul#define BGE_MBX_RX_CONS10_HI 0x02D0 38284059Swpaul#define BGE_MBX_RX_CONS10_LO 0x02D4 38384059Swpaul#define BGE_MBX_RX_CONS11_HI 0x02D8 38484059Swpaul#define BGE_MBX_RX_CONS11_LO 0x02DC 38584059Swpaul#define BGE_MBX_RX_CONS12_HI 0x02E0 38684059Swpaul#define BGE_MBX_RX_CONS12_LO 0x02E4 38784059Swpaul#define BGE_MBX_RX_CONS13_HI 0x02E8 38884059Swpaul#define BGE_MBX_RX_CONS13_LO 0x02EC 38984059Swpaul#define BGE_MBX_RX_CONS14_HI 0x02F0 39084059Swpaul#define BGE_MBX_RX_CONS14_LO 0x02F4 39184059Swpaul#define BGE_MBX_RX_CONS15_HI 0x02F8 39284059Swpaul#define BGE_MBX_RX_CONS15_LO 0x02FC 39384059Swpaul#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 39484059Swpaul#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 39584059Swpaul#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 39684059Swpaul#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 39784059Swpaul#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 39884059Swpaul#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 39984059Swpaul#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 40084059Swpaul#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 40184059Swpaul#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 40284059Swpaul#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 40384059Swpaul#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 40484059Swpaul#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 40584059Swpaul#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 40684059Swpaul#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 40784059Swpaul#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 40884059Swpaul#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 40984059Swpaul#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 41084059Swpaul#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 41184059Swpaul#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 41284059Swpaul#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 41384059Swpaul#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 41484059Swpaul#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 41584059Swpaul#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 41684059Swpaul#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 41784059Swpaul#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 41884059Swpaul#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 41984059Swpaul#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 42084059Swpaul#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 42184059Swpaul#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 42284059Swpaul#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 42384059Swpaul#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 42484059Swpaul#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 42584059Swpaul#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 42684059Swpaul#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 42784059Swpaul#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 42884059Swpaul#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 42984059Swpaul#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 43084059Swpaul#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 43184059Swpaul#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 43284059Swpaul#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 43384059Swpaul#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 43484059Swpaul#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 43584059Swpaul#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 43684059Swpaul#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 43784059Swpaul#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 43884059Swpaul#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 43984059Swpaul#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 44084059Swpaul#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 44184059Swpaul#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 44284059Swpaul#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 44384059Swpaul#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 44484059Swpaul#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 44584059Swpaul#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 44684059Swpaul#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 44784059Swpaul#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 44884059Swpaul#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 44984059Swpaul#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 45084059Swpaul#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 45184059Swpaul#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 45284059Swpaul#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 45384059Swpaul#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 45484059Swpaul#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 45584059Swpaul#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 45684059Swpaul#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 45784059Swpaul 45884059Swpaul#define BGE_TX_RINGS_MAX 4 45984059Swpaul#define BGE_TX_RINGS_EXTSSRAM_MAX 16 46084059Swpaul#define BGE_RX_RINGS_MAX 16 46184059Swpaul 46284059Swpaul/* Ethernet MAC control registers */ 46384059Swpaul#define BGE_MAC_MODE 0x0400 46484059Swpaul#define BGE_MAC_STS 0x0404 46584059Swpaul#define BGE_MAC_EVT_ENB 0x0408 46684059Swpaul#define BGE_MAC_LED_CTL 0x040C 46784059Swpaul#define BGE_MAC_ADDR1_LO 0x0410 46884059Swpaul#define BGE_MAC_ADDR1_HI 0x0414 46984059Swpaul#define BGE_MAC_ADDR2_LO 0x0418 47084059Swpaul#define BGE_MAC_ADDR2_HI 0x041C 47184059Swpaul#define BGE_MAC_ADDR3_LO 0x0420 47284059Swpaul#define BGE_MAC_ADDR3_HI 0x0424 47384059Swpaul#define BGE_MAC_ADDR4_LO 0x0428 47484059Swpaul#define BGE_MAC_ADDR4_HI 0x042C 47584059Swpaul#define BGE_WOL_PATPTR 0x0430 47684059Swpaul#define BGE_WOL_PATCFG 0x0434 47784059Swpaul#define BGE_TX_RANDOM_BACKOFF 0x0438 47884059Swpaul#define BGE_RX_MTU 0x043C 47984059Swpaul#define BGE_GBIT_PCS_TEST 0x0440 48084059Swpaul#define BGE_TX_TBI_AUTONEG 0x0444 48184059Swpaul#define BGE_RX_TBI_AUTONEG 0x0448 48284059Swpaul#define BGE_MI_COMM 0x044C 48384059Swpaul#define BGE_MI_STS 0x0450 48484059Swpaul#define BGE_MI_MODE 0x0454 48584059Swpaul#define BGE_AUTOPOLL_STS 0x0458 48684059Swpaul#define BGE_TX_MODE 0x045C 48784059Swpaul#define BGE_TX_STS 0x0460 48884059Swpaul#define BGE_TX_LENGTHS 0x0464 48984059Swpaul#define BGE_RX_MODE 0x0468 49084059Swpaul#define BGE_RX_STS 0x046C 49184059Swpaul#define BGE_MAR0 0x0470 49284059Swpaul#define BGE_MAR1 0x0474 49384059Swpaul#define BGE_MAR2 0x0478 49484059Swpaul#define BGE_MAR3 0x047C 49584059Swpaul#define BGE_RX_BD_RULES_CTL0 0x0480 49684059Swpaul#define BGE_RX_BD_RULES_MASKVAL0 0x0484 49784059Swpaul#define BGE_RX_BD_RULES_CTL1 0x0488 49884059Swpaul#define BGE_RX_BD_RULES_MASKVAL1 0x048C 49984059Swpaul#define BGE_RX_BD_RULES_CTL2 0x0490 50084059Swpaul#define BGE_RX_BD_RULES_MASKVAL2 0x0494 50184059Swpaul#define BGE_RX_BD_RULES_CTL3 0x0498 50284059Swpaul#define BGE_RX_BD_RULES_MASKVAL3 0x049C 50384059Swpaul#define BGE_RX_BD_RULES_CTL4 0x04A0 50484059Swpaul#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 50584059Swpaul#define BGE_RX_BD_RULES_CTL5 0x04A8 50684059Swpaul#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 50784059Swpaul#define BGE_RX_BD_RULES_CTL6 0x04B0 50884059Swpaul#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 50984059Swpaul#define BGE_RX_BD_RULES_CTL7 0x04B8 51084059Swpaul#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 51184059Swpaul#define BGE_RX_BD_RULES_CTL8 0x04C0 51284059Swpaul#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 51384059Swpaul#define BGE_RX_BD_RULES_CTL9 0x04C8 51484059Swpaul#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 51584059Swpaul#define BGE_RX_BD_RULES_CTL10 0x04D0 51684059Swpaul#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 51784059Swpaul#define BGE_RX_BD_RULES_CTL11 0x04D8 51884059Swpaul#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 51984059Swpaul#define BGE_RX_BD_RULES_CTL12 0x04E0 52084059Swpaul#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 52184059Swpaul#define BGE_RX_BD_RULES_CTL13 0x04E8 52284059Swpaul#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 52384059Swpaul#define BGE_RX_BD_RULES_CTL14 0x04F0 52484059Swpaul#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 52584059Swpaul#define BGE_RX_BD_RULES_CTL15 0x04F8 52684059Swpaul#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 52784059Swpaul#define BGE_RX_RULES_CFG 0x0500 52884059Swpaul#define BGE_RX_STATS 0x0800 52984059Swpaul#define BGE_TX_STATS 0x0880 53084059Swpaul 53184059Swpaul/* Ethernet MAC Mode register */ 53284059Swpaul#define BGE_MACMODE_RESET 0x00000001 53384059Swpaul#define BGE_MACMODE_HALF_DUPLEX 0x00000002 53484059Swpaul#define BGE_MACMODE_PORTMODE 0x0000000C 53584059Swpaul#define BGE_MACMODE_LOOPBACK 0x00000010 53684059Swpaul#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 53784059Swpaul#define BGE_MACMODE_TX_BURST_ENB 0x00000100 53884059Swpaul#define BGE_MACMODE_MAX_DEFER 0x00000200 53984059Swpaul#define BGE_MACMODE_LINK_POLARITY 0x00000400 54084059Swpaul#define BGE_MACMODE_RX_STATS_ENB 0x00000800 54184059Swpaul#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 54284059Swpaul#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 54384059Swpaul#define BGE_MACMODE_TX_STATS_ENB 0x00004000 54484059Swpaul#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 54584059Swpaul#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 54684059Swpaul#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 54784059Swpaul#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 54884059Swpaul#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 54984059Swpaul#define BGE_MACMODE_MIP_ENB 0x00100000 55084059Swpaul#define BGE_MACMODE_TXDMA_ENB 0x00200000 55184059Swpaul#define BGE_MACMODE_RXDMA_ENB 0x00400000 55284059Swpaul#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 55384059Swpaul 55484059Swpaul#define BGE_PORTMODE_NONE 0x00000000 55584059Swpaul#define BGE_PORTMODE_MII 0x00000004 55684059Swpaul#define BGE_PORTMODE_GMII 0x00000008 55784059Swpaul#define BGE_PORTMODE_TBI 0x0000000C 55884059Swpaul 55984059Swpaul/* MAC Status register */ 56084059Swpaul#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 56184059Swpaul#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 56284059Swpaul#define BGE_MACSTAT_RX_CFG 0x00000004 56384059Swpaul#define BGE_MACSTAT_CFG_CHANGED 0x00000008 56484059Swpaul#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 56584059Swpaul#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 56684059Swpaul#define BGE_MACSTAT_LINK_CHANGED 0x00001000 56784059Swpaul#define BGE_MACSTAT_MI_COMPLETE 0x00400000 56884059Swpaul#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 56984059Swpaul#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 57084059Swpaul#define BGE_MACSTAT_ODI_ERROR 0x02000000 57184059Swpaul#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 57284059Swpaul#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 57384059Swpaul 57484059Swpaul/* MAC Event Enable Register */ 57584059Swpaul#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 57684059Swpaul#define BGE_EVTENB_LINK_CHANGED 0x00001000 57784059Swpaul#define BGE_EVTENB_MI_COMPLETE 0x00400000 57884059Swpaul#define BGE_EVTENB_MI_INTERRUPT 0x00800000 57984059Swpaul#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 58084059Swpaul#define BGE_EVTENB_ODI_ERROR 0x02000000 58184059Swpaul#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 58284059Swpaul#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 58384059Swpaul 58484059Swpaul/* LED Control Register */ 58584059Swpaul#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 58684059Swpaul#define BGE_LEDCTL_1000MBPS_LED 0x00000002 58784059Swpaul#define BGE_LEDCTL_100MBPS_LED 0x00000004 58884059Swpaul#define BGE_LEDCTL_10MBPS_LED 0x00000008 58984059Swpaul#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 59084059Swpaul#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 59184059Swpaul#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 59284059Swpaul#define BGE_LEDCTL_1000MBPS_STS 0x00000080 59384059Swpaul#define BGE_LEDCTL_100MBPS_STS 0x00000100 59484059Swpaul#define BGE_LEDCTL_10MBPS_STS 0x00000200 59584059Swpaul#define BGE_LEDCTL_TRADLED_STS 0x00000400 59684059Swpaul#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 59784059Swpaul#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 59884059Swpaul 59984059Swpaul/* TX backoff seed register */ 60084059Swpaul#define BGE_TX_BACKOFF_SEED_MASK 0x3F 60184059Swpaul 60284059Swpaul/* Autopoll status register */ 60384059Swpaul#define BGE_AUTOPOLLSTS_ERROR 0x00000001 60484059Swpaul 60584059Swpaul/* Transmit MAC mode register */ 60684059Swpaul#define BGE_TXMODE_RESET 0x00000001 60784059Swpaul#define BGE_TXMODE_ENABLE 0x00000002 60884059Swpaul#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 60984059Swpaul#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 61084059Swpaul#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 61184059Swpaul 61284059Swpaul/* Transmit MAC status register */ 61384059Swpaul#define BGE_TXSTAT_RX_XOFFED 0x00000001 61484059Swpaul#define BGE_TXSTAT_SENT_XOFF 0x00000002 61584059Swpaul#define BGE_TXSTAT_SENT_XON 0x00000004 61684059Swpaul#define BGE_TXSTAT_LINK_UP 0x00000008 61784059Swpaul#define BGE_TXSTAT_ODI_UFLOW 0x00000010 61884059Swpaul#define BGE_TXSTAT_ODI_OFLOW 0x00000020 61984059Swpaul 62084059Swpaul/* Transmit MAC lengths register */ 62184059Swpaul#define BGE_TXLEN_SLOTTIME 0x000000FF 62284059Swpaul#define BGE_TXLEN_IPG 0x00000F00 62384059Swpaul#define BGE_TXLEN_CRS 0x00003000 62484059Swpaul 62584059Swpaul/* Receive MAC mode register */ 62684059Swpaul#define BGE_RXMODE_RESET 0x00000001 62784059Swpaul#define BGE_RXMODE_ENABLE 0x00000002 62884059Swpaul#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 62984059Swpaul#define BGE_RXMODE_RX_GIANTS 0x00000020 63084059Swpaul#define BGE_RXMODE_RX_RUNTS 0x00000040 63184059Swpaul#define BGE_RXMODE_8022_LENCHECK 0x00000080 63284059Swpaul#define BGE_RXMODE_RX_PROMISC 0x00000100 63384059Swpaul#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 63484059Swpaul#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 63584059Swpaul 63684059Swpaul/* Receive MAC status register */ 63784059Swpaul#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 63884059Swpaul#define BGE_RXSTAT_RCVD_XOFF 0x00000002 63984059Swpaul#define BGE_RXSTAT_RCVD_XON 0x00000004 64084059Swpaul 64184059Swpaul/* Receive Rules Control register */ 64284059Swpaul#define BGE_RXRULECTL_OFFSET 0x000000FF 64384059Swpaul#define BGE_RXRULECTL_CLASS 0x00001F00 64484059Swpaul#define BGE_RXRULECTL_HDRTYPE 0x0000E000 64584059Swpaul#define BGE_RXRULECTL_COMPARE_OP 0x00030000 64684059Swpaul#define BGE_RXRULECTL_MAP 0x01000000 64784059Swpaul#define BGE_RXRULECTL_DISCARD 0x02000000 64884059Swpaul#define BGE_RXRULECTL_MASK 0x04000000 64984059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 65084059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 65184059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 65284059Swpaul#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 65384059Swpaul 65484059Swpaul/* Receive Rules Mask register */ 65584059Swpaul#define BGE_RXRULEMASK_VALUE 0x0000FFFF 65684059Swpaul#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 65784059Swpaul 65884059Swpaul/* MI communication register */ 65984059Swpaul#define BGE_MICOMM_DATA 0x0000FFFF 66084059Swpaul#define BGE_MICOMM_REG 0x001F0000 66184059Swpaul#define BGE_MICOMM_PHY 0x03E00000 66284059Swpaul#define BGE_MICOMM_CMD 0x0C000000 66384059Swpaul#define BGE_MICOMM_READFAIL 0x10000000 66484059Swpaul#define BGE_MICOMM_BUSY 0x20000000 66584059Swpaul 66684059Swpaul#define BGE_MIREG(x) ((x & 0x1F) << 16) 66784059Swpaul#define BGE_MIPHY(x) ((x & 0x1F) << 21) 66884059Swpaul#define BGE_MICMD_WRITE 0x04000000 66984059Swpaul#define BGE_MICMD_READ 0x08000000 67084059Swpaul 67184059Swpaul/* MI status register */ 67284059Swpaul#define BGE_MISTS_LINK 0x00000001 67384059Swpaul#define BGE_MISTS_10MBPS 0x00000002 67484059Swpaul 67584059Swpaul#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 67684059Swpaul#define BGE_MIMODE_AUTOPOLL 0x00000010 67784059Swpaul#define BGE_MIMODE_CLKCNT 0x001F0000 67884059Swpaul 67984059Swpaul 68084059Swpaul/* 68184059Swpaul * Send data initiator control registers. 68284059Swpaul */ 68384059Swpaul#define BGE_SDI_MODE 0x0C00 68484059Swpaul#define BGE_SDI_STATUS 0x0C04 68584059Swpaul#define BGE_SDI_STATS_CTL 0x0C08 68684059Swpaul#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 68784059Swpaul#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 68884059Swpaul#define BGE_LOCSTATS_COS0 0x0C80 68984059Swpaul#define BGE_LOCSTATS_COS1 0x0C84 69084059Swpaul#define BGE_LOCSTATS_COS2 0x0C88 69184059Swpaul#define BGE_LOCSTATS_COS3 0x0C8C 69284059Swpaul#define BGE_LOCSTATS_COS4 0x0C90 69384059Swpaul#define BGE_LOCSTATS_COS5 0x0C84 69484059Swpaul#define BGE_LOCSTATS_COS6 0x0C98 69584059Swpaul#define BGE_LOCSTATS_COS7 0x0C9C 69684059Swpaul#define BGE_LOCSTATS_COS8 0x0CA0 69784059Swpaul#define BGE_LOCSTATS_COS9 0x0CA4 69884059Swpaul#define BGE_LOCSTATS_COS10 0x0CA8 69984059Swpaul#define BGE_LOCSTATS_COS11 0x0CAC 70084059Swpaul#define BGE_LOCSTATS_COS12 0x0CB0 70184059Swpaul#define BGE_LOCSTATS_COS13 0x0CB4 70284059Swpaul#define BGE_LOCSTATS_COS14 0x0CB8 70384059Swpaul#define BGE_LOCSTATS_COS15 0x0CBC 70484059Swpaul#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 70584059Swpaul#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 70684059Swpaul#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 70784059Swpaul#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 70884059Swpaul#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 70984059Swpaul#define BGE_LOCSTATS_IRQS 0x0CD4 71084059Swpaul#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 71184059Swpaul#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 71284059Swpaul 71384059Swpaul/* Send Data Initiator mode register */ 71484059Swpaul#define BGE_SDIMODE_RESET 0x00000001 71584059Swpaul#define BGE_SDIMODE_ENABLE 0x00000002 71684059Swpaul#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 71784059Swpaul 71884059Swpaul/* Send Data Initiator stats register */ 71984059Swpaul#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 72084059Swpaul 72184059Swpaul/* Send Data Initiator stats control register */ 72284059Swpaul#define BGE_SDISTATSCTL_ENABLE 0x00000001 72384059Swpaul#define BGE_SDISTATSCTL_FASTER 0x00000002 72484059Swpaul#define BGE_SDISTATSCTL_CLEAR 0x00000004 72584059Swpaul#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 72684059Swpaul#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 72784059Swpaul 72884059Swpaul/* 72984059Swpaul * Send Data Completion Control registers 73084059Swpaul */ 73184059Swpaul#define BGE_SDC_MODE 0x1000 73284059Swpaul#define BGE_SDC_STATUS 0x1004 73384059Swpaul 73484059Swpaul/* Send Data completion mode register */ 73584059Swpaul#define BGE_SDCMODE_RESET 0x00000001 73684059Swpaul#define BGE_SDCMODE_ENABLE 0x00000002 73784059Swpaul#define BGE_SDCMODE_ATTN 0x00000004 73884059Swpaul 73984059Swpaul/* Send Data completion status register */ 74084059Swpaul#define BGE_SDCSTAT_ATTN 0x00000004 74184059Swpaul 74284059Swpaul/* 74384059Swpaul * Send BD Ring Selector Control registers 74484059Swpaul */ 74584059Swpaul#define BGE_SRS_MODE 0x1400 74684059Swpaul#define BGE_SRS_STATUS 0x1404 74784059Swpaul#define BGE_SRS_HWDIAG 0x1408 74884059Swpaul#define BGE_SRS_LOC_NIC_CONS0 0x1440 74984059Swpaul#define BGE_SRS_LOC_NIC_CONS1 0x1444 75084059Swpaul#define BGE_SRS_LOC_NIC_CONS2 0x1448 75184059Swpaul#define BGE_SRS_LOC_NIC_CONS3 0x144C 75284059Swpaul#define BGE_SRS_LOC_NIC_CONS4 0x1450 75384059Swpaul#define BGE_SRS_LOC_NIC_CONS5 0x1454 75484059Swpaul#define BGE_SRS_LOC_NIC_CONS6 0x1458 75584059Swpaul#define BGE_SRS_LOC_NIC_CONS7 0x145C 75684059Swpaul#define BGE_SRS_LOC_NIC_CONS8 0x1460 75784059Swpaul#define BGE_SRS_LOC_NIC_CONS9 0x1464 75884059Swpaul#define BGE_SRS_LOC_NIC_CONS10 0x1468 75984059Swpaul#define BGE_SRS_LOC_NIC_CONS11 0x146C 76084059Swpaul#define BGE_SRS_LOC_NIC_CONS12 0x1470 76184059Swpaul#define BGE_SRS_LOC_NIC_CONS13 0x1474 76284059Swpaul#define BGE_SRS_LOC_NIC_CONS14 0x1478 76384059Swpaul#define BGE_SRS_LOC_NIC_CONS15 0x147C 76484059Swpaul 76584059Swpaul/* Send BD Ring Selector Mode register */ 76684059Swpaul#define BGE_SRSMODE_RESET 0x00000001 76784059Swpaul#define BGE_SRSMODE_ENABLE 0x00000002 76884059Swpaul#define BGE_SRSMODE_ATTN 0x00000004 76984059Swpaul 77084059Swpaul/* Send BD Ring Selector Status register */ 77184059Swpaul#define BGE_SRSSTAT_ERROR 0x00000004 77284059Swpaul 77384059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 77484059Swpaul#define BGE_SRSHWDIAG_STATE 0x0000000F 77584059Swpaul#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 77684059Swpaul#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 77784059Swpaul#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 77884059Swpaul 77984059Swpaul/* 78084059Swpaul * Send BD Initiator Selector Control registers 78184059Swpaul */ 78284059Swpaul#define BGE_SBDI_MODE 0x1800 78384059Swpaul#define BGE_SBDI_STATUS 0x1804 78484059Swpaul#define BGE_SBDI_LOC_NIC_PROD0 0x1808 78584059Swpaul#define BGE_SBDI_LOC_NIC_PROD1 0x180C 78684059Swpaul#define BGE_SBDI_LOC_NIC_PROD2 0x1810 78784059Swpaul#define BGE_SBDI_LOC_NIC_PROD3 0x1814 78884059Swpaul#define BGE_SBDI_LOC_NIC_PROD4 0x1818 78984059Swpaul#define BGE_SBDI_LOC_NIC_PROD5 0x181C 79084059Swpaul#define BGE_SBDI_LOC_NIC_PROD6 0x1820 79184059Swpaul#define BGE_SBDI_LOC_NIC_PROD7 0x1824 79284059Swpaul#define BGE_SBDI_LOC_NIC_PROD8 0x1828 79384059Swpaul#define BGE_SBDI_LOC_NIC_PROD9 0x182C 79484059Swpaul#define BGE_SBDI_LOC_NIC_PROD10 0x1830 79584059Swpaul#define BGE_SBDI_LOC_NIC_PROD11 0x1834 79684059Swpaul#define BGE_SBDI_LOC_NIC_PROD12 0x1838 79784059Swpaul#define BGE_SBDI_LOC_NIC_PROD13 0x183C 79884059Swpaul#define BGE_SBDI_LOC_NIC_PROD14 0x1840 79984059Swpaul#define BGE_SBDI_LOC_NIC_PROD15 0x1844 80084059Swpaul 80184059Swpaul/* Send BD Initiator Mode register */ 80284059Swpaul#define BGE_SBDIMODE_RESET 0x00000001 80384059Swpaul#define BGE_SBDIMODE_ENABLE 0x00000002 80484059Swpaul#define BGE_SBDIMODE_ATTN 0x00000004 80584059Swpaul 80684059Swpaul/* Send BD Initiator Status register */ 80784059Swpaul#define BGE_SBDISTAT_ERROR 0x00000004 80884059Swpaul 80984059Swpaul/* 81084059Swpaul * Send BD Completion Control registers 81184059Swpaul */ 81284059Swpaul#define BGE_SBDC_MODE 0x1C00 81384059Swpaul#define BGE_SBDC_STATUS 0x1C04 81484059Swpaul 81584059Swpaul/* Send BD Completion Control Mode register */ 81684059Swpaul#define BGE_SBDCMODE_RESET 0x00000001 81784059Swpaul#define BGE_SBDCMODE_ENABLE 0x00000002 81884059Swpaul#define BGE_SBDCMODE_ATTN 0x00000004 81984059Swpaul 82084059Swpaul/* Send BD Completion Control Status register */ 82184059Swpaul#define BGE_SBDCSTAT_ATTN 0x00000004 82284059Swpaul 82384059Swpaul/* 82484059Swpaul * Receive List Placement Control registers 82584059Swpaul */ 82684059Swpaul#define BGE_RXLP_MODE 0x2000 82784059Swpaul#define BGE_RXLP_STATUS 0x2004 82884059Swpaul#define BGE_RXLP_SEL_LIST_LOCK 0x2008 82984059Swpaul#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 83084059Swpaul#define BGE_RXLP_CFG 0x2010 83184059Swpaul#define BGE_RXLP_STATS_CTL 0x2014 83284059Swpaul#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 83384059Swpaul#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 83484059Swpaul#define BGE_RXLP_HEAD0 0x2100 83584059Swpaul#define BGE_RXLP_TAIL0 0x2104 83684059Swpaul#define BGE_RXLP_COUNT0 0x2108 83784059Swpaul#define BGE_RXLP_HEAD1 0x2110 83884059Swpaul#define BGE_RXLP_TAIL1 0x2114 83984059Swpaul#define BGE_RXLP_COUNT1 0x2118 84084059Swpaul#define BGE_RXLP_HEAD2 0x2120 84184059Swpaul#define BGE_RXLP_TAIL2 0x2124 84284059Swpaul#define BGE_RXLP_COUNT2 0x2128 84384059Swpaul#define BGE_RXLP_HEAD3 0x2130 84484059Swpaul#define BGE_RXLP_TAIL3 0x2134 84584059Swpaul#define BGE_RXLP_COUNT3 0x2138 84684059Swpaul#define BGE_RXLP_HEAD4 0x2140 84784059Swpaul#define BGE_RXLP_TAIL4 0x2144 84884059Swpaul#define BGE_RXLP_COUNT4 0x2148 84984059Swpaul#define BGE_RXLP_HEAD5 0x2150 85084059Swpaul#define BGE_RXLP_TAIL5 0x2154 85184059Swpaul#define BGE_RXLP_COUNT5 0x2158 85284059Swpaul#define BGE_RXLP_HEAD6 0x2160 85384059Swpaul#define BGE_RXLP_TAIL6 0x2164 85484059Swpaul#define BGE_RXLP_COUNT6 0x2168 85584059Swpaul#define BGE_RXLP_HEAD7 0x2170 85684059Swpaul#define BGE_RXLP_TAIL7 0x2174 85784059Swpaul#define BGE_RXLP_COUNT7 0x2178 85884059Swpaul#define BGE_RXLP_HEAD8 0x2180 85984059Swpaul#define BGE_RXLP_TAIL8 0x2184 86084059Swpaul#define BGE_RXLP_COUNT8 0x2188 86184059Swpaul#define BGE_RXLP_HEAD9 0x2190 86284059Swpaul#define BGE_RXLP_TAIL9 0x2194 86384059Swpaul#define BGE_RXLP_COUNT9 0x2198 86484059Swpaul#define BGE_RXLP_HEAD10 0x21A0 86584059Swpaul#define BGE_RXLP_TAIL10 0x21A4 86684059Swpaul#define BGE_RXLP_COUNT10 0x21A8 86784059Swpaul#define BGE_RXLP_HEAD11 0x21B0 86884059Swpaul#define BGE_RXLP_TAIL11 0x21B4 86984059Swpaul#define BGE_RXLP_COUNT11 0x21B8 87084059Swpaul#define BGE_RXLP_HEAD12 0x21C0 87184059Swpaul#define BGE_RXLP_TAIL12 0x21C4 87284059Swpaul#define BGE_RXLP_COUNT12 0x21C8 87384059Swpaul#define BGE_RXLP_HEAD13 0x21D0 87484059Swpaul#define BGE_RXLP_TAIL13 0x21D4 87584059Swpaul#define BGE_RXLP_COUNT13 0x21D8 87684059Swpaul#define BGE_RXLP_HEAD14 0x21E0 87784059Swpaul#define BGE_RXLP_TAIL14 0x21E4 87884059Swpaul#define BGE_RXLP_COUNT14 0x21E8 87984059Swpaul#define BGE_RXLP_HEAD15 0x21F0 88084059Swpaul#define BGE_RXLP_TAIL15 0x21F4 88184059Swpaul#define BGE_RXLP_COUNT15 0x21F8 88284059Swpaul#define BGE_RXLP_LOCSTAT_COS0 0x2200 88384059Swpaul#define BGE_RXLP_LOCSTAT_COS1 0x2204 88484059Swpaul#define BGE_RXLP_LOCSTAT_COS2 0x2208 88584059Swpaul#define BGE_RXLP_LOCSTAT_COS3 0x220C 88684059Swpaul#define BGE_RXLP_LOCSTAT_COS4 0x2210 88784059Swpaul#define BGE_RXLP_LOCSTAT_COS5 0x2214 88884059Swpaul#define BGE_RXLP_LOCSTAT_COS6 0x2218 88984059Swpaul#define BGE_RXLP_LOCSTAT_COS7 0x221C 89084059Swpaul#define BGE_RXLP_LOCSTAT_COS8 0x2220 89184059Swpaul#define BGE_RXLP_LOCSTAT_COS9 0x2224 89284059Swpaul#define BGE_RXLP_LOCSTAT_COS10 0x2228 89384059Swpaul#define BGE_RXLP_LOCSTAT_COS11 0x222C 89484059Swpaul#define BGE_RXLP_LOCSTAT_COS12 0x2230 89584059Swpaul#define BGE_RXLP_LOCSTAT_COS13 0x2234 89684059Swpaul#define BGE_RXLP_LOCSTAT_COS14 0x2238 89784059Swpaul#define BGE_RXLP_LOCSTAT_COS15 0x223C 89884059Swpaul#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 89984059Swpaul#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 90084059Swpaul#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 90184059Swpaul#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 90284059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 90384059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 90484059Swpaul#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 90584059Swpaul 90684059Swpaul 90784059Swpaul/* Receive List Placement mode register */ 90884059Swpaul#define BGE_RXLPMODE_RESET 0x00000001 90984059Swpaul#define BGE_RXLPMODE_ENABLE 0x00000002 91084059Swpaul#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 91184059Swpaul#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 91284059Swpaul#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 91384059Swpaul 91484059Swpaul/* Receive List Placement Status register */ 91584059Swpaul#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 91684059Swpaul#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 91784059Swpaul#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 91884059Swpaul 91984059Swpaul/* 92084059Swpaul * Receive Data and Receive BD Initiator Control Registers 92184059Swpaul */ 92284059Swpaul#define BGE_RDBDI_MODE 0x2400 92384059Swpaul#define BGE_RDBDI_STATUS 0x2404 92484059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 92584059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 92684059Swpaul#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 92784059Swpaul#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 92884059Swpaul#define BGE_RX_STD_RCB_HADDR_HI 0x2450 92984059Swpaul#define BGE_RX_STD_RCB_HADDR_LO 0x2454 93084059Swpaul#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 93184059Swpaul#define BGE_RX_STD_RCB_NICADDR 0x245C 93284059Swpaul#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 93384059Swpaul#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 93484059Swpaul#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 93584059Swpaul#define BGE_RX_MINI_RCB_NICADDR 0x246C 93684059Swpaul#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 93784059Swpaul#define BGE_RDBDI_STD_RX_CONS 0x2474 93884059Swpaul#define BGE_RDBDI_MINI_RX_CONS 0x2478 93984059Swpaul#define BGE_RDBDI_RETURN_PROD0 0x2480 94084059Swpaul#define BGE_RDBDI_RETURN_PROD1 0x2484 94184059Swpaul#define BGE_RDBDI_RETURN_PROD2 0x2488 94284059Swpaul#define BGE_RDBDI_RETURN_PROD3 0x248C 94384059Swpaul#define BGE_RDBDI_RETURN_PROD4 0x2490 94484059Swpaul#define BGE_RDBDI_RETURN_PROD5 0x2494 94584059Swpaul#define BGE_RDBDI_RETURN_PROD6 0x2498 94684059Swpaul#define BGE_RDBDI_RETURN_PROD7 0x249C 94784059Swpaul#define BGE_RDBDI_RETURN_PROD8 0x24A0 94884059Swpaul#define BGE_RDBDI_RETURN_PROD9 0x24A4 94984059Swpaul#define BGE_RDBDI_RETURN_PROD10 0x24A8 95084059Swpaul#define BGE_RDBDI_RETURN_PROD11 0x24AC 95184059Swpaul#define BGE_RDBDI_RETURN_PROD12 0x24B0 95284059Swpaul#define BGE_RDBDI_RETURN_PROD13 0x24B4 95384059Swpaul#define BGE_RDBDI_RETURN_PROD14 0x24B8 95484059Swpaul#define BGE_RDBDI_RETURN_PROD15 0x24BC 95584059Swpaul#define BGE_RDBDI_HWDIAG 0x24C0 95684059Swpaul 95784059Swpaul 95884059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 95984059Swpaul#define BGE_RDBDIMODE_RESET 0x00000001 96084059Swpaul#define BGE_RDBDIMODE_ENABLE 0x00000002 96184059Swpaul#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 96284059Swpaul#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 96384059Swpaul#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 96484059Swpaul 96584059Swpaul/* Receive Data and Receive BD Initiator Status register */ 96684059Swpaul#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 96784059Swpaul#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 96884059Swpaul#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 96984059Swpaul 97084059Swpaul 97184059Swpaul/* 97284059Swpaul * Receive Data Completion Control registers 97384059Swpaul */ 97484059Swpaul#define BGE_RDC_MODE 0x2800 97584059Swpaul 97684059Swpaul/* Receive Data Completion Mode register */ 97784059Swpaul#define BGE_RDCMODE_RESET 0x00000001 97884059Swpaul#define BGE_RDCMODE_ENABLE 0x00000002 97984059Swpaul#define BGE_RDCMODE_ATTN 0x00000004 98084059Swpaul 98184059Swpaul/* 98284059Swpaul * Receive BD Initiator Control registers 98384059Swpaul */ 98484059Swpaul#define BGE_RBDI_MODE 0x2C00 98584059Swpaul#define BGE_RBDI_STATUS 0x2C04 98684059Swpaul#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 98784059Swpaul#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 98884059Swpaul#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 98984059Swpaul#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 99084059Swpaul#define BGE_RBDI_STD_REPL_THRESH 0x2C18 99184059Swpaul#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 99284059Swpaul 99384059Swpaul/* Receive BD Initiator Mode register */ 99484059Swpaul#define BGE_RBDIMODE_RESET 0x00000001 99584059Swpaul#define BGE_RBDIMODE_ENABLE 0x00000002 99684059Swpaul#define BGE_RBDIMODE_ATTN 0x00000004 99784059Swpaul 99884059Swpaul/* Receive BD Initiator Status register */ 99984059Swpaul#define BGE_RBDISTAT_ATTN 0x00000004 100084059Swpaul 100184059Swpaul/* 100284059Swpaul * Receive BD Completion Control registers 100384059Swpaul */ 100484059Swpaul#define BGE_RBDC_MODE 0x3000 100584059Swpaul#define BGE_RBDC_STATUS 0x3004 100684059Swpaul#define BGE_RBDC_JUMBO_BD_PROD 0x3008 100784059Swpaul#define BGE_RBDC_STD_BD_PROD 0x300C 100884059Swpaul#define BGE_RBDC_MINI_BD_PROD 0x3010 100984059Swpaul 101084059Swpaul/* Receive BD completion mode register */ 101184059Swpaul#define BGE_RBDCMODE_RESET 0x00000001 101284059Swpaul#define BGE_RBDCMODE_ENABLE 0x00000002 101384059Swpaul#define BGE_RBDCMODE_ATTN 0x00000004 101484059Swpaul 101584059Swpaul/* Receive BD completion status register */ 101684059Swpaul#define BGE_RBDCSTAT_ERROR 0x00000004 101784059Swpaul 101884059Swpaul/* 101984059Swpaul * Receive List Selector Control registers 102084059Swpaul */ 102184059Swpaul#define BGE_RXLS_MODE 0x3400 102284059Swpaul#define BGE_RXLS_STATUS 0x3404 102384059Swpaul 102484059Swpaul/* Receive List Selector Mode register */ 102584059Swpaul#define BGE_RXLSMODE_RESET 0x00000001 102684059Swpaul#define BGE_RXLSMODE_ENABLE 0x00000002 102784059Swpaul#define BGE_RXLSMODE_ATTN 0x00000004 102884059Swpaul 102984059Swpaul/* Receive List Selector Status register */ 103084059Swpaul#define BGE_RXLSSTAT_ERROR 0x00000004 103184059Swpaul 103284059Swpaul/* 103384059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 103484059Swpaul */ 103584059Swpaul#define BGE_MBCF_MODE 0x3800 103684059Swpaul#define BGE_MBCF_STATUS 0x3804 103784059Swpaul 103884059Swpaul/* Mbuf Cluster Free mode register */ 103984059Swpaul#define BGE_MBCFMODE_RESET 0x00000001 104084059Swpaul#define BGE_MBCFMODE_ENABLE 0x00000002 104184059Swpaul#define BGE_MBCFMODE_ATTN 0x00000004 104284059Swpaul 104384059Swpaul/* Mbuf Cluster Free status register */ 104484059Swpaul#define BGE_MBCFSTAT_ERROR 0x00000004 104584059Swpaul 104684059Swpaul/* 104784059Swpaul * Host Coalescing Control registers 104884059Swpaul */ 104984059Swpaul#define BGE_HCC_MODE 0x3C00 105084059Swpaul#define BGE_HCC_STATUS 0x3C04 105184059Swpaul#define BGE_HCC_RX_COAL_TICKS 0x3C08 105284059Swpaul#define BGE_HCC_TX_COAL_TICKS 0x3C0C 105384059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 105484059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 105584059Swpaul#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 105684059Swpaul#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 105784059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 105884059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 105984059Swpaul#define BGE_HCC_STATS_TICKS 0x3C28 106084059Swpaul#define BGE_HCC_STATS_ADDR_HI 0x3C30 106184059Swpaul#define BGE_HCC_STATS_ADDR_LO 0x3C34 106284059Swpaul#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 106384059Swpaul#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 106484059Swpaul#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 106584059Swpaul#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 106684059Swpaul#define BGE_FLOW_ATTN 0x3C48 106784059Swpaul#define BGE_HCC_JUMBO_BD_CONS 0x3C50 106884059Swpaul#define BGE_HCC_STD_BD_CONS 0x3C54 106984059Swpaul#define BGE_HCC_MINI_BD_CONS 0x3C58 107084059Swpaul#define BGE_HCC_RX_RETURN_PROD0 0x3C80 107184059Swpaul#define BGE_HCC_RX_RETURN_PROD1 0x3C84 107284059Swpaul#define BGE_HCC_RX_RETURN_PROD2 0x3C88 107384059Swpaul#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 107484059Swpaul#define BGE_HCC_RX_RETURN_PROD4 0x3C90 107584059Swpaul#define BGE_HCC_RX_RETURN_PROD5 0x3C94 107684059Swpaul#define BGE_HCC_RX_RETURN_PROD6 0x3C98 107784059Swpaul#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 107884059Swpaul#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 107984059Swpaul#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 108084059Swpaul#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 108184059Swpaul#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 108284059Swpaul#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 108384059Swpaul#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 108484059Swpaul#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 108584059Swpaul#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 108684059Swpaul#define BGE_HCC_TX_BD_CONS0 0x3CC0 108784059Swpaul#define BGE_HCC_TX_BD_CONS1 0x3CC4 108884059Swpaul#define BGE_HCC_TX_BD_CONS2 0x3CC8 108984059Swpaul#define BGE_HCC_TX_BD_CONS3 0x3CCC 109084059Swpaul#define BGE_HCC_TX_BD_CONS4 0x3CD0 109184059Swpaul#define BGE_HCC_TX_BD_CONS5 0x3CD4 109284059Swpaul#define BGE_HCC_TX_BD_CONS6 0x3CD8 109384059Swpaul#define BGE_HCC_TX_BD_CONS7 0x3CDC 109484059Swpaul#define BGE_HCC_TX_BD_CONS8 0x3CE0 109584059Swpaul#define BGE_HCC_TX_BD_CONS9 0x3CE4 109684059Swpaul#define BGE_HCC_TX_BD_CONS10 0x3CE8 109784059Swpaul#define BGE_HCC_TX_BD_CONS11 0x3CEC 109884059Swpaul#define BGE_HCC_TX_BD_CONS12 0x3CF0 109984059Swpaul#define BGE_HCC_TX_BD_CONS13 0x3CF4 110084059Swpaul#define BGE_HCC_TX_BD_CONS14 0x3CF8 110184059Swpaul#define BGE_HCC_TX_BD_CONS15 0x3CFC 110284059Swpaul 110384059Swpaul 110484059Swpaul/* Host coalescing mode register */ 110584059Swpaul#define BGE_HCCMODE_RESET 0x00000001 110684059Swpaul#define BGE_HCCMODE_ENABLE 0x00000002 110784059Swpaul#define BGE_HCCMODE_ATTN 0x00000004 110884059Swpaul#define BGE_HCCMODE_COAL_NOW 0x00000008 110984059Swpaul#define BGE_HCCMODE_MSI_BITS 0x0x000070 111084059Swpaul#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 111184059Swpaul 111284059Swpaul#define BGE_STATBLKSZ_FULL 0x00000000 111384059Swpaul#define BGE_STATBLKSZ_64BYTE 0x00000080 111484059Swpaul#define BGE_STATBLKSZ_32BYTE 0x00000100 111584059Swpaul 111684059Swpaul/* Host coalescing status register */ 111784059Swpaul#define BGE_HCCSTAT_ERROR 0x00000004 111884059Swpaul 111984059Swpaul/* Flow attention register */ 112084059Swpaul#define BGE_FLOWATTN_MB_LOWAT 0x00000040 112184059Swpaul#define BGE_FLOWATTN_MEMARB 0x00000080 112284059Swpaul#define BGE_FLOWATTN_HOSTCOAL 0x00008000 112384059Swpaul#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 112484059Swpaul#define BGE_FLOWATTN_RCB_INVAL 0x00020000 112584059Swpaul#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 112684059Swpaul#define BGE_FLOWATTN_RDBDI 0x00080000 112784059Swpaul#define BGE_FLOWATTN_RXLS 0x00100000 112884059Swpaul#define BGE_FLOWATTN_RXLP 0x00200000 112984059Swpaul#define BGE_FLOWATTN_RBDC 0x00400000 113084059Swpaul#define BGE_FLOWATTN_RBDI 0x00800000 113184059Swpaul#define BGE_FLOWATTN_SDC 0x08000000 113284059Swpaul#define BGE_FLOWATTN_SDI 0x10000000 113384059Swpaul#define BGE_FLOWATTN_SRS 0x20000000 113484059Swpaul#define BGE_FLOWATTN_SBDC 0x40000000 113584059Swpaul#define BGE_FLOWATTN_SBDI 0x80000000 113684059Swpaul 113784059Swpaul/* 113884059Swpaul * Memory arbiter registers 113984059Swpaul */ 114084059Swpaul#define BGE_MARB_MODE 0x4000 114184059Swpaul#define BGE_MARB_STATUS 0x4004 114284059Swpaul#define BGE_MARB_TRAPADDR_HI 0x4008 114384059Swpaul#define BGE_MARB_TRAPADDR_LO 0x400C 114484059Swpaul 114584059Swpaul/* Memory arbiter mode register */ 114684059Swpaul#define BGE_MARBMODE_RESET 0x00000001 114784059Swpaul#define BGE_MARBMODE_ENABLE 0x00000002 114884059Swpaul#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 114984059Swpaul#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 115084059Swpaul#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 115184059Swpaul#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 115284059Swpaul#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 115384059Swpaul#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 115484059Swpaul#define BGE_MARBMODE_PCI_TRAP 0x00000100 115584059Swpaul#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 115684059Swpaul#define BGE_MARBMODE_RXQ_TRAP 0x00000400 115784059Swpaul#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 115884059Swpaul#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 115984059Swpaul#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 116084059Swpaul#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 116184059Swpaul#define BGE_MARBMODE_MBUF_TRAP 0x00008000 116284059Swpaul#define BGE_MARBMODE_TXDI_TRAP 0x00010000 116384059Swpaul#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 116484059Swpaul#define BGE_MARBMODE_TXBD_TRAP 0x00040000 116584059Swpaul#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 116684059Swpaul#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 116784059Swpaul#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 116884059Swpaul#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 116984059Swpaul#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 117084059Swpaul#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 117184059Swpaul#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 117284059Swpaul 117384059Swpaul/* Memory arbiter status register */ 117484059Swpaul#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 117584059Swpaul#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 117684059Swpaul#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 117784059Swpaul#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 117884059Swpaul#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 117984059Swpaul#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 118084059Swpaul#define BGE_MARBSTAT_PCI_TRAP 0x00000100 118184059Swpaul#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 118284059Swpaul#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 118384059Swpaul#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 118484059Swpaul#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 118584059Swpaul#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 118684059Swpaul#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 118784059Swpaul#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 118884059Swpaul#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 118984059Swpaul#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 119084059Swpaul#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 119184059Swpaul#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 119284059Swpaul#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 119384059Swpaul#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 119484059Swpaul#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 119584059Swpaul#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 119684059Swpaul#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 119784059Swpaul#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 119884059Swpaul 119984059Swpaul/* 120084059Swpaul * Buffer manager control registers 120184059Swpaul */ 120284059Swpaul#define BGE_BMAN_MODE 0x4400 120384059Swpaul#define BGE_BMAN_STATUS 0x4404 120484059Swpaul#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 120584059Swpaul#define BGE_BMAN_MBUFPOOL_LEN 0x440C 120684059Swpaul#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 120784059Swpaul#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 120884059Swpaul#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 120984059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 121084059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 121184059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 121284059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 121384059Swpaul#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 121484059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 121584059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 121684059Swpaul#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 121784059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 121884059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 121984059Swpaul#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 122084059Swpaul#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 122184059Swpaul#define BGE_BMAN_HWDIAG_1 0x444C 122284059Swpaul#define BGE_BMAN_HWDIAG_2 0x4450 122384059Swpaul#define BGE_BMAN_HWDIAG_3 0x4454 122484059Swpaul 122584059Swpaul/* Buffer manager mode register */ 122684059Swpaul#define BGE_BMANMODE_RESET 0x00000001 122784059Swpaul#define BGE_BMANMODE_ENABLE 0x00000002 122884059Swpaul#define BGE_BMANMODE_ATTN 0x00000004 122984059Swpaul#define BGE_BMANMODE_TESTMODE 0x00000008 123084059Swpaul#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 123184059Swpaul 123284059Swpaul/* Buffer manager status register */ 123384059Swpaul#define BGE_BMANSTAT_ERRO 0x00000004 123484059Swpaul#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 123584059Swpaul 123684059Swpaul 123784059Swpaul/* 123884059Swpaul * Read DMA Control registers 123984059Swpaul */ 124084059Swpaul#define BGE_RDMA_MODE 0x4800 124184059Swpaul#define BGE_RDMA_STATUS 0x4804 124284059Swpaul 124384059Swpaul/* Read DMA mode register */ 124484059Swpaul#define BGE_RDMAMODE_RESET 0x00000001 124584059Swpaul#define BGE_RDMAMODE_ENABLE 0x00000002 124684059Swpaul#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 124784059Swpaul#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 124884059Swpaul#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 124984059Swpaul#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 125084059Swpaul#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 125184059Swpaul#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 125284059Swpaul#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 125384059Swpaul#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 125484059Swpaul#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 125584059Swpaul 125684059Swpaul/* Read DMA status register */ 125784059Swpaul#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 125884059Swpaul#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 125984059Swpaul#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 126084059Swpaul#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 126184059Swpaul#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 126284059Swpaul#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 126384059Swpaul#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 126484059Swpaul#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 126584059Swpaul 126684059Swpaul/* 126784059Swpaul * Write DMA control registers 126884059Swpaul */ 126984059Swpaul#define BGE_WDMA_MODE 0x4C00 127084059Swpaul#define BGE_WDMA_STATUS 0x4C04 127184059Swpaul 127284059Swpaul/* Write DMA mode register */ 127384059Swpaul#define BGE_WDMAMODE_RESET 0x00000001 127484059Swpaul#define BGE_WDMAMODE_ENABLE 0x00000002 127584059Swpaul#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 127684059Swpaul#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 127784059Swpaul#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 127884059Swpaul#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 127984059Swpaul#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 128084059Swpaul#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 128184059Swpaul#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 128284059Swpaul#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 128384059Swpaul#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 128484059Swpaul 128584059Swpaul/* Write DMA status register */ 128684059Swpaul#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 128784059Swpaul#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 128884059Swpaul#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 128984059Swpaul#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 129084059Swpaul#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 129184059Swpaul#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 129284059Swpaul#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 129384059Swpaul#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 129484059Swpaul 129584059Swpaul 129684059Swpaul/* 129784059Swpaul * RX CPU registers 129884059Swpaul */ 129984059Swpaul#define BGE_RXCPU_MODE 0x5000 130084059Swpaul#define BGE_RXCPU_STATUS 0x5004 130184059Swpaul#define BGE_RXCPU_PC 0x501C 130284059Swpaul 130384059Swpaul/* RX CPU mode register */ 130484059Swpaul#define BGE_RXCPUMODE_RESET 0x00000001 130584059Swpaul#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 130684059Swpaul#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 130784059Swpaul#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 130884059Swpaul#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 130984059Swpaul#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 131084059Swpaul#define BGE_RXCPUMODE_ROMFAIL 0x00000040 131184059Swpaul#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 131284059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 131384059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 131484059Swpaul#define BGE_RXCPUMODE_HALTCPU 0x00000400 131584059Swpaul#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 131684059Swpaul#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 131784059Swpaul#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 131884059Swpaul 131984059Swpaul/* RX CPU status register */ 132084059Swpaul#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 132184059Swpaul#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 132284059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 132384059Swpaul#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 132484059Swpaul#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 132584059Swpaul#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 132684059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 132784059Swpaul#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 132884059Swpaul#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 132984059Swpaul#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 133084059Swpaul#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 133184059Swpaul#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 133284059Swpaul#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 133384059Swpaul#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 133484059Swpaul#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 133584059Swpaul#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 133684059Swpaul#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 133784059Swpaul 133884059Swpaul 133984059Swpaul/* 134084059Swpaul * TX CPU registers 134184059Swpaul */ 134284059Swpaul#define BGE_TXCPU_MODE 0x5400 134384059Swpaul#define BGE_TXCPU_STATUS 0x5404 134484059Swpaul#define BGE_TXCPU_PC 0x541C 134584059Swpaul 134684059Swpaul/* TX CPU mode register */ 134784059Swpaul#define BGE_TXCPUMODE_RESET 0x00000001 134884059Swpaul#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 134984059Swpaul#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 135084059Swpaul#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 135184059Swpaul#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 135284059Swpaul#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 135384059Swpaul#define BGE_TXCPUMODE_ROMFAIL 0x00000040 135484059Swpaul#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 135584059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 135684059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 135784059Swpaul#define BGE_TXCPUMODE_HALTCPU 0x00000400 135884059Swpaul#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 135984059Swpaul#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 136084059Swpaul 136184059Swpaul/* TX CPU status register */ 136284059Swpaul#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 136384059Swpaul#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 136484059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 136584059Swpaul#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 136684059Swpaul#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 136784059Swpaul#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 136884059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 136984059Swpaul#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 137084059Swpaul#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 137184059Swpaul#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 137284059Swpaul#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 137384059Swpaul#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 137484059Swpaul#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 137584059Swpaul#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 137684059Swpaul#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 137784059Swpaul#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 137884059Swpaul#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 137984059Swpaul 138084059Swpaul 138184059Swpaul/* 138284059Swpaul * Low priority mailbox registers 138384059Swpaul */ 138484059Swpaul#define BGE_LPMBX_IRQ0_HI 0x5800 138584059Swpaul#define BGE_LPMBX_IRQ0_LO 0x5804 138684059Swpaul#define BGE_LPMBX_IRQ1_HI 0x5808 138784059Swpaul#define BGE_LPMBX_IRQ1_LO 0x580C 138884059Swpaul#define BGE_LPMBX_IRQ2_HI 0x5810 138984059Swpaul#define BGE_LPMBX_IRQ2_LO 0x5814 139084059Swpaul#define BGE_LPMBX_IRQ3_HI 0x5818 139184059Swpaul#define BGE_LPMBX_IRQ3_LO 0x581C 139284059Swpaul#define BGE_LPMBX_GEN0_HI 0x5820 139384059Swpaul#define BGE_LPMBX_GEN0_LO 0x5824 139484059Swpaul#define BGE_LPMBX_GEN1_HI 0x5828 139584059Swpaul#define BGE_LPMBX_GEN1_LO 0x582C 139684059Swpaul#define BGE_LPMBX_GEN2_HI 0x5830 139784059Swpaul#define BGE_LPMBX_GEN2_LO 0x5834 139884059Swpaul#define BGE_LPMBX_GEN3_HI 0x5828 139984059Swpaul#define BGE_LPMBX_GEN3_LO 0x582C 140084059Swpaul#define BGE_LPMBX_GEN4_HI 0x5840 140184059Swpaul#define BGE_LPMBX_GEN4_LO 0x5844 140284059Swpaul#define BGE_LPMBX_GEN5_HI 0x5848 140384059Swpaul#define BGE_LPMBX_GEN5_LO 0x584C 140484059Swpaul#define BGE_LPMBX_GEN6_HI 0x5850 140584059Swpaul#define BGE_LPMBX_GEN6_LO 0x5854 140684059Swpaul#define BGE_LPMBX_GEN7_HI 0x5858 140784059Swpaul#define BGE_LPMBX_GEN7_LO 0x585C 140884059Swpaul#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 140984059Swpaul#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 141084059Swpaul#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 141184059Swpaul#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 141284059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 141384059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 141484059Swpaul#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 141584059Swpaul#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 141684059Swpaul#define BGE_LPMBX_RX_CONS0_HI 0x5880 141784059Swpaul#define BGE_LPMBX_RX_CONS0_LO 0x5884 141884059Swpaul#define BGE_LPMBX_RX_CONS1_HI 0x5888 141984059Swpaul#define BGE_LPMBX_RX_CONS1_LO 0x588C 142084059Swpaul#define BGE_LPMBX_RX_CONS2_HI 0x5890 142184059Swpaul#define BGE_LPMBX_RX_CONS2_LO 0x5894 142284059Swpaul#define BGE_LPMBX_RX_CONS3_HI 0x5898 142384059Swpaul#define BGE_LPMBX_RX_CONS3_LO 0x589C 142484059Swpaul#define BGE_LPMBX_RX_CONS4_HI 0x58A0 142584059Swpaul#define BGE_LPMBX_RX_CONS4_LO 0x58A4 142684059Swpaul#define BGE_LPMBX_RX_CONS5_HI 0x58A8 142784059Swpaul#define BGE_LPMBX_RX_CONS5_LO 0x58AC 142884059Swpaul#define BGE_LPMBX_RX_CONS6_HI 0x58B0 142984059Swpaul#define BGE_LPMBX_RX_CONS6_LO 0x58B4 143084059Swpaul#define BGE_LPMBX_RX_CONS7_HI 0x58B8 143184059Swpaul#define BGE_LPMBX_RX_CONS7_LO 0x58BC 143284059Swpaul#define BGE_LPMBX_RX_CONS8_HI 0x58C0 143384059Swpaul#define BGE_LPMBX_RX_CONS8_LO 0x58C4 143484059Swpaul#define BGE_LPMBX_RX_CONS9_HI 0x58C8 143584059Swpaul#define BGE_LPMBX_RX_CONS9_LO 0x58CC 143684059Swpaul#define BGE_LPMBX_RX_CONS10_HI 0x58D0 143784059Swpaul#define BGE_LPMBX_RX_CONS10_LO 0x58D4 143884059Swpaul#define BGE_LPMBX_RX_CONS11_HI 0x58D8 143984059Swpaul#define BGE_LPMBX_RX_CONS11_LO 0x58DC 144084059Swpaul#define BGE_LPMBX_RX_CONS12_HI 0x58E0 144184059Swpaul#define BGE_LPMBX_RX_CONS12_LO 0x58E4 144284059Swpaul#define BGE_LPMBX_RX_CONS13_HI 0x58E8 144384059Swpaul#define BGE_LPMBX_RX_CONS13_LO 0x58EC 144484059Swpaul#define BGE_LPMBX_RX_CONS14_HI 0x58F0 144584059Swpaul#define BGE_LPMBX_RX_CONS14_LO 0x58F4 144684059Swpaul#define BGE_LPMBX_RX_CONS15_HI 0x58F8 144784059Swpaul#define BGE_LPMBX_RX_CONS15_LO 0x58FC 144884059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 144984059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 145084059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 145184059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 145284059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 145384059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 145484059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 145584059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 145684059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 145784059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 145884059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 145984059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 146084059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 146184059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 146284059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 146384059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 146484059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 146584059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 146684059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 146784059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 146884059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 146984059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 147084059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 147184059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 147284059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 147384059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 147484059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 147584059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 147684059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 147784059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 147884059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 147984059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 148084059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 148184059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 148284059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 148384059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 148484059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 148584059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 148684059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 148784059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 148884059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 148984059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 149084059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 149184059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 149284059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 149384059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 149484059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 149584059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 149684059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 149784059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 149884059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 149984059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 150084059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 150184059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 150284059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 150384059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 150484059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 150584059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 150684059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 150784059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 150884059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 150984059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 151084059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 151184059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 151284059Swpaul 151384059Swpaul/* 151484059Swpaul * Flow throw Queue reset register 151584059Swpaul */ 151684059Swpaul#define BGE_FTQ_RESET 0x5C00 151784059Swpaul 151884059Swpaul#define BGE_FTQRESET_DMAREAD 0x00000002 151984059Swpaul#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 152084059Swpaul#define BGE_FTQRESET_DMADONE 0x00000010 152184059Swpaul#define BGE_FTQRESET_SBDC 0x00000020 152284059Swpaul#define BGE_FTQRESET_SDI 0x00000040 152384059Swpaul#define BGE_FTQRESET_WDMA 0x00000080 152484059Swpaul#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 152584059Swpaul#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 152684059Swpaul#define BGE_FTQRESET_SDC 0x00000400 152784059Swpaul#define BGE_FTQRESET_HCC 0x00000800 152884059Swpaul#define BGE_FTQRESET_TXFIFO 0x00001000 152984059Swpaul#define BGE_FTQRESET_MBC 0x00002000 153084059Swpaul#define BGE_FTQRESET_RBDC 0x00004000 153184059Swpaul#define BGE_FTQRESET_RXLP 0x00008000 153284059Swpaul#define BGE_FTQRESET_RDBDI 0x00010000 153384059Swpaul#define BGE_FTQRESET_RDC 0x00020000 153484059Swpaul#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 153584059Swpaul 153684059Swpaul/* 153784059Swpaul * Message Signaled Interrupt registers 153884059Swpaul */ 153984059Swpaul#define BGE_MSI_MODE 0x6000 154084059Swpaul#define BGE_MSI_STATUS 0x6004 154184059Swpaul#define BGE_MSI_FIFOACCESS 0x6008 154284059Swpaul 154384059Swpaul/* MSI mode register */ 154484059Swpaul#define BGE_MSIMODE_RESET 0x00000001 154584059Swpaul#define BGE_MSIMODE_ENABLE 0x00000002 154684059Swpaul#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 154784059Swpaul#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 154884059Swpaul#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 154984059Swpaul#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 155084059Swpaul#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 155184059Swpaul 155284059Swpaul/* MSI status register */ 155384059Swpaul#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 155484059Swpaul#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 155584059Swpaul#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 155684059Swpaul#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 155784059Swpaul#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 155884059Swpaul 155984059Swpaul 156084059Swpaul/* 156184059Swpaul * DMA Completion registers 156284059Swpaul */ 156384059Swpaul#define BGE_DMAC_MODE 0x6400 156484059Swpaul 156584059Swpaul/* DMA Completion mode register */ 156684059Swpaul#define BGE_DMACMODE_RESET 0x00000001 156784059Swpaul#define BGE_DMACMODE_ENABLE 0x00000002 156884059Swpaul 156984059Swpaul 157084059Swpaul/* 157184059Swpaul * General control registers. 157284059Swpaul */ 157384059Swpaul#define BGE_MODE_CTL 0x6800 157484059Swpaul#define BGE_MISC_CFG 0x6804 157584059Swpaul#define BGE_MISC_LOCAL_CTL 0x6808 157684059Swpaul#define BGE_EE_ADDR 0x6838 157784059Swpaul#define BGE_EE_DATA 0x683C 157884059Swpaul#define BGE_EE_CTL 0x6840 157984059Swpaul#define BGE_MDI_CTL 0x6844 158084059Swpaul#define BGE_EE_DELAY 0x6848 158184059Swpaul 158284059Swpaul/* Mode control register */ 158384059Swpaul#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 158484059Swpaul#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 158584059Swpaul#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 158684059Swpaul#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 158784059Swpaul#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 158884059Swpaul#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 158984059Swpaul#define BGE_MODECTL_NO_RX_CRC 0x00000400 159084059Swpaul#define BGE_MODECTL_RX_BADFRAMES 0x00000800 159184059Swpaul#define BGE_MODECTL_NO_TX_INTR 0x00002000 159284059Swpaul#define BGE_MODECTL_NO_RX_INTR 0x00004000 159384059Swpaul#define BGE_MODECTL_FORCE_PCI32 0x00008000 159484059Swpaul#define BGE_MODECTL_STACKUP 0x00010000 159584059Swpaul#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 159684059Swpaul#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 159784059Swpaul#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 159884059Swpaul#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 159984059Swpaul#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 160084059Swpaul#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 160184059Swpaul#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 160284059Swpaul#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 160384059Swpaul#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 160484059Swpaul#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 160584059Swpaul 160684059Swpaul/* Misc. config register */ 160784059Swpaul#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 160884059Swpaul#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 160984059Swpaul 161084059Swpaul#define BGE_32BITTIME_66MHZ (0x41 << 1) 161184059Swpaul 161284059Swpaul/* Misc. Local Control */ 161384059Swpaul#define BGE_MLC_INTR_STATE 0x00000001 161484059Swpaul#define BGE_MLC_INTR_CLR 0x00000002 161584059Swpaul#define BGE_MLC_INTR_SET 0x00000004 161684059Swpaul#define BGE_MLC_INTR_ONATTN 0x00000008 161784059Swpaul#define BGE_MLC_MISCIO_IN0 0x00000100 161884059Swpaul#define BGE_MLC_MISCIO_IN1 0x00000200 161984059Swpaul#define BGE_MLC_MISCIO_IN2 0x00000400 162084059Swpaul#define BGE_MLC_MISCIO_OUTEN0 0x00000800 162184059Swpaul#define BGE_MLC_MISCIO_OUTEN1 0x00001000 162284059Swpaul#define BGE_MLC_MISCIO_OUTEN2 0x00002000 162384059Swpaul#define BGE_MLC_MISCIO_OUT0 0x00004000 162484059Swpaul#define BGE_MLC_MISCIO_OUT1 0x00008000 162584059Swpaul#define BGE_MLC_MISCIO_OUT2 0x00010000 162684059Swpaul#define BGE_MLC_EXTRAM_ENB 0x00020000 162784059Swpaul#define BGE_MLC_SRAM_SIZE 0x001C0000 162884059Swpaul#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 162984059Swpaul#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 163084059Swpaul#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 163184059Swpaul#define BGE_MLC_AUTO_EEPROM 0x01000000 163284059Swpaul 163384059Swpaul#define BGE_SSRAMSIZE_256KB 0x00000000 163484059Swpaul#define BGE_SSRAMSIZE_512KB 0x00040000 163584059Swpaul#define BGE_SSRAMSIZE_1MB 0x00080000 163684059Swpaul#define BGE_SSRAMSIZE_2MB 0x000C0000 163784059Swpaul#define BGE_SSRAMSIZE_4MB 0x00100000 163884059Swpaul#define BGE_SSRAMSIZE_8MB 0x00140000 163984059Swpaul#define BGE_SSRAMSIZE_16M 0x00180000 164084059Swpaul 164184059Swpaul/* EEPROM address register */ 164284059Swpaul#define BGE_EEADDR_ADDRESS 0x0000FFFC 164384059Swpaul#define BGE_EEADDR_HALFCLK 0x01FF0000 164484059Swpaul#define BGE_EEADDR_START 0x02000000 164584059Swpaul#define BGE_EEADDR_DEVID 0x1C000000 164684059Swpaul#define BGE_EEADDR_RESET 0x20000000 164784059Swpaul#define BGE_EEADDR_DONE 0x40000000 164884059Swpaul#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 164984059Swpaul 165084059Swpaul#define BGE_EEDEVID(x) ((x & 7) << 26) 165184059Swpaul#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 165284059Swpaul#define BGE_HALFCLK_384SCL 0x60 165384059Swpaul#define BGE_EE_READCMD \ 165484059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 165584059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 165684059Swpaul#define BGE_EE_WRCMD \ 165784059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 165884059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 165984059Swpaul 166084059Swpaul/* EEPROM Control register */ 166184059Swpaul#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 166284059Swpaul#define BGE_EECTL_CLKOUT 0x00000002 166384059Swpaul#define BGE_EECTL_CLKIN 0x00000004 166484059Swpaul#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 166584059Swpaul#define BGE_EECTL_DATAOUT 0x00000010 166684059Swpaul#define BGE_EECTL_DATAIN 0x00000020 166784059Swpaul 166884059Swpaul/* MDI (MII/GMII) access register */ 166984059Swpaul#define BGE_MDI_DATA 0x00000001 167084059Swpaul#define BGE_MDI_DIR 0x00000002 167184059Swpaul#define BGE_MDI_SEL 0x00000004 167284059Swpaul#define BGE_MDI_CLK 0x00000008 167384059Swpaul 167484059Swpaul#define BGE_MEMWIN_START 0x00008000 167584059Swpaul#define BGE_MEMWIN_END 0x0000FFFF 167684059Swpaul 167784059Swpaul 167884059Swpaul#define BGE_MEMWIN_READ(sc, x, val) \ 167984059Swpaul do { \ 168084059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 168184059Swpaul (0xFFFF0000 & x), 4); \ 168284059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 168384059Swpaul } while(0) 168484059Swpaul 168584059Swpaul#define BGE_MEMWIN_WRITE(sc, x, val) \ 168684059Swpaul do { \ 168784059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 168884059Swpaul (0xFFFF0000 & x), 4); \ 168984059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 169084059Swpaul } while(0) 169184059Swpaul 169284059Swpaul/* 169384059Swpaul * This magic number is used to prevent PXE restart when we 169484059Swpaul * issue a software reset. We write this magic number to the 169584059Swpaul * firmware mailbox at 0xB50 in order to prevent the PXE boot 169684059Swpaul * code from running. 169784059Swpaul */ 169884059Swpaul#define BGE_MAGIC_NUMBER 0x4B657654 169984059Swpaul 170084059Swpaultypedef struct { 170184059Swpaul u_int32_t bge_addr_hi; 170284059Swpaul u_int32_t bge_addr_lo; 170384059Swpaul} bge_hostaddr; 1704118026Swpaul 1705115200Sps#define BGE_HOSTADDR(x, y) \ 1706115200Sps do { \ 1707115200Sps (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1708115200Sps (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1709115200Sps } while(0) 171084059Swpaul 1711118026Swpaul#define BGE_ADDR_LO(y) \ 1712118026Swpaul ((u_int64_t) (y) & 0xFFFFFFFF) 1713118026Swpaul#define BGE_ADDR_HI(y) \ 1714118026Swpaul ((u_int64_t) (y) >> 32) 1715118026Swpaul 171684059Swpaul/* Ring control block structure */ 171784059Swpaulstruct bge_rcb { 171884059Swpaul bge_hostaddr bge_hostaddr; 1719108847Sjdp u_int32_t bge_maxlen_flags; 172084059Swpaul u_int32_t bge_nicaddr; 172184059Swpaul}; 1722108847Sjdp#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 172384059Swpaul 172484059Swpaul#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 172584059Swpaul#define BGE_RCB_FLAG_RING_DISABLED 0x0002 172684059Swpaul 172784059Swpaulstruct bge_tx_bd { 172884059Swpaul bge_hostaddr bge_addr; 172984059Swpaul u_int16_t bge_flags; 173084059Swpaul u_int16_t bge_len; 173184059Swpaul u_int16_t bge_vlan_tag; 173284059Swpaul u_int16_t bge_rsvd; 173384059Swpaul}; 173484059Swpaul 173584059Swpaul#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 173684059Swpaul#define BGE_TXBDFLAG_IP_CSUM 0x0002 173784059Swpaul#define BGE_TXBDFLAG_END 0x0004 173884059Swpaul#define BGE_TXBDFLAG_IP_FRAG 0x0008 173984059Swpaul#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 174084059Swpaul#define BGE_TXBDFLAG_VLAN_TAG 0x0040 174184059Swpaul#define BGE_TXBDFLAG_COAL_NOW 0x0080 174284059Swpaul#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 174384059Swpaul#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 174484059Swpaul#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 174584059Swpaul#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 174684059Swpaul#define BGE_TXBDFLAG_NO_CRC 0x8000 174784059Swpaul 174884059Swpaul#define BGE_NIC_TXRING_ADDR(ringno, size) \ 174984059Swpaul BGE_SEND_RING_1_TO_4 + \ 175084059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 175184059Swpaul 175284059Swpaulstruct bge_rx_bd { 175384059Swpaul bge_hostaddr bge_addr; 175484059Swpaul u_int16_t bge_len; 175584059Swpaul u_int16_t bge_idx; 175684059Swpaul u_int16_t bge_flags; 175784059Swpaul u_int16_t bge_type; 175884059Swpaul u_int16_t bge_tcp_udp_csum; 175984059Swpaul u_int16_t bge_ip_csum; 176084059Swpaul u_int16_t bge_vlan_tag; 176184059Swpaul u_int16_t bge_error_flag; 176284059Swpaul u_int32_t bge_rsvd; 176384059Swpaul u_int32_t bge_opaque; 176484059Swpaul}; 176584059Swpaul 176684059Swpaul#define BGE_RXBDFLAG_END 0x0004 176784059Swpaul#define BGE_RXBDFLAG_JUMBO_RING 0x0020 176884059Swpaul#define BGE_RXBDFLAG_VLAN_TAG 0x0040 176984059Swpaul#define BGE_RXBDFLAG_ERROR 0x0400 177084059Swpaul#define BGE_RXBDFLAG_MINI_RING 0x0800 177184059Swpaul#define BGE_RXBDFLAG_IP_CSUM 0x1000 177284059Swpaul#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 177384059Swpaul#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 177484059Swpaul 177584059Swpaul#define BGE_RXERRFLAG_BAD_CRC 0x0001 177684059Swpaul#define BGE_RXERRFLAG_COLL_DETECT 0x0002 177784059Swpaul#define BGE_RXERRFLAG_LINK_LOST 0x0004 177884059Swpaul#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 177984059Swpaul#define BGE_RXERRFLAG_MAC_ABORT 0x0010 178084059Swpaul#define BGE_RXERRFLAG_RUNT 0x0020 178184059Swpaul#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 178284059Swpaul#define BGE_RXERRFLAG_GIANT 0x0080 178384059Swpaul 178484059Swpaulstruct bge_sts_idx { 178584059Swpaul u_int16_t bge_rx_prod_idx; 178684059Swpaul u_int16_t bge_tx_cons_idx; 178784059Swpaul}; 178884059Swpaul 178984059Swpaulstruct bge_status_block { 179084059Swpaul u_int32_t bge_status; 179184059Swpaul u_int32_t bge_rsvd0; 179284059Swpaul u_int16_t bge_rx_jumbo_cons_idx; 179384059Swpaul u_int16_t bge_rx_std_cons_idx; 179484059Swpaul u_int16_t bge_rx_mini_cons_idx; 179584059Swpaul u_int16_t bge_rsvd1; 179684059Swpaul struct bge_sts_idx bge_idx[16]; 179784059Swpaul}; 179884059Swpaul 179984059Swpaul#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 180084059Swpaul#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 180184059Swpaul 180284059Swpaul#define BGE_STATFLAG_UPDATED 0x00000001 180384059Swpaul#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 180484059Swpaul#define BGE_STATFLAG_ERROR 0x00000004 180584059Swpaul 180684059Swpaul 180784059Swpaul/* 180884059Swpaul * Broadcom Vendor ID 180984059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 181084059Swpaul * even though they're now manufactured by Broadcom) 181184059Swpaul */ 181284059Swpaul#define BCOM_VENDORID 0x14E4 181384059Swpaul#define BCOM_DEVICEID_BCM5700 0x1644 181484059Swpaul#define BCOM_DEVICEID_BCM5701 0x1645 1815117659Swpaul#define BCOM_DEVICEID_BCM5702 0x16A6 1816117659Swpaul#define BCOM_DEVICEID_BCM5702X 0x16C6 1817117659Swpaul#define BCOM_DEVICEID_BCM5703 0x16A7 1818117659Swpaul#define BCOM_DEVICEID_BCM5703X 0x16C7 1819114547Sps#define BCOM_DEVICEID_BCM5704C 0x1648 1820114547Sps#define BCOM_DEVICEID_BCM5704S 0x16A8 1821117659Swpaul#define BCOM_DEVICEID_BCM5705 0x1653 1822117659Swpaul#define BCOM_DEVICEID_BCM5705M 0x165D 1823117659Swpaul#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1824117659Swpaul#define BCOM_DEVICEID_BCM5782 0x1696 182584059Swpaul 182684059Swpaul/* 182784059Swpaul * Alteon AceNIC PCI vendor/device ID. 182884059Swpaul */ 182984059Swpaul#define ALT_VENDORID 0x12AE 183084059Swpaul#define ALT_DEVICEID_ACENIC 0x0001 183184059Swpaul#define ALT_DEVICEID_ACENIC_COPPER 0x0002 183284059Swpaul#define ALT_DEVICEID_BCM5700 0x0003 183384059Swpaul#define ALT_DEVICEID_BCM5701 0x0004 183484059Swpaul 183584059Swpaul/* 183684059Swpaul * 3Com 3c985 PCI vendor/device ID. 183784059Swpaul */ 183884059Swpaul#define TC_VENDORID 0x10B7 183984059Swpaul#define TC_DEVICEID_3C985 0x0001 184084059Swpaul#define TC_DEVICEID_3C996 0x0003 184184059Swpaul 184284059Swpaul/* 184384059Swpaul * SysKonnect PCI vendor ID 184484059Swpaul */ 184584059Swpaul#define SK_VENDORID 0x1148 184684059Swpaul#define SK_DEVICEID_ALTIMA 0x4400 184784059Swpaul#define SK_SUBSYSID_9D21 0x4421 184884059Swpaul#define SK_SUBSYSID_9D41 0x4441 184984059Swpaul 185084059Swpaul/* 185189835Sjdp * Altima PCI vendor/device ID. 185289835Sjdp */ 185389835Sjdp#define ALTIMA_VENDORID 0x173b 185489835Sjdp#define ALTIMA_DEVICE_AC1000 0x03e8 1855100695Sjdp#define ALTIMA_DEVICE_AC9100 0x03ea 185689835Sjdp 185789835Sjdp/* 185884059Swpaul * Offset of MAC address inside EEPROM. 185984059Swpaul */ 186084059Swpaul#define BGE_EE_MAC_OFFSET 0x7C 186184059Swpaul#define BGE_EE_HWCFG_OFFSET 0xC8 186284059Swpaul 186393751Swpaul#define BGE_HWCFG_VOLTAGE 0x00000003 186493751Swpaul#define BGE_HWCFG_PHYLED_MODE 0x0000000C 186593751Swpaul#define BGE_HWCFG_MEDIA 0x00000030 186693751Swpaul 186793751Swpaul#define BGE_VOLTAGE_1POINT3 0x00000000 186893751Swpaul#define BGE_VOLTAGE_1POINT8 0x00000001 186993751Swpaul 187093751Swpaul#define BGE_PHYLEDMODE_UNSPEC 0x00000000 187193751Swpaul#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 187293751Swpaul#define BGE_PHYLEDMODE_SINGLELED 0x00000008 187393751Swpaul 187493751Swpaul#define BGE_MEDIA_UNSPEC 0x00000000 187593751Swpaul#define BGE_MEDIA_COPPER 0x00000010 187693751Swpaul#define BGE_MEDIA_FIBER 0x00000020 187793751Swpaul 187884059Swpaul#define BGE_PCI_READ_CMD 0x06000000 187984059Swpaul#define BGE_PCI_WRITE_CMD 0x70000000 188084059Swpaul 188184059Swpaul#define BGE_TICKS_PER_SEC 1000000 188284059Swpaul 188384059Swpaul/* 188484059Swpaul * Ring size constants. 188584059Swpaul */ 188684059Swpaul#define BGE_EVENT_RING_CNT 256 188784059Swpaul#define BGE_CMD_RING_CNT 64 188884059Swpaul#define BGE_STD_RX_RING_CNT 512 188984059Swpaul#define BGE_JUMBO_RX_RING_CNT 256 189084059Swpaul#define BGE_MINI_RX_RING_CNT 1024 189184059Swpaul#define BGE_RETURN_RING_CNT 1024 189284059Swpaul 1893117659Swpaul/* 5705 has smaller return ring size */ 1894117659Swpaul 1895117659Swpaul#define BGE_RETURN_RING_CNT_5705 512 1896117659Swpaul 189784059Swpaul/* 189884059Swpaul * Possible TX ring sizes. 189984059Swpaul */ 190084059Swpaul#define BGE_TX_RING_CNT_128 128 190184059Swpaul#define BGE_TX_RING_BASE_128 0x3800 190284059Swpaul 190384059Swpaul#define BGE_TX_RING_CNT_256 256 190484059Swpaul#define BGE_TX_RING_BASE_256 0x3000 190584059Swpaul 190684059Swpaul#define BGE_TX_RING_CNT_512 512 190784059Swpaul#define BGE_TX_RING_BASE_512 0x2000 190884059Swpaul 190984059Swpaul#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 191084059Swpaul#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 191184059Swpaul 191284059Swpaul/* 191384059Swpaul * Tigon III statistics counters. 191484059Swpaul */ 1915117659Swpaul/* Statistics maintained MAC Receive block. */ 1916117659Swpaulstruct bge_rx_mac_stats { 191784059Swpaul bge_hostaddr ifHCInOctets; 191884059Swpaul bge_hostaddr Reserved1; 191984059Swpaul bge_hostaddr etherStatsFragments; 192084059Swpaul bge_hostaddr ifHCInUcastPkts; 192184059Swpaul bge_hostaddr ifHCInMulticastPkts; 192284059Swpaul bge_hostaddr ifHCInBroadcastPkts; 192384059Swpaul bge_hostaddr dot3StatsFCSErrors; 192484059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 192584059Swpaul bge_hostaddr xonPauseFramesReceived; 192684059Swpaul bge_hostaddr xoffPauseFramesReceived; 192784059Swpaul bge_hostaddr macControlFramesReceived; 192884059Swpaul bge_hostaddr xoffStateEntered; 192984059Swpaul bge_hostaddr dot3StatsFramesTooLong; 193084059Swpaul bge_hostaddr etherStatsJabbers; 193184059Swpaul bge_hostaddr etherStatsUndersizePkts; 193284059Swpaul bge_hostaddr inRangeLengthError; 193384059Swpaul bge_hostaddr outRangeLengthError; 193484059Swpaul bge_hostaddr etherStatsPkts64Octets; 193584059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 193684059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 193784059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 193884059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 193984059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 194084059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 194184059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 194284059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 194384059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1944117659Swpaul}; 194584059Swpaul 194684059Swpaul 1947117659Swpaul/* Statistics maintained MAC Transmit block. */ 1948117659Swpaulstruct bge_tx_mac_stats { 194984059Swpaul bge_hostaddr ifHCOutOctets; 195084059Swpaul bge_hostaddr Reserved2; 195184059Swpaul bge_hostaddr etherStatsCollisions; 195284059Swpaul bge_hostaddr outXonSent; 195384059Swpaul bge_hostaddr outXoffSent; 195484059Swpaul bge_hostaddr flowControlDone; 195584059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 195684059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 195784059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 195884059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 195984059Swpaul bge_hostaddr Reserved3; 196084059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 196184059Swpaul bge_hostaddr dot3StatsLateCollisions; 196284059Swpaul bge_hostaddr dot3Collided2Times; 196384059Swpaul bge_hostaddr dot3Collided3Times; 196484059Swpaul bge_hostaddr dot3Collided4Times; 196584059Swpaul bge_hostaddr dot3Collided5Times; 196684059Swpaul bge_hostaddr dot3Collided6Times; 196784059Swpaul bge_hostaddr dot3Collided7Times; 196884059Swpaul bge_hostaddr dot3Collided8Times; 196984059Swpaul bge_hostaddr dot3Collided9Times; 197084059Swpaul bge_hostaddr dot3Collided10Times; 197184059Swpaul bge_hostaddr dot3Collided11Times; 197284059Swpaul bge_hostaddr dot3Collided12Times; 197384059Swpaul bge_hostaddr dot3Collided13Times; 197484059Swpaul bge_hostaddr dot3Collided14Times; 197584059Swpaul bge_hostaddr dot3Collided15Times; 197684059Swpaul bge_hostaddr ifHCOutUcastPkts; 197784059Swpaul bge_hostaddr ifHCOutMulticastPkts; 197884059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 197984059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 198084059Swpaul bge_hostaddr ifOutDiscards; 198184059Swpaul bge_hostaddr ifOutErrors; 1982117659Swpaul}; 198384059Swpaul 1984117659Swpaul/* Stats counters access through registers */ 1985117659Swpaulstruct bge_mac_stats_regs { 1986117659Swpaul u_int32_t ifHCOutOctets; 1987117659Swpaul u_int32_t Reserved0; 1988117659Swpaul u_int32_t etherStatsCollisions; 1989117659Swpaul u_int32_t outXonSent; 1990117659Swpaul u_int32_t outXoffSent; 1991117659Swpaul u_int32_t Reserved1; 1992117659Swpaul u_int32_t dot3StatsInternalMacTransmitErrors; 1993117659Swpaul u_int32_t dot3StatsSingleCollisionFrames; 1994117659Swpaul u_int32_t dot3StatsMultipleCollisionFrames; 1995117659Swpaul u_int32_t dot3StatsDeferredTransmissions; 1996117659Swpaul u_int32_t Reserved2; 1997117659Swpaul u_int32_t dot3StatsExcessiveCollisions; 1998117659Swpaul u_int32_t dot3StatsLateCollisions; 1999117659Swpaul u_int32_t Reserved3[14]; 2000117659Swpaul u_int32_t ifHCOutUcastPkts; 2001117659Swpaul u_int32_t ifHCOutMulticastPkts; 2002117659Swpaul u_int32_t ifHCOutBroadcastPkts; 2003117659Swpaul u_int32_t Reserved4[2]; 2004117659Swpaul u_int32_t ifHCInOctets; 2005117659Swpaul u_int32_t Reserved5; 2006117659Swpaul u_int32_t etherStatsFragments; 2007117659Swpaul u_int32_t ifHCInUcastPkts; 2008117659Swpaul u_int32_t ifHCInMulticastPkts; 2009117659Swpaul u_int32_t ifHCInBroadcastPkts; 2010117659Swpaul u_int32_t dot3StatsFCSErrors; 2011117659Swpaul u_int32_t dot3StatsAlignmentErrors; 2012117659Swpaul u_int32_t xonPauseFramesReceived; 2013117659Swpaul u_int32_t xoffPauseFramesReceived; 2014117659Swpaul u_int32_t macControlFramesReceived; 2015117659Swpaul u_int32_t xoffStateEntered; 2016117659Swpaul u_int32_t dot3StatsFramesTooLong; 2017117659Swpaul u_int32_t etherStatsJabbers; 2018117659Swpaul u_int32_t etherStatsUndersizePkts; 2019117659Swpaul}; 2020117659Swpaul 2021117659Swpaulstruct bge_stats { 2022117659Swpaul u_int8_t Reserved0[256]; 2023117659Swpaul 2024117659Swpaul /* Statistics maintained by Receive MAC. */ 2025117659Swpaul struct bge_rx_mac_stats rxstats; 2026117659Swpaul 2027117659Swpaul bge_hostaddr Unused1[37]; 2028117659Swpaul 2029117659Swpaul /* Statistics maintained by Transmit MAC. */ 2030117659Swpaul struct bge_tx_mac_stats txstats; 2031117659Swpaul 203284059Swpaul bge_hostaddr Unused2[31]; 203384059Swpaul 203484059Swpaul /* Statistics maintained by Receive List Placement. */ 203584059Swpaul bge_hostaddr COSIfHCInPkts[16]; 203684059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 203784059Swpaul bge_hostaddr nicDmaWriteQueueFull; 203884059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 203984059Swpaul bge_hostaddr nicNoMoreRxBDs; 204084059Swpaul bge_hostaddr ifInDiscards; 204184059Swpaul bge_hostaddr ifInErrors; 204284059Swpaul bge_hostaddr nicRecvThresholdHit; 204384059Swpaul 204484059Swpaul bge_hostaddr Unused3[9]; 204584059Swpaul 204684059Swpaul /* Statistics maintained by Send Data Initiator. */ 204784059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 204884059Swpaul bge_hostaddr nicDmaReadQueueFull; 204984059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 205084059Swpaul bge_hostaddr nicSendDataCompQueueFull; 205184059Swpaul 205284059Swpaul /* Statistics maintained by Host Coalescing. */ 205384059Swpaul bge_hostaddr nicRingSetSendProdIndex; 205484059Swpaul bge_hostaddr nicRingStatusUpdate; 205584059Swpaul bge_hostaddr nicInterrupts; 205684059Swpaul bge_hostaddr nicAvoidedInterrupts; 205784059Swpaul bge_hostaddr nicSendThresholdHit; 205884059Swpaul 205984059Swpaul u_int8_t Reserved4[320]; 206084059Swpaul}; 206184059Swpaul 206284059Swpaul/* 206384059Swpaul * Tigon general information block. This resides in host memory 206484059Swpaul * and contains the status counters, ring control blocks and 206584059Swpaul * producer pointers. 206684059Swpaul */ 206784059Swpaul 206884059Swpaulstruct bge_gib { 206984059Swpaul struct bge_stats bge_stats; 207084059Swpaul struct bge_rcb bge_tx_rcb[16]; 207184059Swpaul struct bge_rcb bge_std_rx_rcb; 207284059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 207384059Swpaul struct bge_rcb bge_mini_rx_rcb; 207484059Swpaul struct bge_rcb bge_return_rcb; 207584059Swpaul}; 207684059Swpaul 207784059Swpaul#define BGE_FRAMELEN 1518 207884059Swpaul#define BGE_MAX_FRAMELEN 1536 207984059Swpaul#define BGE_JUMBO_FRAMELEN 9018 208084059Swpaul#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 208184059Swpaul#define BGE_PAGE_SIZE PAGE_SIZE 208284059Swpaul#define BGE_MIN_FRAMELEN 60 208384059Swpaul 208484059Swpaul/* 208584059Swpaul * Other utility macros. 208684059Swpaul */ 208784059Swpaul#define BGE_INC(x, y) (x) = (x + 1) % y 208884059Swpaul 208984059Swpaul/* 209084059Swpaul * Vital product data and structures. 209184059Swpaul */ 209284059Swpaul#define BGE_VPD_FLAG 0x8000 209384059Swpaul 209484059Swpaul/* VPD structures */ 209584059Swpaulstruct vpd_res { 209684059Swpaul u_int8_t vr_id; 209784059Swpaul u_int8_t vr_len; 209884059Swpaul u_int8_t vr_pad; 209984059Swpaul}; 210084059Swpaul 210184059Swpaulstruct vpd_key { 210284059Swpaul char vk_key[2]; 210384059Swpaul u_int8_t vk_len; 210484059Swpaul}; 210584059Swpaul 210684059Swpaul#define VPD_RES_ID 0x82 /* ID string */ 210784059Swpaul#define VPD_RES_READ 0x90 /* start of read only area */ 210884059Swpaul#define VPD_RES_WRITE 0x81 /* start of read/write area */ 210984059Swpaul#define VPD_RES_END 0x78 /* end tag */ 211084059Swpaul 211184059Swpaul 211284059Swpaul/* 211384059Swpaul * Register access macros. The Tigon always uses memory mapped register 211484059Swpaul * accesses and all registers must be accessed with 32 bit operations. 211584059Swpaul */ 211684059Swpaul 211784059Swpaul#define CSR_WRITE_4(sc, reg, val) \ 211884059Swpaul bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 211984059Swpaul 212084059Swpaul#define CSR_READ_4(sc, reg) \ 212184059Swpaul bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 212284059Swpaul 212384059Swpaul#define BGE_SETBIT(sc, reg, x) \ 2124106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 212584059Swpaul#define BGE_CLRBIT(sc, reg, x) \ 2126106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 212784059Swpaul 212884059Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 2129106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 213084059Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 2131106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 213284059Swpaul 213384059Swpaul/* 213484059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 213584059Swpaul * values are tuneable. They control the actual amount of buffers 213684059Swpaul * allocated for the standard, mini and jumbo receive rings. 213784059Swpaul */ 213884059Swpaul 213984059Swpaul#define BGE_SSLOTS 256 214084059Swpaul#define BGE_MSLOTS 256 214184059Swpaul#define BGE_JSLOTS 384 214284059Swpaul 214384059Swpaul#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 214484059Swpaul#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 214584059Swpaul (BGE_JRAWLEN % sizeof(u_int64_t)))) 214684059Swpaul#define BGE_JPAGESZ PAGE_SIZE 214784059Swpaul#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 214884059Swpaul#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 214984059Swpaul 215084059Swpaul/* 215184059Swpaul * Ring structures. Most of these reside in host memory and we tell 215284059Swpaul * the NIC where they are via the ring control blocks. The exceptions 215384059Swpaul * are the tx and command rings, which live in NIC memory and which 215484059Swpaul * we access via the shared memory window. 215584059Swpaul */ 2156118026Swpaul 215784059Swpaulstruct bge_ring_data { 2158118026Swpaul struct bge_rx_bd *bge_rx_std_ring; 2159118026Swpaul bus_addr_t bge_rx_std_ring_paddr; 2160118026Swpaul struct bge_rx_bd *bge_rx_jumbo_ring; 2161118026Swpaul bus_addr_t bge_rx_jumbo_ring_paddr; 2162118026Swpaul struct bge_rx_bd *bge_rx_return_ring; 2163118026Swpaul bus_addr_t bge_rx_return_ring_paddr; 2164118026Swpaul struct bge_tx_bd *bge_tx_ring; 2165118026Swpaul bus_addr_t bge_tx_ring_paddr; 2166118026Swpaul struct bge_status_block *bge_status_block; 2167118026Swpaul bus_addr_t bge_status_block_paddr; 2168118026Swpaul struct bge_stats *bge_stats; 2169118026Swpaul bus_addr_t bge_stats_paddr; 2170118026Swpaul void *bge_jumbo_buf; 217184059Swpaul struct bge_gib bge_info; 217284059Swpaul}; 217384059Swpaul 2174118026Swpaul#define BGE_STD_RX_RING_SZ \ 2175118026Swpaul (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2176118026Swpaul#define BGE_JUMBO_RX_RING_SZ \ 2177118026Swpaul (sizeof(struct bge_rx_bd) * BGE_JUMBO_RX_RING_CNT) 2178118026Swpaul#define BGE_TX_RING_SZ \ 2179118026Swpaul (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2180118026Swpaul#define BGE_RX_RTN_RING_SZ(x) \ 2181118026Swpaul (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2182118026Swpaul 2183118026Swpaul#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2184118026Swpaul 2185118026Swpaul#define BGE_STATS_SZ sizeof (struct bge_stats) 2186118026Swpaul 218784059Swpaul/* 218884059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 218984059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 219084059Swpaul * not the other way around. 219184059Swpaul */ 219284059Swpaulstruct bge_chain_data { 2193118026Swpaul bus_dma_tag_t bge_parent_tag; 2194118026Swpaul bus_dma_tag_t bge_rx_std_ring_tag; 2195118026Swpaul bus_dma_tag_t bge_rx_jumbo_ring_tag; 2196118026Swpaul bus_dma_tag_t bge_rx_return_ring_tag; 2197118026Swpaul bus_dma_tag_t bge_tx_ring_tag; 2198118026Swpaul bus_dma_tag_t bge_status_tag; 2199118026Swpaul bus_dma_tag_t bge_stats_tag; 2200118026Swpaul bus_dma_tag_t bge_jumbo_tag; 2201118026Swpaul bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2202118026Swpaul bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2203118026Swpaul bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2204118026Swpaul bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2205118026Swpaul bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2206118026Swpaul bus_dmamap_t bge_rx_std_ring_map; 2207118026Swpaul bus_dmamap_t bge_rx_jumbo_ring_map; 2208118026Swpaul bus_dmamap_t bge_tx_ring_map; 2209118026Swpaul bus_dmamap_t bge_rx_return_ring_map; 2210118026Swpaul bus_dmamap_t bge_status_map; 2211118026Swpaul bus_dmamap_t bge_stats_map; 2212118026Swpaul bus_dmamap_t bge_jumbo_map; 221384059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 221484059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 221584059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 221684059Swpaul /* Stick the jumbo mem management stuff here too. */ 221784059Swpaul caddr_t bge_jslots[BGE_JSLOTS]; 221884059Swpaul}; 221984059Swpaul 2220118026Swpaulstruct bge_dmamap_arg { 2221118026Swpaul struct bge_softc *sc; 2222118026Swpaul bus_addr_t bge_busaddr; 2223118026Swpaul u_int16_t bge_flags; 2224118026Swpaul int bge_idx; 2225118026Swpaul int bge_maxsegs; 2226118026Swpaul struct bge_tx_bd *bge_ring; 2227118026Swpaul}; 2228118026Swpaul 222984059Swpaulstruct bge_type { 223084059Swpaul u_int16_t bge_vid; 223184059Swpaul u_int16_t bge_did; 223284059Swpaul char *bge_name; 223384059Swpaul}; 223484059Swpaul 223584059Swpaul#define BGE_HWREV_TIGON 0x01 223684059Swpaul#define BGE_HWREV_TIGON_II 0x02 2237117659Swpaul#define BGE_TIMEOUT 100000 223884059Swpaul#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 223984059Swpaul 224084059Swpaulstruct bge_jpool_entry { 224184059Swpaul int slot; 224284059Swpaul SLIST_ENTRY(bge_jpool_entry) jpool_entries; 224384059Swpaul}; 224484059Swpaul 224584059Swpaulstruct bge_bcom_hack { 224684059Swpaul int reg; 224784059Swpaul int val; 224884059Swpaul}; 224984059Swpaul 225084059Swpaulstruct bge_softc { 225184059Swpaul struct arpcom arpcom; /* interface info */ 225284059Swpaul device_t bge_dev; 225384059Swpaul device_t bge_miibus; 225484059Swpaul bus_space_handle_t bge_bhandle; 225584059Swpaul vm_offset_t bge_vhandle; 225684059Swpaul bus_space_tag_t bge_btag; 225784059Swpaul void *bge_intrhand; 225884059Swpaul struct resource *bge_irq; 225984059Swpaul struct resource *bge_res; 226084059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 226184059Swpaul u_int8_t bge_unit; /* interface number */ 226284059Swpaul u_int8_t bge_extram; /* has external SSRAM */ 226384059Swpaul u_int8_t bge_tbi; 226498779Sjdp u_int8_t bge_rx_alignment_bug; 2265114813Sps u_int32_t bge_chipid; 2266114813Sps u_int8_t bge_asicrev; 2267114813Sps u_int8_t bge_chiprev; 2268118026Swpaul struct bge_ring_data bge_ldata; /* rings */ 226984059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 227084059Swpaul u_int16_t bge_tx_saved_considx; 227184059Swpaul u_int16_t bge_rx_saved_considx; 227284059Swpaul u_int16_t bge_ev_saved_considx; 2273117659Swpaul u_int16_t bge_return_ring_cnt; 227484059Swpaul u_int16_t bge_std; /* current std ring head */ 227584059Swpaul u_int16_t bge_jumbo; /* current jumo ring head */ 227684059Swpaul SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 227784059Swpaul SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 227884059Swpaul u_int32_t bge_stat_ticks; 227984059Swpaul u_int32_t bge_rx_coal_ticks; 228084059Swpaul u_int32_t bge_tx_coal_ticks; 228184059Swpaul u_int32_t bge_rx_max_coal_bds; 228284059Swpaul u_int32_t bge_tx_max_coal_bds; 228384059Swpaul u_int32_t bge_tx_buf_ratio; 228484059Swpaul int bge_if_flags; 228584059Swpaul int bge_txcnt; 228684059Swpaul int bge_link; 228784059Swpaul struct callout_handle bge_stat_ch; 228884059Swpaul char *bge_vpd_prodname; 228984059Swpaul char *bge_vpd_readonly; 229084059Swpaul}; 229184059Swpaul 229284059Swpaul#ifdef __alpha__ 229384059Swpaul#undef vtophys 229484059Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 229584059Swpaul#endif 2296