if_bgereg.h revision 110367
184059Swpaul/* 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 110367 2003-02-05 08:54:36Z ps $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 6484059Swpaul#define BGE_PAGE_ZERO 0x00000000 6584059Swpaul#define BGE_PAGE_ZERO_END 0x000000FF 6684059Swpaul#define BGE_SEND_RING_RCB 0x00000100 6784059Swpaul#define BGE_SEND_RING_RCB_END 0x000001FF 6884059Swpaul#define BGE_RX_RETURN_RING_RCB 0x00000200 6984059Swpaul#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 7084059Swpaul#define BGE_STATS_BLOCK 0x00000300 7184059Swpaul#define BGE_STATS_BLOCK_END 0x00000AFF 7284059Swpaul#define BGE_STATUS_BLOCK 0x00000B00 7384059Swpaul#define BGE_STATUS_BLOCK_END 0x00000B4F 7484059Swpaul#define BGE_SOFTWARE_GENCOMM 0x00000B50 75110367Sps#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76110367Sps#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 7784059Swpaul#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 7884059Swpaul#define BGE_UNMAPPED 0x00001000 7984059Swpaul#define BGE_UNMAPPED_END 0x00001FFF 8084059Swpaul#define BGE_DMA_DESCRIPTORS 0x00002000 8184059Swpaul#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 8284059Swpaul#define BGE_SEND_RING_1_TO_4 0x00004000 8384059Swpaul#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8484059Swpaul 8584059Swpaul/* Mappings for internal memory configuration */ 8684059Swpaul#define BGE_STD_RX_RINGS 0x00006000 8784059Swpaul#define BGE_STD_RX_RINGS_END 0x00006FFF 8884059Swpaul#define BGE_JUMBO_RX_RINGS 0x00007000 8984059Swpaul#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 9084059Swpaul#define BGE_BUFFPOOL_1 0x00008000 9184059Swpaul#define BGE_BUFFPOOL_1_END 0x0000FFFF 9284059Swpaul#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 9384059Swpaul#define BGE_BUFFPOOL_2_END 0x00017FFF 9484059Swpaul#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 9584059Swpaul#define BGE_BUFFPOOL_3_END 0x0001FFFF 9684059Swpaul 9784059Swpaul/* Mappings for external SSRAM configurations */ 9884059Swpaul#define BGE_SEND_RING_5_TO_6 0x00006000 9984059Swpaul#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 10084059Swpaul#define BGE_SEND_RING_7_TO_8 0x00007000 10184059Swpaul#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 10284059Swpaul#define BGE_SEND_RING_9_TO_16 0x00008000 10384059Swpaul#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 10484059Swpaul#define BGE_EXT_STD_RX_RINGS 0x0000C000 10584059Swpaul#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 10684059Swpaul#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 10784059Swpaul#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 10884059Swpaul#define BGE_MINI_RX_RINGS 0x0000E000 10984059Swpaul#define BGE_MINI_RX_RINGS_END 0x0000FFFF 11084059Swpaul#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 11184059Swpaul#define BGE_AVAIL_REGION1_END 0x00017FFF 11284059Swpaul#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 11384059Swpaul#define BGE_AVAIL_REGION2_END 0x0001FFFF 11484059Swpaul#define BGE_EXT_SSRAM 0x00020000 11584059Swpaul#define BGE_EXT_SSRAM_END 0x000FFFFF 11684059Swpaul 11784059Swpaul 11884059Swpaul/* 11984059Swpaul * BCM570x register offsets. These are memory mapped registers 12084059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 12184059Swpaul * Each register must be accessed using 32 bit operations. 12284059Swpaul * 12384059Swpaul * All registers are accessed through a 32K shared memory block. 12484059Swpaul * The first group of registers are actually copies of the PCI 12584059Swpaul * configuration space registers. 12684059Swpaul */ 12784059Swpaul 12884059Swpaul/* 12984059Swpaul * PCI registers defined in the PCI 2.2 spec. 13084059Swpaul */ 13184059Swpaul#define BGE_PCI_VID 0x00 13284059Swpaul#define BGE_PCI_DID 0x02 13384059Swpaul#define BGE_PCI_CMD 0x04 13484059Swpaul#define BGE_PCI_STS 0x06 13584059Swpaul#define BGE_PCI_REV 0x08 13684059Swpaul#define BGE_PCI_CLASS 0x09 13784059Swpaul#define BGE_PCI_CACHESZ 0x0C 13884059Swpaul#define BGE_PCI_LATTIMER 0x0D 13984059Swpaul#define BGE_PCI_HDRTYPE 0x0E 14084059Swpaul#define BGE_PCI_BIST 0x0F 14184059Swpaul#define BGE_PCI_BAR0 0x10 14284059Swpaul#define BGE_PCI_BAR1 0x14 14384059Swpaul#define BGE_PCI_SUBSYS 0x2C 14484059Swpaul#define BGE_PCI_SUBVID 0x2E 14584059Swpaul#define BGE_PCI_ROMBASE 0x30 14684059Swpaul#define BGE_PCI_CAPPTR 0x34 14784059Swpaul#define BGE_PCI_INTLINE 0x3C 14884059Swpaul#define BGE_PCI_INTPIN 0x3D 14984059Swpaul#define BGE_PCI_MINGNT 0x3E 15084059Swpaul#define BGE_PCI_MAXLAT 0x3F 15184059Swpaul#define BGE_PCI_PCIXCAP 0x40 15284059Swpaul#define BGE_PCI_NEXTPTR_PM 0x41 15384059Swpaul#define BGE_PCI_PCIX_CMD 0x42 15484059Swpaul#define BGE_PCI_PCIX_STS 0x44 15584059Swpaul#define BGE_PCI_PWRMGMT_CAPID 0x48 15684059Swpaul#define BGE_PCI_NEXTPTR_VPD 0x49 15784059Swpaul#define BGE_PCI_PWRMGMT_CAPS 0x4A 15884059Swpaul#define BGE_PCI_PWRMGMT_CMD 0x4C 15984059Swpaul#define BGE_PCI_PWRMGMT_STS 0x4D 16084059Swpaul#define BGE_PCI_PWRMGMT_DATA 0x4F 16184059Swpaul#define BGE_PCI_VPD_CAPID 0x50 16284059Swpaul#define BGE_PCI_NEXTPTR_MSI 0x51 16384059Swpaul#define BGE_PCI_VPD_ADDR 0x52 16484059Swpaul#define BGE_PCI_VPD_DATA 0x54 16584059Swpaul#define BGE_PCI_MSI_CAPID 0x58 16684059Swpaul#define BGE_PCI_NEXTPTR_NONE 0x59 16784059Swpaul#define BGE_PCI_MSI_CTL 0x5A 16884059Swpaul#define BGE_PCI_MSI_ADDR_HI 0x5C 16984059Swpaul#define BGE_PCI_MSI_ADDR_LO 0x60 17084059Swpaul#define BGE_PCI_MSI_DATA 0x64 17184059Swpaul 17284059Swpaul/* 17384059Swpaul * PCI registers specific to the BCM570x family. 17484059Swpaul */ 17584059Swpaul#define BGE_PCI_MISC_CTL 0x68 17684059Swpaul#define BGE_PCI_DMA_RW_CTL 0x6C 17784059Swpaul#define BGE_PCI_PCISTATE 0x70 17884059Swpaul#define BGE_PCI_CLKCTL 0x74 17984059Swpaul#define BGE_PCI_REG_BASEADDR 0x78 18084059Swpaul#define BGE_PCI_MEMWIN_BASEADDR 0x7C 18184059Swpaul#define BGE_PCI_REG_DATA 0x80 18284059Swpaul#define BGE_PCI_MEMWIN_DATA 0x84 18384059Swpaul#define BGE_PCI_MODECTL 0x88 18484059Swpaul#define BGE_PCI_MISC_CFG 0x8C 18584059Swpaul#define BGE_PCI_MISC_LOCALCTL 0x90 18684059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 18784059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 18884059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 18984059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 19084059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 19184059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 19284059Swpaul#define BGE_PCI_ISR_MBX_HI 0xB0 19384059Swpaul#define BGE_PCI_ISR_MBX_LO 0xB4 19484059Swpaul 19584059Swpaul/* PCI Misc. Host control register */ 19684059Swpaul#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 19784059Swpaul#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 19884059Swpaul#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 19984059Swpaul#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 20084059Swpaul#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 20184059Swpaul#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 20284059Swpaul#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 20384059Swpaul#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 20484059Swpaul#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 20584059Swpaul 20684059Swpaul#define BGE_BIGENDIAN_INIT \ 207104325Sjake (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 20884059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 209104325Sjake BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 21084059Swpaul 21184059Swpaul#define BGE_LITTLEENDIAN_INIT \ 21284059Swpaul (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 21384059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 21484059Swpaul 21584059Swpaul#define BGE_ASICREV_TIGON_I 0x40000000 21684059Swpaul#define BGE_ASICREV_TIGON_II 0x60000000 21784059Swpaul#define BGE_ASICREV_BCM5700_B0 0x71000000 21884059Swpaul#define BGE_ASICREV_BCM5700_B1 0x71020000 21984059Swpaul#define BGE_ASICREV_BCM5700_B2 0x71030000 22084059Swpaul#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 22184059Swpaul#define BGE_ASICREV_BCM5700_C0 0x72000000 22292934Swpaul#define BGE_ASICREV_BCM5701_A0 0x00000000 /* grrrr */ 22392934Swpaul#define BGE_ASICREV_BCM5701_B0 0x01000000 22492934Swpaul#define BGE_ASICREV_BCM5701_B2 0x01020000 22592934Swpaul#define BGE_ASICREV_BCM5701_B5 0x01050000 226103103Sjdp#define BGE_ASICREV_BCM5703_A0 0x10000000 227103103Sjdp#define BGE_ASICREV_BCM5703_A1 0x10010000 228103103Sjdp#define BGE_ASICREV_BCM5703_A2 0x10020000 22984059Swpaul 23093751Swpaul/* shorthand one */ 23193751Swpaul#define BGE_ASICREV_BCM5700 0x71000000 23293751Swpaul 23384059Swpaul/* PCI DMA Read/Write Control register */ 23484059Swpaul#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 23584059Swpaul#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 23684059Swpaul#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 23784059Swpaul#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 23884059Swpaul#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 23984059Swpaul#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 24084059Swpaul#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 24184059Swpaul#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 24284059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 24384059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 24484059Swpaul 24584059Swpaul#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 24684059Swpaul#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 24784059Swpaul#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 24884059Swpaul#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 24984059Swpaul#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 25084059Swpaul#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 25184059Swpaul#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 25284059Swpaul#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 25384059Swpaul 25484059Swpaul#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 25584059Swpaul#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 25684059Swpaul#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 25784059Swpaul#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 25884059Swpaul#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 25984059Swpaul#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 26084059Swpaul#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 26184059Swpaul#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 26284059Swpaul 26384059Swpaul/* 26484059Swpaul * PCI state register -- note, this register is read only 26584059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 26684059Swpaul * register is set. 26784059Swpaul */ 26884059Swpaul#define BGE_PCISTATE_FORCE_RESET 0x00000001 26984059Swpaul#define BGE_PCISTATE_INTR_STATE 0x00000002 27084059Swpaul#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 27184059Swpaul#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 27284059Swpaul#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 27384059Swpaul#define BGE_PCISTATE_WANT_EXPROM 0x00000020 27484059Swpaul#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 27584059Swpaul#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 27684059Swpaul#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 27784059Swpaul 27884059Swpaul/* 27984059Swpaul * PCI Clock Control register -- note, this register is read only 28084059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 28184059Swpaul * register is set. 28284059Swpaul */ 28384059Swpaul#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 28484059Swpaul#define BGE_PCICLOCKCTL_M66EN 0x00000080 28584059Swpaul#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 28684059Swpaul#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 28784059Swpaul#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 28884059Swpaul#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 28984059Swpaul#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 29084059Swpaul#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 29184059Swpaul#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 29284059Swpaul#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 29384059Swpaul 29484059Swpaul 29584059Swpaul#ifndef PCIM_CMD_MWIEN 29684059Swpaul#define PCIM_CMD_MWIEN 0x0010 29784059Swpaul#endif 29884059Swpaul 29984059Swpaul/* 30084059Swpaul * High priority mailbox registers 30184059Swpaul * Each mailbox is 64-bits wide, though we only use the 30284059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 30384059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 30484059Swpaul * has been updated. 30584059Swpaul */ 30684059Swpaul#define BGE_MBX_IRQ0_HI 0x0200 30784059Swpaul#define BGE_MBX_IRQ0_LO 0x0204 30884059Swpaul#define BGE_MBX_IRQ1_HI 0x0208 30984059Swpaul#define BGE_MBX_IRQ1_LO 0x020C 31084059Swpaul#define BGE_MBX_IRQ2_HI 0x0210 31184059Swpaul#define BGE_MBX_IRQ2_LO 0x0214 31284059Swpaul#define BGE_MBX_IRQ3_HI 0x0218 31384059Swpaul#define BGE_MBX_IRQ3_LO 0x021C 31484059Swpaul#define BGE_MBX_GEN0_HI 0x0220 31584059Swpaul#define BGE_MBX_GEN0_LO 0x0224 31684059Swpaul#define BGE_MBX_GEN1_HI 0x0228 31784059Swpaul#define BGE_MBX_GEN1_LO 0x022C 31884059Swpaul#define BGE_MBX_GEN2_HI 0x0230 31984059Swpaul#define BGE_MBX_GEN2_LO 0x0234 32084059Swpaul#define BGE_MBX_GEN3_HI 0x0228 32184059Swpaul#define BGE_MBX_GEN3_LO 0x022C 32284059Swpaul#define BGE_MBX_GEN4_HI 0x0240 32384059Swpaul#define BGE_MBX_GEN4_LO 0x0244 32484059Swpaul#define BGE_MBX_GEN5_HI 0x0248 32584059Swpaul#define BGE_MBX_GEN5_LO 0x024C 32684059Swpaul#define BGE_MBX_GEN6_HI 0x0250 32784059Swpaul#define BGE_MBX_GEN6_LO 0x0254 32884059Swpaul#define BGE_MBX_GEN7_HI 0x0258 32984059Swpaul#define BGE_MBX_GEN7_LO 0x025C 33084059Swpaul#define BGE_MBX_RELOAD_STATS_HI 0x0260 33184059Swpaul#define BGE_MBX_RELOAD_STATS_LO 0x0264 33284059Swpaul#define BGE_MBX_RX_STD_PROD_HI 0x0268 33384059Swpaul#define BGE_MBX_RX_STD_PROD_LO 0x026C 33484059Swpaul#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 33584059Swpaul#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 33684059Swpaul#define BGE_MBX_RX_MINI_PROD_HI 0x0278 33784059Swpaul#define BGE_MBX_RX_MINI_PROD_LO 0x027C 33884059Swpaul#define BGE_MBX_RX_CONS0_HI 0x0280 33984059Swpaul#define BGE_MBX_RX_CONS0_LO 0x0284 34084059Swpaul#define BGE_MBX_RX_CONS1_HI 0x0288 34184059Swpaul#define BGE_MBX_RX_CONS1_LO 0x028C 34284059Swpaul#define BGE_MBX_RX_CONS2_HI 0x0290 34384059Swpaul#define BGE_MBX_RX_CONS2_LO 0x0294 34484059Swpaul#define BGE_MBX_RX_CONS3_HI 0x0298 34584059Swpaul#define BGE_MBX_RX_CONS3_LO 0x029C 34684059Swpaul#define BGE_MBX_RX_CONS4_HI 0x02A0 34784059Swpaul#define BGE_MBX_RX_CONS4_LO 0x02A4 34884059Swpaul#define BGE_MBX_RX_CONS5_HI 0x02A8 34984059Swpaul#define BGE_MBX_RX_CONS5_LO 0x02AC 35084059Swpaul#define BGE_MBX_RX_CONS6_HI 0x02B0 35184059Swpaul#define BGE_MBX_RX_CONS6_LO 0x02B4 35284059Swpaul#define BGE_MBX_RX_CONS7_HI 0x02B8 35384059Swpaul#define BGE_MBX_RX_CONS7_LO 0x02BC 35484059Swpaul#define BGE_MBX_RX_CONS8_HI 0x02C0 35584059Swpaul#define BGE_MBX_RX_CONS8_LO 0x02C4 35684059Swpaul#define BGE_MBX_RX_CONS9_HI 0x02C8 35784059Swpaul#define BGE_MBX_RX_CONS9_LO 0x02CC 35884059Swpaul#define BGE_MBX_RX_CONS10_HI 0x02D0 35984059Swpaul#define BGE_MBX_RX_CONS10_LO 0x02D4 36084059Swpaul#define BGE_MBX_RX_CONS11_HI 0x02D8 36184059Swpaul#define BGE_MBX_RX_CONS11_LO 0x02DC 36284059Swpaul#define BGE_MBX_RX_CONS12_HI 0x02E0 36384059Swpaul#define BGE_MBX_RX_CONS12_LO 0x02E4 36484059Swpaul#define BGE_MBX_RX_CONS13_HI 0x02E8 36584059Swpaul#define BGE_MBX_RX_CONS13_LO 0x02EC 36684059Swpaul#define BGE_MBX_RX_CONS14_HI 0x02F0 36784059Swpaul#define BGE_MBX_RX_CONS14_LO 0x02F4 36884059Swpaul#define BGE_MBX_RX_CONS15_HI 0x02F8 36984059Swpaul#define BGE_MBX_RX_CONS15_LO 0x02FC 37084059Swpaul#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 37184059Swpaul#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 37284059Swpaul#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 37384059Swpaul#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 37484059Swpaul#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 37584059Swpaul#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 37684059Swpaul#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 37784059Swpaul#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 37884059Swpaul#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 37984059Swpaul#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 38084059Swpaul#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 38184059Swpaul#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 38284059Swpaul#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 38384059Swpaul#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 38484059Swpaul#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 38584059Swpaul#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 38684059Swpaul#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 38784059Swpaul#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 38884059Swpaul#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 38984059Swpaul#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 39084059Swpaul#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 39184059Swpaul#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 39284059Swpaul#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 39384059Swpaul#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 39484059Swpaul#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 39584059Swpaul#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 39684059Swpaul#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 39784059Swpaul#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 39884059Swpaul#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 39984059Swpaul#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 40084059Swpaul#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 40184059Swpaul#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 40284059Swpaul#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 40384059Swpaul#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 40484059Swpaul#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 40584059Swpaul#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 40684059Swpaul#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 40784059Swpaul#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 40884059Swpaul#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 40984059Swpaul#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 41084059Swpaul#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 41184059Swpaul#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 41284059Swpaul#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 41384059Swpaul#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 41484059Swpaul#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 41584059Swpaul#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 41684059Swpaul#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 41784059Swpaul#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 41884059Swpaul#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 41984059Swpaul#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 42084059Swpaul#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 42184059Swpaul#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 42284059Swpaul#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 42384059Swpaul#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 42484059Swpaul#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 42584059Swpaul#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 42684059Swpaul#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 42784059Swpaul#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 42884059Swpaul#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 42984059Swpaul#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 43084059Swpaul#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 43184059Swpaul#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 43284059Swpaul#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 43384059Swpaul#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 43484059Swpaul 43584059Swpaul#define BGE_TX_RINGS_MAX 4 43684059Swpaul#define BGE_TX_RINGS_EXTSSRAM_MAX 16 43784059Swpaul#define BGE_RX_RINGS_MAX 16 43884059Swpaul 43984059Swpaul/* Ethernet MAC control registers */ 44084059Swpaul#define BGE_MAC_MODE 0x0400 44184059Swpaul#define BGE_MAC_STS 0x0404 44284059Swpaul#define BGE_MAC_EVT_ENB 0x0408 44384059Swpaul#define BGE_MAC_LED_CTL 0x040C 44484059Swpaul#define BGE_MAC_ADDR1_LO 0x0410 44584059Swpaul#define BGE_MAC_ADDR1_HI 0x0414 44684059Swpaul#define BGE_MAC_ADDR2_LO 0x0418 44784059Swpaul#define BGE_MAC_ADDR2_HI 0x041C 44884059Swpaul#define BGE_MAC_ADDR3_LO 0x0420 44984059Swpaul#define BGE_MAC_ADDR3_HI 0x0424 45084059Swpaul#define BGE_MAC_ADDR4_LO 0x0428 45184059Swpaul#define BGE_MAC_ADDR4_HI 0x042C 45284059Swpaul#define BGE_WOL_PATPTR 0x0430 45384059Swpaul#define BGE_WOL_PATCFG 0x0434 45484059Swpaul#define BGE_TX_RANDOM_BACKOFF 0x0438 45584059Swpaul#define BGE_RX_MTU 0x043C 45684059Swpaul#define BGE_GBIT_PCS_TEST 0x0440 45784059Swpaul#define BGE_TX_TBI_AUTONEG 0x0444 45884059Swpaul#define BGE_RX_TBI_AUTONEG 0x0448 45984059Swpaul#define BGE_MI_COMM 0x044C 46084059Swpaul#define BGE_MI_STS 0x0450 46184059Swpaul#define BGE_MI_MODE 0x0454 46284059Swpaul#define BGE_AUTOPOLL_STS 0x0458 46384059Swpaul#define BGE_TX_MODE 0x045C 46484059Swpaul#define BGE_TX_STS 0x0460 46584059Swpaul#define BGE_TX_LENGTHS 0x0464 46684059Swpaul#define BGE_RX_MODE 0x0468 46784059Swpaul#define BGE_RX_STS 0x046C 46884059Swpaul#define BGE_MAR0 0x0470 46984059Swpaul#define BGE_MAR1 0x0474 47084059Swpaul#define BGE_MAR2 0x0478 47184059Swpaul#define BGE_MAR3 0x047C 47284059Swpaul#define BGE_RX_BD_RULES_CTL0 0x0480 47384059Swpaul#define BGE_RX_BD_RULES_MASKVAL0 0x0484 47484059Swpaul#define BGE_RX_BD_RULES_CTL1 0x0488 47584059Swpaul#define BGE_RX_BD_RULES_MASKVAL1 0x048C 47684059Swpaul#define BGE_RX_BD_RULES_CTL2 0x0490 47784059Swpaul#define BGE_RX_BD_RULES_MASKVAL2 0x0494 47884059Swpaul#define BGE_RX_BD_RULES_CTL3 0x0498 47984059Swpaul#define BGE_RX_BD_RULES_MASKVAL3 0x049C 48084059Swpaul#define BGE_RX_BD_RULES_CTL4 0x04A0 48184059Swpaul#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 48284059Swpaul#define BGE_RX_BD_RULES_CTL5 0x04A8 48384059Swpaul#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 48484059Swpaul#define BGE_RX_BD_RULES_CTL6 0x04B0 48584059Swpaul#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 48684059Swpaul#define BGE_RX_BD_RULES_CTL7 0x04B8 48784059Swpaul#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 48884059Swpaul#define BGE_RX_BD_RULES_CTL8 0x04C0 48984059Swpaul#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 49084059Swpaul#define BGE_RX_BD_RULES_CTL9 0x04C8 49184059Swpaul#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 49284059Swpaul#define BGE_RX_BD_RULES_CTL10 0x04D0 49384059Swpaul#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 49484059Swpaul#define BGE_RX_BD_RULES_CTL11 0x04D8 49584059Swpaul#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 49684059Swpaul#define BGE_RX_BD_RULES_CTL12 0x04E0 49784059Swpaul#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 49884059Swpaul#define BGE_RX_BD_RULES_CTL13 0x04E8 49984059Swpaul#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 50084059Swpaul#define BGE_RX_BD_RULES_CTL14 0x04F0 50184059Swpaul#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 50284059Swpaul#define BGE_RX_BD_RULES_CTL15 0x04F8 50384059Swpaul#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 50484059Swpaul#define BGE_RX_RULES_CFG 0x0500 50584059Swpaul#define BGE_RX_STATS 0x0800 50684059Swpaul#define BGE_TX_STATS 0x0880 50784059Swpaul 50884059Swpaul/* Ethernet MAC Mode register */ 50984059Swpaul#define BGE_MACMODE_RESET 0x00000001 51084059Swpaul#define BGE_MACMODE_HALF_DUPLEX 0x00000002 51184059Swpaul#define BGE_MACMODE_PORTMODE 0x0000000C 51284059Swpaul#define BGE_MACMODE_LOOPBACK 0x00000010 51384059Swpaul#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 51484059Swpaul#define BGE_MACMODE_TX_BURST_ENB 0x00000100 51584059Swpaul#define BGE_MACMODE_MAX_DEFER 0x00000200 51684059Swpaul#define BGE_MACMODE_LINK_POLARITY 0x00000400 51784059Swpaul#define BGE_MACMODE_RX_STATS_ENB 0x00000800 51884059Swpaul#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 51984059Swpaul#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 52084059Swpaul#define BGE_MACMODE_TX_STATS_ENB 0x00004000 52184059Swpaul#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 52284059Swpaul#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 52384059Swpaul#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 52484059Swpaul#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 52584059Swpaul#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 52684059Swpaul#define BGE_MACMODE_MIP_ENB 0x00100000 52784059Swpaul#define BGE_MACMODE_TXDMA_ENB 0x00200000 52884059Swpaul#define BGE_MACMODE_RXDMA_ENB 0x00400000 52984059Swpaul#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 53084059Swpaul 53184059Swpaul#define BGE_PORTMODE_NONE 0x00000000 53284059Swpaul#define BGE_PORTMODE_MII 0x00000004 53384059Swpaul#define BGE_PORTMODE_GMII 0x00000008 53484059Swpaul#define BGE_PORTMODE_TBI 0x0000000C 53584059Swpaul 53684059Swpaul/* MAC Status register */ 53784059Swpaul#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 53884059Swpaul#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 53984059Swpaul#define BGE_MACSTAT_RX_CFG 0x00000004 54084059Swpaul#define BGE_MACSTAT_CFG_CHANGED 0x00000008 54184059Swpaul#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 54284059Swpaul#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 54384059Swpaul#define BGE_MACSTAT_LINK_CHANGED 0x00001000 54484059Swpaul#define BGE_MACSTAT_MI_COMPLETE 0x00400000 54584059Swpaul#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 54684059Swpaul#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 54784059Swpaul#define BGE_MACSTAT_ODI_ERROR 0x02000000 54884059Swpaul#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 54984059Swpaul#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 55084059Swpaul 55184059Swpaul/* MAC Event Enable Register */ 55284059Swpaul#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 55384059Swpaul#define BGE_EVTENB_LINK_CHANGED 0x00001000 55484059Swpaul#define BGE_EVTENB_MI_COMPLETE 0x00400000 55584059Swpaul#define BGE_EVTENB_MI_INTERRUPT 0x00800000 55684059Swpaul#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 55784059Swpaul#define BGE_EVTENB_ODI_ERROR 0x02000000 55884059Swpaul#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 55984059Swpaul#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 56084059Swpaul 56184059Swpaul/* LED Control Register */ 56284059Swpaul#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 56384059Swpaul#define BGE_LEDCTL_1000MBPS_LED 0x00000002 56484059Swpaul#define BGE_LEDCTL_100MBPS_LED 0x00000004 56584059Swpaul#define BGE_LEDCTL_10MBPS_LED 0x00000008 56684059Swpaul#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 56784059Swpaul#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 56884059Swpaul#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 56984059Swpaul#define BGE_LEDCTL_1000MBPS_STS 0x00000080 57084059Swpaul#define BGE_LEDCTL_100MBPS_STS 0x00000100 57184059Swpaul#define BGE_LEDCTL_10MBPS_STS 0x00000200 57284059Swpaul#define BGE_LEDCTL_TRADLED_STS 0x00000400 57384059Swpaul#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 57484059Swpaul#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 57584059Swpaul 57684059Swpaul/* TX backoff seed register */ 57784059Swpaul#define BGE_TX_BACKOFF_SEED_MASK 0x3F 57884059Swpaul 57984059Swpaul/* Autopoll status register */ 58084059Swpaul#define BGE_AUTOPOLLSTS_ERROR 0x00000001 58184059Swpaul 58284059Swpaul/* Transmit MAC mode register */ 58384059Swpaul#define BGE_TXMODE_RESET 0x00000001 58484059Swpaul#define BGE_TXMODE_ENABLE 0x00000002 58584059Swpaul#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 58684059Swpaul#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 58784059Swpaul#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 58884059Swpaul 58984059Swpaul/* Transmit MAC status register */ 59084059Swpaul#define BGE_TXSTAT_RX_XOFFED 0x00000001 59184059Swpaul#define BGE_TXSTAT_SENT_XOFF 0x00000002 59284059Swpaul#define BGE_TXSTAT_SENT_XON 0x00000004 59384059Swpaul#define BGE_TXSTAT_LINK_UP 0x00000008 59484059Swpaul#define BGE_TXSTAT_ODI_UFLOW 0x00000010 59584059Swpaul#define BGE_TXSTAT_ODI_OFLOW 0x00000020 59684059Swpaul 59784059Swpaul/* Transmit MAC lengths register */ 59884059Swpaul#define BGE_TXLEN_SLOTTIME 0x000000FF 59984059Swpaul#define BGE_TXLEN_IPG 0x00000F00 60084059Swpaul#define BGE_TXLEN_CRS 0x00003000 60184059Swpaul 60284059Swpaul/* Receive MAC mode register */ 60384059Swpaul#define BGE_RXMODE_RESET 0x00000001 60484059Swpaul#define BGE_RXMODE_ENABLE 0x00000002 60584059Swpaul#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 60684059Swpaul#define BGE_RXMODE_RX_GIANTS 0x00000020 60784059Swpaul#define BGE_RXMODE_RX_RUNTS 0x00000040 60884059Swpaul#define BGE_RXMODE_8022_LENCHECK 0x00000080 60984059Swpaul#define BGE_RXMODE_RX_PROMISC 0x00000100 61084059Swpaul#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 61184059Swpaul#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 61284059Swpaul 61384059Swpaul/* Receive MAC status register */ 61484059Swpaul#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 61584059Swpaul#define BGE_RXSTAT_RCVD_XOFF 0x00000002 61684059Swpaul#define BGE_RXSTAT_RCVD_XON 0x00000004 61784059Swpaul 61884059Swpaul/* Receive Rules Control register */ 61984059Swpaul#define BGE_RXRULECTL_OFFSET 0x000000FF 62084059Swpaul#define BGE_RXRULECTL_CLASS 0x00001F00 62184059Swpaul#define BGE_RXRULECTL_HDRTYPE 0x0000E000 62284059Swpaul#define BGE_RXRULECTL_COMPARE_OP 0x00030000 62384059Swpaul#define BGE_RXRULECTL_MAP 0x01000000 62484059Swpaul#define BGE_RXRULECTL_DISCARD 0x02000000 62584059Swpaul#define BGE_RXRULECTL_MASK 0x04000000 62684059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 62784059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 62884059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 62984059Swpaul#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 63084059Swpaul 63184059Swpaul/* Receive Rules Mask register */ 63284059Swpaul#define BGE_RXRULEMASK_VALUE 0x0000FFFF 63384059Swpaul#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 63484059Swpaul 63584059Swpaul/* MI communication register */ 63684059Swpaul#define BGE_MICOMM_DATA 0x0000FFFF 63784059Swpaul#define BGE_MICOMM_REG 0x001F0000 63884059Swpaul#define BGE_MICOMM_PHY 0x03E00000 63984059Swpaul#define BGE_MICOMM_CMD 0x0C000000 64084059Swpaul#define BGE_MICOMM_READFAIL 0x10000000 64184059Swpaul#define BGE_MICOMM_BUSY 0x20000000 64284059Swpaul 64384059Swpaul#define BGE_MIREG(x) ((x & 0x1F) << 16) 64484059Swpaul#define BGE_MIPHY(x) ((x & 0x1F) << 21) 64584059Swpaul#define BGE_MICMD_WRITE 0x04000000 64684059Swpaul#define BGE_MICMD_READ 0x08000000 64784059Swpaul 64884059Swpaul/* MI status register */ 64984059Swpaul#define BGE_MISTS_LINK 0x00000001 65084059Swpaul#define BGE_MISTS_10MBPS 0x00000002 65184059Swpaul 65284059Swpaul#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 65384059Swpaul#define BGE_MIMODE_AUTOPOLL 0x00000010 65484059Swpaul#define BGE_MIMODE_CLKCNT 0x001F0000 65584059Swpaul 65684059Swpaul 65784059Swpaul/* 65884059Swpaul * Send data initiator control registers. 65984059Swpaul */ 66084059Swpaul#define BGE_SDI_MODE 0x0C00 66184059Swpaul#define BGE_SDI_STATUS 0x0C04 66284059Swpaul#define BGE_SDI_STATS_CTL 0x0C08 66384059Swpaul#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 66484059Swpaul#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 66584059Swpaul#define BGE_LOCSTATS_COS0 0x0C80 66684059Swpaul#define BGE_LOCSTATS_COS1 0x0C84 66784059Swpaul#define BGE_LOCSTATS_COS2 0x0C88 66884059Swpaul#define BGE_LOCSTATS_COS3 0x0C8C 66984059Swpaul#define BGE_LOCSTATS_COS4 0x0C90 67084059Swpaul#define BGE_LOCSTATS_COS5 0x0C84 67184059Swpaul#define BGE_LOCSTATS_COS6 0x0C98 67284059Swpaul#define BGE_LOCSTATS_COS7 0x0C9C 67384059Swpaul#define BGE_LOCSTATS_COS8 0x0CA0 67484059Swpaul#define BGE_LOCSTATS_COS9 0x0CA4 67584059Swpaul#define BGE_LOCSTATS_COS10 0x0CA8 67684059Swpaul#define BGE_LOCSTATS_COS11 0x0CAC 67784059Swpaul#define BGE_LOCSTATS_COS12 0x0CB0 67884059Swpaul#define BGE_LOCSTATS_COS13 0x0CB4 67984059Swpaul#define BGE_LOCSTATS_COS14 0x0CB8 68084059Swpaul#define BGE_LOCSTATS_COS15 0x0CBC 68184059Swpaul#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 68284059Swpaul#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 68384059Swpaul#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 68484059Swpaul#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 68584059Swpaul#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 68684059Swpaul#define BGE_LOCSTATS_IRQS 0x0CD4 68784059Swpaul#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 68884059Swpaul#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 68984059Swpaul 69084059Swpaul/* Send Data Initiator mode register */ 69184059Swpaul#define BGE_SDIMODE_RESET 0x00000001 69284059Swpaul#define BGE_SDIMODE_ENABLE 0x00000002 69384059Swpaul#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 69484059Swpaul 69584059Swpaul/* Send Data Initiator stats register */ 69684059Swpaul#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 69784059Swpaul 69884059Swpaul/* Send Data Initiator stats control register */ 69984059Swpaul#define BGE_SDISTATSCTL_ENABLE 0x00000001 70084059Swpaul#define BGE_SDISTATSCTL_FASTER 0x00000002 70184059Swpaul#define BGE_SDISTATSCTL_CLEAR 0x00000004 70284059Swpaul#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 70384059Swpaul#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 70484059Swpaul 70584059Swpaul/* 70684059Swpaul * Send Data Completion Control registers 70784059Swpaul */ 70884059Swpaul#define BGE_SDC_MODE 0x1000 70984059Swpaul#define BGE_SDC_STATUS 0x1004 71084059Swpaul 71184059Swpaul/* Send Data completion mode register */ 71284059Swpaul#define BGE_SDCMODE_RESET 0x00000001 71384059Swpaul#define BGE_SDCMODE_ENABLE 0x00000002 71484059Swpaul#define BGE_SDCMODE_ATTN 0x00000004 71584059Swpaul 71684059Swpaul/* Send Data completion status register */ 71784059Swpaul#define BGE_SDCSTAT_ATTN 0x00000004 71884059Swpaul 71984059Swpaul/* 72084059Swpaul * Send BD Ring Selector Control registers 72184059Swpaul */ 72284059Swpaul#define BGE_SRS_MODE 0x1400 72384059Swpaul#define BGE_SRS_STATUS 0x1404 72484059Swpaul#define BGE_SRS_HWDIAG 0x1408 72584059Swpaul#define BGE_SRS_LOC_NIC_CONS0 0x1440 72684059Swpaul#define BGE_SRS_LOC_NIC_CONS1 0x1444 72784059Swpaul#define BGE_SRS_LOC_NIC_CONS2 0x1448 72884059Swpaul#define BGE_SRS_LOC_NIC_CONS3 0x144C 72984059Swpaul#define BGE_SRS_LOC_NIC_CONS4 0x1450 73084059Swpaul#define BGE_SRS_LOC_NIC_CONS5 0x1454 73184059Swpaul#define BGE_SRS_LOC_NIC_CONS6 0x1458 73284059Swpaul#define BGE_SRS_LOC_NIC_CONS7 0x145C 73384059Swpaul#define BGE_SRS_LOC_NIC_CONS8 0x1460 73484059Swpaul#define BGE_SRS_LOC_NIC_CONS9 0x1464 73584059Swpaul#define BGE_SRS_LOC_NIC_CONS10 0x1468 73684059Swpaul#define BGE_SRS_LOC_NIC_CONS11 0x146C 73784059Swpaul#define BGE_SRS_LOC_NIC_CONS12 0x1470 73884059Swpaul#define BGE_SRS_LOC_NIC_CONS13 0x1474 73984059Swpaul#define BGE_SRS_LOC_NIC_CONS14 0x1478 74084059Swpaul#define BGE_SRS_LOC_NIC_CONS15 0x147C 74184059Swpaul 74284059Swpaul/* Send BD Ring Selector Mode register */ 74384059Swpaul#define BGE_SRSMODE_RESET 0x00000001 74484059Swpaul#define BGE_SRSMODE_ENABLE 0x00000002 74584059Swpaul#define BGE_SRSMODE_ATTN 0x00000004 74684059Swpaul 74784059Swpaul/* Send BD Ring Selector Status register */ 74884059Swpaul#define BGE_SRSSTAT_ERROR 0x00000004 74984059Swpaul 75084059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 75184059Swpaul#define BGE_SRSHWDIAG_STATE 0x0000000F 75284059Swpaul#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 75384059Swpaul#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 75484059Swpaul#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 75584059Swpaul 75684059Swpaul/* 75784059Swpaul * Send BD Initiator Selector Control registers 75884059Swpaul */ 75984059Swpaul#define BGE_SBDI_MODE 0x1800 76084059Swpaul#define BGE_SBDI_STATUS 0x1804 76184059Swpaul#define BGE_SBDI_LOC_NIC_PROD0 0x1808 76284059Swpaul#define BGE_SBDI_LOC_NIC_PROD1 0x180C 76384059Swpaul#define BGE_SBDI_LOC_NIC_PROD2 0x1810 76484059Swpaul#define BGE_SBDI_LOC_NIC_PROD3 0x1814 76584059Swpaul#define BGE_SBDI_LOC_NIC_PROD4 0x1818 76684059Swpaul#define BGE_SBDI_LOC_NIC_PROD5 0x181C 76784059Swpaul#define BGE_SBDI_LOC_NIC_PROD6 0x1820 76884059Swpaul#define BGE_SBDI_LOC_NIC_PROD7 0x1824 76984059Swpaul#define BGE_SBDI_LOC_NIC_PROD8 0x1828 77084059Swpaul#define BGE_SBDI_LOC_NIC_PROD9 0x182C 77184059Swpaul#define BGE_SBDI_LOC_NIC_PROD10 0x1830 77284059Swpaul#define BGE_SBDI_LOC_NIC_PROD11 0x1834 77384059Swpaul#define BGE_SBDI_LOC_NIC_PROD12 0x1838 77484059Swpaul#define BGE_SBDI_LOC_NIC_PROD13 0x183C 77584059Swpaul#define BGE_SBDI_LOC_NIC_PROD14 0x1840 77684059Swpaul#define BGE_SBDI_LOC_NIC_PROD15 0x1844 77784059Swpaul 77884059Swpaul/* Send BD Initiator Mode register */ 77984059Swpaul#define BGE_SBDIMODE_RESET 0x00000001 78084059Swpaul#define BGE_SBDIMODE_ENABLE 0x00000002 78184059Swpaul#define BGE_SBDIMODE_ATTN 0x00000004 78284059Swpaul 78384059Swpaul/* Send BD Initiator Status register */ 78484059Swpaul#define BGE_SBDISTAT_ERROR 0x00000004 78584059Swpaul 78684059Swpaul/* 78784059Swpaul * Send BD Completion Control registers 78884059Swpaul */ 78984059Swpaul#define BGE_SBDC_MODE 0x1C00 79084059Swpaul#define BGE_SBDC_STATUS 0x1C04 79184059Swpaul 79284059Swpaul/* Send BD Completion Control Mode register */ 79384059Swpaul#define BGE_SBDCMODE_RESET 0x00000001 79484059Swpaul#define BGE_SBDCMODE_ENABLE 0x00000002 79584059Swpaul#define BGE_SBDCMODE_ATTN 0x00000004 79684059Swpaul 79784059Swpaul/* Send BD Completion Control Status register */ 79884059Swpaul#define BGE_SBDCSTAT_ATTN 0x00000004 79984059Swpaul 80084059Swpaul/* 80184059Swpaul * Receive List Placement Control registers 80284059Swpaul */ 80384059Swpaul#define BGE_RXLP_MODE 0x2000 80484059Swpaul#define BGE_RXLP_STATUS 0x2004 80584059Swpaul#define BGE_RXLP_SEL_LIST_LOCK 0x2008 80684059Swpaul#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 80784059Swpaul#define BGE_RXLP_CFG 0x2010 80884059Swpaul#define BGE_RXLP_STATS_CTL 0x2014 80984059Swpaul#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 81084059Swpaul#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 81184059Swpaul#define BGE_RXLP_HEAD0 0x2100 81284059Swpaul#define BGE_RXLP_TAIL0 0x2104 81384059Swpaul#define BGE_RXLP_COUNT0 0x2108 81484059Swpaul#define BGE_RXLP_HEAD1 0x2110 81584059Swpaul#define BGE_RXLP_TAIL1 0x2114 81684059Swpaul#define BGE_RXLP_COUNT1 0x2118 81784059Swpaul#define BGE_RXLP_HEAD2 0x2120 81884059Swpaul#define BGE_RXLP_TAIL2 0x2124 81984059Swpaul#define BGE_RXLP_COUNT2 0x2128 82084059Swpaul#define BGE_RXLP_HEAD3 0x2130 82184059Swpaul#define BGE_RXLP_TAIL3 0x2134 82284059Swpaul#define BGE_RXLP_COUNT3 0x2138 82384059Swpaul#define BGE_RXLP_HEAD4 0x2140 82484059Swpaul#define BGE_RXLP_TAIL4 0x2144 82584059Swpaul#define BGE_RXLP_COUNT4 0x2148 82684059Swpaul#define BGE_RXLP_HEAD5 0x2150 82784059Swpaul#define BGE_RXLP_TAIL5 0x2154 82884059Swpaul#define BGE_RXLP_COUNT5 0x2158 82984059Swpaul#define BGE_RXLP_HEAD6 0x2160 83084059Swpaul#define BGE_RXLP_TAIL6 0x2164 83184059Swpaul#define BGE_RXLP_COUNT6 0x2168 83284059Swpaul#define BGE_RXLP_HEAD7 0x2170 83384059Swpaul#define BGE_RXLP_TAIL7 0x2174 83484059Swpaul#define BGE_RXLP_COUNT7 0x2178 83584059Swpaul#define BGE_RXLP_HEAD8 0x2180 83684059Swpaul#define BGE_RXLP_TAIL8 0x2184 83784059Swpaul#define BGE_RXLP_COUNT8 0x2188 83884059Swpaul#define BGE_RXLP_HEAD9 0x2190 83984059Swpaul#define BGE_RXLP_TAIL9 0x2194 84084059Swpaul#define BGE_RXLP_COUNT9 0x2198 84184059Swpaul#define BGE_RXLP_HEAD10 0x21A0 84284059Swpaul#define BGE_RXLP_TAIL10 0x21A4 84384059Swpaul#define BGE_RXLP_COUNT10 0x21A8 84484059Swpaul#define BGE_RXLP_HEAD11 0x21B0 84584059Swpaul#define BGE_RXLP_TAIL11 0x21B4 84684059Swpaul#define BGE_RXLP_COUNT11 0x21B8 84784059Swpaul#define BGE_RXLP_HEAD12 0x21C0 84884059Swpaul#define BGE_RXLP_TAIL12 0x21C4 84984059Swpaul#define BGE_RXLP_COUNT12 0x21C8 85084059Swpaul#define BGE_RXLP_HEAD13 0x21D0 85184059Swpaul#define BGE_RXLP_TAIL13 0x21D4 85284059Swpaul#define BGE_RXLP_COUNT13 0x21D8 85384059Swpaul#define BGE_RXLP_HEAD14 0x21E0 85484059Swpaul#define BGE_RXLP_TAIL14 0x21E4 85584059Swpaul#define BGE_RXLP_COUNT14 0x21E8 85684059Swpaul#define BGE_RXLP_HEAD15 0x21F0 85784059Swpaul#define BGE_RXLP_TAIL15 0x21F4 85884059Swpaul#define BGE_RXLP_COUNT15 0x21F8 85984059Swpaul#define BGE_RXLP_LOCSTAT_COS0 0x2200 86084059Swpaul#define BGE_RXLP_LOCSTAT_COS1 0x2204 86184059Swpaul#define BGE_RXLP_LOCSTAT_COS2 0x2208 86284059Swpaul#define BGE_RXLP_LOCSTAT_COS3 0x220C 86384059Swpaul#define BGE_RXLP_LOCSTAT_COS4 0x2210 86484059Swpaul#define BGE_RXLP_LOCSTAT_COS5 0x2214 86584059Swpaul#define BGE_RXLP_LOCSTAT_COS6 0x2218 86684059Swpaul#define BGE_RXLP_LOCSTAT_COS7 0x221C 86784059Swpaul#define BGE_RXLP_LOCSTAT_COS8 0x2220 86884059Swpaul#define BGE_RXLP_LOCSTAT_COS9 0x2224 86984059Swpaul#define BGE_RXLP_LOCSTAT_COS10 0x2228 87084059Swpaul#define BGE_RXLP_LOCSTAT_COS11 0x222C 87184059Swpaul#define BGE_RXLP_LOCSTAT_COS12 0x2230 87284059Swpaul#define BGE_RXLP_LOCSTAT_COS13 0x2234 87384059Swpaul#define BGE_RXLP_LOCSTAT_COS14 0x2238 87484059Swpaul#define BGE_RXLP_LOCSTAT_COS15 0x223C 87584059Swpaul#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 87684059Swpaul#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 87784059Swpaul#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 87884059Swpaul#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 87984059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 88084059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 88184059Swpaul#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 88284059Swpaul 88384059Swpaul 88484059Swpaul/* Receive List Placement mode register */ 88584059Swpaul#define BGE_RXLPMODE_RESET 0x00000001 88684059Swpaul#define BGE_RXLPMODE_ENABLE 0x00000002 88784059Swpaul#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 88884059Swpaul#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 88984059Swpaul#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 89084059Swpaul 89184059Swpaul/* Receive List Placement Status register */ 89284059Swpaul#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 89384059Swpaul#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 89484059Swpaul#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 89584059Swpaul 89684059Swpaul/* 89784059Swpaul * Receive Data and Receive BD Initiator Control Registers 89884059Swpaul */ 89984059Swpaul#define BGE_RDBDI_MODE 0x2400 90084059Swpaul#define BGE_RDBDI_STATUS 0x2404 90184059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 90284059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 90384059Swpaul#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 90484059Swpaul#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 90584059Swpaul#define BGE_RX_STD_RCB_HADDR_HI 0x2450 90684059Swpaul#define BGE_RX_STD_RCB_HADDR_LO 0x2454 90784059Swpaul#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 90884059Swpaul#define BGE_RX_STD_RCB_NICADDR 0x245C 90984059Swpaul#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 91084059Swpaul#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 91184059Swpaul#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 91284059Swpaul#define BGE_RX_MINI_RCB_NICADDR 0x246C 91384059Swpaul#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 91484059Swpaul#define BGE_RDBDI_STD_RX_CONS 0x2474 91584059Swpaul#define BGE_RDBDI_MINI_RX_CONS 0x2478 91684059Swpaul#define BGE_RDBDI_RETURN_PROD0 0x2480 91784059Swpaul#define BGE_RDBDI_RETURN_PROD1 0x2484 91884059Swpaul#define BGE_RDBDI_RETURN_PROD2 0x2488 91984059Swpaul#define BGE_RDBDI_RETURN_PROD3 0x248C 92084059Swpaul#define BGE_RDBDI_RETURN_PROD4 0x2490 92184059Swpaul#define BGE_RDBDI_RETURN_PROD5 0x2494 92284059Swpaul#define BGE_RDBDI_RETURN_PROD6 0x2498 92384059Swpaul#define BGE_RDBDI_RETURN_PROD7 0x249C 92484059Swpaul#define BGE_RDBDI_RETURN_PROD8 0x24A0 92584059Swpaul#define BGE_RDBDI_RETURN_PROD9 0x24A4 92684059Swpaul#define BGE_RDBDI_RETURN_PROD10 0x24A8 92784059Swpaul#define BGE_RDBDI_RETURN_PROD11 0x24AC 92884059Swpaul#define BGE_RDBDI_RETURN_PROD12 0x24B0 92984059Swpaul#define BGE_RDBDI_RETURN_PROD13 0x24B4 93084059Swpaul#define BGE_RDBDI_RETURN_PROD14 0x24B8 93184059Swpaul#define BGE_RDBDI_RETURN_PROD15 0x24BC 93284059Swpaul#define BGE_RDBDI_HWDIAG 0x24C0 93384059Swpaul 93484059Swpaul 93584059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 93684059Swpaul#define BGE_RDBDIMODE_RESET 0x00000001 93784059Swpaul#define BGE_RDBDIMODE_ENABLE 0x00000002 93884059Swpaul#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 93984059Swpaul#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 94084059Swpaul#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 94184059Swpaul 94284059Swpaul/* Receive Data and Receive BD Initiator Status register */ 94384059Swpaul#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 94484059Swpaul#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 94584059Swpaul#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 94684059Swpaul 94784059Swpaul 94884059Swpaul/* 94984059Swpaul * Receive Data Completion Control registers 95084059Swpaul */ 95184059Swpaul#define BGE_RDC_MODE 0x2800 95284059Swpaul 95384059Swpaul/* Receive Data Completion Mode register */ 95484059Swpaul#define BGE_RDCMODE_RESET 0x00000001 95584059Swpaul#define BGE_RDCMODE_ENABLE 0x00000002 95684059Swpaul#define BGE_RDCMODE_ATTN 0x00000004 95784059Swpaul 95884059Swpaul/* 95984059Swpaul * Receive BD Initiator Control registers 96084059Swpaul */ 96184059Swpaul#define BGE_RBDI_MODE 0x2C00 96284059Swpaul#define BGE_RBDI_STATUS 0x2C04 96384059Swpaul#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 96484059Swpaul#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 96584059Swpaul#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 96684059Swpaul#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 96784059Swpaul#define BGE_RBDI_STD_REPL_THRESH 0x2C18 96884059Swpaul#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 96984059Swpaul 97084059Swpaul/* Receive BD Initiator Mode register */ 97184059Swpaul#define BGE_RBDIMODE_RESET 0x00000001 97284059Swpaul#define BGE_RBDIMODE_ENABLE 0x00000002 97384059Swpaul#define BGE_RBDIMODE_ATTN 0x00000004 97484059Swpaul 97584059Swpaul/* Receive BD Initiator Status register */ 97684059Swpaul#define BGE_RBDISTAT_ATTN 0x00000004 97784059Swpaul 97884059Swpaul/* 97984059Swpaul * Receive BD Completion Control registers 98084059Swpaul */ 98184059Swpaul#define BGE_RBDC_MODE 0x3000 98284059Swpaul#define BGE_RBDC_STATUS 0x3004 98384059Swpaul#define BGE_RBDC_JUMBO_BD_PROD 0x3008 98484059Swpaul#define BGE_RBDC_STD_BD_PROD 0x300C 98584059Swpaul#define BGE_RBDC_MINI_BD_PROD 0x3010 98684059Swpaul 98784059Swpaul/* Receive BD completion mode register */ 98884059Swpaul#define BGE_RBDCMODE_RESET 0x00000001 98984059Swpaul#define BGE_RBDCMODE_ENABLE 0x00000002 99084059Swpaul#define BGE_RBDCMODE_ATTN 0x00000004 99184059Swpaul 99284059Swpaul/* Receive BD completion status register */ 99384059Swpaul#define BGE_RBDCSTAT_ERROR 0x00000004 99484059Swpaul 99584059Swpaul/* 99684059Swpaul * Receive List Selector Control registers 99784059Swpaul */ 99884059Swpaul#define BGE_RXLS_MODE 0x3400 99984059Swpaul#define BGE_RXLS_STATUS 0x3404 100084059Swpaul 100184059Swpaul/* Receive List Selector Mode register */ 100284059Swpaul#define BGE_RXLSMODE_RESET 0x00000001 100384059Swpaul#define BGE_RXLSMODE_ENABLE 0x00000002 100484059Swpaul#define BGE_RXLSMODE_ATTN 0x00000004 100584059Swpaul 100684059Swpaul/* Receive List Selector Status register */ 100784059Swpaul#define BGE_RXLSSTAT_ERROR 0x00000004 100884059Swpaul 100984059Swpaul/* 101084059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 101184059Swpaul */ 101284059Swpaul#define BGE_MBCF_MODE 0x3800 101384059Swpaul#define BGE_MBCF_STATUS 0x3804 101484059Swpaul 101584059Swpaul/* Mbuf Cluster Free mode register */ 101684059Swpaul#define BGE_MBCFMODE_RESET 0x00000001 101784059Swpaul#define BGE_MBCFMODE_ENABLE 0x00000002 101884059Swpaul#define BGE_MBCFMODE_ATTN 0x00000004 101984059Swpaul 102084059Swpaul/* Mbuf Cluster Free status register */ 102184059Swpaul#define BGE_MBCFSTAT_ERROR 0x00000004 102284059Swpaul 102384059Swpaul/* 102484059Swpaul * Host Coalescing Control registers 102584059Swpaul */ 102684059Swpaul#define BGE_HCC_MODE 0x3C00 102784059Swpaul#define BGE_HCC_STATUS 0x3C04 102884059Swpaul#define BGE_HCC_RX_COAL_TICKS 0x3C08 102984059Swpaul#define BGE_HCC_TX_COAL_TICKS 0x3C0C 103084059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 103184059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 103284059Swpaul#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 103384059Swpaul#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 103484059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 103584059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 103684059Swpaul#define BGE_HCC_STATS_TICKS 0x3C28 103784059Swpaul#define BGE_HCC_STATS_ADDR_HI 0x3C30 103884059Swpaul#define BGE_HCC_STATS_ADDR_LO 0x3C34 103984059Swpaul#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 104084059Swpaul#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 104184059Swpaul#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 104284059Swpaul#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 104384059Swpaul#define BGE_FLOW_ATTN 0x3C48 104484059Swpaul#define BGE_HCC_JUMBO_BD_CONS 0x3C50 104584059Swpaul#define BGE_HCC_STD_BD_CONS 0x3C54 104684059Swpaul#define BGE_HCC_MINI_BD_CONS 0x3C58 104784059Swpaul#define BGE_HCC_RX_RETURN_PROD0 0x3C80 104884059Swpaul#define BGE_HCC_RX_RETURN_PROD1 0x3C84 104984059Swpaul#define BGE_HCC_RX_RETURN_PROD2 0x3C88 105084059Swpaul#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 105184059Swpaul#define BGE_HCC_RX_RETURN_PROD4 0x3C90 105284059Swpaul#define BGE_HCC_RX_RETURN_PROD5 0x3C94 105384059Swpaul#define BGE_HCC_RX_RETURN_PROD6 0x3C98 105484059Swpaul#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 105584059Swpaul#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 105684059Swpaul#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 105784059Swpaul#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 105884059Swpaul#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 105984059Swpaul#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 106084059Swpaul#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 106184059Swpaul#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 106284059Swpaul#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 106384059Swpaul#define BGE_HCC_TX_BD_CONS0 0x3CC0 106484059Swpaul#define BGE_HCC_TX_BD_CONS1 0x3CC4 106584059Swpaul#define BGE_HCC_TX_BD_CONS2 0x3CC8 106684059Swpaul#define BGE_HCC_TX_BD_CONS3 0x3CCC 106784059Swpaul#define BGE_HCC_TX_BD_CONS4 0x3CD0 106884059Swpaul#define BGE_HCC_TX_BD_CONS5 0x3CD4 106984059Swpaul#define BGE_HCC_TX_BD_CONS6 0x3CD8 107084059Swpaul#define BGE_HCC_TX_BD_CONS7 0x3CDC 107184059Swpaul#define BGE_HCC_TX_BD_CONS8 0x3CE0 107284059Swpaul#define BGE_HCC_TX_BD_CONS9 0x3CE4 107384059Swpaul#define BGE_HCC_TX_BD_CONS10 0x3CE8 107484059Swpaul#define BGE_HCC_TX_BD_CONS11 0x3CEC 107584059Swpaul#define BGE_HCC_TX_BD_CONS12 0x3CF0 107684059Swpaul#define BGE_HCC_TX_BD_CONS13 0x3CF4 107784059Swpaul#define BGE_HCC_TX_BD_CONS14 0x3CF8 107884059Swpaul#define BGE_HCC_TX_BD_CONS15 0x3CFC 107984059Swpaul 108084059Swpaul 108184059Swpaul/* Host coalescing mode register */ 108284059Swpaul#define BGE_HCCMODE_RESET 0x00000001 108384059Swpaul#define BGE_HCCMODE_ENABLE 0x00000002 108484059Swpaul#define BGE_HCCMODE_ATTN 0x00000004 108584059Swpaul#define BGE_HCCMODE_COAL_NOW 0x00000008 108684059Swpaul#define BGE_HCCMODE_MSI_BITS 0x0x000070 108784059Swpaul#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 108884059Swpaul 108984059Swpaul#define BGE_STATBLKSZ_FULL 0x00000000 109084059Swpaul#define BGE_STATBLKSZ_64BYTE 0x00000080 109184059Swpaul#define BGE_STATBLKSZ_32BYTE 0x00000100 109284059Swpaul 109384059Swpaul/* Host coalescing status register */ 109484059Swpaul#define BGE_HCCSTAT_ERROR 0x00000004 109584059Swpaul 109684059Swpaul/* Flow attention register */ 109784059Swpaul#define BGE_FLOWATTN_MB_LOWAT 0x00000040 109884059Swpaul#define BGE_FLOWATTN_MEMARB 0x00000080 109984059Swpaul#define BGE_FLOWATTN_HOSTCOAL 0x00008000 110084059Swpaul#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 110184059Swpaul#define BGE_FLOWATTN_RCB_INVAL 0x00020000 110284059Swpaul#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 110384059Swpaul#define BGE_FLOWATTN_RDBDI 0x00080000 110484059Swpaul#define BGE_FLOWATTN_RXLS 0x00100000 110584059Swpaul#define BGE_FLOWATTN_RXLP 0x00200000 110684059Swpaul#define BGE_FLOWATTN_RBDC 0x00400000 110784059Swpaul#define BGE_FLOWATTN_RBDI 0x00800000 110884059Swpaul#define BGE_FLOWATTN_SDC 0x08000000 110984059Swpaul#define BGE_FLOWATTN_SDI 0x10000000 111084059Swpaul#define BGE_FLOWATTN_SRS 0x20000000 111184059Swpaul#define BGE_FLOWATTN_SBDC 0x40000000 111284059Swpaul#define BGE_FLOWATTN_SBDI 0x80000000 111384059Swpaul 111484059Swpaul/* 111584059Swpaul * Memory arbiter registers 111684059Swpaul */ 111784059Swpaul#define BGE_MARB_MODE 0x4000 111884059Swpaul#define BGE_MARB_STATUS 0x4004 111984059Swpaul#define BGE_MARB_TRAPADDR_HI 0x4008 112084059Swpaul#define BGE_MARB_TRAPADDR_LO 0x400C 112184059Swpaul 112284059Swpaul/* Memory arbiter mode register */ 112384059Swpaul#define BGE_MARBMODE_RESET 0x00000001 112484059Swpaul#define BGE_MARBMODE_ENABLE 0x00000002 112584059Swpaul#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 112684059Swpaul#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 112784059Swpaul#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 112884059Swpaul#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 112984059Swpaul#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 113084059Swpaul#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 113184059Swpaul#define BGE_MARBMODE_PCI_TRAP 0x00000100 113284059Swpaul#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 113384059Swpaul#define BGE_MARBMODE_RXQ_TRAP 0x00000400 113484059Swpaul#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 113584059Swpaul#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 113684059Swpaul#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 113784059Swpaul#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 113884059Swpaul#define BGE_MARBMODE_MBUF_TRAP 0x00008000 113984059Swpaul#define BGE_MARBMODE_TXDI_TRAP 0x00010000 114084059Swpaul#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 114184059Swpaul#define BGE_MARBMODE_TXBD_TRAP 0x00040000 114284059Swpaul#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 114384059Swpaul#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 114484059Swpaul#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 114584059Swpaul#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 114684059Swpaul#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 114784059Swpaul#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 114884059Swpaul#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 114984059Swpaul 115084059Swpaul/* Memory arbiter status register */ 115184059Swpaul#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 115284059Swpaul#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 115384059Swpaul#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 115484059Swpaul#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 115584059Swpaul#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 115684059Swpaul#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 115784059Swpaul#define BGE_MARBSTAT_PCI_TRAP 0x00000100 115884059Swpaul#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 115984059Swpaul#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 116084059Swpaul#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 116184059Swpaul#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 116284059Swpaul#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 116384059Swpaul#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 116484059Swpaul#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 116584059Swpaul#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 116684059Swpaul#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 116784059Swpaul#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 116884059Swpaul#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 116984059Swpaul#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 117084059Swpaul#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 117184059Swpaul#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 117284059Swpaul#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 117384059Swpaul#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 117484059Swpaul#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 117584059Swpaul 117684059Swpaul/* 117784059Swpaul * Buffer manager control registers 117884059Swpaul */ 117984059Swpaul#define BGE_BMAN_MODE 0x4400 118084059Swpaul#define BGE_BMAN_STATUS 0x4404 118184059Swpaul#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 118284059Swpaul#define BGE_BMAN_MBUFPOOL_LEN 0x440C 118384059Swpaul#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 118484059Swpaul#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 118584059Swpaul#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 118684059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 118784059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 118884059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 118984059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 119084059Swpaul#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 119184059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 119284059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 119384059Swpaul#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 119484059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 119584059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 119684059Swpaul#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 119784059Swpaul#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 119884059Swpaul#define BGE_BMAN_HWDIAG_1 0x444C 119984059Swpaul#define BGE_BMAN_HWDIAG_2 0x4450 120084059Swpaul#define BGE_BMAN_HWDIAG_3 0x4454 120184059Swpaul 120284059Swpaul/* Buffer manager mode register */ 120384059Swpaul#define BGE_BMANMODE_RESET 0x00000001 120484059Swpaul#define BGE_BMANMODE_ENABLE 0x00000002 120584059Swpaul#define BGE_BMANMODE_ATTN 0x00000004 120684059Swpaul#define BGE_BMANMODE_TESTMODE 0x00000008 120784059Swpaul#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 120884059Swpaul 120984059Swpaul/* Buffer manager status register */ 121084059Swpaul#define BGE_BMANSTAT_ERRO 0x00000004 121184059Swpaul#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 121284059Swpaul 121384059Swpaul 121484059Swpaul/* 121584059Swpaul * Read DMA Control registers 121684059Swpaul */ 121784059Swpaul#define BGE_RDMA_MODE 0x4800 121884059Swpaul#define BGE_RDMA_STATUS 0x4804 121984059Swpaul 122084059Swpaul/* Read DMA mode register */ 122184059Swpaul#define BGE_RDMAMODE_RESET 0x00000001 122284059Swpaul#define BGE_RDMAMODE_ENABLE 0x00000002 122384059Swpaul#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 122484059Swpaul#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 122584059Swpaul#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 122684059Swpaul#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 122784059Swpaul#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 122884059Swpaul#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 122984059Swpaul#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 123084059Swpaul#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 123184059Swpaul#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 123284059Swpaul 123384059Swpaul/* Read DMA status register */ 123484059Swpaul#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 123584059Swpaul#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 123684059Swpaul#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 123784059Swpaul#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 123884059Swpaul#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 123984059Swpaul#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 124084059Swpaul#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 124184059Swpaul#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 124284059Swpaul 124384059Swpaul/* 124484059Swpaul * Write DMA control registers 124584059Swpaul */ 124684059Swpaul#define BGE_WDMA_MODE 0x4C00 124784059Swpaul#define BGE_WDMA_STATUS 0x4C04 124884059Swpaul 124984059Swpaul/* Write DMA mode register */ 125084059Swpaul#define BGE_WDMAMODE_RESET 0x00000001 125184059Swpaul#define BGE_WDMAMODE_ENABLE 0x00000002 125284059Swpaul#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 125384059Swpaul#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 125484059Swpaul#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 125584059Swpaul#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 125684059Swpaul#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 125784059Swpaul#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 125884059Swpaul#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 125984059Swpaul#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 126084059Swpaul#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 126184059Swpaul 126284059Swpaul/* Write DMA status register */ 126384059Swpaul#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 126484059Swpaul#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 126584059Swpaul#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 126684059Swpaul#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 126784059Swpaul#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 126884059Swpaul#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 126984059Swpaul#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 127084059Swpaul#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 127184059Swpaul 127284059Swpaul 127384059Swpaul/* 127484059Swpaul * RX CPU registers 127584059Swpaul */ 127684059Swpaul#define BGE_RXCPU_MODE 0x5000 127784059Swpaul#define BGE_RXCPU_STATUS 0x5004 127884059Swpaul#define BGE_RXCPU_PC 0x501C 127984059Swpaul 128084059Swpaul/* RX CPU mode register */ 128184059Swpaul#define BGE_RXCPUMODE_RESET 0x00000001 128284059Swpaul#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 128384059Swpaul#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 128484059Swpaul#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 128584059Swpaul#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 128684059Swpaul#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 128784059Swpaul#define BGE_RXCPUMODE_ROMFAIL 0x00000040 128884059Swpaul#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 128984059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 129084059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 129184059Swpaul#define BGE_RXCPUMODE_HALTCPU 0x00000400 129284059Swpaul#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 129384059Swpaul#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 129484059Swpaul#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 129584059Swpaul 129684059Swpaul/* RX CPU status register */ 129784059Swpaul#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 129884059Swpaul#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 129984059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 130084059Swpaul#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 130184059Swpaul#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 130284059Swpaul#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 130384059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 130484059Swpaul#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 130584059Swpaul#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 130684059Swpaul#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 130784059Swpaul#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 130884059Swpaul#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 130984059Swpaul#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 131084059Swpaul#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 131184059Swpaul#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 131284059Swpaul#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 131384059Swpaul#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 131484059Swpaul 131584059Swpaul 131684059Swpaul/* 131784059Swpaul * TX CPU registers 131884059Swpaul */ 131984059Swpaul#define BGE_TXCPU_MODE 0x5400 132084059Swpaul#define BGE_TXCPU_STATUS 0x5404 132184059Swpaul#define BGE_TXCPU_PC 0x541C 132284059Swpaul 132384059Swpaul/* TX CPU mode register */ 132484059Swpaul#define BGE_TXCPUMODE_RESET 0x00000001 132584059Swpaul#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 132684059Swpaul#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 132784059Swpaul#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 132884059Swpaul#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 132984059Swpaul#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 133084059Swpaul#define BGE_TXCPUMODE_ROMFAIL 0x00000040 133184059Swpaul#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 133284059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 133384059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 133484059Swpaul#define BGE_TXCPUMODE_HALTCPU 0x00000400 133584059Swpaul#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 133684059Swpaul#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 133784059Swpaul 133884059Swpaul/* TX CPU status register */ 133984059Swpaul#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 134084059Swpaul#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 134184059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 134284059Swpaul#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 134384059Swpaul#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 134484059Swpaul#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 134584059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 134684059Swpaul#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 134784059Swpaul#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 134884059Swpaul#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 134984059Swpaul#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 135084059Swpaul#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 135184059Swpaul#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 135284059Swpaul#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 135384059Swpaul#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 135484059Swpaul#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 135584059Swpaul#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 135684059Swpaul 135784059Swpaul 135884059Swpaul/* 135984059Swpaul * Low priority mailbox registers 136084059Swpaul */ 136184059Swpaul#define BGE_LPMBX_IRQ0_HI 0x5800 136284059Swpaul#define BGE_LPMBX_IRQ0_LO 0x5804 136384059Swpaul#define BGE_LPMBX_IRQ1_HI 0x5808 136484059Swpaul#define BGE_LPMBX_IRQ1_LO 0x580C 136584059Swpaul#define BGE_LPMBX_IRQ2_HI 0x5810 136684059Swpaul#define BGE_LPMBX_IRQ2_LO 0x5814 136784059Swpaul#define BGE_LPMBX_IRQ3_HI 0x5818 136884059Swpaul#define BGE_LPMBX_IRQ3_LO 0x581C 136984059Swpaul#define BGE_LPMBX_GEN0_HI 0x5820 137084059Swpaul#define BGE_LPMBX_GEN0_LO 0x5824 137184059Swpaul#define BGE_LPMBX_GEN1_HI 0x5828 137284059Swpaul#define BGE_LPMBX_GEN1_LO 0x582C 137384059Swpaul#define BGE_LPMBX_GEN2_HI 0x5830 137484059Swpaul#define BGE_LPMBX_GEN2_LO 0x5834 137584059Swpaul#define BGE_LPMBX_GEN3_HI 0x5828 137684059Swpaul#define BGE_LPMBX_GEN3_LO 0x582C 137784059Swpaul#define BGE_LPMBX_GEN4_HI 0x5840 137884059Swpaul#define BGE_LPMBX_GEN4_LO 0x5844 137984059Swpaul#define BGE_LPMBX_GEN5_HI 0x5848 138084059Swpaul#define BGE_LPMBX_GEN5_LO 0x584C 138184059Swpaul#define BGE_LPMBX_GEN6_HI 0x5850 138284059Swpaul#define BGE_LPMBX_GEN6_LO 0x5854 138384059Swpaul#define BGE_LPMBX_GEN7_HI 0x5858 138484059Swpaul#define BGE_LPMBX_GEN7_LO 0x585C 138584059Swpaul#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 138684059Swpaul#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 138784059Swpaul#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 138884059Swpaul#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 138984059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 139084059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 139184059Swpaul#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 139284059Swpaul#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 139384059Swpaul#define BGE_LPMBX_RX_CONS0_HI 0x5880 139484059Swpaul#define BGE_LPMBX_RX_CONS0_LO 0x5884 139584059Swpaul#define BGE_LPMBX_RX_CONS1_HI 0x5888 139684059Swpaul#define BGE_LPMBX_RX_CONS1_LO 0x588C 139784059Swpaul#define BGE_LPMBX_RX_CONS2_HI 0x5890 139884059Swpaul#define BGE_LPMBX_RX_CONS2_LO 0x5894 139984059Swpaul#define BGE_LPMBX_RX_CONS3_HI 0x5898 140084059Swpaul#define BGE_LPMBX_RX_CONS3_LO 0x589C 140184059Swpaul#define BGE_LPMBX_RX_CONS4_HI 0x58A0 140284059Swpaul#define BGE_LPMBX_RX_CONS4_LO 0x58A4 140384059Swpaul#define BGE_LPMBX_RX_CONS5_HI 0x58A8 140484059Swpaul#define BGE_LPMBX_RX_CONS5_LO 0x58AC 140584059Swpaul#define BGE_LPMBX_RX_CONS6_HI 0x58B0 140684059Swpaul#define BGE_LPMBX_RX_CONS6_LO 0x58B4 140784059Swpaul#define BGE_LPMBX_RX_CONS7_HI 0x58B8 140884059Swpaul#define BGE_LPMBX_RX_CONS7_LO 0x58BC 140984059Swpaul#define BGE_LPMBX_RX_CONS8_HI 0x58C0 141084059Swpaul#define BGE_LPMBX_RX_CONS8_LO 0x58C4 141184059Swpaul#define BGE_LPMBX_RX_CONS9_HI 0x58C8 141284059Swpaul#define BGE_LPMBX_RX_CONS9_LO 0x58CC 141384059Swpaul#define BGE_LPMBX_RX_CONS10_HI 0x58D0 141484059Swpaul#define BGE_LPMBX_RX_CONS10_LO 0x58D4 141584059Swpaul#define BGE_LPMBX_RX_CONS11_HI 0x58D8 141684059Swpaul#define BGE_LPMBX_RX_CONS11_LO 0x58DC 141784059Swpaul#define BGE_LPMBX_RX_CONS12_HI 0x58E0 141884059Swpaul#define BGE_LPMBX_RX_CONS12_LO 0x58E4 141984059Swpaul#define BGE_LPMBX_RX_CONS13_HI 0x58E8 142084059Swpaul#define BGE_LPMBX_RX_CONS13_LO 0x58EC 142184059Swpaul#define BGE_LPMBX_RX_CONS14_HI 0x58F0 142284059Swpaul#define BGE_LPMBX_RX_CONS14_LO 0x58F4 142384059Swpaul#define BGE_LPMBX_RX_CONS15_HI 0x58F8 142484059Swpaul#define BGE_LPMBX_RX_CONS15_LO 0x58FC 142584059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 142684059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 142784059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 142884059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 142984059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 143084059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 143184059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 143284059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 143384059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 143484059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 143584059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 143684059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 143784059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 143884059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 143984059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 144084059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 144184059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 144284059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 144384059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 144484059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 144584059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 144684059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 144784059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 144884059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 144984059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 145084059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 145184059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 145284059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 145384059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 145484059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 145584059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 145684059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 145784059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 145884059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 145984059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 146084059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 146184059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 146284059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 146384059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 146484059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 146584059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 146684059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 146784059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 146884059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 146984059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 147084059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 147184059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 147284059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 147384059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 147484059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 147584059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 147684059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 147784059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 147884059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 147984059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 148084059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 148184059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 148284059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 148384059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 148484059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 148584059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 148684059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 148784059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 148884059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 148984059Swpaul 149084059Swpaul/* 149184059Swpaul * Flow throw Queue reset register 149284059Swpaul */ 149384059Swpaul#define BGE_FTQ_RESET 0x5C00 149484059Swpaul 149584059Swpaul#define BGE_FTQRESET_DMAREAD 0x00000002 149684059Swpaul#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 149784059Swpaul#define BGE_FTQRESET_DMADONE 0x00000010 149884059Swpaul#define BGE_FTQRESET_SBDC 0x00000020 149984059Swpaul#define BGE_FTQRESET_SDI 0x00000040 150084059Swpaul#define BGE_FTQRESET_WDMA 0x00000080 150184059Swpaul#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 150284059Swpaul#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 150384059Swpaul#define BGE_FTQRESET_SDC 0x00000400 150484059Swpaul#define BGE_FTQRESET_HCC 0x00000800 150584059Swpaul#define BGE_FTQRESET_TXFIFO 0x00001000 150684059Swpaul#define BGE_FTQRESET_MBC 0x00002000 150784059Swpaul#define BGE_FTQRESET_RBDC 0x00004000 150884059Swpaul#define BGE_FTQRESET_RXLP 0x00008000 150984059Swpaul#define BGE_FTQRESET_RDBDI 0x00010000 151084059Swpaul#define BGE_FTQRESET_RDC 0x00020000 151184059Swpaul#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 151284059Swpaul 151384059Swpaul/* 151484059Swpaul * Message Signaled Interrupt registers 151584059Swpaul */ 151684059Swpaul#define BGE_MSI_MODE 0x6000 151784059Swpaul#define BGE_MSI_STATUS 0x6004 151884059Swpaul#define BGE_MSI_FIFOACCESS 0x6008 151984059Swpaul 152084059Swpaul/* MSI mode register */ 152184059Swpaul#define BGE_MSIMODE_RESET 0x00000001 152284059Swpaul#define BGE_MSIMODE_ENABLE 0x00000002 152384059Swpaul#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 152484059Swpaul#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 152584059Swpaul#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 152684059Swpaul#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 152784059Swpaul#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 152884059Swpaul 152984059Swpaul/* MSI status register */ 153084059Swpaul#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 153184059Swpaul#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 153284059Swpaul#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 153384059Swpaul#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 153484059Swpaul#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 153584059Swpaul 153684059Swpaul 153784059Swpaul/* 153884059Swpaul * DMA Completion registers 153984059Swpaul */ 154084059Swpaul#define BGE_DMAC_MODE 0x6400 154184059Swpaul 154284059Swpaul/* DMA Completion mode register */ 154384059Swpaul#define BGE_DMACMODE_RESET 0x00000001 154484059Swpaul#define BGE_DMACMODE_ENABLE 0x00000002 154584059Swpaul 154684059Swpaul 154784059Swpaul/* 154884059Swpaul * General control registers. 154984059Swpaul */ 155084059Swpaul#define BGE_MODE_CTL 0x6800 155184059Swpaul#define BGE_MISC_CFG 0x6804 155284059Swpaul#define BGE_MISC_LOCAL_CTL 0x6808 155384059Swpaul#define BGE_EE_ADDR 0x6838 155484059Swpaul#define BGE_EE_DATA 0x683C 155584059Swpaul#define BGE_EE_CTL 0x6840 155684059Swpaul#define BGE_MDI_CTL 0x6844 155784059Swpaul#define BGE_EE_DELAY 0x6848 155884059Swpaul 155984059Swpaul/* Mode control register */ 156084059Swpaul#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 156184059Swpaul#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 156284059Swpaul#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 156384059Swpaul#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 156484059Swpaul#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 156584059Swpaul#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 156684059Swpaul#define BGE_MODECTL_NO_RX_CRC 0x00000400 156784059Swpaul#define BGE_MODECTL_RX_BADFRAMES 0x00000800 156884059Swpaul#define BGE_MODECTL_NO_TX_INTR 0x00002000 156984059Swpaul#define BGE_MODECTL_NO_RX_INTR 0x00004000 157084059Swpaul#define BGE_MODECTL_FORCE_PCI32 0x00008000 157184059Swpaul#define BGE_MODECTL_STACKUP 0x00010000 157284059Swpaul#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 157384059Swpaul#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 157484059Swpaul#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 157584059Swpaul#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 157684059Swpaul#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 157784059Swpaul#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 157884059Swpaul#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 157984059Swpaul#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 158084059Swpaul#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 158184059Swpaul#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 158284059Swpaul 158384059Swpaul/* Misc. config register */ 158484059Swpaul#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 158584059Swpaul#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 158684059Swpaul 158784059Swpaul#define BGE_32BITTIME_66MHZ (0x41 << 1) 158884059Swpaul 158984059Swpaul/* Misc. Local Control */ 159084059Swpaul#define BGE_MLC_INTR_STATE 0x00000001 159184059Swpaul#define BGE_MLC_INTR_CLR 0x00000002 159284059Swpaul#define BGE_MLC_INTR_SET 0x00000004 159384059Swpaul#define BGE_MLC_INTR_ONATTN 0x00000008 159484059Swpaul#define BGE_MLC_MISCIO_IN0 0x00000100 159584059Swpaul#define BGE_MLC_MISCIO_IN1 0x00000200 159684059Swpaul#define BGE_MLC_MISCIO_IN2 0x00000400 159784059Swpaul#define BGE_MLC_MISCIO_OUTEN0 0x00000800 159884059Swpaul#define BGE_MLC_MISCIO_OUTEN1 0x00001000 159984059Swpaul#define BGE_MLC_MISCIO_OUTEN2 0x00002000 160084059Swpaul#define BGE_MLC_MISCIO_OUT0 0x00004000 160184059Swpaul#define BGE_MLC_MISCIO_OUT1 0x00008000 160284059Swpaul#define BGE_MLC_MISCIO_OUT2 0x00010000 160384059Swpaul#define BGE_MLC_EXTRAM_ENB 0x00020000 160484059Swpaul#define BGE_MLC_SRAM_SIZE 0x001C0000 160584059Swpaul#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 160684059Swpaul#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 160784059Swpaul#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 160884059Swpaul#define BGE_MLC_AUTO_EEPROM 0x01000000 160984059Swpaul 161084059Swpaul#define BGE_SSRAMSIZE_256KB 0x00000000 161184059Swpaul#define BGE_SSRAMSIZE_512KB 0x00040000 161284059Swpaul#define BGE_SSRAMSIZE_1MB 0x00080000 161384059Swpaul#define BGE_SSRAMSIZE_2MB 0x000C0000 161484059Swpaul#define BGE_SSRAMSIZE_4MB 0x00100000 161584059Swpaul#define BGE_SSRAMSIZE_8MB 0x00140000 161684059Swpaul#define BGE_SSRAMSIZE_16M 0x00180000 161784059Swpaul 161884059Swpaul/* EEPROM address register */ 161984059Swpaul#define BGE_EEADDR_ADDRESS 0x0000FFFC 162084059Swpaul#define BGE_EEADDR_HALFCLK 0x01FF0000 162184059Swpaul#define BGE_EEADDR_START 0x02000000 162284059Swpaul#define BGE_EEADDR_DEVID 0x1C000000 162384059Swpaul#define BGE_EEADDR_RESET 0x20000000 162484059Swpaul#define BGE_EEADDR_DONE 0x40000000 162584059Swpaul#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 162684059Swpaul 162784059Swpaul#define BGE_EEDEVID(x) ((x & 7) << 26) 162884059Swpaul#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 162984059Swpaul#define BGE_HALFCLK_384SCL 0x60 163084059Swpaul#define BGE_EE_READCMD \ 163184059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 163284059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 163384059Swpaul#define BGE_EE_WRCMD \ 163484059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 163584059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 163684059Swpaul 163784059Swpaul/* EEPROM Control register */ 163884059Swpaul#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 163984059Swpaul#define BGE_EECTL_CLKOUT 0x00000002 164084059Swpaul#define BGE_EECTL_CLKIN 0x00000004 164184059Swpaul#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 164284059Swpaul#define BGE_EECTL_DATAOUT 0x00000010 164384059Swpaul#define BGE_EECTL_DATAIN 0x00000020 164484059Swpaul 164584059Swpaul/* MDI (MII/GMII) access register */ 164684059Swpaul#define BGE_MDI_DATA 0x00000001 164784059Swpaul#define BGE_MDI_DIR 0x00000002 164884059Swpaul#define BGE_MDI_SEL 0x00000004 164984059Swpaul#define BGE_MDI_CLK 0x00000008 165084059Swpaul 165184059Swpaul#define BGE_MEMWIN_START 0x00008000 165284059Swpaul#define BGE_MEMWIN_END 0x0000FFFF 165384059Swpaul 165484059Swpaul 165584059Swpaul#define BGE_MEMWIN_READ(sc, x, val) \ 165684059Swpaul do { \ 165784059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 165884059Swpaul (0xFFFF0000 & x), 4); \ 165984059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 166084059Swpaul } while(0) 166184059Swpaul 166284059Swpaul#define BGE_MEMWIN_WRITE(sc, x, val) \ 166384059Swpaul do { \ 166484059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 166584059Swpaul (0xFFFF0000 & x), 4); \ 166684059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 166784059Swpaul } while(0) 166884059Swpaul 166984059Swpaul/* 167084059Swpaul * This magic number is used to prevent PXE restart when we 167184059Swpaul * issue a software reset. We write this magic number to the 167284059Swpaul * firmware mailbox at 0xB50 in order to prevent the PXE boot 167384059Swpaul * code from running. 167484059Swpaul */ 167584059Swpaul#define BGE_MAGIC_NUMBER 0x4B657654 167684059Swpaul 167784059Swpaultypedef struct { 167884059Swpaul u_int32_t bge_addr_hi; 167984059Swpaul u_int32_t bge_addr_lo; 168084059Swpaul} bge_hostaddr; 1681108847Sjdp#define BGE_HOSTADDR(x) ((x).bge_addr_lo) 168284059Swpaul 168384059Swpaul/* Ring control block structure */ 168484059Swpaulstruct bge_rcb { 168584059Swpaul bge_hostaddr bge_hostaddr; 1686108847Sjdp u_int32_t bge_maxlen_flags; 168784059Swpaul u_int32_t bge_nicaddr; 168884059Swpaul}; 1689108847Sjdp#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 169084059Swpaul 169184059Swpaul#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 169284059Swpaul#define BGE_RCB_FLAG_RING_DISABLED 0x0002 169384059Swpaul 169484059Swpaulstruct bge_tx_bd { 169584059Swpaul bge_hostaddr bge_addr; 169684059Swpaul u_int16_t bge_flags; 169784059Swpaul u_int16_t bge_len; 169884059Swpaul u_int16_t bge_vlan_tag; 169984059Swpaul u_int16_t bge_rsvd; 170084059Swpaul}; 170184059Swpaul 170284059Swpaul#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 170384059Swpaul#define BGE_TXBDFLAG_IP_CSUM 0x0002 170484059Swpaul#define BGE_TXBDFLAG_END 0x0004 170584059Swpaul#define BGE_TXBDFLAG_IP_FRAG 0x0008 170684059Swpaul#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 170784059Swpaul#define BGE_TXBDFLAG_VLAN_TAG 0x0040 170884059Swpaul#define BGE_TXBDFLAG_COAL_NOW 0x0080 170984059Swpaul#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 171084059Swpaul#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 171184059Swpaul#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 171284059Swpaul#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 171384059Swpaul#define BGE_TXBDFLAG_NO_CRC 0x8000 171484059Swpaul 171584059Swpaul#define BGE_NIC_TXRING_ADDR(ringno, size) \ 171684059Swpaul BGE_SEND_RING_1_TO_4 + \ 171784059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 171884059Swpaul 171984059Swpaulstruct bge_rx_bd { 172084059Swpaul bge_hostaddr bge_addr; 172184059Swpaul u_int16_t bge_len; 172284059Swpaul u_int16_t bge_idx; 172384059Swpaul u_int16_t bge_flags; 172484059Swpaul u_int16_t bge_type; 172584059Swpaul u_int16_t bge_tcp_udp_csum; 172684059Swpaul u_int16_t bge_ip_csum; 172784059Swpaul u_int16_t bge_vlan_tag; 172884059Swpaul u_int16_t bge_error_flag; 172984059Swpaul u_int32_t bge_rsvd; 173084059Swpaul u_int32_t bge_opaque; 173184059Swpaul}; 173284059Swpaul 173384059Swpaul#define BGE_RXBDFLAG_END 0x0004 173484059Swpaul#define BGE_RXBDFLAG_JUMBO_RING 0x0020 173584059Swpaul#define BGE_RXBDFLAG_VLAN_TAG 0x0040 173684059Swpaul#define BGE_RXBDFLAG_ERROR 0x0400 173784059Swpaul#define BGE_RXBDFLAG_MINI_RING 0x0800 173884059Swpaul#define BGE_RXBDFLAG_IP_CSUM 0x1000 173984059Swpaul#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 174084059Swpaul#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 174184059Swpaul 174284059Swpaul#define BGE_RXERRFLAG_BAD_CRC 0x0001 174384059Swpaul#define BGE_RXERRFLAG_COLL_DETECT 0x0002 174484059Swpaul#define BGE_RXERRFLAG_LINK_LOST 0x0004 174584059Swpaul#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 174684059Swpaul#define BGE_RXERRFLAG_MAC_ABORT 0x0010 174784059Swpaul#define BGE_RXERRFLAG_RUNT 0x0020 174884059Swpaul#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 174984059Swpaul#define BGE_RXERRFLAG_GIANT 0x0080 175084059Swpaul 175184059Swpaulstruct bge_sts_idx { 175284059Swpaul u_int16_t bge_rx_prod_idx; 175384059Swpaul u_int16_t bge_tx_cons_idx; 175484059Swpaul}; 175584059Swpaul 175684059Swpaulstruct bge_status_block { 175784059Swpaul u_int32_t bge_status; 175884059Swpaul u_int32_t bge_rsvd0; 175984059Swpaul u_int16_t bge_rx_jumbo_cons_idx; 176084059Swpaul u_int16_t bge_rx_std_cons_idx; 176184059Swpaul u_int16_t bge_rx_mini_cons_idx; 176284059Swpaul u_int16_t bge_rsvd1; 176384059Swpaul struct bge_sts_idx bge_idx[16]; 176484059Swpaul}; 176584059Swpaul 176684059Swpaul#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 176784059Swpaul#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 176884059Swpaul 176984059Swpaul#define BGE_STATFLAG_UPDATED 0x00000001 177084059Swpaul#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 177184059Swpaul#define BGE_STATFLAG_ERROR 0x00000004 177284059Swpaul 177384059Swpaul 177484059Swpaul/* 177584059Swpaul * Broadcom Vendor ID 177684059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 177784059Swpaul * even though they're now manufactured by Broadcom) 177884059Swpaul */ 177984059Swpaul#define BCOM_VENDORID 0x14E4 178084059Swpaul#define BCOM_DEVICEID_BCM5700 0x1644 178184059Swpaul#define BCOM_DEVICEID_BCM5701 0x1645 1782104102Siwasaki#define BCOM_DEVICEID_BCM5702X 0x16A6 1783103103Sjdp#define BCOM_DEVICEID_BCM5703X 0x16A7 178484059Swpaul 178584059Swpaul/* 178684059Swpaul * Alteon AceNIC PCI vendor/device ID. 178784059Swpaul */ 178884059Swpaul#define ALT_VENDORID 0x12AE 178984059Swpaul#define ALT_DEVICEID_ACENIC 0x0001 179084059Swpaul#define ALT_DEVICEID_ACENIC_COPPER 0x0002 179184059Swpaul#define ALT_DEVICEID_BCM5700 0x0003 179284059Swpaul#define ALT_DEVICEID_BCM5701 0x0004 179384059Swpaul 179484059Swpaul/* 179584059Swpaul * 3Com 3c985 PCI vendor/device ID. 179684059Swpaul */ 179784059Swpaul#define TC_VENDORID 0x10B7 179884059Swpaul#define TC_DEVICEID_3C985 0x0001 179984059Swpaul#define TC_DEVICEID_3C996 0x0003 180084059Swpaul 180184059Swpaul/* 180284059Swpaul * SysKonnect PCI vendor ID 180384059Swpaul */ 180484059Swpaul#define SK_VENDORID 0x1148 180584059Swpaul#define SK_DEVICEID_ALTIMA 0x4400 180684059Swpaul#define SK_SUBSYSID_9D21 0x4421 180784059Swpaul#define SK_SUBSYSID_9D41 0x4441 180884059Swpaul 180984059Swpaul/* 181089835Sjdp * Altima PCI vendor/device ID. 181189835Sjdp */ 181289835Sjdp#define ALTIMA_VENDORID 0x173b 181389835Sjdp#define ALTIMA_DEVICE_AC1000 0x03e8 1814100695Sjdp#define ALTIMA_DEVICE_AC9100 0x03ea 181589835Sjdp 181689835Sjdp/* 181784059Swpaul * Offset of MAC address inside EEPROM. 181884059Swpaul */ 181984059Swpaul#define BGE_EE_MAC_OFFSET 0x7C 182084059Swpaul#define BGE_EE_HWCFG_OFFSET 0xC8 182184059Swpaul 182293751Swpaul#define BGE_HWCFG_VOLTAGE 0x00000003 182393751Swpaul#define BGE_HWCFG_PHYLED_MODE 0x0000000C 182493751Swpaul#define BGE_HWCFG_MEDIA 0x00000030 182593751Swpaul 182693751Swpaul#define BGE_VOLTAGE_1POINT3 0x00000000 182793751Swpaul#define BGE_VOLTAGE_1POINT8 0x00000001 182893751Swpaul 182993751Swpaul#define BGE_PHYLEDMODE_UNSPEC 0x00000000 183093751Swpaul#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 183193751Swpaul#define BGE_PHYLEDMODE_SINGLELED 0x00000008 183293751Swpaul 183393751Swpaul#define BGE_MEDIA_UNSPEC 0x00000000 183493751Swpaul#define BGE_MEDIA_COPPER 0x00000010 183593751Swpaul#define BGE_MEDIA_FIBER 0x00000020 183693751Swpaul 183784059Swpaul#define BGE_PCI_READ_CMD 0x06000000 183884059Swpaul#define BGE_PCI_WRITE_CMD 0x70000000 183984059Swpaul 184084059Swpaul#define BGE_TICKS_PER_SEC 1000000 184184059Swpaul 184284059Swpaul/* 184384059Swpaul * Ring size constants. 184484059Swpaul */ 184584059Swpaul#define BGE_EVENT_RING_CNT 256 184684059Swpaul#define BGE_CMD_RING_CNT 64 184784059Swpaul#define BGE_STD_RX_RING_CNT 512 184884059Swpaul#define BGE_JUMBO_RX_RING_CNT 256 184984059Swpaul#define BGE_MINI_RX_RING_CNT 1024 185084059Swpaul#define BGE_RETURN_RING_CNT 1024 185184059Swpaul 185284059Swpaul/* 185384059Swpaul * Possible TX ring sizes. 185484059Swpaul */ 185584059Swpaul#define BGE_TX_RING_CNT_128 128 185684059Swpaul#define BGE_TX_RING_BASE_128 0x3800 185784059Swpaul 185884059Swpaul#define BGE_TX_RING_CNT_256 256 185984059Swpaul#define BGE_TX_RING_BASE_256 0x3000 186084059Swpaul 186184059Swpaul#define BGE_TX_RING_CNT_512 512 186284059Swpaul#define BGE_TX_RING_BASE_512 0x2000 186384059Swpaul 186484059Swpaul#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 186584059Swpaul#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 186684059Swpaul 186784059Swpaul/* 186884059Swpaul * Tigon III statistics counters. 186984059Swpaul */ 187084059Swpaulstruct bge_stats { 187184059Swpaul u_int8_t Reserved0[256]; 187284059Swpaul 187384059Swpaul /* Statistics maintained by Receive MAC. */ 187484059Swpaul bge_hostaddr ifHCInOctets; 187584059Swpaul bge_hostaddr Reserved1; 187684059Swpaul bge_hostaddr etherStatsFragments; 187784059Swpaul bge_hostaddr ifHCInUcastPkts; 187884059Swpaul bge_hostaddr ifHCInMulticastPkts; 187984059Swpaul bge_hostaddr ifHCInBroadcastPkts; 188084059Swpaul bge_hostaddr dot3StatsFCSErrors; 188184059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 188284059Swpaul bge_hostaddr xonPauseFramesReceived; 188384059Swpaul bge_hostaddr xoffPauseFramesReceived; 188484059Swpaul bge_hostaddr macControlFramesReceived; 188584059Swpaul bge_hostaddr xoffStateEntered; 188684059Swpaul bge_hostaddr dot3StatsFramesTooLong; 188784059Swpaul bge_hostaddr etherStatsJabbers; 188884059Swpaul bge_hostaddr etherStatsUndersizePkts; 188984059Swpaul bge_hostaddr inRangeLengthError; 189084059Swpaul bge_hostaddr outRangeLengthError; 189184059Swpaul bge_hostaddr etherStatsPkts64Octets; 189284059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 189384059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 189484059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 189584059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 189684059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 189784059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 189884059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 189984059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 190084059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 190184059Swpaul 190284059Swpaul bge_hostaddr Unused1[37]; 190384059Swpaul 190484059Swpaul /* Statistics maintained by Transmit MAC. */ 190584059Swpaul bge_hostaddr ifHCOutOctets; 190684059Swpaul bge_hostaddr Reserved2; 190784059Swpaul bge_hostaddr etherStatsCollisions; 190884059Swpaul bge_hostaddr outXonSent; 190984059Swpaul bge_hostaddr outXoffSent; 191084059Swpaul bge_hostaddr flowControlDone; 191184059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 191284059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 191384059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 191484059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 191584059Swpaul bge_hostaddr Reserved3; 191684059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 191784059Swpaul bge_hostaddr dot3StatsLateCollisions; 191884059Swpaul bge_hostaddr dot3Collided2Times; 191984059Swpaul bge_hostaddr dot3Collided3Times; 192084059Swpaul bge_hostaddr dot3Collided4Times; 192184059Swpaul bge_hostaddr dot3Collided5Times; 192284059Swpaul bge_hostaddr dot3Collided6Times; 192384059Swpaul bge_hostaddr dot3Collided7Times; 192484059Swpaul bge_hostaddr dot3Collided8Times; 192584059Swpaul bge_hostaddr dot3Collided9Times; 192684059Swpaul bge_hostaddr dot3Collided10Times; 192784059Swpaul bge_hostaddr dot3Collided11Times; 192884059Swpaul bge_hostaddr dot3Collided12Times; 192984059Swpaul bge_hostaddr dot3Collided13Times; 193084059Swpaul bge_hostaddr dot3Collided14Times; 193184059Swpaul bge_hostaddr dot3Collided15Times; 193284059Swpaul bge_hostaddr ifHCOutUcastPkts; 193384059Swpaul bge_hostaddr ifHCOutMulticastPkts; 193484059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 193584059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 193684059Swpaul bge_hostaddr ifOutDiscards; 193784059Swpaul bge_hostaddr ifOutErrors; 193884059Swpaul 193984059Swpaul bge_hostaddr Unused2[31]; 194084059Swpaul 194184059Swpaul /* Statistics maintained by Receive List Placement. */ 194284059Swpaul bge_hostaddr COSIfHCInPkts[16]; 194384059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 194484059Swpaul bge_hostaddr nicDmaWriteQueueFull; 194584059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 194684059Swpaul bge_hostaddr nicNoMoreRxBDs; 194784059Swpaul bge_hostaddr ifInDiscards; 194884059Swpaul bge_hostaddr ifInErrors; 194984059Swpaul bge_hostaddr nicRecvThresholdHit; 195084059Swpaul 195184059Swpaul bge_hostaddr Unused3[9]; 195284059Swpaul 195384059Swpaul /* Statistics maintained by Send Data Initiator. */ 195484059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 195584059Swpaul bge_hostaddr nicDmaReadQueueFull; 195684059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 195784059Swpaul bge_hostaddr nicSendDataCompQueueFull; 195884059Swpaul 195984059Swpaul /* Statistics maintained by Host Coalescing. */ 196084059Swpaul bge_hostaddr nicRingSetSendProdIndex; 196184059Swpaul bge_hostaddr nicRingStatusUpdate; 196284059Swpaul bge_hostaddr nicInterrupts; 196384059Swpaul bge_hostaddr nicAvoidedInterrupts; 196484059Swpaul bge_hostaddr nicSendThresholdHit; 196584059Swpaul 196684059Swpaul u_int8_t Reserved4[320]; 196784059Swpaul}; 196884059Swpaul 196984059Swpaul/* 197084059Swpaul * Tigon general information block. This resides in host memory 197184059Swpaul * and contains the status counters, ring control blocks and 197284059Swpaul * producer pointers. 197384059Swpaul */ 197484059Swpaul 197584059Swpaulstruct bge_gib { 197684059Swpaul struct bge_stats bge_stats; 197784059Swpaul struct bge_rcb bge_tx_rcb[16]; 197884059Swpaul struct bge_rcb bge_std_rx_rcb; 197984059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 198084059Swpaul struct bge_rcb bge_mini_rx_rcb; 198184059Swpaul struct bge_rcb bge_return_rcb; 198284059Swpaul}; 198384059Swpaul 198484059Swpaul#define BGE_FRAMELEN 1518 198584059Swpaul#define BGE_MAX_FRAMELEN 1536 198684059Swpaul#define BGE_JUMBO_FRAMELEN 9018 198784059Swpaul#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 198884059Swpaul#define BGE_PAGE_SIZE PAGE_SIZE 198984059Swpaul#define BGE_MIN_FRAMELEN 60 199084059Swpaul 199184059Swpaul/* 199284059Swpaul * Other utility macros. 199384059Swpaul */ 199484059Swpaul#define BGE_INC(x, y) (x) = (x + 1) % y 199584059Swpaul 199684059Swpaul/* 199784059Swpaul * Vital product data and structures. 199884059Swpaul */ 199984059Swpaul#define BGE_VPD_FLAG 0x8000 200084059Swpaul 200184059Swpaul/* VPD structures */ 200284059Swpaulstruct vpd_res { 200384059Swpaul u_int8_t vr_id; 200484059Swpaul u_int8_t vr_len; 200584059Swpaul u_int8_t vr_pad; 200684059Swpaul}; 200784059Swpaul 200884059Swpaulstruct vpd_key { 200984059Swpaul char vk_key[2]; 201084059Swpaul u_int8_t vk_len; 201184059Swpaul}; 201284059Swpaul 201384059Swpaul#define VPD_RES_ID 0x82 /* ID string */ 201484059Swpaul#define VPD_RES_READ 0x90 /* start of read only area */ 201584059Swpaul#define VPD_RES_WRITE 0x81 /* start of read/write area */ 201684059Swpaul#define VPD_RES_END 0x78 /* end tag */ 201784059Swpaul 201884059Swpaul 201984059Swpaul/* 202084059Swpaul * Register access macros. The Tigon always uses memory mapped register 202184059Swpaul * accesses and all registers must be accessed with 32 bit operations. 202284059Swpaul */ 202384059Swpaul 202484059Swpaul#define CSR_WRITE_4(sc, reg, val) \ 202584059Swpaul bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 202684059Swpaul 202784059Swpaul#define CSR_READ_4(sc, reg) \ 202884059Swpaul bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 202984059Swpaul 203084059Swpaul#define BGE_SETBIT(sc, reg, x) \ 2031106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 203284059Swpaul#define BGE_CLRBIT(sc, reg, x) \ 2033106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 203484059Swpaul 203584059Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 2036106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 203784059Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 2038106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 203984059Swpaul 204084059Swpaul/* 204184059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 204284059Swpaul * values are tuneable. They control the actual amount of buffers 204384059Swpaul * allocated for the standard, mini and jumbo receive rings. 204484059Swpaul */ 204584059Swpaul 204684059Swpaul#define BGE_SSLOTS 256 204784059Swpaul#define BGE_MSLOTS 256 204884059Swpaul#define BGE_JSLOTS 384 204984059Swpaul 205084059Swpaul#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 205184059Swpaul#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 205284059Swpaul (BGE_JRAWLEN % sizeof(u_int64_t)))) 205384059Swpaul#define BGE_JPAGESZ PAGE_SIZE 205484059Swpaul#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 205584059Swpaul#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 205684059Swpaul 205784059Swpaul/* 205884059Swpaul * Ring structures. Most of these reside in host memory and we tell 205984059Swpaul * the NIC where they are via the ring control blocks. The exceptions 206084059Swpaul * are the tx and command rings, which live in NIC memory and which 206184059Swpaul * we access via the shared memory window. 206284059Swpaul */ 206384059Swpaulstruct bge_ring_data { 206484059Swpaul struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 206584059Swpaul struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 206684059Swpaul struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 206784059Swpaul struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 206884059Swpaul struct bge_status_block bge_status_block; 206984059Swpaul struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 207084059Swpaul struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 207184059Swpaul struct bge_gib bge_info; 207284059Swpaul}; 207384059Swpaul 207484059Swpaul/* 207584059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 207684059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 207784059Swpaul * not the other way around. 207884059Swpaul */ 207984059Swpaulstruct bge_chain_data { 208084059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 208184059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 208284059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 208384059Swpaul struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 208484059Swpaul /* Stick the jumbo mem management stuff here too. */ 208584059Swpaul caddr_t bge_jslots[BGE_JSLOTS]; 208684059Swpaul void *bge_jumbo_buf; 208784059Swpaul}; 208884059Swpaul 208984059Swpaulstruct bge_type { 209084059Swpaul u_int16_t bge_vid; 209184059Swpaul u_int16_t bge_did; 209284059Swpaul char *bge_name; 209384059Swpaul}; 209484059Swpaul 209584059Swpaul#define BGE_HWREV_TIGON 0x01 209684059Swpaul#define BGE_HWREV_TIGON_II 0x02 209784059Swpaul#define BGE_TIMEOUT 1000 209884059Swpaul#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 209984059Swpaul 210084059Swpaulstruct bge_jpool_entry { 210184059Swpaul int slot; 210284059Swpaul SLIST_ENTRY(bge_jpool_entry) jpool_entries; 210384059Swpaul}; 210484059Swpaul 210584059Swpaulstruct bge_bcom_hack { 210684059Swpaul int reg; 210784059Swpaul int val; 210884059Swpaul}; 210984059Swpaul 211084059Swpaulstruct bge_softc { 211184059Swpaul struct arpcom arpcom; /* interface info */ 211284059Swpaul device_t bge_dev; 211384059Swpaul device_t bge_miibus; 211484059Swpaul bus_space_handle_t bge_bhandle; 211584059Swpaul vm_offset_t bge_vhandle; 211684059Swpaul bus_space_tag_t bge_btag; 211784059Swpaul void *bge_intrhand; 211884059Swpaul struct resource *bge_irq; 211984059Swpaul struct resource *bge_res; 212084059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 212184059Swpaul u_int8_t bge_unit; /* interface number */ 212284059Swpaul u_int8_t bge_extram; /* has external SSRAM */ 212384059Swpaul u_int8_t bge_tbi; 212498779Sjdp u_int8_t bge_rx_alignment_bug; 212592934Swpaul u_int32_t bge_asicrev; 212684059Swpaul struct bge_ring_data *bge_rdata; /* rings */ 212784059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 212884059Swpaul u_int16_t bge_tx_saved_considx; 212984059Swpaul u_int16_t bge_rx_saved_considx; 213084059Swpaul u_int16_t bge_ev_saved_considx; 213184059Swpaul u_int16_t bge_std; /* current std ring head */ 213284059Swpaul u_int16_t bge_jumbo; /* current jumo ring head */ 213384059Swpaul SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 213484059Swpaul SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 213584059Swpaul u_int32_t bge_stat_ticks; 213684059Swpaul u_int32_t bge_rx_coal_ticks; 213784059Swpaul u_int32_t bge_tx_coal_ticks; 213884059Swpaul u_int32_t bge_rx_max_coal_bds; 213984059Swpaul u_int32_t bge_tx_max_coal_bds; 214084059Swpaul u_int32_t bge_tx_buf_ratio; 214184059Swpaul int bge_if_flags; 214284059Swpaul int bge_txcnt; 214384059Swpaul int bge_link; 214484059Swpaul struct callout_handle bge_stat_ch; 214584059Swpaul char *bge_vpd_prodname; 214684059Swpaul char *bge_vpd_readonly; 214784059Swpaul}; 214884059Swpaul 214984059Swpaul#ifdef __alpha__ 215084059Swpaul#undef vtophys 215184059Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 215284059Swpaul#endif 2153