if_bgereg.h revision 106696
184059Swpaul/* 284059Swpaul * Copyright (c) 2001 Wind River Systems 384059Swpaul * Copyright (c) 1997, 1998, 1999, 2001 484059Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 584059Swpaul * 684059Swpaul * Redistribution and use in source and binary forms, with or without 784059Swpaul * modification, are permitted provided that the following conditions 884059Swpaul * are met: 984059Swpaul * 1. Redistributions of source code must retain the above copyright 1084059Swpaul * notice, this list of conditions and the following disclaimer. 1184059Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1284059Swpaul * notice, this list of conditions and the following disclaimer in the 1384059Swpaul * documentation and/or other materials provided with the distribution. 1484059Swpaul * 3. All advertising materials mentioning features or use of this software 1584059Swpaul * must display the following acknowledgement: 1684059Swpaul * This product includes software developed by Bill Paul. 1784059Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1884059Swpaul * may be used to endorse or promote products derived from this software 1984059Swpaul * without specific prior written permission. 2084059Swpaul * 2184059Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2284059Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2384059Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2484059Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2584059Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2684059Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2784059Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2884059Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2984059Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3084059Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3184059Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3284059Swpaul * 3384059Swpaul * $FreeBSD: head/sys/dev/bge/if_bgereg.h 106696 2002-11-09 12:55:07Z alfred $ 3484059Swpaul */ 3584059Swpaul 3684059Swpaul/* 3784059Swpaul * BCM570x memory map. The internal memory layout varies somewhat 3884059Swpaul * depending on whether or not we have external SSRAM attached. 3984059Swpaul * The BCM5700 can have up to 16MB of external memory. The BCM5701 4084059Swpaul * is apparently not designed to use external SSRAM. The mappings 4184059Swpaul * up to the first 4 send rings are the same for both internal and 4284059Swpaul * external memory configurations. Note that mini RX ring space is 4384059Swpaul * only available with external SSRAM configurations, which means 4484059Swpaul * the mini RX ring is not supported on the BCM5701. 4584059Swpaul * 4684059Swpaul * The NIC's memory can be accessed by the host in one of 3 ways: 4784059Swpaul * 4884059Swpaul * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 4984059Swpaul * registers in PCI config space can be used to read any 32-bit 5084059Swpaul * address within the NIC's memory. 5184059Swpaul * 5284059Swpaul * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 5384059Swpaul * space can be used in conjunction with the memory window in the 5484059Swpaul * device register space at offset 0x8000 to read any 32K chunk 5584059Swpaul * of NIC memory. 5684059Swpaul * 5784059Swpaul * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 5884059Swpaul * set, the device I/O mapping consumes 32MB of host address space, 5984059Swpaul * allowing all of the registers and internal NIC memory to be 6084059Swpaul * accessed directly. NIC memory addresses are offset by 0x01000000. 6184059Swpaul * Flat mode consumes so much host address space that it is not 6284059Swpaul * recommended. 6384059Swpaul */ 6484059Swpaul#define BGE_PAGE_ZERO 0x00000000 6584059Swpaul#define BGE_PAGE_ZERO_END 0x000000FF 6684059Swpaul#define BGE_SEND_RING_RCB 0x00000100 6784059Swpaul#define BGE_SEND_RING_RCB_END 0x000001FF 6884059Swpaul#define BGE_RX_RETURN_RING_RCB 0x00000200 6984059Swpaul#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 7084059Swpaul#define BGE_STATS_BLOCK 0x00000300 7184059Swpaul#define BGE_STATS_BLOCK_END 0x00000AFF 7284059Swpaul#define BGE_STATUS_BLOCK 0x00000B00 7384059Swpaul#define BGE_STATUS_BLOCK_END 0x00000B4F 7484059Swpaul#define BGE_SOFTWARE_GENCOMM 0x00000B50 7584059Swpaul#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 7684059Swpaul#define BGE_UNMAPPED 0x00001000 7784059Swpaul#define BGE_UNMAPPED_END 0x00001FFF 7884059Swpaul#define BGE_DMA_DESCRIPTORS 0x00002000 7984059Swpaul#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 8084059Swpaul#define BGE_SEND_RING_1_TO_4 0x00004000 8184059Swpaul#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 8284059Swpaul 8384059Swpaul/* Mappings for internal memory configuration */ 8484059Swpaul#define BGE_STD_RX_RINGS 0x00006000 8584059Swpaul#define BGE_STD_RX_RINGS_END 0x00006FFF 8684059Swpaul#define BGE_JUMBO_RX_RINGS 0x00007000 8784059Swpaul#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 8884059Swpaul#define BGE_BUFFPOOL_1 0x00008000 8984059Swpaul#define BGE_BUFFPOOL_1_END 0x0000FFFF 9084059Swpaul#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 9184059Swpaul#define BGE_BUFFPOOL_2_END 0x00017FFF 9284059Swpaul#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 9384059Swpaul#define BGE_BUFFPOOL_3_END 0x0001FFFF 9484059Swpaul 9584059Swpaul/* Mappings for external SSRAM configurations */ 9684059Swpaul#define BGE_SEND_RING_5_TO_6 0x00006000 9784059Swpaul#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 9884059Swpaul#define BGE_SEND_RING_7_TO_8 0x00007000 9984059Swpaul#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 10084059Swpaul#define BGE_SEND_RING_9_TO_16 0x00008000 10184059Swpaul#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 10284059Swpaul#define BGE_EXT_STD_RX_RINGS 0x0000C000 10384059Swpaul#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 10484059Swpaul#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 10584059Swpaul#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 10684059Swpaul#define BGE_MINI_RX_RINGS 0x0000E000 10784059Swpaul#define BGE_MINI_RX_RINGS_END 0x0000FFFF 10884059Swpaul#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 10984059Swpaul#define BGE_AVAIL_REGION1_END 0x00017FFF 11084059Swpaul#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 11184059Swpaul#define BGE_AVAIL_REGION2_END 0x0001FFFF 11284059Swpaul#define BGE_EXT_SSRAM 0x00020000 11384059Swpaul#define BGE_EXT_SSRAM_END 0x000FFFFF 11484059Swpaul 11584059Swpaul 11684059Swpaul/* 11784059Swpaul * BCM570x register offsets. These are memory mapped registers 11884059Swpaul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 11984059Swpaul * Each register must be accessed using 32 bit operations. 12084059Swpaul * 12184059Swpaul * All registers are accessed through a 32K shared memory block. 12284059Swpaul * The first group of registers are actually copies of the PCI 12384059Swpaul * configuration space registers. 12484059Swpaul */ 12584059Swpaul 12684059Swpaul/* 12784059Swpaul * PCI registers defined in the PCI 2.2 spec. 12884059Swpaul */ 12984059Swpaul#define BGE_PCI_VID 0x00 13084059Swpaul#define BGE_PCI_DID 0x02 13184059Swpaul#define BGE_PCI_CMD 0x04 13284059Swpaul#define BGE_PCI_STS 0x06 13384059Swpaul#define BGE_PCI_REV 0x08 13484059Swpaul#define BGE_PCI_CLASS 0x09 13584059Swpaul#define BGE_PCI_CACHESZ 0x0C 13684059Swpaul#define BGE_PCI_LATTIMER 0x0D 13784059Swpaul#define BGE_PCI_HDRTYPE 0x0E 13884059Swpaul#define BGE_PCI_BIST 0x0F 13984059Swpaul#define BGE_PCI_BAR0 0x10 14084059Swpaul#define BGE_PCI_BAR1 0x14 14184059Swpaul#define BGE_PCI_SUBSYS 0x2C 14284059Swpaul#define BGE_PCI_SUBVID 0x2E 14384059Swpaul#define BGE_PCI_ROMBASE 0x30 14484059Swpaul#define BGE_PCI_CAPPTR 0x34 14584059Swpaul#define BGE_PCI_INTLINE 0x3C 14684059Swpaul#define BGE_PCI_INTPIN 0x3D 14784059Swpaul#define BGE_PCI_MINGNT 0x3E 14884059Swpaul#define BGE_PCI_MAXLAT 0x3F 14984059Swpaul#define BGE_PCI_PCIXCAP 0x40 15084059Swpaul#define BGE_PCI_NEXTPTR_PM 0x41 15184059Swpaul#define BGE_PCI_PCIX_CMD 0x42 15284059Swpaul#define BGE_PCI_PCIX_STS 0x44 15384059Swpaul#define BGE_PCI_PWRMGMT_CAPID 0x48 15484059Swpaul#define BGE_PCI_NEXTPTR_VPD 0x49 15584059Swpaul#define BGE_PCI_PWRMGMT_CAPS 0x4A 15684059Swpaul#define BGE_PCI_PWRMGMT_CMD 0x4C 15784059Swpaul#define BGE_PCI_PWRMGMT_STS 0x4D 15884059Swpaul#define BGE_PCI_PWRMGMT_DATA 0x4F 15984059Swpaul#define BGE_PCI_VPD_CAPID 0x50 16084059Swpaul#define BGE_PCI_NEXTPTR_MSI 0x51 16184059Swpaul#define BGE_PCI_VPD_ADDR 0x52 16284059Swpaul#define BGE_PCI_VPD_DATA 0x54 16384059Swpaul#define BGE_PCI_MSI_CAPID 0x58 16484059Swpaul#define BGE_PCI_NEXTPTR_NONE 0x59 16584059Swpaul#define BGE_PCI_MSI_CTL 0x5A 16684059Swpaul#define BGE_PCI_MSI_ADDR_HI 0x5C 16784059Swpaul#define BGE_PCI_MSI_ADDR_LO 0x60 16884059Swpaul#define BGE_PCI_MSI_DATA 0x64 16984059Swpaul 17084059Swpaul/* 17184059Swpaul * PCI registers specific to the BCM570x family. 17284059Swpaul */ 17384059Swpaul#define BGE_PCI_MISC_CTL 0x68 17484059Swpaul#define BGE_PCI_DMA_RW_CTL 0x6C 17584059Swpaul#define BGE_PCI_PCISTATE 0x70 17684059Swpaul#define BGE_PCI_CLKCTL 0x74 17784059Swpaul#define BGE_PCI_REG_BASEADDR 0x78 17884059Swpaul#define BGE_PCI_MEMWIN_BASEADDR 0x7C 17984059Swpaul#define BGE_PCI_REG_DATA 0x80 18084059Swpaul#define BGE_PCI_MEMWIN_DATA 0x84 18184059Swpaul#define BGE_PCI_MODECTL 0x88 18284059Swpaul#define BGE_PCI_MISC_CFG 0x8C 18384059Swpaul#define BGE_PCI_MISC_LOCALCTL 0x90 18484059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 18584059Swpaul#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 18684059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 18784059Swpaul#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 18884059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 18984059Swpaul#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 19084059Swpaul#define BGE_PCI_ISR_MBX_HI 0xB0 19184059Swpaul#define BGE_PCI_ISR_MBX_LO 0xB4 19284059Swpaul 19384059Swpaul/* PCI Misc. Host control register */ 19484059Swpaul#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 19584059Swpaul#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 19684059Swpaul#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 19784059Swpaul#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 19884059Swpaul#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 19984059Swpaul#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 20084059Swpaul#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 20184059Swpaul#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 20284059Swpaul#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 20384059Swpaul 20484059Swpaul#define BGE_BIGENDIAN_INIT \ 205104325Sjake (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 20684059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 207104325Sjake BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 20884059Swpaul 20984059Swpaul#define BGE_LITTLEENDIAN_INIT \ 21084059Swpaul (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 21184059Swpaul BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 21284059Swpaul 21384059Swpaul#define BGE_ASICREV_TIGON_I 0x40000000 21484059Swpaul#define BGE_ASICREV_TIGON_II 0x60000000 21584059Swpaul#define BGE_ASICREV_BCM5700_B0 0x71000000 21684059Swpaul#define BGE_ASICREV_BCM5700_B1 0x71020000 21784059Swpaul#define BGE_ASICREV_BCM5700_B2 0x71030000 21884059Swpaul#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 21984059Swpaul#define BGE_ASICREV_BCM5700_C0 0x72000000 22092934Swpaul#define BGE_ASICREV_BCM5701_A0 0x00000000 /* grrrr */ 22192934Swpaul#define BGE_ASICREV_BCM5701_B0 0x01000000 22292934Swpaul#define BGE_ASICREV_BCM5701_B2 0x01020000 22392934Swpaul#define BGE_ASICREV_BCM5701_B5 0x01050000 224103103Sjdp#define BGE_ASICREV_BCM5703_A0 0x10000000 225103103Sjdp#define BGE_ASICREV_BCM5703_A1 0x10010000 226103103Sjdp#define BGE_ASICREV_BCM5703_A2 0x10020000 22784059Swpaul 22893751Swpaul/* shorthand one */ 22993751Swpaul#define BGE_ASICREV_BCM5700 0x71000000 23093751Swpaul 23184059Swpaul/* PCI DMA Read/Write Control register */ 23284059Swpaul#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 23384059Swpaul#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 23484059Swpaul#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 23584059Swpaul#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 23684059Swpaul#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 23784059Swpaul#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 23884059Swpaul#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 23984059Swpaul#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 24084059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 24184059Swpaul#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 24284059Swpaul 24384059Swpaul#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 24484059Swpaul#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 24584059Swpaul#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 24684059Swpaul#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 24784059Swpaul#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 24884059Swpaul#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 24984059Swpaul#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 25084059Swpaul#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 25184059Swpaul 25284059Swpaul#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 25384059Swpaul#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 25484059Swpaul#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 25584059Swpaul#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 25684059Swpaul#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 25784059Swpaul#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 25884059Swpaul#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 25984059Swpaul#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 26084059Swpaul 26184059Swpaul/* 26284059Swpaul * PCI state register -- note, this register is read only 26384059Swpaul * unless the PCISTATE_WR bit of the PCI Misc. Host Control 26484059Swpaul * register is set. 26584059Swpaul */ 26684059Swpaul#define BGE_PCISTATE_FORCE_RESET 0x00000001 26784059Swpaul#define BGE_PCISTATE_INTR_STATE 0x00000002 26884059Swpaul#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 26984059Swpaul#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 27084059Swpaul#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 27184059Swpaul#define BGE_PCISTATE_WANT_EXPROM 0x00000020 27284059Swpaul#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 27384059Swpaul#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 27484059Swpaul#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 27584059Swpaul 27684059Swpaul/* 27784059Swpaul * PCI Clock Control register -- note, this register is read only 27884059Swpaul * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 27984059Swpaul * register is set. 28084059Swpaul */ 28184059Swpaul#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 28284059Swpaul#define BGE_PCICLOCKCTL_M66EN 0x00000080 28384059Swpaul#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 28484059Swpaul#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 28584059Swpaul#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 28684059Swpaul#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 28784059Swpaul#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 28884059Swpaul#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 28984059Swpaul#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 29084059Swpaul#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 29184059Swpaul 29284059Swpaul 29384059Swpaul#ifndef PCIM_CMD_MWIEN 29484059Swpaul#define PCIM_CMD_MWIEN 0x0010 29584059Swpaul#endif 29684059Swpaul 29784059Swpaul/* 29884059Swpaul * High priority mailbox registers 29984059Swpaul * Each mailbox is 64-bits wide, though we only use the 30084059Swpaul * lower 32 bits. To write a 64-bit value, write the upper 32 bits 30184059Swpaul * first. The NIC will load the mailbox after the lower 32 bit word 30284059Swpaul * has been updated. 30384059Swpaul */ 30484059Swpaul#define BGE_MBX_IRQ0_HI 0x0200 30584059Swpaul#define BGE_MBX_IRQ0_LO 0x0204 30684059Swpaul#define BGE_MBX_IRQ1_HI 0x0208 30784059Swpaul#define BGE_MBX_IRQ1_LO 0x020C 30884059Swpaul#define BGE_MBX_IRQ2_HI 0x0210 30984059Swpaul#define BGE_MBX_IRQ2_LO 0x0214 31084059Swpaul#define BGE_MBX_IRQ3_HI 0x0218 31184059Swpaul#define BGE_MBX_IRQ3_LO 0x021C 31284059Swpaul#define BGE_MBX_GEN0_HI 0x0220 31384059Swpaul#define BGE_MBX_GEN0_LO 0x0224 31484059Swpaul#define BGE_MBX_GEN1_HI 0x0228 31584059Swpaul#define BGE_MBX_GEN1_LO 0x022C 31684059Swpaul#define BGE_MBX_GEN2_HI 0x0230 31784059Swpaul#define BGE_MBX_GEN2_LO 0x0234 31884059Swpaul#define BGE_MBX_GEN3_HI 0x0228 31984059Swpaul#define BGE_MBX_GEN3_LO 0x022C 32084059Swpaul#define BGE_MBX_GEN4_HI 0x0240 32184059Swpaul#define BGE_MBX_GEN4_LO 0x0244 32284059Swpaul#define BGE_MBX_GEN5_HI 0x0248 32384059Swpaul#define BGE_MBX_GEN5_LO 0x024C 32484059Swpaul#define BGE_MBX_GEN6_HI 0x0250 32584059Swpaul#define BGE_MBX_GEN6_LO 0x0254 32684059Swpaul#define BGE_MBX_GEN7_HI 0x0258 32784059Swpaul#define BGE_MBX_GEN7_LO 0x025C 32884059Swpaul#define BGE_MBX_RELOAD_STATS_HI 0x0260 32984059Swpaul#define BGE_MBX_RELOAD_STATS_LO 0x0264 33084059Swpaul#define BGE_MBX_RX_STD_PROD_HI 0x0268 33184059Swpaul#define BGE_MBX_RX_STD_PROD_LO 0x026C 33284059Swpaul#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 33384059Swpaul#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 33484059Swpaul#define BGE_MBX_RX_MINI_PROD_HI 0x0278 33584059Swpaul#define BGE_MBX_RX_MINI_PROD_LO 0x027C 33684059Swpaul#define BGE_MBX_RX_CONS0_HI 0x0280 33784059Swpaul#define BGE_MBX_RX_CONS0_LO 0x0284 33884059Swpaul#define BGE_MBX_RX_CONS1_HI 0x0288 33984059Swpaul#define BGE_MBX_RX_CONS1_LO 0x028C 34084059Swpaul#define BGE_MBX_RX_CONS2_HI 0x0290 34184059Swpaul#define BGE_MBX_RX_CONS2_LO 0x0294 34284059Swpaul#define BGE_MBX_RX_CONS3_HI 0x0298 34384059Swpaul#define BGE_MBX_RX_CONS3_LO 0x029C 34484059Swpaul#define BGE_MBX_RX_CONS4_HI 0x02A0 34584059Swpaul#define BGE_MBX_RX_CONS4_LO 0x02A4 34684059Swpaul#define BGE_MBX_RX_CONS5_HI 0x02A8 34784059Swpaul#define BGE_MBX_RX_CONS5_LO 0x02AC 34884059Swpaul#define BGE_MBX_RX_CONS6_HI 0x02B0 34984059Swpaul#define BGE_MBX_RX_CONS6_LO 0x02B4 35084059Swpaul#define BGE_MBX_RX_CONS7_HI 0x02B8 35184059Swpaul#define BGE_MBX_RX_CONS7_LO 0x02BC 35284059Swpaul#define BGE_MBX_RX_CONS8_HI 0x02C0 35384059Swpaul#define BGE_MBX_RX_CONS8_LO 0x02C4 35484059Swpaul#define BGE_MBX_RX_CONS9_HI 0x02C8 35584059Swpaul#define BGE_MBX_RX_CONS9_LO 0x02CC 35684059Swpaul#define BGE_MBX_RX_CONS10_HI 0x02D0 35784059Swpaul#define BGE_MBX_RX_CONS10_LO 0x02D4 35884059Swpaul#define BGE_MBX_RX_CONS11_HI 0x02D8 35984059Swpaul#define BGE_MBX_RX_CONS11_LO 0x02DC 36084059Swpaul#define BGE_MBX_RX_CONS12_HI 0x02E0 36184059Swpaul#define BGE_MBX_RX_CONS12_LO 0x02E4 36284059Swpaul#define BGE_MBX_RX_CONS13_HI 0x02E8 36384059Swpaul#define BGE_MBX_RX_CONS13_LO 0x02EC 36484059Swpaul#define BGE_MBX_RX_CONS14_HI 0x02F0 36584059Swpaul#define BGE_MBX_RX_CONS14_LO 0x02F4 36684059Swpaul#define BGE_MBX_RX_CONS15_HI 0x02F8 36784059Swpaul#define BGE_MBX_RX_CONS15_LO 0x02FC 36884059Swpaul#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 36984059Swpaul#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 37084059Swpaul#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 37184059Swpaul#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 37284059Swpaul#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 37384059Swpaul#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 37484059Swpaul#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 37584059Swpaul#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 37684059Swpaul#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 37784059Swpaul#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 37884059Swpaul#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 37984059Swpaul#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 38084059Swpaul#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 38184059Swpaul#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 38284059Swpaul#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 38384059Swpaul#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 38484059Swpaul#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 38584059Swpaul#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 38684059Swpaul#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 38784059Swpaul#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 38884059Swpaul#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 38984059Swpaul#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 39084059Swpaul#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 39184059Swpaul#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 39284059Swpaul#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 39384059Swpaul#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 39484059Swpaul#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 39584059Swpaul#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 39684059Swpaul#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 39784059Swpaul#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 39884059Swpaul#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 39984059Swpaul#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 40084059Swpaul#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 40184059Swpaul#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 40284059Swpaul#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 40384059Swpaul#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 40484059Swpaul#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 40584059Swpaul#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 40684059Swpaul#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 40784059Swpaul#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 40884059Swpaul#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 40984059Swpaul#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 41084059Swpaul#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 41184059Swpaul#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 41284059Swpaul#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 41384059Swpaul#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 41484059Swpaul#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 41584059Swpaul#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 41684059Swpaul#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 41784059Swpaul#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 41884059Swpaul#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 41984059Swpaul#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 42084059Swpaul#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 42184059Swpaul#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 42284059Swpaul#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 42384059Swpaul#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 42484059Swpaul#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 42584059Swpaul#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 42684059Swpaul#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 42784059Swpaul#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 42884059Swpaul#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 42984059Swpaul#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 43084059Swpaul#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 43184059Swpaul#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 43284059Swpaul 43384059Swpaul#define BGE_TX_RINGS_MAX 4 43484059Swpaul#define BGE_TX_RINGS_EXTSSRAM_MAX 16 43584059Swpaul#define BGE_RX_RINGS_MAX 16 43684059Swpaul 43784059Swpaul/* Ethernet MAC control registers */ 43884059Swpaul#define BGE_MAC_MODE 0x0400 43984059Swpaul#define BGE_MAC_STS 0x0404 44084059Swpaul#define BGE_MAC_EVT_ENB 0x0408 44184059Swpaul#define BGE_MAC_LED_CTL 0x040C 44284059Swpaul#define BGE_MAC_ADDR1_LO 0x0410 44384059Swpaul#define BGE_MAC_ADDR1_HI 0x0414 44484059Swpaul#define BGE_MAC_ADDR2_LO 0x0418 44584059Swpaul#define BGE_MAC_ADDR2_HI 0x041C 44684059Swpaul#define BGE_MAC_ADDR3_LO 0x0420 44784059Swpaul#define BGE_MAC_ADDR3_HI 0x0424 44884059Swpaul#define BGE_MAC_ADDR4_LO 0x0428 44984059Swpaul#define BGE_MAC_ADDR4_HI 0x042C 45084059Swpaul#define BGE_WOL_PATPTR 0x0430 45184059Swpaul#define BGE_WOL_PATCFG 0x0434 45284059Swpaul#define BGE_TX_RANDOM_BACKOFF 0x0438 45384059Swpaul#define BGE_RX_MTU 0x043C 45484059Swpaul#define BGE_GBIT_PCS_TEST 0x0440 45584059Swpaul#define BGE_TX_TBI_AUTONEG 0x0444 45684059Swpaul#define BGE_RX_TBI_AUTONEG 0x0448 45784059Swpaul#define BGE_MI_COMM 0x044C 45884059Swpaul#define BGE_MI_STS 0x0450 45984059Swpaul#define BGE_MI_MODE 0x0454 46084059Swpaul#define BGE_AUTOPOLL_STS 0x0458 46184059Swpaul#define BGE_TX_MODE 0x045C 46284059Swpaul#define BGE_TX_STS 0x0460 46384059Swpaul#define BGE_TX_LENGTHS 0x0464 46484059Swpaul#define BGE_RX_MODE 0x0468 46584059Swpaul#define BGE_RX_STS 0x046C 46684059Swpaul#define BGE_MAR0 0x0470 46784059Swpaul#define BGE_MAR1 0x0474 46884059Swpaul#define BGE_MAR2 0x0478 46984059Swpaul#define BGE_MAR3 0x047C 47084059Swpaul#define BGE_RX_BD_RULES_CTL0 0x0480 47184059Swpaul#define BGE_RX_BD_RULES_MASKVAL0 0x0484 47284059Swpaul#define BGE_RX_BD_RULES_CTL1 0x0488 47384059Swpaul#define BGE_RX_BD_RULES_MASKVAL1 0x048C 47484059Swpaul#define BGE_RX_BD_RULES_CTL2 0x0490 47584059Swpaul#define BGE_RX_BD_RULES_MASKVAL2 0x0494 47684059Swpaul#define BGE_RX_BD_RULES_CTL3 0x0498 47784059Swpaul#define BGE_RX_BD_RULES_MASKVAL3 0x049C 47884059Swpaul#define BGE_RX_BD_RULES_CTL4 0x04A0 47984059Swpaul#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 48084059Swpaul#define BGE_RX_BD_RULES_CTL5 0x04A8 48184059Swpaul#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 48284059Swpaul#define BGE_RX_BD_RULES_CTL6 0x04B0 48384059Swpaul#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 48484059Swpaul#define BGE_RX_BD_RULES_CTL7 0x04B8 48584059Swpaul#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 48684059Swpaul#define BGE_RX_BD_RULES_CTL8 0x04C0 48784059Swpaul#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 48884059Swpaul#define BGE_RX_BD_RULES_CTL9 0x04C8 48984059Swpaul#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 49084059Swpaul#define BGE_RX_BD_RULES_CTL10 0x04D0 49184059Swpaul#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 49284059Swpaul#define BGE_RX_BD_RULES_CTL11 0x04D8 49384059Swpaul#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 49484059Swpaul#define BGE_RX_BD_RULES_CTL12 0x04E0 49584059Swpaul#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 49684059Swpaul#define BGE_RX_BD_RULES_CTL13 0x04E8 49784059Swpaul#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 49884059Swpaul#define BGE_RX_BD_RULES_CTL14 0x04F0 49984059Swpaul#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 50084059Swpaul#define BGE_RX_BD_RULES_CTL15 0x04F8 50184059Swpaul#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 50284059Swpaul#define BGE_RX_RULES_CFG 0x0500 50384059Swpaul#define BGE_RX_STATS 0x0800 50484059Swpaul#define BGE_TX_STATS 0x0880 50584059Swpaul 50684059Swpaul/* Ethernet MAC Mode register */ 50784059Swpaul#define BGE_MACMODE_RESET 0x00000001 50884059Swpaul#define BGE_MACMODE_HALF_DUPLEX 0x00000002 50984059Swpaul#define BGE_MACMODE_PORTMODE 0x0000000C 51084059Swpaul#define BGE_MACMODE_LOOPBACK 0x00000010 51184059Swpaul#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 51284059Swpaul#define BGE_MACMODE_TX_BURST_ENB 0x00000100 51384059Swpaul#define BGE_MACMODE_MAX_DEFER 0x00000200 51484059Swpaul#define BGE_MACMODE_LINK_POLARITY 0x00000400 51584059Swpaul#define BGE_MACMODE_RX_STATS_ENB 0x00000800 51684059Swpaul#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 51784059Swpaul#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 51884059Swpaul#define BGE_MACMODE_TX_STATS_ENB 0x00004000 51984059Swpaul#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 52084059Swpaul#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 52184059Swpaul#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 52284059Swpaul#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 52384059Swpaul#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 52484059Swpaul#define BGE_MACMODE_MIP_ENB 0x00100000 52584059Swpaul#define BGE_MACMODE_TXDMA_ENB 0x00200000 52684059Swpaul#define BGE_MACMODE_RXDMA_ENB 0x00400000 52784059Swpaul#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 52884059Swpaul 52984059Swpaul#define BGE_PORTMODE_NONE 0x00000000 53084059Swpaul#define BGE_PORTMODE_MII 0x00000004 53184059Swpaul#define BGE_PORTMODE_GMII 0x00000008 53284059Swpaul#define BGE_PORTMODE_TBI 0x0000000C 53384059Swpaul 53484059Swpaul/* MAC Status register */ 53584059Swpaul#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 53684059Swpaul#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 53784059Swpaul#define BGE_MACSTAT_RX_CFG 0x00000004 53884059Swpaul#define BGE_MACSTAT_CFG_CHANGED 0x00000008 53984059Swpaul#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 54084059Swpaul#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 54184059Swpaul#define BGE_MACSTAT_LINK_CHANGED 0x00001000 54284059Swpaul#define BGE_MACSTAT_MI_COMPLETE 0x00400000 54384059Swpaul#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 54484059Swpaul#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 54584059Swpaul#define BGE_MACSTAT_ODI_ERROR 0x02000000 54684059Swpaul#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 54784059Swpaul#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 54884059Swpaul 54984059Swpaul/* MAC Event Enable Register */ 55084059Swpaul#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 55184059Swpaul#define BGE_EVTENB_LINK_CHANGED 0x00001000 55284059Swpaul#define BGE_EVTENB_MI_COMPLETE 0x00400000 55384059Swpaul#define BGE_EVTENB_MI_INTERRUPT 0x00800000 55484059Swpaul#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 55584059Swpaul#define BGE_EVTENB_ODI_ERROR 0x02000000 55684059Swpaul#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 55784059Swpaul#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 55884059Swpaul 55984059Swpaul/* LED Control Register */ 56084059Swpaul#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 56184059Swpaul#define BGE_LEDCTL_1000MBPS_LED 0x00000002 56284059Swpaul#define BGE_LEDCTL_100MBPS_LED 0x00000004 56384059Swpaul#define BGE_LEDCTL_10MBPS_LED 0x00000008 56484059Swpaul#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 56584059Swpaul#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 56684059Swpaul#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 56784059Swpaul#define BGE_LEDCTL_1000MBPS_STS 0x00000080 56884059Swpaul#define BGE_LEDCTL_100MBPS_STS 0x00000100 56984059Swpaul#define BGE_LEDCTL_10MBPS_STS 0x00000200 57084059Swpaul#define BGE_LEDCTL_TRADLED_STS 0x00000400 57184059Swpaul#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 57284059Swpaul#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 57384059Swpaul 57484059Swpaul/* TX backoff seed register */ 57584059Swpaul#define BGE_TX_BACKOFF_SEED_MASK 0x3F 57684059Swpaul 57784059Swpaul/* Autopoll status register */ 57884059Swpaul#define BGE_AUTOPOLLSTS_ERROR 0x00000001 57984059Swpaul 58084059Swpaul/* Transmit MAC mode register */ 58184059Swpaul#define BGE_TXMODE_RESET 0x00000001 58284059Swpaul#define BGE_TXMODE_ENABLE 0x00000002 58384059Swpaul#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 58484059Swpaul#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 58584059Swpaul#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 58684059Swpaul 58784059Swpaul/* Transmit MAC status register */ 58884059Swpaul#define BGE_TXSTAT_RX_XOFFED 0x00000001 58984059Swpaul#define BGE_TXSTAT_SENT_XOFF 0x00000002 59084059Swpaul#define BGE_TXSTAT_SENT_XON 0x00000004 59184059Swpaul#define BGE_TXSTAT_LINK_UP 0x00000008 59284059Swpaul#define BGE_TXSTAT_ODI_UFLOW 0x00000010 59384059Swpaul#define BGE_TXSTAT_ODI_OFLOW 0x00000020 59484059Swpaul 59584059Swpaul/* Transmit MAC lengths register */ 59684059Swpaul#define BGE_TXLEN_SLOTTIME 0x000000FF 59784059Swpaul#define BGE_TXLEN_IPG 0x00000F00 59884059Swpaul#define BGE_TXLEN_CRS 0x00003000 59984059Swpaul 60084059Swpaul/* Receive MAC mode register */ 60184059Swpaul#define BGE_RXMODE_RESET 0x00000001 60284059Swpaul#define BGE_RXMODE_ENABLE 0x00000002 60384059Swpaul#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 60484059Swpaul#define BGE_RXMODE_RX_GIANTS 0x00000020 60584059Swpaul#define BGE_RXMODE_RX_RUNTS 0x00000040 60684059Swpaul#define BGE_RXMODE_8022_LENCHECK 0x00000080 60784059Swpaul#define BGE_RXMODE_RX_PROMISC 0x00000100 60884059Swpaul#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 60984059Swpaul#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 61084059Swpaul 61184059Swpaul/* Receive MAC status register */ 61284059Swpaul#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 61384059Swpaul#define BGE_RXSTAT_RCVD_XOFF 0x00000002 61484059Swpaul#define BGE_RXSTAT_RCVD_XON 0x00000004 61584059Swpaul 61684059Swpaul/* Receive Rules Control register */ 61784059Swpaul#define BGE_RXRULECTL_OFFSET 0x000000FF 61884059Swpaul#define BGE_RXRULECTL_CLASS 0x00001F00 61984059Swpaul#define BGE_RXRULECTL_HDRTYPE 0x0000E000 62084059Swpaul#define BGE_RXRULECTL_COMPARE_OP 0x00030000 62184059Swpaul#define BGE_RXRULECTL_MAP 0x01000000 62284059Swpaul#define BGE_RXRULECTL_DISCARD 0x02000000 62384059Swpaul#define BGE_RXRULECTL_MASK 0x04000000 62484059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 62584059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 62684059Swpaul#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 62784059Swpaul#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 62884059Swpaul 62984059Swpaul/* Receive Rules Mask register */ 63084059Swpaul#define BGE_RXRULEMASK_VALUE 0x0000FFFF 63184059Swpaul#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 63284059Swpaul 63384059Swpaul/* MI communication register */ 63484059Swpaul#define BGE_MICOMM_DATA 0x0000FFFF 63584059Swpaul#define BGE_MICOMM_REG 0x001F0000 63684059Swpaul#define BGE_MICOMM_PHY 0x03E00000 63784059Swpaul#define BGE_MICOMM_CMD 0x0C000000 63884059Swpaul#define BGE_MICOMM_READFAIL 0x10000000 63984059Swpaul#define BGE_MICOMM_BUSY 0x20000000 64084059Swpaul 64184059Swpaul#define BGE_MIREG(x) ((x & 0x1F) << 16) 64284059Swpaul#define BGE_MIPHY(x) ((x & 0x1F) << 21) 64384059Swpaul#define BGE_MICMD_WRITE 0x04000000 64484059Swpaul#define BGE_MICMD_READ 0x08000000 64584059Swpaul 64684059Swpaul/* MI status register */ 64784059Swpaul#define BGE_MISTS_LINK 0x00000001 64884059Swpaul#define BGE_MISTS_10MBPS 0x00000002 64984059Swpaul 65084059Swpaul#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 65184059Swpaul#define BGE_MIMODE_AUTOPOLL 0x00000010 65284059Swpaul#define BGE_MIMODE_CLKCNT 0x001F0000 65384059Swpaul 65484059Swpaul 65584059Swpaul/* 65684059Swpaul * Send data initiator control registers. 65784059Swpaul */ 65884059Swpaul#define BGE_SDI_MODE 0x0C00 65984059Swpaul#define BGE_SDI_STATUS 0x0C04 66084059Swpaul#define BGE_SDI_STATS_CTL 0x0C08 66184059Swpaul#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 66284059Swpaul#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 66384059Swpaul#define BGE_LOCSTATS_COS0 0x0C80 66484059Swpaul#define BGE_LOCSTATS_COS1 0x0C84 66584059Swpaul#define BGE_LOCSTATS_COS2 0x0C88 66684059Swpaul#define BGE_LOCSTATS_COS3 0x0C8C 66784059Swpaul#define BGE_LOCSTATS_COS4 0x0C90 66884059Swpaul#define BGE_LOCSTATS_COS5 0x0C84 66984059Swpaul#define BGE_LOCSTATS_COS6 0x0C98 67084059Swpaul#define BGE_LOCSTATS_COS7 0x0C9C 67184059Swpaul#define BGE_LOCSTATS_COS8 0x0CA0 67284059Swpaul#define BGE_LOCSTATS_COS9 0x0CA4 67384059Swpaul#define BGE_LOCSTATS_COS10 0x0CA8 67484059Swpaul#define BGE_LOCSTATS_COS11 0x0CAC 67584059Swpaul#define BGE_LOCSTATS_COS12 0x0CB0 67684059Swpaul#define BGE_LOCSTATS_COS13 0x0CB4 67784059Swpaul#define BGE_LOCSTATS_COS14 0x0CB8 67884059Swpaul#define BGE_LOCSTATS_COS15 0x0CBC 67984059Swpaul#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 68084059Swpaul#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 68184059Swpaul#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 68284059Swpaul#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 68384059Swpaul#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 68484059Swpaul#define BGE_LOCSTATS_IRQS 0x0CD4 68584059Swpaul#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 68684059Swpaul#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 68784059Swpaul 68884059Swpaul/* Send Data Initiator mode register */ 68984059Swpaul#define BGE_SDIMODE_RESET 0x00000001 69084059Swpaul#define BGE_SDIMODE_ENABLE 0x00000002 69184059Swpaul#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 69284059Swpaul 69384059Swpaul/* Send Data Initiator stats register */ 69484059Swpaul#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 69584059Swpaul 69684059Swpaul/* Send Data Initiator stats control register */ 69784059Swpaul#define BGE_SDISTATSCTL_ENABLE 0x00000001 69884059Swpaul#define BGE_SDISTATSCTL_FASTER 0x00000002 69984059Swpaul#define BGE_SDISTATSCTL_CLEAR 0x00000004 70084059Swpaul#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 70184059Swpaul#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 70284059Swpaul 70384059Swpaul/* 70484059Swpaul * Send Data Completion Control registers 70584059Swpaul */ 70684059Swpaul#define BGE_SDC_MODE 0x1000 70784059Swpaul#define BGE_SDC_STATUS 0x1004 70884059Swpaul 70984059Swpaul/* Send Data completion mode register */ 71084059Swpaul#define BGE_SDCMODE_RESET 0x00000001 71184059Swpaul#define BGE_SDCMODE_ENABLE 0x00000002 71284059Swpaul#define BGE_SDCMODE_ATTN 0x00000004 71384059Swpaul 71484059Swpaul/* Send Data completion status register */ 71584059Swpaul#define BGE_SDCSTAT_ATTN 0x00000004 71684059Swpaul 71784059Swpaul/* 71884059Swpaul * Send BD Ring Selector Control registers 71984059Swpaul */ 72084059Swpaul#define BGE_SRS_MODE 0x1400 72184059Swpaul#define BGE_SRS_STATUS 0x1404 72284059Swpaul#define BGE_SRS_HWDIAG 0x1408 72384059Swpaul#define BGE_SRS_LOC_NIC_CONS0 0x1440 72484059Swpaul#define BGE_SRS_LOC_NIC_CONS1 0x1444 72584059Swpaul#define BGE_SRS_LOC_NIC_CONS2 0x1448 72684059Swpaul#define BGE_SRS_LOC_NIC_CONS3 0x144C 72784059Swpaul#define BGE_SRS_LOC_NIC_CONS4 0x1450 72884059Swpaul#define BGE_SRS_LOC_NIC_CONS5 0x1454 72984059Swpaul#define BGE_SRS_LOC_NIC_CONS6 0x1458 73084059Swpaul#define BGE_SRS_LOC_NIC_CONS7 0x145C 73184059Swpaul#define BGE_SRS_LOC_NIC_CONS8 0x1460 73284059Swpaul#define BGE_SRS_LOC_NIC_CONS9 0x1464 73384059Swpaul#define BGE_SRS_LOC_NIC_CONS10 0x1468 73484059Swpaul#define BGE_SRS_LOC_NIC_CONS11 0x146C 73584059Swpaul#define BGE_SRS_LOC_NIC_CONS12 0x1470 73684059Swpaul#define BGE_SRS_LOC_NIC_CONS13 0x1474 73784059Swpaul#define BGE_SRS_LOC_NIC_CONS14 0x1478 73884059Swpaul#define BGE_SRS_LOC_NIC_CONS15 0x147C 73984059Swpaul 74084059Swpaul/* Send BD Ring Selector Mode register */ 74184059Swpaul#define BGE_SRSMODE_RESET 0x00000001 74284059Swpaul#define BGE_SRSMODE_ENABLE 0x00000002 74384059Swpaul#define BGE_SRSMODE_ATTN 0x00000004 74484059Swpaul 74584059Swpaul/* Send BD Ring Selector Status register */ 74684059Swpaul#define BGE_SRSSTAT_ERROR 0x00000004 74784059Swpaul 74884059Swpaul/* Send BD Ring Selector HW Diagnostics register */ 74984059Swpaul#define BGE_SRSHWDIAG_STATE 0x0000000F 75084059Swpaul#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 75184059Swpaul#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 75284059Swpaul#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 75384059Swpaul 75484059Swpaul/* 75584059Swpaul * Send BD Initiator Selector Control registers 75684059Swpaul */ 75784059Swpaul#define BGE_SBDI_MODE 0x1800 75884059Swpaul#define BGE_SBDI_STATUS 0x1804 75984059Swpaul#define BGE_SBDI_LOC_NIC_PROD0 0x1808 76084059Swpaul#define BGE_SBDI_LOC_NIC_PROD1 0x180C 76184059Swpaul#define BGE_SBDI_LOC_NIC_PROD2 0x1810 76284059Swpaul#define BGE_SBDI_LOC_NIC_PROD3 0x1814 76384059Swpaul#define BGE_SBDI_LOC_NIC_PROD4 0x1818 76484059Swpaul#define BGE_SBDI_LOC_NIC_PROD5 0x181C 76584059Swpaul#define BGE_SBDI_LOC_NIC_PROD6 0x1820 76684059Swpaul#define BGE_SBDI_LOC_NIC_PROD7 0x1824 76784059Swpaul#define BGE_SBDI_LOC_NIC_PROD8 0x1828 76884059Swpaul#define BGE_SBDI_LOC_NIC_PROD9 0x182C 76984059Swpaul#define BGE_SBDI_LOC_NIC_PROD10 0x1830 77084059Swpaul#define BGE_SBDI_LOC_NIC_PROD11 0x1834 77184059Swpaul#define BGE_SBDI_LOC_NIC_PROD12 0x1838 77284059Swpaul#define BGE_SBDI_LOC_NIC_PROD13 0x183C 77384059Swpaul#define BGE_SBDI_LOC_NIC_PROD14 0x1840 77484059Swpaul#define BGE_SBDI_LOC_NIC_PROD15 0x1844 77584059Swpaul 77684059Swpaul/* Send BD Initiator Mode register */ 77784059Swpaul#define BGE_SBDIMODE_RESET 0x00000001 77884059Swpaul#define BGE_SBDIMODE_ENABLE 0x00000002 77984059Swpaul#define BGE_SBDIMODE_ATTN 0x00000004 78084059Swpaul 78184059Swpaul/* Send BD Initiator Status register */ 78284059Swpaul#define BGE_SBDISTAT_ERROR 0x00000004 78384059Swpaul 78484059Swpaul/* 78584059Swpaul * Send BD Completion Control registers 78684059Swpaul */ 78784059Swpaul#define BGE_SBDC_MODE 0x1C00 78884059Swpaul#define BGE_SBDC_STATUS 0x1C04 78984059Swpaul 79084059Swpaul/* Send BD Completion Control Mode register */ 79184059Swpaul#define BGE_SBDCMODE_RESET 0x00000001 79284059Swpaul#define BGE_SBDCMODE_ENABLE 0x00000002 79384059Swpaul#define BGE_SBDCMODE_ATTN 0x00000004 79484059Swpaul 79584059Swpaul/* Send BD Completion Control Status register */ 79684059Swpaul#define BGE_SBDCSTAT_ATTN 0x00000004 79784059Swpaul 79884059Swpaul/* 79984059Swpaul * Receive List Placement Control registers 80084059Swpaul */ 80184059Swpaul#define BGE_RXLP_MODE 0x2000 80284059Swpaul#define BGE_RXLP_STATUS 0x2004 80384059Swpaul#define BGE_RXLP_SEL_LIST_LOCK 0x2008 80484059Swpaul#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 80584059Swpaul#define BGE_RXLP_CFG 0x2010 80684059Swpaul#define BGE_RXLP_STATS_CTL 0x2014 80784059Swpaul#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 80884059Swpaul#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 80984059Swpaul#define BGE_RXLP_HEAD0 0x2100 81084059Swpaul#define BGE_RXLP_TAIL0 0x2104 81184059Swpaul#define BGE_RXLP_COUNT0 0x2108 81284059Swpaul#define BGE_RXLP_HEAD1 0x2110 81384059Swpaul#define BGE_RXLP_TAIL1 0x2114 81484059Swpaul#define BGE_RXLP_COUNT1 0x2118 81584059Swpaul#define BGE_RXLP_HEAD2 0x2120 81684059Swpaul#define BGE_RXLP_TAIL2 0x2124 81784059Swpaul#define BGE_RXLP_COUNT2 0x2128 81884059Swpaul#define BGE_RXLP_HEAD3 0x2130 81984059Swpaul#define BGE_RXLP_TAIL3 0x2134 82084059Swpaul#define BGE_RXLP_COUNT3 0x2138 82184059Swpaul#define BGE_RXLP_HEAD4 0x2140 82284059Swpaul#define BGE_RXLP_TAIL4 0x2144 82384059Swpaul#define BGE_RXLP_COUNT4 0x2148 82484059Swpaul#define BGE_RXLP_HEAD5 0x2150 82584059Swpaul#define BGE_RXLP_TAIL5 0x2154 82684059Swpaul#define BGE_RXLP_COUNT5 0x2158 82784059Swpaul#define BGE_RXLP_HEAD6 0x2160 82884059Swpaul#define BGE_RXLP_TAIL6 0x2164 82984059Swpaul#define BGE_RXLP_COUNT6 0x2168 83084059Swpaul#define BGE_RXLP_HEAD7 0x2170 83184059Swpaul#define BGE_RXLP_TAIL7 0x2174 83284059Swpaul#define BGE_RXLP_COUNT7 0x2178 83384059Swpaul#define BGE_RXLP_HEAD8 0x2180 83484059Swpaul#define BGE_RXLP_TAIL8 0x2184 83584059Swpaul#define BGE_RXLP_COUNT8 0x2188 83684059Swpaul#define BGE_RXLP_HEAD9 0x2190 83784059Swpaul#define BGE_RXLP_TAIL9 0x2194 83884059Swpaul#define BGE_RXLP_COUNT9 0x2198 83984059Swpaul#define BGE_RXLP_HEAD10 0x21A0 84084059Swpaul#define BGE_RXLP_TAIL10 0x21A4 84184059Swpaul#define BGE_RXLP_COUNT10 0x21A8 84284059Swpaul#define BGE_RXLP_HEAD11 0x21B0 84384059Swpaul#define BGE_RXLP_TAIL11 0x21B4 84484059Swpaul#define BGE_RXLP_COUNT11 0x21B8 84584059Swpaul#define BGE_RXLP_HEAD12 0x21C0 84684059Swpaul#define BGE_RXLP_TAIL12 0x21C4 84784059Swpaul#define BGE_RXLP_COUNT12 0x21C8 84884059Swpaul#define BGE_RXLP_HEAD13 0x21D0 84984059Swpaul#define BGE_RXLP_TAIL13 0x21D4 85084059Swpaul#define BGE_RXLP_COUNT13 0x21D8 85184059Swpaul#define BGE_RXLP_HEAD14 0x21E0 85284059Swpaul#define BGE_RXLP_TAIL14 0x21E4 85384059Swpaul#define BGE_RXLP_COUNT14 0x21E8 85484059Swpaul#define BGE_RXLP_HEAD15 0x21F0 85584059Swpaul#define BGE_RXLP_TAIL15 0x21F4 85684059Swpaul#define BGE_RXLP_COUNT15 0x21F8 85784059Swpaul#define BGE_RXLP_LOCSTAT_COS0 0x2200 85884059Swpaul#define BGE_RXLP_LOCSTAT_COS1 0x2204 85984059Swpaul#define BGE_RXLP_LOCSTAT_COS2 0x2208 86084059Swpaul#define BGE_RXLP_LOCSTAT_COS3 0x220C 86184059Swpaul#define BGE_RXLP_LOCSTAT_COS4 0x2210 86284059Swpaul#define BGE_RXLP_LOCSTAT_COS5 0x2214 86384059Swpaul#define BGE_RXLP_LOCSTAT_COS6 0x2218 86484059Swpaul#define BGE_RXLP_LOCSTAT_COS7 0x221C 86584059Swpaul#define BGE_RXLP_LOCSTAT_COS8 0x2220 86684059Swpaul#define BGE_RXLP_LOCSTAT_COS9 0x2224 86784059Swpaul#define BGE_RXLP_LOCSTAT_COS10 0x2228 86884059Swpaul#define BGE_RXLP_LOCSTAT_COS11 0x222C 86984059Swpaul#define BGE_RXLP_LOCSTAT_COS12 0x2230 87084059Swpaul#define BGE_RXLP_LOCSTAT_COS13 0x2234 87184059Swpaul#define BGE_RXLP_LOCSTAT_COS14 0x2238 87284059Swpaul#define BGE_RXLP_LOCSTAT_COS15 0x223C 87384059Swpaul#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 87484059Swpaul#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 87584059Swpaul#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 87684059Swpaul#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 87784059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 87884059Swpaul#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 87984059Swpaul#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 88084059Swpaul 88184059Swpaul 88284059Swpaul/* Receive List Placement mode register */ 88384059Swpaul#define BGE_RXLPMODE_RESET 0x00000001 88484059Swpaul#define BGE_RXLPMODE_ENABLE 0x00000002 88584059Swpaul#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 88684059Swpaul#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 88784059Swpaul#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 88884059Swpaul 88984059Swpaul/* Receive List Placement Status register */ 89084059Swpaul#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 89184059Swpaul#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 89284059Swpaul#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 89384059Swpaul 89484059Swpaul/* 89584059Swpaul * Receive Data and Receive BD Initiator Control Registers 89684059Swpaul */ 89784059Swpaul#define BGE_RDBDI_MODE 0x2400 89884059Swpaul#define BGE_RDBDI_STATUS 0x2404 89984059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 90084059Swpaul#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 90184059Swpaul#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 90284059Swpaul#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 90384059Swpaul#define BGE_RX_STD_RCB_HADDR_HI 0x2450 90484059Swpaul#define BGE_RX_STD_RCB_HADDR_LO 0x2454 90584059Swpaul#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 90684059Swpaul#define BGE_RX_STD_RCB_NICADDR 0x245C 90784059Swpaul#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 90884059Swpaul#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 90984059Swpaul#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 91084059Swpaul#define BGE_RX_MINI_RCB_NICADDR 0x246C 91184059Swpaul#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 91284059Swpaul#define BGE_RDBDI_STD_RX_CONS 0x2474 91384059Swpaul#define BGE_RDBDI_MINI_RX_CONS 0x2478 91484059Swpaul#define BGE_RDBDI_RETURN_PROD0 0x2480 91584059Swpaul#define BGE_RDBDI_RETURN_PROD1 0x2484 91684059Swpaul#define BGE_RDBDI_RETURN_PROD2 0x2488 91784059Swpaul#define BGE_RDBDI_RETURN_PROD3 0x248C 91884059Swpaul#define BGE_RDBDI_RETURN_PROD4 0x2490 91984059Swpaul#define BGE_RDBDI_RETURN_PROD5 0x2494 92084059Swpaul#define BGE_RDBDI_RETURN_PROD6 0x2498 92184059Swpaul#define BGE_RDBDI_RETURN_PROD7 0x249C 92284059Swpaul#define BGE_RDBDI_RETURN_PROD8 0x24A0 92384059Swpaul#define BGE_RDBDI_RETURN_PROD9 0x24A4 92484059Swpaul#define BGE_RDBDI_RETURN_PROD10 0x24A8 92584059Swpaul#define BGE_RDBDI_RETURN_PROD11 0x24AC 92684059Swpaul#define BGE_RDBDI_RETURN_PROD12 0x24B0 92784059Swpaul#define BGE_RDBDI_RETURN_PROD13 0x24B4 92884059Swpaul#define BGE_RDBDI_RETURN_PROD14 0x24B8 92984059Swpaul#define BGE_RDBDI_RETURN_PROD15 0x24BC 93084059Swpaul#define BGE_RDBDI_HWDIAG 0x24C0 93184059Swpaul 93284059Swpaul 93384059Swpaul/* Receive Data and Receive BD Initiator Mode register */ 93484059Swpaul#define BGE_RDBDIMODE_RESET 0x00000001 93584059Swpaul#define BGE_RDBDIMODE_ENABLE 0x00000002 93684059Swpaul#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 93784059Swpaul#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 93884059Swpaul#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 93984059Swpaul 94084059Swpaul/* Receive Data and Receive BD Initiator Status register */ 94184059Swpaul#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 94284059Swpaul#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 94384059Swpaul#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 94484059Swpaul 94584059Swpaul 94684059Swpaul/* 94784059Swpaul * Receive Data Completion Control registers 94884059Swpaul */ 94984059Swpaul#define BGE_RDC_MODE 0x2800 95084059Swpaul 95184059Swpaul/* Receive Data Completion Mode register */ 95284059Swpaul#define BGE_RDCMODE_RESET 0x00000001 95384059Swpaul#define BGE_RDCMODE_ENABLE 0x00000002 95484059Swpaul#define BGE_RDCMODE_ATTN 0x00000004 95584059Swpaul 95684059Swpaul/* 95784059Swpaul * Receive BD Initiator Control registers 95884059Swpaul */ 95984059Swpaul#define BGE_RBDI_MODE 0x2C00 96084059Swpaul#define BGE_RBDI_STATUS 0x2C04 96184059Swpaul#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 96284059Swpaul#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 96384059Swpaul#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 96484059Swpaul#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 96584059Swpaul#define BGE_RBDI_STD_REPL_THRESH 0x2C18 96684059Swpaul#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 96784059Swpaul 96884059Swpaul/* Receive BD Initiator Mode register */ 96984059Swpaul#define BGE_RBDIMODE_RESET 0x00000001 97084059Swpaul#define BGE_RBDIMODE_ENABLE 0x00000002 97184059Swpaul#define BGE_RBDIMODE_ATTN 0x00000004 97284059Swpaul 97384059Swpaul/* Receive BD Initiator Status register */ 97484059Swpaul#define BGE_RBDISTAT_ATTN 0x00000004 97584059Swpaul 97684059Swpaul/* 97784059Swpaul * Receive BD Completion Control registers 97884059Swpaul */ 97984059Swpaul#define BGE_RBDC_MODE 0x3000 98084059Swpaul#define BGE_RBDC_STATUS 0x3004 98184059Swpaul#define BGE_RBDC_JUMBO_BD_PROD 0x3008 98284059Swpaul#define BGE_RBDC_STD_BD_PROD 0x300C 98384059Swpaul#define BGE_RBDC_MINI_BD_PROD 0x3010 98484059Swpaul 98584059Swpaul/* Receive BD completion mode register */ 98684059Swpaul#define BGE_RBDCMODE_RESET 0x00000001 98784059Swpaul#define BGE_RBDCMODE_ENABLE 0x00000002 98884059Swpaul#define BGE_RBDCMODE_ATTN 0x00000004 98984059Swpaul 99084059Swpaul/* Receive BD completion status register */ 99184059Swpaul#define BGE_RBDCSTAT_ERROR 0x00000004 99284059Swpaul 99384059Swpaul/* 99484059Swpaul * Receive List Selector Control registers 99584059Swpaul */ 99684059Swpaul#define BGE_RXLS_MODE 0x3400 99784059Swpaul#define BGE_RXLS_STATUS 0x3404 99884059Swpaul 99984059Swpaul/* Receive List Selector Mode register */ 100084059Swpaul#define BGE_RXLSMODE_RESET 0x00000001 100184059Swpaul#define BGE_RXLSMODE_ENABLE 0x00000002 100284059Swpaul#define BGE_RXLSMODE_ATTN 0x00000004 100384059Swpaul 100484059Swpaul/* Receive List Selector Status register */ 100584059Swpaul#define BGE_RXLSSTAT_ERROR 0x00000004 100684059Swpaul 100784059Swpaul/* 100884059Swpaul * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 100984059Swpaul */ 101084059Swpaul#define BGE_MBCF_MODE 0x3800 101184059Swpaul#define BGE_MBCF_STATUS 0x3804 101284059Swpaul 101384059Swpaul/* Mbuf Cluster Free mode register */ 101484059Swpaul#define BGE_MBCFMODE_RESET 0x00000001 101584059Swpaul#define BGE_MBCFMODE_ENABLE 0x00000002 101684059Swpaul#define BGE_MBCFMODE_ATTN 0x00000004 101784059Swpaul 101884059Swpaul/* Mbuf Cluster Free status register */ 101984059Swpaul#define BGE_MBCFSTAT_ERROR 0x00000004 102084059Swpaul 102184059Swpaul/* 102284059Swpaul * Host Coalescing Control registers 102384059Swpaul */ 102484059Swpaul#define BGE_HCC_MODE 0x3C00 102584059Swpaul#define BGE_HCC_STATUS 0x3C04 102684059Swpaul#define BGE_HCC_RX_COAL_TICKS 0x3C08 102784059Swpaul#define BGE_HCC_TX_COAL_TICKS 0x3C0C 102884059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 102984059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 103084059Swpaul#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 103184059Swpaul#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 103284059Swpaul#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 103384059Swpaul#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 103484059Swpaul#define BGE_HCC_STATS_TICKS 0x3C28 103584059Swpaul#define BGE_HCC_STATS_ADDR_HI 0x3C30 103684059Swpaul#define BGE_HCC_STATS_ADDR_LO 0x3C34 103784059Swpaul#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 103884059Swpaul#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 103984059Swpaul#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 104084059Swpaul#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 104184059Swpaul#define BGE_FLOW_ATTN 0x3C48 104284059Swpaul#define BGE_HCC_JUMBO_BD_CONS 0x3C50 104384059Swpaul#define BGE_HCC_STD_BD_CONS 0x3C54 104484059Swpaul#define BGE_HCC_MINI_BD_CONS 0x3C58 104584059Swpaul#define BGE_HCC_RX_RETURN_PROD0 0x3C80 104684059Swpaul#define BGE_HCC_RX_RETURN_PROD1 0x3C84 104784059Swpaul#define BGE_HCC_RX_RETURN_PROD2 0x3C88 104884059Swpaul#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 104984059Swpaul#define BGE_HCC_RX_RETURN_PROD4 0x3C90 105084059Swpaul#define BGE_HCC_RX_RETURN_PROD5 0x3C94 105184059Swpaul#define BGE_HCC_RX_RETURN_PROD6 0x3C98 105284059Swpaul#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 105384059Swpaul#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 105484059Swpaul#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 105584059Swpaul#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 105684059Swpaul#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 105784059Swpaul#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 105884059Swpaul#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 105984059Swpaul#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 106084059Swpaul#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 106184059Swpaul#define BGE_HCC_TX_BD_CONS0 0x3CC0 106284059Swpaul#define BGE_HCC_TX_BD_CONS1 0x3CC4 106384059Swpaul#define BGE_HCC_TX_BD_CONS2 0x3CC8 106484059Swpaul#define BGE_HCC_TX_BD_CONS3 0x3CCC 106584059Swpaul#define BGE_HCC_TX_BD_CONS4 0x3CD0 106684059Swpaul#define BGE_HCC_TX_BD_CONS5 0x3CD4 106784059Swpaul#define BGE_HCC_TX_BD_CONS6 0x3CD8 106884059Swpaul#define BGE_HCC_TX_BD_CONS7 0x3CDC 106984059Swpaul#define BGE_HCC_TX_BD_CONS8 0x3CE0 107084059Swpaul#define BGE_HCC_TX_BD_CONS9 0x3CE4 107184059Swpaul#define BGE_HCC_TX_BD_CONS10 0x3CE8 107284059Swpaul#define BGE_HCC_TX_BD_CONS11 0x3CEC 107384059Swpaul#define BGE_HCC_TX_BD_CONS12 0x3CF0 107484059Swpaul#define BGE_HCC_TX_BD_CONS13 0x3CF4 107584059Swpaul#define BGE_HCC_TX_BD_CONS14 0x3CF8 107684059Swpaul#define BGE_HCC_TX_BD_CONS15 0x3CFC 107784059Swpaul 107884059Swpaul 107984059Swpaul/* Host coalescing mode register */ 108084059Swpaul#define BGE_HCCMODE_RESET 0x00000001 108184059Swpaul#define BGE_HCCMODE_ENABLE 0x00000002 108284059Swpaul#define BGE_HCCMODE_ATTN 0x00000004 108384059Swpaul#define BGE_HCCMODE_COAL_NOW 0x00000008 108484059Swpaul#define BGE_HCCMODE_MSI_BITS 0x0x000070 108584059Swpaul#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 108684059Swpaul 108784059Swpaul#define BGE_STATBLKSZ_FULL 0x00000000 108884059Swpaul#define BGE_STATBLKSZ_64BYTE 0x00000080 108984059Swpaul#define BGE_STATBLKSZ_32BYTE 0x00000100 109084059Swpaul 109184059Swpaul/* Host coalescing status register */ 109284059Swpaul#define BGE_HCCSTAT_ERROR 0x00000004 109384059Swpaul 109484059Swpaul/* Flow attention register */ 109584059Swpaul#define BGE_FLOWATTN_MB_LOWAT 0x00000040 109684059Swpaul#define BGE_FLOWATTN_MEMARB 0x00000080 109784059Swpaul#define BGE_FLOWATTN_HOSTCOAL 0x00008000 109884059Swpaul#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 109984059Swpaul#define BGE_FLOWATTN_RCB_INVAL 0x00020000 110084059Swpaul#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 110184059Swpaul#define BGE_FLOWATTN_RDBDI 0x00080000 110284059Swpaul#define BGE_FLOWATTN_RXLS 0x00100000 110384059Swpaul#define BGE_FLOWATTN_RXLP 0x00200000 110484059Swpaul#define BGE_FLOWATTN_RBDC 0x00400000 110584059Swpaul#define BGE_FLOWATTN_RBDI 0x00800000 110684059Swpaul#define BGE_FLOWATTN_SDC 0x08000000 110784059Swpaul#define BGE_FLOWATTN_SDI 0x10000000 110884059Swpaul#define BGE_FLOWATTN_SRS 0x20000000 110984059Swpaul#define BGE_FLOWATTN_SBDC 0x40000000 111084059Swpaul#define BGE_FLOWATTN_SBDI 0x80000000 111184059Swpaul 111284059Swpaul/* 111384059Swpaul * Memory arbiter registers 111484059Swpaul */ 111584059Swpaul#define BGE_MARB_MODE 0x4000 111684059Swpaul#define BGE_MARB_STATUS 0x4004 111784059Swpaul#define BGE_MARB_TRAPADDR_HI 0x4008 111884059Swpaul#define BGE_MARB_TRAPADDR_LO 0x400C 111984059Swpaul 112084059Swpaul/* Memory arbiter mode register */ 112184059Swpaul#define BGE_MARBMODE_RESET 0x00000001 112284059Swpaul#define BGE_MARBMODE_ENABLE 0x00000002 112384059Swpaul#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 112484059Swpaul#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 112584059Swpaul#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 112684059Swpaul#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 112784059Swpaul#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 112884059Swpaul#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 112984059Swpaul#define BGE_MARBMODE_PCI_TRAP 0x00000100 113084059Swpaul#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 113184059Swpaul#define BGE_MARBMODE_RXQ_TRAP 0x00000400 113284059Swpaul#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 113384059Swpaul#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 113484059Swpaul#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 113584059Swpaul#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 113684059Swpaul#define BGE_MARBMODE_MBUF_TRAP 0x00008000 113784059Swpaul#define BGE_MARBMODE_TXDI_TRAP 0x00010000 113884059Swpaul#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 113984059Swpaul#define BGE_MARBMODE_TXBD_TRAP 0x00040000 114084059Swpaul#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 114184059Swpaul#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 114284059Swpaul#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 114384059Swpaul#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 114484059Swpaul#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 114584059Swpaul#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 114684059Swpaul#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 114784059Swpaul 114884059Swpaul/* Memory arbiter status register */ 114984059Swpaul#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 115084059Swpaul#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 115184059Swpaul#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 115284059Swpaul#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 115384059Swpaul#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 115484059Swpaul#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 115584059Swpaul#define BGE_MARBSTAT_PCI_TRAP 0x00000100 115684059Swpaul#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 115784059Swpaul#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 115884059Swpaul#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 115984059Swpaul#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 116084059Swpaul#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 116184059Swpaul#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 116284059Swpaul#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 116384059Swpaul#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 116484059Swpaul#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 116584059Swpaul#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 116684059Swpaul#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 116784059Swpaul#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 116884059Swpaul#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 116984059Swpaul#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 117084059Swpaul#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 117184059Swpaul#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 117284059Swpaul#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 117384059Swpaul 117484059Swpaul/* 117584059Swpaul * Buffer manager control registers 117684059Swpaul */ 117784059Swpaul#define BGE_BMAN_MODE 0x4400 117884059Swpaul#define BGE_BMAN_STATUS 0x4404 117984059Swpaul#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 118084059Swpaul#define BGE_BMAN_MBUFPOOL_LEN 0x440C 118184059Swpaul#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 118284059Swpaul#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 118384059Swpaul#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 118484059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 118584059Swpaul#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 118684059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 118784059Swpaul#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 118884059Swpaul#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 118984059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 119084059Swpaul#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 119184059Swpaul#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 119284059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 119384059Swpaul#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 119484059Swpaul#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 119584059Swpaul#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 119684059Swpaul#define BGE_BMAN_HWDIAG_1 0x444C 119784059Swpaul#define BGE_BMAN_HWDIAG_2 0x4450 119884059Swpaul#define BGE_BMAN_HWDIAG_3 0x4454 119984059Swpaul 120084059Swpaul/* Buffer manager mode register */ 120184059Swpaul#define BGE_BMANMODE_RESET 0x00000001 120284059Swpaul#define BGE_BMANMODE_ENABLE 0x00000002 120384059Swpaul#define BGE_BMANMODE_ATTN 0x00000004 120484059Swpaul#define BGE_BMANMODE_TESTMODE 0x00000008 120584059Swpaul#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 120684059Swpaul 120784059Swpaul/* Buffer manager status register */ 120884059Swpaul#define BGE_BMANSTAT_ERRO 0x00000004 120984059Swpaul#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 121084059Swpaul 121184059Swpaul 121284059Swpaul/* 121384059Swpaul * Read DMA Control registers 121484059Swpaul */ 121584059Swpaul#define BGE_RDMA_MODE 0x4800 121684059Swpaul#define BGE_RDMA_STATUS 0x4804 121784059Swpaul 121884059Swpaul/* Read DMA mode register */ 121984059Swpaul#define BGE_RDMAMODE_RESET 0x00000001 122084059Swpaul#define BGE_RDMAMODE_ENABLE 0x00000002 122184059Swpaul#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 122284059Swpaul#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 122384059Swpaul#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 122484059Swpaul#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 122584059Swpaul#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 122684059Swpaul#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 122784059Swpaul#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 122884059Swpaul#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 122984059Swpaul#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 123084059Swpaul 123184059Swpaul/* Read DMA status register */ 123284059Swpaul#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 123384059Swpaul#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 123484059Swpaul#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 123584059Swpaul#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 123684059Swpaul#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 123784059Swpaul#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 123884059Swpaul#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 123984059Swpaul#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 124084059Swpaul 124184059Swpaul/* 124284059Swpaul * Write DMA control registers 124384059Swpaul */ 124484059Swpaul#define BGE_WDMA_MODE 0x4C00 124584059Swpaul#define BGE_WDMA_STATUS 0x4C04 124684059Swpaul 124784059Swpaul/* Write DMA mode register */ 124884059Swpaul#define BGE_WDMAMODE_RESET 0x00000001 124984059Swpaul#define BGE_WDMAMODE_ENABLE 0x00000002 125084059Swpaul#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 125184059Swpaul#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 125284059Swpaul#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 125384059Swpaul#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 125484059Swpaul#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 125584059Swpaul#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 125684059Swpaul#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 125784059Swpaul#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 125884059Swpaul#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 125984059Swpaul 126084059Swpaul/* Write DMA status register */ 126184059Swpaul#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 126284059Swpaul#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 126384059Swpaul#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 126484059Swpaul#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 126584059Swpaul#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 126684059Swpaul#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 126784059Swpaul#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 126884059Swpaul#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 126984059Swpaul 127084059Swpaul 127184059Swpaul/* 127284059Swpaul * RX CPU registers 127384059Swpaul */ 127484059Swpaul#define BGE_RXCPU_MODE 0x5000 127584059Swpaul#define BGE_RXCPU_STATUS 0x5004 127684059Swpaul#define BGE_RXCPU_PC 0x501C 127784059Swpaul 127884059Swpaul/* RX CPU mode register */ 127984059Swpaul#define BGE_RXCPUMODE_RESET 0x00000001 128084059Swpaul#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 128184059Swpaul#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 128284059Swpaul#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 128384059Swpaul#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 128484059Swpaul#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 128584059Swpaul#define BGE_RXCPUMODE_ROMFAIL 0x00000040 128684059Swpaul#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 128784059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 128884059Swpaul#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 128984059Swpaul#define BGE_RXCPUMODE_HALTCPU 0x00000400 129084059Swpaul#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 129184059Swpaul#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 129284059Swpaul#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 129384059Swpaul 129484059Swpaul/* RX CPU status register */ 129584059Swpaul#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 129684059Swpaul#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 129784059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 129884059Swpaul#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 129984059Swpaul#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 130084059Swpaul#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 130184059Swpaul#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 130284059Swpaul#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 130384059Swpaul#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 130484059Swpaul#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 130584059Swpaul#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 130684059Swpaul#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 130784059Swpaul#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 130884059Swpaul#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 130984059Swpaul#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 131084059Swpaul#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 131184059Swpaul#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 131284059Swpaul 131384059Swpaul 131484059Swpaul/* 131584059Swpaul * TX CPU registers 131684059Swpaul */ 131784059Swpaul#define BGE_TXCPU_MODE 0x5400 131884059Swpaul#define BGE_TXCPU_STATUS 0x5404 131984059Swpaul#define BGE_TXCPU_PC 0x541C 132084059Swpaul 132184059Swpaul/* TX CPU mode register */ 132284059Swpaul#define BGE_TXCPUMODE_RESET 0x00000001 132384059Swpaul#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 132484059Swpaul#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 132584059Swpaul#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 132684059Swpaul#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 132784059Swpaul#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 132884059Swpaul#define BGE_TXCPUMODE_ROMFAIL 0x00000040 132984059Swpaul#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 133084059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 133184059Swpaul#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 133284059Swpaul#define BGE_TXCPUMODE_HALTCPU 0x00000400 133384059Swpaul#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 133484059Swpaul#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 133584059Swpaul 133684059Swpaul/* TX CPU status register */ 133784059Swpaul#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 133884059Swpaul#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 133984059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 134084059Swpaul#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 134184059Swpaul#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 134284059Swpaul#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 134384059Swpaul#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 134484059Swpaul#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 134584059Swpaul#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 134684059Swpaul#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 134784059Swpaul#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 134884059Swpaul#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 134984059Swpaul#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 135084059Swpaul#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 135184059Swpaul#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 135284059Swpaul#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 135384059Swpaul#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 135484059Swpaul 135584059Swpaul 135684059Swpaul/* 135784059Swpaul * Low priority mailbox registers 135884059Swpaul */ 135984059Swpaul#define BGE_LPMBX_IRQ0_HI 0x5800 136084059Swpaul#define BGE_LPMBX_IRQ0_LO 0x5804 136184059Swpaul#define BGE_LPMBX_IRQ1_HI 0x5808 136284059Swpaul#define BGE_LPMBX_IRQ1_LO 0x580C 136384059Swpaul#define BGE_LPMBX_IRQ2_HI 0x5810 136484059Swpaul#define BGE_LPMBX_IRQ2_LO 0x5814 136584059Swpaul#define BGE_LPMBX_IRQ3_HI 0x5818 136684059Swpaul#define BGE_LPMBX_IRQ3_LO 0x581C 136784059Swpaul#define BGE_LPMBX_GEN0_HI 0x5820 136884059Swpaul#define BGE_LPMBX_GEN0_LO 0x5824 136984059Swpaul#define BGE_LPMBX_GEN1_HI 0x5828 137084059Swpaul#define BGE_LPMBX_GEN1_LO 0x582C 137184059Swpaul#define BGE_LPMBX_GEN2_HI 0x5830 137284059Swpaul#define BGE_LPMBX_GEN2_LO 0x5834 137384059Swpaul#define BGE_LPMBX_GEN3_HI 0x5828 137484059Swpaul#define BGE_LPMBX_GEN3_LO 0x582C 137584059Swpaul#define BGE_LPMBX_GEN4_HI 0x5840 137684059Swpaul#define BGE_LPMBX_GEN4_LO 0x5844 137784059Swpaul#define BGE_LPMBX_GEN5_HI 0x5848 137884059Swpaul#define BGE_LPMBX_GEN5_LO 0x584C 137984059Swpaul#define BGE_LPMBX_GEN6_HI 0x5850 138084059Swpaul#define BGE_LPMBX_GEN6_LO 0x5854 138184059Swpaul#define BGE_LPMBX_GEN7_HI 0x5858 138284059Swpaul#define BGE_LPMBX_GEN7_LO 0x585C 138384059Swpaul#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 138484059Swpaul#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 138584059Swpaul#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 138684059Swpaul#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 138784059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 138884059Swpaul#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 138984059Swpaul#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 139084059Swpaul#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 139184059Swpaul#define BGE_LPMBX_RX_CONS0_HI 0x5880 139284059Swpaul#define BGE_LPMBX_RX_CONS0_LO 0x5884 139384059Swpaul#define BGE_LPMBX_RX_CONS1_HI 0x5888 139484059Swpaul#define BGE_LPMBX_RX_CONS1_LO 0x588C 139584059Swpaul#define BGE_LPMBX_RX_CONS2_HI 0x5890 139684059Swpaul#define BGE_LPMBX_RX_CONS2_LO 0x5894 139784059Swpaul#define BGE_LPMBX_RX_CONS3_HI 0x5898 139884059Swpaul#define BGE_LPMBX_RX_CONS3_LO 0x589C 139984059Swpaul#define BGE_LPMBX_RX_CONS4_HI 0x58A0 140084059Swpaul#define BGE_LPMBX_RX_CONS4_LO 0x58A4 140184059Swpaul#define BGE_LPMBX_RX_CONS5_HI 0x58A8 140284059Swpaul#define BGE_LPMBX_RX_CONS5_LO 0x58AC 140384059Swpaul#define BGE_LPMBX_RX_CONS6_HI 0x58B0 140484059Swpaul#define BGE_LPMBX_RX_CONS6_LO 0x58B4 140584059Swpaul#define BGE_LPMBX_RX_CONS7_HI 0x58B8 140684059Swpaul#define BGE_LPMBX_RX_CONS7_LO 0x58BC 140784059Swpaul#define BGE_LPMBX_RX_CONS8_HI 0x58C0 140884059Swpaul#define BGE_LPMBX_RX_CONS8_LO 0x58C4 140984059Swpaul#define BGE_LPMBX_RX_CONS9_HI 0x58C8 141084059Swpaul#define BGE_LPMBX_RX_CONS9_LO 0x58CC 141184059Swpaul#define BGE_LPMBX_RX_CONS10_HI 0x58D0 141284059Swpaul#define BGE_LPMBX_RX_CONS10_LO 0x58D4 141384059Swpaul#define BGE_LPMBX_RX_CONS11_HI 0x58D8 141484059Swpaul#define BGE_LPMBX_RX_CONS11_LO 0x58DC 141584059Swpaul#define BGE_LPMBX_RX_CONS12_HI 0x58E0 141684059Swpaul#define BGE_LPMBX_RX_CONS12_LO 0x58E4 141784059Swpaul#define BGE_LPMBX_RX_CONS13_HI 0x58E8 141884059Swpaul#define BGE_LPMBX_RX_CONS13_LO 0x58EC 141984059Swpaul#define BGE_LPMBX_RX_CONS14_HI 0x58F0 142084059Swpaul#define BGE_LPMBX_RX_CONS14_LO 0x58F4 142184059Swpaul#define BGE_LPMBX_RX_CONS15_HI 0x58F8 142284059Swpaul#define BGE_LPMBX_RX_CONS15_LO 0x58FC 142384059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 142484059Swpaul#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 142584059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 142684059Swpaul#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 142784059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 142884059Swpaul#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 142984059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 143084059Swpaul#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 143184059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 143284059Swpaul#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 143384059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 143484059Swpaul#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 143584059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 143684059Swpaul#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 143784059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 143884059Swpaul#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 143984059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 144084059Swpaul#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 144184059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 144284059Swpaul#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 144384059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 144484059Swpaul#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 144584059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 144684059Swpaul#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 144784059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 144884059Swpaul#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 144984059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 145084059Swpaul#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 145184059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 145284059Swpaul#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 145384059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 145484059Swpaul#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 145584059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 145684059Swpaul#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 145784059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 145884059Swpaul#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 145984059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 146084059Swpaul#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 146184059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 146284059Swpaul#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 146384059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 146484059Swpaul#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 146584059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 146684059Swpaul#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 146784059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 146884059Swpaul#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 146984059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 147084059Swpaul#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 147184059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 147284059Swpaul#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 147384059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 147484059Swpaul#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 147584059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 147684059Swpaul#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 147784059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 147884059Swpaul#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 147984059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 148084059Swpaul#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 148184059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 148284059Swpaul#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 148384059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 148484059Swpaul#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 148584059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 148684059Swpaul#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 148784059Swpaul 148884059Swpaul/* 148984059Swpaul * Flow throw Queue reset register 149084059Swpaul */ 149184059Swpaul#define BGE_FTQ_RESET 0x5C00 149284059Swpaul 149384059Swpaul#define BGE_FTQRESET_DMAREAD 0x00000002 149484059Swpaul#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 149584059Swpaul#define BGE_FTQRESET_DMADONE 0x00000010 149684059Swpaul#define BGE_FTQRESET_SBDC 0x00000020 149784059Swpaul#define BGE_FTQRESET_SDI 0x00000040 149884059Swpaul#define BGE_FTQRESET_WDMA 0x00000080 149984059Swpaul#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 150084059Swpaul#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 150184059Swpaul#define BGE_FTQRESET_SDC 0x00000400 150284059Swpaul#define BGE_FTQRESET_HCC 0x00000800 150384059Swpaul#define BGE_FTQRESET_TXFIFO 0x00001000 150484059Swpaul#define BGE_FTQRESET_MBC 0x00002000 150584059Swpaul#define BGE_FTQRESET_RBDC 0x00004000 150684059Swpaul#define BGE_FTQRESET_RXLP 0x00008000 150784059Swpaul#define BGE_FTQRESET_RDBDI 0x00010000 150884059Swpaul#define BGE_FTQRESET_RDC 0x00020000 150984059Swpaul#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 151084059Swpaul 151184059Swpaul/* 151284059Swpaul * Message Signaled Interrupt registers 151384059Swpaul */ 151484059Swpaul#define BGE_MSI_MODE 0x6000 151584059Swpaul#define BGE_MSI_STATUS 0x6004 151684059Swpaul#define BGE_MSI_FIFOACCESS 0x6008 151784059Swpaul 151884059Swpaul/* MSI mode register */ 151984059Swpaul#define BGE_MSIMODE_RESET 0x00000001 152084059Swpaul#define BGE_MSIMODE_ENABLE 0x00000002 152184059Swpaul#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 152284059Swpaul#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 152384059Swpaul#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 152484059Swpaul#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 152584059Swpaul#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 152684059Swpaul 152784059Swpaul/* MSI status register */ 152884059Swpaul#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 152984059Swpaul#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 153084059Swpaul#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 153184059Swpaul#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 153284059Swpaul#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 153384059Swpaul 153484059Swpaul 153584059Swpaul/* 153684059Swpaul * DMA Completion registers 153784059Swpaul */ 153884059Swpaul#define BGE_DMAC_MODE 0x6400 153984059Swpaul 154084059Swpaul/* DMA Completion mode register */ 154184059Swpaul#define BGE_DMACMODE_RESET 0x00000001 154284059Swpaul#define BGE_DMACMODE_ENABLE 0x00000002 154384059Swpaul 154484059Swpaul 154584059Swpaul/* 154684059Swpaul * General control registers. 154784059Swpaul */ 154884059Swpaul#define BGE_MODE_CTL 0x6800 154984059Swpaul#define BGE_MISC_CFG 0x6804 155084059Swpaul#define BGE_MISC_LOCAL_CTL 0x6808 155184059Swpaul#define BGE_EE_ADDR 0x6838 155284059Swpaul#define BGE_EE_DATA 0x683C 155384059Swpaul#define BGE_EE_CTL 0x6840 155484059Swpaul#define BGE_MDI_CTL 0x6844 155584059Swpaul#define BGE_EE_DELAY 0x6848 155684059Swpaul 155784059Swpaul/* Mode control register */ 155884059Swpaul#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 155984059Swpaul#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 156084059Swpaul#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 156184059Swpaul#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 156284059Swpaul#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 156384059Swpaul#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 156484059Swpaul#define BGE_MODECTL_NO_RX_CRC 0x00000400 156584059Swpaul#define BGE_MODECTL_RX_BADFRAMES 0x00000800 156684059Swpaul#define BGE_MODECTL_NO_TX_INTR 0x00002000 156784059Swpaul#define BGE_MODECTL_NO_RX_INTR 0x00004000 156884059Swpaul#define BGE_MODECTL_FORCE_PCI32 0x00008000 156984059Swpaul#define BGE_MODECTL_STACKUP 0x00010000 157084059Swpaul#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 157184059Swpaul#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 157284059Swpaul#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 157384059Swpaul#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 157484059Swpaul#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 157584059Swpaul#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 157684059Swpaul#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 157784059Swpaul#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 157884059Swpaul#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 157984059Swpaul#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 158084059Swpaul 158184059Swpaul/* Misc. config register */ 158284059Swpaul#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 158384059Swpaul#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 158484059Swpaul 158584059Swpaul#define BGE_32BITTIME_66MHZ (0x41 << 1) 158684059Swpaul 158784059Swpaul/* Misc. Local Control */ 158884059Swpaul#define BGE_MLC_INTR_STATE 0x00000001 158984059Swpaul#define BGE_MLC_INTR_CLR 0x00000002 159084059Swpaul#define BGE_MLC_INTR_SET 0x00000004 159184059Swpaul#define BGE_MLC_INTR_ONATTN 0x00000008 159284059Swpaul#define BGE_MLC_MISCIO_IN0 0x00000100 159384059Swpaul#define BGE_MLC_MISCIO_IN1 0x00000200 159484059Swpaul#define BGE_MLC_MISCIO_IN2 0x00000400 159584059Swpaul#define BGE_MLC_MISCIO_OUTEN0 0x00000800 159684059Swpaul#define BGE_MLC_MISCIO_OUTEN1 0x00001000 159784059Swpaul#define BGE_MLC_MISCIO_OUTEN2 0x00002000 159884059Swpaul#define BGE_MLC_MISCIO_OUT0 0x00004000 159984059Swpaul#define BGE_MLC_MISCIO_OUT1 0x00008000 160084059Swpaul#define BGE_MLC_MISCIO_OUT2 0x00010000 160184059Swpaul#define BGE_MLC_EXTRAM_ENB 0x00020000 160284059Swpaul#define BGE_MLC_SRAM_SIZE 0x001C0000 160384059Swpaul#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 160484059Swpaul#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 160584059Swpaul#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 160684059Swpaul#define BGE_MLC_AUTO_EEPROM 0x01000000 160784059Swpaul 160884059Swpaul#define BGE_SSRAMSIZE_256KB 0x00000000 160984059Swpaul#define BGE_SSRAMSIZE_512KB 0x00040000 161084059Swpaul#define BGE_SSRAMSIZE_1MB 0x00080000 161184059Swpaul#define BGE_SSRAMSIZE_2MB 0x000C0000 161284059Swpaul#define BGE_SSRAMSIZE_4MB 0x00100000 161384059Swpaul#define BGE_SSRAMSIZE_8MB 0x00140000 161484059Swpaul#define BGE_SSRAMSIZE_16M 0x00180000 161584059Swpaul 161684059Swpaul/* EEPROM address register */ 161784059Swpaul#define BGE_EEADDR_ADDRESS 0x0000FFFC 161884059Swpaul#define BGE_EEADDR_HALFCLK 0x01FF0000 161984059Swpaul#define BGE_EEADDR_START 0x02000000 162084059Swpaul#define BGE_EEADDR_DEVID 0x1C000000 162184059Swpaul#define BGE_EEADDR_RESET 0x20000000 162284059Swpaul#define BGE_EEADDR_DONE 0x40000000 162384059Swpaul#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 162484059Swpaul 162584059Swpaul#define BGE_EEDEVID(x) ((x & 7) << 26) 162684059Swpaul#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 162784059Swpaul#define BGE_HALFCLK_384SCL 0x60 162884059Swpaul#define BGE_EE_READCMD \ 162984059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 163084059Swpaul BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 163184059Swpaul#define BGE_EE_WRCMD \ 163284059Swpaul (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 163384059Swpaul BGE_EEADDR_START|BGE_EEADDR_DONE) 163484059Swpaul 163584059Swpaul/* EEPROM Control register */ 163684059Swpaul#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 163784059Swpaul#define BGE_EECTL_CLKOUT 0x00000002 163884059Swpaul#define BGE_EECTL_CLKIN 0x00000004 163984059Swpaul#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 164084059Swpaul#define BGE_EECTL_DATAOUT 0x00000010 164184059Swpaul#define BGE_EECTL_DATAIN 0x00000020 164284059Swpaul 164384059Swpaul/* MDI (MII/GMII) access register */ 164484059Swpaul#define BGE_MDI_DATA 0x00000001 164584059Swpaul#define BGE_MDI_DIR 0x00000002 164684059Swpaul#define BGE_MDI_SEL 0x00000004 164784059Swpaul#define BGE_MDI_CLK 0x00000008 164884059Swpaul 164984059Swpaul#define BGE_MEMWIN_START 0x00008000 165084059Swpaul#define BGE_MEMWIN_END 0x0000FFFF 165184059Swpaul 165284059Swpaul 165384059Swpaul#define BGE_MEMWIN_READ(sc, x, val) \ 165484059Swpaul do { \ 165584059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 165684059Swpaul (0xFFFF0000 & x), 4); \ 165784059Swpaul val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 165884059Swpaul } while(0) 165984059Swpaul 166084059Swpaul#define BGE_MEMWIN_WRITE(sc, x, val) \ 166184059Swpaul do { \ 166284059Swpaul pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 166384059Swpaul (0xFFFF0000 & x), 4); \ 166484059Swpaul CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 166584059Swpaul } while(0) 166684059Swpaul 166784059Swpaul/* 166884059Swpaul * This magic number is used to prevent PXE restart when we 166984059Swpaul * issue a software reset. We write this magic number to the 167084059Swpaul * firmware mailbox at 0xB50 in order to prevent the PXE boot 167184059Swpaul * code from running. 167284059Swpaul */ 167384059Swpaul#define BGE_MAGIC_NUMBER 0x4B657654 167484059Swpaul 167584059Swpaultypedef struct { 167684059Swpaul u_int32_t bge_addr_hi; 167784059Swpaul u_int32_t bge_addr_lo; 167884059Swpaul} bge_hostaddr; 167984059Swpaul#define BGE_HOSTADDR(x) x.bge_addr_lo 168084059Swpaul 168184059Swpaul/* Ring control block structure */ 168284059Swpaulstruct bge_rcb { 168384059Swpaul bge_hostaddr bge_hostaddr; 168484059Swpaul u_int16_t bge_flags; 168584059Swpaul u_int16_t bge_max_len; 168684059Swpaul u_int32_t bge_nicaddr; 168784059Swpaul}; 168884059Swpaul 168984059Swpaulstruct bge_rcb_opaque { 169084059Swpaul u_int32_t bge_reg0; 169184059Swpaul u_int32_t bge_reg1; 169284059Swpaul u_int32_t bge_reg2; 169384059Swpaul u_int32_t bge_reg3; 169484059Swpaul}; 169584059Swpaul 169684059Swpaul#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 169784059Swpaul#define BGE_RCB_FLAG_RING_DISABLED 0x0002 169884059Swpaul 169984059Swpaulstruct bge_tx_bd { 170084059Swpaul bge_hostaddr bge_addr; 170184059Swpaul u_int16_t bge_flags; 170284059Swpaul u_int16_t bge_len; 170384059Swpaul u_int16_t bge_vlan_tag; 170484059Swpaul u_int16_t bge_rsvd; 170584059Swpaul}; 170684059Swpaul 170784059Swpaul#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 170884059Swpaul#define BGE_TXBDFLAG_IP_CSUM 0x0002 170984059Swpaul#define BGE_TXBDFLAG_END 0x0004 171084059Swpaul#define BGE_TXBDFLAG_IP_FRAG 0x0008 171184059Swpaul#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 171284059Swpaul#define BGE_TXBDFLAG_VLAN_TAG 0x0040 171384059Swpaul#define BGE_TXBDFLAG_COAL_NOW 0x0080 171484059Swpaul#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 171584059Swpaul#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 171684059Swpaul#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 171784059Swpaul#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 171884059Swpaul#define BGE_TXBDFLAG_NO_CRC 0x8000 171984059Swpaul 172084059Swpaul#define BGE_NIC_TXRING_ADDR(ringno, size) \ 172184059Swpaul BGE_SEND_RING_1_TO_4 + \ 172284059Swpaul ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 172384059Swpaul 172484059Swpaulstruct bge_rx_bd { 172584059Swpaul bge_hostaddr bge_addr; 172684059Swpaul u_int16_t bge_len; 172784059Swpaul u_int16_t bge_idx; 172884059Swpaul u_int16_t bge_flags; 172984059Swpaul u_int16_t bge_type; 173084059Swpaul u_int16_t bge_tcp_udp_csum; 173184059Swpaul u_int16_t bge_ip_csum; 173284059Swpaul u_int16_t bge_vlan_tag; 173384059Swpaul u_int16_t bge_error_flag; 173484059Swpaul u_int32_t bge_rsvd; 173584059Swpaul u_int32_t bge_opaque; 173684059Swpaul}; 173784059Swpaul 173884059Swpaul#define BGE_RXBDFLAG_END 0x0004 173984059Swpaul#define BGE_RXBDFLAG_JUMBO_RING 0x0020 174084059Swpaul#define BGE_RXBDFLAG_VLAN_TAG 0x0040 174184059Swpaul#define BGE_RXBDFLAG_ERROR 0x0400 174284059Swpaul#define BGE_RXBDFLAG_MINI_RING 0x0800 174384059Swpaul#define BGE_RXBDFLAG_IP_CSUM 0x1000 174484059Swpaul#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 174584059Swpaul#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 174684059Swpaul 174784059Swpaul#define BGE_RXERRFLAG_BAD_CRC 0x0001 174884059Swpaul#define BGE_RXERRFLAG_COLL_DETECT 0x0002 174984059Swpaul#define BGE_RXERRFLAG_LINK_LOST 0x0004 175084059Swpaul#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 175184059Swpaul#define BGE_RXERRFLAG_MAC_ABORT 0x0010 175284059Swpaul#define BGE_RXERRFLAG_RUNT 0x0020 175384059Swpaul#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 175484059Swpaul#define BGE_RXERRFLAG_GIANT 0x0080 175584059Swpaul 175684059Swpaulstruct bge_sts_idx { 175784059Swpaul u_int16_t bge_rx_prod_idx; 175884059Swpaul u_int16_t bge_tx_cons_idx; 175984059Swpaul}; 176084059Swpaul 176184059Swpaulstruct bge_status_block { 176284059Swpaul u_int32_t bge_status; 176384059Swpaul u_int32_t bge_rsvd0; 176484059Swpaul u_int16_t bge_rx_jumbo_cons_idx; 176584059Swpaul u_int16_t bge_rx_std_cons_idx; 176684059Swpaul u_int16_t bge_rx_mini_cons_idx; 176784059Swpaul u_int16_t bge_rsvd1; 176884059Swpaul struct bge_sts_idx bge_idx[16]; 176984059Swpaul}; 177084059Swpaul 177184059Swpaul#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 177284059Swpaul#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 177384059Swpaul 177484059Swpaul#define BGE_STATFLAG_UPDATED 0x00000001 177584059Swpaul#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 177684059Swpaul#define BGE_STATFLAG_ERROR 0x00000004 177784059Swpaul 177884059Swpaul 177984059Swpaul/* 178084059Swpaul * Broadcom Vendor ID 178184059Swpaul * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 178284059Swpaul * even though they're now manufactured by Broadcom) 178384059Swpaul */ 178484059Swpaul#define BCOM_VENDORID 0x14E4 178584059Swpaul#define BCOM_DEVICEID_BCM5700 0x1644 178684059Swpaul#define BCOM_DEVICEID_BCM5701 0x1645 1787104102Siwasaki#define BCOM_DEVICEID_BCM5702X 0x16A6 1788103103Sjdp#define BCOM_DEVICEID_BCM5703X 0x16A7 178984059Swpaul 179084059Swpaul/* 179184059Swpaul * Alteon AceNIC PCI vendor/device ID. 179284059Swpaul */ 179384059Swpaul#define ALT_VENDORID 0x12AE 179484059Swpaul#define ALT_DEVICEID_ACENIC 0x0001 179584059Swpaul#define ALT_DEVICEID_ACENIC_COPPER 0x0002 179684059Swpaul#define ALT_DEVICEID_BCM5700 0x0003 179784059Swpaul#define ALT_DEVICEID_BCM5701 0x0004 179884059Swpaul 179984059Swpaul/* 180084059Swpaul * 3Com 3c985 PCI vendor/device ID. 180184059Swpaul */ 180284059Swpaul#define TC_VENDORID 0x10B7 180384059Swpaul#define TC_DEVICEID_3C985 0x0001 180484059Swpaul#define TC_DEVICEID_3C996 0x0003 180584059Swpaul 180684059Swpaul/* 180784059Swpaul * SysKonnect PCI vendor ID 180884059Swpaul */ 180984059Swpaul#define SK_VENDORID 0x1148 181084059Swpaul#define SK_DEVICEID_ALTIMA 0x4400 181184059Swpaul#define SK_SUBSYSID_9D21 0x4421 181284059Swpaul#define SK_SUBSYSID_9D41 0x4441 181384059Swpaul 181484059Swpaul/* 181589835Sjdp * Altima PCI vendor/device ID. 181689835Sjdp */ 181789835Sjdp#define ALTIMA_VENDORID 0x173b 181889835Sjdp#define ALTIMA_DEVICE_AC1000 0x03e8 1819100695Sjdp#define ALTIMA_DEVICE_AC9100 0x03ea 182089835Sjdp 182189835Sjdp/* 182284059Swpaul * Offset of MAC address inside EEPROM. 182384059Swpaul */ 182484059Swpaul#define BGE_EE_MAC_OFFSET 0x7C 182584059Swpaul#define BGE_EE_HWCFG_OFFSET 0xC8 182684059Swpaul 182793751Swpaul#define BGE_HWCFG_VOLTAGE 0x00000003 182893751Swpaul#define BGE_HWCFG_PHYLED_MODE 0x0000000C 182993751Swpaul#define BGE_HWCFG_MEDIA 0x00000030 183093751Swpaul 183193751Swpaul#define BGE_VOLTAGE_1POINT3 0x00000000 183293751Swpaul#define BGE_VOLTAGE_1POINT8 0x00000001 183393751Swpaul 183493751Swpaul#define BGE_PHYLEDMODE_UNSPEC 0x00000000 183593751Swpaul#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 183693751Swpaul#define BGE_PHYLEDMODE_SINGLELED 0x00000008 183793751Swpaul 183893751Swpaul#define BGE_MEDIA_UNSPEC 0x00000000 183993751Swpaul#define BGE_MEDIA_COPPER 0x00000010 184093751Swpaul#define BGE_MEDIA_FIBER 0x00000020 184193751Swpaul 184284059Swpaul#define BGE_PCI_READ_CMD 0x06000000 184384059Swpaul#define BGE_PCI_WRITE_CMD 0x70000000 184484059Swpaul 184584059Swpaul#define BGE_TICKS_PER_SEC 1000000 184684059Swpaul 184784059Swpaul/* 184884059Swpaul * Ring size constants. 184984059Swpaul */ 185084059Swpaul#define BGE_EVENT_RING_CNT 256 185184059Swpaul#define BGE_CMD_RING_CNT 64 185284059Swpaul#define BGE_STD_RX_RING_CNT 512 185384059Swpaul#define BGE_JUMBO_RX_RING_CNT 256 185484059Swpaul#define BGE_MINI_RX_RING_CNT 1024 185584059Swpaul#define BGE_RETURN_RING_CNT 1024 185684059Swpaul 185784059Swpaul/* 185884059Swpaul * Possible TX ring sizes. 185984059Swpaul */ 186084059Swpaul#define BGE_TX_RING_CNT_128 128 186184059Swpaul#define BGE_TX_RING_BASE_128 0x3800 186284059Swpaul 186384059Swpaul#define BGE_TX_RING_CNT_256 256 186484059Swpaul#define BGE_TX_RING_BASE_256 0x3000 186584059Swpaul 186684059Swpaul#define BGE_TX_RING_CNT_512 512 186784059Swpaul#define BGE_TX_RING_BASE_512 0x2000 186884059Swpaul 186984059Swpaul#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 187084059Swpaul#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 187184059Swpaul 187284059Swpaul/* 187384059Swpaul * Tigon III statistics counters. 187484059Swpaul */ 187584059Swpaulstruct bge_stats { 187684059Swpaul u_int8_t Reserved0[256]; 187784059Swpaul 187884059Swpaul /* Statistics maintained by Receive MAC. */ 187984059Swpaul bge_hostaddr ifHCInOctets; 188084059Swpaul bge_hostaddr Reserved1; 188184059Swpaul bge_hostaddr etherStatsFragments; 188284059Swpaul bge_hostaddr ifHCInUcastPkts; 188384059Swpaul bge_hostaddr ifHCInMulticastPkts; 188484059Swpaul bge_hostaddr ifHCInBroadcastPkts; 188584059Swpaul bge_hostaddr dot3StatsFCSErrors; 188684059Swpaul bge_hostaddr dot3StatsAlignmentErrors; 188784059Swpaul bge_hostaddr xonPauseFramesReceived; 188884059Swpaul bge_hostaddr xoffPauseFramesReceived; 188984059Swpaul bge_hostaddr macControlFramesReceived; 189084059Swpaul bge_hostaddr xoffStateEntered; 189184059Swpaul bge_hostaddr dot3StatsFramesTooLong; 189284059Swpaul bge_hostaddr etherStatsJabbers; 189384059Swpaul bge_hostaddr etherStatsUndersizePkts; 189484059Swpaul bge_hostaddr inRangeLengthError; 189584059Swpaul bge_hostaddr outRangeLengthError; 189684059Swpaul bge_hostaddr etherStatsPkts64Octets; 189784059Swpaul bge_hostaddr etherStatsPkts65Octetsto127Octets; 189884059Swpaul bge_hostaddr etherStatsPkts128Octetsto255Octets; 189984059Swpaul bge_hostaddr etherStatsPkts256Octetsto511Octets; 190084059Swpaul bge_hostaddr etherStatsPkts512Octetsto1023Octets; 190184059Swpaul bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 190284059Swpaul bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 190384059Swpaul bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 190484059Swpaul bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 190584059Swpaul bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 190684059Swpaul 190784059Swpaul bge_hostaddr Unused1[37]; 190884059Swpaul 190984059Swpaul /* Statistics maintained by Transmit MAC. */ 191084059Swpaul bge_hostaddr ifHCOutOctets; 191184059Swpaul bge_hostaddr Reserved2; 191284059Swpaul bge_hostaddr etherStatsCollisions; 191384059Swpaul bge_hostaddr outXonSent; 191484059Swpaul bge_hostaddr outXoffSent; 191584059Swpaul bge_hostaddr flowControlDone; 191684059Swpaul bge_hostaddr dot3StatsInternalMacTransmitErrors; 191784059Swpaul bge_hostaddr dot3StatsSingleCollisionFrames; 191884059Swpaul bge_hostaddr dot3StatsMultipleCollisionFrames; 191984059Swpaul bge_hostaddr dot3StatsDeferredTransmissions; 192084059Swpaul bge_hostaddr Reserved3; 192184059Swpaul bge_hostaddr dot3StatsExcessiveCollisions; 192284059Swpaul bge_hostaddr dot3StatsLateCollisions; 192384059Swpaul bge_hostaddr dot3Collided2Times; 192484059Swpaul bge_hostaddr dot3Collided3Times; 192584059Swpaul bge_hostaddr dot3Collided4Times; 192684059Swpaul bge_hostaddr dot3Collided5Times; 192784059Swpaul bge_hostaddr dot3Collided6Times; 192884059Swpaul bge_hostaddr dot3Collided7Times; 192984059Swpaul bge_hostaddr dot3Collided8Times; 193084059Swpaul bge_hostaddr dot3Collided9Times; 193184059Swpaul bge_hostaddr dot3Collided10Times; 193284059Swpaul bge_hostaddr dot3Collided11Times; 193384059Swpaul bge_hostaddr dot3Collided12Times; 193484059Swpaul bge_hostaddr dot3Collided13Times; 193584059Swpaul bge_hostaddr dot3Collided14Times; 193684059Swpaul bge_hostaddr dot3Collided15Times; 193784059Swpaul bge_hostaddr ifHCOutUcastPkts; 193884059Swpaul bge_hostaddr ifHCOutMulticastPkts; 193984059Swpaul bge_hostaddr ifHCOutBroadcastPkts; 194084059Swpaul bge_hostaddr dot3StatsCarrierSenseErrors; 194184059Swpaul bge_hostaddr ifOutDiscards; 194284059Swpaul bge_hostaddr ifOutErrors; 194384059Swpaul 194484059Swpaul bge_hostaddr Unused2[31]; 194584059Swpaul 194684059Swpaul /* Statistics maintained by Receive List Placement. */ 194784059Swpaul bge_hostaddr COSIfHCInPkts[16]; 194884059Swpaul bge_hostaddr COSFramesDroppedDueToFilters; 194984059Swpaul bge_hostaddr nicDmaWriteQueueFull; 195084059Swpaul bge_hostaddr nicDmaWriteHighPriQueueFull; 195184059Swpaul bge_hostaddr nicNoMoreRxBDs; 195284059Swpaul bge_hostaddr ifInDiscards; 195384059Swpaul bge_hostaddr ifInErrors; 195484059Swpaul bge_hostaddr nicRecvThresholdHit; 195584059Swpaul 195684059Swpaul bge_hostaddr Unused3[9]; 195784059Swpaul 195884059Swpaul /* Statistics maintained by Send Data Initiator. */ 195984059Swpaul bge_hostaddr COSIfHCOutPkts[16]; 196084059Swpaul bge_hostaddr nicDmaReadQueueFull; 196184059Swpaul bge_hostaddr nicDmaReadHighPriQueueFull; 196284059Swpaul bge_hostaddr nicSendDataCompQueueFull; 196384059Swpaul 196484059Swpaul /* Statistics maintained by Host Coalescing. */ 196584059Swpaul bge_hostaddr nicRingSetSendProdIndex; 196684059Swpaul bge_hostaddr nicRingStatusUpdate; 196784059Swpaul bge_hostaddr nicInterrupts; 196884059Swpaul bge_hostaddr nicAvoidedInterrupts; 196984059Swpaul bge_hostaddr nicSendThresholdHit; 197084059Swpaul 197184059Swpaul u_int8_t Reserved4[320]; 197284059Swpaul}; 197384059Swpaul 197484059Swpaul/* 197584059Swpaul * Tigon general information block. This resides in host memory 197684059Swpaul * and contains the status counters, ring control blocks and 197784059Swpaul * producer pointers. 197884059Swpaul */ 197984059Swpaul 198084059Swpaulstruct bge_gib { 198184059Swpaul struct bge_stats bge_stats; 198284059Swpaul struct bge_rcb bge_tx_rcb[16]; 198384059Swpaul struct bge_rcb bge_std_rx_rcb; 198484059Swpaul struct bge_rcb bge_jumbo_rx_rcb; 198584059Swpaul struct bge_rcb bge_mini_rx_rcb; 198684059Swpaul struct bge_rcb bge_return_rcb; 198784059Swpaul}; 198884059Swpaul 198984059Swpaul/* 199084059Swpaul * NOTE! On the Alpha, we have an alignment constraint. 199184059Swpaul * The first thing in the packet is a 14-byte Ethernet header. 199284059Swpaul * This means that the packet is misaligned. To compensate, 199384059Swpaul * we actually offset the data 2 bytes into the cluster. This 199484059Swpaul * alignes the packet after the Ethernet header at a 32-bit 199584059Swpaul * boundary. 199684059Swpaul */ 199784059Swpaul 199884059Swpaul#define ETHER_ALIGN 2 199984059Swpaul 200084059Swpaul#define BGE_FRAMELEN 1518 200184059Swpaul#define BGE_MAX_FRAMELEN 1536 200284059Swpaul#define BGE_JUMBO_FRAMELEN 9018 200384059Swpaul#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 200484059Swpaul#define BGE_PAGE_SIZE PAGE_SIZE 200584059Swpaul#define BGE_MIN_FRAMELEN 60 200684059Swpaul 200784059Swpaul/* 200884059Swpaul * Other utility macros. 200984059Swpaul */ 201084059Swpaul#define BGE_INC(x, y) (x) = (x + 1) % y 201184059Swpaul 201284059Swpaul/* 201384059Swpaul * Vital product data and structures. 201484059Swpaul */ 201584059Swpaul#define BGE_VPD_FLAG 0x8000 201684059Swpaul 201784059Swpaul/* VPD structures */ 201884059Swpaulstruct vpd_res { 201984059Swpaul u_int8_t vr_id; 202084059Swpaul u_int8_t vr_len; 202184059Swpaul u_int8_t vr_pad; 202284059Swpaul}; 202384059Swpaul 202484059Swpaulstruct vpd_key { 202584059Swpaul char vk_key[2]; 202684059Swpaul u_int8_t vk_len; 202784059Swpaul}; 202884059Swpaul 202984059Swpaul#define VPD_RES_ID 0x82 /* ID string */ 203084059Swpaul#define VPD_RES_READ 0x90 /* start of read only area */ 203184059Swpaul#define VPD_RES_WRITE 0x81 /* start of read/write area */ 203284059Swpaul#define VPD_RES_END 0x78 /* end tag */ 203384059Swpaul 203484059Swpaul 203584059Swpaul/* 203684059Swpaul * Register access macros. The Tigon always uses memory mapped register 203784059Swpaul * accesses and all registers must be accessed with 32 bit operations. 203884059Swpaul */ 203984059Swpaul 204084059Swpaul#define CSR_WRITE_4(sc, reg, val) \ 204184059Swpaul bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 204284059Swpaul 204384059Swpaul#define CSR_READ_4(sc, reg) \ 204484059Swpaul bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 204584059Swpaul 204684059Swpaul#define BGE_SETBIT(sc, reg, x) \ 2047106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 204884059Swpaul#define BGE_CLRBIT(sc, reg, x) \ 2049106696Salfred CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 205084059Swpaul 205184059Swpaul#define PCI_SETBIT(dev, reg, x, s) \ 2052106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 205384059Swpaul#define PCI_CLRBIT(dev, reg, x, s) \ 2054106696Salfred pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 205584059Swpaul 205684059Swpaul/* 205784059Swpaul * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 205884059Swpaul * values are tuneable. They control the actual amount of buffers 205984059Swpaul * allocated for the standard, mini and jumbo receive rings. 206084059Swpaul */ 206184059Swpaul 206284059Swpaul#define BGE_SSLOTS 256 206384059Swpaul#define BGE_MSLOTS 256 206484059Swpaul#define BGE_JSLOTS 384 206584059Swpaul 206684059Swpaul#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 206784059Swpaul#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 206884059Swpaul (BGE_JRAWLEN % sizeof(u_int64_t)))) 206984059Swpaul#define BGE_JPAGESZ PAGE_SIZE 207084059Swpaul#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 207184059Swpaul#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 207284059Swpaul 207384059Swpaul/* 207484059Swpaul * Ring structures. Most of these reside in host memory and we tell 207584059Swpaul * the NIC where they are via the ring control blocks. The exceptions 207684059Swpaul * are the tx and command rings, which live in NIC memory and which 207784059Swpaul * we access via the shared memory window. 207884059Swpaul */ 207984059Swpaulstruct bge_ring_data { 208084059Swpaul struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 208184059Swpaul struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 208284059Swpaul struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 208384059Swpaul struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 208484059Swpaul struct bge_status_block bge_status_block; 208584059Swpaul struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 208684059Swpaul struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 208784059Swpaul struct bge_gib bge_info; 208884059Swpaul}; 208984059Swpaul 209084059Swpaul/* 209184059Swpaul * Mbuf pointers. We need these to keep track of the virtual addresses 209284059Swpaul * of our mbuf chains since we can only convert from physical to virtual, 209384059Swpaul * not the other way around. 209484059Swpaul */ 209584059Swpaulstruct bge_chain_data { 209684059Swpaul struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 209784059Swpaul struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 209884059Swpaul struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 209984059Swpaul struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 210084059Swpaul /* Stick the jumbo mem management stuff here too. */ 210184059Swpaul caddr_t bge_jslots[BGE_JSLOTS]; 210284059Swpaul void *bge_jumbo_buf; 210384059Swpaul}; 210484059Swpaul 210584059Swpaulstruct bge_type { 210684059Swpaul u_int16_t bge_vid; 210784059Swpaul u_int16_t bge_did; 210884059Swpaul char *bge_name; 210984059Swpaul}; 211084059Swpaul 211184059Swpaul#define BGE_HWREV_TIGON 0x01 211284059Swpaul#define BGE_HWREV_TIGON_II 0x02 211384059Swpaul#define BGE_TIMEOUT 1000 211484059Swpaul#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 211584059Swpaul 211684059Swpaulstruct bge_jpool_entry { 211784059Swpaul int slot; 211884059Swpaul SLIST_ENTRY(bge_jpool_entry) jpool_entries; 211984059Swpaul}; 212084059Swpaul 212184059Swpaulstruct bge_bcom_hack { 212284059Swpaul int reg; 212384059Swpaul int val; 212484059Swpaul}; 212584059Swpaul 212684059Swpaulstruct bge_softc { 212784059Swpaul struct arpcom arpcom; /* interface info */ 212884059Swpaul device_t bge_dev; 212984059Swpaul device_t bge_miibus; 213084059Swpaul bus_space_handle_t bge_bhandle; 213184059Swpaul vm_offset_t bge_vhandle; 213284059Swpaul bus_space_tag_t bge_btag; 213384059Swpaul void *bge_intrhand; 213484059Swpaul struct resource *bge_irq; 213584059Swpaul struct resource *bge_res; 213684059Swpaul struct ifmedia bge_ifmedia; /* TBI media info */ 213784059Swpaul u_int8_t bge_unit; /* interface number */ 213884059Swpaul u_int8_t bge_extram; /* has external SSRAM */ 213984059Swpaul u_int8_t bge_tbi; 214098779Sjdp u_int8_t bge_rx_alignment_bug; 214192934Swpaul u_int32_t bge_asicrev; 214284059Swpaul struct bge_ring_data *bge_rdata; /* rings */ 214384059Swpaul struct bge_chain_data bge_cdata; /* mbufs */ 214484059Swpaul u_int16_t bge_tx_saved_considx; 214584059Swpaul u_int16_t bge_rx_saved_considx; 214684059Swpaul u_int16_t bge_ev_saved_considx; 214784059Swpaul u_int16_t bge_std; /* current std ring head */ 214884059Swpaul u_int16_t bge_jumbo; /* current jumo ring head */ 214984059Swpaul SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 215084059Swpaul SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 215184059Swpaul u_int32_t bge_stat_ticks; 215284059Swpaul u_int32_t bge_rx_coal_ticks; 215384059Swpaul u_int32_t bge_tx_coal_ticks; 215484059Swpaul u_int32_t bge_rx_max_coal_bds; 215584059Swpaul u_int32_t bge_tx_max_coal_bds; 215684059Swpaul u_int32_t bge_tx_buf_ratio; 215784059Swpaul int bge_if_flags; 215884059Swpaul int bge_txcnt; 215984059Swpaul int bge_link; 216084059Swpaul struct callout_handle bge_stat_ch; 216184059Swpaul char *bge_vpd_prodname; 216284059Swpaul char *bge_vpd_readonly; 216384059Swpaul}; 216484059Swpaul 216584059Swpaul#ifdef __alpha__ 216684059Swpaul#undef vtophys 216784059Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 216884059Swpaul#endif 2169