if_athioctl.h revision 238638
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athioctl.h 238638 2012-07-20 02:17:48Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Ioctl-related defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHIOCTL_H 36116743Ssam#define _DEV_ATH_ATHIOCTL_H 37116743Ssam 38116743Ssamstruct ath_tx_aggr_stats { 39116743Ssam u_int32_t aggr_pkts[64]; 40116743Ssam u_int32_t aggr_single_pkt; 41116743Ssam u_int32_t aggr_nonbaw_pkt; 42155492Ssam u_int32_t aggr_aggr_pkt; 43138570Ssam u_int32_t aggr_baw_closed_single_pkt; 44116743Ssam u_int32_t aggr_low_hwq_single_pkt; 45116743Ssam u_int32_t aggr_sched_nopkt; 46116743Ssam u_int32_t aggr_rts_aggr_limited; 47138570Ssam}; 48116743Ssam 49138570Ssamstruct ath_intr_stats { 50116743Ssam u_int32_t sync_intr[32]; 51116743Ssam}; 52116743Ssam 53116743Ssamstruct ath_stats { 54116743Ssam u_int32_t ast_watchdog; /* device reset by watchdog */ 55116743Ssam u_int32_t ast_hardware; /* fatal hardware error interrupts */ 56116743Ssam u_int32_t ast_bmiss; /* beacon miss interrupts */ 57116743Ssam u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */ 58116743Ssam u_int32_t ast_bstuck; /* beacon stuck interrupts */ 59116743Ssam u_int32_t ast_rxorn; /* rx overrun interrupts */ 60116743Ssam u_int32_t ast_rxeol; /* rx eol interrupts */ 61116743Ssam u_int32_t ast_txurn; /* tx underrun interrupts */ 62116743Ssam u_int32_t ast_mib; /* mib interrupts */ 63116743Ssam u_int32_t ast_intrcoal; /* interrupts coalesced */ 64116743Ssam u_int32_t ast_tx_packets; /* packet sent on the interface */ 65116743Ssam u_int32_t ast_tx_mgmt; /* management frames transmitted */ 66116743Ssam u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 67116743Ssam u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 68116743Ssam u_int32_t ast_tx_encap; /* tx encapsulation failed */ 69116743Ssam u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 70127779Ssam u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 71127779Ssam u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 72170530Ssam u_int32_t ast_tx_linear; /* tx linearized to cluster */ 73170530Ssam u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 74116743Ssam u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 75116743Ssam u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 76116743Ssam u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 77116743Ssam u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 78116743Ssam u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 79116743Ssam u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 80138570Ssam u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 81116743Ssam u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 82116743Ssam u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 83119147Ssam u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 84127779Ssam u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 85138570Ssam u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 86138570Ssam u_int32_t ast_tx_protect; /* tx frames with protection */ 87119147Ssam u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ 88138570Ssam u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ 89138570Ssam u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 90161187Ssam u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 91138570Ssam u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 92116743Ssam u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 93116743Ssam u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 94116743Ssam u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 95116743Ssam u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 96116743Ssam u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 97116743Ssam u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */ 98116743Ssam u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 99138570Ssam u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 100138570Ssam u_int32_t ast_rx_packets; /* packet recv on the interface */ 101138570Ssam u_int32_t ast_rx_mgt; /* management frames received */ 102138570Ssam u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 103159894Ssam int8_t ast_tx_rssi; /* tx rssi of last ack */ 104159894Ssam int8_t ast_rx_rssi; /* rx rssi from histogram */ 105160992Ssam u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */ 106170530Ssam u_int32_t ast_be_xmit; /* beacons transmitted */ 107170530Ssam u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 108170530Ssam u_int32_t ast_per_cal; /* periodic calibration calls */ 109170530Ssam u_int32_t ast_per_calfail;/* periodic calibration failed */ 110170530Ssam u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 111170530Ssam u_int32_t ast_rate_calls; /* rate control checks */ 112186904Ssam u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 113186904Ssam u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 114186904Ssam u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 115186904Ssam u_int32_t ast_ant_txswitch;/* tx antenna switches */ 116186904Ssam u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ 117186904Ssam u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ 118186904Ssam u_int32_t ast_cabq_xmit; /* cabq frames transmitted */ 119116743Ssam u_int32_t ast_cabq_busy; /* cabq found busy */ 120116743Ssam u_int32_t ast_tx_raw; /* tx frames through raw api */ 121116743Ssam u_int32_t ast_ff_txok; /* fast frames tx'd successfully */ 122116743Ssam u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */ 123123044Ssam u_int32_t ast_ff_rx; /* fast frames rx'd */ 124138570Ssam u_int32_t ast_ff_flush; /* fast frames flushed from staging q */ 125138570Ssam u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */ 126138570Ssam int8_t ast_rx_noise; /* rx noise floor */ 127138570Ssam u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */ 128138570Ssam u_int32_t ast_tdma_update;/* TDMA slot timing updates */ 129138570Ssam u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */ 130138570Ssam u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */ 131138570Ssam u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/ 132138570Ssam u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/ 133138570Ssam u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 134123044Ssam u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 135123044Ssam u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 136123044Ssam u_int32_t ast_be_missed; /* missed beacons */ 137123044Ssam u_int32_t ast_ani_cal; /* ANI calibrations performed */ 138119783Ssam u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */ 139119783Ssam u_int32_t ast_rx_halfgi; /* RX half-GI */ 140119783Ssam u_int32_t ast_rx_2040; /* RX 40mhz frame */ 141119783Ssam u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */ 142154140Ssam u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */ 143119783Ssam u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */ 144119783Ssam u_int32_t ast_rx_hi_rx_chain; 145123928Ssam u_int32_t ast_tx_htprotect; /* HT tx frames with protection */ 146154140Ssam u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */ 147154140Ssam u_int32_t ast_tx_timeout; /* Global TX timeout */ 148170530Ssam u_int32_t ast_tx_cst; /* Carrier sense timeout */ 149119783Ssam u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */ 150119783Ssam u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */ 151119783Ssam u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */ 152119783Ssam u_int32_t ast_tx_swretries; /* software TX retries */ 153154140Ssam u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */ 154154140Ssam u_int32_t ast_tx_data_underrun; 155119783Ssam u_int32_t ast_tx_delim_underrun; 156170530Ssam u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */ 157170530Ssam u_int32_t ast_tx_getnobuf; 158170530Ssam u_int32_t ast_tx_getbusybuf; 159170530Ssam u_int32_t ast_tx_intr; 160170530Ssam u_int32_t ast_rx_intr; 161119783Ssam u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */ 162170530Ssam u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */ 163170530Ssam u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */ 164170530Ssam u_int32_t ast_rx_keymiss; 165119783Ssam 166119783Ssam u_int32_t ast_pad[16]; 167154140Ssam}; 168119783Ssam 169119783Ssam#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 170123928Ssam#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq) 171123928Ssam#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq) 172170530Ssam 173119783Ssamstruct ath_diag { 174119783Ssam char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ 175119783Ssam u_int16_t ad_id; 176119783Ssam#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ 177154140Ssam#define ATH_DIAG_IN 0x4000 /* copy in parameters */ 178154140Ssam#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ 179119783Ssam#define ATH_DIAG_ID 0x0fff 180123928Ssam u_int16_t ad_in_size; /* pack to fit, yech */ 181123928Ssam caddr_t ad_in_data; 182170530Ssam caddr_t ad_out_data; 183170530Ssam u_int ad_out_size; 184170530Ssam 185170530Ssam}; 186170530Ssam#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) 187119783Ssam#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag) 188116743Ssam 189 190/* 191 * The rate control ioctl has to support multiple potential rate 192 * control classes. For now, instead of trying to support an 193 * abstraction for this in the API, let's just use a TLV 194 * representation for the payload and let userspace sort it out. 195 */ 196struct ath_rateioctl_tlv { 197 uint16_t tlv_id; 198 uint16_t tlv_len; /* length excluding TLV header */ 199}; 200 201/* 202 * This is purely the six byte MAC address. 203 */ 204#define ATH_RATE_TLV_MACADDR 0xaab0 205 206/* 207 * The rate control modules may decide to push a mapping table 208 * of rix -> net80211 ratecode as part of the update. 209 */ 210#define ATH_RATE_TLV_RATETABLE_NENTRIES 64 211struct ath_rateioctl_rt { 212 uint16_t nentries; 213 uint16_t pad[1]; 214 uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES]; 215}; 216#define ATH_RATE_TLV_RATETABLE 0xaab1 217 218/* 219 * This is the sample node statistics structure. 220 * More in ath_rate/sample/sample.h. 221 */ 222#define ATH_RATE_TLV_SAMPLENODE 0xaab2 223 224struct ath_rateioctl { 225 char if_name[IFNAMSIZ]; /* if name */ 226 union { 227 uint8_t macaddr[IEEE80211_ADDR_LEN]; 228 uint64_t pad; 229 } is_u; 230 uint32_t len; 231 caddr_t buf; 232}; 233#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl) 234 235/* 236 * Radio capture format. 237 */ 238#define ATH_RX_RADIOTAP_PRESENT_BASE ( \ 239 (1 << IEEE80211_RADIOTAP_TSFT) | \ 240 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 241 (1 << IEEE80211_RADIOTAP_RATE) | \ 242 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 243 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 244 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 245 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 246 0) 247 248#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 249#define ATH_RX_RADIOTAP_PRESENT \ 250 (ATH_RX_RADIOTAP_PRESENT_BASE | \ 251 (1 << IEEE80211_RADIOTAP_VENDOREXT) | \ 252 (1 << IEEE80211_RADIOTAP_EXT) | \ 253 0) 254#else 255#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE 256#endif /* ATH_ENABLE_RADIOTAP_PRESENT */ 257 258#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 259/* 260 * This is higher than the vendor bitmap used inside 261 * the Atheros reference codebase. 262 */ 263 264/* Bit 8 */ 265#define ATH_RADIOTAP_VENDOR_HEADER 8 266 267/* 268 * Using four chains makes all the fields in the 269 * per-chain info header be 4-byte aligned. 270 */ 271#define ATH_RADIOTAP_MAX_CHAINS 4 272 273/* 274 * The vendor radiotap header data needs to be: 275 * 276 * + Aligned to a 4 byte address 277 * + .. so all internal fields are 4 bytes aligned; 278 * + .. and no 64 bit fields are allowed. 279 * 280 * So padding is required to ensure this is the case. 281 * 282 * Note that because of the lack of alignment with the 283 * vendor header (6 bytes), the first field must be 284 * two bytes so it can be accessed by alignment-strict 285 * platform (eg MIPS.) 286 */ 287struct ath_radiotap_vendor_hdr { /* 30 bytes */ 288 uint8_t vh_version; /* 1 */ 289 uint8_t vh_rx_chainmask; /* 1 */ 290 291 /* At this point it should be 4 byte aligned */ 292 uint32_t evm[ATH_RADIOTAP_MAX_CHAINS]; /* 4 * 4 = 16 */ 293 294 uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 295 uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 296 297 uint8_t vh_phyerr_code; /* Phy error code, or 0xff */ 298 uint8_t vh_rs_status; /* RX status */ 299 uint8_t vh_rssi; /* Raw RSSI */ 300 uint8_t vh_pad1[1]; /* Pad to 4 byte boundary */ 301} __packed; 302#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 303 304struct ath_rx_radiotap_header { 305 struct ieee80211_radiotap_header wr_ihdr; 306 307#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 308 /* Vendor extension header bitmap */ 309 uint32_t wr_ext_bitmap; /* 4 */ 310 311 /* 312 * This padding is needed because: 313 * + the radiotap header is 8 bytes; 314 * + the extension bitmap is 4 bytes; 315 * + the tsf is 8 bytes, so it must start on an 8 byte 316 * boundary. 317 */ 318 uint32_t wr_pad1; 319#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 320 321 /* Normal radiotap fields */ 322 u_int64_t wr_tsf; 323 u_int8_t wr_flags; 324 u_int8_t wr_rate; 325 int8_t wr_antsignal; 326 int8_t wr_antnoise; 327 u_int8_t wr_antenna; 328 u_int8_t wr_pad[3]; 329 u_int32_t wr_chan_flags; 330 u_int16_t wr_chan_freq; 331 u_int8_t wr_chan_ieee; 332 int8_t wr_chan_maxpow; 333 334#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 335 /* 336 * Vendor header section, as required by the 337 * presence of the vendor extension bit and bitmap 338 * entry. 339 * 340 * XXX This must be aligned to a 4 byte address? 341 * XXX or 8 byte address? 342 */ 343 struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */ 344 345 /* 346 * Because of the lack of alignment enforced by the above 347 * header, this vendor section won't be aligned in any 348 * useful way. So, this will include a two-byte version 349 * value which will force the structure to be 4-byte aligned. 350 */ 351 struct ath_radiotap_vendor_hdr wr_v; 352#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 353} __packed; 354 355#define ATH_TX_RADIOTAP_PRESENT ( \ 356 (1 << IEEE80211_RADIOTAP_TSFT) | \ 357 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 358 (1 << IEEE80211_RADIOTAP_RATE) | \ 359 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 360 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 361 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 362 0) 363 364struct ath_tx_radiotap_header { 365 struct ieee80211_radiotap_header wt_ihdr; 366 u_int64_t wt_tsf; 367 u_int8_t wt_flags; 368 u_int8_t wt_rate; 369 u_int8_t wt_txpower; 370 u_int8_t wt_antenna; 371 u_int32_t wt_chan_flags; 372 u_int16_t wt_chan_freq; 373 u_int8_t wt_chan_ieee; 374 int8_t wt_chan_maxpow; 375} __packed; 376 377/* 378 * DFS ioctl commands 379 */ 380 381#define DFS_SET_THRESH 2 382#define DFS_GET_THRESH 3 383#define DFS_RADARDETECTS 6 384 385/* 386 * DFS ioctl parameter types 387 */ 388#define DFS_PARAM_FIRPWR 1 389#define DFS_PARAM_RRSSI 2 390#define DFS_PARAM_HEIGHT 3 391#define DFS_PARAM_PRSSI 4 392#define DFS_PARAM_INBAND 5 393#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */ 394#define DFS_PARAM_RELSTEP_EN 7 395#define DFS_PARAM_RELSTEP 8 396#define DFS_PARAM_RELPWR_EN 9 397#define DFS_PARAM_RELPWR 10 398#define DFS_PARAM_MAXLEN 11 399#define DFS_PARAM_USEFIR128 12 400#define DFS_PARAM_BLOCKRADAR 13 401#define DFS_PARAM_MAXRSSI_EN 14 402 403/* FreeBSD-specific start at 32 */ 404#define DFS_PARAM_ENABLE 32 405#define DFS_PARAM_EN_EXTCH 33 406 407#endif /* _DEV_ATH_ATHIOCTL_H */ 408