if_athioctl.h revision 238632
179455Sobrien/*- 279455Sobrien * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 379455Sobrien * All rights reserved. 479455Sobrien * 579455Sobrien * Redistribution and use in source and binary forms, with or without 679455Sobrien * modification, are permitted provided that the following conditions 779455Sobrien * are met: 879455Sobrien * 1. Redistributions of source code must retain the above copyright 979455Sobrien * notice, this list of conditions and the following disclaimer, 1079455Sobrien * without modification. 1179455Sobrien * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1279455Sobrien * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 1379455Sobrien * redistribution must be conditioned upon including a substantially 1479455Sobrien * similar Disclaimer requirement for further binary redistribution. 1579455Sobrien * 1679455Sobrien * NO WARRANTY 1779455Sobrien * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1879455Sobrien * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1979455Sobrien * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 2079455Sobrien * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 2179455Sobrien * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 2279455Sobrien * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2379455Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2479455Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 2579455Sobrien * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2679455Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 2779455Sobrien * THE POSSIBILITY OF SUCH DAMAGES. 2879455Sobrien * 2979455Sobrien * $FreeBSD: head/sys/dev/ath/if_athioctl.h 238632 2012-07-20 01:27:20Z adrian $ 3079455Sobrien */ 3179455Sobrien 3279455Sobrien/* 3379455Sobrien * Ioctl-related defintions for the Atheros Wireless LAN controller driver. 3479455Sobrien */ 3579455Sobrien#ifndef _DEV_ATH_ATHIOCTL_H 3679455Sobrien#define _DEV_ATH_ATHIOCTL_H 3779455Sobrien 3879455Sobrienstruct ath_tx_aggr_stats { 3979455Sobrien u_int32_t aggr_pkts[64]; 4079455Sobrien u_int32_t aggr_single_pkt; 4179455Sobrien u_int32_t aggr_nonbaw_pkt; 4279455Sobrien u_int32_t aggr_aggr_pkt; 43203872Skib u_int32_t aggr_baw_closed_single_pkt; 44203872Skib u_int32_t aggr_low_hwq_single_pkt; 4592839Simp u_int32_t aggr_sched_nopkt; 46203872Skib u_int32_t aggr_rts_aggr_limited; 4779455Sobrien}; 48125471Sbde 49125471Sbdestruct ath_intr_stats { 50125471Sbde u_int32_t sync_intr[32]; 51125471Sbde}; 52125471Sbde 53125471Sbdestruct ath_stats { 54125471Sbde u_int32_t ast_watchdog; /* device reset by watchdog */ 55125471Sbde u_int32_t ast_hardware; /* fatal hardware error interrupts */ 56125471Sbde u_int32_t ast_bmiss; /* beacon miss interrupts */ 57125471Sbde u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */ 58125471Sbde u_int32_t ast_bstuck; /* beacon stuck interrupts */ 59125471Sbde u_int32_t ast_rxorn; /* rx overrun interrupts */ 60125471Sbde u_int32_t ast_rxeol; /* rx eol interrupts */ 61125471Sbde u_int32_t ast_txurn; /* tx underrun interrupts */ 62125471Sbde u_int32_t ast_mib; /* mib interrupts */ 63125471Sbde u_int32_t ast_intrcoal; /* interrupts coalesced */ 64125471Sbde u_int32_t ast_tx_packets; /* packet sent on the interface */ 65125471Sbde u_int32_t ast_tx_mgmt; /* management frames transmitted */ 66125469Sbde u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 67125469Sbde u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 68125469Sbde u_int32_t ast_tx_encap; /* tx encapsulation failed */ 69125469Sbde u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 70125469Sbde u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 71125469Sbde u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 72125469Sbde u_int32_t ast_tx_linear; /* tx linearized to cluster */ 73125485Sbde u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 74125469Sbde u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 75125469Sbde u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 76125469Sbde u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 77125469Sbde u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 78125469Sbde u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 79125469Sbde u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 80125469Sbde u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 81125469Sbde u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 82125469Sbde u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 83125469Sbde u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 84125469Sbde u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 85125469Sbde u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 86125469Sbde u_int32_t ast_tx_protect; /* tx frames with protection */ 87125469Sbde u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ 88125469Sbde u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ 89125469Sbde u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 90125469Sbde u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 91125469Sbde u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 92125469Sbde u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 93125469Sbde u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 94125469Sbde u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 95125485Sbde u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 96125485Sbde u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 97125485Sbde u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */ 98125485Sbde u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 99125485Sbde u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 100125485Sbde u_int32_t ast_rx_packets; /* packet recv on the interface */ 101125485Sbde u_int32_t ast_rx_mgt; /* management frames received */ 102125485Sbde u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 103125485Sbde int8_t ast_tx_rssi; /* tx rssi of last ack */ 104125485Sbde int8_t ast_rx_rssi; /* rx rssi from histogram */ 105125485Sbde u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */ 106125485Sbde u_int32_t ast_be_xmit; /* beacons transmitted */ 107125485Sbde u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 108125485Sbde u_int32_t ast_per_cal; /* periodic calibration calls */ 109125485Sbde u_int32_t ast_per_calfail;/* periodic calibration failed */ 110125469Sbde u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 111125485Sbde u_int32_t ast_rate_calls; /* rate control checks */ 112125485Sbde u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 113125485Sbde u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 114125485Sbde u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 115125485Sbde u_int32_t ast_ant_txswitch;/* tx antenna switches */ 116125485Sbde u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ 117125485Sbde u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ 118125485Sbde u_int32_t ast_cabq_xmit; /* cabq frames transmitted */ 119125485Sbde u_int32_t ast_cabq_busy; /* cabq found busy */ 120125485Sbde u_int32_t ast_tx_raw; /* tx frames through raw api */ 121125485Sbde u_int32_t ast_ff_txok; /* fast frames tx'd successfully */ 122125469Sbde u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */ 123125469Sbde u_int32_t ast_ff_rx; /* fast frames rx'd */ 124125469Sbde u_int32_t ast_ff_flush; /* fast frames flushed from staging q */ 125125469Sbde u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */ 126125469Sbde int8_t ast_rx_noise; /* rx noise floor */ 12779455Sobrien u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */ 12879455Sobrien u_int32_t ast_tdma_update;/* TDMA slot timing updates */ 12979455Sobrien u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */ 13079455Sobrien u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */ 131203872Skib u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/ 13279455Sobrien u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/ 13379455Sobrien u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 13479455Sobrien u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 13579455Sobrien u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 13679455Sobrien u_int32_t ast_be_missed; /* missed beacons */ 13779455Sobrien u_int32_t ast_ani_cal; /* ANI calibrations performed */ 13879455Sobrien u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */ 13979455Sobrien u_int32_t ast_rx_halfgi; /* RX half-GI */ 14079455Sobrien u_int32_t ast_rx_2040; /* RX 40mhz frame */ 14179455Sobrien u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */ 14279455Sobrien u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */ 14379455Sobrien u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */ 14479455Sobrien u_int32_t ast_rx_hi_rx_chain; 14579455Sobrien u_int32_t ast_tx_htprotect; /* HT tx frames with protection */ 14679455Sobrien u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */ 14779455Sobrien u_int32_t ast_tx_timeout; /* Global TX timeout */ 14879455Sobrien u_int32_t ast_tx_cst; /* Carrier sense timeout */ 14979455Sobrien u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */ 15079455Sobrien u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */ 15179455Sobrien u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */ 15279455Sobrien u_int32_t ast_tx_swretries; /* software TX retries */ 15379455Sobrien u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */ 15479455Sobrien u_int32_t ast_tx_data_underrun; 15579455Sobrien u_int32_t ast_tx_delim_underrun; 15679455Sobrien u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */ 15779455Sobrien u_int32_t ast_tx_getnobuf; 15879455Sobrien u_int32_t ast_tx_getbusybuf; 15979455Sobrien u_int32_t ast_tx_intr; 16079455Sobrien u_int32_t ast_rx_intr; 16179455Sobrien u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */ 162203872Skib u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */ 16379455Sobrien u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */ 16479455Sobrien u_int32_t ast_rx_keymiss; 16579455Sobrien 16679455Sobrien u_int32_t ast_pad[16]; 16779455Sobrien}; 16879455Sobrien 16979455Sobrien#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 17079455Sobrien#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq) 17179455Sobrien#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq) 17279455Sobrien 17379455Sobrienstruct ath_diag { 17479455Sobrien char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ 17579455Sobrien u_int16_t ad_id; 17679455Sobrien#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ 17779455Sobrien#define ATH_DIAG_IN 0x4000 /* copy in parameters */ 17879455Sobrien#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ 17979455Sobrien#define ATH_DIAG_ID 0x0fff 180203872Skib u_int16_t ad_in_size; /* pack to fit, yech */ 18179455Sobrien caddr_t ad_in_data; 18279455Sobrien caddr_t ad_out_data; 18379455Sobrien u_int ad_out_size; 18479455Sobrien 18579455Sobrien}; 18679455Sobrien#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) 18779455Sobrien#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag) 18879455Sobrien 18979455Sobrien 19079455Sobrien/* 19179455Sobrien * The rate control ioctl has to support multiple potential rate 19279455Sobrien * control classes. For now, instead of trying to support an 19379455Sobrien * abstraction for this in the API, let's just use a TLV 19479455Sobrien * representation for the payload and let userspace sort it out. 19579455Sobrien */ 19679455Sobrienstruct ath_rateioctl_tlv { 197203872Skib uint16_t tlv_id; 19879455Sobrien uint16_t tlv_len; /* length excluding TLV header */ 19979455Sobrien}; 20079455Sobrien 20179455Sobrien/* 20279455Sobrien * This is purely the six byte MAC address. 203203872Skib */ 20479455Sobrien#define ATH_RATE_TLV_MACADDR 0xaab0 20579455Sobrien 20679455Sobrien/* 20779455Sobrien * This is the sample node statistics structure. 20879455Sobrien * More in ath_rate/sample/sample.h. 20979455Sobrien */ 210203872Skib#define ATH_RATE_TLV_SAMPLENODE 0xaab2 21179455Sobrien 21279455Sobrienstruct ath_rateioctl { 21379455Sobrien char if_name[IFNAMSIZ]; /* if name */ 21479455Sobrien union { 21579455Sobrien uint8_t macaddr[IEEE80211_ADDR_LEN]; 216203872Skib uint64_t pad; 21779455Sobrien } is_u; 21879455Sobrien uint32_t len; 21979455Sobrien caddr_t buf; 22079455Sobrien}; 22179455Sobrien#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl) 22279455Sobrien 22379455Sobrien/* 22479455Sobrien * Radio capture format. 22579455Sobrien */ 22679455Sobrien#define ATH_RX_RADIOTAP_PRESENT_BASE ( \ 22779455Sobrien (1 << IEEE80211_RADIOTAP_TSFT) | \ 22879455Sobrien (1 << IEEE80211_RADIOTAP_FLAGS) | \ 229102231Strhodes (1 << IEEE80211_RADIOTAP_RATE) | \ 23079455Sobrien (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 23179455Sobrien (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 23279455Sobrien (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 23379455Sobrien (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 23479455Sobrien 0) 23579455Sobrien 23679455Sobrien#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 23779455Sobrien#define ATH_RX_RADIOTAP_PRESENT \ 23879455Sobrien (ATH_RX_RADIOTAP_PRESENT_BASE | \ 23979455Sobrien (1 << IEEE80211_RADIOTAP_VENDOREXT) | \ 24079455Sobrien (1 << IEEE80211_RADIOTAP_EXT) | \ 24179455Sobrien 0) 24279455Sobrien#else 24379455Sobrien#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE 24479455Sobrien#endif /* ATH_ENABLE_RADIOTAP_PRESENT */ 24579455Sobrien 24679455Sobrien#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 24779455Sobrien/* 24879455Sobrien * This is higher than the vendor bitmap used inside 24979455Sobrien * the Atheros reference codebase. 25079455Sobrien */ 25179455Sobrien 25279455Sobrien/* Bit 8 */ 25379455Sobrien#define ATH_RADIOTAP_VENDOR_HEADER 8 25479455Sobrien 25579455Sobrien/* 25679455Sobrien * Using four chains makes all the fields in the 25779455Sobrien * per-chain info header be 4-byte aligned. 25879455Sobrien */ 25979455Sobrien#define ATH_RADIOTAP_MAX_CHAINS 4 26079455Sobrien 26179455Sobrien/* 26279455Sobrien * The vendor radiotap header data needs to be: 26379455Sobrien * 26479455Sobrien * + Aligned to a 4 byte address 26579455Sobrien * + .. so all internal fields are 4 bytes aligned; 26679455Sobrien * + .. and no 64 bit fields are allowed. 26779455Sobrien * 26879455Sobrien * So padding is required to ensure this is the case. 26979455Sobrien * 27079455Sobrien * Note that because of the lack of alignment with the 27179455Sobrien * vendor header (6 bytes), the first field must be 27279455Sobrien * two bytes so it can be accessed by alignment-strict 27379455Sobrien * platform (eg MIPS.) 27479455Sobrien */ 27579455Sobrienstruct ath_radiotap_vendor_hdr { /* 30 bytes */ 27679455Sobrien uint8_t vh_version; /* 1 */ 27779455Sobrien uint8_t vh_rx_chainmask; /* 1 */ 27879455Sobrien 27979455Sobrien /* At this point it should be 4 byte aligned */ 28079455Sobrien uint32_t evm[ATH_RADIOTAP_MAX_CHAINS]; /* 4 * 4 = 16 */ 28179455Sobrien 28279455Sobrien uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 28379455Sobrien uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 28479455Sobrien 28579455Sobrien uint8_t vh_phyerr_code; /* Phy error code, or 0xff */ 28679455Sobrien uint8_t vh_rs_status; /* RX status */ 28779455Sobrien uint8_t vh_rssi; /* Raw RSSI */ 28879455Sobrien uint8_t vh_pad1[1]; /* Pad to 4 byte boundary */ 28979455Sobrien} __packed; 29079455Sobrien#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 29179455Sobrien 29279455Sobrienstruct ath_rx_radiotap_header { 29379455Sobrien struct ieee80211_radiotap_header wr_ihdr; 29479455Sobrien 29579455Sobrien#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 29679455Sobrien /* Vendor extension header bitmap */ 29779455Sobrien uint32_t wr_ext_bitmap; /* 4 */ 29879455Sobrien 29979455Sobrien /* 30079455Sobrien * This padding is needed because: 30179455Sobrien * + the radiotap header is 8 bytes; 30279455Sobrien * + the extension bitmap is 4 bytes; 30379455Sobrien * + the tsf is 8 bytes, so it must start on an 8 byte 30479455Sobrien * boundary. 30579455Sobrien */ 30679455Sobrien uint32_t wr_pad1; 30779455Sobrien#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 30879455Sobrien 309203872Skib /* Normal radiotap fields */ 310203872Skib u_int64_t wr_tsf; 311203872Skib u_int8_t wr_flags; 312203872Skib u_int8_t wr_rate; 313203872Skib int8_t wr_antsignal; 31479455Sobrien int8_t wr_antnoise; 31579455Sobrien u_int8_t wr_antenna; 31679455Sobrien u_int8_t wr_pad[3]; 31779455Sobrien u_int32_t wr_chan_flags; 31879455Sobrien u_int16_t wr_chan_freq; 31979455Sobrien u_int8_t wr_chan_ieee; 32079455Sobrien int8_t wr_chan_maxpow; 32192839Simp 32279455Sobrien#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 32379455Sobrien /* 32479455Sobrien * Vendor header section, as required by the 32579455Sobrien * presence of the vendor extension bit and bitmap 32679455Sobrien * entry. 32779455Sobrien * 32879455Sobrien * XXX This must be aligned to a 4 byte address? 32979455Sobrien * XXX or 8 byte address? 33079455Sobrien */ 33179455Sobrien struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */ 33279455Sobrien 333203872Skib /* 33479455Sobrien * Because of the lack of alignment enforced by the above 33579455Sobrien * header, this vendor section won't be aligned in any 33679455Sobrien * useful way. So, this will include a two-byte version 33779455Sobrien * value which will force the structure to be 4-byte aligned. 33879455Sobrien */ 33979455Sobrien struct ath_radiotap_vendor_hdr wr_v; 340175853Syar#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 34179455Sobrien} __packed; 342175853Syar 34379455Sobrien#define ATH_TX_RADIOTAP_PRESENT ( \ 34479455Sobrien (1 << IEEE80211_RADIOTAP_TSFT) | \ 34579455Sobrien (1 << IEEE80211_RADIOTAP_FLAGS) | \ 34679455Sobrien (1 << IEEE80211_RADIOTAP_RATE) | \ 34779455Sobrien (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 348203872Skib (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 34979455Sobrien (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 350175854Syar 0) 35179455Sobrien 35279455Sobrienstruct ath_tx_radiotap_header { 35379455Sobrien struct ieee80211_radiotap_header wt_ihdr; 354203872Skib u_int64_t wt_tsf; 35579455Sobrien u_int8_t wt_flags; 35679455Sobrien u_int8_t wt_rate; 35779455Sobrien u_int8_t wt_txpower; 35879455Sobrien u_int8_t wt_antenna; 35979455Sobrien u_int32_t wt_chan_flags; 36079455Sobrien u_int16_t wt_chan_freq; 36179455Sobrien u_int8_t wt_chan_ieee; 362203872Skib int8_t wt_chan_maxpow; 36379455Sobrien} __packed; 36479455Sobrien 36579455Sobrien/* 36679455Sobrien * DFS ioctl commands 36779455Sobrien */ 36879455Sobrien 36979455Sobrien#define DFS_SET_THRESH 2 37079455Sobrien#define DFS_GET_THRESH 3 37179455Sobrien#define DFS_RADARDETECTS 6 37279455Sobrien 373203872Skib/* 37479455Sobrien * DFS ioctl parameter types 37579455Sobrien */ 37679455Sobrien#define DFS_PARAM_FIRPWR 1 37779455Sobrien#define DFS_PARAM_RRSSI 2 37879455Sobrien#define DFS_PARAM_HEIGHT 3 37979455Sobrien#define DFS_PARAM_PRSSI 4 38079455Sobrien#define DFS_PARAM_INBAND 5 38179455Sobrien#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */ 38279455Sobrien#define DFS_PARAM_RELSTEP_EN 7 38379455Sobrien#define DFS_PARAM_RELSTEP 8 38479455Sobrien#define DFS_PARAM_RELPWR_EN 9 385203872Skib#define DFS_PARAM_RELPWR 10 38679455Sobrien#define DFS_PARAM_MAXLEN 11 38779455Sobrien#define DFS_PARAM_USEFIR128 12 38879455Sobrien#define DFS_PARAM_BLOCKRADAR 13 38979455Sobrien#define DFS_PARAM_MAXRSSI_EN 14 39079455Sobrien 391203872Skib/* FreeBSD-specific start at 32 */ 39279455Sobrien#define DFS_PARAM_ENABLE 32 39379455Sobrien#define DFS_PARAM_EN_EXTCH 33 39479455Sobrien 39579455Sobrien#endif /* _DEV_ATH_ATHIOCTL_H */ 39679455Sobrien